267019bb2b156815f269a9ae4429ceec6d4e2d7a
[linux-2.6.git] / drivers / net / sfc / falcon.c
1 /****************************************************************************
2  * Driver for Solarflare Solarstorm network controllers and boards
3  * Copyright 2005-2006 Fen Systems Ltd.
4  * Copyright 2006-2009 Solarflare Communications Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License version 2 as published
8  * by the Free Software Foundation, incorporated herein by reference.
9  */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/mii.h>
18 #include <linux/slab.h>
19 #include "net_driver.h"
20 #include "bitfield.h"
21 #include "efx.h"
22 #include "mac.h"
23 #include "spi.h"
24 #include "nic.h"
25 #include "regs.h"
26 #include "io.h"
27 #include "mdio_10g.h"
28 #include "phy.h"
29 #include "workarounds.h"
30
31 /* Hardware control for SFC4000 (aka Falcon). */
32
33 static const unsigned int
34 /* "Large" EEPROM device: Atmel AT25640 or similar
35  * 8 KB, 16-bit address, 32 B write block */
36 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
37                      | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
38                      | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
39 /* Default flash device: Atmel AT25F1024
40  * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
41 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
42                       | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
43                       | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
44                       | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
45                       | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
46
47 /**************************************************************************
48  *
49  * I2C bus - this is a bit-bashing interface using GPIO pins
50  * Note that it uses the output enables to tristate the outputs
51  * SDA is the data pin and SCL is the clock
52  *
53  **************************************************************************
54  */
55 static void falcon_setsda(void *data, int state)
56 {
57         struct efx_nic *efx = (struct efx_nic *)data;
58         efx_oword_t reg;
59
60         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
61         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
62         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
63 }
64
65 static void falcon_setscl(void *data, int state)
66 {
67         struct efx_nic *efx = (struct efx_nic *)data;
68         efx_oword_t reg;
69
70         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
71         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
72         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
73 }
74
75 static int falcon_getsda(void *data)
76 {
77         struct efx_nic *efx = (struct efx_nic *)data;
78         efx_oword_t reg;
79
80         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
81         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
82 }
83
84 static int falcon_getscl(void *data)
85 {
86         struct efx_nic *efx = (struct efx_nic *)data;
87         efx_oword_t reg;
88
89         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
90         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
91 }
92
93 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
94         .setsda         = falcon_setsda,
95         .setscl         = falcon_setscl,
96         .getsda         = falcon_getsda,
97         .getscl         = falcon_getscl,
98         .udelay         = 5,
99         /* Wait up to 50 ms for slave to let us pull SCL high */
100         .timeout        = DIV_ROUND_UP(HZ, 20),
101 };
102
103 static void falcon_push_irq_moderation(struct efx_channel *channel)
104 {
105         efx_dword_t timer_cmd;
106         struct efx_nic *efx = channel->efx;
107
108         /* Set timer register */
109         if (channel->irq_moderation) {
110                 EFX_POPULATE_DWORD_2(timer_cmd,
111                                      FRF_AB_TC_TIMER_MODE,
112                                      FFE_BB_TIMER_MODE_INT_HLDOFF,
113                                      FRF_AB_TC_TIMER_VAL,
114                                      channel->irq_moderation - 1);
115         } else {
116                 EFX_POPULATE_DWORD_2(timer_cmd,
117                                      FRF_AB_TC_TIMER_MODE,
118                                      FFE_BB_TIMER_MODE_DIS,
119                                      FRF_AB_TC_TIMER_VAL, 0);
120         }
121         BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
122         efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
123                                channel->channel);
124 }
125
126 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx);
127
128 static void falcon_prepare_flush(struct efx_nic *efx)
129 {
130         falcon_deconfigure_mac_wrapper(efx);
131
132         /* Wait for the tx and rx fifo's to get to the next packet boundary
133          * (~1ms without back-pressure), then to drain the remainder of the
134          * fifo's at data path speeds (negligible), with a healthy margin. */
135         msleep(10);
136 }
137
138 /* Acknowledge a legacy interrupt from Falcon
139  *
140  * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
141  *
142  * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
143  * BIU. Interrupt acknowledge is read sensitive so must write instead
144  * (then read to ensure the BIU collector is flushed)
145  *
146  * NB most hardware supports MSI interrupts
147  */
148 inline void falcon_irq_ack_a1(struct efx_nic *efx)
149 {
150         efx_dword_t reg;
151
152         EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
153         efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
154         efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
155 }
156
157
158 irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
159 {
160         struct efx_nic *efx = dev_id;
161         efx_oword_t *int_ker = efx->irq_status.addr;
162         int syserr;
163         int queues;
164
165         /* Check to see if this is our interrupt.  If it isn't, we
166          * exit without having touched the hardware.
167          */
168         if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
169                 netif_vdbg(efx, intr, efx->net_dev,
170                            "IRQ %d on CPU %d not for me\n", irq,
171                            raw_smp_processor_id());
172                 return IRQ_NONE;
173         }
174         efx->last_irq_cpu = raw_smp_processor_id();
175         netif_vdbg(efx, intr, efx->net_dev,
176                    "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
177                    irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
178
179         /* Determine interrupting queues, clear interrupt status
180          * register and acknowledge the device interrupt.
181          */
182         BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS);
183         queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q);
184
185         /* Check to see if we have a serious error condition */
186         if (queues & (1U << efx->fatal_irq_level)) {
187                 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
188                 if (unlikely(syserr))
189                         return efx_nic_fatal_interrupt(efx);
190         }
191
192         EFX_ZERO_OWORD(*int_ker);
193         wmb(); /* Ensure the vector is cleared before interrupt ack */
194         falcon_irq_ack_a1(efx);
195
196         if (queues & 1)
197                 efx_schedule_channel(efx_get_channel(efx, 0));
198         if (queues & 2)
199                 efx_schedule_channel(efx_get_channel(efx, 1));
200         return IRQ_HANDLED;
201 }
202 /**************************************************************************
203  *
204  * EEPROM/flash
205  *
206  **************************************************************************
207  */
208
209 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
210
211 static int falcon_spi_poll(struct efx_nic *efx)
212 {
213         efx_oword_t reg;
214         efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
215         return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
216 }
217
218 /* Wait for SPI command completion */
219 static int falcon_spi_wait(struct efx_nic *efx)
220 {
221         /* Most commands will finish quickly, so we start polling at
222          * very short intervals.  Sometimes the command may have to
223          * wait for VPD or expansion ROM access outside of our
224          * control, so we allow up to 100 ms. */
225         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
226         int i;
227
228         for (i = 0; i < 10; i++) {
229                 if (!falcon_spi_poll(efx))
230                         return 0;
231                 udelay(10);
232         }
233
234         for (;;) {
235                 if (!falcon_spi_poll(efx))
236                         return 0;
237                 if (time_after_eq(jiffies, timeout)) {
238                         netif_err(efx, hw, efx->net_dev,
239                                   "timed out waiting for SPI\n");
240                         return -ETIMEDOUT;
241                 }
242                 schedule_timeout_uninterruptible(1);
243         }
244 }
245
246 int falcon_spi_cmd(struct efx_nic *efx, const struct efx_spi_device *spi,
247                    unsigned int command, int address,
248                    const void *in, void *out, size_t len)
249 {
250         bool addressed = (address >= 0);
251         bool reading = (out != NULL);
252         efx_oword_t reg;
253         int rc;
254
255         /* Input validation */
256         if (len > FALCON_SPI_MAX_LEN)
257                 return -EINVAL;
258         BUG_ON(!mutex_is_locked(&efx->spi_lock));
259
260         /* Check that previous command is not still running */
261         rc = falcon_spi_poll(efx);
262         if (rc)
263                 return rc;
264
265         /* Program address register, if we have an address */
266         if (addressed) {
267                 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
268                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
269         }
270
271         /* Program data register, if we have data */
272         if (in != NULL) {
273                 memcpy(&reg, in, len);
274                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
275         }
276
277         /* Issue read/write command */
278         EFX_POPULATE_OWORD_7(reg,
279                              FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
280                              FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
281                              FRF_AB_EE_SPI_HCMD_DABCNT, len,
282                              FRF_AB_EE_SPI_HCMD_READ, reading,
283                              FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
284                              FRF_AB_EE_SPI_HCMD_ADBCNT,
285                              (addressed ? spi->addr_len : 0),
286                              FRF_AB_EE_SPI_HCMD_ENC, command);
287         efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
288
289         /* Wait for read/write to complete */
290         rc = falcon_spi_wait(efx);
291         if (rc)
292                 return rc;
293
294         /* Read data */
295         if (out != NULL) {
296                 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
297                 memcpy(out, &reg, len);
298         }
299
300         return 0;
301 }
302
303 static size_t
304 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
305 {
306         return min(FALCON_SPI_MAX_LEN,
307                    (spi->block_size - (start & (spi->block_size - 1))));
308 }
309
310 static inline u8
311 efx_spi_munge_command(const struct efx_spi_device *spi,
312                       const u8 command, const unsigned int address)
313 {
314         return command | (((address >> 8) & spi->munge_address) << 3);
315 }
316
317 /* Wait up to 10 ms for buffered write completion */
318 int
319 falcon_spi_wait_write(struct efx_nic *efx, const struct efx_spi_device *spi)
320 {
321         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
322         u8 status;
323         int rc;
324
325         for (;;) {
326                 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
327                                     &status, sizeof(status));
328                 if (rc)
329                         return rc;
330                 if (!(status & SPI_STATUS_NRDY))
331                         return 0;
332                 if (time_after_eq(jiffies, timeout)) {
333                         netif_err(efx, hw, efx->net_dev,
334                                   "SPI write timeout on device %d"
335                                   " last status=0x%02x\n",
336                                   spi->device_id, status);
337                         return -ETIMEDOUT;
338                 }
339                 schedule_timeout_uninterruptible(1);
340         }
341 }
342
343 int falcon_spi_read(struct efx_nic *efx, const struct efx_spi_device *spi,
344                     loff_t start, size_t len, size_t *retlen, u8 *buffer)
345 {
346         size_t block_len, pos = 0;
347         unsigned int command;
348         int rc = 0;
349
350         while (pos < len) {
351                 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
352
353                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
354                 rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL,
355                                     buffer + pos, block_len);
356                 if (rc)
357                         break;
358                 pos += block_len;
359
360                 /* Avoid locking up the system */
361                 cond_resched();
362                 if (signal_pending(current)) {
363                         rc = -EINTR;
364                         break;
365                 }
366         }
367
368         if (retlen)
369                 *retlen = pos;
370         return rc;
371 }
372
373 int
374 falcon_spi_write(struct efx_nic *efx, const struct efx_spi_device *spi,
375                  loff_t start, size_t len, size_t *retlen, const u8 *buffer)
376 {
377         u8 verify_buffer[FALCON_SPI_MAX_LEN];
378         size_t block_len, pos = 0;
379         unsigned int command;
380         int rc = 0;
381
382         while (pos < len) {
383                 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
384                 if (rc)
385                         break;
386
387                 block_len = min(len - pos,
388                                 falcon_spi_write_limit(spi, start + pos));
389                 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
390                 rc = falcon_spi_cmd(efx, spi, command, start + pos,
391                                     buffer + pos, NULL, block_len);
392                 if (rc)
393                         break;
394
395                 rc = falcon_spi_wait_write(efx, spi);
396                 if (rc)
397                         break;
398
399                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
400                 rc = falcon_spi_cmd(efx, spi, command, start + pos,
401                                     NULL, verify_buffer, block_len);
402                 if (memcmp(verify_buffer, buffer + pos, block_len)) {
403                         rc = -EIO;
404                         break;
405                 }
406
407                 pos += block_len;
408
409                 /* Avoid locking up the system */
410                 cond_resched();
411                 if (signal_pending(current)) {
412                         rc = -EINTR;
413                         break;
414                 }
415         }
416
417         if (retlen)
418                 *retlen = pos;
419         return rc;
420 }
421
422 /**************************************************************************
423  *
424  * MAC wrapper
425  *
426  **************************************************************************
427  */
428
429 static void falcon_push_multicast_hash(struct efx_nic *efx)
430 {
431         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
432
433         WARN_ON(!mutex_is_locked(&efx->mac_lock));
434
435         efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
436         efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
437 }
438
439 static void falcon_reset_macs(struct efx_nic *efx)
440 {
441         struct falcon_nic_data *nic_data = efx->nic_data;
442         efx_oword_t reg, mac_ctrl;
443         int count;
444
445         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
446                 /* It's not safe to use GLB_CTL_REG to reset the
447                  * macs, so instead use the internal MAC resets
448                  */
449                 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
450                 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
451
452                 for (count = 0; count < 10000; count++) {
453                         efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
454                         if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
455                             0)
456                                 return;
457                         udelay(10);
458                 }
459
460                 netif_err(efx, hw, efx->net_dev,
461                           "timed out waiting for XMAC core reset\n");
462         }
463
464         /* Mac stats will fail whist the TX fifo is draining */
465         WARN_ON(nic_data->stats_disable_count == 0);
466
467         efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);
468         EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);
469         efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
470
471         efx_reado(efx, &reg, FR_AB_GLB_CTL);
472         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
473         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
474         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
475         efx_writeo(efx, &reg, FR_AB_GLB_CTL);
476
477         count = 0;
478         while (1) {
479                 efx_reado(efx, &reg, FR_AB_GLB_CTL);
480                 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
481                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
482                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
483                         netif_dbg(efx, hw, efx->net_dev,
484                                   "Completed MAC reset after %d loops\n",
485                                   count);
486                         break;
487                 }
488                 if (count > 20) {
489                         netif_err(efx, hw, efx->net_dev, "MAC reset failed\n");
490                         break;
491                 }
492                 count++;
493                 udelay(10);
494         }
495
496         /* Ensure the correct MAC is selected before statistics
497          * are re-enabled by the caller */
498         efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
499
500         falcon_setup_xaui(efx);
501 }
502
503 void falcon_drain_tx_fifo(struct efx_nic *efx)
504 {
505         efx_oword_t reg;
506
507         if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
508             (efx->loopback_mode != LOOPBACK_NONE))
509                 return;
510
511         efx_reado(efx, &reg, FR_AB_MAC_CTRL);
512         /* There is no point in draining more than once */
513         if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
514                 return;
515
516         falcon_reset_macs(efx);
517 }
518
519 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
520 {
521         efx_oword_t reg;
522
523         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
524                 return;
525
526         /* Isolate the MAC -> RX */
527         efx_reado(efx, &reg, FR_AZ_RX_CFG);
528         EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
529         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
530
531         /* Isolate TX -> MAC */
532         falcon_drain_tx_fifo(efx);
533 }
534
535 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
536 {
537         struct efx_link_state *link_state = &efx->link_state;
538         efx_oword_t reg;
539         int link_speed, isolate;
540
541         isolate = (efx->reset_pending != RESET_TYPE_NONE);
542
543         switch (link_state->speed) {
544         case 10000: link_speed = 3; break;
545         case 1000:  link_speed = 2; break;
546         case 100:   link_speed = 1; break;
547         default:    link_speed = 0; break;
548         }
549         /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
550          * as advertised.  Disable to ensure packets are not
551          * indefinitely held and TX queue can be flushed at any point
552          * while the link is down. */
553         EFX_POPULATE_OWORD_5(reg,
554                              FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
555                              FRF_AB_MAC_BCAD_ACPT, 1,
556                              FRF_AB_MAC_UC_PROM, efx->promiscuous,
557                              FRF_AB_MAC_LINK_STATUS, 1, /* always set */
558                              FRF_AB_MAC_SPEED, link_speed);
559         /* On B0, MAC backpressure can be disabled and packets get
560          * discarded. */
561         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
562                 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
563                                     !link_state->up || isolate);
564         }
565
566         efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
567
568         /* Restore the multicast hash registers. */
569         falcon_push_multicast_hash(efx);
570
571         efx_reado(efx, &reg, FR_AZ_RX_CFG);
572         /* Enable XOFF signal from RX FIFO (we enabled it during NIC
573          * initialisation but it may read back as 0) */
574         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
575         /* Unisolate the MAC -> RX */
576         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
577                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate);
578         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
579 }
580
581 static void falcon_stats_request(struct efx_nic *efx)
582 {
583         struct falcon_nic_data *nic_data = efx->nic_data;
584         efx_oword_t reg;
585
586         WARN_ON(nic_data->stats_pending);
587         WARN_ON(nic_data->stats_disable_count);
588
589         if (nic_data->stats_dma_done == NULL)
590                 return; /* no mac selected */
591
592         *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE;
593         nic_data->stats_pending = true;
594         wmb(); /* ensure done flag is clear */
595
596         /* Initiate DMA transfer of stats */
597         EFX_POPULATE_OWORD_2(reg,
598                              FRF_AB_MAC_STAT_DMA_CMD, 1,
599                              FRF_AB_MAC_STAT_DMA_ADR,
600                              efx->stats_buffer.dma_addr);
601         efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
602
603         mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2));
604 }
605
606 static void falcon_stats_complete(struct efx_nic *efx)
607 {
608         struct falcon_nic_data *nic_data = efx->nic_data;
609
610         if (!nic_data->stats_pending)
611                 return;
612
613         nic_data->stats_pending = 0;
614         if (*nic_data->stats_dma_done == FALCON_STATS_DONE) {
615                 rmb(); /* read the done flag before the stats */
616                 efx->mac_op->update_stats(efx);
617         } else {
618                 netif_err(efx, hw, efx->net_dev,
619                           "timed out waiting for statistics\n");
620         }
621 }
622
623 static void falcon_stats_timer_func(unsigned long context)
624 {
625         struct efx_nic *efx = (struct efx_nic *)context;
626         struct falcon_nic_data *nic_data = efx->nic_data;
627
628         spin_lock(&efx->stats_lock);
629
630         falcon_stats_complete(efx);
631         if (nic_data->stats_disable_count == 0)
632                 falcon_stats_request(efx);
633
634         spin_unlock(&efx->stats_lock);
635 }
636
637 static bool falcon_loopback_link_poll(struct efx_nic *efx)
638 {
639         struct efx_link_state old_state = efx->link_state;
640
641         WARN_ON(!mutex_is_locked(&efx->mac_lock));
642         WARN_ON(!LOOPBACK_INTERNAL(efx));
643
644         efx->link_state.fd = true;
645         efx->link_state.fc = efx->wanted_fc;
646         efx->link_state.up = true;
647         efx->link_state.speed = 10000;
648
649         return !efx_link_state_equal(&efx->link_state, &old_state);
650 }
651
652 static int falcon_reconfigure_port(struct efx_nic *efx)
653 {
654         int rc;
655
656         WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0);
657
658         /* Poll the PHY link state *before* reconfiguring it. This means we
659          * will pick up the correct speed (in loopback) to select the correct
660          * MAC.
661          */
662         if (LOOPBACK_INTERNAL(efx))
663                 falcon_loopback_link_poll(efx);
664         else
665                 efx->phy_op->poll(efx);
666
667         falcon_stop_nic_stats(efx);
668         falcon_deconfigure_mac_wrapper(efx);
669
670         falcon_reset_macs(efx);
671
672         efx->phy_op->reconfigure(efx);
673         rc = efx->mac_op->reconfigure(efx);
674         BUG_ON(rc);
675
676         falcon_start_nic_stats(efx);
677
678         /* Synchronise efx->link_state with the kernel */
679         efx_link_status_changed(efx);
680
681         return 0;
682 }
683
684 /**************************************************************************
685  *
686  * PHY access via GMII
687  *
688  **************************************************************************
689  */
690
691 /* Wait for GMII access to complete */
692 static int falcon_gmii_wait(struct efx_nic *efx)
693 {
694         efx_oword_t md_stat;
695         int count;
696
697         /* wait upto 50ms - taken max from datasheet */
698         for (count = 0; count < 5000; count++) {
699                 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
700                 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
701                         if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
702                             EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
703                                 netif_err(efx, hw, efx->net_dev,
704                                           "error from GMII access "
705                                           EFX_OWORD_FMT"\n",
706                                           EFX_OWORD_VAL(md_stat));
707                                 return -EIO;
708                         }
709                         return 0;
710                 }
711                 udelay(10);
712         }
713         netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n");
714         return -ETIMEDOUT;
715 }
716
717 /* Write an MDIO register of a PHY connected to Falcon. */
718 static int falcon_mdio_write(struct net_device *net_dev,
719                              int prtad, int devad, u16 addr, u16 value)
720 {
721         struct efx_nic *efx = netdev_priv(net_dev);
722         efx_oword_t reg;
723         int rc;
724
725         netif_vdbg(efx, hw, efx->net_dev,
726                    "writing MDIO %d register %d.%d with 0x%04x\n",
727                     prtad, devad, addr, value);
728
729         mutex_lock(&efx->mdio_lock);
730
731         /* Check MDIO not currently being accessed */
732         rc = falcon_gmii_wait(efx);
733         if (rc)
734                 goto out;
735
736         /* Write the address/ID register */
737         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
738         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
739
740         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
741                              FRF_AB_MD_DEV_ADR, devad);
742         efx_writeo(efx, &reg, FR_AB_MD_ID);
743
744         /* Write data */
745         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
746         efx_writeo(efx, &reg, FR_AB_MD_TXD);
747
748         EFX_POPULATE_OWORD_2(reg,
749                              FRF_AB_MD_WRC, 1,
750                              FRF_AB_MD_GC, 0);
751         efx_writeo(efx, &reg, FR_AB_MD_CS);
752
753         /* Wait for data to be written */
754         rc = falcon_gmii_wait(efx);
755         if (rc) {
756                 /* Abort the write operation */
757                 EFX_POPULATE_OWORD_2(reg,
758                                      FRF_AB_MD_WRC, 0,
759                                      FRF_AB_MD_GC, 1);
760                 efx_writeo(efx, &reg, FR_AB_MD_CS);
761                 udelay(10);
762         }
763
764 out:
765         mutex_unlock(&efx->mdio_lock);
766         return rc;
767 }
768
769 /* Read an MDIO register of a PHY connected to Falcon. */
770 static int falcon_mdio_read(struct net_device *net_dev,
771                             int prtad, int devad, u16 addr)
772 {
773         struct efx_nic *efx = netdev_priv(net_dev);
774         efx_oword_t reg;
775         int rc;
776
777         mutex_lock(&efx->mdio_lock);
778
779         /* Check MDIO not currently being accessed */
780         rc = falcon_gmii_wait(efx);
781         if (rc)
782                 goto out;
783
784         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
785         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
786
787         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
788                              FRF_AB_MD_DEV_ADR, devad);
789         efx_writeo(efx, &reg, FR_AB_MD_ID);
790
791         /* Request data to be read */
792         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
793         efx_writeo(efx, &reg, FR_AB_MD_CS);
794
795         /* Wait for data to become available */
796         rc = falcon_gmii_wait(efx);
797         if (rc == 0) {
798                 efx_reado(efx, &reg, FR_AB_MD_RXD);
799                 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
800                 netif_vdbg(efx, hw, efx->net_dev,
801                            "read from MDIO %d register %d.%d, got %04x\n",
802                            prtad, devad, addr, rc);
803         } else {
804                 /* Abort the read operation */
805                 EFX_POPULATE_OWORD_2(reg,
806                                      FRF_AB_MD_RIC, 0,
807                                      FRF_AB_MD_GC, 1);
808                 efx_writeo(efx, &reg, FR_AB_MD_CS);
809
810                 netif_dbg(efx, hw, efx->net_dev,
811                           "read from MDIO %d register %d.%d, got error %d\n",
812                           prtad, devad, addr, rc);
813         }
814
815 out:
816         mutex_unlock(&efx->mdio_lock);
817         return rc;
818 }
819
820 /* This call is responsible for hooking in the MAC and PHY operations */
821 static int falcon_probe_port(struct efx_nic *efx)
822 {
823         struct falcon_nic_data *nic_data = efx->nic_data;
824         int rc;
825
826         switch (efx->phy_type) {
827         case PHY_TYPE_SFX7101:
828                 efx->phy_op = &falcon_sfx7101_phy_ops;
829                 break;
830         case PHY_TYPE_QT2022C2:
831         case PHY_TYPE_QT2025C:
832                 efx->phy_op = &falcon_qt202x_phy_ops;
833                 break;
834         case PHY_TYPE_TXC43128:
835                 efx->phy_op = &falcon_txc_phy_ops;
836                 break;
837         default:
838                 netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n",
839                           efx->phy_type);
840                 return -ENODEV;
841         }
842
843         /* Fill out MDIO structure and loopback modes */
844         efx->mdio.mdio_read = falcon_mdio_read;
845         efx->mdio.mdio_write = falcon_mdio_write;
846         rc = efx->phy_op->probe(efx);
847         if (rc != 0)
848                 return rc;
849
850         /* Initial assumption */
851         efx->link_state.speed = 10000;
852         efx->link_state.fd = true;
853
854         /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
855         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
856                 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
857         else
858                 efx->wanted_fc = EFX_FC_RX;
859         if (efx->mdio.mmds & MDIO_DEVS_AN)
860                 efx->wanted_fc |= EFX_FC_AUTO;
861
862         /* Allocate buffer for stats */
863         rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
864                                   FALCON_MAC_STATS_SIZE);
865         if (rc)
866                 return rc;
867         netif_dbg(efx, probe, efx->net_dev,
868                   "stats buffer at %llx (virt %p phys %llx)\n",
869                   (u64)efx->stats_buffer.dma_addr,
870                   efx->stats_buffer.addr,
871                   (u64)virt_to_phys(efx->stats_buffer.addr));
872         nic_data->stats_dma_done = efx->stats_buffer.addr + XgDmaDone_offset;
873
874         return 0;
875 }
876
877 static void falcon_remove_port(struct efx_nic *efx)
878 {
879         efx->phy_op->remove(efx);
880         efx_nic_free_buffer(efx, &efx->stats_buffer);
881 }
882
883 /**************************************************************************
884  *
885  * Falcon test code
886  *
887  **************************************************************************/
888
889 static int
890 falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
891 {
892         struct falcon_nvconfig *nvconfig;
893         struct efx_spi_device *spi;
894         void *region;
895         int rc, magic_num, struct_ver;
896         __le16 *word, *limit;
897         u32 csum;
898
899         spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
900         if (!spi)
901                 return -EINVAL;
902
903         region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
904         if (!region)
905                 return -ENOMEM;
906         nvconfig = region + FALCON_NVCONFIG_OFFSET;
907
908         mutex_lock(&efx->spi_lock);
909         rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region);
910         mutex_unlock(&efx->spi_lock);
911         if (rc) {
912                 netif_err(efx, hw, efx->net_dev, "Failed to read %s\n",
913                           efx->spi_flash ? "flash" : "EEPROM");
914                 rc = -EIO;
915                 goto out;
916         }
917
918         magic_num = le16_to_cpu(nvconfig->board_magic_num);
919         struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
920
921         rc = -EINVAL;
922         if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
923                 netif_err(efx, hw, efx->net_dev,
924                           "NVRAM bad magic 0x%x\n", magic_num);
925                 goto out;
926         }
927         if (struct_ver < 2) {
928                 netif_err(efx, hw, efx->net_dev,
929                           "NVRAM has ancient version 0x%x\n", struct_ver);
930                 goto out;
931         } else if (struct_ver < 4) {
932                 word = &nvconfig->board_magic_num;
933                 limit = (__le16 *) (nvconfig + 1);
934         } else {
935                 word = region;
936                 limit = region + FALCON_NVCONFIG_END;
937         }
938         for (csum = 0; word < limit; ++word)
939                 csum += le16_to_cpu(*word);
940
941         if (~csum & 0xffff) {
942                 netif_err(efx, hw, efx->net_dev,
943                           "NVRAM has incorrect checksum\n");
944                 goto out;
945         }
946
947         rc = 0;
948         if (nvconfig_out)
949                 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
950
951  out:
952         kfree(region);
953         return rc;
954 }
955
956 static int falcon_test_nvram(struct efx_nic *efx)
957 {
958         return falcon_read_nvram(efx, NULL);
959 }
960
961 static const struct efx_nic_register_test falcon_b0_register_tests[] = {
962         { FR_AZ_ADR_REGION,
963           EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
964         { FR_AZ_RX_CFG,
965           EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
966         { FR_AZ_TX_CFG,
967           EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
968         { FR_AZ_TX_RESERVED,
969           EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
970         { FR_AB_MAC_CTRL,
971           EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
972         { FR_AZ_SRM_TX_DC_CFG,
973           EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
974         { FR_AZ_RX_DC_CFG,
975           EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
976         { FR_AZ_RX_DC_PF_WM,
977           EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
978         { FR_BZ_DP_CTRL,
979           EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
980         { FR_AB_GM_CFG2,
981           EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
982         { FR_AB_GMF_CFG0,
983           EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
984         { FR_AB_XM_GLB_CFG,
985           EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
986         { FR_AB_XM_TX_CFG,
987           EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
988         { FR_AB_XM_RX_CFG,
989           EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
990         { FR_AB_XM_RX_PARAM,
991           EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
992         { FR_AB_XM_FC,
993           EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
994         { FR_AB_XM_ADR_LO,
995           EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
996         { FR_AB_XX_SD_CTL,
997           EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
998 };
999
1000 static int falcon_b0_test_registers(struct efx_nic *efx)
1001 {
1002         return efx_nic_test_registers(efx, falcon_b0_register_tests,
1003                                       ARRAY_SIZE(falcon_b0_register_tests));
1004 }
1005
1006 /**************************************************************************
1007  *
1008  * Device reset
1009  *
1010  **************************************************************************
1011  */
1012
1013 /* Resets NIC to known state.  This routine must be called in process
1014  * context and is allowed to sleep. */
1015 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
1016 {
1017         struct falcon_nic_data *nic_data = efx->nic_data;
1018         efx_oword_t glb_ctl_reg_ker;
1019         int rc;
1020
1021         netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n",
1022                   RESET_TYPE(method));
1023
1024         /* Initiate device reset */
1025         if (method == RESET_TYPE_WORLD) {
1026                 rc = pci_save_state(efx->pci_dev);
1027                 if (rc) {
1028                         netif_err(efx, drv, efx->net_dev,
1029                                   "failed to backup PCI state of primary "
1030                                   "function prior to hardware reset\n");
1031                         goto fail1;
1032                 }
1033                 if (efx_nic_is_dual_func(efx)) {
1034                         rc = pci_save_state(nic_data->pci_dev2);
1035                         if (rc) {
1036                                 netif_err(efx, drv, efx->net_dev,
1037                                           "failed to backup PCI state of "
1038                                           "secondary function prior to "
1039                                           "hardware reset\n");
1040                                 goto fail2;
1041                         }
1042                 }
1043
1044                 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
1045                                      FRF_AB_EXT_PHY_RST_DUR,
1046                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
1047                                      FRF_AB_SWRST, 1);
1048         } else {
1049                 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
1050                                      /* exclude PHY from "invisible" reset */
1051                                      FRF_AB_EXT_PHY_RST_CTL,
1052                                      method == RESET_TYPE_INVISIBLE,
1053                                      /* exclude EEPROM/flash and PCIe */
1054                                      FRF_AB_PCIE_CORE_RST_CTL, 1,
1055                                      FRF_AB_PCIE_NSTKY_RST_CTL, 1,
1056                                      FRF_AB_PCIE_SD_RST_CTL, 1,
1057                                      FRF_AB_EE_RST_CTL, 1,
1058                                      FRF_AB_EXT_PHY_RST_DUR,
1059                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
1060                                      FRF_AB_SWRST, 1);
1061         }
1062         efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1063
1064         netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n");
1065         schedule_timeout_uninterruptible(HZ / 20);
1066
1067         /* Restore PCI configuration if needed */
1068         if (method == RESET_TYPE_WORLD) {
1069                 if (efx_nic_is_dual_func(efx)) {
1070                         rc = pci_restore_state(nic_data->pci_dev2);
1071                         if (rc) {
1072                                 netif_err(efx, drv, efx->net_dev,
1073                                           "failed to restore PCI config for "
1074                                           "the secondary function\n");
1075                                 goto fail3;
1076                         }
1077                 }
1078                 rc = pci_restore_state(efx->pci_dev);
1079                 if (rc) {
1080                         netif_err(efx, drv, efx->net_dev,
1081                                   "failed to restore PCI config for the "
1082                                   "primary function\n");
1083                         goto fail4;
1084                 }
1085                 netif_dbg(efx, drv, efx->net_dev,
1086                           "successfully restored PCI config\n");
1087         }
1088
1089         /* Assert that reset complete */
1090         efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1091         if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
1092                 rc = -ETIMEDOUT;
1093                 netif_err(efx, hw, efx->net_dev,
1094                           "timed out waiting for hardware reset\n");
1095                 goto fail5;
1096         }
1097         netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n");
1098
1099         return 0;
1100
1101         /* pci_save_state() and pci_restore_state() MUST be called in pairs */
1102 fail2:
1103 fail3:
1104         pci_restore_state(efx->pci_dev);
1105 fail1:
1106 fail4:
1107 fail5:
1108         return rc;
1109 }
1110
1111 static void falcon_monitor(struct efx_nic *efx)
1112 {
1113         bool link_changed;
1114         int rc;
1115
1116         BUG_ON(!mutex_is_locked(&efx->mac_lock));
1117
1118         rc = falcon_board(efx)->type->monitor(efx);
1119         if (rc) {
1120                 netif_err(efx, hw, efx->net_dev,
1121                           "Board sensor %s; shutting down PHY\n",
1122                           (rc == -ERANGE) ? "reported fault" : "failed");
1123                 efx->phy_mode |= PHY_MODE_LOW_POWER;
1124                 rc = __efx_reconfigure_port(efx);
1125                 WARN_ON(rc);
1126         }
1127
1128         if (LOOPBACK_INTERNAL(efx))
1129                 link_changed = falcon_loopback_link_poll(efx);
1130         else
1131                 link_changed = efx->phy_op->poll(efx);
1132
1133         if (link_changed) {
1134                 falcon_stop_nic_stats(efx);
1135                 falcon_deconfigure_mac_wrapper(efx);
1136
1137                 falcon_reset_macs(efx);
1138                 rc = efx->mac_op->reconfigure(efx);
1139                 BUG_ON(rc);
1140
1141                 falcon_start_nic_stats(efx);
1142
1143                 efx_link_status_changed(efx);
1144         }
1145
1146         falcon_poll_xmac(efx);
1147 }
1148
1149 /* Zeroes out the SRAM contents.  This routine must be called in
1150  * process context and is allowed to sleep.
1151  */
1152 static int falcon_reset_sram(struct efx_nic *efx)
1153 {
1154         efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
1155         int count;
1156
1157         /* Set the SRAM wake/sleep GPIO appropriately. */
1158         efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1159         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
1160         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
1161         efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1162
1163         /* Initiate SRAM reset */
1164         EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
1165                              FRF_AZ_SRM_INIT_EN, 1,
1166                              FRF_AZ_SRM_NB_SZ, 0);
1167         efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1168
1169         /* Wait for SRAM reset to complete */
1170         count = 0;
1171         do {
1172                 netif_dbg(efx, hw, efx->net_dev,
1173                           "waiting for SRAM reset (attempt %d)...\n", count);
1174
1175                 /* SRAM reset is slow; expect around 16ms */
1176                 schedule_timeout_uninterruptible(HZ / 50);
1177
1178                 /* Check for reset complete */
1179                 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1180                 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
1181                         netif_dbg(efx, hw, efx->net_dev,
1182                                   "SRAM reset complete\n");
1183
1184                         return 0;
1185                 }
1186         } while (++count < 20); /* wait upto 0.4 sec */
1187
1188         netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n");
1189         return -ETIMEDOUT;
1190 }
1191
1192 static int falcon_spi_device_init(struct efx_nic *efx,
1193                                   struct efx_spi_device **spi_device_ret,
1194                                   unsigned int device_id, u32 device_type)
1195 {
1196         struct efx_spi_device *spi_device;
1197
1198         if (device_type != 0) {
1199                 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
1200                 if (!spi_device)
1201                         return -ENOMEM;
1202                 spi_device->device_id = device_id;
1203                 spi_device->size =
1204                         1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
1205                 spi_device->addr_len =
1206                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
1207                 spi_device->munge_address = (spi_device->size == 1 << 9 &&
1208                                              spi_device->addr_len == 1);
1209                 spi_device->erase_command =
1210                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
1211                 spi_device->erase_size =
1212                         1 << SPI_DEV_TYPE_FIELD(device_type,
1213                                                 SPI_DEV_TYPE_ERASE_SIZE);
1214                 spi_device->block_size =
1215                         1 << SPI_DEV_TYPE_FIELD(device_type,
1216                                                 SPI_DEV_TYPE_BLOCK_SIZE);
1217         } else {
1218                 spi_device = NULL;
1219         }
1220
1221         kfree(*spi_device_ret);
1222         *spi_device_ret = spi_device;
1223         return 0;
1224 }
1225
1226 static void falcon_remove_spi_devices(struct efx_nic *efx)
1227 {
1228         kfree(efx->spi_eeprom);
1229         efx->spi_eeprom = NULL;
1230         kfree(efx->spi_flash);
1231         efx->spi_flash = NULL;
1232 }
1233
1234 /* Extract non-volatile configuration */
1235 static int falcon_probe_nvconfig(struct efx_nic *efx)
1236 {
1237         struct falcon_nvconfig *nvconfig;
1238         int board_rev;
1239         int rc;
1240
1241         nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
1242         if (!nvconfig)
1243                 return -ENOMEM;
1244
1245         rc = falcon_read_nvram(efx, nvconfig);
1246         if (rc == -EINVAL) {
1247                 netif_err(efx, probe, efx->net_dev,
1248                           "NVRAM is invalid therefore using defaults\n");
1249                 efx->phy_type = PHY_TYPE_NONE;
1250                 efx->mdio.prtad = MDIO_PRTAD_NONE;
1251                 board_rev = 0;
1252                 rc = 0;
1253         } else if (rc) {
1254                 goto fail1;
1255         } else {
1256                 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
1257                 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
1258
1259                 efx->phy_type = v2->port0_phy_type;
1260                 efx->mdio.prtad = v2->port0_phy_addr;
1261                 board_rev = le16_to_cpu(v2->board_revision);
1262
1263                 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
1264                         rc = falcon_spi_device_init(
1265                                 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
1266                                 le32_to_cpu(v3->spi_device_type
1267                                             [FFE_AB_SPI_DEVICE_FLASH]));
1268                         if (rc)
1269                                 goto fail2;
1270                         rc = falcon_spi_device_init(
1271                                 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
1272                                 le32_to_cpu(v3->spi_device_type
1273                                             [FFE_AB_SPI_DEVICE_EEPROM]));
1274                         if (rc)
1275                                 goto fail2;
1276                 }
1277         }
1278
1279         /* Read the MAC addresses */
1280         memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
1281
1282         netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n",
1283                   efx->phy_type, efx->mdio.prtad);
1284
1285         rc = falcon_probe_board(efx, board_rev);
1286         if (rc)
1287                 goto fail2;
1288
1289         kfree(nvconfig);
1290         return 0;
1291
1292  fail2:
1293         falcon_remove_spi_devices(efx);
1294  fail1:
1295         kfree(nvconfig);
1296         return rc;
1297 }
1298
1299 /* Probe all SPI devices on the NIC */
1300 static void falcon_probe_spi_devices(struct efx_nic *efx)
1301 {
1302         efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
1303         int boot_dev;
1304
1305         efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
1306         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1307         efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1308
1309         if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
1310                 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
1311                             FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
1312                 netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n",
1313                           boot_dev == FFE_AB_SPI_DEVICE_FLASH ?
1314                           "flash" : "EEPROM");
1315         } else {
1316                 /* Disable VPD and set clock dividers to safe
1317                  * values for initial programming. */
1318                 boot_dev = -1;
1319                 netif_dbg(efx, probe, efx->net_dev,
1320                           "Booted from internal ASIC settings;"
1321                           " setting SPI config\n");
1322                 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
1323                                      /* 125 MHz / 7 ~= 20 MHz */
1324                                      FRF_AB_EE_SF_CLOCK_DIV, 7,
1325                                      /* 125 MHz / 63 ~= 2 MHz */
1326                                      FRF_AB_EE_EE_CLOCK_DIV, 63);
1327                 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1328         }
1329
1330         if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
1331                 falcon_spi_device_init(efx, &efx->spi_flash,
1332                                        FFE_AB_SPI_DEVICE_FLASH,
1333                                        default_flash_type);
1334         if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
1335                 falcon_spi_device_init(efx, &efx->spi_eeprom,
1336                                        FFE_AB_SPI_DEVICE_EEPROM,
1337                                        large_eeprom_type);
1338 }
1339
1340 static int falcon_probe_nic(struct efx_nic *efx)
1341 {
1342         struct falcon_nic_data *nic_data;
1343         struct falcon_board *board;
1344         int rc;
1345
1346         /* Allocate storage for hardware specific data */
1347         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
1348         if (!nic_data)
1349                 return -ENOMEM;
1350         efx->nic_data = nic_data;
1351
1352         rc = -ENODEV;
1353
1354         if (efx_nic_fpga_ver(efx) != 0) {
1355                 netif_err(efx, probe, efx->net_dev,
1356                           "Falcon FPGA not supported\n");
1357                 goto fail1;
1358         }
1359
1360         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1361                 efx_oword_t nic_stat;
1362                 struct pci_dev *dev;
1363                 u8 pci_rev = efx->pci_dev->revision;
1364
1365                 if ((pci_rev == 0xff) || (pci_rev == 0)) {
1366                         netif_err(efx, probe, efx->net_dev,
1367                                   "Falcon rev A0 not supported\n");
1368                         goto fail1;
1369                 }
1370                 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1371                 if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) {
1372                         netif_err(efx, probe, efx->net_dev,
1373                                   "Falcon rev A1 1G not supported\n");
1374                         goto fail1;
1375                 }
1376                 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
1377                         netif_err(efx, probe, efx->net_dev,
1378                                   "Falcon rev A1 PCI-X not supported\n");
1379                         goto fail1;
1380                 }
1381
1382                 dev = pci_dev_get(efx->pci_dev);
1383                 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
1384                                              dev))) {
1385                         if (dev->bus == efx->pci_dev->bus &&
1386                             dev->devfn == efx->pci_dev->devfn + 1) {
1387                                 nic_data->pci_dev2 = dev;
1388                                 break;
1389                         }
1390                 }
1391                 if (!nic_data->pci_dev2) {
1392                         netif_err(efx, probe, efx->net_dev,
1393                                   "failed to find secondary function\n");
1394                         rc = -ENODEV;
1395                         goto fail2;
1396                 }
1397         }
1398
1399         /* Now we can reset the NIC */
1400         rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
1401         if (rc) {
1402                 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
1403                 goto fail3;
1404         }
1405
1406         /* Allocate memory for INT_KER */
1407         rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
1408         if (rc)
1409                 goto fail4;
1410         BUG_ON(efx->irq_status.dma_addr & 0x0f);
1411
1412         netif_dbg(efx, probe, efx->net_dev,
1413                   "INT_KER at %llx (virt %p phys %llx)\n",
1414                   (u64)efx->irq_status.dma_addr,
1415                   efx->irq_status.addr,
1416                   (u64)virt_to_phys(efx->irq_status.addr));
1417
1418         falcon_probe_spi_devices(efx);
1419
1420         /* Read in the non-volatile configuration */
1421         rc = falcon_probe_nvconfig(efx);
1422         if (rc)
1423                 goto fail5;
1424
1425         /* Initialise I2C adapter */
1426         board = falcon_board(efx);
1427         board->i2c_adap.owner = THIS_MODULE;
1428         board->i2c_data = falcon_i2c_bit_operations;
1429         board->i2c_data.data = efx;
1430         board->i2c_adap.algo_data = &board->i2c_data;
1431         board->i2c_adap.dev.parent = &efx->pci_dev->dev;
1432         strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
1433                 sizeof(board->i2c_adap.name));
1434         rc = i2c_bit_add_bus(&board->i2c_adap);
1435         if (rc)
1436                 goto fail5;
1437
1438         rc = falcon_board(efx)->type->init(efx);
1439         if (rc) {
1440                 netif_err(efx, probe, efx->net_dev,
1441                           "failed to initialise board\n");
1442                 goto fail6;
1443         }
1444
1445         nic_data->stats_disable_count = 1;
1446         setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func,
1447                     (unsigned long)efx);
1448
1449         return 0;
1450
1451  fail6:
1452         BUG_ON(i2c_del_adapter(&board->i2c_adap));
1453         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1454  fail5:
1455         falcon_remove_spi_devices(efx);
1456         efx_nic_free_buffer(efx, &efx->irq_status);
1457  fail4:
1458  fail3:
1459         if (nic_data->pci_dev2) {
1460                 pci_dev_put(nic_data->pci_dev2);
1461                 nic_data->pci_dev2 = NULL;
1462         }
1463  fail2:
1464  fail1:
1465         kfree(efx->nic_data);
1466         return rc;
1467 }
1468
1469 static void falcon_init_rx_cfg(struct efx_nic *efx)
1470 {
1471         /* Prior to Siena the RX DMA engine will split each frame at
1472          * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
1473          * be so large that that never happens. */
1474         const unsigned huge_buf_size = (3 * 4096) >> 5;
1475         /* RX control FIFO thresholds (32 entries) */
1476         const unsigned ctrl_xon_thr = 20;
1477         const unsigned ctrl_xoff_thr = 25;
1478         /* RX data FIFO thresholds (256-byte units; size varies) */
1479         int data_xon_thr = efx_nic_rx_xon_thresh >> 8;
1480         int data_xoff_thr = efx_nic_rx_xoff_thresh >> 8;
1481         efx_oword_t reg;
1482
1483         efx_reado(efx, &reg, FR_AZ_RX_CFG);
1484         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1485                 /* Data FIFO size is 5.5K */
1486                 if (data_xon_thr < 0)
1487                         data_xon_thr = 512 >> 8;
1488                 if (data_xoff_thr < 0)
1489                         data_xoff_thr = 2048 >> 8;
1490                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
1491                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
1492                                     huge_buf_size);
1493                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
1494                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
1495                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
1496                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
1497         } else {
1498                 /* Data FIFO size is 80K; register fields moved */
1499                 if (data_xon_thr < 0)
1500                         data_xon_thr = 27648 >> 8; /* ~3*max MTU */
1501                 if (data_xoff_thr < 0)
1502                         data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
1503                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
1504                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
1505                                     huge_buf_size);
1506                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
1507                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
1508                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
1509                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
1510                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
1511
1512                 /* Enable hash insertion. This is broken for the
1513                  * 'Falcon' hash so also select Toeplitz TCP/IPv4 and
1514                  * IPv4 hashes. */
1515                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1);
1516                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1);
1517                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1);
1518         }
1519         /* Always enable XOFF signal from RX FIFO.  We enable
1520          * or disable transmission of pause frames at the MAC. */
1521         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
1522         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1523 }
1524
1525 /* This call performs hardware-specific global initialisation, such as
1526  * defining the descriptor cache sizes and number of RSS channels.
1527  * It does not set up any buffers, descriptor rings or event queues.
1528  */
1529 static int falcon_init_nic(struct efx_nic *efx)
1530 {
1531         efx_oword_t temp;
1532         int rc;
1533
1534         /* Use on-chip SRAM */
1535         efx_reado(efx, &temp, FR_AB_NIC_STAT);
1536         EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
1537         efx_writeo(efx, &temp, FR_AB_NIC_STAT);
1538
1539         rc = falcon_reset_sram(efx);
1540         if (rc)
1541                 return rc;
1542
1543         /* Clear the parity enables on the TX data fifos as
1544          * they produce false parity errors because of timing issues
1545          */
1546         if (EFX_WORKAROUND_5129(efx)) {
1547                 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
1548                 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
1549                 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
1550         }
1551
1552         if (EFX_WORKAROUND_7244(efx)) {
1553                 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
1554                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
1555                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
1556                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
1557                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
1558                 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
1559         }
1560
1561         /* XXX This is documented only for Falcon A0/A1 */
1562         /* Setup RX.  Wait for descriptor is broken and must
1563          * be disabled.  RXDP recovery shouldn't be needed, but is.
1564          */
1565         efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
1566         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
1567         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
1568         if (EFX_WORKAROUND_5583(efx))
1569                 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
1570         efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
1571
1572         /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
1573          * descriptors (which is bad).
1574          */
1575         efx_reado(efx, &temp, FR_AZ_TX_CFG);
1576         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
1577         efx_writeo(efx, &temp, FR_AZ_TX_CFG);
1578
1579         falcon_init_rx_cfg(efx);
1580
1581         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1582                 /* Set hash key for IPv4 */
1583                 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
1584                 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
1585
1586                 /* Set destination of both TX and RX Flush events */
1587                 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
1588                 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
1589         }
1590
1591         efx_nic_init_common(efx);
1592
1593         return 0;
1594 }
1595
1596 static void falcon_remove_nic(struct efx_nic *efx)
1597 {
1598         struct falcon_nic_data *nic_data = efx->nic_data;
1599         struct falcon_board *board = falcon_board(efx);
1600         int rc;
1601
1602         board->type->fini(efx);
1603
1604         /* Remove I2C adapter and clear it in preparation for a retry */
1605         rc = i2c_del_adapter(&board->i2c_adap);
1606         BUG_ON(rc);
1607         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1608
1609         falcon_remove_spi_devices(efx);
1610         efx_nic_free_buffer(efx, &efx->irq_status);
1611
1612         falcon_reset_hw(efx, RESET_TYPE_ALL);
1613
1614         /* Release the second function after the reset */
1615         if (nic_data->pci_dev2) {
1616                 pci_dev_put(nic_data->pci_dev2);
1617                 nic_data->pci_dev2 = NULL;
1618         }
1619
1620         /* Tear down the private nic state */
1621         kfree(efx->nic_data);
1622         efx->nic_data = NULL;
1623 }
1624
1625 static void falcon_update_nic_stats(struct efx_nic *efx)
1626 {
1627         struct falcon_nic_data *nic_data = efx->nic_data;
1628         efx_oword_t cnt;
1629
1630         if (nic_data->stats_disable_count)
1631                 return;
1632
1633         efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
1634         efx->n_rx_nodesc_drop_cnt +=
1635                 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
1636
1637         if (nic_data->stats_pending &&
1638             *nic_data->stats_dma_done == FALCON_STATS_DONE) {
1639                 nic_data->stats_pending = false;
1640                 rmb(); /* read the done flag before the stats */
1641                 efx->mac_op->update_stats(efx);
1642         }
1643 }
1644
1645 void falcon_start_nic_stats(struct efx_nic *efx)
1646 {
1647         struct falcon_nic_data *nic_data = efx->nic_data;
1648
1649         spin_lock_bh(&efx->stats_lock);
1650         if (--nic_data->stats_disable_count == 0)
1651                 falcon_stats_request(efx);
1652         spin_unlock_bh(&efx->stats_lock);
1653 }
1654
1655 void falcon_stop_nic_stats(struct efx_nic *efx)
1656 {
1657         struct falcon_nic_data *nic_data = efx->nic_data;
1658         int i;
1659
1660         might_sleep();
1661
1662         spin_lock_bh(&efx->stats_lock);
1663         ++nic_data->stats_disable_count;
1664         spin_unlock_bh(&efx->stats_lock);
1665
1666         del_timer_sync(&nic_data->stats_timer);
1667
1668         /* Wait enough time for the most recent transfer to
1669          * complete. */
1670         for (i = 0; i < 4 && nic_data->stats_pending; i++) {
1671                 if (*nic_data->stats_dma_done == FALCON_STATS_DONE)
1672                         break;
1673                 msleep(1);
1674         }
1675
1676         spin_lock_bh(&efx->stats_lock);
1677         falcon_stats_complete(efx);
1678         spin_unlock_bh(&efx->stats_lock);
1679 }
1680
1681 static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
1682 {
1683         falcon_board(efx)->type->set_id_led(efx, mode);
1684 }
1685
1686 /**************************************************************************
1687  *
1688  * Wake on LAN
1689  *
1690  **************************************************************************
1691  */
1692
1693 static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1694 {
1695         wol->supported = 0;
1696         wol->wolopts = 0;
1697         memset(&wol->sopass, 0, sizeof(wol->sopass));
1698 }
1699
1700 static int falcon_set_wol(struct efx_nic *efx, u32 type)
1701 {
1702         if (type != 0)
1703                 return -EINVAL;
1704         return 0;
1705 }
1706
1707 /**************************************************************************
1708  *
1709  * Revision-dependent attributes used by efx.c and nic.c
1710  *
1711  **************************************************************************
1712  */
1713
1714 struct efx_nic_type falcon_a1_nic_type = {
1715         .probe = falcon_probe_nic,
1716         .remove = falcon_remove_nic,
1717         .init = falcon_init_nic,
1718         .fini = efx_port_dummy_op_void,
1719         .monitor = falcon_monitor,
1720         .reset = falcon_reset_hw,
1721         .probe_port = falcon_probe_port,
1722         .remove_port = falcon_remove_port,
1723         .prepare_flush = falcon_prepare_flush,
1724         .update_stats = falcon_update_nic_stats,
1725         .start_stats = falcon_start_nic_stats,
1726         .stop_stats = falcon_stop_nic_stats,
1727         .set_id_led = falcon_set_id_led,
1728         .push_irq_moderation = falcon_push_irq_moderation,
1729         .push_multicast_hash = falcon_push_multicast_hash,
1730         .reconfigure_port = falcon_reconfigure_port,
1731         .get_wol = falcon_get_wol,
1732         .set_wol = falcon_set_wol,
1733         .resume_wol = efx_port_dummy_op_void,
1734         .test_nvram = falcon_test_nvram,
1735         .default_mac_ops = &falcon_xmac_operations,
1736
1737         .revision = EFX_REV_FALCON_A1,
1738         .mem_map_size = 0x20000,
1739         .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
1740         .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
1741         .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
1742         .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
1743         .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
1744         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1745         .rx_buffer_padding = 0x24,
1746         .max_interrupt_mode = EFX_INT_MODE_MSI,
1747         .phys_addr_channels = 4,
1748         .tx_dc_base = 0x130000,
1749         .rx_dc_base = 0x100000,
1750         .offload_features = NETIF_F_IP_CSUM,
1751         .reset_world_flags = ETH_RESET_IRQ,
1752 };
1753
1754 struct efx_nic_type falcon_b0_nic_type = {
1755         .probe = falcon_probe_nic,
1756         .remove = falcon_remove_nic,
1757         .init = falcon_init_nic,
1758         .fini = efx_port_dummy_op_void,
1759         .monitor = falcon_monitor,
1760         .reset = falcon_reset_hw,
1761         .probe_port = falcon_probe_port,
1762         .remove_port = falcon_remove_port,
1763         .prepare_flush = falcon_prepare_flush,
1764         .update_stats = falcon_update_nic_stats,
1765         .start_stats = falcon_start_nic_stats,
1766         .stop_stats = falcon_stop_nic_stats,
1767         .set_id_led = falcon_set_id_led,
1768         .push_irq_moderation = falcon_push_irq_moderation,
1769         .push_multicast_hash = falcon_push_multicast_hash,
1770         .reconfigure_port = falcon_reconfigure_port,
1771         .get_wol = falcon_get_wol,
1772         .set_wol = falcon_set_wol,
1773         .resume_wol = efx_port_dummy_op_void,
1774         .test_registers = falcon_b0_test_registers,
1775         .test_nvram = falcon_test_nvram,
1776         .default_mac_ops = &falcon_xmac_operations,
1777
1778         .revision = EFX_REV_FALCON_B0,
1779         /* Map everything up to and including the RSS indirection
1780          * table.  Don't map MSI-X table, MSI-X PBA since Linux
1781          * requires that they not be mapped.  */
1782         .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
1783                          FR_BZ_RX_INDIRECTION_TBL_STEP *
1784                          FR_BZ_RX_INDIRECTION_TBL_ROWS),
1785         .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1786         .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1787         .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1788         .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1789         .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1790         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1791         .rx_buffer_hash_size = 0x10,
1792         .rx_buffer_padding = 0,
1793         .max_interrupt_mode = EFX_INT_MODE_MSIX,
1794         .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
1795                                    * interrupt handler only supports 32
1796                                    * channels */
1797         .tx_dc_base = 0x130000,
1798         .rx_dc_base = 0x100000,
1799         .offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH | NETIF_F_NTUPLE,
1800         .reset_world_flags = ETH_RESET_IRQ,
1801 };
1802