phy: Change mii_bus id field to a string
[linux-2.6.git] / drivers / net / sb1250-mac.c
1 /*
2  * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation
3  * Copyright (c) 2006, 2007  Maciej W. Rozycki
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License
7  * as published by the Free Software Foundation; either version 2
8  * of the License, or (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
18  *
19  *
20  * This driver is designed for the Broadcom SiByte SOC built-in
21  * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp.
22  *
23  * Updated to the driver model and the PHY abstraction layer
24  * by Maciej W. Rozycki.
25  */
26
27 #include <linux/bug.h>
28 #include <linux/module.h>
29 #include <linux/kernel.h>
30 #include <linux/string.h>
31 #include <linux/timer.h>
32 #include <linux/errno.h>
33 #include <linux/ioport.h>
34 #include <linux/slab.h>
35 #include <linux/interrupt.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/skbuff.h>
39 #include <linux/init.h>
40 #include <linux/bitops.h>
41 #include <linux/err.h>
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/phy.h>
45 #include <linux/platform_device.h>
46
47 #include <asm/cache.h>
48 #include <asm/io.h>
49 #include <asm/processor.h>      /* Processor type for cache alignment. */
50
51 /* This is only here until the firmware is ready.  In that case,
52    the firmware leaves the ethernet address in the register for us. */
53 #ifdef CONFIG_SIBYTE_STANDALONE
54 #define SBMAC_ETH0_HWADDR "40:00:00:00:01:00"
55 #define SBMAC_ETH1_HWADDR "40:00:00:00:01:01"
56 #define SBMAC_ETH2_HWADDR "40:00:00:00:01:02"
57 #define SBMAC_ETH3_HWADDR "40:00:00:00:01:03"
58 #endif
59
60
61 /* These identify the driver base version and may not be removed. */
62 #if 0
63 static char version1[] __initdata =
64 "sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n";
65 #endif
66
67
68 /* Operational parameters that usually are not changed. */
69
70 #define CONFIG_SBMAC_COALESCE
71
72 /* Time in jiffies before concluding the transmitter is hung. */
73 #define TX_TIMEOUT  (2*HZ)
74
75
76 MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
77 MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
78
79 /* A few user-configurable values which may be modified when a driver
80    module is loaded. */
81
82 /* 1 normal messages, 0 quiet .. 7 verbose. */
83 static int debug = 1;
84 module_param(debug, int, S_IRUGO);
85 MODULE_PARM_DESC(debug, "Debug messages");
86
87 #ifdef CONFIG_SBMAC_COALESCE
88 static int int_pktcnt_tx = 255;
89 module_param(int_pktcnt_tx, int, S_IRUGO);
90 MODULE_PARM_DESC(int_pktcnt_tx, "TX packet count");
91
92 static int int_timeout_tx = 255;
93 module_param(int_timeout_tx, int, S_IRUGO);
94 MODULE_PARM_DESC(int_timeout_tx, "TX timeout value");
95
96 static int int_pktcnt_rx = 64;
97 module_param(int_pktcnt_rx, int, S_IRUGO);
98 MODULE_PARM_DESC(int_pktcnt_rx, "RX packet count");
99
100 static int int_timeout_rx = 64;
101 module_param(int_timeout_rx, int, S_IRUGO);
102 MODULE_PARM_DESC(int_timeout_rx, "RX timeout value");
103 #endif
104
105 #include <asm/sibyte/board.h>
106 #include <asm/sibyte/sb1250.h>
107 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
108 #include <asm/sibyte/bcm1480_regs.h>
109 #include <asm/sibyte/bcm1480_int.h>
110 #define R_MAC_DMA_OODPKTLOST_RX R_MAC_DMA_OODPKTLOST
111 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
112 #include <asm/sibyte/sb1250_regs.h>
113 #include <asm/sibyte/sb1250_int.h>
114 #else
115 #error invalid SiByte MAC configuation
116 #endif
117 #include <asm/sibyte/sb1250_scd.h>
118 #include <asm/sibyte/sb1250_mac.h>
119 #include <asm/sibyte/sb1250_dma.h>
120
121 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
122 #define UNIT_INT(n)             (K_BCM1480_INT_MAC_0 + ((n) * 2))
123 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
124 #define UNIT_INT(n)             (K_INT_MAC_0 + (n))
125 #else
126 #error invalid SiByte MAC configuation
127 #endif
128
129 #ifdef K_INT_PHY
130 #define SBMAC_PHY_INT                   K_INT_PHY
131 #else
132 #define SBMAC_PHY_INT                   PHY_POLL
133 #endif
134
135 /**********************************************************************
136  *  Simple types
137  ********************************************************************* */
138
139 enum sbmac_speed {
140         sbmac_speed_none = 0,
141         sbmac_speed_10 = SPEED_10,
142         sbmac_speed_100 = SPEED_100,
143         sbmac_speed_1000 = SPEED_1000,
144 };
145
146 enum sbmac_duplex {
147         sbmac_duplex_none = -1,
148         sbmac_duplex_half = DUPLEX_HALF,
149         sbmac_duplex_full = DUPLEX_FULL,
150 };
151
152 enum sbmac_fc {
153         sbmac_fc_none,
154         sbmac_fc_disabled,
155         sbmac_fc_frame,
156         sbmac_fc_collision,
157         sbmac_fc_carrier,
158 };
159
160 enum sbmac_state {
161         sbmac_state_uninit,
162         sbmac_state_off,
163         sbmac_state_on,
164         sbmac_state_broken,
165 };
166
167
168 /**********************************************************************
169  *  Macros
170  ********************************************************************* */
171
172
173 #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
174                           (d)->sbdma_dscrtable : (d)->f+1)
175
176
177 #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
178
179 #define SBMAC_MAX_TXDESCR       256
180 #define SBMAC_MAX_RXDESCR       256
181
182 #define ETHER_ALIGN     2
183 #define ETHER_ADDR_LEN  6
184 #define ENET_PACKET_SIZE        1518
185 /*#define ENET_PACKET_SIZE      9216 */
186
187 /**********************************************************************
188  *  DMA Descriptor structure
189  ********************************************************************* */
190
191 struct sbdmadscr {
192         uint64_t  dscr_a;
193         uint64_t  dscr_b;
194 };
195
196 /**********************************************************************
197  *  DMA Controller structure
198  ********************************************************************* */
199
200 struct sbmacdma {
201
202         /*
203          * This stuff is used to identify the channel and the registers
204          * associated with it.
205          */
206         struct sbmac_softc      *sbdma_eth;     /* back pointer to associated
207                                                    MAC */
208         int                     sbdma_channel;  /* channel number */
209         int                     sbdma_txdir;    /* direction (1=transmit) */
210         int                     sbdma_maxdescr; /* total # of descriptors
211                                                    in ring */
212 #ifdef CONFIG_SBMAC_COALESCE
213         int                     sbdma_int_pktcnt;
214                                                 /* # descriptors rx/tx
215                                                    before interrupt */
216         int                     sbdma_int_timeout;
217                                                 /* # usec rx/tx interrupt */
218 #endif
219         void __iomem            *sbdma_config0; /* DMA config register 0 */
220         void __iomem            *sbdma_config1; /* DMA config register 1 */
221         void __iomem            *sbdma_dscrbase;
222                                                 /* descriptor base address */
223         void __iomem            *sbdma_dscrcnt; /* descriptor count register */
224         void __iomem            *sbdma_curdscr; /* current descriptor
225                                                    address */
226         void __iomem            *sbdma_oodpktlost;
227                                                 /* pkt drop (rx only) */
228
229         /*
230          * This stuff is for maintenance of the ring
231          */
232         void                    *sbdma_dscrtable_unaligned;
233         struct sbdmadscr        *sbdma_dscrtable;
234                                                 /* base of descriptor table */
235         struct sbdmadscr        *sbdma_dscrtable_end;
236                                                 /* end of descriptor table */
237         struct sk_buff          **sbdma_ctxtable;
238                                                 /* context table, one
239                                                    per descr */
240         dma_addr_t              sbdma_dscrtable_phys;
241                                                 /* and also the phys addr */
242         struct sbdmadscr        *sbdma_addptr;  /* next dscr for sw to add */
243         struct sbdmadscr        *sbdma_remptr;  /* next dscr for sw
244                                                    to remove */
245 };
246
247
248 /**********************************************************************
249  *  Ethernet softc structure
250  ********************************************************************* */
251
252 struct sbmac_softc {
253
254         /*
255          * Linux-specific things
256          */
257         struct net_device       *sbm_dev;       /* pointer to linux device */
258         struct napi_struct      napi;
259         struct phy_device       *phy_dev;       /* the associated PHY device */
260         struct mii_bus          mii_bus;        /* the MII bus */
261         int                     phy_irq[PHY_MAX_ADDR];
262         spinlock_t              sbm_lock;       /* spin lock */
263         int                     sbm_devflags;   /* current device flags */
264
265         int                     sbm_buffersize;
266
267         /*
268          * Controller-specific things
269          */
270         void __iomem            *sbm_base;      /* MAC's base address */
271         enum sbmac_state        sbm_state;      /* current state */
272
273         void __iomem            *sbm_macenable; /* MAC Enable Register */
274         void __iomem            *sbm_maccfg;    /* MAC Config Register */
275         void __iomem            *sbm_fifocfg;   /* FIFO Config Register */
276         void __iomem            *sbm_framecfg;  /* Frame Config Register */
277         void __iomem            *sbm_rxfilter;  /* Receive Filter Register */
278         void __iomem            *sbm_isr;       /* Interrupt Status Register */
279         void __iomem            *sbm_imr;       /* Interrupt Mask Register */
280         void __iomem            *sbm_mdio;      /* MDIO Register */
281
282         enum sbmac_speed        sbm_speed;      /* current speed */
283         enum sbmac_duplex       sbm_duplex;     /* current duplex */
284         enum sbmac_fc           sbm_fc;         /* cur. flow control setting */
285         int                     sbm_pause;      /* current pause setting */
286         int                     sbm_link;       /* current link state */
287
288         unsigned char           sbm_hwaddr[ETHER_ADDR_LEN];
289
290         struct sbmacdma         sbm_txdma;      /* only channel 0 for now */
291         struct sbmacdma         sbm_rxdma;
292         int                     rx_hw_checksum;
293         int                     sbe_idx;
294 };
295
296
297 /**********************************************************************
298  *  Externs
299  ********************************************************************* */
300
301 /**********************************************************************
302  *  Prototypes
303  ********************************************************************* */
304
305 static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan,
306                           int txrx, int maxdescr);
307 static void sbdma_channel_start(struct sbmacdma *d, int rxtx);
308 static int sbdma_add_rcvbuffer(struct sbmacdma *d, struct sk_buff *m);
309 static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *m);
310 static void sbdma_emptyring(struct sbmacdma *d);
311 static void sbdma_fillring(struct sbmacdma *d);
312 static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d,
313                             int work_to_do, int poll);
314 static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d,
315                              int poll);
316 static int sbmac_initctx(struct sbmac_softc *s);
317 static void sbmac_channel_start(struct sbmac_softc *s);
318 static void sbmac_channel_stop(struct sbmac_softc *s);
319 static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *,
320                                                 enum sbmac_state);
321 static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff);
322 static uint64_t sbmac_addr2reg(unsigned char *ptr);
323 static irqreturn_t sbmac_intr(int irq, void *dev_instance);
324 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
325 static void sbmac_setmulti(struct sbmac_softc *sc);
326 static int sbmac_init(struct platform_device *pldev, long long base);
327 static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed);
328 static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex,
329                             enum sbmac_fc fc);
330
331 static int sbmac_open(struct net_device *dev);
332 static void sbmac_tx_timeout (struct net_device *dev);
333 static void sbmac_set_rx_mode(struct net_device *dev);
334 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
335 static int sbmac_close(struct net_device *dev);
336 static int sbmac_poll(struct napi_struct *napi, int budget);
337
338 static void sbmac_mii_poll(struct net_device *dev);
339 static int sbmac_mii_probe(struct net_device *dev);
340
341 static void sbmac_mii_sync(void __iomem *sbm_mdio);
342 static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data,
343                                int bitcnt);
344 static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx);
345 static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
346                            u16 val);
347
348
349 /**********************************************************************
350  *  Globals
351  ********************************************************************* */
352
353 static char sbmac_string[] = "sb1250-mac";
354 static char sbmac_pretty[] = "SB1250 MAC";
355
356 static char sbmac_mdio_string[] = "sb1250-mac-mdio";
357
358
359 /**********************************************************************
360  *  MDIO constants
361  ********************************************************************* */
362
363 #define MII_COMMAND_START       0x01
364 #define MII_COMMAND_READ        0x02
365 #define MII_COMMAND_WRITE       0x01
366 #define MII_COMMAND_ACK         0x02
367
368 #define M_MAC_MDIO_DIR_OUTPUT   0               /* for clarity */
369
370 #define ENABLE          1
371 #define DISABLE         0
372
373 /**********************************************************************
374  *  SBMAC_MII_SYNC(sbm_mdio)
375  *
376  *  Synchronize with the MII - send a pattern of bits to the MII
377  *  that will guarantee that it is ready to accept a command.
378  *
379  *  Input parameters:
380  *         sbm_mdio - address of the MAC's MDIO register
381  *
382  *  Return value:
383  *         nothing
384  ********************************************************************* */
385
386 static void sbmac_mii_sync(void __iomem *sbm_mdio)
387 {
388         int cnt;
389         uint64_t bits;
390         int mac_mdio_genc;
391
392         mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
393
394         bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
395
396         __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
397
398         for (cnt = 0; cnt < 32; cnt++) {
399                 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio);
400                 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
401         }
402 }
403
404 /**********************************************************************
405  *  SBMAC_MII_SENDDATA(sbm_mdio, data, bitcnt)
406  *
407  *  Send some bits to the MII.  The bits to be sent are right-
408  *  justified in the 'data' parameter.
409  *
410  *  Input parameters:
411  *         sbm_mdio - address of the MAC's MDIO register
412  *         data     - data to send
413  *         bitcnt   - number of bits to send
414  ********************************************************************* */
415
416 static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data,
417                                int bitcnt)
418 {
419         int i;
420         uint64_t bits;
421         unsigned int curmask;
422         int mac_mdio_genc;
423
424         mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
425
426         bits = M_MAC_MDIO_DIR_OUTPUT;
427         __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
428
429         curmask = 1 << (bitcnt - 1);
430
431         for (i = 0; i < bitcnt; i++) {
432                 if (data & curmask)
433                         bits |= M_MAC_MDIO_OUT;
434                 else bits &= ~M_MAC_MDIO_OUT;
435                 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
436                 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio);
437                 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
438                 curmask >>= 1;
439         }
440 }
441
442
443
444 /**********************************************************************
445  *  SBMAC_MII_READ(bus, phyaddr, regidx)
446  *  Read a PHY register.
447  *
448  *  Input parameters:
449  *         bus     - MDIO bus handle
450  *         phyaddr - PHY's address
451  *         regnum  - index of register to read
452  *
453  *  Return value:
454  *         value read, or 0xffff if an error occurred.
455  ********************************************************************* */
456
457 static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
458 {
459         struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv;
460         void __iomem *sbm_mdio = sc->sbm_mdio;
461         int idx;
462         int error;
463         int regval;
464         int mac_mdio_genc;
465
466         /*
467          * Synchronize ourselves so that the PHY knows the next
468          * thing coming down is a command
469          */
470         sbmac_mii_sync(sbm_mdio);
471
472         /*
473          * Send the data to the PHY.  The sequence is
474          * a "start" command (2 bits)
475          * a "read" command (2 bits)
476          * the PHY addr (5 bits)
477          * the register index (5 bits)
478          */
479         sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2);
480         sbmac_mii_senddata(sbm_mdio, MII_COMMAND_READ, 2);
481         sbmac_mii_senddata(sbm_mdio, phyaddr, 5);
482         sbmac_mii_senddata(sbm_mdio, regidx, 5);
483
484         mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
485
486         /*
487          * Switch the port around without a clock transition.
488          */
489         __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
490
491         /*
492          * Send out a clock pulse to signal we want the status
493          */
494         __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
495                      sbm_mdio);
496         __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
497
498         /*
499          * If an error occurred, the PHY will signal '1' back
500          */
501         error = __raw_readq(sbm_mdio) & M_MAC_MDIO_IN;
502
503         /*
504          * Issue an 'idle' clock pulse, but keep the direction
505          * the same.
506          */
507         __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
508                      sbm_mdio);
509         __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
510
511         regval = 0;
512
513         for (idx = 0; idx < 16; idx++) {
514                 regval <<= 1;
515
516                 if (error == 0) {
517                         if (__raw_readq(sbm_mdio) & M_MAC_MDIO_IN)
518                                 regval |= 1;
519                 }
520
521                 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
522                              sbm_mdio);
523                 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
524         }
525
526         /* Switch back to output */
527         __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio);
528
529         if (error == 0)
530                 return regval;
531         return 0xffff;
532 }
533
534
535 /**********************************************************************
536  *  SBMAC_MII_WRITE(bus, phyaddr, regidx, regval)
537  *
538  *  Write a value to a PHY register.
539  *
540  *  Input parameters:
541  *         bus     - MDIO bus handle
542  *         phyaddr - PHY to use
543  *         regidx  - register within the PHY
544  *         regval  - data to write to register
545  *
546  *  Return value:
547  *         0 for success
548  ********************************************************************* */
549
550 static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
551                            u16 regval)
552 {
553         struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv;
554         void __iomem *sbm_mdio = sc->sbm_mdio;
555         int mac_mdio_genc;
556
557         sbmac_mii_sync(sbm_mdio);
558
559         sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2);
560         sbmac_mii_senddata(sbm_mdio, MII_COMMAND_WRITE, 2);
561         sbmac_mii_senddata(sbm_mdio, phyaddr, 5);
562         sbmac_mii_senddata(sbm_mdio, regidx, 5);
563         sbmac_mii_senddata(sbm_mdio, MII_COMMAND_ACK, 2);
564         sbmac_mii_senddata(sbm_mdio, regval, 16);
565
566         mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
567
568         __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio);
569
570         return 0;
571 }
572
573
574
575 /**********************************************************************
576  *  SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
577  *
578  *  Initialize a DMA channel context.  Since there are potentially
579  *  eight DMA channels per MAC, it's nice to do this in a standard
580  *  way.
581  *
582  *  Input parameters:
583  *         d - struct sbmacdma (DMA channel context)
584  *         s - struct sbmac_softc (pointer to a MAC)
585  *         chan - channel number (0..1 right now)
586  *         txrx - Identifies DMA_TX or DMA_RX for channel direction
587  *      maxdescr - number of descriptors
588  *
589  *  Return value:
590  *         nothing
591  ********************************************************************* */
592
593 static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan,
594                           int txrx, int maxdescr)
595 {
596 #ifdef CONFIG_SBMAC_COALESCE
597         int int_pktcnt, int_timeout;
598 #endif
599
600         /*
601          * Save away interesting stuff in the structure
602          */
603
604         d->sbdma_eth       = s;
605         d->sbdma_channel   = chan;
606         d->sbdma_txdir     = txrx;
607
608 #if 0
609         /* RMON clearing */
610         s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
611 #endif
612
613         __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BYTES);
614         __raw_writeq(0, s->sbm_base + R_MAC_RMON_COLLISIONS);
615         __raw_writeq(0, s->sbm_base + R_MAC_RMON_LATE_COL);
616         __raw_writeq(0, s->sbm_base + R_MAC_RMON_EX_COL);
617         __raw_writeq(0, s->sbm_base + R_MAC_RMON_FCS_ERROR);
618         __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_ABORT);
619         __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BAD);
620         __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_GOOD);
621         __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_RUNT);
622         __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_OVERSIZE);
623         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BYTES);
624         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_MCAST);
625         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BCAST);
626         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BAD);
627         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_GOOD);
628         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_RUNT);
629         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_OVERSIZE);
630         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_FCS_ERROR);
631         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_LENGTH_ERROR);
632         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_CODE_ERROR);
633         __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_ALIGN_ERROR);
634
635         /*
636          * initialize register pointers
637          */
638
639         d->sbdma_config0 =
640                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
641         d->sbdma_config1 =
642                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
643         d->sbdma_dscrbase =
644                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
645         d->sbdma_dscrcnt =
646                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
647         d->sbdma_curdscr =
648                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
649         if (d->sbdma_txdir)
650                 d->sbdma_oodpktlost = NULL;
651         else
652                 d->sbdma_oodpktlost =
653                         s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_OODPKTLOST_RX);
654
655         /*
656          * Allocate memory for the ring
657          */
658
659         d->sbdma_maxdescr = maxdescr;
660
661         d->sbdma_dscrtable_unaligned = kcalloc(d->sbdma_maxdescr + 1,
662                                                sizeof(*d->sbdma_dscrtable),
663                                                GFP_KERNEL);
664
665         /*
666          * The descriptor table must be aligned to at least 16 bytes or the
667          * MAC will corrupt it.
668          */
669         d->sbdma_dscrtable = (struct sbdmadscr *)
670                              ALIGN((unsigned long)d->sbdma_dscrtable_unaligned,
671                                    sizeof(*d->sbdma_dscrtable));
672
673         d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
674
675         d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
676
677         /*
678          * And context table
679          */
680
681         d->sbdma_ctxtable = kcalloc(d->sbdma_maxdescr,
682                                     sizeof(*d->sbdma_ctxtable), GFP_KERNEL);
683
684 #ifdef CONFIG_SBMAC_COALESCE
685         /*
686          * Setup Rx/Tx DMA coalescing defaults
687          */
688
689         int_pktcnt = (txrx == DMA_TX) ? int_pktcnt_tx : int_pktcnt_rx;
690         if ( int_pktcnt ) {
691                 d->sbdma_int_pktcnt = int_pktcnt;
692         } else {
693                 d->sbdma_int_pktcnt = 1;
694         }
695
696         int_timeout = (txrx == DMA_TX) ? int_timeout_tx : int_timeout_rx;
697         if ( int_timeout ) {
698                 d->sbdma_int_timeout = int_timeout;
699         } else {
700                 d->sbdma_int_timeout = 0;
701         }
702 #endif
703
704 }
705
706 /**********************************************************************
707  *  SBDMA_CHANNEL_START(d)
708  *
709  *  Initialize the hardware registers for a DMA channel.
710  *
711  *  Input parameters:
712  *         d - DMA channel to init (context must be previously init'd
713  *         rxtx - DMA_RX or DMA_TX depending on what type of channel
714  *
715  *  Return value:
716  *         nothing
717  ********************************************************************* */
718
719 static void sbdma_channel_start(struct sbmacdma *d, int rxtx)
720 {
721         /*
722          * Turn on the DMA channel
723          */
724
725 #ifdef CONFIG_SBMAC_COALESCE
726         __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
727                        0, d->sbdma_config1);
728         __raw_writeq(M_DMA_EOP_INT_EN |
729                        V_DMA_RINGSZ(d->sbdma_maxdescr) |
730                        V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
731                        0, d->sbdma_config0);
732 #else
733         __raw_writeq(0, d->sbdma_config1);
734         __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) |
735                        0, d->sbdma_config0);
736 #endif
737
738         __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase);
739
740         /*
741          * Initialize ring pointers
742          */
743
744         d->sbdma_addptr = d->sbdma_dscrtable;
745         d->sbdma_remptr = d->sbdma_dscrtable;
746 }
747
748 /**********************************************************************
749  *  SBDMA_CHANNEL_STOP(d)
750  *
751  *  Initialize the hardware registers for a DMA channel.
752  *
753  *  Input parameters:
754  *         d - DMA channel to init (context must be previously init'd
755  *
756  *  Return value:
757  *         nothing
758  ********************************************************************* */
759
760 static void sbdma_channel_stop(struct sbmacdma *d)
761 {
762         /*
763          * Turn off the DMA channel
764          */
765
766         __raw_writeq(0, d->sbdma_config1);
767
768         __raw_writeq(0, d->sbdma_dscrbase);
769
770         __raw_writeq(0, d->sbdma_config0);
771
772         /*
773          * Zero ring pointers
774          */
775
776         d->sbdma_addptr = NULL;
777         d->sbdma_remptr = NULL;
778 }
779
780 static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset)
781 {
782         unsigned long addr;
783         unsigned long newaddr;
784
785         addr = (unsigned long) skb->data;
786
787         newaddr = (addr + power2 - 1) & ~(power2 - 1);
788
789         skb_reserve(skb,newaddr-addr+offset);
790 }
791
792
793 /**********************************************************************
794  *  SBDMA_ADD_RCVBUFFER(d,sb)
795  *
796  *  Add a buffer to the specified DMA channel.   For receive channels,
797  *  this queues a buffer for inbound packets.
798  *
799  *  Input parameters:
800  *         d - DMA channel descriptor
801  *         sb - sk_buff to add, or NULL if we should allocate one
802  *
803  *  Return value:
804  *         0 if buffer could not be added (ring is full)
805  *         1 if buffer added successfully
806  ********************************************************************* */
807
808
809 static int sbdma_add_rcvbuffer(struct sbmacdma *d, struct sk_buff *sb)
810 {
811         struct sbdmadscr *dsc;
812         struct sbdmadscr *nextdsc;
813         struct sk_buff *sb_new = NULL;
814         int pktsize = ENET_PACKET_SIZE;
815
816         /* get pointer to our current place in the ring */
817
818         dsc = d->sbdma_addptr;
819         nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
820
821         /*
822          * figure out if the ring is full - if the next descriptor
823          * is the same as the one that we're going to remove from
824          * the ring, the ring is full
825          */
826
827         if (nextdsc == d->sbdma_remptr) {
828                 return -ENOSPC;
829         }
830
831         /*
832          * Allocate a sk_buff if we don't already have one.
833          * If we do have an sk_buff, reset it so that it's empty.
834          *
835          * Note: sk_buffs don't seem to be guaranteed to have any sort
836          * of alignment when they are allocated.  Therefore, allocate enough
837          * extra space to make sure that:
838          *
839          *    1. the data does not start in the middle of a cache line.
840          *    2. The data does not end in the middle of a cache line
841          *    3. The buffer can be aligned such that the IP addresses are
842          *       naturally aligned.
843          *
844          *  Remember, the SOCs MAC writes whole cache lines at a time,
845          *  without reading the old contents first.  So, if the sk_buff's
846          *  data portion starts in the middle of a cache line, the SOC
847          *  DMA will trash the beginning (and ending) portions.
848          */
849
850         if (sb == NULL) {
851                 sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN);
852                 if (sb_new == NULL) {
853                         pr_info("%s: sk_buff allocation failed\n",
854                                d->sbdma_eth->sbm_dev->name);
855                         return -ENOBUFS;
856                 }
857
858                 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, ETHER_ALIGN);
859         }
860         else {
861                 sb_new = sb;
862                 /*
863                  * nothing special to reinit buffer, it's already aligned
864                  * and sb->data already points to a good place.
865                  */
866         }
867
868         /*
869          * fill in the descriptor
870          */
871
872 #ifdef CONFIG_SBMAC_COALESCE
873         /*
874          * Do not interrupt per DMA transfer.
875          */
876         dsc->dscr_a = virt_to_phys(sb_new->data) |
877                 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) | 0;
878 #else
879         dsc->dscr_a = virt_to_phys(sb_new->data) |
880                 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
881                 M_DMA_DSCRA_INTERRUPT;
882 #endif
883
884         /* receiving: no options */
885         dsc->dscr_b = 0;
886
887         /*
888          * fill in the context
889          */
890
891         d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
892
893         /*
894          * point at next packet
895          */
896
897         d->sbdma_addptr = nextdsc;
898
899         /*
900          * Give the buffer to the DMA engine.
901          */
902
903         __raw_writeq(1, d->sbdma_dscrcnt);
904
905         return 0;                                       /* we did it */
906 }
907
908 /**********************************************************************
909  *  SBDMA_ADD_TXBUFFER(d,sb)
910  *
911  *  Add a transmit buffer to the specified DMA channel, causing a
912  *  transmit to start.
913  *
914  *  Input parameters:
915  *         d - DMA channel descriptor
916  *         sb - sk_buff to add
917  *
918  *  Return value:
919  *         0 transmit queued successfully
920  *         otherwise error code
921  ********************************************************************* */
922
923
924 static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *sb)
925 {
926         struct sbdmadscr *dsc;
927         struct sbdmadscr *nextdsc;
928         uint64_t phys;
929         uint64_t ncb;
930         int length;
931
932         /* get pointer to our current place in the ring */
933
934         dsc = d->sbdma_addptr;
935         nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
936
937         /*
938          * figure out if the ring is full - if the next descriptor
939          * is the same as the one that we're going to remove from
940          * the ring, the ring is full
941          */
942
943         if (nextdsc == d->sbdma_remptr) {
944                 return -ENOSPC;
945         }
946
947         /*
948          * Under Linux, it's not necessary to copy/coalesce buffers
949          * like it is on NetBSD.  We think they're all contiguous,
950          * but that may not be true for GBE.
951          */
952
953         length = sb->len;
954
955         /*
956          * fill in the descriptor.  Note that the number of cache
957          * blocks in the descriptor is the number of blocks
958          * *spanned*, so we need to add in the offset (if any)
959          * while doing the calculation.
960          */
961
962         phys = virt_to_phys(sb->data);
963         ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
964
965         dsc->dscr_a = phys |
966                 V_DMA_DSCRA_A_SIZE(ncb) |
967 #ifndef CONFIG_SBMAC_COALESCE
968                 M_DMA_DSCRA_INTERRUPT |
969 #endif
970                 M_DMA_ETHTX_SOP;
971
972         /* transmitting: set outbound options and length */
973
974         dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
975                 V_DMA_DSCRB_PKT_SIZE(length);
976
977         /*
978          * fill in the context
979          */
980
981         d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
982
983         /*
984          * point at next packet
985          */
986
987         d->sbdma_addptr = nextdsc;
988
989         /*
990          * Give the buffer to the DMA engine.
991          */
992
993         __raw_writeq(1, d->sbdma_dscrcnt);
994
995         return 0;                                       /* we did it */
996 }
997
998
999
1000
1001 /**********************************************************************
1002  *  SBDMA_EMPTYRING(d)
1003  *
1004  *  Free all allocated sk_buffs on the specified DMA channel;
1005  *
1006  *  Input parameters:
1007  *         d  - DMA channel
1008  *
1009  *  Return value:
1010  *         nothing
1011  ********************************************************************* */
1012
1013 static void sbdma_emptyring(struct sbmacdma *d)
1014 {
1015         int idx;
1016         struct sk_buff *sb;
1017
1018         for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
1019                 sb = d->sbdma_ctxtable[idx];
1020                 if (sb) {
1021                         dev_kfree_skb(sb);
1022                         d->sbdma_ctxtable[idx] = NULL;
1023                 }
1024         }
1025 }
1026
1027
1028 /**********************************************************************
1029  *  SBDMA_FILLRING(d)
1030  *
1031  *  Fill the specified DMA channel (must be receive channel)
1032  *  with sk_buffs
1033  *
1034  *  Input parameters:
1035  *         d - DMA channel
1036  *
1037  *  Return value:
1038  *         nothing
1039  ********************************************************************* */
1040
1041 static void sbdma_fillring(struct sbmacdma *d)
1042 {
1043         int idx;
1044
1045         for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) {
1046                 if (sbdma_add_rcvbuffer(d,NULL) != 0)
1047                         break;
1048         }
1049 }
1050
1051 #ifdef CONFIG_NET_POLL_CONTROLLER
1052 static void sbmac_netpoll(struct net_device *netdev)
1053 {
1054         struct sbmac_softc *sc = netdev_priv(netdev);
1055         int irq = sc->sbm_dev->irq;
1056
1057         __raw_writeq(0, sc->sbm_imr);
1058
1059         sbmac_intr(irq, netdev);
1060
1061 #ifdef CONFIG_SBMAC_COALESCE
1062         __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1063         ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
1064         sc->sbm_imr);
1065 #else
1066         __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | 
1067         (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
1068 #endif
1069 }
1070 #endif
1071
1072 /**********************************************************************
1073  *  SBDMA_RX_PROCESS(sc,d,work_to_do,poll)
1074  *
1075  *  Process "completed" receive buffers on the specified DMA channel.
1076  *
1077  *  Input parameters:
1078  *            sc - softc structure
1079  *             d - DMA channel context
1080  *    work_to_do - no. of packets to process before enabling interrupt
1081  *                 again (for NAPI)
1082  *          poll - 1: using polling (for NAPI)
1083  *
1084  *  Return value:
1085  *         nothing
1086  ********************************************************************* */
1087
1088 static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d,
1089                             int work_to_do, int poll)
1090 {
1091         struct net_device *dev = sc->sbm_dev;
1092         int curidx;
1093         int hwidx;
1094         struct sbdmadscr *dsc;
1095         struct sk_buff *sb;
1096         int len;
1097         int work_done = 0;
1098         int dropped = 0;
1099
1100         prefetch(d);
1101
1102 again:
1103         /* Check if the HW dropped any frames */
1104         dev->stats.rx_fifo_errors
1105             += __raw_readq(sc->sbm_rxdma.sbdma_oodpktlost) & 0xffff;
1106         __raw_writeq(0, sc->sbm_rxdma.sbdma_oodpktlost);
1107
1108         while (work_to_do-- > 0) {
1109                 /*
1110                  * figure out where we are (as an index) and where
1111                  * the hardware is (also as an index)
1112                  *
1113                  * This could be done faster if (for example) the
1114                  * descriptor table was page-aligned and contiguous in
1115                  * both virtual and physical memory -- you could then
1116                  * just compare the low-order bits of the virtual address
1117                  * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1118                  */
1119
1120                 dsc = d->sbdma_remptr;
1121                 curidx = dsc - d->sbdma_dscrtable;
1122
1123                 prefetch(dsc);
1124                 prefetch(&d->sbdma_ctxtable[curidx]);
1125
1126                 hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1127                          d->sbdma_dscrtable_phys) /
1128                         sizeof(*d->sbdma_dscrtable);
1129
1130                 /*
1131                  * If they're the same, that means we've processed all
1132                  * of the descriptors up to (but not including) the one that
1133                  * the hardware is working on right now.
1134                  */
1135
1136                 if (curidx == hwidx)
1137                         goto done;
1138
1139                 /*
1140                  * Otherwise, get the packet's sk_buff ptr back
1141                  */
1142
1143                 sb = d->sbdma_ctxtable[curidx];
1144                 d->sbdma_ctxtable[curidx] = NULL;
1145
1146                 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1147
1148                 /*
1149                  * Check packet status.  If good, process it.
1150                  * If not, silently drop it and put it back on the
1151                  * receive ring.
1152                  */
1153
1154                 if (likely (!(dsc->dscr_a & M_DMA_ETHRX_BAD))) {
1155
1156                         /*
1157                          * Add a new buffer to replace the old one.  If we fail
1158                          * to allocate a buffer, we're going to drop this
1159                          * packet and put it right back on the receive ring.
1160                          */
1161
1162                         if (unlikely (sbdma_add_rcvbuffer(d,NULL) ==
1163                                       -ENOBUFS)) {
1164                                 dev->stats.rx_dropped++;
1165                                 sbdma_add_rcvbuffer(d,sb); /* re-add old buffer */
1166                                 /* No point in continuing at the moment */
1167                                 printk(KERN_ERR "dropped packet (1)\n");
1168                                 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1169                                 goto done;
1170                         } else {
1171                                 /*
1172                                  * Set length into the packet
1173                                  */
1174                                 skb_put(sb,len);
1175
1176                                 /*
1177                                  * Buffer has been replaced on the
1178                                  * receive ring.  Pass the buffer to
1179                                  * the kernel
1180                                  */
1181                                 sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
1182                                 /* Check hw IPv4/TCP checksum if supported */
1183                                 if (sc->rx_hw_checksum == ENABLE) {
1184                                         if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&
1185                                             !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {
1186                                                 sb->ip_summed = CHECKSUM_UNNECESSARY;
1187                                                 /* don't need to set sb->csum */
1188                                         } else {
1189                                                 sb->ip_summed = CHECKSUM_NONE;
1190                                         }
1191                                 }
1192                                 prefetch(sb->data);
1193                                 prefetch((const void *)(((char *)sb->data)+32));
1194                                 if (poll)
1195                                         dropped = netif_receive_skb(sb);
1196                                 else
1197                                         dropped = netif_rx(sb);
1198
1199                                 if (dropped == NET_RX_DROP) {
1200                                         dev->stats.rx_dropped++;
1201                                         d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1202                                         goto done;
1203                                 }
1204                                 else {
1205                                         dev->stats.rx_bytes += len;
1206                                         dev->stats.rx_packets++;
1207                                 }
1208                         }
1209                 } else {
1210                         /*
1211                          * Packet was mangled somehow.  Just drop it and
1212                          * put it back on the receive ring.
1213                          */
1214                         dev->stats.rx_errors++;
1215                         sbdma_add_rcvbuffer(d,sb);
1216                 }
1217
1218
1219                 /*
1220                  * .. and advance to the next buffer.
1221                  */
1222
1223                 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1224                 work_done++;
1225         }
1226         if (!poll) {
1227                 work_to_do = 32;
1228                 goto again; /* collect fifo drop statistics again */
1229         }
1230 done:
1231         return work_done;
1232 }
1233
1234 /**********************************************************************
1235  *  SBDMA_TX_PROCESS(sc,d)
1236  *
1237  *  Process "completed" transmit buffers on the specified DMA channel.
1238  *  This is normally called within the interrupt service routine.
1239  *  Note that this isn't really ideal for priority channels, since
1240  *  it processes all of the packets on a given channel before
1241  *  returning.
1242  *
1243  *  Input parameters:
1244  *      sc - softc structure
1245  *       d - DMA channel context
1246  *    poll - 1: using polling (for NAPI)
1247  *
1248  *  Return value:
1249  *         nothing
1250  ********************************************************************* */
1251
1252 static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d,
1253                              int poll)
1254 {
1255         struct net_device *dev = sc->sbm_dev;
1256         int curidx;
1257         int hwidx;
1258         struct sbdmadscr *dsc;
1259         struct sk_buff *sb;
1260         unsigned long flags;
1261         int packets_handled = 0;
1262
1263         spin_lock_irqsave(&(sc->sbm_lock), flags);
1264
1265         if (d->sbdma_remptr == d->sbdma_addptr)
1266           goto end_unlock;
1267
1268         hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1269                  d->sbdma_dscrtable_phys) / sizeof(*d->sbdma_dscrtable);
1270
1271         for (;;) {
1272                 /*
1273                  * figure out where we are (as an index) and where
1274                  * the hardware is (also as an index)
1275                  *
1276                  * This could be done faster if (for example) the
1277                  * descriptor table was page-aligned and contiguous in
1278                  * both virtual and physical memory -- you could then
1279                  * just compare the low-order bits of the virtual address
1280                  * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1281                  */
1282
1283                 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1284
1285                 /*
1286                  * If they're the same, that means we've processed all
1287                  * of the descriptors up to (but not including) the one that
1288                  * the hardware is working on right now.
1289                  */
1290
1291                 if (curidx == hwidx)
1292                         break;
1293
1294                 /*
1295                  * Otherwise, get the packet's sk_buff ptr back
1296                  */
1297
1298                 dsc = &(d->sbdma_dscrtable[curidx]);
1299                 sb = d->sbdma_ctxtable[curidx];
1300                 d->sbdma_ctxtable[curidx] = NULL;
1301
1302                 /*
1303                  * Stats
1304                  */
1305
1306                 dev->stats.tx_bytes += sb->len;
1307                 dev->stats.tx_packets++;
1308
1309                 /*
1310                  * for transmits, we just free buffers.
1311                  */
1312
1313                 dev_kfree_skb_irq(sb);
1314
1315                 /*
1316                  * .. and advance to the next buffer.
1317                  */
1318
1319                 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1320
1321                 packets_handled++;
1322
1323         }
1324
1325         /*
1326          * Decide if we should wake up the protocol or not.
1327          * Other drivers seem to do this when we reach a low
1328          * watermark on the transmit queue.
1329          */
1330
1331         if (packets_handled)
1332                 netif_wake_queue(d->sbdma_eth->sbm_dev);
1333
1334 end_unlock:
1335         spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1336
1337 }
1338
1339
1340
1341 /**********************************************************************
1342  *  SBMAC_INITCTX(s)
1343  *
1344  *  Initialize an Ethernet context structure - this is called
1345  *  once per MAC on the 1250.  Memory is allocated here, so don't
1346  *  call it again from inside the ioctl routines that bring the
1347  *  interface up/down
1348  *
1349  *  Input parameters:
1350  *         s - sbmac context structure
1351  *
1352  *  Return value:
1353  *         0
1354  ********************************************************************* */
1355
1356 static int sbmac_initctx(struct sbmac_softc *s)
1357 {
1358
1359         /*
1360          * figure out the addresses of some ports
1361          */
1362
1363         s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
1364         s->sbm_maccfg    = s->sbm_base + R_MAC_CFG;
1365         s->sbm_fifocfg   = s->sbm_base + R_MAC_THRSH_CFG;
1366         s->sbm_framecfg  = s->sbm_base + R_MAC_FRAMECFG;
1367         s->sbm_rxfilter  = s->sbm_base + R_MAC_ADFILTER_CFG;
1368         s->sbm_isr       = s->sbm_base + R_MAC_STATUS;
1369         s->sbm_imr       = s->sbm_base + R_MAC_INT_MASK;
1370         s->sbm_mdio      = s->sbm_base + R_MAC_MDIO;
1371
1372         /*
1373          * Initialize the DMA channels.  Right now, only one per MAC is used
1374          * Note: Only do this _once_, as it allocates memory from the kernel!
1375          */
1376
1377         sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1378         sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1379
1380         /*
1381          * initial state is OFF
1382          */
1383
1384         s->sbm_state = sbmac_state_off;
1385
1386         return 0;
1387 }
1388
1389
1390 static void sbdma_uninitctx(struct sbmacdma *d)
1391 {
1392         if (d->sbdma_dscrtable_unaligned) {
1393                 kfree(d->sbdma_dscrtable_unaligned);
1394                 d->sbdma_dscrtable_unaligned = d->sbdma_dscrtable = NULL;
1395         }
1396
1397         if (d->sbdma_ctxtable) {
1398                 kfree(d->sbdma_ctxtable);
1399                 d->sbdma_ctxtable = NULL;
1400         }
1401 }
1402
1403
1404 static void sbmac_uninitctx(struct sbmac_softc *sc)
1405 {
1406         sbdma_uninitctx(&(sc->sbm_txdma));
1407         sbdma_uninitctx(&(sc->sbm_rxdma));
1408 }
1409
1410
1411 /**********************************************************************
1412  *  SBMAC_CHANNEL_START(s)
1413  *
1414  *  Start packet processing on this MAC.
1415  *
1416  *  Input parameters:
1417  *         s - sbmac structure
1418  *
1419  *  Return value:
1420  *         nothing
1421  ********************************************************************* */
1422
1423 static void sbmac_channel_start(struct sbmac_softc *s)
1424 {
1425         uint64_t reg;
1426         void __iomem *port;
1427         uint64_t cfg,fifo,framecfg;
1428         int idx, th_value;
1429
1430         /*
1431          * Don't do this if running
1432          */
1433
1434         if (s->sbm_state == sbmac_state_on)
1435                 return;
1436
1437         /*
1438          * Bring the controller out of reset, but leave it off.
1439          */
1440
1441         __raw_writeq(0, s->sbm_macenable);
1442
1443         /*
1444          * Ignore all received packets
1445          */
1446
1447         __raw_writeq(0, s->sbm_rxfilter);
1448
1449         /*
1450          * Calculate values for various control registers.
1451          */
1452
1453         cfg = M_MAC_RETRY_EN |
1454                 M_MAC_TX_HOLD_SOP_EN |
1455                 V_MAC_TX_PAUSE_CNT_16K |
1456                 M_MAC_AP_STAT_EN |
1457                 M_MAC_FAST_SYNC |
1458                 M_MAC_SS_EN |
1459                 0;
1460
1461         /*
1462          * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1463          * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1464          * Use a larger RD_THRSH for gigabit
1465          */
1466         if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2)
1467                 th_value = 28;
1468         else
1469                 th_value = 64;
1470
1471         fifo = V_MAC_TX_WR_THRSH(4) |   /* Must be '4' or '8' */
1472                 ((s->sbm_speed == sbmac_speed_1000)
1473                  ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |
1474                 V_MAC_TX_RL_THRSH(4) |
1475                 V_MAC_RX_PL_THRSH(4) |
1476                 V_MAC_RX_RD_THRSH(4) |  /* Must be '4' */
1477                 V_MAC_RX_PL_THRSH(4) |
1478                 V_MAC_RX_RL_THRSH(8) |
1479                 0;
1480
1481         framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
1482                 V_MAC_MAX_FRAMESZ_DEFAULT |
1483                 V_MAC_BACKOFF_SEL(1);
1484
1485         /*
1486          * Clear out the hash address map
1487          */
1488
1489         port = s->sbm_base + R_MAC_HASH_BASE;
1490         for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1491                 __raw_writeq(0, port);
1492                 port += sizeof(uint64_t);
1493         }
1494
1495         /*
1496          * Clear out the exact-match table
1497          */
1498
1499         port = s->sbm_base + R_MAC_ADDR_BASE;
1500         for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1501                 __raw_writeq(0, port);
1502                 port += sizeof(uint64_t);
1503         }
1504
1505         /*
1506          * Clear out the DMA Channel mapping table registers
1507          */
1508
1509         port = s->sbm_base + R_MAC_CHUP0_BASE;
1510         for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1511                 __raw_writeq(0, port);
1512                 port += sizeof(uint64_t);
1513         }
1514
1515
1516         port = s->sbm_base + R_MAC_CHLO0_BASE;
1517         for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1518                 __raw_writeq(0, port);
1519                 port += sizeof(uint64_t);
1520         }
1521
1522         /*
1523          * Program the hardware address.  It goes into the hardware-address
1524          * register as well as the first filter register.
1525          */
1526
1527         reg = sbmac_addr2reg(s->sbm_hwaddr);
1528
1529         port = s->sbm_base + R_MAC_ADDR_BASE;
1530         __raw_writeq(reg, port);
1531         port = s->sbm_base + R_MAC_ETHERNET_ADDR;
1532
1533 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1534         /*
1535          * Pass1 SOCs do not receive packets addressed to the
1536          * destination address in the R_MAC_ETHERNET_ADDR register.
1537          * Set the value to zero.
1538          */
1539         __raw_writeq(0, port);
1540 #else
1541         __raw_writeq(reg, port);
1542 #endif
1543
1544         /*
1545          * Set the receive filter for no packets, and write values
1546          * to the various config registers
1547          */
1548
1549         __raw_writeq(0, s->sbm_rxfilter);
1550         __raw_writeq(0, s->sbm_imr);
1551         __raw_writeq(framecfg, s->sbm_framecfg);
1552         __raw_writeq(fifo, s->sbm_fifocfg);
1553         __raw_writeq(cfg, s->sbm_maccfg);
1554
1555         /*
1556          * Initialize DMA channels (rings should be ok now)
1557          */
1558
1559         sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1560         sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1561
1562         /*
1563          * Configure the speed, duplex, and flow control
1564          */
1565
1566         sbmac_set_speed(s,s->sbm_speed);
1567         sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1568
1569         /*
1570          * Fill the receive ring
1571          */
1572
1573         sbdma_fillring(&(s->sbm_rxdma));
1574
1575         /*
1576          * Turn on the rest of the bits in the enable register
1577          */
1578
1579 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
1580         __raw_writeq(M_MAC_RXDMA_EN0 |
1581                        M_MAC_TXDMA_EN0, s->sbm_macenable);
1582 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
1583         __raw_writeq(M_MAC_RXDMA_EN0 |
1584                        M_MAC_TXDMA_EN0 |
1585                        M_MAC_RX_ENABLE |
1586                        M_MAC_TX_ENABLE, s->sbm_macenable);
1587 #else
1588 #error invalid SiByte MAC configuation
1589 #endif
1590
1591 #ifdef CONFIG_SBMAC_COALESCE
1592         __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1593                        ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr);
1594 #else
1595         __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1596                        (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr);
1597 #endif
1598
1599         /*
1600          * Enable receiving unicasts and broadcasts
1601          */
1602
1603         __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter);
1604
1605         /*
1606          * we're running now.
1607          */
1608
1609         s->sbm_state = sbmac_state_on;
1610
1611         /*
1612          * Program multicast addresses
1613          */
1614
1615         sbmac_setmulti(s);
1616
1617         /*
1618          * If channel was in promiscuous mode before, turn that on
1619          */
1620
1621         if (s->sbm_devflags & IFF_PROMISC) {
1622                 sbmac_promiscuous_mode(s,1);
1623         }
1624
1625 }
1626
1627
1628 /**********************************************************************
1629  *  SBMAC_CHANNEL_STOP(s)
1630  *
1631  *  Stop packet processing on this MAC.
1632  *
1633  *  Input parameters:
1634  *         s - sbmac structure
1635  *
1636  *  Return value:
1637  *         nothing
1638  ********************************************************************* */
1639
1640 static void sbmac_channel_stop(struct sbmac_softc *s)
1641 {
1642         /* don't do this if already stopped */
1643
1644         if (s->sbm_state == sbmac_state_off)
1645                 return;
1646
1647         /* don't accept any packets, disable all interrupts */
1648
1649         __raw_writeq(0, s->sbm_rxfilter);
1650         __raw_writeq(0, s->sbm_imr);
1651
1652         /* Turn off ticker */
1653
1654         /* XXX */
1655
1656         /* turn off receiver and transmitter */
1657
1658         __raw_writeq(0, s->sbm_macenable);
1659
1660         /* We're stopped now. */
1661
1662         s->sbm_state = sbmac_state_off;
1663
1664         /*
1665          * Stop DMA channels (rings should be ok now)
1666          */
1667
1668         sbdma_channel_stop(&(s->sbm_rxdma));
1669         sbdma_channel_stop(&(s->sbm_txdma));
1670
1671         /* Empty the receive and transmit rings */
1672
1673         sbdma_emptyring(&(s->sbm_rxdma));
1674         sbdma_emptyring(&(s->sbm_txdma));
1675
1676 }
1677
1678 /**********************************************************************
1679  *  SBMAC_SET_CHANNEL_STATE(state)
1680  *
1681  *  Set the channel's state ON or OFF
1682  *
1683  *  Input parameters:
1684  *         state - new state
1685  *
1686  *  Return value:
1687  *         old state
1688  ********************************************************************* */
1689 static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *sc,
1690                                                 enum sbmac_state state)
1691 {
1692         enum sbmac_state oldstate = sc->sbm_state;
1693
1694         /*
1695          * If same as previous state, return
1696          */
1697
1698         if (state == oldstate) {
1699                 return oldstate;
1700         }
1701
1702         /*
1703          * If new state is ON, turn channel on
1704          */
1705
1706         if (state == sbmac_state_on) {
1707                 sbmac_channel_start(sc);
1708         }
1709         else {
1710                 sbmac_channel_stop(sc);
1711         }
1712
1713         /*
1714          * Return previous state
1715          */
1716
1717         return oldstate;
1718 }
1719
1720
1721 /**********************************************************************
1722  *  SBMAC_PROMISCUOUS_MODE(sc,onoff)
1723  *
1724  *  Turn on or off promiscuous mode
1725  *
1726  *  Input parameters:
1727  *         sc - softc
1728  *      onoff - 1 to turn on, 0 to turn off
1729  *
1730  *  Return value:
1731  *         nothing
1732  ********************************************************************* */
1733
1734 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1735 {
1736         uint64_t reg;
1737
1738         if (sc->sbm_state != sbmac_state_on)
1739                 return;
1740
1741         if (onoff) {
1742                 reg = __raw_readq(sc->sbm_rxfilter);
1743                 reg |= M_MAC_ALLPKT_EN;
1744                 __raw_writeq(reg, sc->sbm_rxfilter);
1745         }
1746         else {
1747                 reg = __raw_readq(sc->sbm_rxfilter);
1748                 reg &= ~M_MAC_ALLPKT_EN;
1749                 __raw_writeq(reg, sc->sbm_rxfilter);
1750         }
1751 }
1752
1753 /**********************************************************************
1754  *  SBMAC_SETIPHDR_OFFSET(sc,onoff)
1755  *
1756  *  Set the iphdr offset as 15 assuming ethernet encapsulation
1757  *
1758  *  Input parameters:
1759  *         sc - softc
1760  *
1761  *  Return value:
1762  *         nothing
1763  ********************************************************************* */
1764
1765 static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1766 {
1767         uint64_t reg;
1768
1769         /* Hard code the off set to 15 for now */
1770         reg = __raw_readq(sc->sbm_rxfilter);
1771         reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
1772         __raw_writeq(reg, sc->sbm_rxfilter);
1773
1774         /* BCM1250 pass1 didn't have hardware checksum.  Everything
1775            later does.  */
1776         if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) {
1777                 sc->rx_hw_checksum = DISABLE;
1778         } else {
1779                 sc->rx_hw_checksum = ENABLE;
1780         }
1781 }
1782
1783
1784 /**********************************************************************
1785  *  SBMAC_ADDR2REG(ptr)
1786  *
1787  *  Convert six bytes into the 64-bit register value that
1788  *  we typically write into the SBMAC's address/mcast registers
1789  *
1790  *  Input parameters:
1791  *         ptr - pointer to 6 bytes
1792  *
1793  *  Return value:
1794  *         register value
1795  ********************************************************************* */
1796
1797 static uint64_t sbmac_addr2reg(unsigned char *ptr)
1798 {
1799         uint64_t reg = 0;
1800
1801         ptr += 6;
1802
1803         reg |= (uint64_t) *(--ptr);
1804         reg <<= 8;
1805         reg |= (uint64_t) *(--ptr);
1806         reg <<= 8;
1807         reg |= (uint64_t) *(--ptr);
1808         reg <<= 8;
1809         reg |= (uint64_t) *(--ptr);
1810         reg <<= 8;
1811         reg |= (uint64_t) *(--ptr);
1812         reg <<= 8;
1813         reg |= (uint64_t) *(--ptr);
1814
1815         return reg;
1816 }
1817
1818
1819 /**********************************************************************
1820  *  SBMAC_SET_SPEED(s,speed)
1821  *
1822  *  Configure LAN speed for the specified MAC.
1823  *  Warning: must be called when MAC is off!
1824  *
1825  *  Input parameters:
1826  *         s - sbmac structure
1827  *         speed - speed to set MAC to (see enum sbmac_speed)
1828  *
1829  *  Return value:
1830  *         1 if successful
1831  *      0 indicates invalid parameters
1832  ********************************************************************* */
1833
1834 static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed)
1835 {
1836         uint64_t cfg;
1837         uint64_t framecfg;
1838
1839         /*
1840          * Save new current values
1841          */
1842
1843         s->sbm_speed = speed;
1844
1845         if (s->sbm_state == sbmac_state_on)
1846                 return 0;       /* save for next restart */
1847
1848         /*
1849          * Read current register values
1850          */
1851
1852         cfg = __raw_readq(s->sbm_maccfg);
1853         framecfg = __raw_readq(s->sbm_framecfg);
1854
1855         /*
1856          * Mask out the stuff we want to change
1857          */
1858
1859         cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
1860         framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
1861                       M_MAC_SLOT_SIZE);
1862
1863         /*
1864          * Now add in the new bits
1865          */
1866
1867         switch (speed) {
1868         case sbmac_speed_10:
1869                 framecfg |= V_MAC_IFG_RX_10 |
1870                         V_MAC_IFG_TX_10 |
1871                         K_MAC_IFG_THRSH_10 |
1872                         V_MAC_SLOT_SIZE_10;
1873                 cfg |= V_MAC_SPEED_SEL_10MBPS;
1874                 break;
1875
1876         case sbmac_speed_100:
1877                 framecfg |= V_MAC_IFG_RX_100 |
1878                         V_MAC_IFG_TX_100 |
1879                         V_MAC_IFG_THRSH_100 |
1880                         V_MAC_SLOT_SIZE_100;
1881                 cfg |= V_MAC_SPEED_SEL_100MBPS ;
1882                 break;
1883
1884         case sbmac_speed_1000:
1885                 framecfg |= V_MAC_IFG_RX_1000 |
1886                         V_MAC_IFG_TX_1000 |
1887                         V_MAC_IFG_THRSH_1000 |
1888                         V_MAC_SLOT_SIZE_1000;
1889                 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
1890                 break;
1891
1892         default:
1893                 return 0;
1894         }
1895
1896         /*
1897          * Send the bits back to the hardware
1898          */
1899
1900         __raw_writeq(framecfg, s->sbm_framecfg);
1901         __raw_writeq(cfg, s->sbm_maccfg);
1902
1903         return 1;
1904 }
1905
1906 /**********************************************************************
1907  *  SBMAC_SET_DUPLEX(s,duplex,fc)
1908  *
1909  *  Set Ethernet duplex and flow control options for this MAC
1910  *  Warning: must be called when MAC is off!
1911  *
1912  *  Input parameters:
1913  *         s - sbmac structure
1914  *         duplex - duplex setting (see enum sbmac_duplex)
1915  *         fc - flow control setting (see enum sbmac_fc)
1916  *
1917  *  Return value:
1918  *         1 if ok
1919  *         0 if an invalid parameter combination was specified
1920  ********************************************************************* */
1921
1922 static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex,
1923                             enum sbmac_fc fc)
1924 {
1925         uint64_t cfg;
1926
1927         /*
1928          * Save new current values
1929          */
1930
1931         s->sbm_duplex = duplex;
1932         s->sbm_fc = fc;
1933
1934         if (s->sbm_state == sbmac_state_on)
1935                 return 0;       /* save for next restart */
1936
1937         /*
1938          * Read current register values
1939          */
1940
1941         cfg = __raw_readq(s->sbm_maccfg);
1942
1943         /*
1944          * Mask off the stuff we're about to change
1945          */
1946
1947         cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
1948
1949
1950         switch (duplex) {
1951         case sbmac_duplex_half:
1952                 switch (fc) {
1953                 case sbmac_fc_disabled:
1954                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
1955                         break;
1956
1957                 case sbmac_fc_collision:
1958                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
1959                         break;
1960
1961                 case sbmac_fc_carrier:
1962                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
1963                         break;
1964
1965                 case sbmac_fc_frame:            /* not valid in half duplex */
1966                 default:                        /* invalid selection */
1967                         return 0;
1968                 }
1969                 break;
1970
1971         case sbmac_duplex_full:
1972                 switch (fc) {
1973                 case sbmac_fc_disabled:
1974                         cfg |= V_MAC_FC_CMD_DISABLED;
1975                         break;
1976
1977                 case sbmac_fc_frame:
1978                         cfg |= V_MAC_FC_CMD_ENABLED;
1979                         break;
1980
1981                 case sbmac_fc_collision:        /* not valid in full duplex */
1982                 case sbmac_fc_carrier:          /* not valid in full duplex */
1983                 default:
1984                         return 0;
1985                 }
1986                 break;
1987         default:
1988                 return 0;
1989         }
1990
1991         /*
1992          * Send the bits back to the hardware
1993          */
1994
1995         __raw_writeq(cfg, s->sbm_maccfg);
1996
1997         return 1;
1998 }
1999
2000
2001
2002
2003 /**********************************************************************
2004  *  SBMAC_INTR()
2005  *
2006  *  Interrupt handler for MAC interrupts
2007  *
2008  *  Input parameters:
2009  *         MAC structure
2010  *
2011  *  Return value:
2012  *         nothing
2013  ********************************************************************* */
2014 static irqreturn_t sbmac_intr(int irq,void *dev_instance)
2015 {
2016         struct net_device *dev = (struct net_device *) dev_instance;
2017         struct sbmac_softc *sc = netdev_priv(dev);
2018         uint64_t isr;
2019         int handled = 0;
2020
2021         /*
2022          * Read the ISR (this clears the bits in the real
2023          * register, except for counter addr)
2024          */
2025
2026         isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
2027
2028         if (isr == 0)
2029                 return IRQ_RETVAL(0);
2030         handled = 1;
2031
2032         /*
2033          * Transmits on channel 0
2034          */
2035
2036         if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0))
2037                 sbdma_tx_process(sc,&(sc->sbm_txdma), 0);
2038
2039         if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2040                 if (netif_rx_schedule_prep(dev, &sc->napi)) {
2041                         __raw_writeq(0, sc->sbm_imr);
2042                         __netif_rx_schedule(dev, &sc->napi);
2043                         /* Depend on the exit from poll to reenable intr */
2044                 }
2045                 else {
2046                         /* may leave some packets behind */
2047                         sbdma_rx_process(sc,&(sc->sbm_rxdma),
2048                                          SBMAC_MAX_RXDESCR * 2, 0);
2049                 }
2050         }
2051         return IRQ_RETVAL(handled);
2052 }
2053
2054 /**********************************************************************
2055  *  SBMAC_START_TX(skb,dev)
2056  *
2057  *  Start output on the specified interface.  Basically, we
2058  *  queue as many buffers as we can until the ring fills up, or
2059  *  we run off the end of the queue, whichever comes first.
2060  *
2061  *  Input parameters:
2062  *
2063  *
2064  *  Return value:
2065  *         nothing
2066  ********************************************************************* */
2067 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2068 {
2069         struct sbmac_softc *sc = netdev_priv(dev);
2070
2071         /* lock eth irq */
2072         spin_lock_irq (&sc->sbm_lock);
2073
2074         /*
2075          * Put the buffer on the transmit ring.  If we
2076          * don't have room, stop the queue.
2077          */
2078
2079         if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2080                 /* XXX save skb that we could not send */
2081                 netif_stop_queue(dev);
2082                 spin_unlock_irq(&sc->sbm_lock);
2083
2084                 return 1;
2085         }
2086
2087         dev->trans_start = jiffies;
2088
2089         spin_unlock_irq (&sc->sbm_lock);
2090
2091         return 0;
2092 }
2093
2094 /**********************************************************************
2095  *  SBMAC_SETMULTI(sc)
2096  *
2097  *  Reprogram the multicast table into the hardware, given
2098  *  the list of multicasts associated with the interface
2099  *  structure.
2100  *
2101  *  Input parameters:
2102  *         sc - softc
2103  *
2104  *  Return value:
2105  *         nothing
2106  ********************************************************************* */
2107
2108 static void sbmac_setmulti(struct sbmac_softc *sc)
2109 {
2110         uint64_t reg;
2111         void __iomem *port;
2112         int idx;
2113         struct dev_mc_list *mclist;
2114         struct net_device *dev = sc->sbm_dev;
2115
2116         /*
2117          * Clear out entire multicast table.  We do this by nuking
2118          * the entire hash table and all the direct matches except
2119          * the first one, which is used for our station address
2120          */
2121
2122         for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2123                 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
2124                 __raw_writeq(0, port);
2125         }
2126
2127         for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2128                 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
2129                 __raw_writeq(0, port);
2130         }
2131
2132         /*
2133          * Clear the filter to say we don't want any multicasts.
2134          */
2135
2136         reg = __raw_readq(sc->sbm_rxfilter);
2137         reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2138         __raw_writeq(reg, sc->sbm_rxfilter);
2139
2140         if (dev->flags & IFF_ALLMULTI) {
2141                 /*
2142                  * Enable ALL multicasts.  Do this by inverting the
2143                  * multicast enable bit.
2144                  */
2145                 reg = __raw_readq(sc->sbm_rxfilter);
2146                 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2147                 __raw_writeq(reg, sc->sbm_rxfilter);
2148                 return;
2149         }
2150
2151
2152         /*
2153          * Progam new multicast entries.  For now, only use the
2154          * perfect filter.  In the future we'll need to use the
2155          * hash filter if the perfect filter overflows
2156          */
2157
2158         /* XXX only using perfect filter for now, need to use hash
2159          * XXX if the table overflows */
2160
2161         idx = 1;                /* skip station address */
2162         mclist = dev->mc_list;
2163         while (mclist && (idx < MAC_ADDR_COUNT)) {
2164                 reg = sbmac_addr2reg(mclist->dmi_addr);
2165                 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
2166                 __raw_writeq(reg, port);
2167                 idx++;
2168                 mclist = mclist->next;
2169         }
2170
2171         /*
2172          * Enable the "accept multicast bits" if we programmed at least one
2173          * multicast.
2174          */
2175
2176         if (idx > 1) {
2177                 reg = __raw_readq(sc->sbm_rxfilter);
2178                 reg |= M_MAC_MCAST_EN;
2179                 __raw_writeq(reg, sc->sbm_rxfilter);
2180         }
2181 }
2182
2183 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
2184 /**********************************************************************
2185  *  SBMAC_PARSE_XDIGIT(str)
2186  *
2187  *  Parse a hex digit, returning its value
2188  *
2189  *  Input parameters:
2190  *         str - character
2191  *
2192  *  Return value:
2193  *         hex value, or -1 if invalid
2194  ********************************************************************* */
2195
2196 static int sbmac_parse_xdigit(char str)
2197 {
2198         int digit;
2199
2200         if ((str >= '0') && (str <= '9'))
2201                 digit = str - '0';
2202         else if ((str >= 'a') && (str <= 'f'))
2203                 digit = str - 'a' + 10;
2204         else if ((str >= 'A') && (str <= 'F'))
2205                 digit = str - 'A' + 10;
2206         else
2207                 return -1;
2208
2209         return digit;
2210 }
2211
2212 /**********************************************************************
2213  *  SBMAC_PARSE_HWADDR(str,hwaddr)
2214  *
2215  *  Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte
2216  *  Ethernet address.
2217  *
2218  *  Input parameters:
2219  *         str - string
2220  *         hwaddr - pointer to hardware address
2221  *
2222  *  Return value:
2223  *         0 if ok, else -1
2224  ********************************************************************* */
2225
2226 static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr)
2227 {
2228         int digit1,digit2;
2229         int idx = 6;
2230
2231         while (*str && (idx > 0)) {
2232                 digit1 = sbmac_parse_xdigit(*str);
2233                 if (digit1 < 0)
2234                         return -1;
2235                 str++;
2236                 if (!*str)
2237                         return -1;
2238
2239                 if ((*str == ':') || (*str == '-')) {
2240                         digit2 = digit1;
2241                         digit1 = 0;
2242                 }
2243                 else {
2244                         digit2 = sbmac_parse_xdigit(*str);
2245                         if (digit2 < 0)
2246                                 return -1;
2247                         str++;
2248                 }
2249
2250                 *hwaddr++ = (digit1 << 4) | digit2;
2251                 idx--;
2252
2253                 if (*str == '-')
2254                         str++;
2255                 if (*str == ':')
2256                         str++;
2257         }
2258         return 0;
2259 }
2260 #endif
2261
2262 static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2263 {
2264         if (new_mtu >  ENET_PACKET_SIZE)
2265                 return -EINVAL;
2266         _dev->mtu = new_mtu;
2267         pr_info("changing the mtu to %d\n", new_mtu);
2268         return 0;
2269 }
2270
2271 /**********************************************************************
2272  *  SBMAC_INIT(dev)
2273  *
2274  *  Attach routine - init hardware and hook ourselves into linux
2275  *
2276  *  Input parameters:
2277  *         dev - net_device structure
2278  *
2279  *  Return value:
2280  *         status
2281  ********************************************************************* */
2282
2283 static int sbmac_init(struct platform_device *pldev, long long base)
2284 {
2285         struct net_device *dev = pldev->dev.driver_data;
2286         int idx = pldev->id;
2287         struct sbmac_softc *sc = netdev_priv(dev);
2288         unsigned char *eaddr;
2289         uint64_t ea_reg;
2290         int i;
2291         int err;
2292         DECLARE_MAC_BUF(mac);
2293
2294         sc->sbm_dev = dev;
2295         sc->sbe_idx = idx;
2296
2297         eaddr = sc->sbm_hwaddr;
2298
2299         /*
2300          * Read the ethernet address.  The firwmare left this programmed
2301          * for us in the ethernet address register for each mac.
2302          */
2303
2304         ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR);
2305         __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR);
2306         for (i = 0; i < 6; i++) {
2307                 eaddr[i] = (uint8_t) (ea_reg & 0xFF);
2308                 ea_reg >>= 8;
2309         }
2310
2311         for (i = 0; i < 6; i++) {
2312                 dev->dev_addr[i] = eaddr[i];
2313         }
2314
2315
2316         /*
2317          * Init packet size
2318          */
2319
2320         sc->sbm_buffersize = ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN;
2321
2322         /*
2323          * Initialize context (get pointers to registers and stuff), then
2324          * allocate the memory for the descriptor tables.
2325          */
2326
2327         sbmac_initctx(sc);
2328
2329         /*
2330          * Set up Linux device callins
2331          */
2332
2333         spin_lock_init(&(sc->sbm_lock));
2334
2335         dev->open               = sbmac_open;
2336         dev->hard_start_xmit    = sbmac_start_tx;
2337         dev->stop               = sbmac_close;
2338         dev->set_multicast_list = sbmac_set_rx_mode;
2339         dev->do_ioctl           = sbmac_mii_ioctl;
2340         dev->tx_timeout         = sbmac_tx_timeout;
2341         dev->watchdog_timeo     = TX_TIMEOUT;
2342
2343         netif_napi_add(dev, &sc->napi, sbmac_poll, 16);
2344
2345         dev->change_mtu         = sb1250_change_mtu;
2346 #ifdef CONFIG_NET_POLL_CONTROLLER
2347         dev->poll_controller = sbmac_netpoll;
2348 #endif
2349
2350         dev->irq                = UNIT_INT(idx);
2351
2352         /* This is needed for PASS2 for Rx H/W checksum feature */
2353         sbmac_set_iphdr_offset(sc);
2354
2355         err = register_netdev(dev);
2356         if (err) {
2357                 printk(KERN_ERR "%s.%d: unable to register netdev\n",
2358                        sbmac_string, idx);
2359                 sbmac_uninitctx(sc);
2360                 return err;
2361         }
2362
2363         pr_info("%s.%d: registered as %s\n", sbmac_string, idx, dev->name);
2364
2365         if (sc->rx_hw_checksum == ENABLE)
2366                 pr_info("%s: enabling TCP rcv checksum\n", dev->name);
2367
2368         /*
2369          * Display Ethernet address (this is called during the config
2370          * process so we need to finish off the config message that
2371          * was being displayed)
2372          */
2373         pr_info("%s: SiByte Ethernet at 0x%08Lx, address: %s\n",
2374                dev->name, base, print_mac(mac, eaddr));
2375
2376         sc->mii_bus.name = sbmac_mdio_string;
2377         snprintf(sc->mii_bus.id, MII_BUS_ID_SIZE, "%x", idx);
2378         sc->mii_bus.priv = sc;
2379         sc->mii_bus.read = sbmac_mii_read;
2380         sc->mii_bus.write = sbmac_mii_write;
2381         sc->mii_bus.irq = sc->phy_irq;
2382         for (i = 0; i < PHY_MAX_ADDR; ++i)
2383                 sc->mii_bus.irq[i] = SBMAC_PHY_INT;
2384
2385         sc->mii_bus.dev = &pldev->dev;
2386         dev_set_drvdata(&pldev->dev, &sc->mii_bus);
2387
2388         return 0;
2389 }
2390
2391
2392 static int sbmac_open(struct net_device *dev)
2393 {
2394         struct sbmac_softc *sc = netdev_priv(dev);
2395         int err;
2396
2397         if (debug > 1)
2398                 pr_debug("%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2399
2400         /*
2401          * map/route interrupt (clear status first, in case something
2402          * weird is pending; we haven't initialized the mac registers
2403          * yet)
2404          */
2405
2406         __raw_readq(sc->sbm_isr);
2407         err = request_irq(dev->irq, &sbmac_intr, IRQF_SHARED, dev->name, dev);
2408         if (err) {
2409                 printk(KERN_ERR "%s: unable to get IRQ %d\n", dev->name,
2410                        dev->irq);
2411                 goto out_err;
2412         }
2413
2414         /*
2415          * Probe PHY address
2416          */
2417         err = mdiobus_register(&sc->mii_bus);
2418         if (err) {
2419                 printk(KERN_ERR "%s: unable to register MDIO bus\n",
2420                        dev->name);
2421                 goto out_unirq;
2422         }
2423
2424         sc->sbm_speed = sbmac_speed_none;
2425         sc->sbm_duplex = sbmac_duplex_none;
2426         sc->sbm_fc = sbmac_fc_none;
2427         sc->sbm_pause = -1;
2428         sc->sbm_link = 0;
2429
2430         /*
2431          * Attach to the PHY
2432          */
2433         err = sbmac_mii_probe(dev);
2434         if (err)
2435                 goto out_unregister;
2436
2437         /*
2438          * Turn on the channel
2439          */
2440
2441         sbmac_set_channel_state(sc,sbmac_state_on);
2442
2443         netif_start_queue(dev);
2444
2445         sbmac_set_rx_mode(dev);
2446
2447         phy_start(sc->phy_dev);
2448
2449         napi_enable(&sc->napi);
2450
2451         return 0;
2452
2453 out_unregister:
2454         mdiobus_unregister(&sc->mii_bus);
2455
2456 out_unirq:
2457         free_irq(dev->irq, dev);
2458
2459 out_err:
2460         return err;
2461 }
2462
2463 static int sbmac_mii_probe(struct net_device *dev)
2464 {
2465         struct sbmac_softc *sc = netdev_priv(dev);
2466         struct phy_device *phy_dev;
2467         int i;
2468
2469         for (i = 0; i < PHY_MAX_ADDR; i++) {
2470                 phy_dev = sc->mii_bus.phy_map[i];
2471                 if (phy_dev)
2472                         break;
2473         }
2474         if (!phy_dev) {
2475                 printk(KERN_ERR "%s: no PHY found\n", dev->name);
2476                 return -ENXIO;
2477         }
2478
2479         phy_dev = phy_connect(dev, phy_dev->dev.bus_id, &sbmac_mii_poll, 0,
2480                               PHY_INTERFACE_MODE_GMII);
2481         if (IS_ERR(phy_dev)) {
2482                 printk(KERN_ERR "%s: could not attach to PHY\n", dev->name);
2483                 return PTR_ERR(phy_dev);
2484         }
2485
2486         /* Remove any features not supported by the controller */
2487         phy_dev->supported &= SUPPORTED_10baseT_Half |
2488                               SUPPORTED_10baseT_Full |
2489                               SUPPORTED_100baseT_Half |
2490                               SUPPORTED_100baseT_Full |
2491                               SUPPORTED_1000baseT_Half |
2492                               SUPPORTED_1000baseT_Full |
2493                               SUPPORTED_Autoneg |
2494                               SUPPORTED_MII |
2495                               SUPPORTED_Pause |
2496                               SUPPORTED_Asym_Pause;
2497         phy_dev->advertising = phy_dev->supported;
2498
2499         pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
2500                 dev->name, phy_dev->drv->name,
2501                 phy_dev->dev.bus_id, phy_dev->irq);
2502
2503         sc->phy_dev = phy_dev;
2504
2505         return 0;
2506 }
2507
2508
2509 static void sbmac_mii_poll(struct net_device *dev)
2510 {
2511         struct sbmac_softc *sc = netdev_priv(dev);
2512         struct phy_device *phy_dev = sc->phy_dev;
2513         unsigned long flags;
2514         enum sbmac_fc fc;
2515         int link_chg, speed_chg, duplex_chg, pause_chg, fc_chg;
2516
2517         link_chg = (sc->sbm_link != phy_dev->link);
2518         speed_chg = (sc->sbm_speed != phy_dev->speed);
2519         duplex_chg = (sc->sbm_duplex != phy_dev->duplex);
2520         pause_chg = (sc->sbm_pause != phy_dev->pause);
2521
2522         if (!link_chg && !speed_chg && !duplex_chg && !pause_chg)
2523                 return;                                 /* Hmmm... */
2524
2525         if (!phy_dev->link) {
2526                 if (link_chg) {
2527                         sc->sbm_link = phy_dev->link;
2528                         sc->sbm_speed = sbmac_speed_none;
2529                         sc->sbm_duplex = sbmac_duplex_none;
2530                         sc->sbm_fc = sbmac_fc_disabled;
2531                         sc->sbm_pause = -1;
2532                         pr_info("%s: link unavailable\n", dev->name);
2533                 }
2534                 return;
2535         }
2536
2537         if (phy_dev->duplex == DUPLEX_FULL) {
2538                 if (phy_dev->pause)
2539                         fc = sbmac_fc_frame;
2540                 else
2541                         fc = sbmac_fc_disabled;
2542         } else
2543                 fc = sbmac_fc_collision;
2544         fc_chg = (sc->sbm_fc != fc);
2545
2546         pr_info("%s: link available: %dbase-%cD\n", dev->name, phy_dev->speed,
2547                 phy_dev->duplex == DUPLEX_FULL ? 'F' : 'H');
2548
2549         spin_lock_irqsave(&sc->sbm_lock, flags);
2550
2551         sc->sbm_speed = phy_dev->speed;
2552         sc->sbm_duplex = phy_dev->duplex;
2553         sc->sbm_fc = fc;
2554         sc->sbm_pause = phy_dev->pause;
2555         sc->sbm_link = phy_dev->link;
2556
2557         if ((speed_chg || duplex_chg || fc_chg) &&
2558             sc->sbm_state != sbmac_state_off) {
2559                 /*
2560                  * something changed, restart the channel
2561                  */
2562                 if (debug > 1)
2563                         pr_debug("%s: restarting channel "
2564                                  "because PHY state changed\n", dev->name);
2565                 sbmac_channel_stop(sc);
2566                 sbmac_channel_start(sc);
2567         }
2568
2569         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2570 }
2571
2572
2573 static void sbmac_tx_timeout (struct net_device *dev)
2574 {
2575         struct sbmac_softc *sc = netdev_priv(dev);
2576
2577         spin_lock_irq (&sc->sbm_lock);
2578
2579
2580         dev->trans_start = jiffies;
2581         dev->stats.tx_errors++;
2582
2583         spin_unlock_irq (&sc->sbm_lock);
2584
2585         printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
2586 }
2587
2588
2589
2590
2591 static void sbmac_set_rx_mode(struct net_device *dev)
2592 {
2593         unsigned long flags;
2594         struct sbmac_softc *sc = netdev_priv(dev);
2595
2596         spin_lock_irqsave(&sc->sbm_lock, flags);
2597         if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
2598                 /*
2599                  * Promiscuous changed.
2600                  */
2601
2602                 if (dev->flags & IFF_PROMISC) {
2603                         sbmac_promiscuous_mode(sc,1);
2604                 }
2605                 else {
2606                         sbmac_promiscuous_mode(sc,0);
2607                 }
2608         }
2609         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2610
2611         /*
2612          * Program the multicasts.  Do this every time.
2613          */
2614
2615         sbmac_setmulti(sc);
2616
2617 }
2618
2619 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2620 {
2621         struct sbmac_softc *sc = netdev_priv(dev);
2622
2623         if (!netif_running(dev) || !sc->phy_dev)
2624                 return -EINVAL;
2625
2626         return phy_mii_ioctl(sc->phy_dev, if_mii(rq), cmd);
2627 }
2628
2629 static int sbmac_close(struct net_device *dev)
2630 {
2631         struct sbmac_softc *sc = netdev_priv(dev);
2632
2633         napi_disable(&sc->napi);
2634
2635         phy_stop(sc->phy_dev);
2636
2637         sbmac_set_channel_state(sc, sbmac_state_off);
2638
2639         netif_stop_queue(dev);
2640
2641         if (debug > 1)
2642                 pr_debug("%s: Shutting down ethercard\n", dev->name);
2643
2644         phy_disconnect(sc->phy_dev);
2645         sc->phy_dev = NULL;
2646
2647         mdiobus_unregister(&sc->mii_bus);
2648
2649         free_irq(dev->irq, dev);
2650
2651         sbdma_emptyring(&(sc->sbm_txdma));
2652         sbdma_emptyring(&(sc->sbm_rxdma));
2653
2654         return 0;
2655 }
2656
2657 static int sbmac_poll(struct napi_struct *napi, int budget)
2658 {
2659         struct sbmac_softc *sc = container_of(napi, struct sbmac_softc, napi);
2660         struct net_device *dev = sc->sbm_dev;
2661         int work_done;
2662
2663         work_done = sbdma_rx_process(sc, &(sc->sbm_rxdma), budget, 1);
2664         sbdma_tx_process(sc, &(sc->sbm_txdma), 1);
2665
2666         if (work_done < budget) {
2667                 netif_rx_complete(dev, napi);
2668
2669 #ifdef CONFIG_SBMAC_COALESCE
2670                 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
2671                              ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
2672                              sc->sbm_imr);
2673 #else
2674                 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
2675                              (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
2676 #endif
2677         }
2678
2679         return work_done;
2680 }
2681
2682
2683 static int __init sbmac_probe(struct platform_device *pldev)
2684 {
2685         struct net_device *dev;
2686         struct sbmac_softc *sc;
2687         void __iomem *sbm_base;
2688         struct resource *res;
2689         u64 sbmac_orig_hwaddr;
2690         int err;
2691
2692         res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
2693         BUG_ON(!res);
2694         sbm_base = ioremap_nocache(res->start, res->end - res->start + 1);
2695         if (!sbm_base) {
2696                 printk(KERN_ERR "%s: unable to map device registers\n",
2697                        pldev->dev.bus_id);
2698                 err = -ENOMEM;
2699                 goto out_out;
2700         }
2701
2702         /*
2703          * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2704          * value for us by the firmware if we're going to use this MAC.
2705          * If we find a zero, skip this MAC.
2706          */
2707         sbmac_orig_hwaddr = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR);
2708         pr_debug("%s: %sconfiguring MAC at 0x%08Lx\n", pldev->dev.bus_id,
2709                  sbmac_orig_hwaddr ? "" : "not ", (long long)res->start);
2710         if (sbmac_orig_hwaddr == 0) {
2711                 err = 0;
2712                 goto out_unmap;
2713         }
2714
2715         /*
2716          * Okay, cool.  Initialize this MAC.
2717          */
2718         dev = alloc_etherdev(sizeof(struct sbmac_softc));
2719         if (!dev) {
2720                 printk(KERN_ERR "%s: unable to allocate etherdev\n",
2721                        pldev->dev.bus_id);
2722                 err = -ENOMEM;
2723                 goto out_unmap;
2724         }
2725
2726         pldev->dev.driver_data = dev;
2727         SET_NETDEV_DEV(dev, &pldev->dev);
2728
2729         sc = netdev_priv(dev);
2730         sc->sbm_base = sbm_base;
2731
2732         err = sbmac_init(pldev, res->start);
2733         if (err)
2734                 goto out_kfree;
2735
2736         return 0;
2737
2738 out_kfree:
2739         free_netdev(dev);
2740         __raw_writeq(sbmac_orig_hwaddr, sbm_base + R_MAC_ETHERNET_ADDR);
2741
2742 out_unmap:
2743         iounmap(sbm_base);
2744
2745 out_out:
2746         return err;
2747 }
2748
2749 static int __exit sbmac_remove(struct platform_device *pldev)
2750 {
2751         struct net_device *dev = pldev->dev.driver_data;
2752         struct sbmac_softc *sc = netdev_priv(dev);
2753
2754         unregister_netdev(dev);
2755         sbmac_uninitctx(sc);
2756         iounmap(sc->sbm_base);
2757         free_netdev(dev);
2758
2759         return 0;
2760 }
2761
2762
2763 static struct platform_device **sbmac_pldev;
2764 static int sbmac_max_units;
2765
2766 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
2767 static void __init sbmac_setup_hwaddr(int idx, char *addr)
2768 {
2769         void __iomem *sbm_base;
2770         unsigned long start, end;
2771         uint8_t eaddr[6];
2772         uint64_t val;
2773
2774         if (idx >= sbmac_max_units)
2775                 return;
2776
2777         start = A_MAC_CHANNEL_BASE(idx);
2778         end = A_MAC_CHANNEL_BASE(idx + 1) - 1;
2779
2780         sbm_base = ioremap_nocache(start, end - start + 1);
2781         if (!sbm_base) {
2782                 printk(KERN_ERR "%s: unable to map device registers\n",
2783                        sbmac_string);
2784                 return;
2785         }
2786
2787         sbmac_parse_hwaddr(addr, eaddr);
2788         val = sbmac_addr2reg(eaddr);
2789         __raw_writeq(val, sbm_base + R_MAC_ETHERNET_ADDR);
2790         val = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR);
2791
2792         iounmap(sbm_base);
2793 }
2794 #endif
2795
2796 static int __init sbmac_platform_probe_one(int idx)
2797 {
2798         struct platform_device *pldev;
2799         struct {
2800                 struct resource r;
2801                 char name[strlen(sbmac_pretty) + 4];
2802         } *res;
2803         int err;
2804
2805         res = kzalloc(sizeof(*res), GFP_KERNEL);
2806         if (!res) {
2807                 printk(KERN_ERR "%s.%d: unable to allocate memory\n",
2808                        sbmac_string, idx);
2809                 err = -ENOMEM;
2810                 goto out_err;
2811         }
2812
2813         /*
2814          * This is the base address of the MAC.
2815          */
2816         snprintf(res->name, sizeof(res->name), "%s %d", sbmac_pretty, idx);
2817         res->r.name = res->name;
2818         res->r.flags = IORESOURCE_MEM;
2819         res->r.start = A_MAC_CHANNEL_BASE(idx);
2820         res->r.end = A_MAC_CHANNEL_BASE(idx + 1) - 1;
2821
2822         pldev = platform_device_register_simple(sbmac_string, idx, &res->r, 1);
2823         if (IS_ERR(pldev)) {
2824                 printk(KERN_ERR "%s.%d: unable to register platform device\n",
2825                        sbmac_string, idx);
2826                 err = PTR_ERR(pldev);
2827                 goto out_kfree;
2828         }
2829
2830         if (!pldev->dev.driver) {
2831                 err = 0;                /* No hardware at this address. */
2832                 goto out_unregister;
2833         }
2834
2835         sbmac_pldev[idx] = pldev;
2836         return 0;
2837
2838 out_unregister:
2839         platform_device_unregister(pldev);
2840
2841 out_kfree:
2842         kfree(res);
2843
2844 out_err:
2845         return err;
2846 }
2847
2848 static void __init sbmac_platform_probe(void)
2849 {
2850         int i;
2851
2852         /* Set the number of available units based on the SOC type.  */
2853         switch (soc_type) {
2854         case K_SYS_SOC_TYPE_BCM1250:
2855         case K_SYS_SOC_TYPE_BCM1250_ALT:
2856                 sbmac_max_units = 3;
2857                 break;
2858         case K_SYS_SOC_TYPE_BCM1120:
2859         case K_SYS_SOC_TYPE_BCM1125:
2860         case K_SYS_SOC_TYPE_BCM1125H:
2861         case K_SYS_SOC_TYPE_BCM1250_ALT2:       /* Hybrid */
2862                 sbmac_max_units = 2;
2863                 break;
2864         case K_SYS_SOC_TYPE_BCM1x55:
2865         case K_SYS_SOC_TYPE_BCM1x80:
2866                 sbmac_max_units = 4;
2867                 break;
2868         default:
2869                 return;                         /* none */
2870         }
2871
2872         /*
2873          * For bringup when not using the firmware, we can pre-fill
2874          * the MAC addresses using the environment variables
2875          * specified in this file (or maybe from the config file?)
2876          */
2877 #ifdef SBMAC_ETH0_HWADDR
2878         sbmac_setup_hwaddr(0, SBMAC_ETH0_HWADDR);
2879 #endif
2880 #ifdef SBMAC_ETH1_HWADDR
2881         sbmac_setup_hwaddr(1, SBMAC_ETH1_HWADDR);
2882 #endif
2883 #ifdef SBMAC_ETH2_HWADDR
2884         sbmac_setup_hwaddr(2, SBMAC_ETH2_HWADDR);
2885 #endif
2886 #ifdef SBMAC_ETH3_HWADDR
2887         sbmac_setup_hwaddr(3, SBMAC_ETH3_HWADDR);
2888 #endif
2889
2890         sbmac_pldev = kcalloc(sbmac_max_units, sizeof(*sbmac_pldev),
2891                               GFP_KERNEL);
2892         if (!sbmac_pldev) {
2893                 printk(KERN_ERR "%s: unable to allocate memory\n",
2894                        sbmac_string);
2895                 return;
2896         }
2897
2898         /*
2899          * Walk through the Ethernet controllers and find
2900          * those who have their MAC addresses set.
2901          */
2902         for (i = 0; i < sbmac_max_units; i++)
2903                 if (sbmac_platform_probe_one(i))
2904                         break;
2905 }
2906
2907
2908 static void __exit sbmac_platform_cleanup(void)
2909 {
2910         int i;
2911
2912         for (i = 0; i < sbmac_max_units; i++)
2913                 platform_device_unregister(sbmac_pldev[i]);
2914         kfree(sbmac_pldev);
2915 }
2916
2917
2918 static struct platform_driver sbmac_driver = {
2919         .probe = sbmac_probe,
2920         .remove = __exit_p(sbmac_remove),
2921         .driver = {
2922                 .name = sbmac_string,
2923         },
2924 };
2925
2926 static int __init sbmac_init_module(void)
2927 {
2928         int err;
2929
2930         err = platform_driver_register(&sbmac_driver);
2931         if (err)
2932                 return err;
2933
2934         sbmac_platform_probe();
2935
2936         return err;
2937 }
2938
2939 static void __exit sbmac_cleanup_module(void)
2940 {
2941         sbmac_platform_cleanup();
2942         platform_driver_unregister(&sbmac_driver);
2943 }
2944
2945 module_init(sbmac_init_module);
2946 module_exit(sbmac_cleanup_module);