[ETH]: Make eth_type_trans set skb->dev like the other *_type_trans
[linux-2.6.git] / drivers / net / sb1250-mac.c
1 /*
2  * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * as published by the Free Software Foundation; either version 2
7  * of the License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
17  *
18  *
19  * This driver is designed for the Broadcom SiByte SOC built-in
20  * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp.
21  */
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/timer.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/init.h>
34 #include <linux/bitops.h>
35 #include <asm/processor.h>              /* Processor type for cache alignment. */
36 #include <asm/io.h>
37 #include <asm/cache.h>
38
39 /* This is only here until the firmware is ready.  In that case,
40    the firmware leaves the ethernet address in the register for us. */
41 #ifdef CONFIG_SIBYTE_STANDALONE
42 #define SBMAC_ETH0_HWADDR "40:00:00:00:01:00"
43 #define SBMAC_ETH1_HWADDR "40:00:00:00:01:01"
44 #define SBMAC_ETH2_HWADDR "40:00:00:00:01:02"
45 #define SBMAC_ETH3_HWADDR "40:00:00:00:01:03"
46 #endif
47
48
49 /* These identify the driver base version and may not be removed. */
50 #if 0
51 static char version1[] __devinitdata =
52 "sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n";
53 #endif
54
55
56 /* Operational parameters that usually are not changed. */
57
58 #define CONFIG_SBMAC_COALESCE
59
60 #define MAX_UNITS 4             /* More are supported, limit only on options */
61
62 /* Time in jiffies before concluding the transmitter is hung. */
63 #define TX_TIMEOUT  (2*HZ)
64
65
66 MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
67 MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
68
69 /* A few user-configurable values which may be modified when a driver
70    module is loaded. */
71
72 /* 1 normal messages, 0 quiet .. 7 verbose. */
73 static int debug = 1;
74 module_param(debug, int, S_IRUGO);
75 MODULE_PARM_DESC(debug, "Debug messages");
76
77 /* mii status msgs */
78 static int noisy_mii = 1;
79 module_param(noisy_mii, int, S_IRUGO);
80 MODULE_PARM_DESC(noisy_mii, "MII status messages");
81
82 /* Used to pass the media type, etc.
83    Both 'options[]' and 'full_duplex[]' should exist for driver
84    interoperability.
85    The media type is usually passed in 'options[]'.
86 */
87 #ifdef MODULE
88 static int options[MAX_UNITS] = {-1, -1, -1, -1};
89 module_param_array(options, int, NULL, S_IRUGO);
90 MODULE_PARM_DESC(options, "1-" __MODULE_STRING(MAX_UNITS));
91
92 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1};
93 module_param_array(full_duplex, int, NULL, S_IRUGO);
94 MODULE_PARM_DESC(full_duplex, "1-" __MODULE_STRING(MAX_UNITS));
95 #endif
96
97 #ifdef CONFIG_SBMAC_COALESCE
98 static int int_pktcnt = 0;
99 module_param(int_pktcnt, int, S_IRUGO);
100 MODULE_PARM_DESC(int_pktcnt, "Packet count");
101
102 static int int_timeout = 0;
103 module_param(int_timeout, int, S_IRUGO);
104 MODULE_PARM_DESC(int_timeout, "Timeout value");
105 #endif
106
107 #include <asm/sibyte/sb1250.h>
108 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
109 #include <asm/sibyte/bcm1480_regs.h>
110 #include <asm/sibyte/bcm1480_int.h>
111 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
112 #include <asm/sibyte/sb1250_regs.h>
113 #include <asm/sibyte/sb1250_int.h>
114 #else
115 #error invalid SiByte MAC configuation
116 #endif
117 #include <asm/sibyte/sb1250_scd.h>
118 #include <asm/sibyte/sb1250_mac.h>
119 #include <asm/sibyte/sb1250_dma.h>
120
121 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
122 #define UNIT_INT(n)             (K_BCM1480_INT_MAC_0 + ((n) * 2))
123 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
124 #define UNIT_INT(n)             (K_INT_MAC_0 + (n))
125 #else
126 #error invalid SiByte MAC configuation
127 #endif
128
129 /**********************************************************************
130  *  Simple types
131  ********************************************************************* */
132
133
134 typedef enum { sbmac_speed_auto, sbmac_speed_10,
135                sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t;
136
137 typedef enum { sbmac_duplex_auto, sbmac_duplex_half,
138                sbmac_duplex_full } sbmac_duplex_t;
139
140 typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame,
141                sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t;
142
143 typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on,
144                sbmac_state_broken } sbmac_state_t;
145
146
147 /**********************************************************************
148  *  Macros
149  ********************************************************************* */
150
151
152 #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
153                           (d)->sbdma_dscrtable : (d)->f+1)
154
155
156 #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
157
158 #define SBMAC_MAX_TXDESCR       32
159 #define SBMAC_MAX_RXDESCR       32
160
161 #define ETHER_ALIGN     2
162 #define ETHER_ADDR_LEN  6
163 #define ENET_PACKET_SIZE        1518
164 /*#define ENET_PACKET_SIZE      9216 */
165
166 /**********************************************************************
167  *  DMA Descriptor structure
168  ********************************************************************* */
169
170 typedef struct sbdmadscr_s {
171         uint64_t  dscr_a;
172         uint64_t  dscr_b;
173 } sbdmadscr_t;
174
175 typedef unsigned long paddr_t;
176
177 /**********************************************************************
178  *  DMA Controller structure
179  ********************************************************************* */
180
181 typedef struct sbmacdma_s {
182
183         /*
184          * This stuff is used to identify the channel and the registers
185          * associated with it.
186          */
187
188         struct sbmac_softc *sbdma_eth;          /* back pointer to associated MAC */
189         int              sbdma_channel; /* channel number */
190         int              sbdma_txdir;       /* direction (1=transmit) */
191         int              sbdma_maxdescr;        /* total # of descriptors in ring */
192 #ifdef CONFIG_SBMAC_COALESCE
193         int              sbdma_int_pktcnt;  /* # descriptors rx/tx before interrupt*/
194         int              sbdma_int_timeout; /* # usec rx/tx interrupt */
195 #endif
196
197         volatile void __iomem *sbdma_config0;   /* DMA config register 0 */
198         volatile void __iomem *sbdma_config1;   /* DMA config register 1 */
199         volatile void __iomem *sbdma_dscrbase;  /* Descriptor base address */
200         volatile void __iomem *sbdma_dscrcnt;     /* Descriptor count register */
201         volatile void __iomem *sbdma_curdscr;   /* current descriptor address */
202
203         /*
204          * This stuff is for maintenance of the ring
205          */
206
207         sbdmadscr_t     *sbdma_dscrtable;       /* base of descriptor table */
208         sbdmadscr_t     *sbdma_dscrtable_end; /* end of descriptor table */
209
210         struct sk_buff **sbdma_ctxtable;    /* context table, one per descr */
211
212         paddr_t          sbdma_dscrtable_phys; /* and also the phys addr */
213         sbdmadscr_t     *sbdma_addptr;  /* next dscr for sw to add */
214         sbdmadscr_t     *sbdma_remptr;  /* next dscr for sw to remove */
215 } sbmacdma_t;
216
217
218 /**********************************************************************
219  *  Ethernet softc structure
220  ********************************************************************* */
221
222 struct sbmac_softc {
223
224         /*
225          * Linux-specific things
226          */
227
228         struct net_device *sbm_dev;             /* pointer to linux device */
229         spinlock_t sbm_lock;            /* spin lock */
230         struct timer_list sbm_timer;            /* for monitoring MII */
231         struct net_device_stats sbm_stats;
232         int sbm_devflags;                       /* current device flags */
233
234         int          sbm_phy_oldbmsr;
235         int          sbm_phy_oldanlpar;
236         int          sbm_phy_oldk1stsr;
237         int          sbm_phy_oldlinkstat;
238         int sbm_buffersize;
239
240         unsigned char sbm_phys[2];
241
242         /*
243          * Controller-specific things
244          */
245
246         void __iomem            *sbm_base;          /* MAC's base address */
247         sbmac_state_t    sbm_state;         /* current state */
248
249         volatile void __iomem   *sbm_macenable; /* MAC Enable Register */
250         volatile void __iomem   *sbm_maccfg;    /* MAC Configuration Register */
251         volatile void __iomem   *sbm_fifocfg;   /* FIFO configuration register */
252         volatile void __iomem   *sbm_framecfg;  /* Frame configuration register */
253         volatile void __iomem   *sbm_rxfilter;  /* receive filter register */
254         volatile void __iomem   *sbm_isr;       /* Interrupt status register */
255         volatile void __iomem   *sbm_imr;       /* Interrupt mask register */
256         volatile void __iomem   *sbm_mdio;      /* MDIO register */
257
258         sbmac_speed_t    sbm_speed;             /* current speed */
259         sbmac_duplex_t   sbm_duplex;    /* current duplex */
260         sbmac_fc_t       sbm_fc;                /* current flow control setting */
261
262         unsigned char    sbm_hwaddr[ETHER_ADDR_LEN];
263
264         sbmacdma_t       sbm_txdma;             /* for now, only use channel 0 */
265         sbmacdma_t       sbm_rxdma;
266         int              rx_hw_checksum;
267         int              sbe_idx;
268 };
269
270
271 /**********************************************************************
272  *  Externs
273  ********************************************************************* */
274
275 /**********************************************************************
276  *  Prototypes
277  ********************************************************************* */
278
279 static void sbdma_initctx(sbmacdma_t *d,
280                           struct sbmac_softc *s,
281                           int chan,
282                           int txrx,
283                           int maxdescr);
284 static void sbdma_channel_start(sbmacdma_t *d, int rxtx);
285 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *m);
286 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *m);
287 static void sbdma_emptyring(sbmacdma_t *d);
288 static void sbdma_fillring(sbmacdma_t *d);
289 static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d);
290 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d);
291 static int sbmac_initctx(struct sbmac_softc *s);
292 static void sbmac_channel_start(struct sbmac_softc *s);
293 static void sbmac_channel_stop(struct sbmac_softc *s);
294 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *,sbmac_state_t);
295 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff);
296 static uint64_t sbmac_addr2reg(unsigned char *ptr);
297 static irqreturn_t sbmac_intr(int irq,void *dev_instance);
298 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
299 static void sbmac_setmulti(struct sbmac_softc *sc);
300 static int sbmac_init(struct net_device *dev, int idx);
301 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed);
302 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc);
303
304 static int sbmac_open(struct net_device *dev);
305 static void sbmac_timer(unsigned long data);
306 static void sbmac_tx_timeout (struct net_device *dev);
307 static struct net_device_stats *sbmac_get_stats(struct net_device *dev);
308 static void sbmac_set_rx_mode(struct net_device *dev);
309 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
310 static int sbmac_close(struct net_device *dev);
311 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy);
312 static int sbmac_mii_probe(struct net_device *dev);
313
314 static void sbmac_mii_sync(struct sbmac_softc *s);
315 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt);
316 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx);
317 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
318                             unsigned int regval);
319
320
321 /**********************************************************************
322  *  Globals
323  ********************************************************************* */
324
325 static uint64_t sbmac_orig_hwaddr[MAX_UNITS];
326
327
328 /**********************************************************************
329  *  MDIO constants
330  ********************************************************************* */
331
332 #define MII_COMMAND_START       0x01
333 #define MII_COMMAND_READ        0x02
334 #define MII_COMMAND_WRITE       0x01
335 #define MII_COMMAND_ACK         0x02
336
337 #define BMCR_RESET     0x8000
338 #define BMCR_LOOPBACK  0x4000
339 #define BMCR_SPEED0    0x2000
340 #define BMCR_ANENABLE  0x1000
341 #define BMCR_POWERDOWN 0x0800
342 #define BMCR_ISOLATE   0x0400
343 #define BMCR_RESTARTAN 0x0200
344 #define BMCR_DUPLEX    0x0100
345 #define BMCR_COLTEST   0x0080
346 #define BMCR_SPEED1    0x0040
347 #define BMCR_SPEED1000  BMCR_SPEED1
348 #define BMCR_SPEED100   BMCR_SPEED0
349 #define BMCR_SPEED10    0
350
351 #define BMSR_100BT4     0x8000
352 #define BMSR_100BT_FDX  0x4000
353 #define BMSR_100BT_HDX  0x2000
354 #define BMSR_10BT_FDX   0x1000
355 #define BMSR_10BT_HDX   0x0800
356 #define BMSR_100BT2_FDX 0x0400
357 #define BMSR_100BT2_HDX 0x0200
358 #define BMSR_1000BT_XSR 0x0100
359 #define BMSR_PRESUP     0x0040
360 #define BMSR_ANCOMPLT   0x0020
361 #define BMSR_REMFAULT   0x0010
362 #define BMSR_AUTONEG    0x0008
363 #define BMSR_LINKSTAT   0x0004
364 #define BMSR_JABDETECT  0x0002
365 #define BMSR_EXTCAPAB   0x0001
366
367 #define PHYIDR1         0x2000
368 #define PHYIDR2         0x5C60
369
370 #define ANAR_NP         0x8000
371 #define ANAR_RF         0x2000
372 #define ANAR_ASYPAUSE   0x0800
373 #define ANAR_PAUSE      0x0400
374 #define ANAR_T4         0x0200
375 #define ANAR_TXFD       0x0100
376 #define ANAR_TXHD       0x0080
377 #define ANAR_10FD       0x0040
378 #define ANAR_10HD       0x0020
379 #define ANAR_PSB        0x0001
380
381 #define ANLPAR_NP       0x8000
382 #define ANLPAR_ACK      0x4000
383 #define ANLPAR_RF       0x2000
384 #define ANLPAR_ASYPAUSE 0x0800
385 #define ANLPAR_PAUSE    0x0400
386 #define ANLPAR_T4       0x0200
387 #define ANLPAR_TXFD     0x0100
388 #define ANLPAR_TXHD     0x0080
389 #define ANLPAR_10FD     0x0040
390 #define ANLPAR_10HD     0x0020
391 #define ANLPAR_PSB      0x0001  /* 802.3 */
392
393 #define ANER_PDF        0x0010
394 #define ANER_LPNPABLE   0x0008
395 #define ANER_NPABLE     0x0004
396 #define ANER_PAGERX     0x0002
397 #define ANER_LPANABLE   0x0001
398
399 #define ANNPTR_NP       0x8000
400 #define ANNPTR_MP       0x2000
401 #define ANNPTR_ACK2     0x1000
402 #define ANNPTR_TOGTX    0x0800
403 #define ANNPTR_CODE     0x0008
404
405 #define ANNPRR_NP       0x8000
406 #define ANNPRR_MP       0x2000
407 #define ANNPRR_ACK3     0x1000
408 #define ANNPRR_TOGTX    0x0800
409 #define ANNPRR_CODE     0x0008
410
411 #define K1TCR_TESTMODE  0x0000
412 #define K1TCR_MSMCE     0x1000
413 #define K1TCR_MSCV      0x0800
414 #define K1TCR_RPTR      0x0400
415 #define K1TCR_1000BT_FDX 0x200
416 #define K1TCR_1000BT_HDX 0x100
417
418 #define K1STSR_MSMCFLT  0x8000
419 #define K1STSR_MSCFGRES 0x4000
420 #define K1STSR_LRSTAT   0x2000
421 #define K1STSR_RRSTAT   0x1000
422 #define K1STSR_LP1KFD   0x0800
423 #define K1STSR_LP1KHD   0x0400
424 #define K1STSR_LPASMDIR 0x0200
425
426 #define K1SCR_1KX_FDX   0x8000
427 #define K1SCR_1KX_HDX   0x4000
428 #define K1SCR_1KT_FDX   0x2000
429 #define K1SCR_1KT_HDX   0x1000
430
431 #define STRAP_PHY1      0x0800
432 #define STRAP_NCMODE    0x0400
433 #define STRAP_MANMSCFG  0x0200
434 #define STRAP_ANENABLE  0x0100
435 #define STRAP_MSVAL     0x0080
436 #define STRAP_1KHDXADV  0x0010
437 #define STRAP_1KFDXADV  0x0008
438 #define STRAP_100ADV    0x0004
439 #define STRAP_SPEEDSEL  0x0000
440 #define STRAP_SPEED100  0x0001
441
442 #define PHYSUP_SPEED1000 0x10
443 #define PHYSUP_SPEED100  0x08
444 #define PHYSUP_SPEED10   0x00
445 #define PHYSUP_LINKUP    0x04
446 #define PHYSUP_FDX       0x02
447
448 #define MII_BMCR        0x00    /* Basic mode control register (rw) */
449 #define MII_BMSR        0x01    /* Basic mode status register (ro) */
450 #define MII_PHYIDR1     0x02
451 #define MII_PHYIDR2     0x03
452
453 #define MII_K1STSR      0x0A    /* 1K Status Register (ro) */
454 #define MII_ANLPAR      0x05    /* Autonegotiation lnk partner abilities (rw) */
455
456
457 #define M_MAC_MDIO_DIR_OUTPUT   0               /* for clarity */
458
459 #define ENABLE          1
460 #define DISABLE         0
461
462 /**********************************************************************
463  *  SBMAC_MII_SYNC(s)
464  *
465  *  Synchronize with the MII - send a pattern of bits to the MII
466  *  that will guarantee that it is ready to accept a command.
467  *
468  *  Input parameters:
469  *         s - sbmac structure
470  *
471  *  Return value:
472  *         nothing
473  ********************************************************************* */
474
475 static void sbmac_mii_sync(struct sbmac_softc *s)
476 {
477         int cnt;
478         uint64_t bits;
479         int mac_mdio_genc;
480
481         mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
482
483         bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
484
485         __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
486
487         for (cnt = 0; cnt < 32; cnt++) {
488                 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
489                 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
490         }
491 }
492
493 /**********************************************************************
494  *  SBMAC_MII_SENDDATA(s,data,bitcnt)
495  *
496  *  Send some bits to the MII.  The bits to be sent are right-
497  *  justified in the 'data' parameter.
498  *
499  *  Input parameters:
500  *         s - sbmac structure
501  *         data - data to send
502  *         bitcnt - number of bits to send
503  ********************************************************************* */
504
505 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt)
506 {
507         int i;
508         uint64_t bits;
509         unsigned int curmask;
510         int mac_mdio_genc;
511
512         mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
513
514         bits = M_MAC_MDIO_DIR_OUTPUT;
515         __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
516
517         curmask = 1 << (bitcnt - 1);
518
519         for (i = 0; i < bitcnt; i++) {
520                 if (data & curmask)
521                         bits |= M_MAC_MDIO_OUT;
522                 else bits &= ~M_MAC_MDIO_OUT;
523                 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
524                 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
525                 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
526                 curmask >>= 1;
527         }
528 }
529
530
531
532 /**********************************************************************
533  *  SBMAC_MII_READ(s,phyaddr,regidx)
534  *
535  *  Read a PHY register.
536  *
537  *  Input parameters:
538  *         s - sbmac structure
539  *         phyaddr - PHY's address
540  *         regidx = index of register to read
541  *
542  *  Return value:
543  *         value read, or 0 if an error occurred.
544  ********************************************************************* */
545
546 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx)
547 {
548         int idx;
549         int error;
550         int regval;
551         int mac_mdio_genc;
552
553         /*
554          * Synchronize ourselves so that the PHY knows the next
555          * thing coming down is a command
556          */
557
558         sbmac_mii_sync(s);
559
560         /*
561          * Send the data to the PHY.  The sequence is
562          * a "start" command (2 bits)
563          * a "read" command (2 bits)
564          * the PHY addr (5 bits)
565          * the register index (5 bits)
566          */
567
568         sbmac_mii_senddata(s,MII_COMMAND_START, 2);
569         sbmac_mii_senddata(s,MII_COMMAND_READ, 2);
570         sbmac_mii_senddata(s,phyaddr, 5);
571         sbmac_mii_senddata(s,regidx, 5);
572
573         mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
574
575         /*
576          * Switch the port around without a clock transition.
577          */
578         __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
579
580         /*
581          * Send out a clock pulse to signal we want the status
582          */
583
584         __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
585         __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
586
587         /*
588          * If an error occurred, the PHY will signal '1' back
589          */
590         error = __raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN;
591
592         /*
593          * Issue an 'idle' clock pulse, but keep the direction
594          * the same.
595          */
596         __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
597         __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
598
599         regval = 0;
600
601         for (idx = 0; idx < 16; idx++) {
602                 regval <<= 1;
603
604                 if (error == 0) {
605                         if (__raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN)
606                                 regval |= 1;
607                 }
608
609                 __raw_writeq(M_MAC_MDIO_DIR_INPUT|M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
610                 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
611         }
612
613         /* Switch back to output */
614         __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio);
615
616         if (error == 0)
617                 return regval;
618         return 0;
619 }
620
621
622 /**********************************************************************
623  *  SBMAC_MII_WRITE(s,phyaddr,regidx,regval)
624  *
625  *  Write a value to a PHY register.
626  *
627  *  Input parameters:
628  *         s - sbmac structure
629  *         phyaddr - PHY to use
630  *         regidx - register within the PHY
631  *         regval - data to write to register
632  *
633  *  Return value:
634  *         nothing
635  ********************************************************************* */
636
637 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
638                             unsigned int regval)
639 {
640         int mac_mdio_genc;
641
642         sbmac_mii_sync(s);
643
644         sbmac_mii_senddata(s,MII_COMMAND_START,2);
645         sbmac_mii_senddata(s,MII_COMMAND_WRITE,2);
646         sbmac_mii_senddata(s,phyaddr, 5);
647         sbmac_mii_senddata(s,regidx, 5);
648         sbmac_mii_senddata(s,MII_COMMAND_ACK,2);
649         sbmac_mii_senddata(s,regval,16);
650
651         mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
652
653         __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio);
654 }
655
656
657
658 /**********************************************************************
659  *  SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
660  *
661  *  Initialize a DMA channel context.  Since there are potentially
662  *  eight DMA channels per MAC, it's nice to do this in a standard
663  *  way.
664  *
665  *  Input parameters:
666  *         d - sbmacdma_t structure (DMA channel context)
667  *         s - sbmac_softc structure (pointer to a MAC)
668  *         chan - channel number (0..1 right now)
669  *         txrx - Identifies DMA_TX or DMA_RX for channel direction
670  *      maxdescr - number of descriptors
671  *
672  *  Return value:
673  *         nothing
674  ********************************************************************* */
675
676 static void sbdma_initctx(sbmacdma_t *d,
677                           struct sbmac_softc *s,
678                           int chan,
679                           int txrx,
680                           int maxdescr)
681 {
682         /*
683          * Save away interesting stuff in the structure
684          */
685
686         d->sbdma_eth       = s;
687         d->sbdma_channel   = chan;
688         d->sbdma_txdir     = txrx;
689
690 #if 0
691         /* RMON clearing */
692         s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
693 #endif
694
695         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)));
696         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)));
697         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)));
698         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)));
699         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)));
700         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)));
701         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)));
702         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)));
703         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)));
704         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)));
705         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)));
706         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)));
707         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)));
708         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)));
709         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)));
710         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)));
711         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)));
712         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)));
713         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)));
714         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)));
715         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)));
716
717         /*
718          * initialize register pointers
719          */
720
721         d->sbdma_config0 =
722                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
723         d->sbdma_config1 =
724                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
725         d->sbdma_dscrbase =
726                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
727         d->sbdma_dscrcnt =
728                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
729         d->sbdma_curdscr =
730                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
731
732         /*
733          * Allocate memory for the ring
734          */
735
736         d->sbdma_maxdescr = maxdescr;
737
738         d->sbdma_dscrtable = (sbdmadscr_t *)
739                 kmalloc((d->sbdma_maxdescr+1)*sizeof(sbdmadscr_t), GFP_KERNEL);
740
741         /*
742          * The descriptor table must be aligned to at least 16 bytes or the
743          * MAC will corrupt it.
744          */
745         d->sbdma_dscrtable = (sbdmadscr_t *)
746                 ALIGN((unsigned long)d->sbdma_dscrtable, sizeof(sbdmadscr_t));
747
748         memset(d->sbdma_dscrtable,0,d->sbdma_maxdescr*sizeof(sbdmadscr_t));
749
750         d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
751
752         d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
753
754         /*
755          * And context table
756          */
757
758         d->sbdma_ctxtable = (struct sk_buff **)
759                 kmalloc(d->sbdma_maxdescr*sizeof(struct sk_buff *), GFP_KERNEL);
760
761         memset(d->sbdma_ctxtable,0,d->sbdma_maxdescr*sizeof(struct sk_buff *));
762
763 #ifdef CONFIG_SBMAC_COALESCE
764         /*
765          * Setup Rx/Tx DMA coalescing defaults
766          */
767
768         if ( int_pktcnt ) {
769                 d->sbdma_int_pktcnt = int_pktcnt;
770         } else {
771                 d->sbdma_int_pktcnt = 1;
772         }
773
774         if ( int_timeout ) {
775                 d->sbdma_int_timeout = int_timeout;
776         } else {
777                 d->sbdma_int_timeout = 0;
778         }
779 #endif
780
781 }
782
783 /**********************************************************************
784  *  SBDMA_CHANNEL_START(d)
785  *
786  *  Initialize the hardware registers for a DMA channel.
787  *
788  *  Input parameters:
789  *         d - DMA channel to init (context must be previously init'd
790  *         rxtx - DMA_RX or DMA_TX depending on what type of channel
791  *
792  *  Return value:
793  *         nothing
794  ********************************************************************* */
795
796 static void sbdma_channel_start(sbmacdma_t *d, int rxtx )
797 {
798         /*
799          * Turn on the DMA channel
800          */
801
802 #ifdef CONFIG_SBMAC_COALESCE
803         __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
804                        0, d->sbdma_config1);
805         __raw_writeq(M_DMA_EOP_INT_EN |
806                        V_DMA_RINGSZ(d->sbdma_maxdescr) |
807                        V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
808                        0, d->sbdma_config0);
809 #else
810         __raw_writeq(0, d->sbdma_config1);
811         __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) |
812                        0, d->sbdma_config0);
813 #endif
814
815         __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase);
816
817         /*
818          * Initialize ring pointers
819          */
820
821         d->sbdma_addptr = d->sbdma_dscrtable;
822         d->sbdma_remptr = d->sbdma_dscrtable;
823 }
824
825 /**********************************************************************
826  *  SBDMA_CHANNEL_STOP(d)
827  *
828  *  Initialize the hardware registers for a DMA channel.
829  *
830  *  Input parameters:
831  *         d - DMA channel to init (context must be previously init'd
832  *
833  *  Return value:
834  *         nothing
835  ********************************************************************* */
836
837 static void sbdma_channel_stop(sbmacdma_t *d)
838 {
839         /*
840          * Turn off the DMA channel
841          */
842
843         __raw_writeq(0, d->sbdma_config1);
844
845         __raw_writeq(0, d->sbdma_dscrbase);
846
847         __raw_writeq(0, d->sbdma_config0);
848
849         /*
850          * Zero ring pointers
851          */
852
853         d->sbdma_addptr = NULL;
854         d->sbdma_remptr = NULL;
855 }
856
857 static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset)
858 {
859         unsigned long addr;
860         unsigned long newaddr;
861
862         addr = (unsigned long) skb->data;
863
864         newaddr = (addr + power2 - 1) & ~(power2 - 1);
865
866         skb_reserve(skb,newaddr-addr+offset);
867 }
868
869
870 /**********************************************************************
871  *  SBDMA_ADD_RCVBUFFER(d,sb)
872  *
873  *  Add a buffer to the specified DMA channel.   For receive channels,
874  *  this queues a buffer for inbound packets.
875  *
876  *  Input parameters:
877  *         d - DMA channel descriptor
878  *         sb - sk_buff to add, or NULL if we should allocate one
879  *
880  *  Return value:
881  *         0 if buffer could not be added (ring is full)
882  *         1 if buffer added successfully
883  ********************************************************************* */
884
885
886 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb)
887 {
888         sbdmadscr_t *dsc;
889         sbdmadscr_t *nextdsc;
890         struct sk_buff *sb_new = NULL;
891         int pktsize = ENET_PACKET_SIZE;
892
893         /* get pointer to our current place in the ring */
894
895         dsc = d->sbdma_addptr;
896         nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
897
898         /*
899          * figure out if the ring is full - if the next descriptor
900          * is the same as the one that we're going to remove from
901          * the ring, the ring is full
902          */
903
904         if (nextdsc == d->sbdma_remptr) {
905                 return -ENOSPC;
906         }
907
908         /*
909          * Allocate a sk_buff if we don't already have one.
910          * If we do have an sk_buff, reset it so that it's empty.
911          *
912          * Note: sk_buffs don't seem to be guaranteed to have any sort
913          * of alignment when they are allocated.  Therefore, allocate enough
914          * extra space to make sure that:
915          *
916          *    1. the data does not start in the middle of a cache line.
917          *    2. The data does not end in the middle of a cache line
918          *    3. The buffer can be aligned such that the IP addresses are
919          *       naturally aligned.
920          *
921          *  Remember, the SOCs MAC writes whole cache lines at a time,
922          *  without reading the old contents first.  So, if the sk_buff's
923          *  data portion starts in the middle of a cache line, the SOC
924          *  DMA will trash the beginning (and ending) portions.
925          */
926
927         if (sb == NULL) {
928                 sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN);
929                 if (sb_new == NULL) {
930                         printk(KERN_INFO "%s: sk_buff allocation failed\n",
931                                d->sbdma_eth->sbm_dev->name);
932                         return -ENOBUFS;
933                 }
934
935                 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, ETHER_ALIGN);
936         }
937         else {
938                 sb_new = sb;
939                 /*
940                  * nothing special to reinit buffer, it's already aligned
941                  * and sb->data already points to a good place.
942                  */
943         }
944
945         /*
946          * fill in the descriptor
947          */
948
949 #ifdef CONFIG_SBMAC_COALESCE
950         /*
951          * Do not interrupt per DMA transfer.
952          */
953         dsc->dscr_a = virt_to_phys(sb_new->data) |
954                 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) | 0;
955 #else
956         dsc->dscr_a = virt_to_phys(sb_new->data) |
957                 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
958                 M_DMA_DSCRA_INTERRUPT;
959 #endif
960
961         /* receiving: no options */
962         dsc->dscr_b = 0;
963
964         /*
965          * fill in the context
966          */
967
968         d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
969
970         /*
971          * point at next packet
972          */
973
974         d->sbdma_addptr = nextdsc;
975
976         /*
977          * Give the buffer to the DMA engine.
978          */
979
980         __raw_writeq(1, d->sbdma_dscrcnt);
981
982         return 0;                                       /* we did it */
983 }
984
985 /**********************************************************************
986  *  SBDMA_ADD_TXBUFFER(d,sb)
987  *
988  *  Add a transmit buffer to the specified DMA channel, causing a
989  *  transmit to start.
990  *
991  *  Input parameters:
992  *         d - DMA channel descriptor
993  *         sb - sk_buff to add
994  *
995  *  Return value:
996  *         0 transmit queued successfully
997  *         otherwise error code
998  ********************************************************************* */
999
1000
1001 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *sb)
1002 {
1003         sbdmadscr_t *dsc;
1004         sbdmadscr_t *nextdsc;
1005         uint64_t phys;
1006         uint64_t ncb;
1007         int length;
1008
1009         /* get pointer to our current place in the ring */
1010
1011         dsc = d->sbdma_addptr;
1012         nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
1013
1014         /*
1015          * figure out if the ring is full - if the next descriptor
1016          * is the same as the one that we're going to remove from
1017          * the ring, the ring is full
1018          */
1019
1020         if (nextdsc == d->sbdma_remptr) {
1021                 return -ENOSPC;
1022         }
1023
1024         /*
1025          * Under Linux, it's not necessary to copy/coalesce buffers
1026          * like it is on NetBSD.  We think they're all contiguous,
1027          * but that may not be true for GBE.
1028          */
1029
1030         length = sb->len;
1031
1032         /*
1033          * fill in the descriptor.  Note that the number of cache
1034          * blocks in the descriptor is the number of blocks
1035          * *spanned*, so we need to add in the offset (if any)
1036          * while doing the calculation.
1037          */
1038
1039         phys = virt_to_phys(sb->data);
1040         ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
1041
1042         dsc->dscr_a = phys |
1043                 V_DMA_DSCRA_A_SIZE(ncb) |
1044 #ifndef CONFIG_SBMAC_COALESCE
1045                 M_DMA_DSCRA_INTERRUPT |
1046 #endif
1047                 M_DMA_ETHTX_SOP;
1048
1049         /* transmitting: set outbound options and length */
1050
1051         dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
1052                 V_DMA_DSCRB_PKT_SIZE(length);
1053
1054         /*
1055          * fill in the context
1056          */
1057
1058         d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
1059
1060         /*
1061          * point at next packet
1062          */
1063
1064         d->sbdma_addptr = nextdsc;
1065
1066         /*
1067          * Give the buffer to the DMA engine.
1068          */
1069
1070         __raw_writeq(1, d->sbdma_dscrcnt);
1071
1072         return 0;                                       /* we did it */
1073 }
1074
1075
1076
1077
1078 /**********************************************************************
1079  *  SBDMA_EMPTYRING(d)
1080  *
1081  *  Free all allocated sk_buffs on the specified DMA channel;
1082  *
1083  *  Input parameters:
1084  *         d  - DMA channel
1085  *
1086  *  Return value:
1087  *         nothing
1088  ********************************************************************* */
1089
1090 static void sbdma_emptyring(sbmacdma_t *d)
1091 {
1092         int idx;
1093         struct sk_buff *sb;
1094
1095         for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
1096                 sb = d->sbdma_ctxtable[idx];
1097                 if (sb) {
1098                         dev_kfree_skb(sb);
1099                         d->sbdma_ctxtable[idx] = NULL;
1100                 }
1101         }
1102 }
1103
1104
1105 /**********************************************************************
1106  *  SBDMA_FILLRING(d)
1107  *
1108  *  Fill the specified DMA channel (must be receive channel)
1109  *  with sk_buffs
1110  *
1111  *  Input parameters:
1112  *         d - DMA channel
1113  *
1114  *  Return value:
1115  *         nothing
1116  ********************************************************************* */
1117
1118 static void sbdma_fillring(sbmacdma_t *d)
1119 {
1120         int idx;
1121
1122         for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) {
1123                 if (sbdma_add_rcvbuffer(d,NULL) != 0)
1124                         break;
1125         }
1126 }
1127
1128
1129 /**********************************************************************
1130  *  SBDMA_RX_PROCESS(sc,d)
1131  *
1132  *  Process "completed" receive buffers on the specified DMA channel.
1133  *  Note that this isn't really ideal for priority channels, since
1134  *  it processes all of the packets on a given channel before
1135  *  returning.
1136  *
1137  *  Input parameters:
1138  *         sc - softc structure
1139  *         d - DMA channel context
1140  *
1141  *  Return value:
1142  *         nothing
1143  ********************************************************************* */
1144
1145 static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1146 {
1147         int curidx;
1148         int hwidx;
1149         sbdmadscr_t *dsc;
1150         struct sk_buff *sb;
1151         int len;
1152
1153         for (;;) {
1154                 /*
1155                  * figure out where we are (as an index) and where
1156                  * the hardware is (also as an index)
1157                  *
1158                  * This could be done faster if (for example) the
1159                  * descriptor table was page-aligned and contiguous in
1160                  * both virtual and physical memory -- you could then
1161                  * just compare the low-order bits of the virtual address
1162                  * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1163                  */
1164
1165                 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1166                 hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1167                                 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1168
1169                 /*
1170                  * If they're the same, that means we've processed all
1171                  * of the descriptors up to (but not including) the one that
1172                  * the hardware is working on right now.
1173                  */
1174
1175                 if (curidx == hwidx)
1176                         break;
1177
1178                 /*
1179                  * Otherwise, get the packet's sk_buff ptr back
1180                  */
1181
1182                 dsc = &(d->sbdma_dscrtable[curidx]);
1183                 sb = d->sbdma_ctxtable[curidx];
1184                 d->sbdma_ctxtable[curidx] = NULL;
1185
1186                 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1187
1188                 /*
1189                  * Check packet status.  If good, process it.
1190                  * If not, silently drop it and put it back on the
1191                  * receive ring.
1192                  */
1193
1194                 if (!(dsc->dscr_a & M_DMA_ETHRX_BAD)) {
1195
1196                         /*
1197                          * Add a new buffer to replace the old one.  If we fail
1198                          * to allocate a buffer, we're going to drop this
1199                          * packet and put it right back on the receive ring.
1200                          */
1201
1202                         if (sbdma_add_rcvbuffer(d,NULL) == -ENOBUFS) {
1203                                 sc->sbm_stats.rx_dropped++;
1204                                 sbdma_add_rcvbuffer(d,sb); /* re-add old buffer */
1205                         } else {
1206                                 /*
1207                                  * Set length into the packet
1208                                  */
1209                                 skb_put(sb,len);
1210
1211                                 /*
1212                                  * Buffer has been replaced on the
1213                                  * receive ring.  Pass the buffer to
1214                                  * the kernel
1215                                  */
1216                                 sc->sbm_stats.rx_bytes += len;
1217                                 sc->sbm_stats.rx_packets++;
1218                                 sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
1219                                 /* Check hw IPv4/TCP checksum if supported */
1220                                 if (sc->rx_hw_checksum == ENABLE) {
1221                                         if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&
1222                                             !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {
1223                                                 sb->ip_summed = CHECKSUM_UNNECESSARY;
1224                                                 /* don't need to set sb->csum */
1225                                         } else {
1226                                                 sb->ip_summed = CHECKSUM_NONE;
1227                                         }
1228                                 }
1229
1230                                 netif_rx(sb);
1231                         }
1232                 } else {
1233                         /*
1234                          * Packet was mangled somehow.  Just drop it and
1235                          * put it back on the receive ring.
1236                          */
1237                         sc->sbm_stats.rx_errors++;
1238                         sbdma_add_rcvbuffer(d,sb);
1239                 }
1240
1241
1242                 /*
1243                  * .. and advance to the next buffer.
1244                  */
1245
1246                 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1247
1248         }
1249 }
1250
1251
1252
1253 /**********************************************************************
1254  *  SBDMA_TX_PROCESS(sc,d)
1255  *
1256  *  Process "completed" transmit buffers on the specified DMA channel.
1257  *  This is normally called within the interrupt service routine.
1258  *  Note that this isn't really ideal for priority channels, since
1259  *  it processes all of the packets on a given channel before
1260  *  returning.
1261  *
1262  *  Input parameters:
1263  *      sc - softc structure
1264  *         d - DMA channel context
1265  *
1266  *  Return value:
1267  *         nothing
1268  ********************************************************************* */
1269
1270 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1271 {
1272         int curidx;
1273         int hwidx;
1274         sbdmadscr_t *dsc;
1275         struct sk_buff *sb;
1276         unsigned long flags;
1277
1278         spin_lock_irqsave(&(sc->sbm_lock), flags);
1279
1280         for (;;) {
1281                 /*
1282                  * figure out where we are (as an index) and where
1283                  * the hardware is (also as an index)
1284                  *
1285                  * This could be done faster if (for example) the
1286                  * descriptor table was page-aligned and contiguous in
1287                  * both virtual and physical memory -- you could then
1288                  * just compare the low-order bits of the virtual address
1289                  * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1290                  */
1291
1292                 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1293                 hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1294                                 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1295
1296                 /*
1297                  * If they're the same, that means we've processed all
1298                  * of the descriptors up to (but not including) the one that
1299                  * the hardware is working on right now.
1300                  */
1301
1302                 if (curidx == hwidx)
1303                         break;
1304
1305                 /*
1306                  * Otherwise, get the packet's sk_buff ptr back
1307                  */
1308
1309                 dsc = &(d->sbdma_dscrtable[curidx]);
1310                 sb = d->sbdma_ctxtable[curidx];
1311                 d->sbdma_ctxtable[curidx] = NULL;
1312
1313                 /*
1314                  * Stats
1315                  */
1316
1317                 sc->sbm_stats.tx_bytes += sb->len;
1318                 sc->sbm_stats.tx_packets++;
1319
1320                 /*
1321                  * for transmits, we just free buffers.
1322                  */
1323
1324                 dev_kfree_skb_irq(sb);
1325
1326                 /*
1327                  * .. and advance to the next buffer.
1328                  */
1329
1330                 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1331
1332         }
1333
1334         /*
1335          * Decide if we should wake up the protocol or not.
1336          * Other drivers seem to do this when we reach a low
1337          * watermark on the transmit queue.
1338          */
1339
1340         netif_wake_queue(d->sbdma_eth->sbm_dev);
1341
1342         spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1343
1344 }
1345
1346
1347
1348 /**********************************************************************
1349  *  SBMAC_INITCTX(s)
1350  *
1351  *  Initialize an Ethernet context structure - this is called
1352  *  once per MAC on the 1250.  Memory is allocated here, so don't
1353  *  call it again from inside the ioctl routines that bring the
1354  *  interface up/down
1355  *
1356  *  Input parameters:
1357  *         s - sbmac context structure
1358  *
1359  *  Return value:
1360  *         0
1361  ********************************************************************* */
1362
1363 static int sbmac_initctx(struct sbmac_softc *s)
1364 {
1365
1366         /*
1367          * figure out the addresses of some ports
1368          */
1369
1370         s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
1371         s->sbm_maccfg    = s->sbm_base + R_MAC_CFG;
1372         s->sbm_fifocfg   = s->sbm_base + R_MAC_THRSH_CFG;
1373         s->sbm_framecfg  = s->sbm_base + R_MAC_FRAMECFG;
1374         s->sbm_rxfilter  = s->sbm_base + R_MAC_ADFILTER_CFG;
1375         s->sbm_isr       = s->sbm_base + R_MAC_STATUS;
1376         s->sbm_imr       = s->sbm_base + R_MAC_INT_MASK;
1377         s->sbm_mdio      = s->sbm_base + R_MAC_MDIO;
1378
1379         s->sbm_phys[0]   = 1;
1380         s->sbm_phys[1]   = 0;
1381
1382         s->sbm_phy_oldbmsr = 0;
1383         s->sbm_phy_oldanlpar = 0;
1384         s->sbm_phy_oldk1stsr = 0;
1385         s->sbm_phy_oldlinkstat = 0;
1386
1387         /*
1388          * Initialize the DMA channels.  Right now, only one per MAC is used
1389          * Note: Only do this _once_, as it allocates memory from the kernel!
1390          */
1391
1392         sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1393         sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1394
1395         /*
1396          * initial state is OFF
1397          */
1398
1399         s->sbm_state = sbmac_state_off;
1400
1401         /*
1402          * Initial speed is (XXX TEMP) 10MBit/s HDX no FC
1403          */
1404
1405         s->sbm_speed = sbmac_speed_10;
1406         s->sbm_duplex = sbmac_duplex_half;
1407         s->sbm_fc = sbmac_fc_disabled;
1408
1409         return 0;
1410 }
1411
1412
1413 static void sbdma_uninitctx(struct sbmacdma_s *d)
1414 {
1415         if (d->sbdma_dscrtable) {
1416                 kfree(d->sbdma_dscrtable);
1417                 d->sbdma_dscrtable = NULL;
1418         }
1419
1420         if (d->sbdma_ctxtable) {
1421                 kfree(d->sbdma_ctxtable);
1422                 d->sbdma_ctxtable = NULL;
1423         }
1424 }
1425
1426
1427 static void sbmac_uninitctx(struct sbmac_softc *sc)
1428 {
1429         sbdma_uninitctx(&(sc->sbm_txdma));
1430         sbdma_uninitctx(&(sc->sbm_rxdma));
1431 }
1432
1433
1434 /**********************************************************************
1435  *  SBMAC_CHANNEL_START(s)
1436  *
1437  *  Start packet processing on this MAC.
1438  *
1439  *  Input parameters:
1440  *         s - sbmac structure
1441  *
1442  *  Return value:
1443  *         nothing
1444  ********************************************************************* */
1445
1446 static void sbmac_channel_start(struct sbmac_softc *s)
1447 {
1448         uint64_t reg;
1449         volatile void __iomem *port;
1450         uint64_t cfg,fifo,framecfg;
1451         int idx, th_value;
1452
1453         /*
1454          * Don't do this if running
1455          */
1456
1457         if (s->sbm_state == sbmac_state_on)
1458                 return;
1459
1460         /*
1461          * Bring the controller out of reset, but leave it off.
1462          */
1463
1464         __raw_writeq(0, s->sbm_macenable);
1465
1466         /*
1467          * Ignore all received packets
1468          */
1469
1470         __raw_writeq(0, s->sbm_rxfilter);
1471
1472         /*
1473          * Calculate values for various control registers.
1474          */
1475
1476         cfg = M_MAC_RETRY_EN |
1477                 M_MAC_TX_HOLD_SOP_EN |
1478                 V_MAC_TX_PAUSE_CNT_16K |
1479                 M_MAC_AP_STAT_EN |
1480                 M_MAC_FAST_SYNC |
1481                 M_MAC_SS_EN |
1482                 0;
1483
1484         /*
1485          * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1486          * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1487          * Use a larger RD_THRSH for gigabit
1488          */
1489         if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2)
1490                 th_value = 28;
1491         else
1492                 th_value = 64;
1493
1494         fifo = V_MAC_TX_WR_THRSH(4) |   /* Must be '4' or '8' */
1495                 ((s->sbm_speed == sbmac_speed_1000)
1496                  ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |
1497                 V_MAC_TX_RL_THRSH(4) |
1498                 V_MAC_RX_PL_THRSH(4) |
1499                 V_MAC_RX_RD_THRSH(4) |  /* Must be '4' */
1500                 V_MAC_RX_PL_THRSH(4) |
1501                 V_MAC_RX_RL_THRSH(8) |
1502                 0;
1503
1504         framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
1505                 V_MAC_MAX_FRAMESZ_DEFAULT |
1506                 V_MAC_BACKOFF_SEL(1);
1507
1508         /*
1509          * Clear out the hash address map
1510          */
1511
1512         port = s->sbm_base + R_MAC_HASH_BASE;
1513         for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1514                 __raw_writeq(0, port);
1515                 port += sizeof(uint64_t);
1516         }
1517
1518         /*
1519          * Clear out the exact-match table
1520          */
1521
1522         port = s->sbm_base + R_MAC_ADDR_BASE;
1523         for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1524                 __raw_writeq(0, port);
1525                 port += sizeof(uint64_t);
1526         }
1527
1528         /*
1529          * Clear out the DMA Channel mapping table registers
1530          */
1531
1532         port = s->sbm_base + R_MAC_CHUP0_BASE;
1533         for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1534                 __raw_writeq(0, port);
1535                 port += sizeof(uint64_t);
1536         }
1537
1538
1539         port = s->sbm_base + R_MAC_CHLO0_BASE;
1540         for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1541                 __raw_writeq(0, port);
1542                 port += sizeof(uint64_t);
1543         }
1544
1545         /*
1546          * Program the hardware address.  It goes into the hardware-address
1547          * register as well as the first filter register.
1548          */
1549
1550         reg = sbmac_addr2reg(s->sbm_hwaddr);
1551
1552         port = s->sbm_base + R_MAC_ADDR_BASE;
1553         __raw_writeq(reg, port);
1554         port = s->sbm_base + R_MAC_ETHERNET_ADDR;
1555
1556 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1557         /*
1558          * Pass1 SOCs do not receive packets addressed to the
1559          * destination address in the R_MAC_ETHERNET_ADDR register.
1560          * Set the value to zero.
1561          */
1562         __raw_writeq(0, port);
1563 #else
1564         __raw_writeq(reg, port);
1565 #endif
1566
1567         /*
1568          * Set the receive filter for no packets, and write values
1569          * to the various config registers
1570          */
1571
1572         __raw_writeq(0, s->sbm_rxfilter);
1573         __raw_writeq(0, s->sbm_imr);
1574         __raw_writeq(framecfg, s->sbm_framecfg);
1575         __raw_writeq(fifo, s->sbm_fifocfg);
1576         __raw_writeq(cfg, s->sbm_maccfg);
1577
1578         /*
1579          * Initialize DMA channels (rings should be ok now)
1580          */
1581
1582         sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1583         sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1584
1585         /*
1586          * Configure the speed, duplex, and flow control
1587          */
1588
1589         sbmac_set_speed(s,s->sbm_speed);
1590         sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1591
1592         /*
1593          * Fill the receive ring
1594          */
1595
1596         sbdma_fillring(&(s->sbm_rxdma));
1597
1598         /*
1599          * Turn on the rest of the bits in the enable register
1600          */
1601
1602 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
1603         __raw_writeq(M_MAC_RXDMA_EN0 |
1604                        M_MAC_TXDMA_EN0, s->sbm_macenable);
1605 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
1606         __raw_writeq(M_MAC_RXDMA_EN0 |
1607                        M_MAC_TXDMA_EN0 |
1608                        M_MAC_RX_ENABLE |
1609                        M_MAC_TX_ENABLE, s->sbm_macenable);
1610 #else
1611 #error invalid SiByte MAC configuation
1612 #endif
1613
1614 #ifdef CONFIG_SBMAC_COALESCE
1615         /*
1616          * Accept any TX interrupt and EOP count/timer RX interrupts on ch 0
1617          */
1618         __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1619                        ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr);
1620 #else
1621         /*
1622          * Accept any kind of interrupt on TX and RX DMA channel 0
1623          */
1624         __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1625                        (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr);
1626 #endif
1627
1628         /*
1629          * Enable receiving unicasts and broadcasts
1630          */
1631
1632         __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter);
1633
1634         /*
1635          * we're running now.
1636          */
1637
1638         s->sbm_state = sbmac_state_on;
1639
1640         /*
1641          * Program multicast addresses
1642          */
1643
1644         sbmac_setmulti(s);
1645
1646         /*
1647          * If channel was in promiscuous mode before, turn that on
1648          */
1649
1650         if (s->sbm_devflags & IFF_PROMISC) {
1651                 sbmac_promiscuous_mode(s,1);
1652         }
1653
1654 }
1655
1656
1657 /**********************************************************************
1658  *  SBMAC_CHANNEL_STOP(s)
1659  *
1660  *  Stop packet processing on this MAC.
1661  *
1662  *  Input parameters:
1663  *         s - sbmac structure
1664  *
1665  *  Return value:
1666  *         nothing
1667  ********************************************************************* */
1668
1669 static void sbmac_channel_stop(struct sbmac_softc *s)
1670 {
1671         /* don't do this if already stopped */
1672
1673         if (s->sbm_state == sbmac_state_off)
1674                 return;
1675
1676         /* don't accept any packets, disable all interrupts */
1677
1678         __raw_writeq(0, s->sbm_rxfilter);
1679         __raw_writeq(0, s->sbm_imr);
1680
1681         /* Turn off ticker */
1682
1683         /* XXX */
1684
1685         /* turn off receiver and transmitter */
1686
1687         __raw_writeq(0, s->sbm_macenable);
1688
1689         /* We're stopped now. */
1690
1691         s->sbm_state = sbmac_state_off;
1692
1693         /*
1694          * Stop DMA channels (rings should be ok now)
1695          */
1696
1697         sbdma_channel_stop(&(s->sbm_rxdma));
1698         sbdma_channel_stop(&(s->sbm_txdma));
1699
1700         /* Empty the receive and transmit rings */
1701
1702         sbdma_emptyring(&(s->sbm_rxdma));
1703         sbdma_emptyring(&(s->sbm_txdma));
1704
1705 }
1706
1707 /**********************************************************************
1708  *  SBMAC_SET_CHANNEL_STATE(state)
1709  *
1710  *  Set the channel's state ON or OFF
1711  *
1712  *  Input parameters:
1713  *         state - new state
1714  *
1715  *  Return value:
1716  *         old state
1717  ********************************************************************* */
1718 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *sc,
1719                                              sbmac_state_t state)
1720 {
1721         sbmac_state_t oldstate = sc->sbm_state;
1722
1723         /*
1724          * If same as previous state, return
1725          */
1726
1727         if (state == oldstate) {
1728                 return oldstate;
1729         }
1730
1731         /*
1732          * If new state is ON, turn channel on
1733          */
1734
1735         if (state == sbmac_state_on) {
1736                 sbmac_channel_start(sc);
1737         }
1738         else {
1739                 sbmac_channel_stop(sc);
1740         }
1741
1742         /*
1743          * Return previous state
1744          */
1745
1746         return oldstate;
1747 }
1748
1749
1750 /**********************************************************************
1751  *  SBMAC_PROMISCUOUS_MODE(sc,onoff)
1752  *
1753  *  Turn on or off promiscuous mode
1754  *
1755  *  Input parameters:
1756  *         sc - softc
1757  *      onoff - 1 to turn on, 0 to turn off
1758  *
1759  *  Return value:
1760  *         nothing
1761  ********************************************************************* */
1762
1763 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1764 {
1765         uint64_t reg;
1766
1767         if (sc->sbm_state != sbmac_state_on)
1768                 return;
1769
1770         if (onoff) {
1771                 reg = __raw_readq(sc->sbm_rxfilter);
1772                 reg |= M_MAC_ALLPKT_EN;
1773                 __raw_writeq(reg, sc->sbm_rxfilter);
1774         }
1775         else {
1776                 reg = __raw_readq(sc->sbm_rxfilter);
1777                 reg &= ~M_MAC_ALLPKT_EN;
1778                 __raw_writeq(reg, sc->sbm_rxfilter);
1779         }
1780 }
1781
1782 /**********************************************************************
1783  *  SBMAC_SETIPHDR_OFFSET(sc,onoff)
1784  *
1785  *  Set the iphdr offset as 15 assuming ethernet encapsulation
1786  *
1787  *  Input parameters:
1788  *         sc - softc
1789  *
1790  *  Return value:
1791  *         nothing
1792  ********************************************************************* */
1793
1794 static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1795 {
1796         uint64_t reg;
1797
1798         /* Hard code the off set to 15 for now */
1799         reg = __raw_readq(sc->sbm_rxfilter);
1800         reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
1801         __raw_writeq(reg, sc->sbm_rxfilter);
1802
1803         /* BCM1250 pass1 didn't have hardware checksum.  Everything
1804            later does.  */
1805         if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) {
1806                 sc->rx_hw_checksum = DISABLE;
1807         } else {
1808                 sc->rx_hw_checksum = ENABLE;
1809         }
1810 }
1811
1812
1813 /**********************************************************************
1814  *  SBMAC_ADDR2REG(ptr)
1815  *
1816  *  Convert six bytes into the 64-bit register value that
1817  *  we typically write into the SBMAC's address/mcast registers
1818  *
1819  *  Input parameters:
1820  *         ptr - pointer to 6 bytes
1821  *
1822  *  Return value:
1823  *         register value
1824  ********************************************************************* */
1825
1826 static uint64_t sbmac_addr2reg(unsigned char *ptr)
1827 {
1828         uint64_t reg = 0;
1829
1830         ptr += 6;
1831
1832         reg |= (uint64_t) *(--ptr);
1833         reg <<= 8;
1834         reg |= (uint64_t) *(--ptr);
1835         reg <<= 8;
1836         reg |= (uint64_t) *(--ptr);
1837         reg <<= 8;
1838         reg |= (uint64_t) *(--ptr);
1839         reg <<= 8;
1840         reg |= (uint64_t) *(--ptr);
1841         reg <<= 8;
1842         reg |= (uint64_t) *(--ptr);
1843
1844         return reg;
1845 }
1846
1847
1848 /**********************************************************************
1849  *  SBMAC_SET_SPEED(s,speed)
1850  *
1851  *  Configure LAN speed for the specified MAC.
1852  *  Warning: must be called when MAC is off!
1853  *
1854  *  Input parameters:
1855  *         s - sbmac structure
1856  *         speed - speed to set MAC to (see sbmac_speed_t enum)
1857  *
1858  *  Return value:
1859  *         1 if successful
1860  *      0 indicates invalid parameters
1861  ********************************************************************* */
1862
1863 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed)
1864 {
1865         uint64_t cfg;
1866         uint64_t framecfg;
1867
1868         /*
1869          * Save new current values
1870          */
1871
1872         s->sbm_speed = speed;
1873
1874         if (s->sbm_state == sbmac_state_on)
1875                 return 0;       /* save for next restart */
1876
1877         /*
1878          * Read current register values
1879          */
1880
1881         cfg = __raw_readq(s->sbm_maccfg);
1882         framecfg = __raw_readq(s->sbm_framecfg);
1883
1884         /*
1885          * Mask out the stuff we want to change
1886          */
1887
1888         cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
1889         framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
1890                       M_MAC_SLOT_SIZE);
1891
1892         /*
1893          * Now add in the new bits
1894          */
1895
1896         switch (speed) {
1897         case sbmac_speed_10:
1898                 framecfg |= V_MAC_IFG_RX_10 |
1899                         V_MAC_IFG_TX_10 |
1900                         K_MAC_IFG_THRSH_10 |
1901                         V_MAC_SLOT_SIZE_10;
1902                 cfg |= V_MAC_SPEED_SEL_10MBPS;
1903                 break;
1904
1905         case sbmac_speed_100:
1906                 framecfg |= V_MAC_IFG_RX_100 |
1907                         V_MAC_IFG_TX_100 |
1908                         V_MAC_IFG_THRSH_100 |
1909                         V_MAC_SLOT_SIZE_100;
1910                 cfg |= V_MAC_SPEED_SEL_100MBPS ;
1911                 break;
1912
1913         case sbmac_speed_1000:
1914                 framecfg |= V_MAC_IFG_RX_1000 |
1915                         V_MAC_IFG_TX_1000 |
1916                         V_MAC_IFG_THRSH_1000 |
1917                         V_MAC_SLOT_SIZE_1000;
1918                 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
1919                 break;
1920
1921         case sbmac_speed_auto:          /* XXX not implemented */
1922                 /* fall through */
1923         default:
1924                 return 0;
1925         }
1926
1927         /*
1928          * Send the bits back to the hardware
1929          */
1930
1931         __raw_writeq(framecfg, s->sbm_framecfg);
1932         __raw_writeq(cfg, s->sbm_maccfg);
1933
1934         return 1;
1935 }
1936
1937 /**********************************************************************
1938  *  SBMAC_SET_DUPLEX(s,duplex,fc)
1939  *
1940  *  Set Ethernet duplex and flow control options for this MAC
1941  *  Warning: must be called when MAC is off!
1942  *
1943  *  Input parameters:
1944  *         s - sbmac structure
1945  *         duplex - duplex setting (see sbmac_duplex_t)
1946  *         fc - flow control setting (see sbmac_fc_t)
1947  *
1948  *  Return value:
1949  *         1 if ok
1950  *         0 if an invalid parameter combination was specified
1951  ********************************************************************* */
1952
1953 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc)
1954 {
1955         uint64_t cfg;
1956
1957         /*
1958          * Save new current values
1959          */
1960
1961         s->sbm_duplex = duplex;
1962         s->sbm_fc = fc;
1963
1964         if (s->sbm_state == sbmac_state_on)
1965                 return 0;       /* save for next restart */
1966
1967         /*
1968          * Read current register values
1969          */
1970
1971         cfg = __raw_readq(s->sbm_maccfg);
1972
1973         /*
1974          * Mask off the stuff we're about to change
1975          */
1976
1977         cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
1978
1979
1980         switch (duplex) {
1981         case sbmac_duplex_half:
1982                 switch (fc) {
1983                 case sbmac_fc_disabled:
1984                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
1985                         break;
1986
1987                 case sbmac_fc_collision:
1988                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
1989                         break;
1990
1991                 case sbmac_fc_carrier:
1992                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
1993                         break;
1994
1995                 case sbmac_fc_auto:             /* XXX not implemented */
1996                         /* fall through */
1997                 case sbmac_fc_frame:            /* not valid in half duplex */
1998                 default:                        /* invalid selection */
1999                         return 0;
2000                 }
2001                 break;
2002
2003         case sbmac_duplex_full:
2004                 switch (fc) {
2005                 case sbmac_fc_disabled:
2006                         cfg |= V_MAC_FC_CMD_DISABLED;
2007                         break;
2008
2009                 case sbmac_fc_frame:
2010                         cfg |= V_MAC_FC_CMD_ENABLED;
2011                         break;
2012
2013                 case sbmac_fc_collision:        /* not valid in full duplex */
2014                 case sbmac_fc_carrier:          /* not valid in full duplex */
2015                 case sbmac_fc_auto:             /* XXX not implemented */
2016                         /* fall through */
2017                 default:
2018                         return 0;
2019                 }
2020                 break;
2021         case sbmac_duplex_auto:
2022                 /* XXX not implemented */
2023                 break;
2024         }
2025
2026         /*
2027          * Send the bits back to the hardware
2028          */
2029
2030         __raw_writeq(cfg, s->sbm_maccfg);
2031
2032         return 1;
2033 }
2034
2035
2036
2037
2038 /**********************************************************************
2039  *  SBMAC_INTR()
2040  *
2041  *  Interrupt handler for MAC interrupts
2042  *
2043  *  Input parameters:
2044  *         MAC structure
2045  *
2046  *  Return value:
2047  *         nothing
2048  ********************************************************************* */
2049 static irqreturn_t sbmac_intr(int irq,void *dev_instance)
2050 {
2051         struct net_device *dev = (struct net_device *) dev_instance;
2052         struct sbmac_softc *sc = netdev_priv(dev);
2053         uint64_t isr;
2054         int handled = 0;
2055
2056         for (;;) {
2057
2058                 /*
2059                  * Read the ISR (this clears the bits in the real
2060                  * register, except for counter addr)
2061                  */
2062
2063                 isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
2064
2065                 if (isr == 0)
2066                         break;
2067
2068                 handled = 1;
2069
2070                 /*
2071                  * Transmits on channel 0
2072                  */
2073
2074                 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) {
2075                         sbdma_tx_process(sc,&(sc->sbm_txdma));
2076                 }
2077
2078                 /*
2079                  * Receives on channel 0
2080                  */
2081
2082                 /*
2083                  * It's important to test all the bits (or at least the
2084                  * EOP_SEEN bit) when deciding to do the RX process
2085                  * particularly when coalescing, to make sure we
2086                  * take care of the following:
2087                  *
2088                  * If you have some packets waiting (have been received
2089                  * but no interrupt) and get a TX interrupt before
2090                  * the RX timer or counter expires, reading the ISR
2091                  * above will clear the timer and counter, and you
2092                  * won't get another interrupt until a packet shows
2093                  * up to start the timer again.  Testing
2094                  * EOP_SEEN here takes care of this case.
2095                  * (EOP_SEEN is part of M_MAC_INT_CHANNEL << S_MAC_RX_CH0)
2096                  */
2097
2098
2099                 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2100                         sbdma_rx_process(sc,&(sc->sbm_rxdma));
2101                 }
2102         }
2103         return IRQ_RETVAL(handled);
2104 }
2105
2106
2107 /**********************************************************************
2108  *  SBMAC_START_TX(skb,dev)
2109  *
2110  *  Start output on the specified interface.  Basically, we
2111  *  queue as many buffers as we can until the ring fills up, or
2112  *  we run off the end of the queue, whichever comes first.
2113  *
2114  *  Input parameters:
2115  *
2116  *
2117  *  Return value:
2118  *         nothing
2119  ********************************************************************* */
2120 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2121 {
2122         struct sbmac_softc *sc = netdev_priv(dev);
2123
2124         /* lock eth irq */
2125         spin_lock_irq (&sc->sbm_lock);
2126
2127         /*
2128          * Put the buffer on the transmit ring.  If we
2129          * don't have room, stop the queue.
2130          */
2131
2132         if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2133                 /* XXX save skb that we could not send */
2134                 netif_stop_queue(dev);
2135                 spin_unlock_irq(&sc->sbm_lock);
2136
2137                 return 1;
2138         }
2139
2140         dev->trans_start = jiffies;
2141
2142         spin_unlock_irq (&sc->sbm_lock);
2143
2144         return 0;
2145 }
2146
2147 /**********************************************************************
2148  *  SBMAC_SETMULTI(sc)
2149  *
2150  *  Reprogram the multicast table into the hardware, given
2151  *  the list of multicasts associated with the interface
2152  *  structure.
2153  *
2154  *  Input parameters:
2155  *         sc - softc
2156  *
2157  *  Return value:
2158  *         nothing
2159  ********************************************************************* */
2160
2161 static void sbmac_setmulti(struct sbmac_softc *sc)
2162 {
2163         uint64_t reg;
2164         volatile void __iomem *port;
2165         int idx;
2166         struct dev_mc_list *mclist;
2167         struct net_device *dev = sc->sbm_dev;
2168
2169         /*
2170          * Clear out entire multicast table.  We do this by nuking
2171          * the entire hash table and all the direct matches except
2172          * the first one, which is used for our station address
2173          */
2174
2175         for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2176                 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
2177                 __raw_writeq(0, port);
2178         }
2179
2180         for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2181                 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
2182                 __raw_writeq(0, port);
2183         }
2184
2185         /*
2186          * Clear the filter to say we don't want any multicasts.
2187          */
2188
2189         reg = __raw_readq(sc->sbm_rxfilter);
2190         reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2191         __raw_writeq(reg, sc->sbm_rxfilter);
2192
2193         if (dev->flags & IFF_ALLMULTI) {
2194                 /*
2195                  * Enable ALL multicasts.  Do this by inverting the
2196                  * multicast enable bit.
2197                  */
2198                 reg = __raw_readq(sc->sbm_rxfilter);
2199                 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2200                 __raw_writeq(reg, sc->sbm_rxfilter);
2201                 return;
2202         }
2203
2204
2205         /*
2206          * Progam new multicast entries.  For now, only use the
2207          * perfect filter.  In the future we'll need to use the
2208          * hash filter if the perfect filter overflows
2209          */
2210
2211         /* XXX only using perfect filter for now, need to use hash
2212          * XXX if the table overflows */
2213
2214         idx = 1;                /* skip station address */
2215         mclist = dev->mc_list;
2216         while (mclist && (idx < MAC_ADDR_COUNT)) {
2217                 reg = sbmac_addr2reg(mclist->dmi_addr);
2218                 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
2219                 __raw_writeq(reg, port);
2220                 idx++;
2221                 mclist = mclist->next;
2222         }
2223
2224         /*
2225          * Enable the "accept multicast bits" if we programmed at least one
2226          * multicast.
2227          */
2228
2229         if (idx > 1) {
2230                 reg = __raw_readq(sc->sbm_rxfilter);
2231                 reg |= M_MAC_MCAST_EN;
2232                 __raw_writeq(reg, sc->sbm_rxfilter);
2233         }
2234 }
2235
2236
2237
2238 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
2239 /**********************************************************************
2240  *  SBMAC_PARSE_XDIGIT(str)
2241  *
2242  *  Parse a hex digit, returning its value
2243  *
2244  *  Input parameters:
2245  *         str - character
2246  *
2247  *  Return value:
2248  *         hex value, or -1 if invalid
2249  ********************************************************************* */
2250
2251 static int sbmac_parse_xdigit(char str)
2252 {
2253         int digit;
2254
2255         if ((str >= '0') && (str <= '9'))
2256                 digit = str - '0';
2257         else if ((str >= 'a') && (str <= 'f'))
2258                 digit = str - 'a' + 10;
2259         else if ((str >= 'A') && (str <= 'F'))
2260                 digit = str - 'A' + 10;
2261         else
2262                 return -1;
2263
2264         return digit;
2265 }
2266
2267 /**********************************************************************
2268  *  SBMAC_PARSE_HWADDR(str,hwaddr)
2269  *
2270  *  Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte
2271  *  Ethernet address.
2272  *
2273  *  Input parameters:
2274  *         str - string
2275  *         hwaddr - pointer to hardware address
2276  *
2277  *  Return value:
2278  *         0 if ok, else -1
2279  ********************************************************************* */
2280
2281 static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr)
2282 {
2283         int digit1,digit2;
2284         int idx = 6;
2285
2286         while (*str && (idx > 0)) {
2287                 digit1 = sbmac_parse_xdigit(*str);
2288                 if (digit1 < 0)
2289                         return -1;
2290                 str++;
2291                 if (!*str)
2292                         return -1;
2293
2294                 if ((*str == ':') || (*str == '-')) {
2295                         digit2 = digit1;
2296                         digit1 = 0;
2297                 }
2298                 else {
2299                         digit2 = sbmac_parse_xdigit(*str);
2300                         if (digit2 < 0)
2301                                 return -1;
2302                         str++;
2303                 }
2304
2305                 *hwaddr++ = (digit1 << 4) | digit2;
2306                 idx--;
2307
2308                 if (*str == '-')
2309                         str++;
2310                 if (*str == ':')
2311                         str++;
2312         }
2313         return 0;
2314 }
2315 #endif
2316
2317 static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2318 {
2319         if (new_mtu >  ENET_PACKET_SIZE)
2320                 return -EINVAL;
2321         _dev->mtu = new_mtu;
2322         printk(KERN_INFO "changing the mtu to %d\n", new_mtu);
2323         return 0;
2324 }
2325
2326 /**********************************************************************
2327  *  SBMAC_INIT(dev)
2328  *
2329  *  Attach routine - init hardware and hook ourselves into linux
2330  *
2331  *  Input parameters:
2332  *         dev - net_device structure
2333  *
2334  *  Return value:
2335  *         status
2336  ********************************************************************* */
2337
2338 static int sbmac_init(struct net_device *dev, int idx)
2339 {
2340         struct sbmac_softc *sc;
2341         unsigned char *eaddr;
2342         uint64_t ea_reg;
2343         int i;
2344         int err;
2345
2346         sc = netdev_priv(dev);
2347
2348         /* Determine controller base address */
2349
2350         sc->sbm_base = IOADDR(dev->base_addr);
2351         sc->sbm_dev = dev;
2352         sc->sbe_idx = idx;
2353
2354         eaddr = sc->sbm_hwaddr;
2355
2356         /*
2357          * Read the ethernet address.  The firwmare left this programmed
2358          * for us in the ethernet address register for each mac.
2359          */
2360
2361         ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR);
2362         __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR);
2363         for (i = 0; i < 6; i++) {
2364                 eaddr[i] = (uint8_t) (ea_reg & 0xFF);
2365                 ea_reg >>= 8;
2366         }
2367
2368         for (i = 0; i < 6; i++) {
2369                 dev->dev_addr[i] = eaddr[i];
2370         }
2371
2372
2373         /*
2374          * Init packet size
2375          */
2376
2377         sc->sbm_buffersize = ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN;
2378
2379         /*
2380          * Initialize context (get pointers to registers and stuff), then
2381          * allocate the memory for the descriptor tables.
2382          */
2383
2384         sbmac_initctx(sc);
2385
2386         /*
2387          * Set up Linux device callins
2388          */
2389
2390         spin_lock_init(&(sc->sbm_lock));
2391
2392         dev->open               = sbmac_open;
2393         dev->hard_start_xmit    = sbmac_start_tx;
2394         dev->stop               = sbmac_close;
2395         dev->get_stats          = sbmac_get_stats;
2396         dev->set_multicast_list = sbmac_set_rx_mode;
2397         dev->do_ioctl           = sbmac_mii_ioctl;
2398         dev->tx_timeout         = sbmac_tx_timeout;
2399         dev->watchdog_timeo     = TX_TIMEOUT;
2400
2401         dev->change_mtu         = sb1250_change_mtu;
2402
2403         /* This is needed for PASS2 for Rx H/W checksum feature */
2404         sbmac_set_iphdr_offset(sc);
2405
2406         err = register_netdev(dev);
2407         if (err)
2408                 goto out_uninit;
2409
2410         if (sc->rx_hw_checksum == ENABLE) {
2411                 printk(KERN_INFO "%s: enabling TCP rcv checksum\n",
2412                         sc->sbm_dev->name);
2413         }
2414
2415         /*
2416          * Display Ethernet address (this is called during the config
2417          * process so we need to finish off the config message that
2418          * was being displayed)
2419          */
2420         printk(KERN_INFO
2421                "%s: SiByte Ethernet at 0x%08lX, address: %02X:%02X:%02X:%02X:%02X:%02X\n",
2422                dev->name, dev->base_addr,
2423                eaddr[0],eaddr[1],eaddr[2],eaddr[3],eaddr[4],eaddr[5]);
2424
2425
2426         return 0;
2427
2428 out_uninit:
2429         sbmac_uninitctx(sc);
2430
2431         return err;
2432 }
2433
2434
2435 static int sbmac_open(struct net_device *dev)
2436 {
2437         struct sbmac_softc *sc = netdev_priv(dev);
2438
2439         if (debug > 1) {
2440                 printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2441         }
2442
2443         /*
2444          * map/route interrupt (clear status first, in case something
2445          * weird is pending; we haven't initialized the mac registers
2446          * yet)
2447          */
2448
2449         __raw_readq(sc->sbm_isr);
2450         if (request_irq(dev->irq, &sbmac_intr, IRQF_SHARED, dev->name, dev))
2451                 return -EBUSY;
2452
2453         /*
2454          * Probe phy address
2455          */
2456
2457         if(sbmac_mii_probe(dev) == -1) {
2458                 printk("%s: failed to probe PHY.\n", dev->name);
2459                 return -EINVAL;
2460         }
2461
2462         /*
2463          * Configure default speed
2464          */
2465
2466         sbmac_mii_poll(sc,noisy_mii);
2467
2468         /*
2469          * Turn on the channel
2470          */
2471
2472         sbmac_set_channel_state(sc,sbmac_state_on);
2473
2474         /*
2475          * XXX Station address is in dev->dev_addr
2476          */
2477
2478         if (dev->if_port == 0)
2479                 dev->if_port = 0;
2480
2481         netif_start_queue(dev);
2482
2483         sbmac_set_rx_mode(dev);
2484
2485         /* Set the timer to check for link beat. */
2486         init_timer(&sc->sbm_timer);
2487         sc->sbm_timer.expires = jiffies + 2 * HZ/100;
2488         sc->sbm_timer.data = (unsigned long)dev;
2489         sc->sbm_timer.function = &sbmac_timer;
2490         add_timer(&sc->sbm_timer);
2491
2492         return 0;
2493 }
2494
2495 static int sbmac_mii_probe(struct net_device *dev)
2496 {
2497         int i;
2498         struct sbmac_softc *s = netdev_priv(dev);
2499         u16 bmsr, id1, id2;
2500         u32 vendor, device;
2501
2502         for (i=1; i<31; i++) {
2503         bmsr = sbmac_mii_read(s, i, MII_BMSR);
2504                 if (bmsr != 0) {
2505                         s->sbm_phys[0] = i;
2506                         id1 = sbmac_mii_read(s, i, MII_PHYIDR1);
2507                         id2 = sbmac_mii_read(s, i, MII_PHYIDR2);
2508                         vendor = ((u32)id1 << 6) | ((id2 >> 10) & 0x3f);
2509                         device = (id2 >> 4) & 0x3f;
2510
2511                         printk(KERN_INFO "%s: found phy %d, vendor %06x part %02x\n",
2512                                 dev->name, i, vendor, device);
2513                         return i;
2514                 }
2515         }
2516         return -1;
2517 }
2518
2519
2520 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy)
2521 {
2522     int bmsr,bmcr,k1stsr,anlpar;
2523     int chg;
2524     char buffer[100];
2525     char *p = buffer;
2526
2527     /* Read the mode status and mode control registers. */
2528     bmsr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMSR);
2529     bmcr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMCR);
2530
2531     /* get the link partner status */
2532     anlpar = sbmac_mii_read(s,s->sbm_phys[0],MII_ANLPAR);
2533
2534     /* if supported, read the 1000baseT register */
2535     if (bmsr & BMSR_1000BT_XSR) {
2536         k1stsr = sbmac_mii_read(s,s->sbm_phys[0],MII_K1STSR);
2537         }
2538     else {
2539         k1stsr = 0;
2540         }
2541
2542     chg = 0;
2543
2544     if ((bmsr & BMSR_LINKSTAT) == 0) {
2545         /*
2546          * If link status is down, clear out old info so that when
2547          * it comes back up it will force us to reconfigure speed
2548          */
2549         s->sbm_phy_oldbmsr = 0;
2550         s->sbm_phy_oldanlpar = 0;
2551         s->sbm_phy_oldk1stsr = 0;
2552         return 0;
2553         }
2554
2555     if ((s->sbm_phy_oldbmsr != bmsr) ||
2556         (s->sbm_phy_oldanlpar != anlpar) ||
2557         (s->sbm_phy_oldk1stsr != k1stsr)) {
2558         if (debug > 1) {
2559             printk(KERN_DEBUG "%s: bmsr:%x/%x anlpar:%x/%x  k1stsr:%x/%x\n",
2560                s->sbm_dev->name,
2561                s->sbm_phy_oldbmsr,bmsr,
2562                s->sbm_phy_oldanlpar,anlpar,
2563                s->sbm_phy_oldk1stsr,k1stsr);
2564             }
2565         s->sbm_phy_oldbmsr = bmsr;
2566         s->sbm_phy_oldanlpar = anlpar;
2567         s->sbm_phy_oldk1stsr = k1stsr;
2568         chg = 1;
2569         }
2570
2571     if (chg == 0)
2572             return 0;
2573
2574     p += sprintf(p,"Link speed: ");
2575
2576     if (k1stsr & K1STSR_LP1KFD) {
2577         s->sbm_speed = sbmac_speed_1000;
2578         s->sbm_duplex = sbmac_duplex_full;
2579         s->sbm_fc = sbmac_fc_frame;
2580         p += sprintf(p,"1000BaseT FDX");
2581         }
2582     else if (k1stsr & K1STSR_LP1KHD) {
2583         s->sbm_speed = sbmac_speed_1000;
2584         s->sbm_duplex = sbmac_duplex_half;
2585         s->sbm_fc = sbmac_fc_disabled;
2586         p += sprintf(p,"1000BaseT HDX");
2587         }
2588     else if (anlpar & ANLPAR_TXFD) {
2589         s->sbm_speed = sbmac_speed_100;
2590         s->sbm_duplex = sbmac_duplex_full;
2591         s->sbm_fc = (anlpar & ANLPAR_PAUSE) ? sbmac_fc_frame : sbmac_fc_disabled;
2592         p += sprintf(p,"100BaseT FDX");
2593         }
2594     else if (anlpar & ANLPAR_TXHD) {
2595         s->sbm_speed = sbmac_speed_100;
2596         s->sbm_duplex = sbmac_duplex_half;
2597         s->sbm_fc = sbmac_fc_disabled;
2598         p += sprintf(p,"100BaseT HDX");
2599         }
2600     else if (anlpar & ANLPAR_10FD) {
2601         s->sbm_speed = sbmac_speed_10;
2602         s->sbm_duplex = sbmac_duplex_full;
2603         s->sbm_fc = sbmac_fc_frame;
2604         p += sprintf(p,"10BaseT FDX");
2605         }
2606     else if (anlpar & ANLPAR_10HD) {
2607         s->sbm_speed = sbmac_speed_10;
2608         s->sbm_duplex = sbmac_duplex_half;
2609         s->sbm_fc = sbmac_fc_collision;
2610         p += sprintf(p,"10BaseT HDX");
2611         }
2612     else {
2613         p += sprintf(p,"Unknown");
2614         }
2615
2616     if (noisy) {
2617             printk(KERN_INFO "%s: %s\n",s->sbm_dev->name,buffer);
2618             }
2619
2620     return 1;
2621 }
2622
2623
2624 static void sbmac_timer(unsigned long data)
2625 {
2626         struct net_device *dev = (struct net_device *)data;
2627         struct sbmac_softc *sc = netdev_priv(dev);
2628         int next_tick = HZ;
2629         int mii_status;
2630
2631         spin_lock_irq (&sc->sbm_lock);
2632
2633         /* make IFF_RUNNING follow the MII status bit "Link established" */
2634         mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR);
2635
2636         if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) {
2637                 sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT;
2638                 if (mii_status & BMSR_LINKSTAT) {
2639                         netif_carrier_on(dev);
2640                 }
2641                 else {
2642                         netif_carrier_off(dev);
2643                 }
2644         }
2645
2646         /*
2647          * Poll the PHY to see what speed we should be running at
2648          */
2649
2650         if (sbmac_mii_poll(sc,noisy_mii)) {
2651                 if (sc->sbm_state != sbmac_state_off) {
2652                         /*
2653                          * something changed, restart the channel
2654                          */
2655                         if (debug > 1) {
2656                                 printk("%s: restarting channel because speed changed\n",
2657                                        sc->sbm_dev->name);
2658                         }
2659                         sbmac_channel_stop(sc);
2660                         sbmac_channel_start(sc);
2661                 }
2662         }
2663
2664         spin_unlock_irq (&sc->sbm_lock);
2665
2666         sc->sbm_timer.expires = jiffies + next_tick;
2667         add_timer(&sc->sbm_timer);
2668 }
2669
2670
2671 static void sbmac_tx_timeout (struct net_device *dev)
2672 {
2673         struct sbmac_softc *sc = netdev_priv(dev);
2674
2675         spin_lock_irq (&sc->sbm_lock);
2676
2677
2678         dev->trans_start = jiffies;
2679         sc->sbm_stats.tx_errors++;
2680
2681         spin_unlock_irq (&sc->sbm_lock);
2682
2683         printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
2684 }
2685
2686
2687
2688
2689 static struct net_device_stats *sbmac_get_stats(struct net_device *dev)
2690 {
2691         struct sbmac_softc *sc = netdev_priv(dev);
2692         unsigned long flags;
2693
2694         spin_lock_irqsave(&sc->sbm_lock, flags);
2695
2696         /* XXX update other stats here */
2697
2698         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2699
2700         return &sc->sbm_stats;
2701 }
2702
2703
2704
2705 static void sbmac_set_rx_mode(struct net_device *dev)
2706 {
2707         unsigned long flags;
2708         struct sbmac_softc *sc = netdev_priv(dev);
2709
2710         spin_lock_irqsave(&sc->sbm_lock, flags);
2711         if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
2712                 /*
2713                  * Promiscuous changed.
2714                  */
2715
2716                 if (dev->flags & IFF_PROMISC) {
2717                         sbmac_promiscuous_mode(sc,1);
2718                 }
2719                 else {
2720                         sbmac_promiscuous_mode(sc,0);
2721                 }
2722         }
2723         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2724
2725         /*
2726          * Program the multicasts.  Do this every time.
2727          */
2728
2729         sbmac_setmulti(sc);
2730
2731 }
2732
2733 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2734 {
2735         struct sbmac_softc *sc = netdev_priv(dev);
2736         u16 *data = (u16 *)&rq->ifr_ifru;
2737         unsigned long flags;
2738         int retval;
2739
2740         spin_lock_irqsave(&sc->sbm_lock, flags);
2741         retval = 0;
2742
2743         switch(cmd) {
2744         case SIOCDEVPRIVATE:            /* Get the address of the PHY in use. */
2745                 data[0] = sc->sbm_phys[0] & 0x1f;
2746                 /* Fall Through */
2747         case SIOCDEVPRIVATE+1:          /* Read the specified MII register. */
2748                 data[3] = sbmac_mii_read(sc, data[0] & 0x1f, data[1] & 0x1f);
2749                 break;
2750         case SIOCDEVPRIVATE+2:          /* Write the specified MII register */
2751                 if (!capable(CAP_NET_ADMIN)) {
2752                         retval = -EPERM;
2753                         break;
2754                 }
2755                 if (debug > 1) {
2756                     printk(KERN_DEBUG "%s: sbmac_mii_ioctl: write %02X %02X %02X\n",dev->name,
2757                        data[0],data[1],data[2]);
2758                     }
2759                 sbmac_mii_write(sc, data[0] & 0x1f, data[1] & 0x1f, data[2]);
2760                 break;
2761         default:
2762                 retval = -EOPNOTSUPP;
2763         }
2764
2765         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2766         return retval;
2767 }
2768
2769 static int sbmac_close(struct net_device *dev)
2770 {
2771         struct sbmac_softc *sc = netdev_priv(dev);
2772         unsigned long flags;
2773         int irq;
2774
2775         sbmac_set_channel_state(sc,sbmac_state_off);
2776
2777         del_timer_sync(&sc->sbm_timer);
2778
2779         spin_lock_irqsave(&sc->sbm_lock, flags);
2780
2781         netif_stop_queue(dev);
2782
2783         if (debug > 1) {
2784                 printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name);
2785         }
2786
2787         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2788
2789         irq = dev->irq;
2790         synchronize_irq(irq);
2791         free_irq(irq, dev);
2792
2793         sbdma_emptyring(&(sc->sbm_txdma));
2794         sbdma_emptyring(&(sc->sbm_rxdma));
2795
2796         return 0;
2797 }
2798
2799
2800
2801 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
2802 static void
2803 sbmac_setup_hwaddr(int chan,char *addr)
2804 {
2805         uint8_t eaddr[6];
2806         uint64_t val;
2807         unsigned long port;
2808
2809         port = A_MAC_CHANNEL_BASE(chan);
2810         sbmac_parse_hwaddr(addr,eaddr);
2811         val = sbmac_addr2reg(eaddr);
2812         __raw_writeq(val, IOADDR(port+R_MAC_ETHERNET_ADDR));
2813         val = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR));
2814 }
2815 #endif
2816
2817 static struct net_device *dev_sbmac[MAX_UNITS];
2818
2819 static int __init
2820 sbmac_init_module(void)
2821 {
2822         int idx;
2823         struct net_device *dev;
2824         unsigned long port;
2825         int chip_max_units;
2826
2827         /* Set the number of available units based on the SOC type.  */
2828         switch (soc_type) {
2829         case K_SYS_SOC_TYPE_BCM1250:
2830         case K_SYS_SOC_TYPE_BCM1250_ALT:
2831                 chip_max_units = 3;
2832                 break;
2833         case K_SYS_SOC_TYPE_BCM1120:
2834         case K_SYS_SOC_TYPE_BCM1125:
2835         case K_SYS_SOC_TYPE_BCM1125H:
2836         case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */
2837                 chip_max_units = 2;
2838                 break;
2839         case K_SYS_SOC_TYPE_BCM1x55:
2840         case K_SYS_SOC_TYPE_BCM1x80:
2841                 chip_max_units = 4;
2842                 break;
2843         default:
2844                 chip_max_units = 0;
2845                 break;
2846         }
2847         if (chip_max_units > MAX_UNITS)
2848                 chip_max_units = MAX_UNITS;
2849
2850         /*
2851          * For bringup when not using the firmware, we can pre-fill
2852          * the MAC addresses using the environment variables
2853          * specified in this file (or maybe from the config file?)
2854          */
2855 #ifdef SBMAC_ETH0_HWADDR
2856         if (chip_max_units > 0)
2857           sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR);
2858 #endif
2859 #ifdef SBMAC_ETH1_HWADDR
2860         if (chip_max_units > 1)
2861           sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR);
2862 #endif
2863 #ifdef SBMAC_ETH2_HWADDR
2864         if (chip_max_units > 2)
2865           sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR);
2866 #endif
2867 #ifdef SBMAC_ETH3_HWADDR
2868         if (chip_max_units > 3)
2869           sbmac_setup_hwaddr(3,SBMAC_ETH3_HWADDR);
2870 #endif
2871
2872         /*
2873          * Walk through the Ethernet controllers and find
2874          * those who have their MAC addresses set.
2875          */
2876         for (idx = 0; idx < chip_max_units; idx++) {
2877
2878                 /*
2879                  * This is the base address of the MAC.
2880                  */
2881
2882                 port = A_MAC_CHANNEL_BASE(idx);
2883
2884                 /*
2885                  * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2886                  * value for us by the firmware if we're going to use this MAC.
2887                  * If we find a zero, skip this MAC.
2888                  */
2889
2890                 sbmac_orig_hwaddr[idx] = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR));
2891                 if (sbmac_orig_hwaddr[idx] == 0) {
2892                         printk(KERN_DEBUG "sbmac: not configuring MAC at "
2893                                "%lx\n", port);
2894                     continue;
2895                 }
2896
2897                 /*
2898                  * Okay, cool.  Initialize this MAC.
2899                  */
2900
2901                 dev = alloc_etherdev(sizeof(struct sbmac_softc));
2902                 if (!dev)
2903                         return -ENOMEM;
2904
2905                 printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port);
2906
2907                 dev->irq = UNIT_INT(idx);
2908                 dev->base_addr = port;
2909                 dev->mem_end = 0;
2910                 if (sbmac_init(dev, idx)) {
2911                         port = A_MAC_CHANNEL_BASE(idx);
2912                         __raw_writeq(sbmac_orig_hwaddr[idx], IOADDR(port+R_MAC_ETHERNET_ADDR));
2913                         free_netdev(dev);
2914                         continue;
2915                 }
2916                 dev_sbmac[idx] = dev;
2917         }
2918         return 0;
2919 }
2920
2921
2922 static void __exit
2923 sbmac_cleanup_module(void)
2924 {
2925         struct net_device *dev;
2926         int idx;
2927
2928         for (idx = 0; idx < MAX_UNITS; idx++) {
2929                 struct sbmac_softc *sc;
2930                 dev = dev_sbmac[idx];
2931                 if (!dev)
2932                         continue;
2933
2934                 sc = netdev_priv(dev);
2935                 unregister_netdev(dev);
2936                 sbmac_uninitctx(sc);
2937                 free_netdev(dev);
2938         }
2939 }
2940
2941 module_init(sbmac_init_module);
2942 module_exit(sbmac_cleanup_module);