Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-2.6.git] / drivers / net / s2io.c
1 /************************************************************************
2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3  * Copyright(c) 2002-2010 Exar Corp.
4  *
5  * This software may be used and distributed according to the terms of
6  * the GNU General Public License (GPL), incorporated herein by reference.
7  * Drivers based on or derived from this code fall under the GPL and must
8  * retain the authorship, copyright and license notice.  This file is not
9  * a complete program and may only be used when the entire operating
10  * system is licensed under the GPL.
11  * See the file COPYING in this distribution for more information.
12  *
13  * Credits:
14  * Jeff Garzik          : For pointing out the improper error condition
15  *                        check in the s2io_xmit routine and also some
16  *                        issues in the Tx watch dog function. Also for
17  *                        patiently answering all those innumerable
18  *                        questions regaring the 2.6 porting issues.
19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
20  *                        macros available only in 2.6 Kernel.
21  * Francois Romieu      : For pointing out all code part that were
22  *                        deprecated and also styling related comments.
23  * Grant Grundler       : For helping me get rid of some Architecture
24  *                        dependent code.
25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
26  *
27  * The module loadable parameters that are supported by the driver and a brief
28  * explanation of all the variables.
29  *
30  * rx_ring_num : This can be used to program the number of receive rings used
31  * in the driver.
32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
33  *     This is also an array of size 8.
34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35  *              values are 1, 2.
36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
38  * Tx descriptors that can be associated with each corresponding FIFO.
39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40  *     2(MSI_X). Default value is '2(MSI_X)'
41  * lro_max_pkts: This parameter defines maximum number of packets can be
42  *     aggregated as a single large packet
43  * napi: This parameter used to enable/disable NAPI (polling Rx)
44  *     Possible values '1' for enable and '0' for disable. Default is '1'
45  * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
46  *      Possible values '1' for enable and '0' for disable. Default is '0'
47  * vlan_tag_strip: This can be used to enable or disable vlan stripping.
48  *                 Possible values '1' for enable , '0' for disable.
49  *                 Default is '2' - which means disable in promisc mode
50  *                 and enable in non-promiscuous mode.
51  * multiq: This parameter used to enable/disable MULTIQUEUE support.
52  *      Possible values '1' for enable and '0' for disable. Default is '0'
53  ************************************************************************/
54
55 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
56
57 #include <linux/module.h>
58 #include <linux/types.h>
59 #include <linux/errno.h>
60 #include <linux/ioport.h>
61 #include <linux/pci.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/kernel.h>
64 #include <linux/netdevice.h>
65 #include <linux/etherdevice.h>
66 #include <linux/mdio.h>
67 #include <linux/skbuff.h>
68 #include <linux/init.h>
69 #include <linux/delay.h>
70 #include <linux/stddef.h>
71 #include <linux/ioctl.h>
72 #include <linux/timex.h>
73 #include <linux/ethtool.h>
74 #include <linux/workqueue.h>
75 #include <linux/if_vlan.h>
76 #include <linux/ip.h>
77 #include <linux/tcp.h>
78 #include <linux/uaccess.h>
79 #include <linux/io.h>
80 #include <linux/slab.h>
81 #include <linux/prefetch.h>
82 #include <net/tcp.h>
83
84 #include <asm/system.h>
85 #include <asm/div64.h>
86 #include <asm/irq.h>
87
88 /* local include */
89 #include "s2io.h"
90 #include "s2io-regs.h"
91
92 #define DRV_VERSION "2.0.26.28"
93
94 /* S2io Driver name & version. */
95 static const char s2io_driver_name[] = "Neterion";
96 static const char s2io_driver_version[] = DRV_VERSION;
97
98 static const int rxd_size[2] = {32, 48};
99 static const int rxd_count[2] = {127, 85};
100
101 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
102 {
103         int ret;
104
105         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
106                (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
107
108         return ret;
109 }
110
111 /*
112  * Cards with following subsystem_id have a link state indication
113  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
114  * macro below identifies these cards given the subsystem_id.
115  */
116 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid)              \
117         (dev_type == XFRAME_I_DEVICE) ?                                 \
118         ((((subid >= 0x600B) && (subid <= 0x600D)) ||                   \
119           ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
120
121 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
122                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
123
124 static inline int is_s2io_card_up(const struct s2io_nic *sp)
125 {
126         return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
127 }
128
129 /* Ethtool related variables and Macros. */
130 static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
131         "Register test\t(offline)",
132         "Eeprom test\t(offline)",
133         "Link test\t(online)",
134         "RLDRAM test\t(offline)",
135         "BIST Test\t(offline)"
136 };
137
138 static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
139         {"tmac_frms"},
140         {"tmac_data_octets"},
141         {"tmac_drop_frms"},
142         {"tmac_mcst_frms"},
143         {"tmac_bcst_frms"},
144         {"tmac_pause_ctrl_frms"},
145         {"tmac_ttl_octets"},
146         {"tmac_ucst_frms"},
147         {"tmac_nucst_frms"},
148         {"tmac_any_err_frms"},
149         {"tmac_ttl_less_fb_octets"},
150         {"tmac_vld_ip_octets"},
151         {"tmac_vld_ip"},
152         {"tmac_drop_ip"},
153         {"tmac_icmp"},
154         {"tmac_rst_tcp"},
155         {"tmac_tcp"},
156         {"tmac_udp"},
157         {"rmac_vld_frms"},
158         {"rmac_data_octets"},
159         {"rmac_fcs_err_frms"},
160         {"rmac_drop_frms"},
161         {"rmac_vld_mcst_frms"},
162         {"rmac_vld_bcst_frms"},
163         {"rmac_in_rng_len_err_frms"},
164         {"rmac_out_rng_len_err_frms"},
165         {"rmac_long_frms"},
166         {"rmac_pause_ctrl_frms"},
167         {"rmac_unsup_ctrl_frms"},
168         {"rmac_ttl_octets"},
169         {"rmac_accepted_ucst_frms"},
170         {"rmac_accepted_nucst_frms"},
171         {"rmac_discarded_frms"},
172         {"rmac_drop_events"},
173         {"rmac_ttl_less_fb_octets"},
174         {"rmac_ttl_frms"},
175         {"rmac_usized_frms"},
176         {"rmac_osized_frms"},
177         {"rmac_frag_frms"},
178         {"rmac_jabber_frms"},
179         {"rmac_ttl_64_frms"},
180         {"rmac_ttl_65_127_frms"},
181         {"rmac_ttl_128_255_frms"},
182         {"rmac_ttl_256_511_frms"},
183         {"rmac_ttl_512_1023_frms"},
184         {"rmac_ttl_1024_1518_frms"},
185         {"rmac_ip"},
186         {"rmac_ip_octets"},
187         {"rmac_hdr_err_ip"},
188         {"rmac_drop_ip"},
189         {"rmac_icmp"},
190         {"rmac_tcp"},
191         {"rmac_udp"},
192         {"rmac_err_drp_udp"},
193         {"rmac_xgmii_err_sym"},
194         {"rmac_frms_q0"},
195         {"rmac_frms_q1"},
196         {"rmac_frms_q2"},
197         {"rmac_frms_q3"},
198         {"rmac_frms_q4"},
199         {"rmac_frms_q5"},
200         {"rmac_frms_q6"},
201         {"rmac_frms_q7"},
202         {"rmac_full_q0"},
203         {"rmac_full_q1"},
204         {"rmac_full_q2"},
205         {"rmac_full_q3"},
206         {"rmac_full_q4"},
207         {"rmac_full_q5"},
208         {"rmac_full_q6"},
209         {"rmac_full_q7"},
210         {"rmac_pause_cnt"},
211         {"rmac_xgmii_data_err_cnt"},
212         {"rmac_xgmii_ctrl_err_cnt"},
213         {"rmac_accepted_ip"},
214         {"rmac_err_tcp"},
215         {"rd_req_cnt"},
216         {"new_rd_req_cnt"},
217         {"new_rd_req_rtry_cnt"},
218         {"rd_rtry_cnt"},
219         {"wr_rtry_rd_ack_cnt"},
220         {"wr_req_cnt"},
221         {"new_wr_req_cnt"},
222         {"new_wr_req_rtry_cnt"},
223         {"wr_rtry_cnt"},
224         {"wr_disc_cnt"},
225         {"rd_rtry_wr_ack_cnt"},
226         {"txp_wr_cnt"},
227         {"txd_rd_cnt"},
228         {"txd_wr_cnt"},
229         {"rxd_rd_cnt"},
230         {"rxd_wr_cnt"},
231         {"txf_rd_cnt"},
232         {"rxf_wr_cnt"}
233 };
234
235 static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
236         {"rmac_ttl_1519_4095_frms"},
237         {"rmac_ttl_4096_8191_frms"},
238         {"rmac_ttl_8192_max_frms"},
239         {"rmac_ttl_gt_max_frms"},
240         {"rmac_osized_alt_frms"},
241         {"rmac_jabber_alt_frms"},
242         {"rmac_gt_max_alt_frms"},
243         {"rmac_vlan_frms"},
244         {"rmac_len_discard"},
245         {"rmac_fcs_discard"},
246         {"rmac_pf_discard"},
247         {"rmac_da_discard"},
248         {"rmac_red_discard"},
249         {"rmac_rts_discard"},
250         {"rmac_ingm_full_discard"},
251         {"link_fault_cnt"}
252 };
253
254 static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
255         {"\n DRIVER STATISTICS"},
256         {"single_bit_ecc_errs"},
257         {"double_bit_ecc_errs"},
258         {"parity_err_cnt"},
259         {"serious_err_cnt"},
260         {"soft_reset_cnt"},
261         {"fifo_full_cnt"},
262         {"ring_0_full_cnt"},
263         {"ring_1_full_cnt"},
264         {"ring_2_full_cnt"},
265         {"ring_3_full_cnt"},
266         {"ring_4_full_cnt"},
267         {"ring_5_full_cnt"},
268         {"ring_6_full_cnt"},
269         {"ring_7_full_cnt"},
270         {"alarm_transceiver_temp_high"},
271         {"alarm_transceiver_temp_low"},
272         {"alarm_laser_bias_current_high"},
273         {"alarm_laser_bias_current_low"},
274         {"alarm_laser_output_power_high"},
275         {"alarm_laser_output_power_low"},
276         {"warn_transceiver_temp_high"},
277         {"warn_transceiver_temp_low"},
278         {"warn_laser_bias_current_high"},
279         {"warn_laser_bias_current_low"},
280         {"warn_laser_output_power_high"},
281         {"warn_laser_output_power_low"},
282         {"lro_aggregated_pkts"},
283         {"lro_flush_both_count"},
284         {"lro_out_of_sequence_pkts"},
285         {"lro_flush_due_to_max_pkts"},
286         {"lro_avg_aggr_pkts"},
287         {"mem_alloc_fail_cnt"},
288         {"pci_map_fail_cnt"},
289         {"watchdog_timer_cnt"},
290         {"mem_allocated"},
291         {"mem_freed"},
292         {"link_up_cnt"},
293         {"link_down_cnt"},
294         {"link_up_time"},
295         {"link_down_time"},
296         {"tx_tcode_buf_abort_cnt"},
297         {"tx_tcode_desc_abort_cnt"},
298         {"tx_tcode_parity_err_cnt"},
299         {"tx_tcode_link_loss_cnt"},
300         {"tx_tcode_list_proc_err_cnt"},
301         {"rx_tcode_parity_err_cnt"},
302         {"rx_tcode_abort_cnt"},
303         {"rx_tcode_parity_abort_cnt"},
304         {"rx_tcode_rda_fail_cnt"},
305         {"rx_tcode_unkn_prot_cnt"},
306         {"rx_tcode_fcs_err_cnt"},
307         {"rx_tcode_buf_size_err_cnt"},
308         {"rx_tcode_rxd_corrupt_cnt"},
309         {"rx_tcode_unkn_err_cnt"},
310         {"tda_err_cnt"},
311         {"pfc_err_cnt"},
312         {"pcc_err_cnt"},
313         {"tti_err_cnt"},
314         {"tpa_err_cnt"},
315         {"sm_err_cnt"},
316         {"lso_err_cnt"},
317         {"mac_tmac_err_cnt"},
318         {"mac_rmac_err_cnt"},
319         {"xgxs_txgxs_err_cnt"},
320         {"xgxs_rxgxs_err_cnt"},
321         {"rc_err_cnt"},
322         {"prc_pcix_err_cnt"},
323         {"rpa_err_cnt"},
324         {"rda_err_cnt"},
325         {"rti_err_cnt"},
326         {"mc_err_cnt"}
327 };
328
329 #define S2IO_XENA_STAT_LEN      ARRAY_SIZE(ethtool_xena_stats_keys)
330 #define S2IO_ENHANCED_STAT_LEN  ARRAY_SIZE(ethtool_enhanced_stats_keys)
331 #define S2IO_DRIVER_STAT_LEN    ARRAY_SIZE(ethtool_driver_stats_keys)
332
333 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
334 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
335
336 #define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
337 #define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
338
339 #define S2IO_TEST_LEN   ARRAY_SIZE(s2io_gstrings)
340 #define S2IO_STRINGS_LEN        (S2IO_TEST_LEN * ETH_GSTRING_LEN)
341
342 #define S2IO_TIMER_CONF(timer, handle, arg, exp)        \
343         init_timer(&timer);                             \
344         timer.function = handle;                        \
345         timer.data = (unsigned long)arg;                \
346         mod_timer(&timer, (jiffies + exp))              \
347
348 /* copy mac addr to def_mac_addr array */
349 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
350 {
351         sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
352         sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
353         sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
354         sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
355         sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
356         sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
357 }
358
359 /* Add the vlan */
360 static void s2io_vlan_rx_register(struct net_device *dev,
361                                   struct vlan_group *grp)
362 {
363         int i;
364         struct s2io_nic *nic = netdev_priv(dev);
365         unsigned long flags[MAX_TX_FIFOS];
366         struct config_param *config = &nic->config;
367         struct mac_info *mac_control = &nic->mac_control;
368
369         for (i = 0; i < config->tx_fifo_num; i++) {
370                 struct fifo_info *fifo = &mac_control->fifos[i];
371
372                 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
373         }
374
375         nic->vlgrp = grp;
376
377         for (i = config->tx_fifo_num - 1; i >= 0; i--) {
378                 struct fifo_info *fifo = &mac_control->fifos[i];
379
380                 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
381         }
382 }
383
384 /* Unregister the vlan */
385 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
386 {
387         int i;
388         struct s2io_nic *nic = netdev_priv(dev);
389         unsigned long flags[MAX_TX_FIFOS];
390         struct config_param *config = &nic->config;
391         struct mac_info *mac_control = &nic->mac_control;
392
393         for (i = 0; i < config->tx_fifo_num; i++) {
394                 struct fifo_info *fifo = &mac_control->fifos[i];
395
396                 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
397         }
398
399         if (nic->vlgrp)
400                 vlan_group_set_device(nic->vlgrp, vid, NULL);
401
402         for (i = config->tx_fifo_num - 1; i >= 0; i--) {
403                 struct fifo_info *fifo = &mac_control->fifos[i];
404
405                 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
406         }
407 }
408
409 /*
410  * Constants to be programmed into the Xena's registers, to configure
411  * the XAUI.
412  */
413
414 #define END_SIGN        0x0
415 static const u64 herc_act_dtx_cfg[] = {
416         /* Set address */
417         0x8000051536750000ULL, 0x80000515367500E0ULL,
418         /* Write data */
419         0x8000051536750004ULL, 0x80000515367500E4ULL,
420         /* Set address */
421         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
422         /* Write data */
423         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
424         /* Set address */
425         0x801205150D440000ULL, 0x801205150D4400E0ULL,
426         /* Write data */
427         0x801205150D440004ULL, 0x801205150D4400E4ULL,
428         /* Set address */
429         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
430         /* Write data */
431         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
432         /* Done */
433         END_SIGN
434 };
435
436 static const u64 xena_dtx_cfg[] = {
437         /* Set address */
438         0x8000051500000000ULL, 0x80000515000000E0ULL,
439         /* Write data */
440         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
441         /* Set address */
442         0x8001051500000000ULL, 0x80010515000000E0ULL,
443         /* Write data */
444         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
445         /* Set address */
446         0x8002051500000000ULL, 0x80020515000000E0ULL,
447         /* Write data */
448         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
449         END_SIGN
450 };
451
452 /*
453  * Constants for Fixing the MacAddress problem seen mostly on
454  * Alpha machines.
455  */
456 static const u64 fix_mac[] = {
457         0x0060000000000000ULL, 0x0060600000000000ULL,
458         0x0040600000000000ULL, 0x0000600000000000ULL,
459         0x0020600000000000ULL, 0x0060600000000000ULL,
460         0x0020600000000000ULL, 0x0060600000000000ULL,
461         0x0020600000000000ULL, 0x0060600000000000ULL,
462         0x0020600000000000ULL, 0x0060600000000000ULL,
463         0x0020600000000000ULL, 0x0060600000000000ULL,
464         0x0020600000000000ULL, 0x0060600000000000ULL,
465         0x0020600000000000ULL, 0x0060600000000000ULL,
466         0x0020600000000000ULL, 0x0060600000000000ULL,
467         0x0020600000000000ULL, 0x0060600000000000ULL,
468         0x0020600000000000ULL, 0x0060600000000000ULL,
469         0x0020600000000000ULL, 0x0000600000000000ULL,
470         0x0040600000000000ULL, 0x0060600000000000ULL,
471         END_SIGN
472 };
473
474 MODULE_LICENSE("GPL");
475 MODULE_VERSION(DRV_VERSION);
476
477
478 /* Module Loadable parameters. */
479 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
480 S2IO_PARM_INT(rx_ring_num, 1);
481 S2IO_PARM_INT(multiq, 0);
482 S2IO_PARM_INT(rx_ring_mode, 1);
483 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
484 S2IO_PARM_INT(rmac_pause_time, 0x100);
485 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
486 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
487 S2IO_PARM_INT(shared_splits, 0);
488 S2IO_PARM_INT(tmac_util_period, 5);
489 S2IO_PARM_INT(rmac_util_period, 5);
490 S2IO_PARM_INT(l3l4hdr_size, 128);
491 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
492 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
493 /* Frequency of Rx desc syncs expressed as power of 2 */
494 S2IO_PARM_INT(rxsync_frequency, 3);
495 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
496 S2IO_PARM_INT(intr_type, 2);
497 /* Large receive offload feature */
498
499 /* Max pkts to be aggregated by LRO at one time. If not specified,
500  * aggregation happens until we hit max IP pkt size(64K)
501  */
502 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
503 S2IO_PARM_INT(indicate_max_pkts, 0);
504
505 S2IO_PARM_INT(napi, 1);
506 S2IO_PARM_INT(ufo, 0);
507 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
508
509 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
510 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
511 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
512 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
513 static unsigned int rts_frm_len[MAX_RX_RINGS] =
514 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
515
516 module_param_array(tx_fifo_len, uint, NULL, 0);
517 module_param_array(rx_ring_sz, uint, NULL, 0);
518 module_param_array(rts_frm_len, uint, NULL, 0);
519
520 /*
521  * S2IO device table.
522  * This table lists all the devices that this driver supports.
523  */
524 static DEFINE_PCI_DEVICE_TABLE(s2io_tbl) = {
525         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
526          PCI_ANY_ID, PCI_ANY_ID},
527         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
528          PCI_ANY_ID, PCI_ANY_ID},
529         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
530          PCI_ANY_ID, PCI_ANY_ID},
531         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
532          PCI_ANY_ID, PCI_ANY_ID},
533         {0,}
534 };
535
536 MODULE_DEVICE_TABLE(pci, s2io_tbl);
537
538 static struct pci_error_handlers s2io_err_handler = {
539         .error_detected = s2io_io_error_detected,
540         .slot_reset = s2io_io_slot_reset,
541         .resume = s2io_io_resume,
542 };
543
544 static struct pci_driver s2io_driver = {
545         .name = "S2IO",
546         .id_table = s2io_tbl,
547         .probe = s2io_init_nic,
548         .remove = __devexit_p(s2io_rem_nic),
549         .err_handler = &s2io_err_handler,
550 };
551
552 /* A simplifier macro used both by init and free shared_mem Fns(). */
553 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
554
555 /* netqueue manipulation helper functions */
556 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
557 {
558         if (!sp->config.multiq) {
559                 int i;
560
561                 for (i = 0; i < sp->config.tx_fifo_num; i++)
562                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
563         }
564         netif_tx_stop_all_queues(sp->dev);
565 }
566
567 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
568 {
569         if (!sp->config.multiq)
570                 sp->mac_control.fifos[fifo_no].queue_state =
571                         FIFO_QUEUE_STOP;
572
573         netif_tx_stop_all_queues(sp->dev);
574 }
575
576 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
577 {
578         if (!sp->config.multiq) {
579                 int i;
580
581                 for (i = 0; i < sp->config.tx_fifo_num; i++)
582                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
583         }
584         netif_tx_start_all_queues(sp->dev);
585 }
586
587 static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
588 {
589         if (!sp->config.multiq)
590                 sp->mac_control.fifos[fifo_no].queue_state =
591                         FIFO_QUEUE_START;
592
593         netif_tx_start_all_queues(sp->dev);
594 }
595
596 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
597 {
598         if (!sp->config.multiq) {
599                 int i;
600
601                 for (i = 0; i < sp->config.tx_fifo_num; i++)
602                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
603         }
604         netif_tx_wake_all_queues(sp->dev);
605 }
606
607 static inline void s2io_wake_tx_queue(
608         struct fifo_info *fifo, int cnt, u8 multiq)
609 {
610
611         if (multiq) {
612                 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
613                         netif_wake_subqueue(fifo->dev, fifo->fifo_no);
614         } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
615                 if (netif_queue_stopped(fifo->dev)) {
616                         fifo->queue_state = FIFO_QUEUE_START;
617                         netif_wake_queue(fifo->dev);
618                 }
619         }
620 }
621
622 /**
623  * init_shared_mem - Allocation and Initialization of Memory
624  * @nic: Device private variable.
625  * Description: The function allocates all the memory areas shared
626  * between the NIC and the driver. This includes Tx descriptors,
627  * Rx descriptors and the statistics block.
628  */
629
630 static int init_shared_mem(struct s2io_nic *nic)
631 {
632         u32 size;
633         void *tmp_v_addr, *tmp_v_addr_next;
634         dma_addr_t tmp_p_addr, tmp_p_addr_next;
635         struct RxD_block *pre_rxd_blk = NULL;
636         int i, j, blk_cnt;
637         int lst_size, lst_per_page;
638         struct net_device *dev = nic->dev;
639         unsigned long tmp;
640         struct buffAdd *ba;
641         struct config_param *config = &nic->config;
642         struct mac_info *mac_control = &nic->mac_control;
643         unsigned long long mem_allocated = 0;
644
645         /* Allocation and initialization of TXDLs in FIFOs */
646         size = 0;
647         for (i = 0; i < config->tx_fifo_num; i++) {
648                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
649
650                 size += tx_cfg->fifo_len;
651         }
652         if (size > MAX_AVAILABLE_TXDS) {
653                 DBG_PRINT(ERR_DBG,
654                           "Too many TxDs requested: %d, max supported: %d\n",
655                           size, MAX_AVAILABLE_TXDS);
656                 return -EINVAL;
657         }
658
659         size = 0;
660         for (i = 0; i < config->tx_fifo_num; i++) {
661                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
662
663                 size = tx_cfg->fifo_len;
664                 /*
665                  * Legal values are from 2 to 8192
666                  */
667                 if (size < 2) {
668                         DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
669                                   "Valid lengths are 2 through 8192\n",
670                                   i, size);
671                         return -EINVAL;
672                 }
673         }
674
675         lst_size = (sizeof(struct TxD) * config->max_txds);
676         lst_per_page = PAGE_SIZE / lst_size;
677
678         for (i = 0; i < config->tx_fifo_num; i++) {
679                 struct fifo_info *fifo = &mac_control->fifos[i];
680                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
681                 int fifo_len = tx_cfg->fifo_len;
682                 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
683
684                 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
685                 if (!fifo->list_info) {
686                         DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
687                         return -ENOMEM;
688                 }
689                 mem_allocated += list_holder_size;
690         }
691         for (i = 0; i < config->tx_fifo_num; i++) {
692                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
693                                                 lst_per_page);
694                 struct fifo_info *fifo = &mac_control->fifos[i];
695                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
696
697                 fifo->tx_curr_put_info.offset = 0;
698                 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
699                 fifo->tx_curr_get_info.offset = 0;
700                 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
701                 fifo->fifo_no = i;
702                 fifo->nic = nic;
703                 fifo->max_txds = MAX_SKB_FRAGS + 2;
704                 fifo->dev = dev;
705
706                 for (j = 0; j < page_num; j++) {
707                         int k = 0;
708                         dma_addr_t tmp_p;
709                         void *tmp_v;
710                         tmp_v = pci_alloc_consistent(nic->pdev,
711                                                      PAGE_SIZE, &tmp_p);
712                         if (!tmp_v) {
713                                 DBG_PRINT(INFO_DBG,
714                                           "pci_alloc_consistent failed for TxDL\n");
715                                 return -ENOMEM;
716                         }
717                         /* If we got a zero DMA address(can happen on
718                          * certain platforms like PPC), reallocate.
719                          * Store virtual address of page we don't want,
720                          * to be freed later.
721                          */
722                         if (!tmp_p) {
723                                 mac_control->zerodma_virt_addr = tmp_v;
724                                 DBG_PRINT(INIT_DBG,
725                                           "%s: Zero DMA address for TxDL. "
726                                           "Virtual address %p\n",
727                                           dev->name, tmp_v);
728                                 tmp_v = pci_alloc_consistent(nic->pdev,
729                                                              PAGE_SIZE, &tmp_p);
730                                 if (!tmp_v) {
731                                         DBG_PRINT(INFO_DBG,
732                                                   "pci_alloc_consistent failed for TxDL\n");
733                                         return -ENOMEM;
734                                 }
735                                 mem_allocated += PAGE_SIZE;
736                         }
737                         while (k < lst_per_page) {
738                                 int l = (j * lst_per_page) + k;
739                                 if (l == tx_cfg->fifo_len)
740                                         break;
741                                 fifo->list_info[l].list_virt_addr =
742                                         tmp_v + (k * lst_size);
743                                 fifo->list_info[l].list_phy_addr =
744                                         tmp_p + (k * lst_size);
745                                 k++;
746                         }
747                 }
748         }
749
750         for (i = 0; i < config->tx_fifo_num; i++) {
751                 struct fifo_info *fifo = &mac_control->fifos[i];
752                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
753
754                 size = tx_cfg->fifo_len;
755                 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
756                 if (!fifo->ufo_in_band_v)
757                         return -ENOMEM;
758                 mem_allocated += (size * sizeof(u64));
759         }
760
761         /* Allocation and initialization of RXDs in Rings */
762         size = 0;
763         for (i = 0; i < config->rx_ring_num; i++) {
764                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
765                 struct ring_info *ring = &mac_control->rings[i];
766
767                 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
768                         DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
769                                   "multiple of RxDs per Block\n",
770                                   dev->name, i);
771                         return FAILURE;
772                 }
773                 size += rx_cfg->num_rxd;
774                 ring->block_count = rx_cfg->num_rxd /
775                         (rxd_count[nic->rxd_mode] + 1);
776                 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
777         }
778         if (nic->rxd_mode == RXD_MODE_1)
779                 size = (size * (sizeof(struct RxD1)));
780         else
781                 size = (size * (sizeof(struct RxD3)));
782
783         for (i = 0; i < config->rx_ring_num; i++) {
784                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
785                 struct ring_info *ring = &mac_control->rings[i];
786
787                 ring->rx_curr_get_info.block_index = 0;
788                 ring->rx_curr_get_info.offset = 0;
789                 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
790                 ring->rx_curr_put_info.block_index = 0;
791                 ring->rx_curr_put_info.offset = 0;
792                 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
793                 ring->nic = nic;
794                 ring->ring_no = i;
795
796                 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
797                 /*  Allocating all the Rx blocks */
798                 for (j = 0; j < blk_cnt; j++) {
799                         struct rx_block_info *rx_blocks;
800                         int l;
801
802                         rx_blocks = &ring->rx_blocks[j];
803                         size = SIZE_OF_BLOCK;   /* size is always page size */
804                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
805                                                           &tmp_p_addr);
806                         if (tmp_v_addr == NULL) {
807                                 /*
808                                  * In case of failure, free_shared_mem()
809                                  * is called, which should free any
810                                  * memory that was alloced till the
811                                  * failure happened.
812                                  */
813                                 rx_blocks->block_virt_addr = tmp_v_addr;
814                                 return -ENOMEM;
815                         }
816                         mem_allocated += size;
817                         memset(tmp_v_addr, 0, size);
818
819                         size = sizeof(struct rxd_info) *
820                                 rxd_count[nic->rxd_mode];
821                         rx_blocks->block_virt_addr = tmp_v_addr;
822                         rx_blocks->block_dma_addr = tmp_p_addr;
823                         rx_blocks->rxds = kmalloc(size,  GFP_KERNEL);
824                         if (!rx_blocks->rxds)
825                                 return -ENOMEM;
826                         mem_allocated += size;
827                         for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
828                                 rx_blocks->rxds[l].virt_addr =
829                                         rx_blocks->block_virt_addr +
830                                         (rxd_size[nic->rxd_mode] * l);
831                                 rx_blocks->rxds[l].dma_addr =
832                                         rx_blocks->block_dma_addr +
833                                         (rxd_size[nic->rxd_mode] * l);
834                         }
835                 }
836                 /* Interlinking all Rx Blocks */
837                 for (j = 0; j < blk_cnt; j++) {
838                         int next = (j + 1) % blk_cnt;
839                         tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
840                         tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
841                         tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
842                         tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
843
844                         pre_rxd_blk = (struct RxD_block *)tmp_v_addr;
845                         pre_rxd_blk->reserved_2_pNext_RxD_block =
846                                 (unsigned long)tmp_v_addr_next;
847                         pre_rxd_blk->pNext_RxD_Blk_physical =
848                                 (u64)tmp_p_addr_next;
849                 }
850         }
851         if (nic->rxd_mode == RXD_MODE_3B) {
852                 /*
853                  * Allocation of Storages for buffer addresses in 2BUFF mode
854                  * and the buffers as well.
855                  */
856                 for (i = 0; i < config->rx_ring_num; i++) {
857                         struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
858                         struct ring_info *ring = &mac_control->rings[i];
859
860                         blk_cnt = rx_cfg->num_rxd /
861                                 (rxd_count[nic->rxd_mode] + 1);
862                         size = sizeof(struct buffAdd *) * blk_cnt;
863                         ring->ba = kmalloc(size, GFP_KERNEL);
864                         if (!ring->ba)
865                                 return -ENOMEM;
866                         mem_allocated += size;
867                         for (j = 0; j < blk_cnt; j++) {
868                                 int k = 0;
869
870                                 size = sizeof(struct buffAdd) *
871                                         (rxd_count[nic->rxd_mode] + 1);
872                                 ring->ba[j] = kmalloc(size, GFP_KERNEL);
873                                 if (!ring->ba[j])
874                                         return -ENOMEM;
875                                 mem_allocated += size;
876                                 while (k != rxd_count[nic->rxd_mode]) {
877                                         ba = &ring->ba[j][k];
878                                         size = BUF0_LEN + ALIGN_SIZE;
879                                         ba->ba_0_org = kmalloc(size, GFP_KERNEL);
880                                         if (!ba->ba_0_org)
881                                                 return -ENOMEM;
882                                         mem_allocated += size;
883                                         tmp = (unsigned long)ba->ba_0_org;
884                                         tmp += ALIGN_SIZE;
885                                         tmp &= ~((unsigned long)ALIGN_SIZE);
886                                         ba->ba_0 = (void *)tmp;
887
888                                         size = BUF1_LEN + ALIGN_SIZE;
889                                         ba->ba_1_org = kmalloc(size, GFP_KERNEL);
890                                         if (!ba->ba_1_org)
891                                                 return -ENOMEM;
892                                         mem_allocated += size;
893                                         tmp = (unsigned long)ba->ba_1_org;
894                                         tmp += ALIGN_SIZE;
895                                         tmp &= ~((unsigned long)ALIGN_SIZE);
896                                         ba->ba_1 = (void *)tmp;
897                                         k++;
898                                 }
899                         }
900                 }
901         }
902
903         /* Allocation and initialization of Statistics block */
904         size = sizeof(struct stat_block);
905         mac_control->stats_mem =
906                 pci_alloc_consistent(nic->pdev, size,
907                                      &mac_control->stats_mem_phy);
908
909         if (!mac_control->stats_mem) {
910                 /*
911                  * In case of failure, free_shared_mem() is called, which
912                  * should free any memory that was alloced till the
913                  * failure happened.
914                  */
915                 return -ENOMEM;
916         }
917         mem_allocated += size;
918         mac_control->stats_mem_sz = size;
919
920         tmp_v_addr = mac_control->stats_mem;
921         mac_control->stats_info = (struct stat_block *)tmp_v_addr;
922         memset(tmp_v_addr, 0, size);
923         DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n",
924                 dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr);
925         mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
926         return SUCCESS;
927 }
928
929 /**
930  * free_shared_mem - Free the allocated Memory
931  * @nic:  Device private variable.
932  * Description: This function is to free all memory locations allocated by
933  * the init_shared_mem() function and return it to the kernel.
934  */
935
936 static void free_shared_mem(struct s2io_nic *nic)
937 {
938         int i, j, blk_cnt, size;
939         void *tmp_v_addr;
940         dma_addr_t tmp_p_addr;
941         int lst_size, lst_per_page;
942         struct net_device *dev;
943         int page_num = 0;
944         struct config_param *config;
945         struct mac_info *mac_control;
946         struct stat_block *stats;
947         struct swStat *swstats;
948
949         if (!nic)
950                 return;
951
952         dev = nic->dev;
953
954         config = &nic->config;
955         mac_control = &nic->mac_control;
956         stats = mac_control->stats_info;
957         swstats = &stats->sw_stat;
958
959         lst_size = sizeof(struct TxD) * config->max_txds;
960         lst_per_page = PAGE_SIZE / lst_size;
961
962         for (i = 0; i < config->tx_fifo_num; i++) {
963                 struct fifo_info *fifo = &mac_control->fifos[i];
964                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
965
966                 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
967                 for (j = 0; j < page_num; j++) {
968                         int mem_blks = (j * lst_per_page);
969                         struct list_info_hold *fli;
970
971                         if (!fifo->list_info)
972                                 return;
973
974                         fli = &fifo->list_info[mem_blks];
975                         if (!fli->list_virt_addr)
976                                 break;
977                         pci_free_consistent(nic->pdev, PAGE_SIZE,
978                                             fli->list_virt_addr,
979                                             fli->list_phy_addr);
980                         swstats->mem_freed += PAGE_SIZE;
981                 }
982                 /* If we got a zero DMA address during allocation,
983                  * free the page now
984                  */
985                 if (mac_control->zerodma_virt_addr) {
986                         pci_free_consistent(nic->pdev, PAGE_SIZE,
987                                             mac_control->zerodma_virt_addr,
988                                             (dma_addr_t)0);
989                         DBG_PRINT(INIT_DBG,
990                                   "%s: Freeing TxDL with zero DMA address. "
991                                   "Virtual address %p\n",
992                                   dev->name, mac_control->zerodma_virt_addr);
993                         swstats->mem_freed += PAGE_SIZE;
994                 }
995                 kfree(fifo->list_info);
996                 swstats->mem_freed += tx_cfg->fifo_len *
997                         sizeof(struct list_info_hold);
998         }
999
1000         size = SIZE_OF_BLOCK;
1001         for (i = 0; i < config->rx_ring_num; i++) {
1002                 struct ring_info *ring = &mac_control->rings[i];
1003
1004                 blk_cnt = ring->block_count;
1005                 for (j = 0; j < blk_cnt; j++) {
1006                         tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1007                         tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1008                         if (tmp_v_addr == NULL)
1009                                 break;
1010                         pci_free_consistent(nic->pdev, size,
1011                                             tmp_v_addr, tmp_p_addr);
1012                         swstats->mem_freed += size;
1013                         kfree(ring->rx_blocks[j].rxds);
1014                         swstats->mem_freed += sizeof(struct rxd_info) *
1015                                 rxd_count[nic->rxd_mode];
1016                 }
1017         }
1018
1019         if (nic->rxd_mode == RXD_MODE_3B) {
1020                 /* Freeing buffer storage addresses in 2BUFF mode. */
1021                 for (i = 0; i < config->rx_ring_num; i++) {
1022                         struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1023                         struct ring_info *ring = &mac_control->rings[i];
1024
1025                         blk_cnt = rx_cfg->num_rxd /
1026                                 (rxd_count[nic->rxd_mode] + 1);
1027                         for (j = 0; j < blk_cnt; j++) {
1028                                 int k = 0;
1029                                 if (!ring->ba[j])
1030                                         continue;
1031                                 while (k != rxd_count[nic->rxd_mode]) {
1032                                         struct buffAdd *ba = &ring->ba[j][k];
1033                                         kfree(ba->ba_0_org);
1034                                         swstats->mem_freed +=
1035                                                 BUF0_LEN + ALIGN_SIZE;
1036                                         kfree(ba->ba_1_org);
1037                                         swstats->mem_freed +=
1038                                                 BUF1_LEN + ALIGN_SIZE;
1039                                         k++;
1040                                 }
1041                                 kfree(ring->ba[j]);
1042                                 swstats->mem_freed += sizeof(struct buffAdd) *
1043                                         (rxd_count[nic->rxd_mode] + 1);
1044                         }
1045                         kfree(ring->ba);
1046                         swstats->mem_freed += sizeof(struct buffAdd *) *
1047                                 blk_cnt;
1048                 }
1049         }
1050
1051         for (i = 0; i < nic->config.tx_fifo_num; i++) {
1052                 struct fifo_info *fifo = &mac_control->fifos[i];
1053                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1054
1055                 if (fifo->ufo_in_band_v) {
1056                         swstats->mem_freed += tx_cfg->fifo_len *
1057                                 sizeof(u64);
1058                         kfree(fifo->ufo_in_band_v);
1059                 }
1060         }
1061
1062         if (mac_control->stats_mem) {
1063                 swstats->mem_freed += mac_control->stats_mem_sz;
1064                 pci_free_consistent(nic->pdev,
1065                                     mac_control->stats_mem_sz,
1066                                     mac_control->stats_mem,
1067                                     mac_control->stats_mem_phy);
1068         }
1069 }
1070
1071 /**
1072  * s2io_verify_pci_mode -
1073  */
1074
1075 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1076 {
1077         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1078         register u64 val64 = 0;
1079         int     mode;
1080
1081         val64 = readq(&bar0->pci_mode);
1082         mode = (u8)GET_PCI_MODE(val64);
1083
1084         if (val64 & PCI_MODE_UNKNOWN_MODE)
1085                 return -1;      /* Unknown PCI mode */
1086         return mode;
1087 }
1088
1089 #define NEC_VENID   0x1033
1090 #define NEC_DEVID   0x0125
1091 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1092 {
1093         struct pci_dev *tdev = NULL;
1094         while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1095                 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1096                         if (tdev->bus == s2io_pdev->bus->parent) {
1097                                 pci_dev_put(tdev);
1098                                 return 1;
1099                         }
1100                 }
1101         }
1102         return 0;
1103 }
1104
1105 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1106 /**
1107  * s2io_print_pci_mode -
1108  */
1109 static int s2io_print_pci_mode(struct s2io_nic *nic)
1110 {
1111         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1112         register u64 val64 = 0;
1113         int     mode;
1114         struct config_param *config = &nic->config;
1115         const char *pcimode;
1116
1117         val64 = readq(&bar0->pci_mode);
1118         mode = (u8)GET_PCI_MODE(val64);
1119
1120         if (val64 & PCI_MODE_UNKNOWN_MODE)
1121                 return -1;      /* Unknown PCI mode */
1122
1123         config->bus_speed = bus_speed[mode];
1124
1125         if (s2io_on_nec_bridge(nic->pdev)) {
1126                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1127                           nic->dev->name);
1128                 return mode;
1129         }
1130
1131         switch (mode) {
1132         case PCI_MODE_PCI_33:
1133                 pcimode = "33MHz PCI bus";
1134                 break;
1135         case PCI_MODE_PCI_66:
1136                 pcimode = "66MHz PCI bus";
1137                 break;
1138         case PCI_MODE_PCIX_M1_66:
1139                 pcimode = "66MHz PCIX(M1) bus";
1140                 break;
1141         case PCI_MODE_PCIX_M1_100:
1142                 pcimode = "100MHz PCIX(M1) bus";
1143                 break;
1144         case PCI_MODE_PCIX_M1_133:
1145                 pcimode = "133MHz PCIX(M1) bus";
1146                 break;
1147         case PCI_MODE_PCIX_M2_66:
1148                 pcimode = "133MHz PCIX(M2) bus";
1149                 break;
1150         case PCI_MODE_PCIX_M2_100:
1151                 pcimode = "200MHz PCIX(M2) bus";
1152                 break;
1153         case PCI_MODE_PCIX_M2_133:
1154                 pcimode = "266MHz PCIX(M2) bus";
1155                 break;
1156         default:
1157                 pcimode = "unsupported bus!";
1158                 mode = -1;
1159         }
1160
1161         DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1162                   nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1163
1164         return mode;
1165 }
1166
1167 /**
1168  *  init_tti - Initialization transmit traffic interrupt scheme
1169  *  @nic: device private variable
1170  *  @link: link status (UP/DOWN) used to enable/disable continuous
1171  *  transmit interrupts
1172  *  Description: The function configures transmit traffic interrupts
1173  *  Return Value:  SUCCESS on success and
1174  *  '-1' on failure
1175  */
1176
1177 static int init_tti(struct s2io_nic *nic, int link)
1178 {
1179         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1180         register u64 val64 = 0;
1181         int i;
1182         struct config_param *config = &nic->config;
1183
1184         for (i = 0; i < config->tx_fifo_num; i++) {
1185                 /*
1186                  * TTI Initialization. Default Tx timer gets us about
1187                  * 250 interrupts per sec. Continuous interrupts are enabled
1188                  * by default.
1189                  */
1190                 if (nic->device_type == XFRAME_II_DEVICE) {
1191                         int count = (nic->config.bus_speed * 125)/2;
1192                         val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1193                 } else
1194                         val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1195
1196                 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1197                         TTI_DATA1_MEM_TX_URNG_B(0x10) |
1198                         TTI_DATA1_MEM_TX_URNG_C(0x30) |
1199                         TTI_DATA1_MEM_TX_TIMER_AC_EN;
1200                 if (i == 0)
1201                         if (use_continuous_tx_intrs && (link == LINK_UP))
1202                                 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1203                 writeq(val64, &bar0->tti_data1_mem);
1204
1205                 if (nic->config.intr_type == MSI_X) {
1206                         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1207                                 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1208                                 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1209                                 TTI_DATA2_MEM_TX_UFC_D(0x300);
1210                 } else {
1211                         if ((nic->config.tx_steering_type ==
1212                              TX_DEFAULT_STEERING) &&
1213                             (config->tx_fifo_num > 1) &&
1214                             (i >= nic->udp_fifo_idx) &&
1215                             (i < (nic->udp_fifo_idx +
1216                                   nic->total_udp_fifos)))
1217                                 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1218                                         TTI_DATA2_MEM_TX_UFC_B(0x80) |
1219                                         TTI_DATA2_MEM_TX_UFC_C(0x100) |
1220                                         TTI_DATA2_MEM_TX_UFC_D(0x120);
1221                         else
1222                                 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1223                                         TTI_DATA2_MEM_TX_UFC_B(0x20) |
1224                                         TTI_DATA2_MEM_TX_UFC_C(0x40) |
1225                                         TTI_DATA2_MEM_TX_UFC_D(0x80);
1226                 }
1227
1228                 writeq(val64, &bar0->tti_data2_mem);
1229
1230                 val64 = TTI_CMD_MEM_WE |
1231                         TTI_CMD_MEM_STROBE_NEW_CMD |
1232                         TTI_CMD_MEM_OFFSET(i);
1233                 writeq(val64, &bar0->tti_command_mem);
1234
1235                 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1236                                           TTI_CMD_MEM_STROBE_NEW_CMD,
1237                                           S2IO_BIT_RESET) != SUCCESS)
1238                         return FAILURE;
1239         }
1240
1241         return SUCCESS;
1242 }
1243
1244 /**
1245  *  init_nic - Initialization of hardware
1246  *  @nic: device private variable
1247  *  Description: The function sequentially configures every block
1248  *  of the H/W from their reset values.
1249  *  Return Value:  SUCCESS on success and
1250  *  '-1' on failure (endian settings incorrect).
1251  */
1252
1253 static int init_nic(struct s2io_nic *nic)
1254 {
1255         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1256         struct net_device *dev = nic->dev;
1257         register u64 val64 = 0;
1258         void __iomem *add;
1259         u32 time;
1260         int i, j;
1261         int dtx_cnt = 0;
1262         unsigned long long mem_share;
1263         int mem_size;
1264         struct config_param *config = &nic->config;
1265         struct mac_info *mac_control = &nic->mac_control;
1266
1267         /* to set the swapper controle on the card */
1268         if (s2io_set_swapper(nic)) {
1269                 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
1270                 return -EIO;
1271         }
1272
1273         /*
1274          * Herc requires EOI to be removed from reset before XGXS, so..
1275          */
1276         if (nic->device_type & XFRAME_II_DEVICE) {
1277                 val64 = 0xA500000000ULL;
1278                 writeq(val64, &bar0->sw_reset);
1279                 msleep(500);
1280                 val64 = readq(&bar0->sw_reset);
1281         }
1282
1283         /* Remove XGXS from reset state */
1284         val64 = 0;
1285         writeq(val64, &bar0->sw_reset);
1286         msleep(500);
1287         val64 = readq(&bar0->sw_reset);
1288
1289         /* Ensure that it's safe to access registers by checking
1290          * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1291          */
1292         if (nic->device_type == XFRAME_II_DEVICE) {
1293                 for (i = 0; i < 50; i++) {
1294                         val64 = readq(&bar0->adapter_status);
1295                         if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1296                                 break;
1297                         msleep(10);
1298                 }
1299                 if (i == 50)
1300                         return -ENODEV;
1301         }
1302
1303         /*  Enable Receiving broadcasts */
1304         add = &bar0->mac_cfg;
1305         val64 = readq(&bar0->mac_cfg);
1306         val64 |= MAC_RMAC_BCAST_ENABLE;
1307         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1308         writel((u32)val64, add);
1309         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1310         writel((u32) (val64 >> 32), (add + 4));
1311
1312         /* Read registers in all blocks */
1313         val64 = readq(&bar0->mac_int_mask);
1314         val64 = readq(&bar0->mc_int_mask);
1315         val64 = readq(&bar0->xgxs_int_mask);
1316
1317         /*  Set MTU */
1318         val64 = dev->mtu;
1319         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1320
1321         if (nic->device_type & XFRAME_II_DEVICE) {
1322                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1323                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1324                                           &bar0->dtx_control, UF);
1325                         if (dtx_cnt & 0x1)
1326                                 msleep(1); /* Necessary!! */
1327                         dtx_cnt++;
1328                 }
1329         } else {
1330                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1331                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1332                                           &bar0->dtx_control, UF);
1333                         val64 = readq(&bar0->dtx_control);
1334                         dtx_cnt++;
1335                 }
1336         }
1337
1338         /*  Tx DMA Initialization */
1339         val64 = 0;
1340         writeq(val64, &bar0->tx_fifo_partition_0);
1341         writeq(val64, &bar0->tx_fifo_partition_1);
1342         writeq(val64, &bar0->tx_fifo_partition_2);
1343         writeq(val64, &bar0->tx_fifo_partition_3);
1344
1345         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1346                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1347
1348                 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1349                         vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1350
1351                 if (i == (config->tx_fifo_num - 1)) {
1352                         if (i % 2 == 0)
1353                                 i++;
1354                 }
1355
1356                 switch (i) {
1357                 case 1:
1358                         writeq(val64, &bar0->tx_fifo_partition_0);
1359                         val64 = 0;
1360                         j = 0;
1361                         break;
1362                 case 3:
1363                         writeq(val64, &bar0->tx_fifo_partition_1);
1364                         val64 = 0;
1365                         j = 0;
1366                         break;
1367                 case 5:
1368                         writeq(val64, &bar0->tx_fifo_partition_2);
1369                         val64 = 0;
1370                         j = 0;
1371                         break;
1372                 case 7:
1373                         writeq(val64, &bar0->tx_fifo_partition_3);
1374                         val64 = 0;
1375                         j = 0;
1376                         break;
1377                 default:
1378                         j++;
1379                         break;
1380                 }
1381         }
1382
1383         /*
1384          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1385          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1386          */
1387         if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
1388                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1389
1390         val64 = readq(&bar0->tx_fifo_partition_0);
1391         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1392                   &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1393
1394         /*
1395          * Initialization of Tx_PA_CONFIG register to ignore packet
1396          * integrity checking.
1397          */
1398         val64 = readq(&bar0->tx_pa_cfg);
1399         val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1400                 TX_PA_CFG_IGNORE_SNAP_OUI |
1401                 TX_PA_CFG_IGNORE_LLC_CTRL |
1402                 TX_PA_CFG_IGNORE_L2_ERR;
1403         writeq(val64, &bar0->tx_pa_cfg);
1404
1405         /* Rx DMA intialization. */
1406         val64 = 0;
1407         for (i = 0; i < config->rx_ring_num; i++) {
1408                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1409
1410                 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1411         }
1412         writeq(val64, &bar0->rx_queue_priority);
1413
1414         /*
1415          * Allocating equal share of memory to all the
1416          * configured Rings.
1417          */
1418         val64 = 0;
1419         if (nic->device_type & XFRAME_II_DEVICE)
1420                 mem_size = 32;
1421         else
1422                 mem_size = 64;
1423
1424         for (i = 0; i < config->rx_ring_num; i++) {
1425                 switch (i) {
1426                 case 0:
1427                         mem_share = (mem_size / config->rx_ring_num +
1428                                      mem_size % config->rx_ring_num);
1429                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1430                         continue;
1431                 case 1:
1432                         mem_share = (mem_size / config->rx_ring_num);
1433                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1434                         continue;
1435                 case 2:
1436                         mem_share = (mem_size / config->rx_ring_num);
1437                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1438                         continue;
1439                 case 3:
1440                         mem_share = (mem_size / config->rx_ring_num);
1441                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1442                         continue;
1443                 case 4:
1444                         mem_share = (mem_size / config->rx_ring_num);
1445                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1446                         continue;
1447                 case 5:
1448                         mem_share = (mem_size / config->rx_ring_num);
1449                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1450                         continue;
1451                 case 6:
1452                         mem_share = (mem_size / config->rx_ring_num);
1453                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1454                         continue;
1455                 case 7:
1456                         mem_share = (mem_size / config->rx_ring_num);
1457                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1458                         continue;
1459                 }
1460         }
1461         writeq(val64, &bar0->rx_queue_cfg);
1462
1463         /*
1464          * Filling Tx round robin registers
1465          * as per the number of FIFOs for equal scheduling priority
1466          */
1467         switch (config->tx_fifo_num) {
1468         case 1:
1469                 val64 = 0x0;
1470                 writeq(val64, &bar0->tx_w_round_robin_0);
1471                 writeq(val64, &bar0->tx_w_round_robin_1);
1472                 writeq(val64, &bar0->tx_w_round_robin_2);
1473                 writeq(val64, &bar0->tx_w_round_robin_3);
1474                 writeq(val64, &bar0->tx_w_round_robin_4);
1475                 break;
1476         case 2:
1477                 val64 = 0x0001000100010001ULL;
1478                 writeq(val64, &bar0->tx_w_round_robin_0);
1479                 writeq(val64, &bar0->tx_w_round_robin_1);
1480                 writeq(val64, &bar0->tx_w_round_robin_2);
1481                 writeq(val64, &bar0->tx_w_round_robin_3);
1482                 val64 = 0x0001000100000000ULL;
1483                 writeq(val64, &bar0->tx_w_round_robin_4);
1484                 break;
1485         case 3:
1486                 val64 = 0x0001020001020001ULL;
1487                 writeq(val64, &bar0->tx_w_round_robin_0);
1488                 val64 = 0x0200010200010200ULL;
1489                 writeq(val64, &bar0->tx_w_round_robin_1);
1490                 val64 = 0x0102000102000102ULL;
1491                 writeq(val64, &bar0->tx_w_round_robin_2);
1492                 val64 = 0x0001020001020001ULL;
1493                 writeq(val64, &bar0->tx_w_round_robin_3);
1494                 val64 = 0x0200010200000000ULL;
1495                 writeq(val64, &bar0->tx_w_round_robin_4);
1496                 break;
1497         case 4:
1498                 val64 = 0x0001020300010203ULL;
1499                 writeq(val64, &bar0->tx_w_round_robin_0);
1500                 writeq(val64, &bar0->tx_w_round_robin_1);
1501                 writeq(val64, &bar0->tx_w_round_robin_2);
1502                 writeq(val64, &bar0->tx_w_round_robin_3);
1503                 val64 = 0x0001020300000000ULL;
1504                 writeq(val64, &bar0->tx_w_round_robin_4);
1505                 break;
1506         case 5:
1507                 val64 = 0x0001020304000102ULL;
1508                 writeq(val64, &bar0->tx_w_round_robin_0);
1509                 val64 = 0x0304000102030400ULL;
1510                 writeq(val64, &bar0->tx_w_round_robin_1);
1511                 val64 = 0x0102030400010203ULL;
1512                 writeq(val64, &bar0->tx_w_round_robin_2);
1513                 val64 = 0x0400010203040001ULL;
1514                 writeq(val64, &bar0->tx_w_round_robin_3);
1515                 val64 = 0x0203040000000000ULL;
1516                 writeq(val64, &bar0->tx_w_round_robin_4);
1517                 break;
1518         case 6:
1519                 val64 = 0x0001020304050001ULL;
1520                 writeq(val64, &bar0->tx_w_round_robin_0);
1521                 val64 = 0x0203040500010203ULL;
1522                 writeq(val64, &bar0->tx_w_round_robin_1);
1523                 val64 = 0x0405000102030405ULL;
1524                 writeq(val64, &bar0->tx_w_round_robin_2);
1525                 val64 = 0x0001020304050001ULL;
1526                 writeq(val64, &bar0->tx_w_round_robin_3);
1527                 val64 = 0x0203040500000000ULL;
1528                 writeq(val64, &bar0->tx_w_round_robin_4);
1529                 break;
1530         case 7:
1531                 val64 = 0x0001020304050600ULL;
1532                 writeq(val64, &bar0->tx_w_round_robin_0);
1533                 val64 = 0x0102030405060001ULL;
1534                 writeq(val64, &bar0->tx_w_round_robin_1);
1535                 val64 = 0x0203040506000102ULL;
1536                 writeq(val64, &bar0->tx_w_round_robin_2);
1537                 val64 = 0x0304050600010203ULL;
1538                 writeq(val64, &bar0->tx_w_round_robin_3);
1539                 val64 = 0x0405060000000000ULL;
1540                 writeq(val64, &bar0->tx_w_round_robin_4);
1541                 break;
1542         case 8:
1543                 val64 = 0x0001020304050607ULL;
1544                 writeq(val64, &bar0->tx_w_round_robin_0);
1545                 writeq(val64, &bar0->tx_w_round_robin_1);
1546                 writeq(val64, &bar0->tx_w_round_robin_2);
1547                 writeq(val64, &bar0->tx_w_round_robin_3);
1548                 val64 = 0x0001020300000000ULL;
1549                 writeq(val64, &bar0->tx_w_round_robin_4);
1550                 break;
1551         }
1552
1553         /* Enable all configured Tx FIFO partitions */
1554         val64 = readq(&bar0->tx_fifo_partition_0);
1555         val64 |= (TX_FIFO_PARTITION_EN);
1556         writeq(val64, &bar0->tx_fifo_partition_0);
1557
1558         /* Filling the Rx round robin registers as per the
1559          * number of Rings and steering based on QoS with
1560          * equal priority.
1561          */
1562         switch (config->rx_ring_num) {
1563         case 1:
1564                 val64 = 0x0;
1565                 writeq(val64, &bar0->rx_w_round_robin_0);
1566                 writeq(val64, &bar0->rx_w_round_robin_1);
1567                 writeq(val64, &bar0->rx_w_round_robin_2);
1568                 writeq(val64, &bar0->rx_w_round_robin_3);
1569                 writeq(val64, &bar0->rx_w_round_robin_4);
1570
1571                 val64 = 0x8080808080808080ULL;
1572                 writeq(val64, &bar0->rts_qos_steering);
1573                 break;
1574         case 2:
1575                 val64 = 0x0001000100010001ULL;
1576                 writeq(val64, &bar0->rx_w_round_robin_0);
1577                 writeq(val64, &bar0->rx_w_round_robin_1);
1578                 writeq(val64, &bar0->rx_w_round_robin_2);
1579                 writeq(val64, &bar0->rx_w_round_robin_3);
1580                 val64 = 0x0001000100000000ULL;
1581                 writeq(val64, &bar0->rx_w_round_robin_4);
1582
1583                 val64 = 0x8080808040404040ULL;
1584                 writeq(val64, &bar0->rts_qos_steering);
1585                 break;
1586         case 3:
1587                 val64 = 0x0001020001020001ULL;
1588                 writeq(val64, &bar0->rx_w_round_robin_0);
1589                 val64 = 0x0200010200010200ULL;
1590                 writeq(val64, &bar0->rx_w_round_robin_1);
1591                 val64 = 0x0102000102000102ULL;
1592                 writeq(val64, &bar0->rx_w_round_robin_2);
1593                 val64 = 0x0001020001020001ULL;
1594                 writeq(val64, &bar0->rx_w_round_robin_3);
1595                 val64 = 0x0200010200000000ULL;
1596                 writeq(val64, &bar0->rx_w_round_robin_4);
1597
1598                 val64 = 0x8080804040402020ULL;
1599                 writeq(val64, &bar0->rts_qos_steering);
1600                 break;
1601         case 4:
1602                 val64 = 0x0001020300010203ULL;
1603                 writeq(val64, &bar0->rx_w_round_robin_0);
1604                 writeq(val64, &bar0->rx_w_round_robin_1);
1605                 writeq(val64, &bar0->rx_w_round_robin_2);
1606                 writeq(val64, &bar0->rx_w_round_robin_3);
1607                 val64 = 0x0001020300000000ULL;
1608                 writeq(val64, &bar0->rx_w_round_robin_4);
1609
1610                 val64 = 0x8080404020201010ULL;
1611                 writeq(val64, &bar0->rts_qos_steering);
1612                 break;
1613         case 5:
1614                 val64 = 0x0001020304000102ULL;
1615                 writeq(val64, &bar0->rx_w_round_robin_0);
1616                 val64 = 0x0304000102030400ULL;
1617                 writeq(val64, &bar0->rx_w_round_robin_1);
1618                 val64 = 0x0102030400010203ULL;
1619                 writeq(val64, &bar0->rx_w_round_robin_2);
1620                 val64 = 0x0400010203040001ULL;
1621                 writeq(val64, &bar0->rx_w_round_robin_3);
1622                 val64 = 0x0203040000000000ULL;
1623                 writeq(val64, &bar0->rx_w_round_robin_4);
1624
1625                 val64 = 0x8080404020201008ULL;
1626                 writeq(val64, &bar0->rts_qos_steering);
1627                 break;
1628         case 6:
1629                 val64 = 0x0001020304050001ULL;
1630                 writeq(val64, &bar0->rx_w_round_robin_0);
1631                 val64 = 0x0203040500010203ULL;
1632                 writeq(val64, &bar0->rx_w_round_robin_1);
1633                 val64 = 0x0405000102030405ULL;
1634                 writeq(val64, &bar0->rx_w_round_robin_2);
1635                 val64 = 0x0001020304050001ULL;
1636                 writeq(val64, &bar0->rx_w_round_robin_3);
1637                 val64 = 0x0203040500000000ULL;
1638                 writeq(val64, &bar0->rx_w_round_robin_4);
1639
1640                 val64 = 0x8080404020100804ULL;
1641                 writeq(val64, &bar0->rts_qos_steering);
1642                 break;
1643         case 7:
1644                 val64 = 0x0001020304050600ULL;
1645                 writeq(val64, &bar0->rx_w_round_robin_0);
1646                 val64 = 0x0102030405060001ULL;
1647                 writeq(val64, &bar0->rx_w_round_robin_1);
1648                 val64 = 0x0203040506000102ULL;
1649                 writeq(val64, &bar0->rx_w_round_robin_2);
1650                 val64 = 0x0304050600010203ULL;
1651                 writeq(val64, &bar0->rx_w_round_robin_3);
1652                 val64 = 0x0405060000000000ULL;
1653                 writeq(val64, &bar0->rx_w_round_robin_4);
1654
1655                 val64 = 0x8080402010080402ULL;
1656                 writeq(val64, &bar0->rts_qos_steering);
1657                 break;
1658         case 8:
1659                 val64 = 0x0001020304050607ULL;
1660                 writeq(val64, &bar0->rx_w_round_robin_0);
1661                 writeq(val64, &bar0->rx_w_round_robin_1);
1662                 writeq(val64, &bar0->rx_w_round_robin_2);
1663                 writeq(val64, &bar0->rx_w_round_robin_3);
1664                 val64 = 0x0001020300000000ULL;
1665                 writeq(val64, &bar0->rx_w_round_robin_4);
1666
1667                 val64 = 0x8040201008040201ULL;
1668                 writeq(val64, &bar0->rts_qos_steering);
1669                 break;
1670         }
1671
1672         /* UDP Fix */
1673         val64 = 0;
1674         for (i = 0; i < 8; i++)
1675                 writeq(val64, &bar0->rts_frm_len_n[i]);
1676
1677         /* Set the default rts frame length for the rings configured */
1678         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1679         for (i = 0 ; i < config->rx_ring_num ; i++)
1680                 writeq(val64, &bar0->rts_frm_len_n[i]);
1681
1682         /* Set the frame length for the configured rings
1683          * desired by the user
1684          */
1685         for (i = 0; i < config->rx_ring_num; i++) {
1686                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1687                  * specified frame length steering.
1688                  * If the user provides the frame length then program
1689                  * the rts_frm_len register for those values or else
1690                  * leave it as it is.
1691                  */
1692                 if (rts_frm_len[i] != 0) {
1693                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1694                                &bar0->rts_frm_len_n[i]);
1695                 }
1696         }
1697
1698         /* Disable differentiated services steering logic */
1699         for (i = 0; i < 64; i++) {
1700                 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1701                         DBG_PRINT(ERR_DBG,
1702                                   "%s: rts_ds_steer failed on codepoint %d\n",
1703                                   dev->name, i);
1704                         return -ENODEV;
1705                 }
1706         }
1707
1708         /* Program statistics memory */
1709         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1710
1711         if (nic->device_type == XFRAME_II_DEVICE) {
1712                 val64 = STAT_BC(0x320);
1713                 writeq(val64, &bar0->stat_byte_cnt);
1714         }
1715
1716         /*
1717          * Initializing the sampling rate for the device to calculate the
1718          * bandwidth utilization.
1719          */
1720         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1721                 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1722         writeq(val64, &bar0->mac_link_util);
1723
1724         /*
1725          * Initializing the Transmit and Receive Traffic Interrupt
1726          * Scheme.
1727          */
1728
1729         /* Initialize TTI */
1730         if (SUCCESS != init_tti(nic, nic->last_link_state))
1731                 return -ENODEV;
1732
1733         /* RTI Initialization */
1734         if (nic->device_type == XFRAME_II_DEVICE) {
1735                 /*
1736                  * Programmed to generate Apprx 500 Intrs per
1737                  * second
1738                  */
1739                 int count = (nic->config.bus_speed * 125)/4;
1740                 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1741         } else
1742                 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1743         val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1744                 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1745                 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1746                 RTI_DATA1_MEM_RX_TIMER_AC_EN;
1747
1748         writeq(val64, &bar0->rti_data1_mem);
1749
1750         val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1751                 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1752         if (nic->config.intr_type == MSI_X)
1753                 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1754                           RTI_DATA2_MEM_RX_UFC_D(0x40));
1755         else
1756                 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1757                           RTI_DATA2_MEM_RX_UFC_D(0x80));
1758         writeq(val64, &bar0->rti_data2_mem);
1759
1760         for (i = 0; i < config->rx_ring_num; i++) {
1761                 val64 = RTI_CMD_MEM_WE |
1762                         RTI_CMD_MEM_STROBE_NEW_CMD |
1763                         RTI_CMD_MEM_OFFSET(i);
1764                 writeq(val64, &bar0->rti_command_mem);
1765
1766                 /*
1767                  * Once the operation completes, the Strobe bit of the
1768                  * command register will be reset. We poll for this
1769                  * particular condition. We wait for a maximum of 500ms
1770                  * for the operation to complete, if it's not complete
1771                  * by then we return error.
1772                  */
1773                 time = 0;
1774                 while (true) {
1775                         val64 = readq(&bar0->rti_command_mem);
1776                         if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1777                                 break;
1778
1779                         if (time > 10) {
1780                                 DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
1781                                           dev->name);
1782                                 return -ENODEV;
1783                         }
1784                         time++;
1785                         msleep(50);
1786                 }
1787         }
1788
1789         /*
1790          * Initializing proper values as Pause threshold into all
1791          * the 8 Queues on Rx side.
1792          */
1793         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1794         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1795
1796         /* Disable RMAC PAD STRIPPING */
1797         add = &bar0->mac_cfg;
1798         val64 = readq(&bar0->mac_cfg);
1799         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1800         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1801         writel((u32) (val64), add);
1802         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1803         writel((u32) (val64 >> 32), (add + 4));
1804         val64 = readq(&bar0->mac_cfg);
1805
1806         /* Enable FCS stripping by adapter */
1807         add = &bar0->mac_cfg;
1808         val64 = readq(&bar0->mac_cfg);
1809         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1810         if (nic->device_type == XFRAME_II_DEVICE)
1811                 writeq(val64, &bar0->mac_cfg);
1812         else {
1813                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1814                 writel((u32) (val64), add);
1815                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1816                 writel((u32) (val64 >> 32), (add + 4));
1817         }
1818
1819         /*
1820          * Set the time value to be inserted in the pause frame
1821          * generated by xena.
1822          */
1823         val64 = readq(&bar0->rmac_pause_cfg);
1824         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1825         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1826         writeq(val64, &bar0->rmac_pause_cfg);
1827
1828         /*
1829          * Set the Threshold Limit for Generating the pause frame
1830          * If the amount of data in any Queue exceeds ratio of
1831          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1832          * pause frame is generated
1833          */
1834         val64 = 0;
1835         for (i = 0; i < 4; i++) {
1836                 val64 |= (((u64)0xFF00 |
1837                            nic->mac_control.mc_pause_threshold_q0q3)
1838                           << (i * 2 * 8));
1839         }
1840         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1841
1842         val64 = 0;
1843         for (i = 0; i < 4; i++) {
1844                 val64 |= (((u64)0xFF00 |
1845                            nic->mac_control.mc_pause_threshold_q4q7)
1846                           << (i * 2 * 8));
1847         }
1848         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1849
1850         /*
1851          * TxDMA will stop Read request if the number of read split has
1852          * exceeded the limit pointed by shared_splits
1853          */
1854         val64 = readq(&bar0->pic_control);
1855         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1856         writeq(val64, &bar0->pic_control);
1857
1858         if (nic->config.bus_speed == 266) {
1859                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1860                 writeq(0x0, &bar0->read_retry_delay);
1861                 writeq(0x0, &bar0->write_retry_delay);
1862         }
1863
1864         /*
1865          * Programming the Herc to split every write transaction
1866          * that does not start on an ADB to reduce disconnects.
1867          */
1868         if (nic->device_type == XFRAME_II_DEVICE) {
1869                 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1870                         MISC_LINK_STABILITY_PRD(3);
1871                 writeq(val64, &bar0->misc_control);
1872                 val64 = readq(&bar0->pic_control2);
1873                 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1874                 writeq(val64, &bar0->pic_control2);
1875         }
1876         if (strstr(nic->product_name, "CX4")) {
1877                 val64 = TMAC_AVG_IPG(0x17);
1878                 writeq(val64, &bar0->tmac_avg_ipg);
1879         }
1880
1881         return SUCCESS;
1882 }
1883 #define LINK_UP_DOWN_INTERRUPT          1
1884 #define MAC_RMAC_ERR_TIMER              2
1885
1886 static int s2io_link_fault_indication(struct s2io_nic *nic)
1887 {
1888         if (nic->device_type == XFRAME_II_DEVICE)
1889                 return LINK_UP_DOWN_INTERRUPT;
1890         else
1891                 return MAC_RMAC_ERR_TIMER;
1892 }
1893
1894 /**
1895  *  do_s2io_write_bits -  update alarm bits in alarm register
1896  *  @value: alarm bits
1897  *  @flag: interrupt status
1898  *  @addr: address value
1899  *  Description: update alarm bits in alarm register
1900  *  Return Value:
1901  *  NONE.
1902  */
1903 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1904 {
1905         u64 temp64;
1906
1907         temp64 = readq(addr);
1908
1909         if (flag == ENABLE_INTRS)
1910                 temp64 &= ~((u64)value);
1911         else
1912                 temp64 |= ((u64)value);
1913         writeq(temp64, addr);
1914 }
1915
1916 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1917 {
1918         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1919         register u64 gen_int_mask = 0;
1920         u64 interruptible;
1921
1922         writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1923         if (mask & TX_DMA_INTR) {
1924                 gen_int_mask |= TXDMA_INT_M;
1925
1926                 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1927                                    TXDMA_PCC_INT | TXDMA_TTI_INT |
1928                                    TXDMA_LSO_INT | TXDMA_TPA_INT |
1929                                    TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1930
1931                 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1932                                    PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1933                                    PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1934                                    &bar0->pfc_err_mask);
1935
1936                 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1937                                    TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1938                                    TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1939
1940                 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1941                                    PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1942                                    PCC_N_SERR | PCC_6_COF_OV_ERR |
1943                                    PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1944                                    PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1945                                    PCC_TXB_ECC_SG_ERR,
1946                                    flag, &bar0->pcc_err_mask);
1947
1948                 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1949                                    TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1950
1951                 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1952                                    LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1953                                    LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1954                                    flag, &bar0->lso_err_mask);
1955
1956                 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1957                                    flag, &bar0->tpa_err_mask);
1958
1959                 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1960         }
1961
1962         if (mask & TX_MAC_INTR) {
1963                 gen_int_mask |= TXMAC_INT_M;
1964                 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1965                                    &bar0->mac_int_mask);
1966                 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1967                                    TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1968                                    TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1969                                    flag, &bar0->mac_tmac_err_mask);
1970         }
1971
1972         if (mask & TX_XGXS_INTR) {
1973                 gen_int_mask |= TXXGXS_INT_M;
1974                 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1975                                    &bar0->xgxs_int_mask);
1976                 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1977                                    TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1978                                    flag, &bar0->xgxs_txgxs_err_mask);
1979         }
1980
1981         if (mask & RX_DMA_INTR) {
1982                 gen_int_mask |= RXDMA_INT_M;
1983                 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1984                                    RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1985                                    flag, &bar0->rxdma_int_mask);
1986                 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1987                                    RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1988                                    RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1989                                    RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1990                 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1991                                    PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1992                                    PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1993                                    &bar0->prc_pcix_err_mask);
1994                 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1995                                    RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1996                                    &bar0->rpa_err_mask);
1997                 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1998                                    RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1999                                    RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2000                                    RDA_FRM_ECC_SG_ERR |
2001                                    RDA_MISC_ERR|RDA_PCIX_ERR,
2002                                    flag, &bar0->rda_err_mask);
2003                 do_s2io_write_bits(RTI_SM_ERR_ALARM |
2004                                    RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2005                                    flag, &bar0->rti_err_mask);
2006         }
2007
2008         if (mask & RX_MAC_INTR) {
2009                 gen_int_mask |= RXMAC_INT_M;
2010                 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2011                                    &bar0->mac_int_mask);
2012                 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2013                                  RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2014                                  RMAC_DOUBLE_ECC_ERR);
2015                 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2016                         interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2017                 do_s2io_write_bits(interruptible,
2018                                    flag, &bar0->mac_rmac_err_mask);
2019         }
2020
2021         if (mask & RX_XGXS_INTR) {
2022                 gen_int_mask |= RXXGXS_INT_M;
2023                 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2024                                    &bar0->xgxs_int_mask);
2025                 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2026                                    &bar0->xgxs_rxgxs_err_mask);
2027         }
2028
2029         if (mask & MC_INTR) {
2030                 gen_int_mask |= MC_INT_M;
2031                 do_s2io_write_bits(MC_INT_MASK_MC_INT,
2032                                    flag, &bar0->mc_int_mask);
2033                 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2034                                    MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2035                                    &bar0->mc_err_mask);
2036         }
2037         nic->general_int_mask = gen_int_mask;
2038
2039         /* Remove this line when alarm interrupts are enabled */
2040         nic->general_int_mask = 0;
2041 }
2042
2043 /**
2044  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
2045  *  @nic: device private variable,
2046  *  @mask: A mask indicating which Intr block must be modified and,
2047  *  @flag: A flag indicating whether to enable or disable the Intrs.
2048  *  Description: This function will either disable or enable the interrupts
2049  *  depending on the flag argument. The mask argument can be used to
2050  *  enable/disable any Intr block.
2051  *  Return Value: NONE.
2052  */
2053
2054 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2055 {
2056         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2057         register u64 temp64 = 0, intr_mask = 0;
2058
2059         intr_mask = nic->general_int_mask;
2060
2061         /*  Top level interrupt classification */
2062         /*  PIC Interrupts */
2063         if (mask & TX_PIC_INTR) {
2064                 /*  Enable PIC Intrs in the general intr mask register */
2065                 intr_mask |= TXPIC_INT_M;
2066                 if (flag == ENABLE_INTRS) {
2067                         /*
2068                          * If Hercules adapter enable GPIO otherwise
2069                          * disable all PCIX, Flash, MDIO, IIC and GPIO
2070                          * interrupts for now.
2071                          * TODO
2072                          */
2073                         if (s2io_link_fault_indication(nic) ==
2074                             LINK_UP_DOWN_INTERRUPT) {
2075                                 do_s2io_write_bits(PIC_INT_GPIO, flag,
2076                                                    &bar0->pic_int_mask);
2077                                 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2078                                                    &bar0->gpio_int_mask);
2079                         } else
2080                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2081                 } else if (flag == DISABLE_INTRS) {
2082                         /*
2083                          * Disable PIC Intrs in the general
2084                          * intr mask register
2085                          */
2086                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2087                 }
2088         }
2089
2090         /*  Tx traffic interrupts */
2091         if (mask & TX_TRAFFIC_INTR) {
2092                 intr_mask |= TXTRAFFIC_INT_M;
2093                 if (flag == ENABLE_INTRS) {
2094                         /*
2095                          * Enable all the Tx side interrupts
2096                          * writing 0 Enables all 64 TX interrupt levels
2097                          */
2098                         writeq(0x0, &bar0->tx_traffic_mask);
2099                 } else if (flag == DISABLE_INTRS) {
2100                         /*
2101                          * Disable Tx Traffic Intrs in the general intr mask
2102                          * register.
2103                          */
2104                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2105                 }
2106         }
2107
2108         /*  Rx traffic interrupts */
2109         if (mask & RX_TRAFFIC_INTR) {
2110                 intr_mask |= RXTRAFFIC_INT_M;
2111                 if (flag == ENABLE_INTRS) {
2112                         /* writing 0 Enables all 8 RX interrupt levels */
2113                         writeq(0x0, &bar0->rx_traffic_mask);
2114                 } else if (flag == DISABLE_INTRS) {
2115                         /*
2116                          * Disable Rx Traffic Intrs in the general intr mask
2117                          * register.
2118                          */
2119                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2120                 }
2121         }
2122
2123         temp64 = readq(&bar0->general_int_mask);
2124         if (flag == ENABLE_INTRS)
2125                 temp64 &= ~((u64)intr_mask);
2126         else
2127                 temp64 = DISABLE_ALL_INTRS;
2128         writeq(temp64, &bar0->general_int_mask);
2129
2130         nic->general_int_mask = readq(&bar0->general_int_mask);
2131 }
2132
2133 /**
2134  *  verify_pcc_quiescent- Checks for PCC quiescent state
2135  *  Return: 1 If PCC is quiescence
2136  *          0 If PCC is not quiescence
2137  */
2138 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2139 {
2140         int ret = 0, herc;
2141         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2142         u64 val64 = readq(&bar0->adapter_status);
2143
2144         herc = (sp->device_type == XFRAME_II_DEVICE);
2145
2146         if (flag == false) {
2147                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2148                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2149                                 ret = 1;
2150                 } else {
2151                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2152                                 ret = 1;
2153                 }
2154         } else {
2155                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2156                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2157                              ADAPTER_STATUS_RMAC_PCC_IDLE))
2158                                 ret = 1;
2159                 } else {
2160                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2161                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2162                                 ret = 1;
2163                 }
2164         }
2165
2166         return ret;
2167 }
2168 /**
2169  *  verify_xena_quiescence - Checks whether the H/W is ready
2170  *  Description: Returns whether the H/W is ready to go or not. Depending
2171  *  on whether adapter enable bit was written or not the comparison
2172  *  differs and the calling function passes the input argument flag to
2173  *  indicate this.
2174  *  Return: 1 If xena is quiescence
2175  *          0 If Xena is not quiescence
2176  */
2177
2178 static int verify_xena_quiescence(struct s2io_nic *sp)
2179 {
2180         int  mode;
2181         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2182         u64 val64 = readq(&bar0->adapter_status);
2183         mode = s2io_verify_pci_mode(sp);
2184
2185         if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2186                 DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
2187                 return 0;
2188         }
2189         if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2190                 DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
2191                 return 0;
2192         }
2193         if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2194                 DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
2195                 return 0;
2196         }
2197         if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2198                 DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
2199                 return 0;
2200         }
2201         if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2202                 DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
2203                 return 0;
2204         }
2205         if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2206                 DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
2207                 return 0;
2208         }
2209         if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2210                 DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
2211                 return 0;
2212         }
2213         if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2214                 DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
2215                 return 0;
2216         }
2217
2218         /*
2219          * In PCI 33 mode, the P_PLL is not used, and therefore,
2220          * the the P_PLL_LOCK bit in the adapter_status register will
2221          * not be asserted.
2222          */
2223         if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2224             sp->device_type == XFRAME_II_DEVICE &&
2225             mode != PCI_MODE_PCI_33) {
2226                 DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
2227                 return 0;
2228         }
2229         if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2230               ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2231                 DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
2232                 return 0;
2233         }
2234         return 1;
2235 }
2236
2237 /**
2238  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
2239  * @sp: Pointer to device specifc structure
2240  * Description :
2241  * New procedure to clear mac address reading  problems on Alpha platforms
2242  *
2243  */
2244
2245 static void fix_mac_address(struct s2io_nic *sp)
2246 {
2247         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2248         int i = 0;
2249
2250         while (fix_mac[i] != END_SIGN) {
2251                 writeq(fix_mac[i++], &bar0->gpio_control);
2252                 udelay(10);
2253                 (void) readq(&bar0->gpio_control);
2254         }
2255 }
2256
2257 /**
2258  *  start_nic - Turns the device on
2259  *  @nic : device private variable.
2260  *  Description:
2261  *  This function actually turns the device on. Before this  function is
2262  *  called,all Registers are configured from their reset states
2263  *  and shared memory is allocated but the NIC is still quiescent. On
2264  *  calling this function, the device interrupts are cleared and the NIC is
2265  *  literally switched on by writing into the adapter control register.
2266  *  Return Value:
2267  *  SUCCESS on success and -1 on failure.
2268  */
2269
2270 static int start_nic(struct s2io_nic *nic)
2271 {
2272         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2273         struct net_device *dev = nic->dev;
2274         register u64 val64 = 0;
2275         u16 subid, i;
2276         struct config_param *config = &nic->config;
2277         struct mac_info *mac_control = &nic->mac_control;
2278
2279         /*  PRC Initialization and configuration */
2280         for (i = 0; i < config->rx_ring_num; i++) {
2281                 struct ring_info *ring = &mac_control->rings[i];
2282
2283                 writeq((u64)ring->rx_blocks[0].block_dma_addr,
2284                        &bar0->prc_rxd0_n[i]);
2285
2286                 val64 = readq(&bar0->prc_ctrl_n[i]);
2287                 if (nic->rxd_mode == RXD_MODE_1)
2288                         val64 |= PRC_CTRL_RC_ENABLED;
2289                 else
2290                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2291                 if (nic->device_type == XFRAME_II_DEVICE)
2292                         val64 |= PRC_CTRL_GROUP_READS;
2293                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2294                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2295                 writeq(val64, &bar0->prc_ctrl_n[i]);
2296         }
2297
2298         if (nic->rxd_mode == RXD_MODE_3B) {
2299                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2300                 val64 = readq(&bar0->rx_pa_cfg);
2301                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2302                 writeq(val64, &bar0->rx_pa_cfg);
2303         }
2304
2305         if (vlan_tag_strip == 0) {
2306                 val64 = readq(&bar0->rx_pa_cfg);
2307                 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2308                 writeq(val64, &bar0->rx_pa_cfg);
2309                 nic->vlan_strip_flag = 0;
2310         }
2311
2312         /*
2313          * Enabling MC-RLDRAM. After enabling the device, we timeout
2314          * for around 100ms, which is approximately the time required
2315          * for the device to be ready for operation.
2316          */
2317         val64 = readq(&bar0->mc_rldram_mrs);
2318         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2319         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2320         val64 = readq(&bar0->mc_rldram_mrs);
2321
2322         msleep(100);    /* Delay by around 100 ms. */
2323
2324         /* Enabling ECC Protection. */
2325         val64 = readq(&bar0->adapter_control);
2326         val64 &= ~ADAPTER_ECC_EN;
2327         writeq(val64, &bar0->adapter_control);
2328
2329         /*
2330          * Verify if the device is ready to be enabled, if so enable
2331          * it.
2332          */
2333         val64 = readq(&bar0->adapter_status);
2334         if (!verify_xena_quiescence(nic)) {
2335                 DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2336                           "Adapter status reads: 0x%llx\n",
2337                           dev->name, (unsigned long long)val64);
2338                 return FAILURE;
2339         }
2340
2341         /*
2342          * With some switches, link might be already up at this point.
2343          * Because of this weird behavior, when we enable laser,
2344          * we may not get link. We need to handle this. We cannot
2345          * figure out which switch is misbehaving. So we are forced to
2346          * make a global change.
2347          */
2348
2349         /* Enabling Laser. */
2350         val64 = readq(&bar0->adapter_control);
2351         val64 |= ADAPTER_EOI_TX_ON;
2352         writeq(val64, &bar0->adapter_control);
2353
2354         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2355                 /*
2356                  * Dont see link state interrupts initially on some switches,
2357                  * so directly scheduling the link state task here.
2358                  */
2359                 schedule_work(&nic->set_link_task);
2360         }
2361         /* SXE-002: Initialize link and activity LED */
2362         subid = nic->pdev->subsystem_device;
2363         if (((subid & 0xFF) >= 0x07) &&
2364             (nic->device_type == XFRAME_I_DEVICE)) {
2365                 val64 = readq(&bar0->gpio_control);
2366                 val64 |= 0x0000800000000000ULL;
2367                 writeq(val64, &bar0->gpio_control);
2368                 val64 = 0x0411040400000000ULL;
2369                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2370         }
2371
2372         return SUCCESS;
2373 }
2374 /**
2375  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2376  */
2377 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2378                                         struct TxD *txdlp, int get_off)
2379 {
2380         struct s2io_nic *nic = fifo_data->nic;
2381         struct sk_buff *skb;
2382         struct TxD *txds;
2383         u16 j, frg_cnt;
2384
2385         txds = txdlp;
2386         if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2387                 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2388                                  sizeof(u64), PCI_DMA_TODEVICE);
2389                 txds++;
2390         }
2391
2392         skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
2393         if (!skb) {
2394                 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2395                 return NULL;
2396         }
2397         pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2398                          skb_headlen(skb), PCI_DMA_TODEVICE);
2399         frg_cnt = skb_shinfo(skb)->nr_frags;
2400         if (frg_cnt) {
2401                 txds++;
2402                 for (j = 0; j < frg_cnt; j++, txds++) {
2403                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2404                         if (!txds->Buffer_Pointer)
2405                                 break;
2406                         pci_unmap_page(nic->pdev,
2407                                        (dma_addr_t)txds->Buffer_Pointer,
2408                                        frag->size, PCI_DMA_TODEVICE);
2409                 }
2410         }
2411         memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2412         return skb;
2413 }
2414
2415 /**
2416  *  free_tx_buffers - Free all queued Tx buffers
2417  *  @nic : device private variable.
2418  *  Description:
2419  *  Free all queued Tx buffers.
2420  *  Return Value: void
2421  */
2422
2423 static void free_tx_buffers(struct s2io_nic *nic)
2424 {
2425         struct net_device *dev = nic->dev;
2426         struct sk_buff *skb;
2427         struct TxD *txdp;
2428         int i, j;
2429         int cnt = 0;
2430         struct config_param *config = &nic->config;
2431         struct mac_info *mac_control = &nic->mac_control;
2432         struct stat_block *stats = mac_control->stats_info;
2433         struct swStat *swstats = &stats->sw_stat;
2434
2435         for (i = 0; i < config->tx_fifo_num; i++) {
2436                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2437                 struct fifo_info *fifo = &mac_control->fifos[i];
2438                 unsigned long flags;
2439
2440                 spin_lock_irqsave(&fifo->tx_lock, flags);
2441                 for (j = 0; j < tx_cfg->fifo_len; j++) {
2442                         txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
2443                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2444                         if (skb) {
2445                                 swstats->mem_freed += skb->truesize;
2446                                 dev_kfree_skb(skb);
2447                                 cnt++;
2448                         }
2449                 }
2450                 DBG_PRINT(INTR_DBG,
2451                           "%s: forcibly freeing %d skbs on FIFO%d\n",
2452                           dev->name, cnt, i);
2453                 fifo->tx_curr_get_info.offset = 0;
2454                 fifo->tx_curr_put_info.offset = 0;
2455                 spin_unlock_irqrestore(&fifo->tx_lock, flags);
2456         }
2457 }
2458
2459 /**
2460  *   stop_nic -  To stop the nic
2461  *   @nic ; device private variable.
2462  *   Description:
2463  *   This function does exactly the opposite of what the start_nic()
2464  *   function does. This function is called to stop the device.
2465  *   Return Value:
2466  *   void.
2467  */
2468
2469 static void stop_nic(struct s2io_nic *nic)
2470 {
2471         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2472         register u64 val64 = 0;
2473         u16 interruptible;
2474
2475         /*  Disable all interrupts */
2476         en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2477         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2478         interruptible |= TX_PIC_INTR;
2479         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2480
2481         /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2482         val64 = readq(&bar0->adapter_control);
2483         val64 &= ~(ADAPTER_CNTL_EN);
2484         writeq(val64, &bar0->adapter_control);
2485 }
2486
2487 /**
2488  *  fill_rx_buffers - Allocates the Rx side skbs
2489  *  @ring_info: per ring structure
2490  *  @from_card_up: If this is true, we will map the buffer to get
2491  *     the dma address for buf0 and buf1 to give it to the card.
2492  *     Else we will sync the already mapped buffer to give it to the card.
2493  *  Description:
2494  *  The function allocates Rx side skbs and puts the physical
2495  *  address of these buffers into the RxD buffer pointers, so that the NIC
2496  *  can DMA the received frame into these locations.
2497  *  The NIC supports 3 receive modes, viz
2498  *  1. single buffer,
2499  *  2. three buffer and
2500  *  3. Five buffer modes.
2501  *  Each mode defines how many fragments the received frame will be split
2502  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2503  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2504  *  is split into 3 fragments. As of now only single buffer mode is
2505  *  supported.
2506  *   Return Value:
2507  *  SUCCESS on success or an appropriate -ve value on failure.
2508  */
2509 static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2510                            int from_card_up)
2511 {
2512         struct sk_buff *skb;
2513         struct RxD_t *rxdp;
2514         int off, size, block_no, block_no1;
2515         u32 alloc_tab = 0;
2516         u32 alloc_cnt;
2517         u64 tmp;
2518         struct buffAdd *ba;
2519         struct RxD_t *first_rxdp = NULL;
2520         u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2521         int rxd_index = 0;
2522         struct RxD1 *rxdp1;
2523         struct RxD3 *rxdp3;
2524         struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
2525
2526         alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2527
2528         block_no1 = ring->rx_curr_get_info.block_index;
2529         while (alloc_tab < alloc_cnt) {
2530                 block_no = ring->rx_curr_put_info.block_index;
2531
2532                 off = ring->rx_curr_put_info.offset;
2533
2534                 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2535
2536                 rxd_index = off + 1;
2537                 if (block_no)
2538                         rxd_index += (block_no * ring->rxd_count);
2539
2540                 if ((block_no == block_no1) &&
2541                     (off == ring->rx_curr_get_info.offset) &&
2542                     (rxdp->Host_Control)) {
2543                         DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2544                                   ring->dev->name);
2545                         goto end;
2546                 }
2547                 if (off && (off == ring->rxd_count)) {
2548                         ring->rx_curr_put_info.block_index++;
2549                         if (ring->rx_curr_put_info.block_index ==
2550                             ring->block_count)
2551                                 ring->rx_curr_put_info.block_index = 0;
2552                         block_no = ring->rx_curr_put_info.block_index;
2553                         off = 0;
2554                         ring->rx_curr_put_info.offset = off;
2555                         rxdp = ring->rx_blocks[block_no].block_virt_addr;
2556                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2557                                   ring->dev->name, rxdp);
2558
2559                 }
2560
2561                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2562                     ((ring->rxd_mode == RXD_MODE_3B) &&
2563                      (rxdp->Control_2 & s2BIT(0)))) {
2564                         ring->rx_curr_put_info.offset = off;
2565                         goto end;
2566                 }
2567                 /* calculate size of skb based on ring mode */
2568                 size = ring->mtu +
2569                         HEADER_ETHERNET_II_802_3_SIZE +
2570                         HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2571                 if (ring->rxd_mode == RXD_MODE_1)
2572                         size += NET_IP_ALIGN;
2573                 else
2574                         size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2575
2576                 /* allocate skb */
2577                 skb = dev_alloc_skb(size);
2578                 if (!skb) {
2579                         DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2580                                   ring->dev->name);
2581                         if (first_rxdp) {
2582                                 wmb();
2583                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2584                         }
2585                         swstats->mem_alloc_fail_cnt++;
2586
2587                         return -ENOMEM ;
2588                 }
2589                 swstats->mem_allocated += skb->truesize;
2590
2591                 if (ring->rxd_mode == RXD_MODE_1) {
2592                         /* 1 buffer mode - normal operation mode */
2593                         rxdp1 = (struct RxD1 *)rxdp;
2594                         memset(rxdp, 0, sizeof(struct RxD1));
2595                         skb_reserve(skb, NET_IP_ALIGN);
2596                         rxdp1->Buffer0_ptr =
2597                                 pci_map_single(ring->pdev, skb->data,
2598                                                size - NET_IP_ALIGN,
2599                                                PCI_DMA_FROMDEVICE);
2600                         if (pci_dma_mapping_error(nic->pdev,
2601                                                   rxdp1->Buffer0_ptr))
2602                                 goto pci_map_failed;
2603
2604                         rxdp->Control_2 =
2605                                 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2606                         rxdp->Host_Control = (unsigned long)skb;
2607                 } else if (ring->rxd_mode == RXD_MODE_3B) {
2608                         /*
2609                          * 2 buffer mode -
2610                          * 2 buffer mode provides 128
2611                          * byte aligned receive buffers.
2612                          */
2613
2614                         rxdp3 = (struct RxD3 *)rxdp;
2615                         /* save buffer pointers to avoid frequent dma mapping */
2616                         Buffer0_ptr = rxdp3->Buffer0_ptr;
2617                         Buffer1_ptr = rxdp3->Buffer1_ptr;
2618                         memset(rxdp, 0, sizeof(struct RxD3));
2619                         /* restore the buffer pointers for dma sync*/
2620                         rxdp3->Buffer0_ptr = Buffer0_ptr;
2621                         rxdp3->Buffer1_ptr = Buffer1_ptr;
2622
2623                         ba = &ring->ba[block_no][off];
2624                         skb_reserve(skb, BUF0_LEN);
2625                         tmp = (u64)(unsigned long)skb->data;
2626                         tmp += ALIGN_SIZE;
2627                         tmp &= ~ALIGN_SIZE;
2628                         skb->data = (void *) (unsigned long)tmp;
2629                         skb_reset_tail_pointer(skb);
2630
2631                         if (from_card_up) {
2632                                 rxdp3->Buffer0_ptr =
2633                                         pci_map_single(ring->pdev, ba->ba_0,
2634                                                        BUF0_LEN,
2635                                                        PCI_DMA_FROMDEVICE);
2636                                 if (pci_dma_mapping_error(nic->pdev,
2637                                                           rxdp3->Buffer0_ptr))
2638                                         goto pci_map_failed;
2639                         } else
2640                                 pci_dma_sync_single_for_device(ring->pdev,
2641                                                                (dma_addr_t)rxdp3->Buffer0_ptr,
2642                                                                BUF0_LEN,
2643                                                                PCI_DMA_FROMDEVICE);
2644
2645                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2646                         if (ring->rxd_mode == RXD_MODE_3B) {
2647                                 /* Two buffer mode */
2648
2649                                 /*
2650                                  * Buffer2 will have L3/L4 header plus
2651                                  * L4 payload
2652                                  */
2653                                 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2654                                                                     skb->data,
2655                                                                     ring->mtu + 4,
2656                                                                     PCI_DMA_FROMDEVICE);
2657
2658                                 if (pci_dma_mapping_error(nic->pdev,
2659                                                           rxdp3->Buffer2_ptr))
2660                                         goto pci_map_failed;
2661
2662                                 if (from_card_up) {
2663                                         rxdp3->Buffer1_ptr =
2664                                                 pci_map_single(ring->pdev,
2665                                                                ba->ba_1,
2666                                                                BUF1_LEN,
2667                                                                PCI_DMA_FROMDEVICE);
2668
2669                                         if (pci_dma_mapping_error(nic->pdev,
2670                                                                   rxdp3->Buffer1_ptr)) {
2671                                                 pci_unmap_single(ring->pdev,
2672                                                                  (dma_addr_t)(unsigned long)
2673                                                                  skb->data,
2674                                                                  ring->mtu + 4,
2675                                                                  PCI_DMA_FROMDEVICE);
2676                                                 goto pci_map_failed;
2677                                         }
2678                                 }
2679                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2680                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2681                                         (ring->mtu + 4);
2682                         }
2683                         rxdp->Control_2 |= s2BIT(0);
2684                         rxdp->Host_Control = (unsigned long) (skb);
2685                 }
2686                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2687                         rxdp->Control_1 |= RXD_OWN_XENA;
2688                 off++;
2689                 if (off == (ring->rxd_count + 1))
2690                         off = 0;
2691                 ring->rx_curr_put_info.offset = off;
2692
2693                 rxdp->Control_2 |= SET_RXD_MARKER;
2694                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2695                         if (first_rxdp) {
2696                                 wmb();
2697                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2698                         }
2699                         first_rxdp = rxdp;
2700                 }
2701                 ring->rx_bufs_left += 1;
2702                 alloc_tab++;
2703         }
2704
2705 end:
2706         /* Transfer ownership of first descriptor to adapter just before
2707          * exiting. Before that, use memory barrier so that ownership
2708          * and other fields are seen by adapter correctly.
2709          */
2710         if (first_rxdp) {
2711                 wmb();
2712                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2713         }
2714
2715         return SUCCESS;
2716
2717 pci_map_failed:
2718         swstats->pci_map_fail_cnt++;
2719         swstats->mem_freed += skb->truesize;
2720         dev_kfree_skb_irq(skb);
2721         return -ENOMEM;
2722 }
2723
2724 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2725 {
2726         struct net_device *dev = sp->dev;
2727         int j;
2728         struct sk_buff *skb;
2729         struct RxD_t *rxdp;
2730         struct RxD1 *rxdp1;
2731         struct RxD3 *rxdp3;
2732         struct mac_info *mac_control = &sp->mac_control;
2733         struct stat_block *stats = mac_control->stats_info;
2734         struct swStat *swstats = &stats->sw_stat;
2735
2736         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2737                 rxdp = mac_control->rings[ring_no].
2738                         rx_blocks[blk].rxds[j].virt_addr;
2739                 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2740                 if (!skb)
2741                         continue;
2742                 if (sp->rxd_mode == RXD_MODE_1) {
2743                         rxdp1 = (struct RxD1 *)rxdp;
2744                         pci_unmap_single(sp->pdev,
2745                                          (dma_addr_t)rxdp1->Buffer0_ptr,
2746                                          dev->mtu +
2747                                          HEADER_ETHERNET_II_802_3_SIZE +
2748                                          HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2749                                          PCI_DMA_FROMDEVICE);
2750                         memset(rxdp, 0, sizeof(struct RxD1));
2751                 } else if (sp->rxd_mode == RXD_MODE_3B) {
2752                         rxdp3 = (struct RxD3 *)rxdp;
2753                         pci_unmap_single(sp->pdev,
2754                                          (dma_addr_t)rxdp3->Buffer0_ptr,
2755                                          BUF0_LEN,
2756                                          PCI_DMA_FROMDEVICE);
2757                         pci_unmap_single(sp->pdev,
2758                                          (dma_addr_t)rxdp3->Buffer1_ptr,
2759                                          BUF1_LEN,
2760                                          PCI_DMA_FROMDEVICE);
2761                         pci_unmap_single(sp->pdev,
2762                                          (dma_addr_t)rxdp3->Buffer2_ptr,
2763                                          dev->mtu + 4,
2764                                          PCI_DMA_FROMDEVICE);
2765                         memset(rxdp, 0, sizeof(struct RxD3));
2766                 }
2767                 swstats->mem_freed += skb->truesize;
2768                 dev_kfree_skb(skb);
2769                 mac_control->rings[ring_no].rx_bufs_left -= 1;
2770         }
2771 }
2772
2773 /**
2774  *  free_rx_buffers - Frees all Rx buffers
2775  *  @sp: device private variable.
2776  *  Description:
2777  *  This function will free all Rx buffers allocated by host.
2778  *  Return Value:
2779  *  NONE.
2780  */
2781
2782 static void free_rx_buffers(struct s2io_nic *sp)
2783 {
2784         struct net_device *dev = sp->dev;
2785         int i, blk = 0, buf_cnt = 0;
2786         struct config_param *config = &sp->config;
2787         struct mac_info *mac_control = &sp->mac_control;
2788
2789         for (i = 0; i < config->rx_ring_num; i++) {
2790                 struct ring_info *ring = &mac_control->rings[i];
2791
2792                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2793                         free_rxd_blk(sp, i, blk);
2794
2795                 ring->rx_curr_put_info.block_index = 0;
2796                 ring->rx_curr_get_info.block_index = 0;
2797                 ring->rx_curr_put_info.offset = 0;
2798                 ring->rx_curr_get_info.offset = 0;
2799                 ring->rx_bufs_left = 0;
2800                 DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
2801                           dev->name, buf_cnt, i);
2802         }
2803 }
2804
2805 static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2806 {
2807         if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2808                 DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2809                           ring->dev->name);
2810         }
2811         return 0;
2812 }
2813
2814 /**
2815  * s2io_poll - Rx interrupt handler for NAPI support
2816  * @napi : pointer to the napi structure.
2817  * @budget : The number of packets that were budgeted to be processed
2818  * during  one pass through the 'Poll" function.
2819  * Description:
2820  * Comes into picture only if NAPI support has been incorporated. It does
2821  * the same thing that rx_intr_handler does, but not in a interrupt context
2822  * also It will process only a given number of packets.
2823  * Return value:
2824  * 0 on success and 1 if there are No Rx packets to be processed.
2825  */
2826
2827 static int s2io_poll_msix(struct napi_struct *napi, int budget)
2828 {
2829         struct ring_info *ring = container_of(napi, struct ring_info, napi);
2830         struct net_device *dev = ring->dev;
2831         int pkts_processed = 0;
2832         u8 __iomem *addr = NULL;
2833         u8 val8 = 0;
2834         struct s2io_nic *nic = netdev_priv(dev);
2835         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2836         int budget_org = budget;
2837
2838         if (unlikely(!is_s2io_card_up(nic)))
2839                 return 0;
2840
2841         pkts_processed = rx_intr_handler(ring, budget);
2842         s2io_chk_rx_buffers(nic, ring);
2843
2844         if (pkts_processed < budget_org) {
2845                 napi_complete(napi);
2846                 /*Re Enable MSI-Rx Vector*/
2847                 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2848                 addr += 7 - ring->ring_no;
2849                 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2850                 writeb(val8, addr);
2851                 val8 = readb(addr);
2852         }
2853         return pkts_processed;
2854 }
2855
2856 static int s2io_poll_inta(struct napi_struct *napi, int budget)
2857 {
2858         struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2859         int pkts_processed = 0;
2860         int ring_pkts_processed, i;
2861         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2862         int budget_org = budget;
2863         struct config_param *config = &nic->config;
2864         struct mac_info *mac_control = &nic->mac_control;
2865
2866         if (unlikely(!is_s2io_card_up(nic)))
2867                 return 0;
2868
2869         for (i = 0; i < config->rx_ring_num; i++) {
2870                 struct ring_info *ring = &mac_control->rings[i];
2871                 ring_pkts_processed = rx_intr_handler(ring, budget);
2872                 s2io_chk_rx_buffers(nic, ring);
2873                 pkts_processed += ring_pkts_processed;
2874                 budget -= ring_pkts_processed;
2875                 if (budget <= 0)
2876                         break;
2877         }
2878         if (pkts_processed < budget_org) {
2879                 napi_complete(napi);
2880                 /* Re enable the Rx interrupts for the ring */
2881                 writeq(0, &bar0->rx_traffic_mask);
2882                 readl(&bar0->rx_traffic_mask);
2883         }
2884         return pkts_processed;
2885 }
2886
2887 #ifdef CONFIG_NET_POLL_CONTROLLER
2888 /**
2889  * s2io_netpoll - netpoll event handler entry point
2890  * @dev : pointer to the device structure.
2891  * Description:
2892  *      This function will be called by upper layer to check for events on the
2893  * interface in situations where interrupts are disabled. It is used for
2894  * specific in-kernel networking tasks, such as remote consoles and kernel
2895  * debugging over the network (example netdump in RedHat).
2896  */
2897 static void s2io_netpoll(struct net_device *dev)
2898 {
2899         struct s2io_nic *nic = netdev_priv(dev);
2900         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2901         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2902         int i;
2903         struct config_param *config = &nic->config;
2904         struct mac_info *mac_control = &nic->mac_control;
2905
2906         if (pci_channel_offline(nic->pdev))
2907                 return;
2908
2909         disable_irq(dev->irq);
2910
2911         writeq(val64, &bar0->rx_traffic_int);
2912         writeq(val64, &bar0->tx_traffic_int);
2913
2914         /* we need to free up the transmitted skbufs or else netpoll will
2915          * run out of skbs and will fail and eventually netpoll application such
2916          * as netdump will fail.
2917          */
2918         for (i = 0; i < config->tx_fifo_num; i++)
2919                 tx_intr_handler(&mac_control->fifos[i]);
2920
2921         /* check for received packet and indicate up to network */
2922         for (i = 0; i < config->rx_ring_num; i++) {
2923                 struct ring_info *ring = &mac_control->rings[i];
2924
2925                 rx_intr_handler(ring, 0);
2926         }
2927
2928         for (i = 0; i < config->rx_ring_num; i++) {
2929                 struct ring_info *ring = &mac_control->rings[i];
2930
2931                 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2932                         DBG_PRINT(INFO_DBG,
2933                                   "%s: Out of memory in Rx Netpoll!!\n",
2934                                   dev->name);
2935                         break;
2936                 }
2937         }
2938         enable_irq(dev->irq);
2939 }
2940 #endif
2941
2942 /**
2943  *  rx_intr_handler - Rx interrupt handler
2944  *  @ring_info: per ring structure.
2945  *  @budget: budget for napi processing.
2946  *  Description:
2947  *  If the interrupt is because of a received frame or if the
2948  *  receive ring contains fresh as yet un-processed frames,this function is
2949  *  called. It picks out the RxD at which place the last Rx processing had
2950  *  stopped and sends the skb to the OSM's Rx handler and then increments
2951  *  the offset.
2952  *  Return Value:
2953  *  No. of napi packets processed.
2954  */
2955 static int rx_intr_handler(struct ring_info *ring_data, int budget)
2956 {
2957         int get_block, put_block;
2958         struct rx_curr_get_info get_info, put_info;
2959         struct RxD_t *rxdp;
2960         struct sk_buff *skb;
2961         int pkt_cnt = 0, napi_pkts = 0;
2962         int i;
2963         struct RxD1 *rxdp1;
2964         struct RxD3 *rxdp3;
2965
2966         get_info = ring_data->rx_curr_get_info;
2967         get_block = get_info.block_index;
2968         memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2969         put_block = put_info.block_index;
2970         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2971
2972         while (RXD_IS_UP2DT(rxdp)) {
2973                 /*
2974                  * If your are next to put index then it's
2975                  * FIFO full condition
2976                  */
2977                 if ((get_block == put_block) &&
2978                     (get_info.offset + 1) == put_info.offset) {
2979                         DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2980                                   ring_data->dev->name);
2981                         break;
2982                 }
2983                 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2984                 if (skb == NULL) {
2985                         DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
2986                                   ring_data->dev->name);
2987                         return 0;
2988                 }
2989                 if (ring_data->rxd_mode == RXD_MODE_1) {
2990                         rxdp1 = (struct RxD1 *)rxdp;
2991                         pci_unmap_single(ring_data->pdev, (dma_addr_t)
2992                                          rxdp1->Buffer0_ptr,
2993                                          ring_data->mtu +
2994                                          HEADER_ETHERNET_II_802_3_SIZE +
2995                                          HEADER_802_2_SIZE +
2996                                          HEADER_SNAP_SIZE,
2997                                          PCI_DMA_FROMDEVICE);
2998                 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
2999                         rxdp3 = (struct RxD3 *)rxdp;
3000                         pci_dma_sync_single_for_cpu(ring_data->pdev,
3001                                                     (dma_addr_t)rxdp3->Buffer0_ptr,
3002                                                     BUF0_LEN,
3003                                                     PCI_DMA_FROMDEVICE);
3004                         pci_unmap_single(ring_data->pdev,
3005                                          (dma_addr_t)rxdp3->Buffer2_ptr,
3006                                          ring_data->mtu + 4,
3007                                          PCI_DMA_FROMDEVICE);
3008                 }
3009                 prefetch(skb->data);
3010                 rx_osm_handler(ring_data, rxdp);
3011                 get_info.offset++;
3012                 ring_data->rx_curr_get_info.offset = get_info.offset;
3013                 rxdp = ring_data->rx_blocks[get_block].
3014                         rxds[get_info.offset].virt_addr;
3015                 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
3016                         get_info.offset = 0;
3017                         ring_data->rx_curr_get_info.offset = get_info.offset;
3018                         get_block++;
3019                         if (get_block == ring_data->block_count)
3020                                 get_block = 0;
3021                         ring_data->rx_curr_get_info.block_index = get_block;
3022                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3023                 }
3024
3025                 if (ring_data->nic->config.napi) {
3026                         budget--;
3027                         napi_pkts++;
3028                         if (!budget)
3029                                 break;
3030                 }
3031                 pkt_cnt++;
3032                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3033                         break;
3034         }
3035         if (ring_data->lro) {
3036                 /* Clear all LRO sessions before exiting */
3037                 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
3038                         struct lro *lro = &ring_data->lro0_n[i];
3039                         if (lro->in_use) {
3040                                 update_L3L4_header(ring_data->nic, lro);
3041                                 queue_rx_frame(lro->parent, lro->vlan_tag);
3042                                 clear_lro_session(lro);
3043                         }
3044                 }
3045         }
3046         return napi_pkts;
3047 }
3048
3049 /**
3050  *  tx_intr_handler - Transmit interrupt handler
3051  *  @nic : device private variable
3052  *  Description:
3053  *  If an interrupt was raised to indicate DMA complete of the
3054  *  Tx packet, this function is called. It identifies the last TxD
3055  *  whose buffer was freed and frees all skbs whose data have already
3056  *  DMA'ed into the NICs internal memory.
3057  *  Return Value:
3058  *  NONE
3059  */
3060
3061 static void tx_intr_handler(struct fifo_info *fifo_data)
3062 {
3063         struct s2io_nic *nic = fifo_data->nic;
3064         struct tx_curr_get_info get_info, put_info;
3065         struct sk_buff *skb = NULL;
3066         struct TxD *txdlp;
3067         int pkt_cnt = 0;
3068         unsigned long flags = 0;
3069         u8 err_mask;
3070         struct stat_block *stats = nic->mac_control.stats_info;
3071         struct swStat *swstats = &stats->sw_stat;
3072
3073         if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3074                 return;
3075
3076         get_info = fifo_data->tx_curr_get_info;
3077         memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3078         txdlp = (struct TxD *)
3079                 fifo_data->list_info[get_info.offset].list_virt_addr;
3080         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3081                (get_info.offset != put_info.offset) &&
3082                (txdlp->Host_Control)) {
3083                 /* Check for TxD errors */
3084                 if (txdlp->Control_1 & TXD_T_CODE) {
3085                         unsigned long long err;
3086                         err = txdlp->Control_1 & TXD_T_CODE;
3087                         if (err & 0x1) {
3088                                 swstats->parity_err_cnt++;
3089                         }
3090
3091                         /* update t_code statistics */
3092                         err_mask = err >> 48;
3093                         switch (err_mask) {
3094                         case 2:
3095                                 swstats->tx_buf_abort_cnt++;
3096                                 break;
3097
3098                         case 3:
3099                                 swstats->tx_desc_abort_cnt++;
3100                                 break;
3101
3102                         case 7:
3103                                 swstats->tx_parity_err_cnt++;
3104                                 break;
3105
3106                         case 10:
3107                                 swstats->tx_link_loss_cnt++;
3108                                 break;
3109
3110                         case 15:
3111                                 swstats->tx_list_proc_err_cnt++;
3112                                 break;
3113                         }
3114                 }
3115
3116                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3117                 if (skb == NULL) {
3118                         spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3119                         DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3120                                   __func__);
3121                         return;
3122                 }
3123                 pkt_cnt++;
3124
3125                 /* Updating the statistics block */
3126                 swstats->mem_freed += skb->truesize;
3127                 dev_kfree_skb_irq(skb);
3128
3129                 get_info.offset++;
3130                 if (get_info.offset == get_info.fifo_len + 1)
3131                         get_info.offset = 0;
3132                 txdlp = (struct TxD *)
3133                         fifo_data->list_info[get_info.offset].list_virt_addr;
3134                 fifo_data->tx_curr_get_info.offset = get_info.offset;
3135         }
3136
3137         s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3138
3139         spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3140 }
3141
3142 /**
3143  *  s2io_mdio_write - Function to write in to MDIO registers
3144  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3145  *  @addr     : address value
3146  *  @value    : data value
3147  *  @dev      : pointer to net_device structure
3148  *  Description:
3149  *  This function is used to write values to the MDIO registers
3150  *  NONE
3151  */
3152 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3153                             struct net_device *dev)
3154 {
3155         u64 val64;
3156         struct s2io_nic *sp = netdev_priv(dev);
3157         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3158
3159         /* address transaction */
3160         val64 = MDIO_MMD_INDX_ADDR(addr) |
3161                 MDIO_MMD_DEV_ADDR(mmd_type) |
3162                 MDIO_MMS_PRT_ADDR(0x0);
3163         writeq(val64, &bar0->mdio_control);
3164         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3165         writeq(val64, &bar0->mdio_control);
3166         udelay(100);
3167
3168         /* Data transaction */
3169         val64 = MDIO_MMD_INDX_ADDR(addr) |
3170                 MDIO_MMD_DEV_ADDR(mmd_type) |
3171                 MDIO_MMS_PRT_ADDR(0x0) |
3172                 MDIO_MDIO_DATA(value) |
3173                 MDIO_OP(MDIO_OP_WRITE_TRANS);
3174         writeq(val64, &bar0->mdio_control);
3175         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3176         writeq(val64, &bar0->mdio_control);
3177         udelay(100);
3178
3179         val64 = MDIO_MMD_INDX_ADDR(addr) |
3180                 MDIO_MMD_DEV_ADDR(mmd_type) |
3181                 MDIO_MMS_PRT_ADDR(0x0) |
3182                 MDIO_OP(MDIO_OP_READ_TRANS);
3183         writeq(val64, &bar0->mdio_control);
3184         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3185         writeq(val64, &bar0->mdio_control);
3186         udelay(100);
3187 }
3188
3189 /**
3190  *  s2io_mdio_read - Function to write in to MDIO registers
3191  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3192  *  @addr     : address value
3193  *  @dev      : pointer to net_device structure
3194  *  Description:
3195  *  This function is used to read values to the MDIO registers
3196  *  NONE
3197  */
3198 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3199 {
3200         u64 val64 = 0x0;
3201         u64 rval64 = 0x0;
3202         struct s2io_nic *sp = netdev_priv(dev);
3203         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3204
3205         /* address transaction */
3206         val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3207                          | MDIO_MMD_DEV_ADDR(mmd_type)
3208                          | MDIO_MMS_PRT_ADDR(0x0));
3209         writeq(val64, &bar0->mdio_control);
3210         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3211         writeq(val64, &bar0->mdio_control);
3212         udelay(100);
3213
3214         /* Data transaction */
3215         val64 = MDIO_MMD_INDX_ADDR(addr) |
3216                 MDIO_MMD_DEV_ADDR(mmd_type) |
3217                 MDIO_MMS_PRT_ADDR(0x0) |
3218                 MDIO_OP(MDIO_OP_READ_TRANS);
3219         writeq(val64, &bar0->mdio_control);
3220         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3221         writeq(val64, &bar0->mdio_control);
3222         udelay(100);
3223
3224         /* Read the value from regs */
3225         rval64 = readq(&bar0->mdio_control);
3226         rval64 = rval64 & 0xFFFF0000;
3227         rval64 = rval64 >> 16;
3228         return rval64;
3229 }
3230
3231 /**
3232  *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
3233  *  @counter      : counter value to be updated
3234  *  @flag         : flag to indicate the status
3235  *  @type         : counter type
3236  *  Description:
3237  *  This function is to check the status of the xpak counters value
3238  *  NONE
3239  */
3240
3241 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3242                                   u16 flag, u16 type)
3243 {
3244         u64 mask = 0x3;
3245         u64 val64;
3246         int i;
3247         for (i = 0; i < index; i++)
3248                 mask = mask << 0x2;
3249
3250         if (flag > 0) {
3251                 *counter = *counter + 1;
3252                 val64 = *regs_stat & mask;
3253                 val64 = val64 >> (index * 0x2);
3254                 val64 = val64 + 1;
3255                 if (val64 == 3) {
3256                         switch (type) {
3257                         case 1:
3258                                 DBG_PRINT(ERR_DBG,
3259                                           "Take Xframe NIC out of service.\n");
3260                                 DBG_PRINT(ERR_DBG,
3261 "Excessive temperatures may result in premature transceiver failure.\n");
3262                                 break;
3263                         case 2:
3264                                 DBG_PRINT(ERR_DBG,
3265                                           "Take Xframe NIC out of service.\n");
3266                                 DBG_PRINT(ERR_DBG,
3267 "Excessive bias currents may indicate imminent laser diode failure.\n");
3268                                 break;
3269                         case 3:
3270                                 DBG_PRINT(ERR_DBG,
3271                                           "Take Xframe NIC out of service.\n");
3272                                 DBG_PRINT(ERR_DBG,
3273 "Excessive laser output power may saturate far-end receiver.\n");
3274                                 break;
3275                         default:
3276                                 DBG_PRINT(ERR_DBG,
3277                                           "Incorrect XPAK Alarm type\n");
3278                         }
3279                         val64 = 0x0;
3280                 }
3281                 val64 = val64 << (index * 0x2);
3282                 *regs_stat = (*regs_stat & (~mask)) | (val64);
3283
3284         } else {
3285                 *regs_stat = *regs_stat & (~mask);
3286         }
3287 }
3288
3289 /**
3290  *  s2io_updt_xpak_counter - Function to update the xpak counters
3291  *  @dev         : pointer to net_device struct
3292  *  Description:
3293  *  This function is to upate the status of the xpak counters value
3294  *  NONE
3295  */
3296 static void s2io_updt_xpak_counter(struct net_device *dev)
3297 {
3298         u16 flag  = 0x0;
3299         u16 type  = 0x0;
3300         u16 val16 = 0x0;
3301         u64 val64 = 0x0;
3302         u64 addr  = 0x0;
3303
3304         struct s2io_nic *sp = netdev_priv(dev);
3305         struct stat_block *stats = sp->mac_control.stats_info;
3306         struct xpakStat *xstats = &stats->xpak_stat;
3307
3308         /* Check the communication with the MDIO slave */
3309         addr = MDIO_CTRL1;
3310         val64 = 0x0;
3311         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3312         if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
3313                 DBG_PRINT(ERR_DBG,
3314                           "ERR: MDIO slave access failed - Returned %llx\n",
3315                           (unsigned long long)val64);
3316                 return;
3317         }
3318
3319         /* Check for the expected value of control reg 1 */
3320         if (val64 != MDIO_CTRL1_SPEED10G) {
3321                 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3322                           "Returned: %llx- Expected: 0x%x\n",
3323                           (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
3324                 return;
3325         }
3326
3327         /* Loading the DOM register to MDIO register */
3328         addr = 0xA100;
3329         s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3330         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3331
3332         /* Reading the Alarm flags */
3333         addr = 0xA070;
3334         val64 = 0x0;
3335         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3336
3337         flag = CHECKBIT(val64, 0x7);
3338         type = 1;
3339         s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3340                               &xstats->xpak_regs_stat,
3341                               0x0, flag, type);
3342
3343         if (CHECKBIT(val64, 0x6))
3344                 xstats->alarm_transceiver_temp_low++;
3345
3346         flag = CHECKBIT(val64, 0x3);
3347         type = 2;
3348         s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3349                               &xstats->xpak_regs_stat,
3350                               0x2, flag, type);
3351
3352         if (CHECKBIT(val64, 0x2))
3353                 xstats->alarm_laser_bias_current_low++;
3354
3355         flag = CHECKBIT(val64, 0x1);
3356         type = 3;
3357         s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3358                               &xstats->xpak_regs_stat,
3359                               0x4, flag, type);
3360
3361         if (CHECKBIT(val64, 0x0))
3362                 xstats->alarm_laser_output_power_low++;
3363
3364         /* Reading the Warning flags */
3365         addr = 0xA074;
3366         val64 = 0x0;
3367         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3368
3369         if (CHECKBIT(val64, 0x7))
3370                 xstats->warn_transceiver_temp_high++;
3371
3372         if (CHECKBIT(val64, 0x6))
3373                 xstats->warn_transceiver_temp_low++;
3374
3375         if (CHECKBIT(val64, 0x3))
3376                 xstats->warn_laser_bias_current_high++;
3377
3378         if (CHECKBIT(val64, 0x2))
3379                 xstats->warn_laser_bias_current_low++;
3380
3381         if (CHECKBIT(val64, 0x1))
3382                 xstats->warn_laser_output_power_high++;
3383
3384         if (CHECKBIT(val64, 0x0))
3385                 xstats->warn_laser_output_power_low++;
3386 }
3387
3388 /**
3389  *  wait_for_cmd_complete - waits for a command to complete.
3390  *  @sp : private member of the device structure, which is a pointer to the
3391  *  s2io_nic structure.
3392  *  Description: Function that waits for a command to Write into RMAC
3393  *  ADDR DATA registers to be completed and returns either success or
3394  *  error depending on whether the command was complete or not.
3395  *  Return value:
3396  *   SUCCESS on success and FAILURE on failure.
3397  */
3398
3399 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3400                                  int bit_state)
3401 {
3402         int ret = FAILURE, cnt = 0, delay = 1;
3403         u64 val64;
3404
3405         if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3406                 return FAILURE;
3407
3408         do {
3409                 val64 = readq(addr);
3410                 if (bit_state == S2IO_BIT_RESET) {
3411                         if (!(val64 & busy_bit)) {
3412                                 ret = SUCCESS;
3413                                 break;
3414                         }
3415                 } else {
3416                         if (val64 & busy_bit) {
3417                                 ret = SUCCESS;
3418                                 break;
3419                         }
3420                 }
3421
3422                 if (in_interrupt())
3423                         mdelay(delay);
3424                 else
3425                         msleep(delay);
3426
3427                 if (++cnt >= 10)
3428                         delay = 50;
3429         } while (cnt < 20);
3430         return ret;
3431 }
3432 /*
3433  * check_pci_device_id - Checks if the device id is supported
3434  * @id : device id
3435  * Description: Function to check if the pci device id is supported by driver.
3436  * Return value: Actual device id if supported else PCI_ANY_ID
3437  */
3438 static u16 check_pci_device_id(u16 id)
3439 {
3440         switch (id) {
3441         case PCI_DEVICE_ID_HERC_WIN:
3442         case PCI_DEVICE_ID_HERC_UNI:
3443                 return XFRAME_II_DEVICE;
3444         case PCI_DEVICE_ID_S2IO_UNI:
3445         case PCI_DEVICE_ID_S2IO_WIN:
3446                 return XFRAME_I_DEVICE;
3447         default:
3448                 return PCI_ANY_ID;
3449         }
3450 }
3451
3452 /**
3453  *  s2io_reset - Resets the card.
3454  *  @sp : private member of the device structure.
3455  *  Description: Function to Reset the card. This function then also
3456  *  restores the previously saved PCI configuration space registers as
3457  *  the card reset also resets the configuration space.
3458  *  Return value:
3459  *  void.
3460  */
3461
3462 static void s2io_reset(struct s2io_nic *sp)
3463 {
3464         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3465         u64 val64;
3466         u16 subid, pci_cmd;
3467         int i;
3468         u16 val16;
3469         unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3470         unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3471         struct stat_block *stats;
3472         struct swStat *swstats;
3473
3474         DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3475                   __func__, pci_name(sp->pdev));
3476
3477         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3478         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3479
3480         val64 = SW_RESET_ALL;
3481         writeq(val64, &bar0->sw_reset);
3482         if (strstr(sp->product_name, "CX4"))
3483                 msleep(750);
3484         msleep(250);
3485         for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3486
3487                 /* Restore the PCI state saved during initialization. */
3488                 pci_restore_state(sp->pdev);
3489                 pci_save_state(sp->pdev);
3490                 pci_read_config_word(sp->pdev, 0x2, &val16);
3491                 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3492                         break;
3493                 msleep(200);
3494         }
3495
3496         if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3497                 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
3498
3499         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3500
3501         s2io_init_pci(sp);
3502
3503         /* Set swapper to enable I/O register access */
3504         s2io_set_swapper(sp);
3505
3506         /* restore mac_addr entries */
3507         do_s2io_restore_unicast_mc(sp);
3508
3509         /* Restore the MSIX table entries from local variables */
3510         restore_xmsi_data(sp);
3511
3512         /* Clear certain PCI/PCI-X fields after reset */
3513         if (sp->device_type == XFRAME_II_DEVICE) {
3514                 /* Clear "detected parity error" bit */
3515                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3516
3517                 /* Clearing PCIX Ecc status register */
3518                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3519
3520                 /* Clearing PCI_STATUS error reflected here */
3521                 writeq(s2BIT(62), &bar0->txpic_int_reg);
3522         }
3523
3524         /* Reset device statistics maintained by OS */
3525         memset(&sp->stats, 0, sizeof(struct net_device_stats));
3526
3527         stats = sp->mac_control.stats_info;
3528         swstats = &stats->sw_stat;
3529
3530         /* save link up/down time/cnt, reset/memory/watchdog cnt */
3531         up_cnt = swstats->link_up_cnt;
3532         down_cnt = swstats->link_down_cnt;
3533         up_time = swstats->link_up_time;
3534         down_time = swstats->link_down_time;
3535         reset_cnt = swstats->soft_reset_cnt;
3536         mem_alloc_cnt = swstats->mem_allocated;
3537         mem_free_cnt = swstats->mem_freed;
3538         watchdog_cnt = swstats->watchdog_timer_cnt;
3539
3540         memset(stats, 0, sizeof(struct stat_block));
3541
3542         /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3543         swstats->link_up_cnt = up_cnt;
3544         swstats->link_down_cnt = down_cnt;
3545         swstats->link_up_time = up_time;
3546         swstats->link_down_time = down_time;
3547         swstats->soft_reset_cnt = reset_cnt;
3548         swstats->mem_allocated = mem_alloc_cnt;
3549         swstats->mem_freed = mem_free_cnt;
3550         swstats->watchdog_timer_cnt = watchdog_cnt;
3551
3552         /* SXE-002: Configure link and activity LED to turn it off */
3553         subid = sp->pdev->subsystem_device;
3554         if (((subid & 0xFF) >= 0x07) &&
3555             (sp->device_type == XFRAME_I_DEVICE)) {
3556                 val64 = readq(&bar0->gpio_control);
3557                 val64 |= 0x0000800000000000ULL;
3558                 writeq(val64, &bar0->gpio_control);
3559                 val64 = 0x0411040400000000ULL;
3560                 writeq(val64, (void __iomem *)bar0 + 0x2700);
3561         }
3562
3563         /*
3564          * Clear spurious ECC interrupts that would have occurred on
3565          * XFRAME II cards after reset.
3566          */
3567         if (sp->device_type == XFRAME_II_DEVICE) {
3568                 val64 = readq(&bar0->pcc_err_reg);
3569                 writeq(val64, &bar0->pcc_err_reg);
3570         }
3571
3572         sp->device_enabled_once = false;
3573 }
3574
3575 /**
3576  *  s2io_set_swapper - to set the swapper controle on the card
3577  *  @sp : private member of the device structure,
3578  *  pointer to the s2io_nic structure.
3579  *  Description: Function to set the swapper control on the card
3580  *  correctly depending on the 'endianness' of the system.
3581  *  Return value:
3582  *  SUCCESS on success and FAILURE on failure.
3583  */
3584
3585 static int s2io_set_swapper(struct s2io_nic *sp)
3586 {
3587         struct net_device *dev = sp->dev;
3588         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3589         u64 val64, valt, valr;
3590
3591         /*
3592          * Set proper endian settings and verify the same by reading
3593          * the PIF Feed-back register.
3594          */
3595
3596         val64 = readq(&bar0->pif_rd_swapper_fb);
3597         if (val64 != 0x0123456789ABCDEFULL) {
3598                 int i = 0;
3599                 static const u64 value[] = {
3600                         0xC30000C3C30000C3ULL,  /* FE=1, SE=1 */
3601                         0x8100008181000081ULL,  /* FE=1, SE=0 */
3602                         0x4200004242000042ULL,  /* FE=0, SE=1 */
3603                         0                       /* FE=0, SE=0 */
3604                 };
3605
3606                 while (i < 4) {
3607                         writeq(value[i], &bar0->swapper_ctrl);
3608                         val64 = readq(&bar0->pif_rd_swapper_fb);
3609                         if (val64 == 0x0123456789ABCDEFULL)
3610                                 break;
3611                         i++;
3612                 }
3613                 if (i == 4) {
3614                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3615                                   "feedback read %llx\n",
3616                                   dev->name, (unsigned long long)val64);
3617                         return FAILURE;
3618                 }
3619                 valr = value[i];
3620         } else {
3621                 valr = readq(&bar0->swapper_ctrl);
3622         }
3623
3624         valt = 0x0123456789ABCDEFULL;
3625         writeq(valt, &bar0->xmsi_address);
3626         val64 = readq(&bar0->xmsi_address);
3627
3628         if (val64 != valt) {
3629                 int i = 0;
3630                 static const u64 value[] = {
3631                         0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
3632                         0x0081810000818100ULL,  /* FE=1, SE=0 */
3633                         0x0042420000424200ULL,  /* FE=0, SE=1 */
3634                         0                       /* FE=0, SE=0 */
3635                 };
3636
3637                 while (i < 4) {
3638                         writeq((value[i] | valr), &bar0->swapper_ctrl);
3639                         writeq(valt, &bar0->xmsi_address);
3640                         val64 = readq(&bar0->xmsi_address);
3641                         if (val64 == valt)
3642                                 break;
3643                         i++;
3644                 }
3645                 if (i == 4) {
3646                         unsigned long long x = val64;
3647                         DBG_PRINT(ERR_DBG,
3648                                   "Write failed, Xmsi_addr reads:0x%llx\n", x);
3649                         return FAILURE;
3650                 }
3651         }
3652         val64 = readq(&bar0->swapper_ctrl);
3653         val64 &= 0xFFFF000000000000ULL;
3654
3655 #ifdef __BIG_ENDIAN
3656         /*
3657          * The device by default set to a big endian format, so a
3658          * big endian driver need not set anything.
3659          */
3660         val64 |= (SWAPPER_CTRL_TXP_FE |
3661                   SWAPPER_CTRL_TXP_SE |
3662                   SWAPPER_CTRL_TXD_R_FE |
3663                   SWAPPER_CTRL_TXD_W_FE |
3664                   SWAPPER_CTRL_TXF_R_FE |
3665                   SWAPPER_CTRL_RXD_R_FE |
3666                   SWAPPER_CTRL_RXD_W_FE |
3667                   SWAPPER_CTRL_RXF_W_FE |
3668                   SWAPPER_CTRL_XMSI_FE |
3669                   SWAPPER_CTRL_STATS_FE |
3670                   SWAPPER_CTRL_STATS_SE);
3671         if (sp->config.intr_type == INTA)
3672                 val64 |= SWAPPER_CTRL_XMSI_SE;
3673         writeq(val64, &bar0->swapper_ctrl);
3674 #else
3675         /*
3676          * Initially we enable all bits to make it accessible by the
3677          * driver, then we selectively enable only those bits that
3678          * we want to set.
3679          */
3680         val64 |= (SWAPPER_CTRL_TXP_FE |
3681                   SWAPPER_CTRL_TXP_SE |
3682                   SWAPPER_CTRL_TXD_R_FE |
3683                   SWAPPER_CTRL_TXD_R_SE |
3684                   SWAPPER_CTRL_TXD_W_FE |
3685                   SWAPPER_CTRL_TXD_W_SE |
3686                   SWAPPER_CTRL_TXF_R_FE |
3687                   SWAPPER_CTRL_RXD_R_FE |
3688                   SWAPPER_CTRL_RXD_R_SE |
3689                   SWAPPER_CTRL_RXD_W_FE |
3690                   SWAPPER_CTRL_RXD_W_SE |
3691                   SWAPPER_CTRL_RXF_W_FE |
3692                   SWAPPER_CTRL_XMSI_FE |
3693                   SWAPPER_CTRL_STATS_FE |
3694                   SWAPPER_CTRL_STATS_SE);
3695         if (sp->config.intr_type == INTA)
3696                 val64 |= SWAPPER_CTRL_XMSI_SE;
3697         writeq(val64, &bar0->swapper_ctrl);
3698 #endif
3699         val64 = readq(&bar0->swapper_ctrl);
3700
3701         /*
3702          * Verifying if endian settings are accurate by reading a
3703          * feedback register.
3704          */
3705         val64 = readq(&bar0->pif_rd_swapper_fb);
3706         if (val64 != 0x0123456789ABCDEFULL) {
3707                 /* Endian settings are incorrect, calls for another dekko. */
3708                 DBG_PRINT(ERR_DBG,
3709                           "%s: Endian settings are wrong, feedback read %llx\n",
3710                           dev->name, (unsigned long long)val64);
3711                 return FAILURE;
3712         }
3713
3714         return SUCCESS;
3715 }
3716
3717 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3718 {
3719         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3720         u64 val64;
3721         int ret = 0, cnt = 0;
3722
3723         do {
3724                 val64 = readq(&bar0->xmsi_access);
3725                 if (!(val64 & s2BIT(15)))
3726                         break;
3727                 mdelay(1);
3728                 cnt++;
3729         } while (cnt < 5);
3730         if (cnt == 5) {
3731                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3732                 ret = 1;
3733         }
3734
3735         return ret;
3736 }
3737
3738 static void restore_xmsi_data(struct s2io_nic *nic)
3739 {
3740         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3741         u64 val64;
3742         int i, msix_index;
3743
3744         if (nic->device_type == XFRAME_I_DEVICE)
3745                 return;
3746
3747         for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3748                 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3749                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3750                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3751                 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3752                 writeq(val64, &bar0->xmsi_access);
3753                 if (wait_for_msix_trans(nic, msix_index)) {
3754                         DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3755                                   __func__, msix_index);
3756                         continue;
3757                 }
3758         }
3759 }
3760
3761 static void store_xmsi_data(struct s2io_nic *nic)
3762 {
3763         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3764         u64 val64, addr, data;
3765         int i, msix_index;
3766
3767         if (nic->device_type == XFRAME_I_DEVICE)
3768                 return;
3769
3770         /* Store and display */
3771         for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3772                 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3773                 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3774                 writeq(val64, &bar0->xmsi_access);
3775                 if (wait_for_msix_trans(nic, msix_index)) {
3776                         DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3777                                   __func__, msix_index);
3778                         continue;
3779                 }
3780                 addr = readq(&bar0->xmsi_address);
3781                 data = readq(&bar0->xmsi_data);
3782                 if (addr && data) {
3783                         nic->msix_info[i].addr = addr;
3784                         nic->msix_info[i].data = data;
3785                 }
3786         }
3787 }
3788
3789 static int s2io_enable_msi_x(struct s2io_nic *nic)
3790 {
3791         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3792         u64 rx_mat;
3793         u16 msi_control; /* Temp variable */
3794         int ret, i, j, msix_indx = 1;
3795         int size;
3796         struct stat_block *stats = nic->mac_control.stats_info;
3797         struct swStat *swstats = &stats->sw_stat;
3798
3799         size = nic->num_entries * sizeof(struct msix_entry);
3800         nic->entries = kzalloc(size, GFP_KERNEL);
3801         if (!nic->entries) {
3802                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3803                           __func__);
3804                 swstats->mem_alloc_fail_cnt++;
3805                 return -ENOMEM;
3806         }
3807         swstats->mem_allocated += size;
3808
3809         size = nic->num_entries * sizeof(struct s2io_msix_entry);
3810         nic->s2io_entries = kzalloc(size, GFP_KERNEL);
3811         if (!nic->s2io_entries) {
3812                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3813                           __func__);
3814                 swstats->mem_alloc_fail_cnt++;
3815                 kfree(nic->entries);
3816                 swstats->mem_freed
3817                         += (nic->num_entries * sizeof(struct msix_entry));
3818                 return -ENOMEM;
3819         }
3820         swstats->mem_allocated += size;
3821
3822         nic->entries[0].entry = 0;
3823         nic->s2io_entries[0].entry = 0;
3824         nic->s2io_entries[0].in_use = MSIX_FLG;
3825         nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3826         nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3827
3828         for (i = 1; i < nic->num_entries; i++) {
3829                 nic->entries[i].entry = ((i - 1) * 8) + 1;
3830                 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3831                 nic->s2io_entries[i].arg = NULL;
3832                 nic->s2io_entries[i].in_use = 0;
3833         }
3834
3835         rx_mat = readq(&bar0->rx_mat);
3836         for (j = 0; j < nic->config.rx_ring_num; j++) {
3837                 rx_mat |= RX_MAT_SET(j, msix_indx);
3838                 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3839                 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3840                 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3841                 msix_indx += 8;
3842         }
3843         writeq(rx_mat, &bar0->rx_mat);
3844         readq(&bar0->rx_mat);
3845
3846         ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
3847         /* We fail init if error or we get less vectors than min required */
3848         if (ret) {
3849                 DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
3850                 kfree(nic->entries);
3851                 swstats->mem_freed += nic->num_entries *
3852                         sizeof(struct msix_entry);
3853                 kfree(nic->s2io_entries);
3854                 swstats->mem_freed += nic->num_entries *
3855                         sizeof(struct s2io_msix_entry);
3856                 nic->entries = NULL;
3857                 nic->s2io_entries = NULL;
3858                 return -ENOMEM;
3859         }
3860
3861         /*
3862          * To enable MSI-X, MSI also needs to be enabled, due to a bug
3863          * in the herc NIC. (Temp change, needs to be removed later)
3864          */
3865         pci_read_config_word(nic->pdev, 0x42, &msi_control);
3866         msi_control |= 0x1; /* Enable MSI */
3867         pci_write_config_word(nic->pdev, 0x42, msi_control);
3868
3869         return 0;
3870 }
3871
3872 /* Handle software interrupt used during MSI(X) test */
3873 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3874 {
3875         struct s2io_nic *sp = dev_id;
3876
3877         sp->msi_detected = 1;
3878         wake_up(&sp->msi_wait);
3879
3880         return IRQ_HANDLED;
3881 }
3882
3883 /* Test interrupt path by forcing a a software IRQ */
3884 static int s2io_test_msi(struct s2io_nic *sp)
3885 {
3886         struct pci_dev *pdev = sp->pdev;
3887         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3888         int err;
3889         u64 val64, saved64;
3890
3891         err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3892                           sp->name, sp);
3893         if (err) {
3894                 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3895                           sp->dev->name, pci_name(pdev), pdev->irq);
3896                 return err;
3897         }
3898
3899         init_waitqueue_head(&sp->msi_wait);
3900         sp->msi_detected = 0;
3901
3902         saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3903         val64 |= SCHED_INT_CTRL_ONE_SHOT;
3904         val64 |= SCHED_INT_CTRL_TIMER_EN;
3905         val64 |= SCHED_INT_CTRL_INT2MSI(1);
3906         writeq(val64, &bar0->scheduled_int_ctrl);
3907
3908         wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3909
3910         if (!sp->msi_detected) {
3911                 /* MSI(X) test failed, go back to INTx mode */
3912                 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3913                           "using MSI(X) during test\n",
3914                           sp->dev->name, pci_name(pdev));
3915
3916                 err = -EOPNOTSUPP;
3917         }
3918
3919         free_irq(sp->entries[1].vector, sp);
3920
3921         writeq(saved64, &bar0->scheduled_int_ctrl);
3922
3923         return err;
3924 }
3925
3926 static void remove_msix_isr(struct s2io_nic *sp)
3927 {
3928         int i;
3929         u16 msi_control;
3930
3931         for (i = 0; i < sp->num_entries; i++) {
3932                 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
3933                         int vector = sp->entries[i].vector;
3934                         void *arg = sp->s2io_entries[i].arg;
3935                         free_irq(vector, arg);
3936                 }
3937         }
3938
3939         kfree(sp->entries);
3940         kfree(sp->s2io_entries);
3941         sp->entries = NULL;
3942         sp->s2io_entries = NULL;
3943
3944         pci_read_config_word(sp->pdev, 0x42, &msi_control);
3945         msi_control &= 0xFFFE; /* Disable MSI */
3946         pci_write_config_word(sp->pdev, 0x42, msi_control);
3947
3948         pci_disable_msix(sp->pdev);
3949 }
3950
3951 static void remove_inta_isr(struct s2io_nic *sp)
3952 {
3953         struct net_device *dev = sp->dev;
3954
3955         free_irq(sp->pdev->irq, dev);
3956 }
3957
3958 /* ********************************************************* *
3959  * Functions defined below concern the OS part of the driver *
3960  * ********************************************************* */
3961
3962 /**
3963  *  s2io_open - open entry point of the driver
3964  *  @dev : pointer to the device structure.
3965  *  Description:
3966  *  This function is the open entry point of the driver. It mainly calls a
3967  *  function to allocate Rx buffers and inserts them into the buffer
3968  *  descriptors and then enables the Rx part of the NIC.
3969  *  Return value:
3970  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3971  *   file on failure.
3972  */
3973
3974 static int s2io_open(struct net_device *dev)
3975 {
3976         struct s2io_nic *sp = netdev_priv(dev);
3977         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
3978         int err = 0;
3979
3980         /*
3981          * Make sure you have link off by default every time
3982          * Nic is initialized
3983          */
3984         netif_carrier_off(dev);
3985         sp->last_link_state = 0;
3986
3987         /* Initialize H/W and enable interrupts */
3988         err = s2io_card_up(sp);
3989         if (err) {
3990                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3991                           dev->name);
3992                 goto hw_init_failed;
3993         }
3994
3995         if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
3996                 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3997                 s2io_card_down(sp);
3998                 err = -ENODEV;
3999                 goto hw_init_failed;
4000         }
4001         s2io_start_all_tx_queue(sp);
4002         return 0;
4003
4004 hw_init_failed:
4005         if (sp->config.intr_type == MSI_X) {
4006                 if (sp->entries) {
4007                         kfree(sp->entries);
4008                         swstats->mem_freed += sp->num_entries *
4009                                 sizeof(struct msix_entry);
4010                 }
4011                 if (sp->s2io_entries) {
4012                         kfree(sp->s2io_entries);
4013                         swstats->mem_freed += sp->num_entries *
4014                                 sizeof(struct s2io_msix_entry);
4015                 }
4016         }
4017         return err;
4018 }
4019
4020 /**
4021  *  s2io_close -close entry point of the driver
4022  *  @dev : device pointer.
4023  *  Description:
4024  *  This is the stop entry point of the driver. It needs to undo exactly
4025  *  whatever was done by the open entry point,thus it's usually referred to
4026  *  as the close function.Among other things this function mainly stops the
4027  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4028  *  Return value:
4029  *  0 on success and an appropriate (-)ve integer as defined in errno.h
4030  *  file on failure.
4031  */
4032
4033 static int s2io_close(struct net_device *dev)
4034 {
4035         struct s2io_nic *sp = netdev_priv(dev);
4036         struct config_param *config = &sp->config;
4037         u64 tmp64;
4038         int offset;
4039
4040         /* Return if the device is already closed               *
4041          *  Can happen when s2io_card_up failed in change_mtu    *
4042          */
4043         if (!is_s2io_card_up(sp))
4044                 return 0;
4045
4046         s2io_stop_all_tx_queue(sp);
4047         /* delete all populated mac entries */
4048         for (offset = 1; offset < config->max_mc_addr; offset++) {
4049                 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4050                 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4051                         do_s2io_delete_unicast_mc(sp, tmp64);
4052         }
4053
4054         s2io_card_down(sp);
4055
4056         return 0;
4057 }
4058
4059 /**
4060  *  s2io_xmit - Tx entry point of te driver
4061  *  @skb : the socket buffer containing the Tx data.
4062  *  @dev : device pointer.
4063  *  Description :
4064  *  This function is the Tx entry point of the driver. S2IO NIC supports
4065  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
4066  *  NOTE: when device can't queue the pkt,just the trans_start variable will
4067  *  not be upadted.
4068  *  Return value:
4069  *  0 on success & 1 on failure.
4070  */
4071
4072 static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4073 {
4074         struct s2io_nic *sp = netdev_priv(dev);
4075         u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4076         register u64 val64;
4077         struct TxD *txdp;
4078         struct TxFIFO_element __iomem *tx_fifo;
4079         unsigned long flags = 0;
4080         u16 vlan_tag = 0;
4081         struct fifo_info *fifo = NULL;
4082         int do_spin_lock = 1;
4083         int offload_type;
4084         int enable_per_list_interrupt = 0;
4085         struct config_param *config = &sp->config;
4086         struct mac_info *mac_control = &sp->mac_control;
4087         struct stat_block *stats = mac_control->stats_info;
4088         struct swStat *swstats = &stats->sw_stat;
4089
4090         DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4091
4092         if (unlikely(skb->len <= 0)) {
4093                 DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
4094                 dev_kfree_skb_any(skb);
4095                 return NETDEV_TX_OK;
4096         }
4097
4098         if (!is_s2io_card_up(sp)) {
4099                 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4100                           dev->name);
4101                 dev_kfree_skb(skb);
4102                 return NETDEV_TX_OK;
4103         }
4104
4105         queue = 0;
4106         if (vlan_tx_tag_present(skb))
4107                 vlan_tag = vlan_tx_tag_get(skb);
4108         if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4109                 if (skb->protocol == htons(ETH_P_IP)) {
4110                         struct iphdr *ip;
4111                         struct tcphdr *th;
4112                         ip = ip_hdr(skb);
4113
4114                         if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4115                                 th = (struct tcphdr *)(((unsigned char *)ip) +
4116                                                        ip->ihl*4);
4117
4118                                 if (ip->protocol == IPPROTO_TCP) {
4119                                         queue_len = sp->total_tcp_fifos;
4120                                         queue = (ntohs(th->source) +
4121                                                  ntohs(th->dest)) &
4122                                                 sp->fifo_selector[queue_len - 1];
4123                                         if (queue >= queue_len)
4124                                                 queue = queue_len - 1;
4125                                 } else if (ip->protocol == IPPROTO_UDP) {
4126                                         queue_len = sp->total_udp_fifos;
4127                                         queue = (ntohs(th->source) +
4128                                                  ntohs(th->dest)) &
4129                                                 sp->fifo_selector[queue_len - 1];
4130                                         if (queue >= queue_len)
4131                                                 queue = queue_len - 1;
4132                                         queue += sp->udp_fifo_idx;
4133                                         if (skb->len > 1024)
4134                                                 enable_per_list_interrupt = 1;
4135                                         do_spin_lock = 0;
4136                                 }
4137                         }
4138                 }
4139         } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4140                 /* get fifo number based on skb->priority value */
4141                 queue = config->fifo_mapping
4142                         [skb->priority & (MAX_TX_FIFOS - 1)];
4143         fifo = &mac_control->fifos[queue];
4144
4145         if (do_spin_lock)
4146                 spin_lock_irqsave(&fifo->tx_lock, flags);
4147         else {
4148                 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4149                         return NETDEV_TX_LOCKED;
4150         }
4151
4152         if (sp->config.multiq) {
4153                 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4154                         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4155                         return NETDEV_TX_BUSY;
4156                 }
4157         } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4158                 if (netif_queue_stopped(dev)) {
4159                         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4160                         return NETDEV_TX_BUSY;
4161                 }
4162         }
4163
4164         put_off = (u16)fifo->tx_curr_put_info.offset;
4165         get_off = (u16)fifo->tx_curr_get_info.offset;
4166         txdp = (struct TxD *)fifo->list_info[put_off].list_virt_addr;
4167
4168         queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4169         /* Avoid "put" pointer going beyond "get" pointer */
4170         if (txdp->Host_Control ||
4171             ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4172                 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4173                 s2io_stop_tx_queue(sp, fifo->fifo_no);
4174                 dev_kfree_skb(skb);
4175                 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4176                 return NETDEV_TX_OK;
4177         }
4178
4179         offload_type = s2io_offload_type(skb);
4180         if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4181                 txdp->Control_1 |= TXD_TCP_LSO_EN;
4182                 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4183         }
4184         if (skb->ip_summed == CHECKSUM_PARTIAL) {
4185                 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4186                                     TXD_TX_CKO_TCP_EN |
4187                                     TXD_TX_CKO_UDP_EN);
4188         }
4189         txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4190         txdp->Control_1 |= TXD_LIST_OWN_XENA;
4191         txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4192         if (enable_per_list_interrupt)
4193                 if (put_off & (queue_len >> 5))
4194                         txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4195         if (vlan_tag) {
4196                 txdp->Control_2 |= TXD_VLAN_ENABLE;
4197                 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4198         }
4199
4200         frg_len = skb_headlen(skb);
4201         if (offload_type == SKB_GSO_UDP) {
4202                 int ufo_size;
4203
4204                 ufo_size = s2io_udp_mss(skb);
4205                 ufo_size &= ~7;
4206                 txdp->Control_1 |= TXD_UFO_EN;
4207                 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4208                 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4209 #ifdef __BIG_ENDIAN
4210                 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4211                 fifo->ufo_in_band_v[put_off] =
4212                         (__force u64)skb_shinfo(skb)->ip6_frag_id;
4213 #else
4214                 fifo->ufo_in_band_v[put_off] =
4215                         (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
4216 #endif
4217                 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4218                 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4219                                                       fifo->ufo_in_band_v,
4220                                                       sizeof(u64),
4221                                                       PCI_DMA_TODEVICE);
4222                 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4223                         goto pci_map_failed;
4224                 txdp++;
4225         }
4226
4227         txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4228                                               frg_len, PCI_DMA_TODEVICE);
4229         if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4230                 goto pci_map_failed;
4231
4232         txdp->Host_Control = (unsigned long)skb;
4233         txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4234         if (offload_type == SKB_GSO_UDP)
4235                 txdp->Control_1 |= TXD_UFO_EN;
4236
4237         frg_cnt = skb_shinfo(skb)->nr_frags;
4238         /* For fragmented SKB. */
4239         for (i = 0; i < frg_cnt; i++) {
4240                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4241                 /* A '0' length fragment will be ignored */
4242                 if (!frag->size)
4243                         continue;
4244                 txdp++;
4245                 txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4246                                                          frag->page_offset,
4247                                                          frag->size,
4248                                                          PCI_DMA_TODEVICE);
4249                 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4250                 if (offload_type == SKB_GSO_UDP)
4251                         txdp->Control_1 |= TXD_UFO_EN;
4252         }
4253         txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4254
4255         if (offload_type == SKB_GSO_UDP)
4256                 frg_cnt++; /* as Txd0 was used for inband header */
4257
4258         tx_fifo = mac_control->tx_FIFO_start[queue];
4259         val64 = fifo->list_info[put_off].list_phy_addr;
4260         writeq(val64, &tx_fifo->TxDL_Pointer);
4261
4262         val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4263                  TX_FIFO_LAST_LIST);
4264         if (offload_type)
4265                 val64 |= TX_FIFO_SPECIAL_FUNC;
4266
4267         writeq(val64, &tx_fifo->List_Control);
4268
4269         mmiowb();
4270
4271         put_off++;
4272         if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4273                 put_off = 0;
4274         fifo->tx_curr_put_info.offset = put_off;
4275
4276         /* Avoid "put" pointer going beyond "get" pointer */
4277         if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4278                 swstats->fifo_full_cnt++;
4279                 DBG_PRINT(TX_DBG,
4280                           "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4281                           put_off, get_off);
4282                 s2io_stop_tx_queue(sp, fifo->fifo_no);
4283         }
4284         swstats->mem_allocated += skb->truesize;
4285         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4286
4287         if (sp->config.intr_type == MSI_X)
4288                 tx_intr_handler(fifo);
4289
4290         return NETDEV_TX_OK;
4291
4292 pci_map_failed:
4293         swstats->pci_map_fail_cnt++;
4294         s2io_stop_tx_queue(sp, fifo->fifo_no);
4295         swstats->mem_freed += skb->truesize;
4296         dev_kfree_skb(skb);
4297         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4298         return NETDEV_TX_OK;
4299 }
4300
4301 static void
4302 s2io_alarm_handle(unsigned long data)
4303 {
4304         struct s2io_nic *sp = (struct s2io_nic *)data;
4305         struct net_device *dev = sp->dev;
4306
4307         s2io_handle_errors(dev);
4308         mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4309 }
4310
4311 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4312 {
4313         struct ring_info *ring = (struct ring_info *)dev_id;
4314         struct s2io_nic *sp = ring->nic;
4315         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4316
4317         if (unlikely(!is_s2io_card_up(sp)))
4318                 return IRQ_HANDLED;
4319
4320         if (sp->config.napi) {
4321                 u8 __iomem *addr = NULL;
4322                 u8 val8 = 0;
4323
4324                 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4325                 addr += (7 - ring->ring_no);
4326                 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4327                 writeb(val8, addr);
4328                 val8 = readb(addr);
4329                 napi_schedule(&ring->napi);
4330         } else {
4331                 rx_intr_handler(ring, 0);
4332                 s2io_chk_rx_buffers(sp, ring);
4333         }
4334
4335         return IRQ_HANDLED;
4336 }
4337
4338 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4339 {
4340         int i;
4341         struct fifo_info *fifos = (struct fifo_info *)dev_id;
4342         struct s2io_nic *sp = fifos->nic;
4343         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4344         struct config_param *config  = &sp->config;
4345         u64 reason;
4346
4347         if (unlikely(!is_s2io_card_up(sp)))
4348                 return IRQ_NONE;
4349
4350         reason = readq(&bar0->general_int_status);
4351         if (unlikely(reason == S2IO_MINUS_ONE))
4352                 /* Nothing much can be done. Get out */
4353                 return IRQ_HANDLED;
4354
4355         if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4356                 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4357
4358                 if (reason & GEN_INTR_TXPIC)
4359                         s2io_txpic_intr_handle(sp);
4360
4361                 if (reason & GEN_INTR_TXTRAFFIC)
4362                         writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4363
4364                 for (i = 0; i < config->tx_fifo_num; i++)
4365                         tx_intr_handler(&fifos[i]);
4366
4367                 writeq(sp->general_int_mask, &bar0->general_int_mask);
4368                 readl(&bar0->general_int_status);
4369                 return IRQ_HANDLED;
4370         }
4371         /* The interrupt was not raised by us */
4372         return IRQ_NONE;
4373 }
4374
4375 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4376 {
4377         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4378         u64 val64;
4379
4380         val64 = readq(&bar0->pic_int_status);
4381         if (val64 & PIC_INT_GPIO) {
4382                 val64 = readq(&bar0->gpio_int_reg);
4383                 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4384                     (val64 & GPIO_INT_REG_LINK_UP)) {
4385                         /*
4386                          * This is unstable state so clear both up/down
4387                          * interrupt and adapter to re-evaluate the link state.
4388                          */
4389                         val64 |= GPIO_INT_REG_LINK_DOWN;
4390                         val64 |= GPIO_INT_REG_LINK_UP;
4391                         writeq(val64, &bar0->gpio_int_reg);
4392                         val64 = readq(&bar0->gpio_int_mask);
4393                         val64 &= ~(GPIO_INT_MASK_LINK_UP |
4394                                    GPIO_INT_MASK_LINK_DOWN);
4395                         writeq(val64, &bar0->gpio_int_mask);
4396                 } else if (val64 & GPIO_INT_REG_LINK_UP) {
4397                         val64 = readq(&bar0->adapter_status);
4398                         /* Enable Adapter */
4399                         val64 = readq(&bar0->adapter_control);
4400                         val64 |= ADAPTER_CNTL_EN;
4401                         writeq(val64, &bar0->adapter_control);
4402                         val64 |= ADAPTER_LED_ON;
4403                         writeq(val64, &bar0->adapter_control);
4404                         if (!sp->device_enabled_once)
4405                                 sp->device_enabled_once = 1;
4406
4407                         s2io_link(sp, LINK_UP);
4408                         /*
4409                          * unmask link down interrupt and mask link-up
4410                          * intr
4411                          */
4412                         val64 = readq(&bar0->gpio_int_mask);
4413                         val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4414                         val64 |= GPIO_INT_MASK_LINK_UP;
4415                         writeq(val64, &bar0->gpio_int_mask);
4416
4417                 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4418                         val64 = readq(&bar0->adapter_status);
4419                         s2io_link(sp, LINK_DOWN);
4420                         /* Link is down so unmaks link up interrupt */
4421                         val64 = readq(&bar0->gpio_int_mask);
4422                         val64 &= ~GPIO_INT_MASK_LINK_UP;
4423                         val64 |= GPIO_INT_MASK_LINK_DOWN;
4424                         writeq(val64, &bar0->gpio_int_mask);
4425
4426                         /* turn off LED */
4427                         val64 = readq(&bar0->adapter_control);
4428                         val64 = val64 & (~ADAPTER_LED_ON);
4429                         writeq(val64, &bar0->adapter_control);
4430                 }
4431         }
4432         val64 = readq(&bar0->gpio_int_mask);
4433 }
4434
4435 /**
4436  *  do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4437  *  @value: alarm bits
4438  *  @addr: address value
4439  *  @cnt: counter variable
4440  *  Description: Check for alarm and increment the counter
4441  *  Return Value:
4442  *  1 - if alarm bit set
4443  *  0 - if alarm bit is not set
4444  */
4445 static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4446                                  unsigned long long *cnt)
4447 {
4448         u64 val64;
4449         val64 = readq(addr);
4450         if (val64 & value) {
4451                 writeq(val64, addr);
4452                 (*cnt)++;
4453                 return 1;
4454         }
4455         return 0;
4456
4457 }
4458
4459 /**
4460  *  s2io_handle_errors - Xframe error indication handler
4461  *  @nic: device private variable
4462  *  Description: Handle alarms such as loss of link, single or
4463  *  double ECC errors, critical and serious errors.
4464  *  Return Value:
4465  *  NONE
4466  */
4467 static void s2io_handle_errors(void *dev_id)
4468 {
4469         struct net_device *dev = (struct net_device *)dev_id;
4470         struct s2io_nic *sp = netdev_priv(dev);
4471         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4472         u64 temp64 = 0, val64 = 0;
4473         int i = 0;
4474
4475         struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4476         struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4477
4478         if (!is_s2io_card_up(sp))
4479                 return;
4480
4481         if (pci_channel_offline(sp->pdev))
4482                 return;
4483
4484         memset(&sw_stat->ring_full_cnt, 0,
4485                sizeof(sw_stat->ring_full_cnt));
4486
4487         /* Handling the XPAK counters update */
4488         if (stats->xpak_timer_count < 72000) {
4489                 /* waiting for an hour */
4490                 stats->xpak_timer_count++;
4491         } else {
4492                 s2io_updt_xpak_counter(dev);
4493                 /* reset the count to zero */
4494                 stats->xpak_timer_count = 0;
4495         }
4496
4497         /* Handling link status change error Intr */
4498         if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4499                 val64 = readq(&bar0->mac_rmac_err_reg);
4500                 writeq(val64, &bar0->mac_rmac_err_reg);
4501                 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4502                         schedule_work(&sp->set_link_task);
4503         }
4504
4505         /* In case of a serious error, the device will be Reset. */
4506         if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4507                                   &sw_stat->serious_err_cnt))
4508                 goto reset;
4509
4510         /* Check for data parity error */
4511         if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4512                                   &sw_stat->parity_err_cnt))
4513                 goto reset;
4514
4515         /* Check for ring full counter */
4516         if (sp->device_type == XFRAME_II_DEVICE) {
4517                 val64 = readq(&bar0->ring_bump_counter1);
4518                 for (i = 0; i < 4; i++) {
4519                         temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4520                         temp64 >>= 64 - ((i+1)*16);
4521                         sw_stat->ring_full_cnt[i] += temp64;
4522                 }
4523
4524                 val64 = readq(&bar0->ring_bump_counter2);
4525                 for (i = 0; i < 4; i++) {
4526                         temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4527                         temp64 >>= 64 - ((i+1)*16);
4528                         sw_stat->ring_full_cnt[i+4] += temp64;
4529                 }
4530         }
4531
4532         val64 = readq(&bar0->txdma_int_status);
4533         /*check for pfc_err*/
4534         if (val64 & TXDMA_PFC_INT) {
4535                 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4536                                           PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4537                                           PFC_PCIX_ERR,
4538                                           &bar0->pfc_err_reg,
4539                                           &sw_stat->pfc_err_cnt))
4540                         goto reset;
4541                 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4542                                       &bar0->pfc_err_reg,
4543                                       &sw_stat->pfc_err_cnt);
4544         }
4545
4546         /*check for tda_err*/
4547         if (val64 & TXDMA_TDA_INT) {
4548                 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4549                                           TDA_SM0_ERR_ALARM |
4550                                           TDA_SM1_ERR_ALARM,
4551                                           &bar0->tda_err_reg,
4552                                           &sw_stat->tda_err_cnt))
4553                         goto reset;
4554                 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4555                                       &bar0->tda_err_reg,
4556                                       &sw_stat->tda_err_cnt);
4557         }
4558         /*check for pcc_err*/
4559         if (val64 & TXDMA_PCC_INT) {
4560                 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4561                                           PCC_N_SERR | PCC_6_COF_OV_ERR |
4562                                           PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4563                                           PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4564                                           PCC_TXB_ECC_DB_ERR,
4565                                           &bar0->pcc_err_reg,
4566                                           &sw_stat->pcc_err_cnt))
4567                         goto reset;
4568                 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4569                                       &bar0->pcc_err_reg,
4570                                       &sw_stat->pcc_err_cnt);
4571         }
4572
4573         /*check for tti_err*/
4574         if (val64 & TXDMA_TTI_INT) {
4575                 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4576                                           &bar0->tti_err_reg,
4577                                           &sw_stat->tti_err_cnt))
4578                         goto reset;
4579                 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4580                                       &bar0->tti_err_reg,
4581                                       &sw_stat->tti_err_cnt);
4582         }
4583
4584         /*check for lso_err*/
4585         if (val64 & TXDMA_LSO_INT) {
4586                 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4587                                           LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4588                                           &bar0->lso_err_reg,
4589                                           &sw_stat->lso_err_cnt))
4590                         goto reset;
4591                 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4592                                       &bar0->lso_err_reg,
4593                                       &sw_stat->lso_err_cnt);
4594         }
4595
4596         /*check for tpa_err*/
4597         if (val64 & TXDMA_TPA_INT) {
4598                 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4599                                           &bar0->tpa_err_reg,
4600                                           &sw_stat->tpa_err_cnt))
4601                         goto reset;
4602                 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4603                                       &bar0->tpa_err_reg,
4604                                       &sw_stat->tpa_err_cnt);
4605         }
4606
4607         /*check for sm_err*/
4608         if (val64 & TXDMA_SM_INT) {
4609                 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4610                                           &bar0->sm_err_reg,
4611                                           &sw_stat->sm_err_cnt))
4612                         goto reset;
4613         }
4614
4615         val64 = readq(&bar0->mac_int_status);
4616         if (val64 & MAC_INT_STATUS_TMAC_INT) {
4617                 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4618                                           &bar0->mac_tmac_err_reg,
4619                                           &sw_stat->mac_tmac_err_cnt))
4620                         goto reset;
4621                 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4622                                       TMAC_DESC_ECC_SG_ERR |
4623                                       TMAC_DESC_ECC_DB_ERR,
4624                                       &bar0->mac_tmac_err_reg,
4625                                       &sw_stat->mac_tmac_err_cnt);
4626         }
4627
4628         val64 = readq(&bar0->xgxs_int_status);
4629         if (val64 & XGXS_INT_STATUS_TXGXS) {
4630                 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4631                                           &bar0->xgxs_txgxs_err_reg,
4632                                           &sw_stat->xgxs_txgxs_err_cnt))
4633                         goto reset;
4634                 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4635                                       &bar0->xgxs_txgxs_err_reg,
4636                                       &sw_stat->xgxs_txgxs_err_cnt);
4637         }
4638
4639         val64 = readq(&bar0->rxdma_int_status);
4640         if (val64 & RXDMA_INT_RC_INT_M) {
4641                 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4642                                           RC_FTC_ECC_DB_ERR |
4643                                           RC_PRCn_SM_ERR_ALARM |
4644                                           RC_FTC_SM_ERR_ALARM,
4645                                           &bar0->rc_err_reg,
4646                                           &sw_stat->rc_err_cnt))
4647                         goto reset;
4648                 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4649                                       RC_FTC_ECC_SG_ERR |
4650                                       RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4651                                       &sw_stat->rc_err_cnt);
4652                 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4653                                           PRC_PCI_AB_WR_Rn |
4654                                           PRC_PCI_AB_F_WR_Rn,
4655                                           &bar0->prc_pcix_err_reg,
4656                                           &sw_stat->prc_pcix_err_cnt))
4657                         goto reset;
4658                 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4659                                       PRC_PCI_DP_WR_Rn |
4660                                       PRC_PCI_DP_F_WR_Rn,
4661                                       &bar0->prc_pcix_err_reg,
4662                                       &sw_stat->prc_pcix_err_cnt);
4663         }
4664
4665         if (val64 & RXDMA_INT_RPA_INT_M) {
4666                 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4667                                           &bar0->rpa_err_reg,
4668                                           &sw_stat->rpa_err_cnt))
4669                         goto reset;
4670                 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4671                                       &bar0->rpa_err_reg,
4672                                       &sw_stat->rpa_err_cnt);
4673         }
4674
4675         if (val64 & RXDMA_INT_RDA_INT_M) {
4676                 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4677                                           RDA_FRM_ECC_DB_N_AERR |
4678                                           RDA_SM1_ERR_ALARM |
4679                                           RDA_SM0_ERR_ALARM |
4680                                           RDA_RXD_ECC_DB_SERR,
4681                                           &bar0->rda_err_reg,
4682                                           &sw_stat->rda_err_cnt))
4683                         goto reset;
4684                 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4685                                       RDA_FRM_ECC_SG_ERR |
4686                                       RDA_MISC_ERR |
4687                                       RDA_PCIX_ERR,
4688                                       &bar0->rda_err_reg,
4689                                       &sw_stat->rda_err_cnt);
4690         }
4691
4692         if (val64 & RXDMA_INT_RTI_INT_M) {
4693                 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4694                                           &bar0->rti_err_reg,
4695                                           &sw_stat->rti_err_cnt))
4696                         goto reset;
4697                 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4698                                       &bar0->rti_err_reg,
4699                                       &sw_stat->rti_err_cnt);
4700         }
4701
4702         val64 = readq(&bar0->mac_int_status);
4703         if (val64 & MAC_INT_STATUS_RMAC_INT) {
4704                 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4705                                           &bar0->mac_rmac_err_reg,
4706                                           &sw_stat->mac_rmac_err_cnt))
4707                         goto reset;
4708                 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4709                                       RMAC_SINGLE_ECC_ERR |
4710                                       RMAC_DOUBLE_ECC_ERR,
4711                                       &bar0->mac_rmac_err_reg,
4712                                       &sw_stat->mac_rmac_err_cnt);
4713         }
4714
4715         val64 = readq(&bar0->xgxs_int_status);
4716         if (val64 & XGXS_INT_STATUS_RXGXS) {
4717                 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4718                                           &bar0->xgxs_rxgxs_err_reg,
4719                                           &sw_stat->xgxs_rxgxs_err_cnt))
4720                         goto reset;
4721         }
4722
4723         val64 = readq(&bar0->mc_int_status);
4724         if (val64 & MC_INT_STATUS_MC_INT) {
4725                 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4726                                           &bar0->mc_err_reg,
4727                                           &sw_stat->mc_err_cnt))
4728                         goto reset;
4729
4730                 /* Handling Ecc errors */
4731                 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4732                         writeq(val64, &bar0->mc_err_reg);
4733                         if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4734                                 sw_stat->double_ecc_errs++;
4735                                 if (sp->device_type != XFRAME_II_DEVICE) {
4736                                         /*
4737                                          * Reset XframeI only if critical error
4738                                          */
4739                                         if (val64 &
4740                                             (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4741                                              MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4742                                                 goto reset;
4743                                 }
4744                         } else
4745                                 sw_stat->single_ecc_errs++;
4746                 }
4747         }
4748         return;
4749
4750 reset:
4751         s2io_stop_all_tx_queue(sp);
4752         schedule_work(&sp->rst_timer_task);
4753         sw_stat->soft_reset_cnt++;
4754 }
4755
4756 /**
4757  *  s2io_isr - ISR handler of the device .
4758  *  @irq: the irq of the device.
4759  *  @dev_id: a void pointer to the dev structure of the NIC.
4760  *  Description:  This function is the ISR handler of the device. It
4761  *  identifies the reason for the interrupt and calls the relevant
4762  *  service routines. As a contongency measure, this ISR allocates the
4763  *  recv buffers, if their numbers are below the panic value which is
4764  *  presently set to 25% of the original number of rcv buffers allocated.
4765  *  Return value:
4766  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
4767  *   IRQ_NONE: will be returned if interrupt is not from our device
4768  */
4769 static irqreturn_t s2io_isr(int irq, void *dev_id)
4770 {
4771         struct net_device *dev = (struct net_device *)dev_id;
4772         struct s2io_nic *sp = netdev_priv(dev);
4773         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4774         int i;
4775         u64 reason = 0;
4776         struct mac_info *mac_control;
4777         struct config_param *config;
4778
4779         /* Pretend we handled any irq's from a disconnected card */
4780         if (pci_channel_offline(sp->pdev))
4781                 return IRQ_NONE;
4782
4783         if (!is_s2io_card_up(sp))
4784                 return IRQ_NONE;
4785
4786         config = &sp->config;
4787         mac_control = &sp->mac_control;
4788
4789         /*
4790          * Identify the cause for interrupt and call the appropriate
4791          * interrupt handler. Causes for the interrupt could be;
4792          * 1. Rx of packet.
4793          * 2. Tx complete.
4794          * 3. Link down.
4795          */
4796         reason = readq(&bar0->general_int_status);
4797
4798         if (unlikely(reason == S2IO_MINUS_ONE))
4799                 return IRQ_HANDLED;     /* Nothing much can be done. Get out */
4800
4801         if (reason &
4802             (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
4803                 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4804
4805                 if (config->napi) {
4806                         if (reason & GEN_INTR_RXTRAFFIC) {
4807                                 napi_schedule(&sp->napi);
4808                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4809                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4810                                 readl(&bar0->rx_traffic_int);
4811                         }
4812                 } else {
4813                         /*
4814                          * rx_traffic_int reg is an R1 register, writing all 1's
4815                          * will ensure that the actual interrupt causing bit
4816                          * get's cleared and hence a read can be avoided.
4817                          */
4818                         if (reason & GEN_INTR_RXTRAFFIC)
4819                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4820
4821                         for (i = 0; i < config->rx_ring_num; i++) {
4822                                 struct ring_info *ring = &mac_control->rings[i];
4823
4824                                 rx_intr_handler(ring, 0);
4825                         }
4826                 }
4827
4828                 /*
4829                  * tx_traffic_int reg is an R1 register, writing all 1's
4830                  * will ensure that the actual interrupt causing bit get's
4831                  * cleared and hence a read can be avoided.
4832                  */
4833                 if (reason & GEN_INTR_TXTRAFFIC)
4834                         writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4835
4836                 for (i = 0; i < config->tx_fifo_num; i++)
4837                         tx_intr_handler(&mac_control->fifos[i]);
4838
4839                 if (reason & GEN_INTR_TXPIC)
4840                         s2io_txpic_intr_handle(sp);
4841
4842                 /*
4843                  * Reallocate the buffers from the interrupt handler itself.
4844                  */
4845                 if (!config->napi) {
4846                         for (i = 0; i < config->rx_ring_num; i++) {
4847                                 struct ring_info *ring = &mac_control->rings[i];
4848
4849                                 s2io_chk_rx_buffers(sp, ring);
4850                         }
4851                 }
4852                 writeq(sp->general_int_mask, &bar0->general_int_mask);
4853                 readl(&bar0->general_int_status);
4854
4855                 return IRQ_HANDLED;
4856
4857         } else if (!reason) {
4858                 /* The interrupt was not raised by us */
4859                 return IRQ_NONE;
4860         }
4861
4862         return IRQ_HANDLED;
4863 }
4864
4865 /**
4866  * s2io_updt_stats -
4867  */
4868 static void s2io_updt_stats(struct s2io_nic *sp)
4869 {
4870         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4871         u64 val64;
4872         int cnt = 0;
4873
4874         if (is_s2io_card_up(sp)) {
4875                 /* Apprx 30us on a 133 MHz bus */
4876                 val64 = SET_UPDT_CLICKS(10) |
4877                         STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4878                 writeq(val64, &bar0->stat_cfg);
4879                 do {
4880                         udelay(100);
4881                         val64 = readq(&bar0->stat_cfg);
4882                         if (!(val64 & s2BIT(0)))
4883                                 break;
4884                         cnt++;
4885                         if (cnt == 5)
4886                                 break; /* Updt failed */
4887                 } while (1);
4888         }
4889 }
4890
4891 /**
4892  *  s2io_get_stats - Updates the device statistics structure.
4893  *  @dev : pointer to the device structure.
4894  *  Description:
4895  *  This function updates the device statistics structure in the s2io_nic
4896  *  structure and returns a pointer to the same.
4897  *  Return value:
4898  *  pointer to the updated net_device_stats structure.
4899  */
4900 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4901 {
4902         struct s2io_nic *sp = netdev_priv(dev);
4903         struct mac_info *mac_control = &sp->mac_control;
4904         struct stat_block *stats = mac_control->stats_info;
4905         u64 delta;
4906
4907         /* Configure Stats for immediate updt */
4908         s2io_updt_stats(sp);
4909
4910         /* A device reset will cause the on-adapter statistics to be zero'ed.
4911          * This can be done while running by changing the MTU.  To prevent the
4912          * system from having the stats zero'ed, the driver keeps a copy of the
4913          * last update to the system (which is also zero'ed on reset).  This
4914          * enables the driver to accurately know the delta between the last
4915          * update and the current update.
4916          */
4917         delta = ((u64) le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
4918                 le32_to_cpu(stats->rmac_vld_frms)) - sp->stats.rx_packets;
4919         sp->stats.rx_packets += delta;
4920         dev->stats.rx_packets += delta;
4921
4922         delta = ((u64) le32_to_cpu(stats->tmac_frms_oflow) << 32 |
4923                 le32_to_cpu(stats->tmac_frms)) - sp->stats.tx_packets;
4924         sp->stats.tx_packets += delta;
4925         dev->stats.tx_packets += delta;
4926
4927         delta = ((u64) le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
4928                 le32_to_cpu(stats->rmac_data_octets)) - sp->stats.rx_bytes;
4929         sp->stats.rx_bytes += delta;
4930         dev->stats.rx_bytes += delta;
4931
4932         delta = ((u64) le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
4933                 le32_to_cpu(stats->tmac_data_octets)) - sp->stats.tx_bytes;
4934         sp->stats.tx_bytes += delta;
4935         dev->stats.tx_bytes += delta;
4936
4937         delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_errors;
4938         sp->stats.rx_errors += delta;
4939         dev->stats.rx_errors += delta;
4940
4941         delta = ((u64) le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
4942                 le32_to_cpu(stats->tmac_any_err_frms)) - sp->stats.tx_errors;
4943         sp->stats.tx_errors += delta;
4944         dev->stats.tx_errors += delta;
4945
4946         delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_dropped;
4947         sp->stats.rx_dropped += delta;
4948         dev->stats.rx_dropped += delta;
4949
4950         delta = le64_to_cpu(stats->tmac_drop_frms) - sp->stats.tx_dropped;
4951         sp->stats.tx_dropped += delta;
4952         dev->stats.tx_dropped += delta;
4953
4954         /* The adapter MAC interprets pause frames as multicast packets, but
4955          * does not pass them up.  This erroneously increases the multicast
4956          * packet count and needs to be deducted when the multicast frame count
4957          * is queried.
4958          */
4959         delta = (u64) le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
4960                 le32_to_cpu(stats->rmac_vld_mcst_frms);
4961         delta -= le64_to_cpu(stats->rmac_pause_ctrl_frms);
4962         delta -= sp->stats.multicast;
4963         sp->stats.multicast += delta;
4964         dev->stats.multicast += delta;
4965
4966         delta = ((u64) le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
4967                 le32_to_cpu(stats->rmac_usized_frms)) +
4968                 le64_to_cpu(stats->rmac_long_frms) - sp->stats.rx_length_errors;
4969         sp->stats.rx_length_errors += delta;
4970         dev->stats.rx_length_errors += delta;
4971
4972         delta = le64_to_cpu(stats->rmac_fcs_err_frms) - sp->stats.rx_crc_errors;
4973         sp->stats.rx_crc_errors += delta;
4974         dev->stats.rx_crc_errors += delta;
4975
4976         return &dev->stats;
4977 }
4978
4979 /**
4980  *  s2io_set_multicast - entry point for multicast address enable/disable.
4981  *  @dev : pointer to the device structure
4982  *  Description:
4983  *  This function is a driver entry point which gets called by the kernel
4984  *  whenever multicast addresses must be enabled/disabled. This also gets
4985  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
4986  *  determine, if multicast address must be enabled or if promiscuous mode
4987  *  is to be disabled etc.
4988  *  Return value:
4989  *  void.
4990  */
4991
4992 static void s2io_set_multicast(struct net_device *dev)
4993 {
4994         int i, j, prev_cnt;
4995         struct netdev_hw_addr *ha;
4996         struct s2io_nic *sp = netdev_priv(dev);
4997         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4998         u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4999                 0xfeffffffffffULL;
5000         u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
5001         void __iomem *add;
5002         struct config_param *config = &sp->config;
5003
5004         if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
5005                 /*  Enable all Multicast addresses */
5006                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
5007                        &bar0->rmac_addr_data0_mem);
5008                 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
5009                        &bar0->rmac_addr_data1_mem);
5010                 val64 = RMAC_ADDR_CMD_MEM_WE |
5011                         RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5012                         RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
5013                 writeq(val64, &bar0->rmac_addr_cmd_mem);
5014                 /* Wait till command completes */
5015                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5016                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5017                                       S2IO_BIT_RESET);
5018
5019                 sp->m_cast_flg = 1;
5020                 sp->all_multi_pos = config->max_mc_addr - 1;
5021         } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
5022                 /*  Disable all Multicast addresses */
5023                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5024                        &bar0->rmac_addr_data0_mem);
5025                 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
5026                        &bar0->rmac_addr_data1_mem);
5027                 val64 = RMAC_ADDR_CMD_MEM_WE |
5028                         RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5029                         RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
5030                 writeq(val64, &bar0->rmac_addr_cmd_mem);
5031                 /* Wait till command completes */
5032                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5033                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5034                                       S2IO_BIT_RESET);
5035
5036                 sp->m_cast_flg = 0;
5037                 sp->all_multi_pos = 0;
5038         }
5039
5040         if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5041                 /*  Put the NIC into promiscuous mode */
5042                 add = &bar0->mac_cfg;
5043                 val64 = readq(&bar0->mac_cfg);
5044                 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5045
5046                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5047                 writel((u32)val64, add);
5048                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5049                 writel((u32) (val64 >> 32), (add + 4));
5050
5051                 if (vlan_tag_strip != 1) {
5052                         val64 = readq(&bar0->rx_pa_cfg);
5053                         val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5054                         writeq(val64, &bar0->rx_pa_cfg);
5055                         sp->vlan_strip_flag = 0;
5056                 }
5057
5058                 val64 = readq(&bar0->mac_cfg);
5059                 sp->promisc_flg = 1;
5060                 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
5061                           dev->name);
5062         } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5063                 /*  Remove the NIC from promiscuous mode */
5064                 add = &bar0->mac_cfg;
5065                 val64 = readq(&bar0->mac_cfg);
5066                 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5067
5068                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5069                 writel((u32)val64, add);
5070                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5071                 writel((u32) (val64 >> 32), (add + 4));
5072
5073                 if (vlan_tag_strip != 0) {
5074                         val64 = readq(&bar0->rx_pa_cfg);
5075                         val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5076                         writeq(val64, &bar0->rx_pa_cfg);
5077                         sp->vlan_strip_flag = 1;
5078                 }
5079
5080                 val64 = readq(&bar0->mac_cfg);
5081                 sp->promisc_flg = 0;
5082                 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
5083         }
5084
5085         /*  Update individual M_CAST address list */
5086         if ((!sp->m_cast_flg) && netdev_mc_count(dev)) {
5087                 if (netdev_mc_count(dev) >
5088                     (config->max_mc_addr - config->max_mac_addr)) {
5089                         DBG_PRINT(ERR_DBG,
5090                                   "%s: No more Rx filters can be added - "
5091                                   "please enable ALL_MULTI instead\n",
5092                                   dev->name);
5093                         return;
5094                 }
5095
5096                 prev_cnt = sp->mc_addr_count;
5097                 sp->mc_addr_count = netdev_mc_count(dev);
5098
5099                 /* Clear out the previous list of Mc in the H/W. */
5100                 for (i = 0; i < prev_cnt; i++) {
5101                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5102                                &bar0->rmac_addr_data0_mem);
5103                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5104                                &bar0->rmac_addr_data1_mem);
5105                         val64 = RMAC_ADDR_CMD_MEM_WE |
5106                                 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5107                                 RMAC_ADDR_CMD_MEM_OFFSET
5108                                 (config->mc_start_offset + i);
5109                         writeq(val64, &bar0->rmac_addr_cmd_mem);
5110
5111                         /* Wait for command completes */
5112                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5113                                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5114                                                   S2IO_BIT_RESET)) {
5115                                 DBG_PRINT(ERR_DBG,
5116                                           "%s: Adding Multicasts failed\n",
5117                                           dev->name);
5118                                 return;
5119                         }
5120                 }
5121
5122                 /* Create the new Rx filter list and update the same in H/W. */
5123                 i = 0;
5124                 netdev_for_each_mc_addr(ha, dev) {
5125                         mac_addr = 0;
5126                         for (j = 0; j < ETH_ALEN; j++) {
5127                                 mac_addr |= ha->addr[j];
5128                                 mac_addr <<= 8;
5129                         }
5130                         mac_addr >>= 8;
5131                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5132                                &bar0->rmac_addr_data0_mem);
5133                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5134                                &bar0->rmac_addr_data1_mem);
5135                         val64 = RMAC_ADDR_CMD_MEM_WE |
5136                                 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5137                                 RMAC_ADDR_CMD_MEM_OFFSET
5138                                 (i + config->mc_start_offset);
5139                         writeq(val64, &bar0->rmac_addr_cmd_mem);
5140
5141                         /* Wait for command completes */
5142                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5143                                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5144                                                   S2IO_BIT_RESET)) {
5145                                 DBG_PRINT(ERR_DBG,
5146                                           "%s: Adding Multicasts failed\n",
5147                                           dev->name);
5148                                 return;
5149                         }
5150                         i++;
5151                 }
5152         }
5153 }
5154
5155 /* read from CAM unicast & multicast addresses and store it in
5156  * def_mac_addr structure
5157  */
5158 static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5159 {
5160         int offset;
5161         u64 mac_addr = 0x0;
5162         struct config_param *config = &sp->config;
5163
5164         /* store unicast & multicast mac addresses */
5165         for (offset = 0; offset < config->max_mc_addr; offset++) {
5166                 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5167                 /* if read fails disable the entry */
5168                 if (mac_addr == FAILURE)
5169                         mac_addr = S2IO_DISABLE_MAC_ENTRY;
5170                 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5171         }
5172 }
5173
5174 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5175 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5176 {
5177         int offset;
5178         struct config_param *config = &sp->config;
5179         /* restore unicast mac address */
5180         for (offset = 0; offset < config->max_mac_addr; offset++)
5181                 do_s2io_prog_unicast(sp->dev,
5182                                      sp->def_mac_addr[offset].mac_addr);
5183
5184         /* restore multicast mac address */
5185         for (offset = config->mc_start_offset;
5186              offset < config->max_mc_addr; offset++)
5187                 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5188 }
5189
5190 /* add a multicast MAC address to CAM */
5191 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5192 {
5193         int i;
5194         u64 mac_addr = 0;
5195         struct config_param *config = &sp->config;
5196
5197         for (i = 0; i < ETH_ALEN; i++) {
5198                 mac_addr <<= 8;
5199                 mac_addr |= addr[i];
5200         }
5201         if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5202                 return SUCCESS;
5203
5204         /* check if the multicast mac already preset in CAM */
5205         for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5206                 u64 tmp64;
5207                 tmp64 = do_s2io_read_unicast_mc(sp, i);
5208                 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5209                         break;
5210
5211                 if (tmp64 == mac_addr)
5212                         return SUCCESS;
5213         }
5214         if (i == config->max_mc_addr) {
5215                 DBG_PRINT(ERR_DBG,
5216                           "CAM full no space left for multicast MAC\n");
5217                 return FAILURE;
5218         }
5219         /* Update the internal structure with this new mac address */
5220         do_s2io_copy_mac_addr(sp, i, mac_addr);
5221
5222         return do_s2io_add_mac(sp, mac_addr, i);
5223 }
5224
5225 /* add MAC address to CAM */
5226 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5227 {
5228         u64 val64;
5229         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5230
5231         writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5232                &bar0->rmac_addr_data0_mem);
5233
5234         val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5235                 RMAC_ADDR_CMD_MEM_OFFSET(off);
5236         writeq(val64, &bar0->rmac_addr_cmd_mem);
5237
5238         /* Wait till command completes */
5239         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5240                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5241                                   S2IO_BIT_RESET)) {
5242                 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5243                 return FAILURE;
5244         }
5245         return SUCCESS;
5246 }
5247 /* deletes a specified unicast/multicast mac entry from CAM */
5248 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5249 {
5250         int offset;
5251         u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5252         struct config_param *config = &sp->config;
5253
5254         for (offset = 1;
5255              offset < config->max_mc_addr; offset++) {
5256                 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5257                 if (tmp64 == addr) {
5258                         /* disable the entry by writing  0xffffffffffffULL */
5259                         if (do_s2io_add_mac(sp, dis_addr, offset) ==  FAILURE)
5260                                 return FAILURE;
5261                         /* store the new mac list from CAM */
5262                         do_s2io_store_unicast_mc(sp);
5263                         return SUCCESS;
5264                 }
5265         }
5266         DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5267                   (unsigned long long)addr);
5268         return FAILURE;
5269 }
5270
5271 /* read mac entries from CAM */
5272 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5273 {
5274         u64 tmp64 = 0xffffffffffff0000ULL, val64;
5275         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5276
5277         /* read mac addr */
5278         val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5279                 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5280         writeq(val64, &bar0->rmac_addr_cmd_mem);
5281
5282         /* Wait till command completes */
5283         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5284                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5285                                   S2IO_BIT_RESET)) {
5286                 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5287                 return FAILURE;
5288         }
5289         tmp64 = readq(&bar0->rmac_addr_data0_mem);
5290
5291         return tmp64 >> 16;
5292 }
5293
5294 /**
5295  * s2io_set_mac_addr driver entry point
5296  */
5297
5298 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5299 {
5300         struct sockaddr *addr = p;
5301
5302         if (!is_valid_ether_addr(addr->sa_data))
5303                 return -EINVAL;
5304
5305         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5306
5307         /* store the MAC address in CAM */
5308         return do_s2io_prog_unicast(dev, dev->dev_addr);
5309 }
5310 /**
5311  *  do_s2io_prog_unicast - Programs the Xframe mac address
5312  *  @dev : pointer to the device structure.
5313  *  @addr: a uchar pointer to the new mac address which is to be set.
5314  *  Description : This procedure will program the Xframe to receive
5315  *  frames with new Mac Address
5316  *  Return value: SUCCESS on success and an appropriate (-)ve integer
5317  *  as defined in errno.h file on failure.
5318  */
5319
5320 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5321 {
5322         struct s2io_nic *sp = netdev_priv(dev);
5323         register u64 mac_addr = 0, perm_addr = 0;
5324         int i;
5325         u64 tmp64;
5326         struct config_param *config = &sp->config;
5327
5328         /*
5329          * Set the new MAC address as the new unicast filter and reflect this
5330          * change on the device address registered with the OS. It will be
5331          * at offset 0.
5332          */
5333         for (i = 0; i < ETH_ALEN; i++) {
5334                 mac_addr <<= 8;
5335                 mac_addr |= addr[i];
5336                 perm_addr <<= 8;
5337                 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5338         }
5339
5340         /* check if the dev_addr is different than perm_addr */
5341         if (mac_addr == perm_addr)
5342                 return SUCCESS;
5343
5344         /* check if the mac already preset in CAM */
5345         for (i = 1; i < config->max_mac_addr; i++) {
5346                 tmp64 = do_s2io_read_unicast_mc(sp, i);
5347                 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5348                         break;
5349
5350                 if (tmp64 == mac_addr) {
5351                         DBG_PRINT(INFO_DBG,
5352                                   "MAC addr:0x%llx already present in CAM\n",
5353                                   (unsigned long long)mac_addr);
5354                         return SUCCESS;
5355                 }
5356         }
5357         if (i == config->max_mac_addr) {
5358                 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5359                 return FAILURE;
5360         }
5361         /* Update the internal structure with this new mac address */
5362         do_s2io_copy_mac_addr(sp, i, mac_addr);
5363
5364         return do_s2io_add_mac(sp, mac_addr, i);
5365 }
5366
5367 /**
5368  * s2io_ethtool_sset - Sets different link parameters.
5369  * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
5370  * @info: pointer to the structure with parameters given by ethtool to set
5371  * link information.
5372  * Description:
5373  * The function sets different link parameters provided by the user onto
5374  * the NIC.
5375  * Return value:
5376  * 0 on success.
5377  */
5378
5379 static int s2io_ethtool_sset(struct net_device *dev,
5380                              struct ethtool_cmd *info)
5381 {
5382         struct s2io_nic *sp = netdev_priv(dev);
5383         if ((info->autoneg == AUTONEG_ENABLE) ||
5384             (ethtool_cmd_speed(info) != SPEED_10000) ||
5385             (info->duplex != DUPLEX_FULL))
5386                 return -EINVAL;
5387         else {
5388                 s2io_close(sp->dev);
5389                 s2io_open(sp->dev);
5390         }
5391
5392         return 0;
5393 }
5394
5395 /**
5396  * s2io_ethtol_gset - Return link specific information.
5397  * @sp : private member of the device structure, pointer to the
5398  *      s2io_nic structure.
5399  * @info : pointer to the structure with parameters given by ethtool
5400  * to return link information.
5401  * Description:
5402  * Returns link specific information like speed, duplex etc.. to ethtool.
5403  * Return value :
5404  * return 0 on success.
5405  */
5406
5407 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5408 {
5409         struct s2io_nic *sp = netdev_priv(dev);
5410         info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5411         info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5412         info->port = PORT_FIBRE;
5413
5414         /* info->transceiver */
5415         info->transceiver = XCVR_EXTERNAL;
5416
5417         if (netif_carrier_ok(sp->dev)) {
5418                 ethtool_cmd_speed_set(info, SPEED_10000);
5419                 info->duplex = DUPLEX_FULL;
5420         } else {
5421                 ethtool_cmd_speed_set(info, -1);
5422                 info->duplex = -1;
5423         }
5424
5425         info->autoneg = AUTONEG_DISABLE;
5426         return 0;
5427 }
5428
5429 /**
5430  * s2io_ethtool_gdrvinfo - Returns driver specific information.
5431  * @sp : private member of the device structure, which is a pointer to the
5432  * s2io_nic structure.
5433  * @info : pointer to the structure with parameters given by ethtool to
5434  * return driver information.
5435  * Description:
5436  * Returns driver specefic information like name, version etc.. to ethtool.
5437  * Return value:
5438  *  void
5439  */
5440
5441 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5442                                   struct ethtool_drvinfo *info)
5443 {
5444         struct s2io_nic *sp = netdev_priv(dev);
5445
5446         strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5447         strncpy(info->version, s2io_driver_version, sizeof(info->version));
5448         strncpy(info->fw_version, "", sizeof(info->fw_version));
5449         strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5450         info->regdump_len = XENA_REG_SPACE;
5451         info->eedump_len = XENA_EEPROM_SPACE;
5452 }
5453
5454 /**
5455  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5456  *  @sp: private member of the device structure, which is a pointer to the
5457  *  s2io_nic structure.
5458  *  @regs : pointer to the structure with parameters given by ethtool for
5459  *  dumping the registers.
5460  *  @reg_space: The input argumnet into which all the registers are dumped.
5461  *  Description:
5462  *  Dumps the entire register space of xFrame NIC into the user given
5463  *  buffer area.
5464  * Return value :
5465  * void .
5466  */
5467
5468 static void s2io_ethtool_gregs(struct net_device *dev,
5469                                struct ethtool_regs *regs, void *space)
5470 {
5471         int i;
5472         u64 reg;
5473         u8 *reg_space = (u8 *)space;
5474         struct s2io_nic *sp = netdev_priv(dev);
5475
5476         regs->len = XENA_REG_SPACE;
5477         regs->version = sp->pdev->subsystem_device;
5478
5479         for (i = 0; i < regs->len; i += 8) {
5480                 reg = readq(sp->bar0 + i);
5481                 memcpy((reg_space + i), &reg, 8);
5482         }
5483 }
5484
5485 /*
5486  *  s2io_set_led - control NIC led
5487  */
5488 static void s2io_set_led(struct s2io_nic *sp, bool on)
5489 {
5490         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5491         u16 subid = sp->pdev->subsystem_device;
5492         u64 val64;
5493
5494         if ((sp->device_type == XFRAME_II_DEVICE) ||
5495             ((subid & 0xFF) >= 0x07)) {
5496                 val64 = readq(&bar0->gpio_control);
5497                 if (on)
5498                         val64 |= GPIO_CTRL_GPIO_0;
5499                 else
5500                         val64 &= ~GPIO_CTRL_GPIO_0;
5501
5502                 writeq(val64, &bar0->gpio_control);
5503       &nb