Create platform_device.h to contain all the platform device details.
[linux-2.6.git] / drivers / net / s2io.c
1 /************************************************************************
2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3  * Copyright(c) 2002-2005 Neterion Inc.
4
5  * This software may be used and distributed according to the terms of
6  * the GNU General Public License (GPL), incorporated herein by reference.
7  * Drivers based on or derived from this code fall under the GPL and must
8  * retain the authorship, copyright and license notice.  This file is not
9  * a complete program and may only be used when the entire operating
10  * system is licensed under the GPL.
11  * See the file COPYING in this distribution for more information.
12  *
13  * Credits:
14  * Jeff Garzik          : For pointing out the improper error condition
15  *                        check in the s2io_xmit routine and also some
16  *                        issues in the Tx watch dog function. Also for
17  *                        patiently answering all those innumerable
18  *                        questions regaring the 2.6 porting issues.
19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
20  *                        macros available only in 2.6 Kernel.
21  * Francois Romieu      : For pointing out all code part that were
22  *                        deprecated and also styling related comments.
23  * Grant Grundler       : For helping me get rid of some Architecture
24  *                        dependent code.
25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
26  *
27  * The module loadable parameters that are supported by the driver and a brief
28  * explaination of all the variables.
29  * rx_ring_num : This can be used to program the number of receive rings used
30  * in the driver.
31  * rx_ring_sz: This defines the number of descriptors each ring can have. This
32  * is also an array of size 8.
33  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
34  * tx_fifo_len: This too is an array of 8. Each element defines the number of
35  * Tx descriptors that can be associated with each corresponding FIFO.
36  ************************************************************************/
37
38 #include <linux/config.h>
39 #include <linux/module.h>
40 #include <linux/types.h>
41 #include <linux/errno.h>
42 #include <linux/ioport.h>
43 #include <linux/pci.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/kernel.h>
46 #include <linux/netdevice.h>
47 #include <linux/etherdevice.h>
48 #include <linux/skbuff.h>
49 #include <linux/init.h>
50 #include <linux/delay.h>
51 #include <linux/stddef.h>
52 #include <linux/ioctl.h>
53 #include <linux/timex.h>
54 #include <linux/sched.h>
55 #include <linux/ethtool.h>
56 #include <linux/version.h>
57 #include <linux/workqueue.h>
58 #include <linux/if_vlan.h>
59
60 #include <asm/system.h>
61 #include <asm/uaccess.h>
62 #include <asm/io.h>
63
64 /* local include */
65 #include "s2io.h"
66 #include "s2io-regs.h"
67
68 #define DRV_VERSION "Version 2.0.9.1"
69
70 /* S2io Driver name & version. */
71 static char s2io_driver_name[] = "Neterion";
72 static char s2io_driver_version[] = DRV_VERSION;
73
74 static inline int RXD_IS_UP2DT(RxD_t *rxdp)
75 {
76         int ret;
77
78         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
79                 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
80
81         return ret;
82 }
83
84 /*
85  * Cards with following subsystem_id have a link state indication
86  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
87  * macro below identifies these cards given the subsystem_id.
88  */
89 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
90         (dev_type == XFRAME_I_DEVICE) ?                 \
91                 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
92                  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
93
94 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
95                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
96 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
97 #define PANIC   1
98 #define LOW     2
99 static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
100 {
101         int level = 0;
102         mac_info_t *mac_control;
103
104         mac_control = &sp->mac_control;
105         if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16) {
106                 level = LOW;
107                 if (rxb_size <= MAX_RXDS_PER_BLOCK) {
108                         level = PANIC;
109                 }
110         }
111
112         return level;
113 }
114
115 /* Ethtool related variables and Macros. */
116 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
117         "Register test\t(offline)",
118         "Eeprom test\t(offline)",
119         "Link test\t(online)",
120         "RLDRAM test\t(offline)",
121         "BIST Test\t(offline)"
122 };
123
124 static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
125         {"tmac_frms"},
126         {"tmac_data_octets"},
127         {"tmac_drop_frms"},
128         {"tmac_mcst_frms"},
129         {"tmac_bcst_frms"},
130         {"tmac_pause_ctrl_frms"},
131         {"tmac_any_err_frms"},
132         {"tmac_vld_ip_octets"},
133         {"tmac_vld_ip"},
134         {"tmac_drop_ip"},
135         {"tmac_icmp"},
136         {"tmac_rst_tcp"},
137         {"tmac_tcp"},
138         {"tmac_udp"},
139         {"rmac_vld_frms"},
140         {"rmac_data_octets"},
141         {"rmac_fcs_err_frms"},
142         {"rmac_drop_frms"},
143         {"rmac_vld_mcst_frms"},
144         {"rmac_vld_bcst_frms"},
145         {"rmac_in_rng_len_err_frms"},
146         {"rmac_long_frms"},
147         {"rmac_pause_ctrl_frms"},
148         {"rmac_discarded_frms"},
149         {"rmac_usized_frms"},
150         {"rmac_osized_frms"},
151         {"rmac_frag_frms"},
152         {"rmac_jabber_frms"},
153         {"rmac_ip"},
154         {"rmac_ip_octets"},
155         {"rmac_hdr_err_ip"},
156         {"rmac_drop_ip"},
157         {"rmac_icmp"},
158         {"rmac_tcp"},
159         {"rmac_udp"},
160         {"rmac_err_drp_udp"},
161         {"rmac_pause_cnt"},
162         {"rmac_accepted_ip"},
163         {"rmac_err_tcp"},
164         {"\n DRIVER STATISTICS"},
165         {"single_bit_ecc_errs"},
166         {"double_bit_ecc_errs"},
167 };
168
169 #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
170 #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
171
172 #define S2IO_TEST_LEN   sizeof(s2io_gstrings) / ETH_GSTRING_LEN
173 #define S2IO_STRINGS_LEN        S2IO_TEST_LEN * ETH_GSTRING_LEN
174
175 #define S2IO_TIMER_CONF(timer, handle, arg, exp)                \
176                         init_timer(&timer);                     \
177                         timer.function = handle;                \
178                         timer.data = (unsigned long) arg;       \
179                         mod_timer(&timer, (jiffies + exp))      \
180
181 /* Add the vlan */
182 static void s2io_vlan_rx_register(struct net_device *dev,
183                                         struct vlan_group *grp)
184 {
185         nic_t *nic = dev->priv;
186         unsigned long flags;
187
188         spin_lock_irqsave(&nic->tx_lock, flags);
189         nic->vlgrp = grp;
190         spin_unlock_irqrestore(&nic->tx_lock, flags);
191 }
192
193 /* Unregister the vlan */
194 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
195 {
196         nic_t *nic = dev->priv;
197         unsigned long flags;
198
199         spin_lock_irqsave(&nic->tx_lock, flags);
200         if (nic->vlgrp)
201                 nic->vlgrp->vlan_devices[vid] = NULL;
202         spin_unlock_irqrestore(&nic->tx_lock, flags);
203 }
204
205 /*
206  * Constants to be programmed into the Xena's registers, to configure
207  * the XAUI.
208  */
209
210 #define SWITCH_SIGN     0xA5A5A5A5A5A5A5A5ULL
211 #define END_SIGN        0x0
212
213 static u64 herc_act_dtx_cfg[] = {
214         /* Set address */
215         0x8000051536750000ULL, 0x80000515367500E0ULL,
216         /* Write data */
217         0x8000051536750004ULL, 0x80000515367500E4ULL,
218         /* Set address */
219         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
220         /* Write data */
221         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
222         /* Set address */
223         0x801205150D440000ULL, 0x801205150D4400E0ULL,
224         /* Write data */
225         0x801205150D440004ULL, 0x801205150D4400E4ULL,
226         /* Set address */
227         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
228         /* Write data */
229         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
230         /* Done */
231         END_SIGN
232 };
233
234 static u64 xena_mdio_cfg[] = {
235         /* Reset PMA PLL */
236         0xC001010000000000ULL, 0xC0010100000000E0ULL,
237         0xC0010100008000E4ULL,
238         /* Remove Reset from PMA PLL */
239         0xC001010000000000ULL, 0xC0010100000000E0ULL,
240         0xC0010100000000E4ULL,
241         END_SIGN
242 };
243
244 static u64 xena_dtx_cfg[] = {
245         0x8000051500000000ULL, 0x80000515000000E0ULL,
246         0x80000515D93500E4ULL, 0x8001051500000000ULL,
247         0x80010515000000E0ULL, 0x80010515001E00E4ULL,
248         0x8002051500000000ULL, 0x80020515000000E0ULL,
249         0x80020515F21000E4ULL,
250         /* Set PADLOOPBACKN */
251         0x8002051500000000ULL, 0x80020515000000E0ULL,
252         0x80020515B20000E4ULL, 0x8003051500000000ULL,
253         0x80030515000000E0ULL, 0x80030515B20000E4ULL,
254         0x8004051500000000ULL, 0x80040515000000E0ULL,
255         0x80040515B20000E4ULL, 0x8005051500000000ULL,
256         0x80050515000000E0ULL, 0x80050515B20000E4ULL,
257         SWITCH_SIGN,
258         /* Remove PADLOOPBACKN */
259         0x8002051500000000ULL, 0x80020515000000E0ULL,
260         0x80020515F20000E4ULL, 0x8003051500000000ULL,
261         0x80030515000000E0ULL, 0x80030515F20000E4ULL,
262         0x8004051500000000ULL, 0x80040515000000E0ULL,
263         0x80040515F20000E4ULL, 0x8005051500000000ULL,
264         0x80050515000000E0ULL, 0x80050515F20000E4ULL,
265         END_SIGN
266 };
267
268 /*
269  * Constants for Fixing the MacAddress problem seen mostly on
270  * Alpha machines.
271  */
272 static u64 fix_mac[] = {
273         0x0060000000000000ULL, 0x0060600000000000ULL,
274         0x0040600000000000ULL, 0x0000600000000000ULL,
275         0x0020600000000000ULL, 0x0060600000000000ULL,
276         0x0020600000000000ULL, 0x0060600000000000ULL,
277         0x0020600000000000ULL, 0x0060600000000000ULL,
278         0x0020600000000000ULL, 0x0060600000000000ULL,
279         0x0020600000000000ULL, 0x0060600000000000ULL,
280         0x0020600000000000ULL, 0x0060600000000000ULL,
281         0x0020600000000000ULL, 0x0060600000000000ULL,
282         0x0020600000000000ULL, 0x0060600000000000ULL,
283         0x0020600000000000ULL, 0x0060600000000000ULL,
284         0x0020600000000000ULL, 0x0060600000000000ULL,
285         0x0020600000000000ULL, 0x0000600000000000ULL,
286         0x0040600000000000ULL, 0x0060600000000000ULL,
287         END_SIGN
288 };
289
290 /* Module Loadable parameters. */
291 static unsigned int tx_fifo_num = 1;
292 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
293     {[0 ...(MAX_TX_FIFOS - 1)] = 0 };
294 static unsigned int rx_ring_num = 1;
295 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
296     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
297 static unsigned int rts_frm_len[MAX_RX_RINGS] =
298     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
299 static unsigned int use_continuous_tx_intrs = 1;
300 static unsigned int rmac_pause_time = 65535;
301 static unsigned int mc_pause_threshold_q0q3 = 187;
302 static unsigned int mc_pause_threshold_q4q7 = 187;
303 static unsigned int shared_splits;
304 static unsigned int tmac_util_period = 5;
305 static unsigned int rmac_util_period = 5;
306 static unsigned int bimodal = 0;
307 #ifndef CONFIG_S2IO_NAPI
308 static unsigned int indicate_max_pkts;
309 #endif
310 /* Frequency of Rx desc syncs expressed as power of 2 */
311 static unsigned int rxsync_frequency = 3;
312 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
313 static unsigned int intr_type = 0;
314
315 /*
316  * S2IO device table.
317  * This table lists all the devices that this driver supports.
318  */
319 static struct pci_device_id s2io_tbl[] __devinitdata = {
320         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
321          PCI_ANY_ID, PCI_ANY_ID},
322         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
323          PCI_ANY_ID, PCI_ANY_ID},
324         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
325          PCI_ANY_ID, PCI_ANY_ID},
326         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
327          PCI_ANY_ID, PCI_ANY_ID},
328         {0,}
329 };
330
331 MODULE_DEVICE_TABLE(pci, s2io_tbl);
332
333 static struct pci_driver s2io_driver = {
334       .name = "S2IO",
335       .id_table = s2io_tbl,
336       .probe = s2io_init_nic,
337       .remove = __devexit_p(s2io_rem_nic),
338 };
339
340 /* A simplifier macro used both by init and free shared_mem Fns(). */
341 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
342
343 /**
344  * init_shared_mem - Allocation and Initialization of Memory
345  * @nic: Device private variable.
346  * Description: The function allocates all the memory areas shared
347  * between the NIC and the driver. This includes Tx descriptors,
348  * Rx descriptors and the statistics block.
349  */
350
351 static int init_shared_mem(struct s2io_nic *nic)
352 {
353         u32 size;
354         void *tmp_v_addr, *tmp_v_addr_next;
355         dma_addr_t tmp_p_addr, tmp_p_addr_next;
356         RxD_block_t *pre_rxd_blk = NULL;
357         int i, j, blk_cnt, rx_sz, tx_sz;
358         int lst_size, lst_per_page;
359         struct net_device *dev = nic->dev;
360 #ifdef CONFIG_2BUFF_MODE
361         unsigned long tmp;
362         buffAdd_t *ba;
363 #endif
364
365         mac_info_t *mac_control;
366         struct config_param *config;
367
368         mac_control = &nic->mac_control;
369         config = &nic->config;
370
371
372         /* Allocation and initialization of TXDLs in FIOFs */
373         size = 0;
374         for (i = 0; i < config->tx_fifo_num; i++) {
375                 size += config->tx_cfg[i].fifo_len;
376         }
377         if (size > MAX_AVAILABLE_TXDS) {
378                 DBG_PRINT(ERR_DBG, "%s: Requested TxDs too high, ",
379                           __FUNCTION__);
380                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
381                 return FAILURE;
382         }
383
384         lst_size = (sizeof(TxD_t) * config->max_txds);
385         tx_sz = lst_size * size;
386         lst_per_page = PAGE_SIZE / lst_size;
387
388         for (i = 0; i < config->tx_fifo_num; i++) {
389                 int fifo_len = config->tx_cfg[i].fifo_len;
390                 int list_holder_size = fifo_len * sizeof(list_info_hold_t);
391                 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
392                                                           GFP_KERNEL);
393                 if (!mac_control->fifos[i].list_info) {
394                         DBG_PRINT(ERR_DBG,
395                                   "Malloc failed for list_info\n");
396                         return -ENOMEM;
397                 }
398                 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
399         }
400         for (i = 0; i < config->tx_fifo_num; i++) {
401                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
402                                                 lst_per_page);
403                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
404                 mac_control->fifos[i].tx_curr_put_info.fifo_len =
405                     config->tx_cfg[i].fifo_len - 1;
406                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
407                 mac_control->fifos[i].tx_curr_get_info.fifo_len =
408                     config->tx_cfg[i].fifo_len - 1;
409                 mac_control->fifos[i].fifo_no = i;
410                 mac_control->fifos[i].nic = nic;
411                 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 1;
412
413                 for (j = 0; j < page_num; j++) {
414                         int k = 0;
415                         dma_addr_t tmp_p;
416                         void *tmp_v;
417                         tmp_v = pci_alloc_consistent(nic->pdev,
418                                                      PAGE_SIZE, &tmp_p);
419                         if (!tmp_v) {
420                                 DBG_PRINT(ERR_DBG,
421                                           "pci_alloc_consistent ");
422                                 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
423                                 return -ENOMEM;
424                         }
425                         /* If we got a zero DMA address(can happen on
426                          * certain platforms like PPC), reallocate.
427                          * Store virtual address of page we don't want,
428                          * to be freed later.
429                          */
430                         if (!tmp_p) {
431                                 mac_control->zerodma_virt_addr = tmp_v;
432                                 DBG_PRINT(INIT_DBG, 
433                                 "%s: Zero DMA address for TxDL. ", dev->name);
434                                 DBG_PRINT(INIT_DBG, 
435                                 "Virtual address %p\n", tmp_v);
436                                 tmp_v = pci_alloc_consistent(nic->pdev,
437                                                      PAGE_SIZE, &tmp_p);
438                                 if (!tmp_v) {
439                                         DBG_PRINT(ERR_DBG,
440                                           "pci_alloc_consistent ");
441                                         DBG_PRINT(ERR_DBG, "failed for TxDL\n");
442                                         return -ENOMEM;
443                                 }
444                         }
445                         while (k < lst_per_page) {
446                                 int l = (j * lst_per_page) + k;
447                                 if (l == config->tx_cfg[i].fifo_len)
448                                         break;
449                                 mac_control->fifos[i].list_info[l].list_virt_addr =
450                                     tmp_v + (k * lst_size);
451                                 mac_control->fifos[i].list_info[l].list_phy_addr =
452                                     tmp_p + (k * lst_size);
453                                 k++;
454                         }
455                 }
456         }
457
458         /* Allocation and initialization of RXDs in Rings */
459         size = 0;
460         for (i = 0; i < config->rx_ring_num; i++) {
461                 if (config->rx_cfg[i].num_rxd % (MAX_RXDS_PER_BLOCK + 1)) {
462                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
463                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
464                                   i);
465                         DBG_PRINT(ERR_DBG, "RxDs per Block");
466                         return FAILURE;
467                 }
468                 size += config->rx_cfg[i].num_rxd;
469                 mac_control->rings[i].block_count =
470                     config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
471                 mac_control->rings[i].pkt_cnt =
472                     config->rx_cfg[i].num_rxd - mac_control->rings[i].block_count;
473         }
474         size = (size * (sizeof(RxD_t)));
475         rx_sz = size;
476
477         for (i = 0; i < config->rx_ring_num; i++) {
478                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
479                 mac_control->rings[i].rx_curr_get_info.offset = 0;
480                 mac_control->rings[i].rx_curr_get_info.ring_len =
481                     config->rx_cfg[i].num_rxd - 1;
482                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
483                 mac_control->rings[i].rx_curr_put_info.offset = 0;
484                 mac_control->rings[i].rx_curr_put_info.ring_len =
485                     config->rx_cfg[i].num_rxd - 1;
486                 mac_control->rings[i].nic = nic;
487                 mac_control->rings[i].ring_no = i;
488
489                 blk_cnt =
490                     config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
491                 /*  Allocating all the Rx blocks */
492                 for (j = 0; j < blk_cnt; j++) {
493 #ifndef CONFIG_2BUFF_MODE
494                         size = (MAX_RXDS_PER_BLOCK + 1) * (sizeof(RxD_t));
495 #else
496                         size = SIZE_OF_BLOCK;
497 #endif
498                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
499                                                           &tmp_p_addr);
500                         if (tmp_v_addr == NULL) {
501                                 /*
502                                  * In case of failure, free_shared_mem()
503                                  * is called, which should free any
504                                  * memory that was alloced till the
505                                  * failure happened.
506                                  */
507                                 mac_control->rings[i].rx_blocks[j].block_virt_addr =
508                                     tmp_v_addr;
509                                 return -ENOMEM;
510                         }
511                         memset(tmp_v_addr, 0, size);
512                         mac_control->rings[i].rx_blocks[j].block_virt_addr =
513                                 tmp_v_addr;
514                         mac_control->rings[i].rx_blocks[j].block_dma_addr =
515                                 tmp_p_addr;
516                 }
517                 /* Interlinking all Rx Blocks */
518                 for (j = 0; j < blk_cnt; j++) {
519                         tmp_v_addr =
520                                 mac_control->rings[i].rx_blocks[j].block_virt_addr;
521                         tmp_v_addr_next =
522                                 mac_control->rings[i].rx_blocks[(j + 1) %
523                                               blk_cnt].block_virt_addr;
524                         tmp_p_addr =
525                                 mac_control->rings[i].rx_blocks[j].block_dma_addr;
526                         tmp_p_addr_next =
527                                 mac_control->rings[i].rx_blocks[(j + 1) %
528                                               blk_cnt].block_dma_addr;
529
530                         pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
531                         pre_rxd_blk->reserved_1 = END_OF_BLOCK; /* last RxD
532                                                                  * marker.
533                                                                  */
534 #ifndef CONFIG_2BUFF_MODE
535                         pre_rxd_blk->reserved_2_pNext_RxD_block =
536                             (unsigned long) tmp_v_addr_next;
537 #endif
538                         pre_rxd_blk->pNext_RxD_Blk_physical =
539                             (u64) tmp_p_addr_next;
540                 }
541         }
542
543 #ifdef CONFIG_2BUFF_MODE
544         /*
545          * Allocation of Storages for buffer addresses in 2BUFF mode
546          * and the buffers as well.
547          */
548         for (i = 0; i < config->rx_ring_num; i++) {
549                 blk_cnt =
550                     config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
551                 mac_control->rings[i].ba = kmalloc((sizeof(buffAdd_t *) * blk_cnt),
552                                      GFP_KERNEL);
553                 if (!mac_control->rings[i].ba)
554                         return -ENOMEM;
555                 for (j = 0; j < blk_cnt; j++) {
556                         int k = 0;
557                         mac_control->rings[i].ba[j] = kmalloc((sizeof(buffAdd_t) *
558                                                  (MAX_RXDS_PER_BLOCK + 1)),
559                                                 GFP_KERNEL);
560                         if (!mac_control->rings[i].ba[j])
561                                 return -ENOMEM;
562                         while (k != MAX_RXDS_PER_BLOCK) {
563                                 ba = &mac_control->rings[i].ba[j][k];
564
565                                 ba->ba_0_org = (void *) kmalloc
566                                     (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
567                                 if (!ba->ba_0_org)
568                                         return -ENOMEM;
569                                 tmp = (unsigned long) ba->ba_0_org;
570                                 tmp += ALIGN_SIZE;
571                                 tmp &= ~((unsigned long) ALIGN_SIZE);
572                                 ba->ba_0 = (void *) tmp;
573
574                                 ba->ba_1_org = (void *) kmalloc
575                                     (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
576                                 if (!ba->ba_1_org)
577                                         return -ENOMEM;
578                                 tmp = (unsigned long) ba->ba_1_org;
579                                 tmp += ALIGN_SIZE;
580                                 tmp &= ~((unsigned long) ALIGN_SIZE);
581                                 ba->ba_1 = (void *) tmp;
582                                 k++;
583                         }
584                 }
585         }
586 #endif
587
588         /* Allocation and initialization of Statistics block */
589         size = sizeof(StatInfo_t);
590         mac_control->stats_mem = pci_alloc_consistent
591             (nic->pdev, size, &mac_control->stats_mem_phy);
592
593         if (!mac_control->stats_mem) {
594                 /*
595                  * In case of failure, free_shared_mem() is called, which
596                  * should free any memory that was alloced till the
597                  * failure happened.
598                  */
599                 return -ENOMEM;
600         }
601         mac_control->stats_mem_sz = size;
602
603         tmp_v_addr = mac_control->stats_mem;
604         mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
605         memset(tmp_v_addr, 0, size);
606         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
607                   (unsigned long long) tmp_p_addr);
608
609         return SUCCESS;
610 }
611
612 /**
613  * free_shared_mem - Free the allocated Memory
614  * @nic:  Device private variable.
615  * Description: This function is to free all memory locations allocated by
616  * the init_shared_mem() function and return it to the kernel.
617  */
618
619 static void free_shared_mem(struct s2io_nic *nic)
620 {
621         int i, j, blk_cnt, size;
622         void *tmp_v_addr;
623         dma_addr_t tmp_p_addr;
624         mac_info_t *mac_control;
625         struct config_param *config;
626         int lst_size, lst_per_page;
627         struct net_device *dev = nic->dev;
628
629         if (!nic)
630                 return;
631
632         mac_control = &nic->mac_control;
633         config = &nic->config;
634
635         lst_size = (sizeof(TxD_t) * config->max_txds);
636         lst_per_page = PAGE_SIZE / lst_size;
637
638         for (i = 0; i < config->tx_fifo_num; i++) {
639                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
640                                                 lst_per_page);
641                 for (j = 0; j < page_num; j++) {
642                         int mem_blks = (j * lst_per_page);
643                         if (!mac_control->fifos[i].list_info)
644                                 return; 
645                         if (!mac_control->fifos[i].list_info[mem_blks].
646                                  list_virt_addr)
647                                 break;
648                         pci_free_consistent(nic->pdev, PAGE_SIZE,
649                                             mac_control->fifos[i].
650                                             list_info[mem_blks].
651                                             list_virt_addr,
652                                             mac_control->fifos[i].
653                                             list_info[mem_blks].
654                                             list_phy_addr);
655                 }
656                 /* If we got a zero DMA address during allocation,
657                  * free the page now
658                  */
659                 if (mac_control->zerodma_virt_addr) {
660                         pci_free_consistent(nic->pdev, PAGE_SIZE,
661                                             mac_control->zerodma_virt_addr,
662                                             (dma_addr_t)0);
663                         DBG_PRINT(INIT_DBG, 
664                                 "%s: Freeing TxDL with zero DMA addr. ",
665                                 dev->name);
666                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
667                                 mac_control->zerodma_virt_addr);
668                 }
669                 kfree(mac_control->fifos[i].list_info);
670         }
671
672 #ifndef CONFIG_2BUFF_MODE
673         size = (MAX_RXDS_PER_BLOCK + 1) * (sizeof(RxD_t));
674 #else
675         size = SIZE_OF_BLOCK;
676 #endif
677         for (i = 0; i < config->rx_ring_num; i++) {
678                 blk_cnt = mac_control->rings[i].block_count;
679                 for (j = 0; j < blk_cnt; j++) {
680                         tmp_v_addr = mac_control->rings[i].rx_blocks[j].
681                                 block_virt_addr;
682                         tmp_p_addr = mac_control->rings[i].rx_blocks[j].
683                                 block_dma_addr;
684                         if (tmp_v_addr == NULL)
685                                 break;
686                         pci_free_consistent(nic->pdev, size,
687                                             tmp_v_addr, tmp_p_addr);
688                 }
689         }
690
691 #ifdef CONFIG_2BUFF_MODE
692         /* Freeing buffer storage addresses in 2BUFF mode. */
693         for (i = 0; i < config->rx_ring_num; i++) {
694                 blk_cnt =
695                     config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
696                 for (j = 0; j < blk_cnt; j++) {
697                         int k = 0;
698                         if (!mac_control->rings[i].ba[j])
699                                 continue;
700                         while (k != MAX_RXDS_PER_BLOCK) {
701                                 buffAdd_t *ba = &mac_control->rings[i].ba[j][k];
702                                 kfree(ba->ba_0_org);
703                                 kfree(ba->ba_1_org);
704                                 k++;
705                         }
706                         kfree(mac_control->rings[i].ba[j]);
707                 }
708                 if (mac_control->rings[i].ba)
709                         kfree(mac_control->rings[i].ba);
710         }
711 #endif
712
713         if (mac_control->stats_mem) {
714                 pci_free_consistent(nic->pdev,
715                                     mac_control->stats_mem_sz,
716                                     mac_control->stats_mem,
717                                     mac_control->stats_mem_phy);
718         }
719 }
720
721 /**
722  * s2io_verify_pci_mode -
723  */
724
725 static int s2io_verify_pci_mode(nic_t *nic)
726 {
727         XENA_dev_config_t __iomem *bar0 = nic->bar0;
728         register u64 val64 = 0;
729         int     mode;
730
731         val64 = readq(&bar0->pci_mode);
732         mode = (u8)GET_PCI_MODE(val64);
733
734         if ( val64 & PCI_MODE_UNKNOWN_MODE)
735                 return -1;      /* Unknown PCI mode */
736         return mode;
737 }
738
739
740 /**
741  * s2io_print_pci_mode -
742  */
743 static int s2io_print_pci_mode(nic_t *nic)
744 {
745         XENA_dev_config_t __iomem *bar0 = nic->bar0;
746         register u64 val64 = 0;
747         int     mode;
748         struct config_param *config = &nic->config;
749
750         val64 = readq(&bar0->pci_mode);
751         mode = (u8)GET_PCI_MODE(val64);
752
753         if ( val64 & PCI_MODE_UNKNOWN_MODE)
754                 return -1;      /* Unknown PCI mode */
755
756         if (val64 & PCI_MODE_32_BITS) {
757                 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
758         } else {
759                 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
760         }
761
762         switch(mode) {
763                 case PCI_MODE_PCI_33:
764                         DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
765                         config->bus_speed = 33;
766                         break;
767                 case PCI_MODE_PCI_66:
768                         DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
769                         config->bus_speed = 133;
770                         break;
771                 case PCI_MODE_PCIX_M1_66:
772                         DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
773                         config->bus_speed = 133; /* Herc doubles the clock rate */
774                         break;
775                 case PCI_MODE_PCIX_M1_100:
776                         DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
777                         config->bus_speed = 200;
778                         break;
779                 case PCI_MODE_PCIX_M1_133:
780                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
781                         config->bus_speed = 266;
782                         break;
783                 case PCI_MODE_PCIX_M2_66:
784                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
785                         config->bus_speed = 133;
786                         break;
787                 case PCI_MODE_PCIX_M2_100:
788                         DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
789                         config->bus_speed = 200;
790                         break;
791                 case PCI_MODE_PCIX_M2_133:
792                         DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
793                         config->bus_speed = 266;
794                         break;
795                 default:
796                         return -1;      /* Unsupported bus speed */
797         }
798
799         return mode;
800 }
801
802 /**
803  *  init_nic - Initialization of hardware
804  *  @nic: device peivate variable
805  *  Description: The function sequentially configures every block
806  *  of the H/W from their reset values.
807  *  Return Value:  SUCCESS on success and
808  *  '-1' on failure (endian settings incorrect).
809  */
810
811 static int init_nic(struct s2io_nic *nic)
812 {
813         XENA_dev_config_t __iomem *bar0 = nic->bar0;
814         struct net_device *dev = nic->dev;
815         register u64 val64 = 0;
816         void __iomem *add;
817         u32 time;
818         int i, j;
819         mac_info_t *mac_control;
820         struct config_param *config;
821         int mdio_cnt = 0, dtx_cnt = 0;
822         unsigned long long mem_share;
823         int mem_size;
824
825         mac_control = &nic->mac_control;
826         config = &nic->config;
827
828         /* to set the swapper controle on the card */
829         if(s2io_set_swapper(nic)) {
830                 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
831                 return -1;
832         }
833
834         /*
835          * Herc requires EOI to be removed from reset before XGXS, so..
836          */
837         if (nic->device_type & XFRAME_II_DEVICE) {
838                 val64 = 0xA500000000ULL;
839                 writeq(val64, &bar0->sw_reset);
840                 msleep(500);
841                 val64 = readq(&bar0->sw_reset);
842         }
843
844         /* Remove XGXS from reset state */
845         val64 = 0;
846         writeq(val64, &bar0->sw_reset);
847         msleep(500);
848         val64 = readq(&bar0->sw_reset);
849
850         /*  Enable Receiving broadcasts */
851         add = &bar0->mac_cfg;
852         val64 = readq(&bar0->mac_cfg);
853         val64 |= MAC_RMAC_BCAST_ENABLE;
854         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
855         writel((u32) val64, add);
856         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
857         writel((u32) (val64 >> 32), (add + 4));
858
859         /* Read registers in all blocks */
860         val64 = readq(&bar0->mac_int_mask);
861         val64 = readq(&bar0->mc_int_mask);
862         val64 = readq(&bar0->xgxs_int_mask);
863
864         /*  Set MTU */
865         val64 = dev->mtu;
866         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
867
868         /*
869          * Configuring the XAUI Interface of Xena.
870          * ***************************************
871          * To Configure the Xena's XAUI, one has to write a series
872          * of 64 bit values into two registers in a particular
873          * sequence. Hence a macro 'SWITCH_SIGN' has been defined
874          * which will be defined in the array of configuration values
875          * (xena_dtx_cfg & xena_mdio_cfg) at appropriate places
876          * to switch writing from one regsiter to another. We continue
877          * writing these values until we encounter the 'END_SIGN' macro.
878          * For example, After making a series of 21 writes into
879          * dtx_control register the 'SWITCH_SIGN' appears and hence we
880          * start writing into mdio_control until we encounter END_SIGN.
881          */
882         if (nic->device_type & XFRAME_II_DEVICE) {
883                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
884                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
885                                           &bar0->dtx_control, UF);
886                         if (dtx_cnt & 0x1)
887                                 msleep(1); /* Necessary!! */
888                         dtx_cnt++;
889                 }
890         } else {
891                 while (1) {
892                       dtx_cfg:
893                         while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
894                                 if (xena_dtx_cfg[dtx_cnt] == SWITCH_SIGN) {
895                                         dtx_cnt++;
896                                         goto mdio_cfg;
897                                 }
898                                 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
899                                                   &bar0->dtx_control, UF);
900                                 val64 = readq(&bar0->dtx_control);
901                                 dtx_cnt++;
902                         }
903                       mdio_cfg:
904                         while (xena_mdio_cfg[mdio_cnt] != END_SIGN) {
905                                 if (xena_mdio_cfg[mdio_cnt] == SWITCH_SIGN) {
906                                         mdio_cnt++;
907                                         goto dtx_cfg;
908                                 }
909                                 SPECIAL_REG_WRITE(xena_mdio_cfg[mdio_cnt],
910                                                   &bar0->mdio_control, UF);
911                                 val64 = readq(&bar0->mdio_control);
912                                 mdio_cnt++;
913                         }
914                         if ((xena_dtx_cfg[dtx_cnt] == END_SIGN) &&
915                             (xena_mdio_cfg[mdio_cnt] == END_SIGN)) {
916                                 break;
917                         } else {
918                                 goto dtx_cfg;
919                         }
920                 }
921         }
922
923         /*  Tx DMA Initialization */
924         val64 = 0;
925         writeq(val64, &bar0->tx_fifo_partition_0);
926         writeq(val64, &bar0->tx_fifo_partition_1);
927         writeq(val64, &bar0->tx_fifo_partition_2);
928         writeq(val64, &bar0->tx_fifo_partition_3);
929
930
931         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
932                 val64 |=
933                     vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
934                          13) | vBIT(config->tx_cfg[i].fifo_priority,
935                                     ((i * 32) + 5), 3);
936
937                 if (i == (config->tx_fifo_num - 1)) {
938                         if (i % 2 == 0)
939                                 i++;
940                 }
941
942                 switch (i) {
943                 case 1:
944                         writeq(val64, &bar0->tx_fifo_partition_0);
945                         val64 = 0;
946                         break;
947                 case 3:
948                         writeq(val64, &bar0->tx_fifo_partition_1);
949                         val64 = 0;
950                         break;
951                 case 5:
952                         writeq(val64, &bar0->tx_fifo_partition_2);
953                         val64 = 0;
954                         break;
955                 case 7:
956                         writeq(val64, &bar0->tx_fifo_partition_3);
957                         break;
958                 }
959         }
960
961         /* Enable Tx FIFO partition 0. */
962         val64 = readq(&bar0->tx_fifo_partition_0);
963         val64 |= BIT(0);        /* To enable the FIFO partition. */
964         writeq(val64, &bar0->tx_fifo_partition_0);
965
966         /*
967          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
968          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
969          */
970         if ((nic->device_type == XFRAME_I_DEVICE) &&
971                 (get_xena_rev_id(nic->pdev) < 4))
972                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
973
974         val64 = readq(&bar0->tx_fifo_partition_0);
975         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
976                   &bar0->tx_fifo_partition_0, (unsigned long long) val64);
977
978         /*
979          * Initialization of Tx_PA_CONFIG register to ignore packet
980          * integrity checking.
981          */
982         val64 = readq(&bar0->tx_pa_cfg);
983         val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
984             TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
985         writeq(val64, &bar0->tx_pa_cfg);
986
987         /* Rx DMA intialization. */
988         val64 = 0;
989         for (i = 0; i < config->rx_ring_num; i++) {
990                 val64 |=
991                     vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
992                          3);
993         }
994         writeq(val64, &bar0->rx_queue_priority);
995
996         /*
997          * Allocating equal share of memory to all the
998          * configured Rings.
999          */
1000         val64 = 0;
1001         if (nic->device_type & XFRAME_II_DEVICE)
1002                 mem_size = 32;
1003         else
1004                 mem_size = 64;
1005
1006         for (i = 0; i < config->rx_ring_num; i++) {
1007                 switch (i) {
1008                 case 0:
1009                         mem_share = (mem_size / config->rx_ring_num +
1010                                      mem_size % config->rx_ring_num);
1011                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1012                         continue;
1013                 case 1:
1014                         mem_share = (mem_size / config->rx_ring_num);
1015                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1016                         continue;
1017                 case 2:
1018                         mem_share = (mem_size / config->rx_ring_num);
1019                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1020                         continue;
1021                 case 3:
1022                         mem_share = (mem_size / config->rx_ring_num);
1023                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1024                         continue;
1025                 case 4:
1026                         mem_share = (mem_size / config->rx_ring_num);
1027                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1028                         continue;
1029                 case 5:
1030                         mem_share = (mem_size / config->rx_ring_num);
1031                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1032                         continue;
1033                 case 6:
1034                         mem_share = (mem_size / config->rx_ring_num);
1035                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1036                         continue;
1037                 case 7:
1038                         mem_share = (mem_size / config->rx_ring_num);
1039                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1040                         continue;
1041                 }
1042         }
1043         writeq(val64, &bar0->rx_queue_cfg);
1044
1045         /*
1046          * Filling Tx round robin registers
1047          * as per the number of FIFOs
1048          */
1049         switch (config->tx_fifo_num) {
1050         case 1:
1051                 val64 = 0x0000000000000000ULL;
1052                 writeq(val64, &bar0->tx_w_round_robin_0);
1053                 writeq(val64, &bar0->tx_w_round_robin_1);
1054                 writeq(val64, &bar0->tx_w_round_robin_2);
1055                 writeq(val64, &bar0->tx_w_round_robin_3);
1056                 writeq(val64, &bar0->tx_w_round_robin_4);
1057                 break;
1058         case 2:
1059                 val64 = 0x0000010000010000ULL;
1060                 writeq(val64, &bar0->tx_w_round_robin_0);
1061                 val64 = 0x0100000100000100ULL;
1062                 writeq(val64, &bar0->tx_w_round_robin_1);
1063                 val64 = 0x0001000001000001ULL;
1064                 writeq(val64, &bar0->tx_w_round_robin_2);
1065                 val64 = 0x0000010000010000ULL;
1066                 writeq(val64, &bar0->tx_w_round_robin_3);
1067                 val64 = 0x0100000000000000ULL;
1068                 writeq(val64, &bar0->tx_w_round_robin_4);
1069                 break;
1070         case 3:
1071                 val64 = 0x0001000102000001ULL;
1072                 writeq(val64, &bar0->tx_w_round_robin_0);
1073                 val64 = 0x0001020000010001ULL;
1074                 writeq(val64, &bar0->tx_w_round_robin_1);
1075                 val64 = 0x0200000100010200ULL;
1076                 writeq(val64, &bar0->tx_w_round_robin_2);
1077                 val64 = 0x0001000102000001ULL;
1078                 writeq(val64, &bar0->tx_w_round_robin_3);
1079                 val64 = 0x0001020000000000ULL;
1080                 writeq(val64, &bar0->tx_w_round_robin_4);
1081                 break;
1082         case 4:
1083                 val64 = 0x0001020300010200ULL;
1084                 writeq(val64, &bar0->tx_w_round_robin_0);
1085                 val64 = 0x0100000102030001ULL;
1086                 writeq(val64, &bar0->tx_w_round_robin_1);
1087                 val64 = 0x0200010000010203ULL;
1088                 writeq(val64, &bar0->tx_w_round_robin_2);
1089                 val64 = 0x0001020001000001ULL;
1090                 writeq(val64, &bar0->tx_w_round_robin_3);
1091                 val64 = 0x0203000100000000ULL;
1092                 writeq(val64, &bar0->tx_w_round_robin_4);
1093                 break;
1094         case 5:
1095                 val64 = 0x0001000203000102ULL;
1096                 writeq(val64, &bar0->tx_w_round_robin_0);
1097                 val64 = 0x0001020001030004ULL;
1098                 writeq(val64, &bar0->tx_w_round_robin_1);
1099                 val64 = 0x0001000203000102ULL;
1100                 writeq(val64, &bar0->tx_w_round_robin_2);
1101                 val64 = 0x0001020001030004ULL;
1102                 writeq(val64, &bar0->tx_w_round_robin_3);
1103                 val64 = 0x0001000000000000ULL;
1104                 writeq(val64, &bar0->tx_w_round_robin_4);
1105                 break;
1106         case 6:
1107                 val64 = 0x0001020304000102ULL;
1108                 writeq(val64, &bar0->tx_w_round_robin_0);
1109                 val64 = 0x0304050001020001ULL;
1110                 writeq(val64, &bar0->tx_w_round_robin_1);
1111                 val64 = 0x0203000100000102ULL;
1112                 writeq(val64, &bar0->tx_w_round_robin_2);
1113                 val64 = 0x0304000102030405ULL;
1114                 writeq(val64, &bar0->tx_w_round_robin_3);
1115                 val64 = 0x0001000200000000ULL;
1116                 writeq(val64, &bar0->tx_w_round_robin_4);
1117                 break;
1118         case 7:
1119                 val64 = 0x0001020001020300ULL;
1120                 writeq(val64, &bar0->tx_w_round_robin_0);
1121                 val64 = 0x0102030400010203ULL;
1122                 writeq(val64, &bar0->tx_w_round_robin_1);
1123                 val64 = 0x0405060001020001ULL;
1124                 writeq(val64, &bar0->tx_w_round_robin_2);
1125                 val64 = 0x0304050000010200ULL;
1126                 writeq(val64, &bar0->tx_w_round_robin_3);
1127                 val64 = 0x0102030000000000ULL;
1128                 writeq(val64, &bar0->tx_w_round_robin_4);
1129                 break;
1130         case 8:
1131                 val64 = 0x0001020300040105ULL;
1132                 writeq(val64, &bar0->tx_w_round_robin_0);
1133                 val64 = 0x0200030106000204ULL;
1134                 writeq(val64, &bar0->tx_w_round_robin_1);
1135                 val64 = 0x0103000502010007ULL;
1136                 writeq(val64, &bar0->tx_w_round_robin_2);
1137                 val64 = 0x0304010002060500ULL;
1138                 writeq(val64, &bar0->tx_w_round_robin_3);
1139                 val64 = 0x0103020400000000ULL;
1140                 writeq(val64, &bar0->tx_w_round_robin_4);
1141                 break;
1142         }
1143
1144         /* Filling the Rx round robin registers as per the
1145          * number of Rings and steering based on QoS.
1146          */
1147         switch (config->rx_ring_num) {
1148         case 1:
1149                 val64 = 0x8080808080808080ULL;
1150                 writeq(val64, &bar0->rts_qos_steering);
1151                 break;
1152         case 2:
1153                 val64 = 0x0000010000010000ULL;
1154                 writeq(val64, &bar0->rx_w_round_robin_0);
1155                 val64 = 0x0100000100000100ULL;
1156                 writeq(val64, &bar0->rx_w_round_robin_1);
1157                 val64 = 0x0001000001000001ULL;
1158                 writeq(val64, &bar0->rx_w_round_robin_2);
1159                 val64 = 0x0000010000010000ULL;
1160                 writeq(val64, &bar0->rx_w_round_robin_3);
1161                 val64 = 0x0100000000000000ULL;
1162                 writeq(val64, &bar0->rx_w_round_robin_4);
1163
1164                 val64 = 0x8080808040404040ULL;
1165                 writeq(val64, &bar0->rts_qos_steering);
1166                 break;
1167         case 3:
1168                 val64 = 0x0001000102000001ULL;
1169                 writeq(val64, &bar0->rx_w_round_robin_0);
1170                 val64 = 0x0001020000010001ULL;
1171                 writeq(val64, &bar0->rx_w_round_robin_1);
1172                 val64 = 0x0200000100010200ULL;
1173                 writeq(val64, &bar0->rx_w_round_robin_2);
1174                 val64 = 0x0001000102000001ULL;
1175                 writeq(val64, &bar0->rx_w_round_robin_3);
1176                 val64 = 0x0001020000000000ULL;
1177                 writeq(val64, &bar0->rx_w_round_robin_4);
1178
1179                 val64 = 0x8080804040402020ULL;
1180                 writeq(val64, &bar0->rts_qos_steering);
1181                 break;
1182         case 4:
1183                 val64 = 0x0001020300010200ULL;
1184                 writeq(val64, &bar0->rx_w_round_robin_0);
1185                 val64 = 0x0100000102030001ULL;
1186                 writeq(val64, &bar0->rx_w_round_robin_1);
1187                 val64 = 0x0200010000010203ULL;
1188                 writeq(val64, &bar0->rx_w_round_robin_2);
1189                 val64 = 0x0001020001000001ULL;  
1190                 writeq(val64, &bar0->rx_w_round_robin_3);
1191                 val64 = 0x0203000100000000ULL;
1192                 writeq(val64, &bar0->rx_w_round_robin_4);
1193
1194                 val64 = 0x8080404020201010ULL;
1195                 writeq(val64, &bar0->rts_qos_steering);
1196                 break;
1197         case 5:
1198                 val64 = 0x0001000203000102ULL;
1199                 writeq(val64, &bar0->rx_w_round_robin_0);
1200                 val64 = 0x0001020001030004ULL;
1201                 writeq(val64, &bar0->rx_w_round_robin_1);
1202                 val64 = 0x0001000203000102ULL;
1203                 writeq(val64, &bar0->rx_w_round_robin_2);
1204                 val64 = 0x0001020001030004ULL;
1205                 writeq(val64, &bar0->rx_w_round_robin_3);
1206                 val64 = 0x0001000000000000ULL;
1207                 writeq(val64, &bar0->rx_w_round_robin_4);
1208
1209                 val64 = 0x8080404020201008ULL;
1210                 writeq(val64, &bar0->rts_qos_steering);
1211                 break;
1212         case 6:
1213                 val64 = 0x0001020304000102ULL;
1214                 writeq(val64, &bar0->rx_w_round_robin_0);
1215                 val64 = 0x0304050001020001ULL;
1216                 writeq(val64, &bar0->rx_w_round_robin_1);
1217                 val64 = 0x0203000100000102ULL;
1218                 writeq(val64, &bar0->rx_w_round_robin_2);
1219                 val64 = 0x0304000102030405ULL;
1220                 writeq(val64, &bar0->rx_w_round_robin_3);
1221                 val64 = 0x0001000200000000ULL;
1222                 writeq(val64, &bar0->rx_w_round_robin_4);
1223
1224                 val64 = 0x8080404020100804ULL;
1225                 writeq(val64, &bar0->rts_qos_steering);
1226                 break;
1227         case 7:
1228                 val64 = 0x0001020001020300ULL;
1229                 writeq(val64, &bar0->rx_w_round_robin_0);
1230                 val64 = 0x0102030400010203ULL;
1231                 writeq(val64, &bar0->rx_w_round_robin_1);
1232                 val64 = 0x0405060001020001ULL;
1233                 writeq(val64, &bar0->rx_w_round_robin_2);
1234                 val64 = 0x0304050000010200ULL;
1235                 writeq(val64, &bar0->rx_w_round_robin_3);
1236                 val64 = 0x0102030000000000ULL;
1237                 writeq(val64, &bar0->rx_w_round_robin_4);
1238
1239                 val64 = 0x8080402010080402ULL;
1240                 writeq(val64, &bar0->rts_qos_steering);
1241                 break;
1242         case 8:
1243                 val64 = 0x0001020300040105ULL;
1244                 writeq(val64, &bar0->rx_w_round_robin_0);
1245                 val64 = 0x0200030106000204ULL;
1246                 writeq(val64, &bar0->rx_w_round_robin_1);
1247                 val64 = 0x0103000502010007ULL;
1248                 writeq(val64, &bar0->rx_w_round_robin_2);
1249                 val64 = 0x0304010002060500ULL;
1250                 writeq(val64, &bar0->rx_w_round_robin_3);
1251                 val64 = 0x0103020400000000ULL;
1252                 writeq(val64, &bar0->rx_w_round_robin_4);
1253
1254                 val64 = 0x8040201008040201ULL;
1255                 writeq(val64, &bar0->rts_qos_steering);
1256                 break;
1257         }
1258
1259         /* UDP Fix */
1260         val64 = 0;
1261         for (i = 0; i < 8; i++)
1262                 writeq(val64, &bar0->rts_frm_len_n[i]);
1263
1264         /* Set the default rts frame length for the rings configured */
1265         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1266         for (i = 0 ; i < config->rx_ring_num ; i++)
1267                 writeq(val64, &bar0->rts_frm_len_n[i]);
1268
1269         /* Set the frame length for the configured rings
1270          * desired by the user
1271          */
1272         for (i = 0; i < config->rx_ring_num; i++) {
1273                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1274                  * specified frame length steering.
1275                  * If the user provides the frame length then program
1276                  * the rts_frm_len register for those values or else
1277                  * leave it as it is.
1278                  */
1279                 if (rts_frm_len[i] != 0) {
1280                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1281                                 &bar0->rts_frm_len_n[i]);
1282                 }
1283         }
1284
1285         /* Program statistics memory */
1286         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1287
1288         if (nic->device_type == XFRAME_II_DEVICE) {
1289                 val64 = STAT_BC(0x320);
1290                 writeq(val64, &bar0->stat_byte_cnt);
1291         }
1292
1293         /*
1294          * Initializing the sampling rate for the device to calculate the
1295          * bandwidth utilization.
1296          */
1297         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1298             MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1299         writeq(val64, &bar0->mac_link_util);
1300
1301
1302         /*
1303          * Initializing the Transmit and Receive Traffic Interrupt
1304          * Scheme.
1305          */
1306         /*
1307          * TTI Initialization. Default Tx timer gets us about
1308          * 250 interrupts per sec. Continuous interrupts are enabled
1309          * by default.
1310          */
1311         if (nic->device_type == XFRAME_II_DEVICE) {
1312                 int count = (nic->config.bus_speed * 125)/2;
1313                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1314         } else {
1315
1316                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1317         }
1318         val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1319             TTI_DATA1_MEM_TX_URNG_B(0x10) |
1320             TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1321                 if (use_continuous_tx_intrs)
1322                         val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1323         writeq(val64, &bar0->tti_data1_mem);
1324
1325         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1326             TTI_DATA2_MEM_TX_UFC_B(0x20) |
1327             TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1328         writeq(val64, &bar0->tti_data2_mem);
1329
1330         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1331         writeq(val64, &bar0->tti_command_mem);
1332
1333         /*
1334          * Once the operation completes, the Strobe bit of the command
1335          * register will be reset. We poll for this particular condition
1336          * We wait for a maximum of 500ms for the operation to complete,
1337          * if it's not complete by then we return error.
1338          */
1339         time = 0;
1340         while (TRUE) {
1341                 val64 = readq(&bar0->tti_command_mem);
1342                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1343                         break;
1344                 }
1345                 if (time > 10) {
1346                         DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1347                                   dev->name);
1348                         return -1;
1349                 }
1350                 msleep(50);
1351                 time++;
1352         }
1353
1354         if (nic->config.bimodal) {
1355                 int k = 0;
1356                 for (k = 0; k < config->rx_ring_num; k++) {
1357                         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1358                         val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1359                         writeq(val64, &bar0->tti_command_mem);
1360
1361                 /*
1362                  * Once the operation completes, the Strobe bit of the command
1363                  * register will be reset. We poll for this particular condition
1364                  * We wait for a maximum of 500ms for the operation to complete,
1365                  * if it's not complete by then we return error.
1366                 */
1367                         time = 0;
1368                         while (TRUE) {
1369                                 val64 = readq(&bar0->tti_command_mem);
1370                                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1371                                         break;
1372                                 }
1373                                 if (time > 10) {
1374                                         DBG_PRINT(ERR_DBG,
1375                                                 "%s: TTI init Failed\n",
1376                                         dev->name);
1377                                         return -1;
1378                                 }
1379                                 time++;
1380                                 msleep(50);
1381                         }
1382                 }
1383         } else {
1384
1385                 /* RTI Initialization */
1386                 if (nic->device_type == XFRAME_II_DEVICE) {
1387                         /*
1388                          * Programmed to generate Apprx 500 Intrs per
1389                          * second
1390                          */
1391                         int count = (nic->config.bus_speed * 125)/4;
1392                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1393                 } else {
1394                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1395                 }
1396                 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1397                     RTI_DATA1_MEM_RX_URNG_B(0x10) |
1398                     RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1399
1400                 writeq(val64, &bar0->rti_data1_mem);
1401
1402                 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1403                     RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1404                 if (nic->intr_type == MSI_X)
1405                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1406                                 RTI_DATA2_MEM_RX_UFC_D(0x40));
1407                 else
1408                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1409                                 RTI_DATA2_MEM_RX_UFC_D(0x80));
1410                 writeq(val64, &bar0->rti_data2_mem);
1411
1412                 for (i = 0; i < config->rx_ring_num; i++) {
1413                         val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1414                                         | RTI_CMD_MEM_OFFSET(i);
1415                         writeq(val64, &bar0->rti_command_mem);
1416
1417                         /*
1418                          * Once the operation completes, the Strobe bit of the
1419                          * command register will be reset. We poll for this
1420                          * particular condition. We wait for a maximum of 500ms
1421                          * for the operation to complete, if it's not complete
1422                          * by then we return error.
1423                          */
1424                         time = 0;
1425                         while (TRUE) {
1426                                 val64 = readq(&bar0->rti_command_mem);
1427                                 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1428                                         break;
1429                                 }
1430                                 if (time > 10) {
1431                                         DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1432                                                   dev->name);
1433                                         return -1;
1434                                 }
1435                                 time++;
1436                                 msleep(50);
1437                         }
1438                 }
1439         }
1440
1441         /*
1442          * Initializing proper values as Pause threshold into all
1443          * the 8 Queues on Rx side.
1444          */
1445         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1446         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1447
1448         /* Disable RMAC PAD STRIPPING */
1449         add = &bar0->mac_cfg;
1450         val64 = readq(&bar0->mac_cfg);
1451         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1452         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1453         writel((u32) (val64), add);
1454         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1455         writel((u32) (val64 >> 32), (add + 4));
1456         val64 = readq(&bar0->mac_cfg);
1457
1458         /*
1459          * Set the time value to be inserted in the pause frame
1460          * generated by xena.
1461          */
1462         val64 = readq(&bar0->rmac_pause_cfg);
1463         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1464         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1465         writeq(val64, &bar0->rmac_pause_cfg);
1466
1467         /*
1468          * Set the Threshold Limit for Generating the pause frame
1469          * If the amount of data in any Queue exceeds ratio of
1470          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1471          * pause frame is generated
1472          */
1473         val64 = 0;
1474         for (i = 0; i < 4; i++) {
1475                 val64 |=
1476                     (((u64) 0xFF00 | nic->mac_control.
1477                       mc_pause_threshold_q0q3)
1478                      << (i * 2 * 8));
1479         }
1480         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1481
1482         val64 = 0;
1483         for (i = 0; i < 4; i++) {
1484                 val64 |=
1485                     (((u64) 0xFF00 | nic->mac_control.
1486                       mc_pause_threshold_q4q7)
1487                      << (i * 2 * 8));
1488         }
1489         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1490
1491         /*
1492          * TxDMA will stop Read request if the number of read split has
1493          * exceeded the limit pointed by shared_splits
1494          */
1495         val64 = readq(&bar0->pic_control);
1496         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1497         writeq(val64, &bar0->pic_control);
1498
1499         /*
1500          * Programming the Herc to split every write transaction
1501          * that does not start on an ADB to reduce disconnects.
1502          */
1503         if (nic->device_type == XFRAME_II_DEVICE) {
1504                 val64 = WREQ_SPLIT_MASK_SET_MASK(255);
1505                 writeq(val64, &bar0->wreq_split_mask);
1506         }
1507
1508         /* Setting Link stability period to 64 ms */ 
1509         if (nic->device_type == XFRAME_II_DEVICE) {
1510                 val64 = MISC_LINK_STABILITY_PRD(3);
1511                 writeq(val64, &bar0->misc_control);
1512         }
1513
1514         return SUCCESS;
1515 }
1516 #define LINK_UP_DOWN_INTERRUPT          1
1517 #define MAC_RMAC_ERR_TIMER              2
1518
1519 int s2io_link_fault_indication(nic_t *nic)
1520 {
1521         if (nic->intr_type != INTA)
1522                 return MAC_RMAC_ERR_TIMER;
1523         if (nic->device_type == XFRAME_II_DEVICE)
1524                 return LINK_UP_DOWN_INTERRUPT;
1525         else
1526                 return MAC_RMAC_ERR_TIMER;
1527 }
1528
1529 /**
1530  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1531  *  @nic: device private variable,
1532  *  @mask: A mask indicating which Intr block must be modified and,
1533  *  @flag: A flag indicating whether to enable or disable the Intrs.
1534  *  Description: This function will either disable or enable the interrupts
1535  *  depending on the flag argument. The mask argument can be used to
1536  *  enable/disable any Intr block.
1537  *  Return Value: NONE.
1538  */
1539
1540 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1541 {
1542         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1543         register u64 val64 = 0, temp64 = 0;
1544
1545         /*  Top level interrupt classification */
1546         /*  PIC Interrupts */
1547         if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1548                 /*  Enable PIC Intrs in the general intr mask register */
1549                 val64 = TXPIC_INT_M | PIC_RX_INT_M;
1550                 if (flag == ENABLE_INTRS) {
1551                         temp64 = readq(&bar0->general_int_mask);
1552                         temp64 &= ~((u64) val64);
1553                         writeq(temp64, &bar0->general_int_mask);
1554                         /*
1555                          * If Hercules adapter enable GPIO otherwise
1556                          * disabled all PCIX, Flash, MDIO, IIC and GPIO
1557                          * interrupts for now.
1558                          * TODO
1559                          */
1560                         if (s2io_link_fault_indication(nic) ==
1561                                         LINK_UP_DOWN_INTERRUPT ) {
1562                                 temp64 = readq(&bar0->pic_int_mask);
1563                                 temp64 &= ~((u64) PIC_INT_GPIO);
1564                                 writeq(temp64, &bar0->pic_int_mask);
1565                                 temp64 = readq(&bar0->gpio_int_mask);
1566                                 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1567                                 writeq(temp64, &bar0->gpio_int_mask);
1568                         } else {
1569                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1570                         }
1571                         /*
1572                          * No MSI Support is available presently, so TTI and
1573                          * RTI interrupts are also disabled.
1574                          */
1575                 } else if (flag == DISABLE_INTRS) {
1576                         /*
1577                          * Disable PIC Intrs in the general
1578                          * intr mask register
1579                          */
1580                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1581                         temp64 = readq(&bar0->general_int_mask);
1582                         val64 |= temp64;
1583                         writeq(val64, &bar0->general_int_mask);
1584                 }
1585         }
1586
1587         /*  DMA Interrupts */
1588         /*  Enabling/Disabling Tx DMA interrupts */
1589         if (mask & TX_DMA_INTR) {
1590                 /* Enable TxDMA Intrs in the general intr mask register */
1591                 val64 = TXDMA_INT_M;
1592                 if (flag == ENABLE_INTRS) {
1593                         temp64 = readq(&bar0->general_int_mask);
1594                         temp64 &= ~((u64) val64);
1595                         writeq(temp64, &bar0->general_int_mask);
1596                         /*
1597                          * Keep all interrupts other than PFC interrupt
1598                          * and PCC interrupt disabled in DMA level.
1599                          */
1600                         val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
1601                                                       TXDMA_PCC_INT_M);
1602                         writeq(val64, &bar0->txdma_int_mask);
1603                         /*
1604                          * Enable only the MISC error 1 interrupt in PFC block
1605                          */
1606                         val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
1607                         writeq(val64, &bar0->pfc_err_mask);
1608                         /*
1609                          * Enable only the FB_ECC error interrupt in PCC block
1610                          */
1611                         val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
1612                         writeq(val64, &bar0->pcc_err_mask);
1613                 } else if (flag == DISABLE_INTRS) {
1614                         /*
1615                          * Disable TxDMA Intrs in the general intr mask
1616                          * register
1617                          */
1618                         writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
1619                         writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
1620                         temp64 = readq(&bar0->general_int_mask);
1621                         val64 |= temp64;
1622                         writeq(val64, &bar0->general_int_mask);
1623                 }
1624         }
1625
1626         /*  Enabling/Disabling Rx DMA interrupts */
1627         if (mask & RX_DMA_INTR) {
1628                 /*  Enable RxDMA Intrs in the general intr mask register */
1629                 val64 = RXDMA_INT_M;
1630                 if (flag == ENABLE_INTRS) {
1631                         temp64 = readq(&bar0->general_int_mask);
1632                         temp64 &= ~((u64) val64);
1633                         writeq(temp64, &bar0->general_int_mask);
1634                         /*
1635                          * All RxDMA block interrupts are disabled for now
1636                          * TODO
1637                          */
1638                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1639                 } else if (flag == DISABLE_INTRS) {
1640                         /*
1641                          * Disable RxDMA Intrs in the general intr mask
1642                          * register
1643                          */
1644                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1645                         temp64 = readq(&bar0->general_int_mask);
1646                         val64 |= temp64;
1647                         writeq(val64, &bar0->general_int_mask);
1648                 }
1649         }
1650
1651         /*  MAC Interrupts */
1652         /*  Enabling/Disabling MAC interrupts */
1653         if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1654                 val64 = TXMAC_INT_M | RXMAC_INT_M;
1655                 if (flag == ENABLE_INTRS) {
1656                         temp64 = readq(&bar0->general_int_mask);
1657                         temp64 &= ~((u64) val64);
1658                         writeq(temp64, &bar0->general_int_mask);
1659                         /*
1660                          * All MAC block error interrupts are disabled for now
1661                          * TODO
1662                          */
1663                 } else if (flag == DISABLE_INTRS) {
1664                         /*
1665                          * Disable MAC Intrs in the general intr mask register
1666                          */
1667                         writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1668                         writeq(DISABLE_ALL_INTRS,
1669                                &bar0->mac_rmac_err_mask);
1670
1671                         temp64 = readq(&bar0->general_int_mask);
1672                         val64 |= temp64;
1673                         writeq(val64, &bar0->general_int_mask);
1674                 }
1675         }
1676
1677         /*  XGXS Interrupts */
1678         if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {
1679                 val64 = TXXGXS_INT_M | RXXGXS_INT_M;
1680                 if (flag == ENABLE_INTRS) {
1681                         temp64 = readq(&bar0->general_int_mask);
1682                         temp64 &= ~((u64) val64);
1683                         writeq(temp64, &bar0->general_int_mask);
1684                         /*
1685                          * All XGXS block error interrupts are disabled for now
1686                          * TODO
1687                          */
1688                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1689                 } else if (flag == DISABLE_INTRS) {
1690                         /*
1691                          * Disable MC Intrs in the general intr mask register
1692                          */
1693                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1694                         temp64 = readq(&bar0->general_int_mask);
1695                         val64 |= temp64;
1696                         writeq(val64, &bar0->general_int_mask);
1697                 }
1698         }
1699
1700         /*  Memory Controller(MC) interrupts */
1701         if (mask & MC_INTR) {
1702                 val64 = MC_INT_M;
1703                 if (flag == ENABLE_INTRS) {
1704                         temp64 = readq(&bar0->general_int_mask);
1705                         temp64 &= ~((u64) val64);
1706                         writeq(temp64, &bar0->general_int_mask);
1707                         /*
1708                          * Enable all MC Intrs.
1709                          */
1710                         writeq(0x0, &bar0->mc_int_mask);
1711                         writeq(0x0, &bar0->mc_err_mask);
1712                 } else if (flag == DISABLE_INTRS) {
1713                         /*
1714                          * Disable MC Intrs in the general intr mask register
1715                          */
1716                         writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1717                         temp64 = readq(&bar0->general_int_mask);
1718                         val64 |= temp64;
1719                         writeq(val64, &bar0->general_int_mask);
1720                 }
1721         }
1722
1723
1724         /*  Tx traffic interrupts */
1725         if (mask & TX_TRAFFIC_INTR) {
1726                 val64 = TXTRAFFIC_INT_M;
1727                 if (flag == ENABLE_INTRS) {
1728                         temp64 = readq(&bar0->general_int_mask);
1729                         temp64 &= ~((u64) val64);
1730                         writeq(temp64, &bar0->general_int_mask);
1731                         /*
1732                          * Enable all the Tx side interrupts
1733                          * writing 0 Enables all 64 TX interrupt levels
1734                          */
1735                         writeq(0x0, &bar0->tx_traffic_mask);
1736                 } else if (flag == DISABLE_INTRS) {
1737                         /*
1738                          * Disable Tx Traffic Intrs in the general intr mask
1739                          * register.
1740                          */
1741                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1742                         temp64 = readq(&bar0->general_int_mask);
1743                         val64 |= temp64;
1744                         writeq(val64, &bar0->general_int_mask);
1745                 }
1746         }
1747
1748         /*  Rx traffic interrupts */
1749         if (mask & RX_TRAFFIC_INTR) {
1750                 val64 = RXTRAFFIC_INT_M;
1751                 if (flag == ENABLE_INTRS) {
1752                         temp64 = readq(&bar0->general_int_mask);
1753                         temp64 &= ~((u64) val64);
1754                         writeq(temp64, &bar0->general_int_mask);
1755                         /* writing 0 Enables all 8 RX interrupt levels */
1756                         writeq(0x0, &bar0->rx_traffic_mask);
1757                 } else if (flag == DISABLE_INTRS) {
1758                         /*
1759                          * Disable Rx Traffic Intrs in the general intr mask
1760                          * register.
1761                          */
1762                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1763                         temp64 = readq(&bar0->general_int_mask);
1764                         val64 |= temp64;
1765                         writeq(val64, &bar0->general_int_mask);
1766                 }
1767         }
1768 }
1769
1770 static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc)
1771 {
1772         int ret = 0;
1773
1774         if (flag == FALSE) {
1775                 if ((!herc && (rev_id >= 4)) || herc) {
1776                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1777                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1778                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1779                                 ret = 1;
1780                         }
1781                 }else {
1782                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1783                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1784                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1785                                 ret = 1;
1786                         }
1787                 }
1788         } else {
1789                 if ((!herc && (rev_id >= 4)) || herc) {
1790                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1791                              ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1792                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1793                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1794                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1795                                 ret = 1;
1796                         }
1797                 } else {
1798                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1799                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1800                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1801                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1802                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1803                                 ret = 1;
1804                         }
1805                 }
1806         }
1807
1808         return ret;
1809 }
1810 /**
1811  *  verify_xena_quiescence - Checks whether the H/W is ready
1812  *  @val64 :  Value read from adapter status register.
1813  *  @flag : indicates if the adapter enable bit was ever written once
1814  *  before.
1815  *  Description: Returns whether the H/W is ready to go or not. Depending
1816  *  on whether adapter enable bit was written or not the comparison
1817  *  differs and the calling function passes the input argument flag to
1818  *  indicate this.
1819  *  Return: 1 If xena is quiescence
1820  *          0 If Xena is not quiescence
1821  */
1822
1823 static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag)
1824 {
1825         int ret = 0, herc;
1826         u64 tmp64 = ~((u64) val64);
1827         int rev_id = get_xena_rev_id(sp->pdev);
1828
1829         herc = (sp->device_type == XFRAME_II_DEVICE);
1830         if (!
1831             (tmp64 &
1832              (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY |
1833               ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY |
1834               ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
1835               ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
1836               ADAPTER_STATUS_P_PLL_LOCK))) {
1837                 ret = check_prc_pcc_state(val64, flag, rev_id, herc);
1838         }
1839
1840         return ret;
1841 }
1842
1843 /**
1844  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
1845  * @sp: Pointer to device specifc structure
1846  * Description :
1847  * New procedure to clear mac address reading  problems on Alpha platforms
1848  *
1849  */
1850
1851 void fix_mac_address(nic_t * sp)
1852 {
1853         XENA_dev_config_t __iomem *bar0 = sp->bar0;
1854         u64 val64;
1855         int i = 0;
1856
1857         while (fix_mac[i] != END_SIGN) {
1858                 writeq(fix_mac[i++], &bar0->gpio_control);
1859                 udelay(10);
1860                 val64 = readq(&bar0->gpio_control);
1861         }
1862 }
1863
1864 /**
1865  *  start_nic - Turns the device on
1866  *  @nic : device private variable.
1867  *  Description:
1868  *  This function actually turns the device on. Before this  function is
1869  *  called,all Registers are configured from their reset states
1870  *  and shared memory is allocated but the NIC is still quiescent. On
1871  *  calling this function, the device interrupts are cleared and the NIC is
1872  *  literally switched on by writing into the adapter control register.
1873  *  Return Value:
1874  *  SUCCESS on success and -1 on failure.
1875  */
1876
1877 static int start_nic(struct s2io_nic *nic)
1878 {
1879         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1880         struct net_device *dev = nic->dev;
1881         register u64 val64 = 0;
1882         u16 interruptible;
1883         u16 subid, i;
1884         mac_info_t *mac_control;
1885         struct config_param *config;
1886
1887         mac_control = &nic->mac_control;
1888         config = &nic->config;
1889
1890         /*  PRC Initialization and configuration */
1891         for (i = 0; i < config->rx_ring_num; i++) {
1892                 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1893                        &bar0->prc_rxd0_n[i]);
1894
1895                 val64 = readq(&bar0->prc_ctrl_n[i]);
1896                 if (nic->config.bimodal)
1897                         val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
1898 #ifndef CONFIG_2BUFF_MODE
1899                 val64 |= PRC_CTRL_RC_ENABLED;
1900 #else
1901                 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
1902 #endif
1903                 writeq(val64, &bar0->prc_ctrl_n[i]);
1904         }
1905
1906 #ifdef CONFIG_2BUFF_MODE
1907         /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
1908         val64 = readq(&bar0->rx_pa_cfg);
1909         val64 |= RX_PA_CFG_IGNORE_L2_ERR;
1910         writeq(val64, &bar0->rx_pa_cfg);
1911 #endif
1912
1913         /*
1914          * Enabling MC-RLDRAM. After enabling the device, we timeout
1915          * for around 100ms, which is approximately the time required
1916          * for the device to be ready for operation.
1917          */
1918         val64 = readq(&bar0->mc_rldram_mrs);
1919         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
1920         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
1921         val64 = readq(&bar0->mc_rldram_mrs);
1922
1923         msleep(100);    /* Delay by around 100 ms. */
1924
1925         /* Enabling ECC Protection. */
1926         val64 = readq(&bar0->adapter_control);
1927         val64 &= ~ADAPTER_ECC_EN;
1928         writeq(val64, &bar0->adapter_control);
1929
1930         /*
1931          * Clearing any possible Link state change interrupts that
1932          * could have popped up just before Enabling the card.
1933          */
1934         val64 = readq(&bar0->mac_rmac_err_reg);
1935         if (val64)
1936                 writeq(val64, &bar0->mac_rmac_err_reg);
1937
1938         /*
1939          * Verify if the device is ready to be enabled, if so enable
1940          * it.
1941          */
1942         val64 = readq(&bar0->adapter_status);
1943         if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
1944                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
1945                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
1946                           (unsigned long long) val64);
1947                 return FAILURE;
1948         }
1949
1950         /*  Enable select interrupts */
1951         if (nic->intr_type != INTA)
1952                 en_dis_able_nic_intrs(nic, ENA_ALL_INTRS, DISABLE_INTRS);
1953         else {
1954                 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
1955                 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
1956                 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
1957                 en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS);
1958         }
1959
1960         /*
1961          * With some switches, link might be already up at this point.
1962          * Because of this weird behavior, when we enable laser,
1963          * we may not get link. We need to handle this. We cannot
1964          * figure out which switch is misbehaving. So we are forced to
1965          * make a global change.
1966          */
1967
1968         /* Enabling Laser. */
1969         val64 = readq(&bar0->adapter_control);
1970         val64 |= ADAPTER_EOI_TX_ON;
1971         writeq(val64, &bar0->adapter_control);
1972
1973         /* SXE-002: Initialize link and activity LED */
1974         subid = nic->pdev->subsystem_device;
1975         if (((subid & 0xFF) >= 0x07) &&
1976             (nic->device_type == XFRAME_I_DEVICE)) {
1977                 val64 = readq(&bar0->gpio_control);
1978                 val64 |= 0x0000800000000000ULL;
1979                 writeq(val64, &bar0->gpio_control);
1980                 val64 = 0x0411040400000000ULL;
1981                 writeq(val64, (void __iomem *)bar0 + 0x2700);
1982         }
1983
1984         /*
1985          * Don't see link state interrupts on certain switches, so
1986          * directly scheduling a link state task from here.
1987          */
1988         schedule_work(&nic->set_link_task);
1989
1990         return SUCCESS;
1991 }
1992
1993 /**
1994  *  free_tx_buffers - Free all queued Tx buffers
1995  *  @nic : device private variable.
1996  *  Description:
1997  *  Free all queued Tx buffers.
1998  *  Return Value: void
1999 */
2000
2001 static void free_tx_buffers(struct s2io_nic *nic)
2002 {
2003         struct net_device *dev = nic->dev;
2004         struct sk_buff *skb;
2005         TxD_t *txdp;
2006         int i, j;
2007         mac_info_t *mac_control;
2008         struct config_param *config;
2009         int cnt = 0, frg_cnt;
2010
2011         mac_control = &nic->mac_control;
2012         config = &nic->config;
2013
2014         for (i = 0; i < config->tx_fifo_num; i++) {
2015                 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2016                         txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
2017                             list_virt_addr;
2018                         skb =
2019                             (struct sk_buff *) ((unsigned long) txdp->
2020                                                 Host_Control);
2021                         if (skb == NULL) {
2022                                 memset(txdp, 0, sizeof(TxD_t) *
2023                                        config->max_txds);
2024                                 continue;
2025                         }
2026                         frg_cnt = skb_shinfo(skb)->nr_frags;
2027                         pci_unmap_single(nic->pdev, (dma_addr_t)
2028                                          txdp->Buffer_Pointer,
2029                                          skb->len - skb->data_len,
2030                                          PCI_DMA_TODEVICE);
2031                         if (frg_cnt) {
2032                                 TxD_t *temp;
2033                                 temp = txdp;
2034                                 txdp++;
2035                                 for (j = 0; j < frg_cnt; j++, txdp++) {
2036                                         skb_frag_t *frag =
2037                                             &skb_shinfo(skb)->frags[j];
2038                                         pci_unmap_page(nic->pdev,
2039                                                        (dma_addr_t)
2040                                                        txdp->
2041                                                        Buffer_Pointer,
2042                                                        frag->size,
2043                                                        PCI_DMA_TODEVICE);
2044                                 }
2045                                 txdp = temp;
2046                         }
2047                         dev_kfree_skb(skb);
2048                         memset(txdp, 0, sizeof(TxD_t) * config->max_txds);
2049                         cnt++;
2050                 }
2051                 DBG_PRINT(INTR_DBG,
2052                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2053                           dev->name, cnt, i);
2054                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2055                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2056         }
2057 }
2058
2059 /**
2060  *   stop_nic -  To stop the nic
2061  *   @nic ; device private variable.
2062  *   Description:
2063  *   This function does exactly the opposite of what the start_nic()
2064  *   function does. This function is called to stop the device.
2065  *   Return Value:
2066  *   void.
2067  */
2068
2069 static void stop_nic(struct s2io_nic *nic)
2070 {
2071         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2072         register u64 val64 = 0;
2073         u16 interruptible, i;
2074         mac_info_t *mac_control;
2075         struct config_param *config;
2076
2077         mac_control = &nic->mac_control;
2078         config = &nic->config;
2079
2080         /*  Disable all interrupts */
2081         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2082         interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2083         interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2084         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2085
2086         /*  Disable PRCs */
2087         for (i = 0; i < config->rx_ring_num; i++) {
2088                 val64 = readq(&bar0->prc_ctrl_n[i]);
2089                 val64 &= ~((u64) PRC_CTRL_RC_ENABLED);
2090                 writeq(val64, &bar0->prc_ctrl_n[i]);
2091         }
2092 }
2093
2094 /**
2095  *  fill_rx_buffers - Allocates the Rx side skbs
2096  *  @nic:  device private variable
2097  *  @ring_no: ring number
2098  *  Description:
2099  *  The function allocates Rx side skbs and puts the physical
2100  *  address of these buffers into the RxD buffer pointers, so that the NIC
2101  *  can DMA the received frame into these locations.
2102  *  The NIC supports 3 receive modes, viz
2103  *  1. single buffer,
2104  *  2. three buffer and
2105  *  3. Five buffer modes.
2106  *  Each mode defines how many fragments the received frame will be split
2107  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2108  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2109  *  is split into 3 fragments. As of now only single buffer mode is
2110  *  supported.
2111  *   Return Value:
2112  *  SUCCESS on success or an appropriate -ve value on failure.
2113  */
2114
2115 int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2116 {
2117         struct net_device *dev = nic->dev;
2118         struct sk_buff *skb;
2119         RxD_t *rxdp;
2120         int off, off1, size, block_no, block_no1;
2121         int offset, offset1;
2122         u32 alloc_tab = 0;
2123         u32 alloc_cnt;
2124         mac_info_t *mac_control;
2125         struct config_param *config;
2126 #ifdef CONFIG_2BUFF_MODE
2127         RxD_t *rxdpnext;
2128         int nextblk;
2129         u64 tmp;
2130         buffAdd_t *ba;
2131         dma_addr_t rxdpphys;
2132 #endif
2133 #ifndef CONFIG_S2IO_NAPI
2134         unsigned long flags;
2135 #endif
2136         RxD_t *first_rxdp = NULL;
2137
2138         mac_control = &nic->mac_control;
2139         config = &nic->config;
2140         alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2141             atomic_read(&nic->rx_bufs_left[ring_no]);
2142         size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2143             HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2144
2145         while (alloc_tab < alloc_cnt) {
2146                 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2147                     block_index;
2148                 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.
2149                     block_index;
2150                 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2151                 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2152 #ifndef CONFIG_2BUFF_MODE
2153                 offset = block_no * (MAX_RXDS_PER_BLOCK + 1) + off;
2154                 offset1 = block_no1 * (MAX_RXDS_PER_BLOCK + 1) + off1;
2155 #else
2156                 offset = block_no * (MAX_RXDS_PER_BLOCK) + off;
2157                 offset1 = block_no1 * (MAX_RXDS_PER_BLOCK) + off1;
2158 #endif
2159
2160                 rxdp = mac_control->rings[ring_no].rx_blocks[block_no].
2161                     block_virt_addr + off;
2162                 if ((offset == offset1) && (rxdp->Host_Control)) {
2163                         DBG_PRINT(INTR_DBG, "%s: Get and Put", dev->name);
2164                         DBG_PRINT(INTR_DBG, " info equated\n");
2165                         goto end;
2166                 }
2167 #ifndef CONFIG_2BUFF_MODE
2168                 if (rxdp->Control_1 == END_OF_BLOCK) {
2169                         mac_control->rings[ring_no].rx_curr_put_info.
2170                             block_index++;
2171                         mac_control->rings[ring_no].rx_curr_put_info.
2172                             block_index %= mac_control->rings[ring_no].block_count;
2173                         block_no = mac_control->rings[ring_no].rx_curr_put_info.
2174                                 block_index;
2175                         off++;
2176                         off %= (MAX_RXDS_PER_BLOCK + 1);
2177                         mac_control->rings[ring_no].rx_curr_put_info.offset =
2178                             off;
2179                         rxdp = (RxD_t *) ((unsigned long) rxdp->Control_2);
2180                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2181                                   dev->name, rxdp);
2182                 }
2183 #ifndef CONFIG_S2IO_NAPI
2184                 spin_lock_irqsave(&nic->put_lock, flags);
2185                 mac_control->rings[ring_no].put_pos =
2186                     (block_no * (MAX_RXDS_PER_BLOCK + 1)) + off;
2187                 spin_unlock_irqrestore(&nic->put_lock, flags);
2188 #endif
2189 #else
2190                 if (rxdp->Host_Control == END_OF_BLOCK) {
2191                         mac_control->rings[ring_no].rx_curr_put_info.
2192                             block_index++;
2193                         mac_control->rings[ring_no].rx_curr_put_info.block_index
2194                             %= mac_control->rings[ring_no].block_count;
2195                         block_no = mac_control->rings[ring_no].rx_curr_put_info
2196                             .block_index;
2197                         off = 0;
2198                         DBG_PRINT(INTR_DBG, "%s: block%d at: 0x%llx\n",
2199                                   dev->name, block_no,
2200                                   (unsigned long long) rxdp->Control_1);
2201                         mac_control->rings[ring_no].rx_curr_put_info.offset =
2202                             off;
2203                         rxdp = mac_control->rings[ring_no].rx_blocks[block_no].
2204                             block_virt_addr;
2205                 }
2206 #ifndef CONFIG_S2IO_NAPI
2207                 spin_lock_irqsave(&nic->put_lock, flags);
2208                 mac_control->rings[ring_no].put_pos = (block_no *
2209                                          (MAX_RXDS_PER_BLOCK + 1)) + off;
2210                 spin_unlock_irqrestore(&nic->put_lock, flags);
2211 #endif
2212 #endif
2213
2214 #ifndef CONFIG_2BUFF_MODE
2215                 if (rxdp->Control_1 & RXD_OWN_XENA)
2216 #else
2217                 if (rxdp->Control_2 & BIT(0))
2218 #endif
2219                 {
2220                         mac_control->rings[ring_no].rx_curr_put_info.
2221                             offset = off;
2222                         goto end;
2223                 }
2224 #ifdef  CONFIG_2BUFF_MODE
2225                 /*
2226                  * RxDs Spanning cache lines will be replenished only
2227                  * if the succeeding RxD is also owned by Host. It
2228                  * will always be the ((8*i)+3) and ((8*i)+6)
2229                  * descriptors for the 48 byte descriptor. The offending
2230                  * decsriptor is of-course the 3rd descriptor.
2231                  */
2232                 rxdpphys = mac_control->rings[ring_no].rx_blocks[block_no].
2233                     block_dma_addr + (off * sizeof(RxD_t));
2234                 if (((u64) (rxdpphys)) % 128 > 80) {
2235                         rxdpnext = mac_control->rings[ring_no].rx_blocks[block_no].
2236                             block_virt_addr + (off + 1);
2237                         if (rxdpnext->Host_Control == END_OF_BLOCK) {
2238                                 nextblk = (block_no + 1) %
2239                                     (mac_control->rings[ring_no].block_count);
2240                                 rxdpnext = mac_control->rings[ring_no].rx_blocks
2241                                     [nextblk].block_virt_addr;
2242                         }
2243                         if (rxdpnext->Control_2 & BIT(0))
2244                                 goto end;
2245                 }
2246 #endif
2247
2248 #ifndef CONFIG_2BUFF_MODE
2249                 skb = dev_alloc_skb(size + NET_IP_ALIGN);
2250 #else
2251                 skb = dev_alloc_skb(dev->mtu + ALIGN_SIZE + BUF0_LEN + 4);
2252 #endif
2253                 if (!skb) {
2254                         DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
2255                         DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
2256                         if (first_rxdp) {
2257                                 wmb();
2258                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2259                         }
2260                         return -ENOMEM;
2261                 }
2262 #ifndef CONFIG_2BUFF_MODE
2263                 skb_reserve(skb, NET_IP_ALIGN);
2264                 memset(rxdp, 0, sizeof(RxD_t));
2265                 rxdp->Buffer0_ptr = pci_map_single
2266                     (nic->pdev, skb->data, size, PCI_DMA_FROMDEVICE);
2267                 rxdp->Control_2 &= (~MASK_BUFFER0_SIZE);
2268                 rxdp->Control_2 |= SET_BUFFER0_SIZE(size);
2269                 rxdp->Host_Control = (unsigned long) (skb);
2270                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2271                         rxdp->Control_1 |= RXD_OWN_XENA;
2272                 off++;
2273                 off %= (MAX_RXDS_PER_BLOCK + 1);
2274                 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2275 #else
2276                 ba = &mac_control->rings[ring_no].ba[block_no][off];
2277                 skb_reserve(skb, BUF0_LEN);
2278                 tmp = ((unsigned long) skb->data & ALIGN_SIZE);
2279                 if (tmp)
2280                         skb_reserve(skb, (ALIGN_SIZE + 1) - tmp);
2281
2282                 memset(rxdp, 0, sizeof(RxD_t));
2283                 rxdp->Buffer2_ptr = pci_map_single
2284                     (nic->pdev, skb->data, dev->mtu + BUF0_LEN + 4,
2285                      PCI_DMA_FROMDEVICE);
2286                 rxdp->Buffer0_ptr =
2287                     pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2288                                    PCI_DMA_FROMDEVICE);
2289                 rxdp->Buffer1_ptr =
2290                     pci_map_single(nic->pdev, ba->ba_1, BUF1_LEN,
2291                                    PCI_DMA_FROMDEVICE);
2292
2293                 rxdp->Control_2 = SET_BUFFER2_SIZE(dev->mtu + 4);
2294                 rxdp->Control_2 |= SET_BUFFER0_SIZE(BUF0_LEN);
2295                 rxdp->Control_2 |= SET_BUFFER1_SIZE(1); /* dummy. */
2296                 rxdp->Control_2 |= BIT(0);      /* Set Buffer_Empty bit. */
2297                 rxdp->Host_Control = (u64) ((unsigned long) (skb));
2298                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2299                         rxdp->Control_1 |= RXD_OWN_XENA;
2300                 off++;
2301                 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2302 #endif
2303                 rxdp->Control_2 |= SET_RXD_MARKER;
2304
2305                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2306                         if (first_rxdp) {
2307                                 wmb();
2308                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2309                         }
2310                         first_rxdp = rxdp;
2311                 }
2312                 atomic_inc(&nic->rx_bufs_left[ring_no]);
2313                 alloc_tab++;
2314         }
2315
2316       end:
2317         /* Transfer ownership of first descriptor to adapter just before
2318          * exiting. Before that, use memory barrier so that ownership
2319          * and other fields are seen by adapter correctly.
2320          */
2321         if (first_rxdp) {
2322                 wmb();
2323                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2324         }
2325
2326         return SUCCESS;
2327 }
2328
2329 /**
2330  *  free_rx_buffers - Frees all Rx buffers
2331  *  @sp: device private variable.
2332  *  Description:
2333  *  This function will free all Rx buffers allocated by host.
2334  *  Return Value:
2335  *  NONE.
2336  */
2337
2338 static void free_rx_buffers(struct s2io_nic *sp)
2339 {
2340         struct net_device *dev = sp->dev;
2341         int i, j, blk = 0, off, buf_cnt = 0;
2342         RxD_t *rxdp;
2343         struct sk_buff *skb;
2344         mac_info_t *mac_control;
2345         struct config_param *config;
2346 #ifdef CONFIG_2BUFF_MODE
2347         buffAdd_t *ba;
2348 #endif
2349
2350         mac_control = &sp->mac_control;
2351         config = &sp->config;
2352
2353         for (i = 0; i < config->rx_ring_num; i++) {
2354                 for (j = 0, blk = 0; j < config->rx_cfg[i].num_rxd; j++) {
2355                         off = j % (MAX_RXDS_PER_BLOCK + 1);
2356                         rxdp = mac_control->rings[i].rx_blocks[blk].
2357                                 block_virt_addr + off;
2358
2359 #ifndef CONFIG_2BUFF_MODE
2360                         if (rxdp->Control_1 == END_OF_BLOCK) {
2361                                 rxdp =
2362                                     (RxD_t *) ((unsigned long) rxdp->
2363                                                Control_2);
2364                                 j++;
2365                                 blk++;
2366                         }
2367 #else
2368                         if (rxdp->Host_Control == END_OF_BLOCK) {
2369                                 blk++;
2370                                 continue;
2371                         }
2372 #endif
2373
2374                         if (!(rxdp->Control_1 & RXD_OWN_XENA)) {
2375                                 memset(rxdp, 0, sizeof(RxD_t));
2376                                 continue;
2377                         }
2378
2379                         skb =
2380                             (struct sk_buff *) ((unsigned long) rxdp->
2381                                                 Host_Control);
2382                         if (skb) {
2383 #ifndef CONFIG_2BUFF_MODE
2384                                 pci_unmap_single(sp->pdev, (dma_addr_t)
2385                                                  rxdp->Buffer0_ptr,
2386                                                  dev->mtu +
2387                                                  HEADER_ETHERNET_II_802_3_SIZE
2388                                                  + HEADER_802_2_SIZE +
2389                                                  HEADER_SNAP_SIZE,
2390                                                  PCI_DMA_FROMDEVICE);
2391 #else
2392                                 ba = &mac_control->rings[i].ba[blk][off];
2393                                 pci_unmap_single(sp->pdev, (dma_addr_t)
2394                                                  rxdp->Buffer0_ptr,
2395                                                  BUF0_LEN,
2396                                                  PCI_DMA_FROMDEVICE);
2397                                 pci_unmap_single(sp->pdev, (dma_addr_t)
2398                                                  rxdp->Buffer1_ptr,
2399                                                  BUF1_LEN,
2400                                                  PCI_DMA_FROMDEVICE);
2401                                 pci_unmap_single(sp->pdev, (dma_addr_t)
2402                                                  rxdp->Buffer2_ptr,
2403                                                  dev->mtu + BUF0_LEN + 4,
2404                                                  PCI_DMA_FROMDEVICE);
2405 #endif
2406                                 dev_kfree_skb(skb);
2407                                 atomic_dec(&sp->rx_bufs_left[i]);
2408                                 buf_cnt++;
2409                         }
2410                         memset(rxdp, 0, sizeof(RxD_t));
2411                 }
2412                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2413                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2414                 mac_control->rings[i].rx_curr_put_info.offset = 0;
2415                 mac_control->rings[i].rx_curr_get_info.offset = 0;
2416                 atomic_set(&sp->rx_bufs_left[i], 0);
2417                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2418                           dev->name, buf_cnt, i);
2419         }
2420 }
2421
2422 /**
2423  * s2io_poll - Rx interrupt handler for NAPI support
2424  * @dev : pointer to the device structure.
2425  * @budget : The number of packets that were budgeted to be processed
2426  * during  one pass through the 'Poll" function.
2427  * Description:
2428  * Comes into picture only if NAPI support has been incorporated. It does
2429  * the same thing that rx_intr_handler does, but not in a interrupt context
2430  * also It will process only a given number of packets.
2431  * Return value:
2432  * 0 on success and 1 if there are No Rx packets to be processed.
2433  */
2434
2435 #if defined(CONFIG_S2IO_NAPI)
2436 static int s2io_poll(struct net_device *dev, int *budget)
2437 {
2438         nic_t *nic = dev->priv;
2439         int pkt_cnt = 0, org_pkts_to_process;
2440         mac_info_t *mac_control;
2441         struct config_param *config;
2442         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2443         u64 val64;
2444         int i;
2445
2446         atomic_inc(&nic->isr_cnt);
2447         mac_control = &nic->mac_control;
2448         config = &nic->config;
2449
2450         nic->pkts_to_process = *budget;
2451         if (nic->pkts_to_process > dev->quota)
2452                 nic->pkts_to_process = dev->quota;
2453         org_pkts_to_process = nic->pkts_to_process;
2454
2455         val64 = readq(&bar0->rx_traffic_int);
2456         writeq(val64, &bar0->rx_traffic_int);
2457
2458         for (i = 0; i < config->rx_ring_num; i++) {
2459                 rx_intr_handler(&mac_control->rings[i]);
2460                 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2461                 if (!nic->pkts_to_process) {
2462                         /* Quota for the current iteration has been met */
2463                         goto no_rx;
2464                 }
2465         }
2466         if (!pkt_cnt)
2467                 pkt_cnt = 1;
2468
2469         dev->quota -= pkt_cnt;
2470         *budget -= pkt_cnt;
2471         netif_rx_complete(dev);
2472
2473         for (i = 0; i < config->rx_ring_num; i++) {
2474                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2475                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2476                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2477                         break;
2478                 }
2479         }
2480         /* Re enable the Rx interrupts. */
2481         en_dis_able_nic_intrs(nic, RX_TRAFFIC_INTR, ENABLE_INTRS);
2482         atomic_dec(&nic->isr_cnt);
2483         return 0;
2484
2485 no_rx:
2486         dev->quota -= pkt_cnt;
2487         *budget -= pkt_cnt;
2488
2489         for (i = 0; i < config->rx_ring_num; i++) {
2490                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2491                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2492                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2493                         break;
2494                 }
2495         }
2496         atomic_dec(&nic->isr_cnt);
2497         return 1;
2498 }
2499 #endif
2500
2501 /**
2502  *  rx_intr_handler - Rx interrupt handler
2503  *  @nic: device private variable.
2504  *  Description:
2505  *  If the interrupt is because of a received frame or if the
2506  *  receive ring contains fresh as yet un-processed frames,this function is
2507  *  called. It picks out the RxD at which place the last Rx processing had
2508  *  stopped and sends the skb to the OSM's Rx handler and then increments
2509  *  the offset.
2510  *  Return Value:
2511  *  NONE.
2512  */
2513 static void rx_intr_handler(ring_info_t *ring_data)
2514 {
2515         nic_t *nic = ring_data->nic;
2516         struct net_device *dev = (struct net_device *) nic->dev;
2517         int get_block, get_offset, put_block, put_offset, ring_bufs;
2518         rx_curr_get_info_t get_info, put_info;
2519         RxD_t *rxdp;
2520         struct sk_buff *skb;
2521 #ifndef CONFIG_S2IO_NAPI
2522         int pkt_cnt = 0;
2523 #endif
2524         spin_lock(&nic->rx_lock);
2525         if (atomic_read(&nic->card_state) == CARD_DOWN) {
2526                 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
2527                           __FUNCTION__, dev->name);
2528                 spin_unlock(&nic->rx_lock);
2529                 return;
2530         }
2531
2532         get_info = ring_data->rx_curr_get_info;
2533         get_block = get_info.block_index;
2534         put_info = ring_data->rx_curr_put_info;
2535         put_block = put_info.block_index;
2536         ring_bufs = get_info.ring_len+1;
2537         rxdp = ring_data->rx_blocks[get_block].block_virt_addr +
2538                     get_info.offset;
2539         get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
2540                 get_info.offset;
2541 #ifndef CONFIG_S2IO_NAPI
2542         spin_lock(&nic->put_lock);
2543         put_offset = ring_data->put_pos;
2544         spin_unlock(&nic->put_lock);
2545 #else
2546         put_offset = (put_block * (MAX_RXDS_PER_BLOCK + 1)) +
2547                 put_info.offset;
2548 #endif
2549         while (RXD_IS_UP2DT(rxdp) &&
2550                (((get_offset + 1) % ring_bufs) != put_offset)) {
2551                 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2552                 if (skb == NULL) {
2553                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
2554                                   dev->name);
2555                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2556                         spin_unlock(&nic->rx_lock);
2557                         return;
2558                 }
2559 #ifndef CONFIG_2BUFF_MODE
2560                 pci_unmap_single(nic->pdev, (dma_addr_t)
2561                                  rxdp->Buffer0_ptr,
2562                                  dev->mtu +
2563                                  HEADER_ETHERNET_II_802_3_SIZE +
2564                                  HEADER_802_2_SIZE +
2565                                  HEADER_SNAP_SIZE,
2566                                  PCI_DMA_FROMDEVICE);
2567 #else
2568                 pci_unmap_single(nic->pdev, (dma_addr_t)
2569                                  rxdp->Buffer0_ptr,
2570                                  BUF0_LEN, PCI_DMA_FROMDEVICE);
2571                 pci_unmap_single(nic->pdev, (dma_addr_t)
2572                                  rxdp->Buffer1_ptr,
2573                                  BUF1_LEN, PCI_DMA_FROMDEVICE);
2574                 pci_unmap_single(nic->pdev, (dma_addr_t)
2575                                  rxdp->Buffer2_ptr,
2576                                  dev->mtu + BUF0_LEN + 4,
2577                                  PCI_DMA_FROMDEVICE);
2578 #endif
2579                 rx_osm_handler(ring_data, rxdp);
2580                 get_info.offset++;
2581                 ring_data->rx_curr_get_info.offset =
2582                     get_info.offset;
2583                 rxdp = ring_data->rx_blocks[get_block].block_virt_addr +
2584                     get_info.offset;
2585                 if (get_info.offset &&
2586                     (!(get_info.offset % MAX_RXDS_PER_BLOCK))) {
2587                         get_info.offset = 0;
2588                         ring_data->rx_curr_get_info.offset
2589                             = get_info.offset;
2590                         get_block++;
2591                         get_block %= ring_data->block_count;
2592                         ring_data->rx_curr_get_info.block_index
2593                             = get_block;
2594                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2595                 }
2596
2597                 get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
2598                             get_info.offset;
2599 #ifdef CONFIG_S2IO_NAPI
2600                 nic->pkts_to_process -= 1;
2601                 if (!nic->pkts_to_process)
2602                         break;
2603 #else
2604                 pkt_cnt++;
2605                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2606                         break;
2607 #endif
2608         }
2609         spin_unlock(&nic->rx_lock);
2610 }
2611
2612 /**
2613  *  tx_intr_handler - Transmit interrupt handler
2614  *  @nic : device private variable
2615  *  Description:
2616  *  If an interrupt was raised to indicate DMA complete of the
2617  *  Tx packet, this function is called. It identifies the last TxD
2618  *  whose buffer was freed and frees all skbs whose data have already
2619  *  DMA'ed into the NICs internal memory.
2620  *  Return Value:
2621  *  NONE
2622  */
2623
2624 static void tx_intr_handler(fifo_info_t *fifo_data)
2625 {
2626         nic_t *nic = fifo_data->nic;
2627         struct net_device *dev = (struct net_device *) nic->dev;
2628         tx_curr_get_info_t get_info, put_info;
2629         struct sk_buff *skb;
2630         TxD_t *txdlp;
2631         u16 j, frg_cnt;
2632
2633         get_info = fifo_data->tx_curr_get_info;
2634         put_info = fifo_data->tx_curr_put_info;
2635         txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
2636             list_virt_addr;
2637         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2638                (get_info.offset != put_info.offset) &&
2639                (txdlp->Host_Control)) {
2640                 /* Check for TxD errors */
2641                 if (txdlp->Control_1 & TXD_T_CODE) {
2642                         unsigned long long err;
2643                         err = txdlp->Control_1 & TXD_T_CODE;
2644                         if ((err >> 48) == 0xA) {
2645                                 DBG_PRINT(TX_DBG, "TxD returned due \
2646 to loss of link\n");
2647                         }
2648                         else {
2649                                 DBG_PRINT(ERR_DBG, "***TxD error \
2650 %llx\n", err);
2651                         }
2652                 }
2653
2654                 skb = (struct sk_buff *) ((unsigned long)
2655                                 txdlp->Host_Control);
2656                 if (skb == NULL) {
2657                         DBG_PRINT(ERR_DBG, "%s: Null skb ",
2658                         __FUNCTION__);
2659                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2660                         return;
2661                 }
2662
2663                 frg_cnt = skb_shinfo(skb)->nr_frags;
2664                 nic->tx_pkt_count++;
2665
2666                 pci_unmap_single(nic->pdev, (dma_addr_t)
2667                                  txdlp->Buffer_Pointer,
2668                                  skb->len - skb->data_len,
2669                                  PCI_DMA_TODEVICE);
2670                 if (frg_cnt) {
2671                         TxD_t *temp;
2672                         temp = txdlp;
2673                         txdlp++;
2674                         for (j = 0; j < frg_cnt; j++, txdlp++) {
2675                                 skb_frag_t *frag =
2676                                     &skb_shinfo(skb)->frags[j];
2677                                 if (!txdlp->Buffer_Pointer)
2678                                         break;
2679                                 pci_unmap_page(nic->pdev,
2680                                                (dma_addr_t)
2681                                                txdlp->
2682                                                Buffer_Pointer,
2683                                                frag->size,
2684                                                PCI_DMA_TODEVICE);
2685                         }
2686                         txdlp = temp;
2687                 }
2688                 memset(txdlp, 0,
2689                        (sizeof(TxD_t) * fifo_data->max_txds));
2690
2691                 /* Updating the statistics block */
2692                 nic->stats.tx_bytes += skb->len;
2693                 dev_kfree_skb_irq(skb);
2694
2695                 get_info.offset++;
2696                 get_info.offset %= get_info.fifo_len + 1;
2697                 txdlp = (TxD_t *) fifo_data->list_info
2698                     [get_info.offset].list_virt_addr;
2699                 fifo_data->tx_curr_get_info.offset =
2700                     get_info.offset;
2701         }
2702
2703         spin_lock(&nic->tx_lock);
2704         if (netif_queue_stopped(dev))
2705                 netif_wake_queue(dev);
2706         spin_unlock(&nic->tx_lock);
2707 }
2708
2709 /**
2710  *  alarm_intr_handler - Alarm Interrrupt handler
2711  *  @nic: device private variable
2712  *  Description: If the interrupt was neither because of Rx packet or Tx
2713  *  complete, this function is called. If the interrupt was to indicate
2714  *  a loss of link, the OSM link status handler is invoked for any other
2715  *  alarm interrupt the block that raised the interrupt is displayed
2716  *  and a H/W reset is issued.
2717  *  Return Value:
2718  *  NONE
2719 */
2720
2721 static void alarm_intr_handler(struct s2io_nic *nic)
2722 {
2723         struct net_device *dev = (struct net_device *) nic->dev;
2724         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2725         register u64 val64 = 0, err_reg = 0;
2726
2727         /* Handling link status change error Intr */
2728         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2729                 err_reg = readq(&bar0->mac_rmac_err_reg);
2730                 writeq(err_reg, &bar0->mac_rmac_err_reg);
2731                 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
2732                         schedule_work(&nic->set_link_task);
2733                 }
2734         }
2735
2736         /* Handling Ecc errors */
2737         val64 = readq(&bar0->mc_err_reg);
2738         writeq(val64, &bar0->mc_err_reg);
2739         if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
2740                 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
2741                         nic->mac_control.stats_info->sw_stat.
2742                                 double_ecc_errs++;
2743                         DBG_PRINT(INIT_DBG, "%s: Device indicates ",
2744                                   dev->name);
2745                         DBG_PRINT(INIT_DBG, "double ECC error!!\n");
2746                         if (nic->device_type != XFRAME_II_DEVICE) {
2747                                 /* Reset XframeI only if critical error */
2748                                 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
2749                                              MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
2750                                         netif_stop_queue(dev);
2751                                         schedule_work(&nic->rst_timer_task);
2752                                 }
2753                         }
2754                 } else {
2755                         nic->mac_control.stats_info->sw_stat.
2756                                 single_ecc_errs++;
2757                 }
2758         }
2759
2760         /* In case of a serious error, the device will be Reset. */
2761         val64 = readq(&bar0->serr_source);
2762         if (val64 & SERR_SOURCE_ANY) {
2763                 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
2764                 DBG_PRINT(ERR_DBG, "serious error %llx!!\n", 
2765                           (unsigned long long)val64);
2766                 netif_stop_queue(dev);
2767                 schedule_work(&nic->rst_timer_task);
2768         }
2769
2770         /*
2771          * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
2772          * Error occurs, the adapter will be recycled by disabling the
2773          * adapter enable bit and enabling it again after the device
2774          * becomes Quiescent.
2775          */
2776         val64 = readq(&bar0->pcc_err_reg);
2777         writeq(val64, &bar0->pcc_err_reg);
2778         if (val64 & PCC_FB_ECC_DB_ERR) {
2779                 u64 ac = readq(&bar0->adapter_control);
2780                 ac &= ~(ADAPTER_CNTL_EN);
2781                 writeq(ac, &bar0->adapter_control);
2782                 ac = readq(&bar0->adapter_control);
2783                 schedule_work(&nic->set_link_task);
2784         }
2785
2786         /* Other type of interrupts are not being handled now,  TODO */
2787 }
2788
2789 /**
2790  *  wait_for_cmd_complete - waits for a command to complete.
2791  *  @sp : private member of the device structure, which is a pointer to the
2792  *  s2io_nic structure.
2793  *  Description: Function that waits for a command to Write into RMAC
2794  *  ADDR DATA registers to be completed and returns either success or
2795  *  error depending on whether the command was complete or not.
2796  *  Return value:
2797  *   SUCCESS on success and FAILURE on failure.
2798  */
2799
2800 int wait_for_cmd_complete(nic_t * sp)
2801 {
2802         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2803         int ret = FAILURE, cnt = 0;
2804         u64 val64;
2805
2806         while (TRUE) {
2807                 val64 = readq(&bar0->rmac_addr_cmd_mem);
2808                 if (!(val64 & RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
2809                         ret = SUCCESS;
2810                         break;
2811                 }
2812                 msleep(50);
2813                 if (cnt++ > 10)
2814                         break;
2815         }
2816
2817         return ret;
2818 }
2819
2820 /**
2821  *  s2io_reset - Resets the card.
2822  *  @sp : private member of the device structure.
2823  *  Description: Function to Reset the card. This function then also
2824  *  restores the previously saved PCI configuration space registers as
2825  *  the card reset also resets the configuration space.
2826  *  Return value:
2827  *  void.
2828  */
2829
2830 void s2io_reset(nic_t * sp)
2831 {
2832         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2833         u64 val64;
2834         u16 subid, pci_cmd;
2835
2836         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
2837         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
2838
2839         val64 = SW_RESET_ALL;
2840         writeq(val64, &bar0->sw_reset);
2841
2842         /*
2843          * At this stage, if the PCI write is indeed completed, the
2844          * card is reset and so is the PCI Config space of the device.
2845          * So a read cannot be issued at this stage on any of the
2846          * registers to ensure the write into "sw_reset" register
2847          * has gone through.
2848          * Question: Is there any system call that will explicitly force
2849          * all the write commands still pending on the bus to be pushed
2850          * through?
2851          * As of now I'am just giving a 250ms delay and hoping that the
2852          * PCI write to sw_reset register is done by this time.
2853          */
2854         msleep(250);
2855
2856         /* Restore the PCI state saved during initialization. */
2857         pci_restore_state(sp->pdev);
2858         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
2859                                      pci_cmd);
2860         s2io_init_pci(sp);
2861
2862         msleep(250);
2863
2864         /* Set swapper to enable I/O register access */
2865         s2io_set_swapper(sp);
2866
2867         /* Restore the MSIX table entries from local variables */
2868         restore_xmsi_data(sp);
2869
2870         /* Clear certain PCI/PCI-X fields after reset */
2871         if (sp->device_type == XFRAME_II_DEVICE) {
2872                 /* Clear parity err detect bit */
2873                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
2874
2875                 /* Clearing PCIX Ecc status register */
2876                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
2877
2878                 /* Clearing PCI_STATUS error reflected here */
2879                 writeq(BIT(62), &bar0->txpic_int_reg);
2880         }
2881
2882         /* Reset device statistics maintained by OS */
2883         memset(&sp->stats, 0, sizeof (struct net_device_stats));
2884
2885         /* SXE-002: Configure link and activity LED to turn it off */
2886         subid = sp->pdev->subsystem_device;
2887         if (((subid & 0xFF) >= 0x07) &&
2888             (sp->device_type == XFRAME_I_DEVICE)) {
2889                 val64 = readq(&bar0->gpio_control);
2890                 val64 |= 0x0000800000000000ULL;
2891                 writeq(val64, &bar0->gpio_control);
2892                 val64 = 0x0411040400000000ULL;
2893                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2894         }
2895
2896         /*
2897          * Clear spurious ECC interrupts that would have occured on
2898          * XFRAME II cards after reset.
2899          */
2900         if (sp->device_type == XFRAME_II_DEVICE) {
2901                 val64 = readq(&bar0->pcc_err_reg);
2902                 writeq(val64, &bar0->pcc_err_reg);
2903         }
2904
2905         sp->device_enabled_once = FALSE;
2906 }
2907
2908 /**
2909  *  s2io_set_swapper - to set the swapper controle on the card
2910  *  @sp : private member of the device structure,
2911  *  pointer to the s2io_nic structure.
2912  *  Description: Function to set the swapper control on the card
2913  *  correctly depending on the 'endianness' of the system.
2914  *  Return value:
2915  *  SUCCESS on success and FAILURE on failure.
2916  */
2917
2918 int s2io_set_swapper(nic_t * sp)
2919 {
2920         struct net_device *dev = sp->dev;
2921         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2922         u64 val64, valt, valr;
2923
2924         /*
2925          * Set proper endian settings and verify the same by reading
2926          * the PIF Feed-back register.
2927          */
2928
2929         val64 = readq(&bar0->pif_rd_swapper_fb);
2930         if (val64 != 0x0123456789ABCDEFULL) {
2931                 int i = 0;
2932                 u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
2933                                 0x8100008181000081ULL,  /* FE=1, SE=0 */
2934                                 0x4200004242000042ULL,  /* FE=0, SE=1 */
2935                                 0};                     /* FE=0, SE=0 */
2936
2937                 while(i<4) {
2938                         writeq(value[i], &bar0->swapper_ctrl);
2939                         val64 = readq(&bar0->pif_rd_swapper_fb);
2940                         if (val64 == 0x0123456789ABCDEFULL)
2941                                 break;
2942                         i++;
2943                 }
2944                 if (i == 4) {
2945                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
2946                                 dev->name);
2947                         DBG_PRINT(ERR_DBG, "feedback read %llx\n",
2948                                 (unsigned long long) val64);
2949                         return FAILURE;
2950                 }
2951                 valr = value[i];
2952         } else {
2953                 valr = readq(&bar0->swapper_ctrl);
2954         }
2955
2956         valt = 0x0123456789ABCDEFULL;
2957         writeq(valt, &bar0->xmsi_address);
2958         val64 = readq(&bar0->xmsi_address);
2959
2960         if(val64 != valt) {
2961                 int i = 0;
2962                 u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
2963                                 0x0081810000818100ULL,  /* FE=1, SE=0 */
2964                                 0x0042420000424200ULL,  /* FE=0, SE=1 */
2965                                 0};                     /* FE=0, SE=0 */
2966
2967                 while(i<4) {
2968                         writeq((value[i] | valr), &bar0->swapper_ctrl);
2969                         writeq(valt, &bar0->xmsi_address);
2970                         val64 = readq(&bar0->xmsi_address);
2971                         if(val64 == valt)
2972                                 break;
2973                         i++;
2974                 }
2975                 if(i == 4) {
2976                         unsigned long long x = val64;
2977                         DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
2978                         DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
2979                         return FAILURE;
2980                 }
2981         }
2982         val64 = readq(&bar0->swapper_ctrl);
2983         val64 &= 0xFFFF000000000000ULL;
2984
2985 #ifdef  __BIG_ENDIAN
2986         /*
2987          * The device by default set to a big endian format, so a
2988          * big endian driver need not set anything.
2989          */
2990         val64 |= (SWAPPER_CTRL_TXP_FE |
2991                  SWAPPER_CTRL_TXP_SE |
2992                  SWAPPER_CTRL_TXD_R_FE |
2993                  SWAPPER_CTRL_TXD_W_FE |
2994                  SWAPPER_CTRL_TXF_R_FE |
2995                  SWAPPER_CTRL_RXD_R_FE |
2996                  SWAPPER_CTRL_RXD_W_FE |
2997                  SWAPPER_CTRL_RXF_W_FE |
2998                  SWAPPER_CTRL_XMSI_FE |
2999                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3000         if (sp->intr_type == INTA)
3001                 val64 |= SWAPPER_CTRL_XMSI_SE;
3002         writeq(val64, &bar0->swapper_ctrl);
3003 #else
3004         /*
3005          * Initially we enable all bits to make it accessible by the
3006          * driver, then we selectively enable only those bits that
3007          * we want to set.
3008          */
3009         val64 |= (SWAPPER_CTRL_TXP_FE |
3010                  SWAPPER_CTRL_TXP_SE |
3011                  SWAPPER_CTRL_TXD_R_FE |
3012                  SWAPPER_CTRL_TXD_R_SE |
3013                  SWAPPER_CTRL_TXD_W_FE |
3014                  SWAPPER_CTRL_TXD_W_SE |
3015                  SWAPPER_CTRL_TXF_R_FE |
3016                  SWAPPER_CTRL_RXD_R_FE |
3017                  SWAPPER_CTRL_RXD_R_SE |
3018                  SWAPPER_CTRL_RXD_W_FE |
3019                  SWAPPER_CTRL_RXD_W_SE |
3020                  SWAPPER_CTRL_RXF_W_FE |
3021                  SWAPPER_CTRL_XMSI_FE |
3022                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3023         if (sp->intr_type == INTA)
3024                 val64 |= SWAPPER_CTRL_XMSI_SE;
3025         writeq(val64, &bar0->swapper_ctrl);
3026 #endif
3027         val64 = readq(&bar0->swapper_ctrl);
3028
3029         /*
3030          * Verifying if endian settings are accurate by reading a
3031          * feedback register.
3032          */
3033         val64 = readq(&bar0->pif_rd_swapper_fb);
3034         if (val64 != 0x0123456789ABCDEFULL) {
3035                 /* Endian settings are incorrect, calls for another dekko. */
3036                 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3037                           dev->name);
3038                 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3039                           (unsigned long long) val64);
3040                 return FAILURE;
3041         }
3042
3043         return SUCCESS;
3044 }
3045
3046 int wait_for_msix_trans(nic_t *nic, int i)
3047 {
3048         XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
3049         u64 val64;
3050         int ret = 0, cnt = 0;
3051
3052         do {
3053                 val64 = readq(&bar0->xmsi_access);
3054                 if (!(val64 & BIT(15)))
3055                         break;
3056                 mdelay(1);
3057                 cnt++;
3058         } while(cnt < 5);
3059         if (cnt == 5) {
3060                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3061                 ret = 1;
3062         }
3063
3064         return ret;
3065 }
3066
3067 void restore_xmsi_data(nic_t *nic)
3068 {
3069         XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
3070         u64 val64;
3071         int i;
3072
3073         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3074                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3075                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3076                 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3077                 writeq(val64, &bar0->xmsi_access);
3078                 if (wait_for_msix_trans(nic, i)) {
3079                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3080                         continue;
3081                 }
3082         }
3083 }
3084
3085 void store_xmsi_data(nic_t *nic)
3086 {
3087         XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
3088         u64 val64, addr, data;
3089         int i;
3090
3091         /* Store and display */
3092         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3093                 val64 = (BIT(15) | vBIT(i, 26, 6));
3094                 writeq(val64, &bar0->xmsi_access);
3095                 if (wait_for_msix_trans(nic, i)) {
3096                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3097                         continue;
3098                 }
3099                 addr = readq(&bar0->xmsi_address);
3100                 data = readq(&bar0->xmsi_data);
3101                 if (addr && data) {
3102                         nic->msix_info[i].addr = addr;
3103                         nic->msix_info[i].data = data;
3104                 }
3105         }
3106 }
3107
3108 int s2io_enable_msi(nic_t *nic)
3109 {
3110         XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
3111         u16 msi_ctrl, msg_val;
3112         struct config_param *config = &nic->config;
3113         struct net_device *dev = nic->dev;
3114         u64 val64, tx_mat, rx_mat;
3115         int i, err;
3116
3117         val64 = readq(&bar0->pic_control);
3118         val64 &= ~BIT(1);
3119         writeq(val64, &bar0->pic_control);
3120
3121         err = pci_enable_msi(nic->pdev);
3122         if (err) {
3123                 DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
3124                           nic->dev->name);
3125                 return err;
3126         }
3127
3128         /*
3129          * Enable MSI and use MSI-1 in stead of the standard MSI-0
3130          * for interrupt handling.
3131          */
3132         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3133         msg_val ^= 0x1;
3134         pci_write_config_word(nic->pdev, 0x4c, msg_val);
3135         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3136
3137         pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
3138         msi_ctrl |= 0x10;
3139         pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
3140
3141         /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3142         tx_mat = readq(&bar0->tx_mat0_n[0]);
3143         for (i=0; i<config->tx_fifo_num; i++) {
3144                 tx_mat |= TX_MAT_SET(i, 1);
3145         }
3146         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3147
3148         rx_mat = readq(&bar0->rx_mat);
3149         for (i=0; i<config->rx_ring_num; i++) {
3150                 rx_mat |= RX_MAT_SET(i, 1);
3151         }
3152         writeq(rx_mat, &bar0->rx_mat);
3153
3154         dev->irq = nic->pdev->irq;
3155         return 0;
3156 }
3157
3158 int s2io_enable_msi_x(nic_t *nic)
3159 {
3160         XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
3161         u64 tx_mat, rx_mat;
3162         u16 msi_control; /* Temp variable */
3163         int ret, i, j, msix_indx = 1;
3164
3165         nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3166                                GFP_KERNEL);
3167         if (nic->entries == NULL) {
3168                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3169                 return -ENOMEM;
3170         }
3171         memset(nic->entries, 0, MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3172
3173         nic->s2io_entries =
3174                 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3175                                    GFP_KERNEL);
3176         if (nic->s2io_entries == NULL) {
3177                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3178                 kfree(nic->entries);
3179                 return -ENOMEM;
3180         }
3181         memset(nic->s2io_entries, 0,
3182                MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3183
3184         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3185                 nic->entries[i].entry = i;
3186                 nic->s2io_entries[i].entry = i;
3187                 nic->s2io_entries[i].arg = NULL;
3188                 nic->s2io_entries[i].in_use = 0;
3189         }
3190
3191         tx_mat = readq(&bar0->tx_mat0_n[0]);
3192         for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3193                 tx_mat |= TX_MAT_SET(i, msix_indx);
3194                 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3195                 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3196                 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3197         }
3198         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3199
3200         if (!nic->config.bimodal) {
3201                 rx_mat = readq(&bar0->rx_mat);
3202                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3203                         rx_mat |= RX_MAT_SET(j, msix_indx);
3204                         nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3205                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3206                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3207                 }
3208                 writeq(rx_mat, &bar0->rx_mat);
3209         } else {
3210                 tx_mat = readq(&bar0->tx_mat0_n[7]);
3211                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3212                         tx_mat |= TX_MAT_SET(i, msix_indx);
3213                         nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3214                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3215                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3216                 }
3217                 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3218         }
3219
3220         ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
3221         if (ret) {
3222                 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3223                 kfree(nic->entries);
3224                 kfree(nic->s2io_entries);
3225                 nic->entries = NULL;
3226                 nic->s2io_entries = NULL;
3227                 return -ENOMEM;
3228         }
3229
3230         /*
3231          * To enable MSI-X, MSI also needs to be enabled, due to a bug
3232          * in the herc NIC. (Temp change, needs to be removed later)
3233          */
3234         pci_read_config_word(nic->pdev, 0x42, &msi_control);
3235         msi_control |= 0x1; /* Enable MSI */
3236         pci_write_config_word(nic->pdev, 0x42, msi_control);
3237
3238         return 0;
3239 }
3240
3241 /* ********************************************************* *
3242  * Functions defined below concern the OS part of the driver *
3243  * ********************************************************* */
3244
3245 /**
3246  *  s2io_open - open entry point of the driver
3247  *  @dev : pointer to the device structure.
3248  *  Description:
3249  *  This function is the open entry point of the driver. It mainly calls a
3250  *  function to allocate Rx buffers and inserts them into the buffer
3251  *  descriptors and then enables the Rx part of the NIC.
3252  *  Return value:
3253  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3254  *   file on failure.
3255  */
3256
3257 int s2io_open(struct net_device *dev)
3258 {
3259         nic_t *sp = dev->priv;
3260         int err = 0;
3261         int i;
3262         u16 msi_control; /* Temp variable */
3263
3264         /*
3265          * Make sure you have link off by default every time
3266          * Nic is initialized
3267          */
3268         netif_carrier_off(dev);
3269         sp->last_link_state = 0;
3270
3271         /* Initialize H/W and enable interrupts */
3272         if (s2io_card_up(sp)) {
3273                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3274                           dev->name);
3275                 err = -ENODEV;
3276                 goto hw_init_failed;
3277         }
3278
3279         /* Store the values of the MSIX table in the nic_t structure */
3280         store_xmsi_data(sp);
3281
3282         /* After proper initialization of H/W, register ISR */
3283         if (sp->intr_type == MSI) {
3284                 err = request_irq((int) sp->pdev->irq, s2io_msi_handle, 
3285                         SA_SHIRQ, sp->name, dev);
3286                 if (err) {
3287                         DBG_PRINT(ERR_DBG, "%s: MSI registration \
3288 failed\n", dev->name);
3289                         goto isr_registration_failed;
3290                 }
3291         }
3292         if (sp->intr_type == MSI_X) {
3293                 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
3294                         if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
3295                                 sprintf(sp->desc1, "%s:MSI-X-%d-TX",
3296                                         dev->name, i);
3297                                 err = request_irq(sp->entries[i].vector,
3298                                           s2io_msix_fifo_handle, 0, sp->desc1,
3299                                           sp->s2io_entries[i].arg);
3300                                 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc1, 
3301                                                         sp->msix_info[i].addr);
3302                         } else {
3303                                 sprintf(sp->desc2, "%s:MSI-X-%d-RX",
3304                                         dev->name, i);
3305                                 err = request_irq(sp->entries[i].vector,
3306                                           s2io_msix_ring_handle, 0, sp->desc2,
3307                                           sp->s2io_entries[i].arg);
3308                                 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc2, 
3309                                                         sp->msix_info[i].addr);
3310                         }
3311                         if (err) {
3312                                 DBG_PRINT(ERR_DBG, "%s: MSI-X-%d registration \
3313 failed\n", dev->name, i);
3314                                 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
3315                                 goto isr_registration_failed;
3316                         }
3317                         sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
3318                 }
3319         }
3320         if (sp->intr_type == INTA) {
3321                 err = request_irq((int) sp->pdev->irq, s2io_isr, SA_SHIRQ,
3322                                 sp->name, dev);
3323                 if (err) {
3324                         DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
3325                                   dev->name);
3326                         goto isr_registration_failed;
3327                 }
3328         }
3329
3330         if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3331                 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3332                 err = -ENODEV;
3333                 goto setting_mac_address_failed;
3334         }
3335
3336         netif_start_queue(dev);
3337         return 0;
3338
3339 setting_mac_address_failed:
3340         if (sp->intr_type != MSI_X)
3341                 free_irq(sp->pdev->irq, dev);
3342 isr_registration_failed:
3343         del_timer_sync(&sp->alarm_timer);
3344         if (sp->intr_type == MSI_X) {
3345                 if (sp->device_type == XFRAME_II_DEVICE) {
3346                         for (i=1; (sp->s2io_entries[i].in_use == 
3347                                 MSIX_REGISTERED_SUCCESS); i++) {
3348                                 int vector = sp->entries[i].vector;
3349                                 void *arg = sp->s2io_entries[i].arg;
3350
3351                                 free_irq(vector, arg);
3352                         }
3353                         pci_disable_msix(sp->pdev);
3354
3355                         /* Temp */
3356                         pci_read_config_word(sp->pdev, 0x42, &msi_control);
3357                         msi_control &= 0xFFFE; /* Disable MSI */
3358                         pci_write_config_word(sp->pdev, 0x42, msi_control);
3359                 }
3360         }
3361         else if (sp->intr_type == MSI)
3362                 pci_disable_msi(sp->pdev);
3363         s2io_reset(sp);
3364 hw_init_failed:
3365         if (sp->intr_type == MSI_X) {
3366                 if (sp->entries)
3367                         kfree(sp->entries);
3368                 if (sp->s2io_entries)
3369                         kfree(sp->s2io_entries);
3370         }
3371         return err;
3372 }
3373
3374 /**
3375  *  s2io_close -close entry point of the driver
3376  *  @dev : device pointer.
3377  *  Description:
3378  *  This is the stop entry point of the driver. It needs to undo exactly
3379  *  whatever was done by the open entry point,thus it's usually referred to
3380  *  as the close function.Among other things this function mainly stops the
3381  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3382  *  Return value:
3383  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3384  *  file on failure.
3385  */
3386
3387 int s2io_close(struct net_device *dev)
3388 {
3389         nic_t *sp = dev->priv;
3390         int i;
3391         u16 msi_control;
3392
3393         flush_scheduled_work();
3394         netif_stop_queue(dev);
3395         /* Reset card, kill tasklet and free Tx and Rx buffers. */
3396         s2io_card_down(sp);
3397
3398         if (sp->intr_type == MSI_X) {
3399                 if (sp->device_type == XFRAME_II_DEVICE) {
3400                         for (i=1; (sp->s2io_entries[i].in_use == 
3401                                         MSIX_REGISTERED_SUCCESS); i++) {
3402                                 int vector = sp->entries[i].vector;
3403                                 void *arg = sp->s2io_entries[i].arg;
3404
3405                                 free_irq(vector, arg);
3406                         }
3407                         pci_read_config_word(sp->pdev, 0x42, &msi_control);
3408                         msi_control &= 0xFFFE; /* Disable MSI */
3409                         pci_write_config_word(sp->pdev, 0x42, msi_control);
3410
3411                         pci_disable_msix(sp->pdev);
3412                 }
3413         }
3414         else {
3415                 free_irq(sp->pdev->irq, dev);
3416                 if (sp->intr_type == MSI)
3417                         pci_disable_msi(sp->pdev);
3418         }       
3419         sp->device_close_flag = TRUE;   /* Device is shut down. */
3420         return 0;
3421 }
3422
3423 /**
3424  *  s2io_xmit - Tx entry point of te driver
3425  *  @skb : the socket buffer containing the Tx data.
3426  *  @dev : device pointer.
3427  *  Description :
3428  *  This function is the Tx entry point of the driver. S2IO NIC supports
3429  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
3430  *  NOTE: when device cant queue the pkt,just the trans_start variable will
3431  *  not be upadted.
3432  *  Return value:
3433  *  0 on success & 1 on failure.
3434  */
3435
3436 int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3437 {
3438         nic_t *sp = dev->priv;
3439         u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3440         register u64 val64;
3441         TxD_t *txdp;
3442         TxFIFO_element_t __iomem *tx_fifo;
3443         unsigned long flags;
3444 #ifdef NETIF_F_TSO
3445         int mss;
3446 #endif
3447         u16 vlan_tag = 0;
3448         int vlan_priority = 0;
3449         mac_info_t *mac_control;
3450         struct config_param *config;
3451
3452         mac_control = &sp->mac_control;
3453         config = &sp->config;
3454
3455         DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
3456         spin_lock_irqsave(&sp->tx_lock, flags);
3457         if (atomic_read(&sp->card_state) == CARD_DOWN) {
3458                 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
3459                           dev->name);
3460                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3461                 dev_kfree_skb(skb);
3462                 return 0;
3463         }
3464
3465         queue = 0;
3466
3467         /* Get Fifo number to Transmit based on vlan priority */
3468         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3469                 vlan_tag = vlan_tx_tag_get(skb);
3470                 vlan_priority = vlan_tag >> 13;
3471                 queue = config->fifo_mapping[vlan_priority];
3472         }
3473
3474         put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3475         get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
3476         txdp = (TxD_t *) mac_control->fifos[queue].list_info[put_off].
3477                 list_virt_addr;
3478
3479         queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
3480         /* Avoid "put" pointer going beyond "get" pointer */
3481         if (txdp->Host_Control || (((put_off + 1) % queue_len) == get_off)) {
3482                 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3483                 netif_stop_queue(dev);
3484                 dev_kfree_skb(skb);
3485                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3486                 return 0;
3487         }
3488
3489         /* A buffer with no data will be dropped */
3490         if (!skb->len) {
3491                 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3492                 dev_kfree_skb(skb);
3493                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3494                 return 0;
3495         }
3496
3497 #ifdef NETIF_F_TSO
3498         mss = skb_shinfo(skb)->tso_size;
3499         if (mss) {
3500                 txdp->Control_1 |= TXD_TCP_LSO_EN;
3501                 txdp->Control_1 |= TXD_TCP_LSO_MSS(mss);
3502         }
3503 #endif
3504
3505         frg_cnt = skb_shinfo(skb)->nr_frags;
3506         frg_len = skb->len - skb->data_len;
3507
3508         txdp->Buffer_Pointer = pci_map_single
3509             (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
3510         txdp->Host_Control = (unsigned long) skb;
3511         if (skb->ip_summed == CHECKSUM_HW) {
3512                 txdp->Control_2 |=
3513                     (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
3514                      TXD_TX_CKO_UDP_EN);
3515         }
3516
3517         txdp->Control_2 |= config->tx_intr_type;
3518
3519         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3520                 txdp->Control_2 |= TXD_VLAN_ENABLE;
3521                 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
3522         }
3523
3524         txdp->Control_1 |= (TXD_BUFFER0_SIZE(frg_len) |
3525                             TXD_GATHER_CODE_FIRST);
3526         txdp->Control_1 |= TXD_LIST_OWN_XENA;
3527
3528         /* For fragmented SKB. */
3529         for (i = 0; i < frg_cnt; i++) {
3530                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3531                 /* A '0' length fragment will be ignored */
3532                 if (!frag->size)
3533                         continue;
3534                 txdp++;
3535                 txdp->Buffer_Pointer = (u64) pci_map_page
3536                     (sp->pdev, frag->page, frag->page_offset,
3537                      frag->size, PCI_DMA_TODEVICE);
3538                 txdp->Control_1 |= TXD_BUFFER0_SIZE(frag->size);
3539         }
3540         txdp->Control_1 |= TXD_GATHER_CODE_LAST;
3541
3542         tx_fifo = mac_control->tx_FIFO_start[queue];
3543         val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
3544         writeq(val64, &tx_fifo->TxDL_Pointer);
3545
3546         val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
3547                  TX_FIFO_LAST_LIST);
3548
3549 #ifdef NETIF_F_TSO
3550         if (mss)
3551                 val64 |= TX_FIFO_SPECIAL_FUNC;
3552 #endif
3553         writeq(val64, &tx_fifo->List_Control);
3554
3555         mmiowb();
3556
3557         put_off++;
3558         put_off %= mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
3559         mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
3560
3561         /* Avoid "put" pointer going beyond "get" pointer */
3562         if (((put_off + 1) % queue_len) == get_off) {
3563                 DBG_PRINT(TX_DBG,
3564                           "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
3565                           put_off, get_off);
3566                 netif_stop_queue(dev);
3567         }
3568
3569         dev->trans_start = jiffies;
3570         spin_unlock_irqrestore(&sp->tx_lock, flags);
3571
3572         return 0;
3573 }
3574
3575 static void
3576 s2io_alarm_handle(unsigned long data)
3577 {
3578         nic_t *sp = (nic_t *)data;
3579
3580         alarm_intr_handler(sp);
3581         mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
3582 }
3583
3584 static irqreturn_t
3585 s2io_msi_handle(int irq, void *dev_id, struct pt_regs *regs)
3586 {
3587         struct net_device *dev = (struct net_device *) dev_id;
3588         nic_t *sp = dev->priv;
3589         int i;
3590         int ret;
3591         mac_info_t *mac_control;
3592         struct config_param *config;
3593
3594         atomic_inc(&sp->isr_cnt);
3595         mac_control = &sp->mac_control;
3596         config = &sp->config;
3597         DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__);
3598
3599         /* If Intr is because of Rx Traffic */
3600         for (i = 0; i < config->rx_ring_num; i++)
3601                 rx_intr_handler(&mac_control->rings[i]);
3602
3603         /* If Intr is because of Tx Traffic */
3604         for (i = 0; i < config->tx_fifo_num; i++)
3605                 tx_intr_handler(&mac_control->fifos[i]);
3606
3607         /*
3608          * If the Rx buffer count is below the panic threshold then
3609          * reallocate the buffers from the interrupt handler itself,
3610          * else schedule a tasklet to reallocate the buffers.
3611          */
3612         for (i = 0; i < config->rx_ring_num; i++) {
3613                 int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
3614                 int level = rx_buffer_level(sp, rxb_size, i);
3615
3616                 if ((level == PANIC) && (!TASKLET_IN_USE)) {
3617                         DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", dev->name);
3618                         DBG_PRINT(INTR_DBG, "PANIC levels\n");
3619                         if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
3620                                 DBG_PRINT(ERR_DBG, "%s:Out of memory",
3621                                           dev->name);
3622                                 DBG_PRINT(ERR_DBG, " in ISR!!\n");
3623                                 clear_bit(0, (&sp->tasklet_status));
3624                                 atomic_dec(&sp->isr_cnt);
3625                                 return IRQ_HANDLED;
3626                         }
3627                         clear_bit(0, (&sp->tasklet_status));
3628                 } else if (level == LOW) {
3629                         tasklet_schedule(&sp->task);
3630                 }
3631         }
3632
3633         atomic_dec(&sp->isr_cnt);
3634         return IRQ_HANDLED;
3635 }
3636
3637 static irqreturn_t
3638 s2io_msix_ring_handle(int irq, void *dev_id, struct pt_regs *regs)
3639 {
3640         ring_info_t *ring = (ring_info_t *)dev_id;
3641         nic_t *sp = ring->nic;
3642         int rxb_size, level, rng_n;
3643
3644         atomic_inc(&sp->isr_cnt);
3645         rx_intr_handler(ring);
3646
3647         rng_n = ring->ring_no;
3648         rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
3649         level = rx_buffer_level(sp, rxb_size, rng_n);
3650
3651         if ((level == PANIC) && (!TASKLET_IN_USE)) {
3652                 int ret;
3653                 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
3654                 DBG_PRINT(INTR_DBG, "PANIC levels\n");
3655                 if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
3656                         DBG_PRINT(ERR_DBG, "Out of memory in %s",
3657                                   __FUNCTION__);
3658                         clear_bit(0, (&sp->tasklet_status));
3659                         return IRQ_HANDLED;
3660                 }
3661                 clear_bit(0, (&sp->tasklet_status));
3662         } else if (level == LOW) {
3663                 tasklet_schedule(&sp->task);
3664         }
3665         atomic_dec(&sp->isr_cnt);
3666
3667         return IRQ_HANDLED;
3668 }
3669
3670 static irqreturn_t
3671 s2io_msix_fifo_handle(int irq, void *dev_id, struct pt_regs *regs)
3672 {
3673         fifo_info_t *fifo = (fifo_info_t *)dev_id;
3674         nic_t *sp = fifo->nic;
3675
3676         atomic_inc(&sp->isr_cnt);
3677         tx_intr_handler(fifo);
3678         atomic_dec(&sp->isr_cnt);
3679         return IRQ_HANDLED;
3680 }
3681
3682 static void s2io_txpic_intr_handle(nic_t *sp)
3683 {
3684         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3685         u64 val64;
3686
3687         val64 = readq(&bar0->pic_int_status);
3688         if (val64 & PIC_INT_GPIO) {
3689                 val64 = readq(&bar0->gpio_int_reg);
3690                 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
3691                     (val64 & GPIO_INT_REG_LINK_UP)) {
3692                         val64 |=  GPIO_INT_REG_LINK_DOWN;
3693                         val64 |= GPIO_INT_REG_LINK_UP;
3694                         writeq(val64, &bar0->gpio_int_reg);
3695                         goto masking;
3696                 }
3697
3698                 if (((sp->last_link_state == LINK_UP) &&
3699                         (val64 & GPIO_INT_REG_LINK_DOWN)) ||
3700                 ((sp->last_link_state == LINK_DOWN) &&
3701                 (val64 & GPIO_INT_REG_LINK_UP))) {
3702                         val64 = readq(&bar0->gpio_int_mask);
3703                         val64 |=  GPIO_INT_MASK_LINK_DOWN;
3704                         val64 |= GPIO_INT_MASK_LINK_UP;
3705                         writeq(val64, &bar0->gpio_int_mask);
3706                         s2io_set_link((unsigned long)sp);
3707                 }
3708 masking:
3709                 if (sp->last_link_state == LINK_UP) {
3710                         /*enable down interrupt */
3711                         val64 = readq(&bar0->gpio_int_mask);
3712                         /* unmasks link down intr */
3713                         val64 &=  ~GPIO_INT_MASK_LINK_DOWN;
3714                         /* masks link up intr */
3715                         val64 |= GPIO_INT_MASK_LINK_UP;
3716                         writeq(val64, &bar0->gpio_int_mask);
3717                 } else {
3718                         /*enable UP Interrupt */
3719                         val64 = readq(&bar0->gpio_int_mask);
3720                         /* unmasks link up interrupt */
3721                         val64 &= ~GPIO_INT_MASK_LINK_UP;
3722                         /* masks link down interrupt */
3723                         val64 |=  GPIO_INT_MASK_LINK_DOWN;
3724                         writeq(val64, &bar0->gpio_int_mask);
3725                 }
3726         }
3727 }
3728
3729 /**
3730  *  s2io_isr - ISR handler of the device .
3731  *  @irq: the irq of the device.
3732  *  @dev_id: a void pointer to the dev structure of the NIC.
3733  *  @pt_regs: pointer to the registers pushed on the stack.
3734  *  Description:  This function is the ISR handler of the device. It
3735  *  identifies the reason for the interrupt and calls the relevant
3736  *  service routines. As a contongency measure, this ISR allocates the
3737  *  recv buffers, if their numbers are below the panic value which is
3738  *  presently set to 25% of the original number of rcv buffers allocated.
3739  *  Return value:
3740  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
3741  *   IRQ_NONE: will be returned if interrupt is not from our device
3742  */
3743 static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
3744 {
3745         struct net_device *dev = (struct net_device *) dev_id;
3746         nic_t *sp = dev->priv;
3747         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3748         int i;
3749         u64 reason = 0, val64;
3750         mac_info_t *mac_control;
3751         struct config_param *config;
3752
3753         atomic_inc(&sp->isr_cnt);
3754         mac_control = &sp->mac_control;
3755         config = &sp->config;
3756
3757         /*
3758          * Identify the cause for interrupt and call the appropriate
3759          * interrupt handler. Causes for the interrupt could be;
3760          * 1. Rx of packet.
3761          * 2. Tx complete.
3762          * 3. Link down.
3763          * 4. Error in any functional blocks of the NIC.
3764          */
3765         reason = readq(&bar0->general_int_status);
3766
3767         if (!reason) {
3768                 /* The interrupt was not raised by Xena. */
3769                 atomic_dec(&sp->isr_cnt);
3770                 return IRQ_NONE;
3771         }
3772
3773 #ifdef CONFIG_S2IO_NAPI
3774         if (reason & GEN_INTR_RXTRAFFIC) {
3775                 if (netif_rx_schedule_prep(dev)) {
3776                         en_dis_able_nic_intrs(sp, RX_TRAFFIC_INTR,
3777                                               DISABLE_INTRS);
3778                         __netif_rx_schedule(dev);
3779                 }
3780         }
3781 #else
3782         /* If Intr is because of Rx Traffic */
3783         if (reason & GEN_INTR_RXTRAFFIC) {
3784                 /*
3785                  * rx_traffic_int reg is an R1 register, writing all 1's
3786                  * will ensure that the actual interrupt causing bit get's
3787                  * cleared and hence a read can be avoided.
3788                  */
3789                 val64 = 0xFFFFFFFFFFFFFFFFULL;
3790                 writeq(val64, &bar0->rx_traffic_int);
3791                 for (i = 0; i < config->rx_ring_num; i++) {
3792                         rx_intr_handler(&mac_control->rings[i]);
3793                 }
3794         }
3795 #endif
3796
3797         /* If Intr is because of Tx Traffic */
3798         if (reason & GEN_INTR_TXTRAFFIC) {
3799                 /*
3800                  * tx_traffic_int reg is an R1 register, writing all 1's
3801                  * will ensure that the actual interrupt causing bit get's
3802                  * cleared and hence a read can be avoided.
3803                  */
3804                 val64 = 0xFFFFFFFFFFFFFFFFULL;
3805                 writeq(val64, &bar0->tx_traffic_int);
3806
3807                 for (i = 0; i < config->tx_fifo_num; i++)
3808                         tx_intr_handler(&mac_control->fifos[i]);
3809         }
3810
3811         if (reason & GEN_INTR_TXPIC)
3812                 s2io_txpic_intr_handle(sp);
3813         /*
3814          * If the Rx buffer count is below the panic threshold then
3815          * reallocate the buffers from the interrupt handler itself,
3816          * else schedule a tasklet to reallocate the buffers.
3817          */
3818 #ifndef CONFIG_S2IO_NAPI
3819         for (i = 0; i < config->rx_ring_num; i++) {
3820                 int ret;
3821                 int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
3822                 int level = rx_buffer_level(sp, rxb_size, i);
3823
3824                 if ((level == PANIC) && (!TASKLET_IN_USE)) {
3825                         DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", dev->name);
3826                         DBG_PRINT(INTR_DBG, "PANIC levels\n");
3827                         if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
3828                                 DBG_PRINT(ERR_DBG, "%s:Out of memory",
3829                                           dev->name);
3830                                 DBG_PRINT(ERR_DBG, " in ISR!!\n");
3831                                 clear_bit(0, (&sp->tasklet_status));
3832                                 atomic_dec(&sp->isr_cnt);
3833                                 return IRQ_HANDLED;
3834                         }
3835                         clear_bit(0, (&sp->tasklet_status));
3836                 } else if (level == LOW) {
3837                         tasklet_schedule(&sp->task);
3838                 }
3839         }
3840 #endif
3841
3842         atomic_dec(&sp->isr_cnt);
3843         return IRQ_HANDLED;
3844 }
3845
3846 /**
3847  * s2io_updt_stats -
3848  */
3849 static void s2io_updt_stats(nic_t *sp)
3850 {
3851         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3852         u64 val64;
3853         int cnt = 0;
3854
3855         if (atomic_read(&sp->card_state) == CARD_UP) {
3856                 /* Apprx 30us on a 133 MHz bus */
3857                 val64 = SET_UPDT_CLICKS(10) |
3858                         STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
3859                 writeq(val64, &bar0->stat_cfg);
3860                 do {
3861                         udelay(100);
3862                         val64 = readq(&bar0->stat_cfg);
3863                         if (!(val64 & BIT(0)))
3864                                 break;
3865                         cnt++;
3866                         if (cnt == 5)
3867                                 break; /* Updt failed */
3868                 } while(1);
3869         }
3870 }
3871
3872 /**
3873  *  s2io_get_stats - Updates the device statistics structure.
3874  *  @dev : pointer to the device structure.
3875  *  Description:
3876  *  This function updates the device statistics structure in the s2io_nic
3877  *  structure and returns a pointer to the same.
3878  *  Return value:
3879  *  pointer to the updated net_device_stats structure.
3880  */
3881
3882 struct net_device_stats *s2io_get_stats(struct net_device *dev)
3883 {
3884         nic_t *sp = dev->priv;
3885         mac_info_t *mac_control;
3886         struct config_param *config;
3887
3888
3889         mac_control = &sp->mac_control;
3890         config = &sp->config;
3891
3892         /* Configure Stats for immediate updt */
3893         s2io_updt_stats(sp);
3894
3895         sp->stats.tx_packets =
3896                 le32_to_cpu(mac_control->stats_info->tmac_frms);
3897         sp->stats.tx_errors =
3898                 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
3899         sp->stats.rx_errors =
3900                 le32_to_cpu(mac_control->stats_info->rmac_drop_frms);
3901         sp->stats.multicast =
3902                 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
3903         sp->stats.rx_length_errors =
3904                 le32_to_cpu(mac_control->stats_info->rmac_long_frms);
3905
3906         return (&sp->stats);
3907 }
3908
3909 /**
3910  *  s2io_set_multicast - entry point for multicast address enable/disable.
3911  *  @dev : pointer to the device structure
3912  *  Description:
3913  *  This function is a driver entry point which gets called by the kernel
3914  *  whenever multicast addresses must be enabled/disabled. This also gets
3915  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
3916  *  determine, if multicast address must be enabled or if promiscuous mode
3917  *  is to be disabled etc.
3918  *  Return value:
3919  *  void.
3920  */
3921
3922 static void s2io_set_multicast(struct net_device *dev)
3923 {
3924         int i, j, prev_cnt;
3925         struct dev_mc_list *mclist;
3926         nic_t *sp = dev->priv;
3927         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3928         u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
3929             0xfeffffffffffULL;
3930         u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
3931         void __iomem *add;
3932
3933         if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
3934                 /*  Enable all Multicast addresses */
3935                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
3936                        &bar0->rmac_addr_data0_mem);
3937                 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
3938                        &bar0->rmac_addr_data1_mem);
3939                 val64 = RMAC_ADDR_CMD_MEM_WE |
3940                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
3941                     RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
3942                 writeq(val64, &bar0->rmac_addr_cmd_mem);
3943                 /* Wait till command completes */
3944                 wait_for_cmd_complete(sp);
3945
3946                 sp->m_cast_flg = 1;
3947                 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
3948         } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
3949                 /*  Disable all Multicast addresses */
3950                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
3951                        &bar0->rmac_addr_data0_mem);
3952                 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
3953                        &bar0->rmac_addr_data1_mem);
3954                 val64 = RMAC_ADDR_CMD_MEM_WE |
3955                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
3956                     RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
3957                 writeq(val64, &bar0->rmac_addr_cmd_mem);
3958                 /* Wait till command completes */
3959                 wait_for_cmd_complete(sp);
3960
3961                 sp->m_cast_flg = 0;
3962                 sp->all_multi_pos = 0;
3963         }
3964
3965         if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
3966                 /*  Put the NIC into promiscuous mode */
3967                 add = &bar0->mac_cfg;
3968                 val64 = readq(&bar0->mac_cfg);
3969                 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
3970
3971                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
3972                 writel((u32) val64, add);
3973                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
3974                 writel((u32) (val64 >> 32), (add + 4));
3975
3976                 val64 = readq(&bar0->mac_cfg);
3977                 sp->promisc_flg = 1;
3978                 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
3979                           dev->name);
3980         } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
3981                 /*  Remove the NIC from promiscuous mode */
3982                 add = &bar0->mac_cfg;
3983                 val64 = readq(&bar0->mac_cfg);
3984                 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
3985
3986                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
3987                 writel((u32) val64, add);
3988                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
3989                 writel((u32) (val64 >> 32), (add + 4));
3990
3991                 val64 = readq(&bar0->mac_cfg);
3992                 sp->promisc_flg = 0;
3993                 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
3994                           dev->name);
3995         }
3996
3997         /*  Update individual M_CAST address list */
3998         if ((!sp->m_cast_flg) && dev->mc_count) {
3999                 if (dev->mc_count >
4000                     (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4001                         DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4002                                   dev->name);
4003                         DBG_PRINT(ERR_DBG, "can be added, please enable ");
4004                         DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4005                         return;
4006                 }
4007
4008                 prev_cnt = sp->mc_addr_count;
4009                 sp->mc_addr_count = dev->mc_count;
4010
4011                 /* Clear out the previous list of Mc in the H/W. */
4012                 for (i = 0; i < prev_cnt; i++) {
4013                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4014                                &bar0->rmac_addr_data0_mem);
4015                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4016                                 &bar0->rmac_addr_data1_mem);
4017                         val64 = RMAC_ADDR_CMD_MEM_WE |
4018                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4019                             RMAC_ADDR_CMD_MEM_OFFSET
4020                             (MAC_MC_ADDR_START_OFFSET + i);
4021                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4022
4023                         /* Wait for command completes */
4024                         if (wait_for_cmd_complete(sp)) {
4025                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4026                                           dev->name);
4027                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4028                                 return;
4029                         }
4030                 }
4031
4032                 /* Create the new Rx filter list and update the same in H/W. */
4033                 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4034                      i++, mclist = mclist->next) {
4035                         memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4036                                ETH_ALEN);
4037                         for (j = 0; j < ETH_ALEN; j++) {
4038                                 mac_addr |= mclist->dmi_addr[j];
4039                                 mac_addr <<= 8;
4040                         }
4041                         mac_addr >>= 8;
4042                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4043                                &bar0->rmac_addr_data0_mem);
4044                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4045                                 &bar0->rmac_addr_data1_mem);
4046                         val64 = RMAC_ADDR_CMD_MEM_WE |
4047                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4048                             RMAC_ADDR_CMD_MEM_OFFSET
4049                             (i + MAC_MC_ADDR_START_OFFSET);
4050                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4051
4052                         /* Wait for command completes */
4053                         if (wait_for_cmd_complete(sp)) {
4054                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4055                                           dev->name);
4056                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4057                                 return;
4058                         }
4059                 }
4060         }
4061 }
4062
4063 /**
4064  *  s2io_set_mac_addr - Programs the Xframe mac address
4065  *  @dev : pointer to the device structure.
4066  *  @addr: a uchar pointer to the new mac address which is to be set.
4067  *  Description : This procedure will program the Xframe to receive
4068  *  frames with new Mac Address
4069  *  Return value: SUCCESS on success and an appropriate (-)ve integer
4070  *  as defined in errno.h file on failure.
4071  */
4072
4073 int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
4074 {
4075         nic_t *sp = dev->priv;
4076         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4077         register u64 val64, mac_addr = 0;
4078         int i;
4079
4080         /*
4081          * Set the new MAC address as the new unicast filter and reflect this
4082          * change on the device address registered with the OS. It will be
4083          * at offset 0.
4084          */
4085         for (i = 0; i < ETH_ALEN; i++) {
4086                 mac_addr <<= 8;
4087                 mac_addr |= addr[i];
4088         }
4089
4090         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4091                &bar0->rmac_addr_data0_mem);
4092
4093         val64 =
4094             RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4095             RMAC_ADDR_CMD_MEM_OFFSET(0);
4096         writeq(val64, &bar0->rmac_addr_cmd_mem);
4097         /* Wait till command completes */
4098         if (wait_for_cmd_complete(sp)) {
4099                 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4100                 return FAILURE;
4101         }
4102
4103         return SUCCESS;
4104 }
4105
4106 /**
4107  * s2io_ethtool_sset - Sets different link parameters.
4108  * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
4109  * @info: pointer to the structure with parameters given by ethtool to set
4110  * link information.
4111  * Description:
4112  * The function sets different link parameters provided by the user onto
4113  * the NIC.
4114  * Return value:
4115  * 0 on success.
4116 */
4117
4118 static int s2io_ethtool_sset(struct net_device *dev,
4119                              struct ethtool_cmd *info)
4120 {
4121         nic_t *sp = dev->priv;
4122         if ((info->autoneg == AUTONEG_ENABLE) ||
4123             (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4124                 return -EINVAL;
4125         else {
4126                 s2io_close(sp->dev);
4127                 s2io_open(sp->dev);
4128         }
4129
4130         return 0;
4131 }
4132
4133 /**
4134  * s2io_ethtol_gset - Return link specific information.
4135  * @sp : private member of the device structure, pointer to the
4136  *      s2io_nic structure.
4137  * @info : pointer to the structure with parameters given by ethtool
4138  * to return link information.
4139  * Description:
4140  * Returns link specific information like speed, duplex etc.. to ethtool.
4141  * Return value :
4142  * return 0 on success.
4143  */
4144
4145 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4146 {
4147         nic_t *sp = dev->priv;
4148         info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4149         info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4150         info->port = PORT_FIBRE;
4151         /* info->transceiver?? TODO */
4152
4153         if (netif_carrier_ok(sp->dev)) {
4154                 info->speed = 10000;
4155                 info->duplex = DUPLEX_FULL;
4156         } else {
4157                 info->speed = -1;
4158                 info->duplex = -1;
4159         }
4160
4161         info->autoneg = AUTONEG_DISABLE;
4162         return 0;
4163 }
4164
4165 /**
4166  * s2io_ethtool_gdrvinfo - Returns driver specific information.
4167  * @sp : private member of the device structure, which is a pointer to the
4168  * s2io_nic structure.
4169  * @info : pointer to the structure with parameters given by ethtool to
4170  * return driver information.
4171  * Description:
4172  * Returns driver specefic information like name, version etc.. to ethtool.
4173  * Return value:
4174  *  void
4175  */
4176
4177 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4178                                   struct ethtool_drvinfo *info)
4179 {
4180         nic_t *sp = dev->priv;
4181
4182         strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4183         strncpy(info->version, s2io_driver_version, sizeof(info->version));
4184         strncpy(info->fw_version, "", sizeof(info->fw_version));
4185         strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
4186         info->regdump_len = XENA_REG_SPACE;
4187         info->eedump_len = XENA_EEPROM_SPACE;
4188         info->testinfo_len = S2IO_TEST_LEN;
4189         info->n_stats = S2IO_STAT_LEN;
4190 }
4191
4192 /**
4193  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
4194  *  @sp: private member of the device structure, which is a pointer to the
4195  *  s2io_nic structure.
4196  *  @regs : pointer to the structure with parameters given by ethtool for
4197  *  dumping the registers.
4198  *  @reg_space: The input argumnet into which all the registers are dumped.
4199  *  Description:
4200  *  Dumps the entire register space of xFrame NIC into the user given
4201  *  buffer area.
4202  * Return value :
4203  * void .
4204 */
4205
4206 static void s2io_ethtool_gregs(struct net_device *dev,
4207                                struct ethtool_regs *regs, void *space)
4208 {
4209         int i;
4210         u64 reg;
4211         u8 *reg_space = (u8 *) space;
4212         nic_t *sp = dev->priv;
4213
4214         regs->len = XENA_REG_SPACE;
4215         regs->version = sp->pdev->subsystem_device;
4216
4217         for (i = 0; i < regs->len; i += 8) {
4218                 reg = readq(sp->bar0 + i);
4219                 memcpy((reg_space + i), &reg, 8);
4220         }
4221 }
4222
4223 /**
4224  *  s2io_phy_id  - timer function that alternates adapter LED.
4225  *  @data : address of the private member of the device structure, which
4226  *  is a pointer to the s2io_nic structure, provided as an u32.
4227  * Description: This is actually the timer function that alternates the
4228  * adapter LED bit of the adapter control bit to set/reset every time on
4229  * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
4230  *  once every second.
4231 */
4232 static void s2io_phy_id(unsigned long data)
4233 {
4234         nic_t *sp = (nic_t *) data;
4235         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4236         u64 val64 = 0;
4237         u16 subid;
4238
4239         subid = sp->pdev->subsystem_device;
4240         if ((sp->device_type == XFRAME_II_DEVICE) ||
4241                    ((subid & 0xFF) >= 0x07)) {
4242                 val64 = readq(&bar0->gpio_control);
4243                 val64 ^= GPIO_CTRL_GPIO_0;
4244                 writeq(val64, &bar0->gpio_control);
4245         } else {
4246                 val64 = readq(&bar0->adapter_control);
4247                 val64 ^= ADAPTER_LED_ON;
4248                 writeq(val64, &bar0->adapter_control);
4249         }
4250
4251         mod_timer(&sp->id_timer, jiffies + HZ / 2);
4252 }
4253
4254 /**
4255  * s2io_ethtool_idnic - To physically identify the nic on the system.
4256  * @sp : private member of the device structure, which is a pointer to the
4257  * s2io_nic structure.
4258  * @id : pointer to the structure with identification parameters given by
4259  * ethtool.
4260  * Description: Used to physically identify the NIC on the system.
4261  * The Link LED will blink for a time specified by the user for
4262  * identification.
4263  * NOTE: The Link has to be Up to be able to blink the LED. Hence
4264  * identification is possible only if it's link is up.
4265  * Return value:
4266  * int , returns 0 on success
4267  */
4268
4269 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4270 {
4271         u64 val64 = 0, last_gpio_ctrl_val;
4272         nic_t *sp = dev->priv;
4273         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4274         u16 subid;
4275
4276         subid = sp->pdev->subsystem_device;
4277         last_gpio_ctrl_val = readq(&bar0->gpio_control);
4278         if ((sp->device_type == XFRAME_I_DEVICE) &&
4279                 ((subid & 0xFF) < 0x07)) {
4280                 val64 = readq(&bar0->adapter_control);
4281                 if (!(val64 & ADAPTER_CNTL_EN)) {
4282                         printk(KERN_ERR
4283                                "Adapter Link down, cannot blink LED\n");
4284                         return -EFAULT;
4285                 }
4286         }
4287         if (sp->id_timer.function == NULL) {
4288                 init_timer(&sp->id_timer);
4289                 sp->id_timer.function = s2io_phy_id;
4290                 sp->id_timer.data = (unsigned long) sp;
4291         }
4292         mod_timer(&sp->id_timer, jiffies);
4293         if (data)
4294                 msleep_interruptible(data * HZ);
4295         else
4296                 msleep_interruptible(MAX_FLICKER_TIME);
4297         del_timer_sync(&sp->id_timer);
4298
4299         if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
4300                 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
4301                 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4302         }
4303
4304         return 0;
4305 }
4306
4307 /**
4308  * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
4309  * @sp : private member of the device structure, which is a pointer to the
4310  *      s2io_nic structure.
4311  * @ep : pointer to the structure with pause parameters given by ethtool.
4312  * Description:
4313  * Returns the Pause frame generation and reception capability of the NIC.
4314  * Return value:
4315  *  void
4316  */
4317 static void s2io_ethtool_getpause_data(struct net_device *dev,
4318                                        struct ethtool_pauseparam *ep)
4319 {
4320         u64 val64;
4321         nic_t *sp = dev->priv;
4322         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4323
4324         val64 = readq(&bar0->rmac_pause_cfg);
4325         if (val64 & RMAC_PAUSE_GEN_ENABLE)
4326                 ep->tx_pause = TRUE;
4327         if (val64 & RMAC_PAUSE_RX_ENABLE)
4328                 ep->rx_pause = TRUE;
4329         ep->autoneg = FALSE;
4330 }
4331
4332 /**
4333  * s2io_ethtool_setpause_data -  set/reset pause frame generation.
4334  * @sp : private member of the device structure, which is a pointer to the
4335  *      s2io_nic structure.
4336  * @ep : pointer to the structure with pause parameters given by ethtool.
4337  * Description:
4338  * It can be used to set or reset Pause frame generation or reception
4339  * support of the NIC.
4340  * Return value:
4341  * int, returns 0 on Success
4342  */
4343
4344 static int s2io_ethtool_setpause_data(struct net_device *dev,
4345                                struct ethtool_pauseparam *ep)
4346 {
4347         u64 val64;
4348         nic_t *sp = dev->priv;
4349         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4350
4351         val64 = readq(&bar0->rmac_pause_cfg);
4352         if (ep->tx_pause)
4353                 val64 |= RMAC_PAUSE_GEN_ENABLE;
4354         else
4355                 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
4356         if (ep->rx_pause)
4357                 val64 |= RMAC_PAUSE_RX_ENABLE;
4358         else
4359                 val64 &= ~RMAC_PAUSE_RX_ENABLE;
4360         writeq(val64, &bar0->rmac_pause_cfg);
4361         return 0;
4362 }
4363
4364 /**
4365  * read_eeprom - reads 4 bytes of data from user given offset.
4366  * @sp : private member of the device structure, which is a pointer to the
4367  *      s2io_nic structure.
4368  * @off : offset at which the data must be written
4369  * @data : Its an output parameter where the data read at the given
4370  *      offset is stored.
4371  * Description:
4372  * Will read 4 bytes of data from the user given offset and return the
4373  * read data.
4374  * NOTE: Will allow to read only part of the EEPROM visible through the
4375  *   I2C bus.
4376  * Return value:
4377  *  -1 on failure and 0 on success.
4378  */
4379
4380 #define S2IO_DEV_ID             5
4381 static int read_eeprom(nic_t * sp, int off, u64 * data)
4382 {
4383         int ret = -1;
4384         u32 exit_cnt = 0;
4385         u64 val64;
4386         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4387
4388         if (sp->device_type == XFRAME_I_DEVICE) {
4389                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4390                     I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
4391                     I2C_CONTROL_CNTL_START;
4392                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4393
4394                 while (exit_cnt < 5) {
4395                         val64 = readq(&bar0->i2c_control);
4396                         if (I2C_CONTROL_CNTL_END(val64)) {
4397                                 *data = I2C_CONTROL_GET_DATA(val64);
4398                                 ret = 0;
4399                                 break;
4400                         }
4401                         msleep(50);
4402                         exit_cnt++;
4403                 }
4404         }
4405
4406         if (sp->device_type == XFRAME_II_DEVICE) {
4407                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4408                         SPI_CONTROL_BYTECNT(0x3) | 
4409                         SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
4410                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4411                 val64 |= SPI_CONTROL_REQ;
4412                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4413                 while (exit_cnt < 5) {
4414                         val64 = readq(&bar0->spi_control);
4415                         if (val64 & SPI_CONTROL_NACK) {
4416                                 ret = 1;
4417                                 break;
4418                         } else if (val64 & SPI_CONTROL_DONE) {
4419                                 *data = readq(&bar0->spi_data);
4420                                 *data &= 0xffffff;
4421                                 ret = 0;
4422                                 break;
4423                         }
4424                         msleep(50);
4425                         exit_cnt++;
4426                 }
4427         }
4428         return ret;
4429 }
4430
4431 /**
4432  *  write_eeprom - actually writes the relevant part of the data value.
4433  *  @sp : private member of the device structure, which is a pointer to the
4434  *       s2io_nic structure.
4435  *  @off : offset at which the data must be written
4436  *  @data : The data that is to be written
4437  *  @cnt : Number of bytes of the data that are actually to be written into
4438  *  the Eeprom. (max of 3)
4439  * Description:
4440  *  Actually writes the relevant part of the data value into the Eeprom
4441  *  through the I2C bus.
4442  * Return value:
4443  *  0 on success, -1 on failure.
4444  */
4445
4446 static int write_eeprom(nic_t * sp, int off, u64 data, int cnt)
4447 {
4448         int exit_cnt = 0, ret = -1;
4449         u64 val64;
4450         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4451
4452         if (sp->device_type == XFRAME_I_DEVICE) {
4453                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4454                     I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
4455                     I2C_CONTROL_CNTL_START;
4456                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4457
4458                 while (exit_cnt < 5) {
4459                         val64 = readq(&bar0->i2c_control);
4460                         if (I2C_CONTROL_CNTL_END(val64)) {
4461                                 if (!(val64 & I2C_CONTROL_NACK))
4462                                         ret = 0;
4463                                 break;
4464                         }
4465                         msleep(50);
4466                         exit_cnt++;
4467                 }
4468         }
4469
4470         if (sp->device_type == XFRAME_II_DEVICE) {
4471                 int write_cnt = (cnt == 8) ? 0 : cnt;
4472                 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
4473
4474                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4475                         SPI_CONTROL_BYTECNT(write_cnt) | 
4476                         SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
4477                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4478                 val64 |= SPI_CONTROL_REQ;
4479                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4480                 while (exit_cnt < 5) {
4481                         val64 = readq(&bar0->spi_control);
4482                         if (val64 & SPI_CONTROL_NACK) {
4483                                 ret = 1;
4484                                 break;
4485                         } else if (val64 & SPI_CONTROL_DONE) {
4486                                 ret = 0;
4487                                 break;
4488                         }
4489                         msleep(50);
4490                         exit_cnt++;
4491                 }
4492         }
4493         return ret;
4494 }
4495
4496 /**
4497  *  s2io_ethtool_geeprom  - reads the value stored in the Eeprom.
4498  *  @sp : private member of the device structure, which is a pointer to the *       s2io_nic structure.
4499  *  @eeprom : pointer to the user level structure provided by ethtool,
4500  *  containing all relevant information.
4501  *  @data_buf : user defined value to be written into Eeprom.
4502  *  Description: Reads the values stored in the Eeprom at given offset
4503  *  for a given length. Stores these values int the input argument data
4504  *  buffer 'data_buf' and returns these to the caller (ethtool.)
4505  *  Return value:
4506  *  int  0 on success
4507  */
4508
4509 static int s2io_ethtool_geeprom(struct net_device *dev,
4510                          struct ethtool_eeprom *eeprom, u8 * data_buf)
4511 {
4512         u32 i, valid;
4513         u64 data;
4514         nic_t *sp = dev->priv;
4515
4516         eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
4517
4518         if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
4519                 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
4520
4521         for (i = 0; i < eeprom->len; i += 4) {
4522                 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
4523                         DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
4524                         return -EFAULT;
4525                 }
4526                 valid = INV(data);
4527                 memcpy((data_buf + i), &valid, 4);
4528         }
4529         return 0;
4530 }
4531
4532 /**
4533  *  s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
4534  *  @sp : private member of the device structure, which is a pointer to the
4535  *  s2io_nic structure.
4536  *  @eeprom : pointer to the user level structure provided by ethtool,
4537  *  containing all relevant information.
4538  *  @data_buf ; user defined value to be written into Eeprom.
4539  *  Description:
4540  *  Tries to write the user provided value in the Eeprom, at the offset
4541  *  given by the user.
4542  *  Return value:
4543  *  0 on success, -EFAULT on failure.
4544  */
4545
4546 static int s2io_ethtool_seeprom(struct net_device *dev,
4547                                 struct ethtool_eeprom *eeprom,
4548                                 u8 * data_buf)
4549 {
4550         int len = eeprom->len, cnt = 0;
4551         u64 valid = 0, data;
4552         nic_t *sp = dev->priv;
4553
4554         if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
4555                 DBG_PRINT(ERR_DBG,
4556                           "ETHTOOL_WRITE_EEPROM Err: Magic value ");
4557                 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
4558                           eeprom->magic);
4559                 return -EFAULT;
4560         }
4561
4562         while (len) {
4563                 data = (u32) data_buf[cnt] & 0x000000FF;
4564                 if (data) {
4565                         valid = (u32) (data << 24);
4566                 } else
4567                         valid = data;
4568
4569                 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
4570                         DBG_PRINT(ERR_DBG,
4571                                   "ETHTOOL_WRITE_EEPROM Err: Cannot ");
4572                         DBG_PRINT(ERR_DBG,
4573                                   "write into the specified offset\n");
4574                         return -EFAULT;
4575                 }
4576                 cnt++;
4577                 len--;
4578         }
4579
4580         return 0;
4581 }
4582
4583 /**
4584  * s2io_register_test - reads and writes into all clock domains.
4585  * @sp : private member of the device structure, which is a pointer to the
4586  * s2io_nic structure.
4587  * @data : variable that returns the result of each of the test conducted b
4588  * by the driver.
4589  * Description:
4590  * Read and write into all clock domains. The NIC has 3 clock domains,
4591  * see that registers in all the three regions are accessible.
4592  * Return value:
4593  * 0 on success.
4594  */
4595
4596 static int s2io_register_test(nic_t * sp, uint64_t * data)
4597 {
4598         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4599         u64 val64 = 0, exp_val;
4600         int fail = 0;
4601
4602         val64 = readq(&bar0->pif_rd_swapper_fb);
4603         if (val64 != 0x123456789abcdefULL) {
4604                 fail = 1;
4605                 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
4606         }
4607
4608         val64 = readq(&bar0->rmac_pause_cfg);
4609         if (val64 != 0xc000ffff00000000ULL) {
4610                 fail = 1;
4611                 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
4612         }
4613
4614         val64 = readq(&bar0->rx_queue_cfg);
4615         if (sp->device_type == XFRAME_II_DEVICE)
4616                 exp_val = 0x0404040404040404ULL;
4617         else
4618                 exp_val = 0x0808080808080808ULL;
4619         if (val64 != exp_val) {
4620                 fail = 1;
4621                 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
4622         }
4623
4624         val64 = readq(&bar0->xgxs_efifo_cfg);
4625         if (val64 != 0x000000001923141EULL) {
4626                 fail = 1;
4627                 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
4628         }
4629
4630         val64 = 0x5A5A5A5A5A5A5A5AULL;
4631         writeq(val64, &bar0->xmsi_data);
4632         val64 = readq(&bar0->xmsi_data);
4633         if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
4634                 fail = 1;
4635                 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
4636         }
4637
4638         val64 = 0xA5A5A5A5A5A5A5A5ULL;
4639         writeq(val64, &bar0->xmsi_data);
4640         val64 = readq(&bar0->xmsi_data);
4641         if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
4642                 fail = 1;
4643                 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
4644         }
4645
4646         *data = fail;
4647         return fail;
4648 }
4649
4650 /**
4651  * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
4652  * @sp : private member of the device structure, which is a pointer to the
4653  * s2io_nic structure.
4654  * @data:variable that returns the result of each of the test conducted by
4655  * the driver.
4656  * Description:
4657  * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
4658  * register.
4659  * Return value:
4660  * 0 on success.
4661  */
4662
4663 static int s2io_eeprom_test(nic_t * sp, uint64_t * data)
4664 {
4665         int fail = 0;
4666         u64 ret_data, org_4F0, org_7F0;
4667         u8 saved_4F0 = 0, saved_7F0 = 0;
4668         struct net_device *dev = sp->dev;
4669
4670         /* Test Write Error at offset 0 */
4671         /* Note that SPI interface allows write access to all areas
4672          * of EEPROM. Hence doing all negative testing only for Xframe I.
4673          */
4674         if (sp->device_type == XFRAME_I_DEVICE)
4675                 if (!write_eeprom(sp, 0, 0, 3))
4676                         fail = 1;
4677
4678         /* Save current values at offsets 0x4F0 and 0x7F0 */
4679         if (!read_eeprom(sp, 0x4F0, &org_4F0))
4680                 saved_4F0 = 1;
4681         if (!read_eeprom(sp, 0x7F0, &org_7F0))
4682                 saved_7F0 = 1;
4683
4684         /* Test Write at offset 4f0 */
4685         if (write_eeprom(sp, 0x4F0, 0x012345, 3))
4686                 fail = 1;
4687         if (read_eeprom(sp, 0x4F0, &ret_data))
4688                 fail = 1;
4689
4690         if (ret_data != 0x012345) {
4691                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. Data written %llx Data read %llx\n", dev->name, (u64)0x12345, ret_data); 
4692                 fail = 1;
4693         }
4694
4695         /* Reset the EEPROM data go FFFF */
4696         write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
4697
4698         /* Test Write Request Error at offset 0x7c */
4699         if (sp->device_type == XFRAME_I_DEVICE)
4700                 if (!write_eeprom(sp, 0x07C, 0, 3))
4701                         fail = 1;
4702
4703         /* Test Write Request at offset 0x7f0 */
4704         if (write_eeprom(sp, 0x7F0, 0x012345, 3))
4705                 fail = 1;
4706         if (read_eeprom(sp, 0x7F0, &ret_data))
4707                 fail = 1;
4708
4709         if (ret_data != 0x012345) {
4710                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. Data written %llx Data read %llx\n", dev->name, (u64)0x12345, ret_data); 
4711                 fail = 1;
4712         }
4713
4714         /* Reset the EEPROM data go FFFF */
4715         write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
4716
4717         if (sp->device_type == XFRAME_I_DEVICE) {
4718                 /* Test Write Error at offset 0x80 */
4719                 if (!write_eeprom(sp, 0x080, 0, 3))
4720                         fail = 1;
4721
4722                 /* Test Write Error at offset 0xfc */
4723                 if (!write_eeprom(sp, 0x0FC, 0, 3))
4724                         fail = 1;
4725
4726                 /* Test Write Error at offset 0x100 */
4727                 if (!write_eeprom(sp, 0x100, 0, 3))
4728                         fail = 1;
4729
4730                 /* Test Write Error at offset 4ec */
4731                 if (!write_eeprom(sp, 0x4EC, 0, 3))
4732                         fail = 1;
4733         }
4734
4735         /* Restore values at offsets 0x4F0 and 0x7F0 */
4736         if (saved_4F0)
4737                 write_eeprom(sp, 0x4F0, org_4F0, 3);
4738         if (saved_7F0)
4739                 write_eeprom(sp, 0x7F0, org_7F0, 3);
4740
4741         *data = fail;
4742         return fail;
4743 }
4744
4745 /**
4746  * s2io_bist_test - invokes the MemBist test of the card .
4747  * @sp : private member of the device structure, which is a pointer to the
4748  * s2io_nic structure.
4749  * @data:variable that returns the result of each of the test conducted by
4750  * the driver.
4751  * Description:
4752  * This invokes the MemBist test of the card. We give around
4753  * 2 secs time for the Test to complete. If it's still not complete
4754  * within this peiod, we consider that the test failed.
4755  * Return value:
4756  * 0 on success and -1 on failure.
4757  */
4758
4759 static int s2io_bist_test(nic_t * sp, uint64_t * data)
4760 {
4761         u8 bist = 0;
4762         int cnt = 0, ret = -1;
4763
4764         pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
4765         bist |= PCI_BIST_START;
4766         pci_write_config_word(sp->pdev, PCI_BIST, bist);
4767
4768         while (cnt < 20) {
4769                 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
4770                 if (!(bist & PCI_BIST_START)) {
4771                         *data = (bist & PCI_BIST_CODE_MASK);
4772                         ret = 0;
4773                         break;
4774                 }
4775                 msleep(100);
4776                 cnt++;
4777         }
4778
4779         return ret;
4780 }
4781
4782 /**
4783  * s2io-link_test - verifies the link state of the nic
4784  * @sp ; private member of the device structure, which is a pointer to the
4785  * s2io_nic structure.
4786  * @data: variable that returns the result of each of the test conducted by
4787  * the driver.
4788  * Description:
4789  * The function verifies the link state of the NIC and updates the input
4790  * argument 'data' appropriately.
4791  * Return value:
4792  * 0 on success.
4793  */
4794
4795 static int s2io_link_test(nic_t * sp, uint64_t * data)
4796 {
4797         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4798         u64 val64;
4799
4800         val64 = readq(&bar0->adapter_status);
4801         if (val64 & ADAPTER_STATUS_RMAC_LOCAL_FAULT)
4802                 *data = 1;
4803
4804         return 0;
4805 }
4806
4807 /**
4808  * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
4809  * @sp - private member of the device structure, which is a pointer to the
4810  * s2io_nic structure.
4811  * @data - variable that returns the result of each of the test
4812  * conducted by the driver.
4813  * Description:
4814  *  This is one of the offline test that tests the read and write
4815  *  access to the RldRam chip on the NIC.
4816  * Return value:
4817  *  0 on success.
4818  */
4819
4820 static int s2io_rldram_test(nic_t * sp, uint64_t * data)
4821 {
4822         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4823         u64 val64;
4824         int cnt, iteration = 0, test_fail = 0;
4825
4826         val64 = readq(&bar0->adapter_control);
4827         val64 &= ~ADAPTER_ECC_EN;
4828         writeq(val64, &bar0->adapter_control);
4829
4830         val64 = readq(&bar0->mc_rldram_test_ctrl);
4831         val64 |= MC_RLDRAM_TEST_MODE;
4832         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
4833
4834         val64 = readq(&bar0->mc_rldram_mrs);
4835         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
4836         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
4837
4838         val64 |= MC_RLDRAM_MRS_ENABLE;
4839         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
4840
4841         while (iteration < 2) {
4842                 val64 = 0x55555555aaaa0000ULL;
4843                 if (iteration == 1) {
4844                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
4845                 }
4846                 writeq(val64, &bar0->mc_rldram_test_d0);
4847
4848                 val64 = 0xaaaa5a5555550000ULL;
4849                 if (iteration == 1) {
4850                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
4851                 }
4852                 writeq(val64, &bar0->mc_rldram_test_d1);
4853
4854                 val64 = 0x55aaaaaaaa5a0000ULL;
4855                 if (iteration == 1) {
4856                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
4857                 }
4858                 writeq(val64, &bar0->mc_rldram_test_d2);
4859
4860                 val64 = (u64) (0x0000003ffffe0100ULL);
4861                 writeq(val64, &bar0->mc_rldram_test_add);
4862
4863                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
4864                         MC_RLDRAM_TEST_GO;
4865                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
4866
4867                 for (cnt = 0; cnt < 5; cnt++) {
4868                         val64 = readq(&bar0->mc_rldram_test_ctrl);
4869                         if (val64 & MC_RLDRAM_TEST_DONE)
4870                                 break;
4871                         msleep(200);
4872                 }
4873
4874                 if (cnt == 5)
4875                         break;
4876
4877                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
4878                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
4879
4880                 for (cnt = 0; cnt < 5; cnt++) {
4881                         val64 = readq(&bar0->mc_rldram_test_ctrl);
4882                         if (val64 & MC_RLDRAM_TEST_DONE)
4883                                 break;
4884                         msleep(500);
4885                 }
4886
4887                 if (cnt == 5)
4888                         break;
4889
4890                 val64 = readq(&bar0->mc_rldram_test_ctrl);
4891                 if (!(val64 & MC_RLDRAM_TEST_PASS))
4892                         test_fail = 1;
4893
4894                 iteration++;
4895         }
4896
4897         *data = test_fail;
4898
4899         /* Bring the adapter out of test mode */
4900         SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
4901
4902         return test_fail;
4903 }
4904
4905 /**
4906  *  s2io_ethtool_test - conducts 6 tsets to determine the health of card.
4907  *  @sp : private member of the device structure, which is a pointer to the
4908  *  s2io_nic structure.
4909  *  @ethtest : pointer to a ethtool command specific structure that will be
4910  *  returned to the user.
4911  *  @data : variable that returns the result of each of the test
4912  * conducted by the driver.
4913  * Description:
4914  *  This function conducts 6 tests ( 4 offline and 2 online) to determine
4915  *  the health of the card.
4916  * Return value:
4917  *  void
4918  */
4919
4920 static void s2io_ethtool_test(struct net_device *dev,
4921                               struct ethtool_test *ethtest,
4922                               uint64_t * data)
4923 {
4924         nic_t *sp = dev->priv;
4925         int orig_state = netif_running(sp->dev);
4926
4927         if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
4928                 /* Offline Tests. */
4929                 if (orig_state)
4930                         s2io_close(sp->dev);
4931
4932                 if (s2io_register_test(sp, &data[0]))
4933                         ethtest->flags |= ETH_TEST_FL_FAILED;
4934
4935                 s2io_reset(sp);
4936
4937                 if (s2io_rldram_test(sp, &data[3]))
4938                         ethtest->flags |= ETH_TEST_FL_FAILED;
4939
4940                 s2io_reset(sp);
4941
4942                 if (s2io_eeprom_test(sp, &data[1]))
4943                         ethtest->flags |= ETH_TEST_FL_FAILED;
4944
4945                 if (s2io_bist_test(sp, &data[4]))
4946                         ethtest->flags |= ETH_TEST_FL_FAILED;
4947
4948                 if (orig_state)
4949                         s2io_open(sp->dev);
4950
4951                 data[2] = 0;
4952         } else {
4953                 /* Online Tests. */
4954                 if (!orig_state) {
4955                         DBG_PRINT(ERR_DBG,
4956                                   "%s: is not up, cannot run test\n",
4957                                   dev->name);
4958                         data[0] = -1;
4959                         data[1] = -1;
4960                         data[2] = -1;
4961                         data[3] = -1;
4962                         data[4] = -1;
4963                 }
4964
4965                 if (s2io_link_test(sp, &data[2]))
4966                         ethtest->flags |= ETH_TEST_FL_FAILED;
4967
4968                 data[0] = 0;
4969                 data[1] = 0;
4970                 data[3] = 0;
4971                 data[4] = 0;
4972         }
4973 }
4974
4975 static void s2io_get_ethtool_stats(struct net_device *dev,
4976                                    struct ethtool_stats *estats,
4977                                    u64 * tmp_stats)
4978 {
4979         int i = 0;
4980         nic_t *sp = dev->priv;
4981         StatInfo_t *stat_info = sp->mac_control.stats_info;
4982
4983         s2io_updt_stats(sp);
4984         tmp_stats[i++] =
4985                 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32  |
4986                 le32_to_cpu(stat_info->tmac_frms);
4987         tmp_stats[i++] =
4988                 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
4989                 le32_to_cpu(stat_info->tmac_data_octets);
4990         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
4991         tmp_stats[i++] =
4992                 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
4993                 le32_to_cpu(stat_info->tmac_mcst_frms);
4994         tmp_stats[i++] =
4995                 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
4996                 le32_to_cpu(stat_info->tmac_bcst_frms);
4997         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
4998         tmp_stats[i++] =
4999                 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5000                 le32_to_cpu(stat_info->tmac_any_err_frms);
5001         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
5002         tmp_stats[i++] =
5003                 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5004                 le32_to_cpu(stat_info->tmac_vld_ip);
5005         tmp_stats[i++] =
5006                 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5007                 le32_to_cpu(stat_info->tmac_drop_ip);
5008         tmp_stats[i++] =
5009                 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5010                 le32_to_cpu(stat_info->tmac_icmp);
5011         tmp_stats[i++] =
5012                 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5013                 le32_to_cpu(stat_info->tmac_rst_tcp);
5014         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
5015         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5016                 le32_to_cpu(stat_info->tmac_udp);
5017         tmp_stats[i++] =
5018                 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5019                 le32_to_cpu(stat_info->rmac_vld_frms);
5020         tmp_stats[i++] =
5021                 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5022                 le32_to_cpu(stat_info->rmac_data_octets);
5023         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5024         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
5025         tmp_stats[i++] =
5026                 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5027                 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5028         tmp_stats[i++] =
5029                 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5030                 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
5031         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
5032         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5033         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
5034         tmp_stats[i++] =
5035                 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5036                 le32_to_cpu(stat_info->rmac_discarded_frms);
5037         tmp_stats[i++] =
5038                 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5039                 le32_to_cpu(stat_info->rmac_usized_frms);
5040         tmp_stats[i++] =
5041                 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
5042                 le32_to_cpu(stat_info->rmac_osized_frms);
5043         tmp_stats[i++] =
5044                 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
5045                 le32_to_cpu(stat_info->rmac_frag_frms);
5046         tmp_stats[i++] =
5047                 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
5048                 le32_to_cpu(stat_info->rmac_jabber_frms);
5049         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
5050                 le32_to_cpu(stat_info->rmac_ip);
5051         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
5052         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
5053         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
5054                 le32_to_cpu(stat_info->rmac_drop_ip);
5055         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
5056                 le32_to_cpu(stat_info->rmac_icmp);
5057         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
5058         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
5059                 le32_to_cpu(stat_info->rmac_udp);
5060         tmp_stats[i++] =
5061                 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
5062                 le32_to_cpu(stat_info->rmac_err_drp_udp);
5063         tmp_stats[i++] =
5064                 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
5065                 le32_to_cpu(stat_info->rmac_pause_cnt);
5066         tmp_stats[i++] =
5067                 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
5068                 le32_to_cpu(stat_info->rmac_accepted_ip);
5069         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
5070         tmp_stats[i++] = 0;
5071         tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
5072         tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
5073 }
5074
5075 int s2io_ethtool_get_regs_len(struct net_device *dev)
5076 {
5077         return (XENA_REG_SPACE);
5078 }
5079
5080
5081 u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
5082 {
5083         nic_t *sp = dev->priv;
5084
5085         return (sp->rx_csum);
5086 }
5087 int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
5088 {
5089         nic_t *sp = dev->priv;
5090
5091         if (data)
5092                 sp->rx_csum = 1;
5093         else
5094                 sp->rx_csum = 0;
5095
5096         return 0;
5097 }
5098 int s2io_get_eeprom_len(struct net_device *dev)
5099 {
5100         return (XENA_EEPROM_SPACE);
5101 }
5102
5103 int s2io_ethtool_self_test_count(struct net_device *dev)
5104 {
5105         return (S2IO_TEST_LEN);
5106 }
5107 void s2io_ethtool_get_strings(struct net_device *dev,
5108                               u32 stringset, u8 * data)
5109 {
5110         switch (stringset) {
5111         case ETH_SS_TEST:
5112                 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
5113                 break;
5114         case ETH_SS_STATS:
5115                 memcpy(data, &ethtool_stats_keys,
5116                        sizeof(ethtool_stats_keys));
5117         }
5118 }
5119 static int s2io_ethtool_get_stats_count(struct net_device *dev)
5120 {
5121         return (S2IO_STAT_LEN);
5122 }
5123
5124 int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
5125 {
5126         if (data)
5127                 dev->features |= NETIF_F_IP_CSUM;
5128         else
5129                 dev->features &= ~NETIF_F_IP_CSUM;
5130
5131         return 0;
5132 }
5133
5134
5135 static struct ethtool_ops netdev_ethtool_ops = {
5136         .get_settings = s2io_ethtool_gset,
5137         .set_settings = s2io_ethtool_sset,
5138         .get_drvinfo = s2io_ethtool_gdrvinfo,
5139         .get_regs_len = s2io_ethtool_get_regs_len,
5140         .get_regs = s2io_ethtool_gregs,
5141         .get_link = ethtool_op_get_link,
5142         .get_eeprom_len = s2io_get_eeprom_len,
5143         .get_eeprom = s2io_ethtool_geeprom,
5144         .set_eeprom = s2io_ethtool_seeprom,
5145         .get_pauseparam = s2io_ethtool_getpause_data,
5146         .set_pauseparam = s2io_ethtool_setpause_data,
5147         .get_rx_csum = s2io_ethtool_get_rx_csum,
5148         .set_rx_csum = s2io_ethtool_set_rx_csum,
5149         .get_tx_csum = ethtool_op_get_tx_csum,
5150         .set_tx_csum = s2io_ethtool_op_set_tx_csum,
5151         .get_sg = ethtool_op_get_sg,
5152         .set_sg = ethtool_op_set_sg,
5153 #ifdef NETIF_F_TSO
5154         .get_tso = ethtool_op_get_tso,
5155         .set_tso = ethtool_op_set_tso,
5156 #endif
5157         .self_test_count = s2io_ethtool_self_test_count,
5158         .self_test = s2io_ethtool_test,
5159         .get_strings = s2io_ethtool_get_strings,
5160         .phys_id = s2io_ethtool_idnic,
5161         .get_stats_count = s2io_ethtool_get_stats_count,
5162         .get_ethtool_stats = s2io_get_ethtool_stats
5163 };
5164
5165 /**
5166  *  s2io_ioctl - Entry point for the Ioctl
5167  *  @dev :  Device pointer.
5168  *  @ifr :  An IOCTL specefic structure, that can contain a pointer to
5169  *  a proprietary structure used to pass information to the driver.
5170  *  @cmd :  This is used to distinguish between the different commands that
5171  *  can be passed to the IOCTL functions.
5172  *  Description:
5173  *  Currently there are no special functionality supported in IOCTL, hence
5174  *  function always return EOPNOTSUPPORTED
5175  */
5176
5177 int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5178 {
5179         return -EOPNOTSUPP;
5180 }
5181
5182 /**
5183  *  s2io_change_mtu - entry point to change MTU size for the device.
5184  *   @dev : device pointer.
5185  *   @new_mtu : the new MTU size for the device.
5186  *   Description: A driver entry point to change MTU size for the device.
5187  *   Before changing the MTU the device must be stopped.
5188  *  Return value:
5189  *   0 on success and an appropriate (-)ve integer as defined in errno.h
5190  *   file on failure.
5191  */
5192
5193 int s2io_change_mtu(struct net_device *dev, int new_mtu)
5194 {
5195         nic_t *sp = dev->priv;
5196
5197         if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
5198                 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
5199                           dev->name);
5200                 return -EPERM;
5201         }
5202
5203         dev->mtu = new_mtu;
5204         if (netif_running(dev)) {
5205                 s2io_card_down(sp);
5206                 netif_stop_queue(dev);
5207                 if (s2io_card_up(sp)) {
5208                         DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5209                                   __FUNCTION__);
5210                 }
5211                 if (netif_queue_stopped(dev))
5212                         netif_wake_queue(dev);
5213         } else { /* Device is down */
5214                 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5215                 u64 val64 = new_mtu;
5216
5217                 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
5218         }
5219
5220         return 0;
5221 }
5222
5223 /**
5224  *  s2io_tasklet - Bottom half of the ISR.
5225  *  @dev_adr : address of the device structure in dma_addr_t format.
5226  *  Description:
5227  *  This is the tasklet or the bottom half of the ISR. This is
5228  *  an extension of the ISR which is scheduled by the scheduler to be run
5229  *  when the load on the CPU is low. All low priority tasks of the ISR can
5230  *  be pushed into the tasklet. For now the tasklet is used only to
5231  *  replenish the Rx buffers in the Rx buffer descriptors.
5232  *  Return value:
5233  *  void.
5234  */
5235
5236 static void s2io_tasklet(unsigned long dev_addr)
5237 {
5238         struct net_device *dev = (struct net_device *) dev_addr;
5239         nic_t *sp = dev->priv;
5240         int i, ret;
5241         mac_info_t *mac_control;
5242         struct config_param *config;
5243
5244         mac_control = &sp->mac_control;
5245         config = &sp->config;
5246
5247         if (!TASKLET_IN_USE) {
5248                 for (i = 0; i < config->rx_ring_num; i++) {
5249                         ret = fill_rx_buffers(sp, i);
5250                         if (ret == -ENOMEM) {
5251                                 DBG_PRINT(ERR_DBG, "%s: Out of ",
5252                                           dev->name);
5253                                 DBG_PRINT(ERR_DBG, "memory in tasklet\n");
5254                                 break;
5255                         } else if (ret == -EFILL) {
5256                                 DBG_PRINT(ERR_DBG,
5257                                           "%s: Rx Ring %d is full\n",
5258                                           dev->name, i);
5259                                 break;
5260                         }
5261                 }
5262                 clear_bit(0, (&sp->tasklet_status));
5263         }
5264 }
5265
5266 /**
5267  * s2io_set_link - Set the LInk status
5268  * @data: long pointer to device private structue
5269  * Description: Sets the link status for the adapter
5270  */
5271
5272 static void s2io_set_link(unsigned long data)
5273 {
5274         nic_t *nic = (nic_t *) data;
5275         struct net_device *dev = nic->dev;
5276         XENA_dev_config_t __iomem *bar0 = nic->bar0;
5277         register u64 val64;
5278         u16 subid;
5279
5280         if (test_and_set_bit(0, &(nic->link_state))) {
5281                 /* The card is being reset, no point doing anything */
5282                 return;
5283         }
5284
5285         subid = nic->pdev->subsystem_device;
5286         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
5287                 /*
5288                  * Allow a small delay for the NICs self initiated
5289                  * cleanup to complete.
5290                  */
5291                 msleep(100);
5292         }
5293
5294         val64 = readq(&bar0->adapter_status);
5295         if (verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
5296                 if (LINK_IS_UP(val64)) {
5297                         val64 = readq(&bar0->adapter_control);
5298                         val64 |= ADAPTER_CNTL_EN;
5299                         writeq(val64, &bar0->adapter_control);
5300                         if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5301                                                              subid)) {
5302                                 val64 = readq(&bar0->gpio_control);
5303                                 val64 |= GPIO_CTRL_GPIO_0;
5304                                 writeq(val64, &bar0->gpio_control);
5305                                 val64 = readq(&bar0->gpio_control);
5306                         } else {
5307                                 val64 |= ADAPTER_LED_ON;
5308                                 writeq(val64, &bar0->adapter_control);
5309                         }
5310                         if (s2io_link_fault_indication(nic) ==
5311                                                 MAC_RMAC_ERR_TIMER) {
5312                                 val64 = readq(&bar0->adapter_status);
5313                                 if (!LINK_IS_UP(val64)) {
5314                                         DBG_PRINT(ERR_DBG, "%s:", dev->name);
5315                                         DBG_PRINT(ERR_DBG, " Link down");
5316                                         DBG_PRINT(ERR_DBG, "after ");
5317                                         DBG_PRINT(ERR_DBG, "enabling ");
5318                                         DBG_PRINT(ERR_DBG, "device \n");
5319                                 }
5320                         }
5321                         if (nic->device_enabled_once == FALSE) {
5322                                 nic->device_enabled_once = TRUE;
5323                         }
5324                         s2io_link(nic, LINK_UP);
5325                 } else {
5326                         if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5327                                                               subid)) {
5328                                 val64 = readq(&bar0->gpio_control);
5329                                 val64 &= ~GPIO_CTRL_GPIO_0;
5330                                 writeq(val64, &bar0->gpio_control);
5331                                 val64 = readq(&bar0->gpio_control);
5332                         }
5333                         s2io_link(nic, LINK_DOWN);
5334                 }
5335         } else {                /* NIC is not Quiescent. */
5336                 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
5337                 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
5338                 netif_stop_queue(dev);
5339         }
5340         clear_bit(0, &(nic->link_state));
5341 }
5342
5343 static void s2io_card_down(nic_t * sp)
5344 {
5345         int cnt = 0;
5346         XENA_dev_config_t __iomem *bar0 = sp->bar0;
5347         unsigned long flags;
5348         register u64 val64 = 0;
5349
5350         del_timer_sync(&sp->alarm_timer);
5351         /* If s2io_set_link task is executing, wait till it completes. */
5352         while (test_and_set_bit(0, &(sp->link_state))) {
5353                 msleep(50);
5354         }
5355         atomic_set(&sp->card_state, CARD_DOWN);
5356
5357         /* disable Tx and Rx traffic on the NIC */
5358         stop_nic(sp);
5359
5360         /* Kill tasklet. */
5361         tasklet_kill(&sp->task);
5362
5363         /* Check if the device is Quiescent and then Reset the NIC */
5364         do {
5365                 val64 = readq(&bar0->adapter_status);
5366                 if (verify_xena_quiescence(sp, val64, sp->device_enabled_once)) {
5367                         break;
5368                 }
5369
5370                 msleep(50);
5371                 cnt++;
5372                 if (cnt == 10) {
5373                         DBG_PRINT(ERR_DBG,
5374                                   "s2io_close:Device not Quiescent ");
5375                         DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
5376                                   (unsigned long long) val64);
5377                         break;
5378                 }
5379         } while (1);
5380         s2io_reset(sp);
5381
5382         /* Waiting till all Interrupt handlers are complete */
5383         cnt = 0;
5384         do {
5385                 msleep(10);
5386                 if (!atomic_read(&sp->isr_cnt))
5387                         break;
5388                 cnt++;
5389         } while(cnt < 5);
5390
5391         spin_lock_irqsave(&sp->tx_lock, flags);
5392         /* Free all Tx buffers */
5393         free_tx_buffers(sp);
5394         spin_unlock_irqrestore(&sp->tx_lock, flags);
5395
5396         /* Free all Rx buffers */
5397         spin_lock_irqsave(&sp->rx_lock, flags);
5398         free_rx_buffers(sp);
5399         spin_unlock_irqrestore(&sp->rx_lock, flags);
5400
5401         clear_bit(0, &(sp->link_state));
5402 }
5403
5404 static int s2io_card_up(nic_t * sp)
5405 {
5406         int i, ret = 0;
5407         mac_info_t *mac_control;
5408         struct config_param *config;
5409         struct net_device *dev = (struct net_device *) sp->dev;
5410
5411         /* Initialize the H/W I/O registers */
5412         if (init_nic(sp) != 0) {
5413                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
5414                           dev->name);
5415                 return -ENODEV;
5416         }
5417
5418         if (sp->intr_type == MSI)
5419                 ret = s2io_enable_msi(sp);
5420         else if (sp->intr_type == MSI_X)
5421                 ret = s2io_enable_msi_x(sp);
5422         if (ret) {
5423                 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
5424                 sp->intr_type = INTA;
5425         }
5426
5427         /*
5428          * Initializing the Rx buffers. For now we are considering only 1
5429          * Rx ring and initializing buffers into 30 Rx blocks
5430          */
5431         mac_control = &sp->mac_control;
5432         config = &sp->config;
5433
5434         for (i = 0; i < config->rx_ring_num; i++) {
5435                 if ((ret = fill_rx_buffers(sp, i))) {
5436                         DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
5437                                   dev->name);
5438                         s2io_reset(sp);
5439                         free_rx_buffers(sp);
5440                         return -ENOMEM;
5441                 }
5442                 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
5443                           atomic_read(&sp->rx_bufs_left[i]));
5444         }
5445
5446         /* Setting its receive mode */
5447         s2io_set_multicast(dev);
5448
5449         /* Enable tasklet for the device */
5450         tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
5451
5452         /* Enable Rx Traffic and interrupts on the NIC */
5453         if (start_nic(sp)) {
5454                 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
5455                 tasklet_kill(&sp->task);
5456                 s2io_reset(sp);
5457                 free_irq(dev->irq, dev);
5458                 free_rx_buffers(sp);
5459                 return -ENODEV;
5460         }
5461
5462         S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
5463
5464         atomic_set(&sp->card_state, CARD_UP);
5465         return 0;
5466 }
5467
5468 /**
5469  * s2io_restart_nic - Resets the NIC.
5470  * @data : long pointer to the device private structure
5471  * Description:
5472  * This function is scheduled to be run by the s2io_tx_watchdog
5473  * function after 0.5 secs to reset the NIC. The idea is to reduce
5474  * the run time of the watch dog routine which is run holding a
5475  * spin lock.
5476  */
5477
5478 static void s2io_restart_nic(unsigned long data)
5479 {
5480         struct net_device *dev = (struct net_device *) data;
5481         nic_t *sp = dev->priv;
5482
5483         s2io_card_down(sp);
5484         if (s2io_card_up(sp)) {
5485                 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5486                           dev->name);
5487         }
5488         netif_wake_queue(dev);
5489         DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
5490                   dev->name);
5491
5492 }
5493
5494 /**
5495  *  s2io_tx_watchdog - Watchdog for transmit side.
5496  *  @dev : Pointer to net device structure
5497  *  Description:
5498  *  This function is triggered if the Tx Queue is stopped
5499  *  for a pre-defined amount of time when the Interface is still up.
5500  *  If the Interface is jammed in such a situation, the hardware is
5501  *  reset (by s2io_close) and restarted again (by s2io_open) to
5502  *  overcome any problem that might have been caused in the hardware.
5503  *  Return value:
5504  *  void
5505  */
5506
5507 static void s2io_tx_watchdog(struct net_device *dev)
5508 {
5509         nic_t *sp = dev->priv;
5510
5511         if (netif_carrier_ok(dev)) {
5512                 schedule_work(&sp->rst_timer_task);
5513         }
5514 }
5515
5516 /**
5517  *   rx_osm_handler - To perform some OS related operations on SKB.
5518  *   @sp: private member of the device structure,pointer to s2io_nic structure.
5519  *   @skb : the socket buffer pointer.
5520  *   @len : length of the packet
5521  *   @cksum : FCS checksum of the frame.
5522  *   @ring_no : the ring from which this RxD was extracted.
5523  *   Description:
5524  *   This function is called by the Tx interrupt serivce routine to perform
5525  *   some OS related operations on the SKB before passing it to the upper
5526  *   layers. It mainly checks if the checksum is OK, if so adds it to the
5527  *   SKBs cksum variable, increments the Rx packet count and passes the SKB
5528  *   to the upper layer. If the checksum is wrong, it increments the Rx
5529  *   packet error count, frees the SKB and returns error.
5530  *   Return value:
5531  *   SUCCESS on success and -1 on failure.
5532  */
5533 static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
5534 {
5535         nic_t *sp = ring_data->nic;
5536         struct net_device *dev = (struct net_device *) sp->dev;
5537         struct sk_buff *skb = (struct sk_buff *)
5538                 ((unsigned long) rxdp->Host_Control);
5539         int ring_no = ring_data->ring_no;
5540         u16 l3_csum, l4_csum;
5541 #ifdef CONFIG_2BUFF_MODE
5542         int buf0_len = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
5543         int buf2_len = RXD_GET_BUFFER2_SIZE(rxdp->Control_2);
5544         int get_block = ring_data->rx_curr_get_info.block_index;
5545         int get_off = ring_data->rx_curr_get_info.offset;
5546         buffAdd_t *ba = &ring_data->ba[get_block][get_off];
5547         unsigned char *buff;
5548 #else
5549         u16 len = (u16) ((RXD_GET_BUFFER0_SIZE(rxdp->Control_2)) >> 48);;
5550 #endif
5551         skb->dev = dev;
5552         if (rxdp->Control_1 & RXD_T_CODE) {
5553                 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
5554                 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
5555                           dev->name, err);
5556                 dev_kfree_skb(skb);
5557                 sp->stats.rx_crc_errors++;
5558                 atomic_dec(&sp->rx_bufs_left[ring_no]);
5559                 rxdp->Host_Control = 0;
5560                 return 0;
5561         }
5562
5563         /* Updating statistics */
5564         rxdp->Host_Control = 0;
5565         sp->rx_pkt_count++;
5566         sp->stats.rx_packets++;
5567 #ifndef CONFIG_2BUFF_MODE
5568         sp->stats.rx_bytes += len;
5569 #else
5570         sp->stats.rx_bytes += buf0_len + buf2_len;
5571 #endif
5572
5573 #ifndef CONFIG_2BUFF_MODE
5574         skb_put(skb, len);
5575 #else
5576         buff = skb_push(skb, buf0_len);
5577         memcpy(buff, ba->ba_0, buf0_len);
5578         skb_put(skb, buf2_len);
5579 #endif
5580
5581         if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
5582             (sp->rx_csum)) {
5583                 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
5584                 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
5585                 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
5586                         /*
5587                          * NIC verifies if the Checksum of the received