Add support the Korina (IDT RC32434) Ethernet MAC
[linux-2.6.git] / drivers / net / s2io.c
1 /************************************************************************
2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3  * Copyright(c) 2002-2007 Neterion Inc.
4
5  * This software may be used and distributed according to the terms of
6  * the GNU General Public License (GPL), incorporated herein by reference.
7  * Drivers based on or derived from this code fall under the GPL and must
8  * retain the authorship, copyright and license notice.  This file is not
9  * a complete program and may only be used when the entire operating
10  * system is licensed under the GPL.
11  * See the file COPYING in this distribution for more information.
12  *
13  * Credits:
14  * Jeff Garzik          : For pointing out the improper error condition
15  *                        check in the s2io_xmit routine and also some
16  *                        issues in the Tx watch dog function. Also for
17  *                        patiently answering all those innumerable
18  *                        questions regaring the 2.6 porting issues.
19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
20  *                        macros available only in 2.6 Kernel.
21  * Francois Romieu      : For pointing out all code part that were
22  *                        deprecated and also styling related comments.
23  * Grant Grundler       : For helping me get rid of some Architecture
24  *                        dependent code.
25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
26  *
27  * The module loadable parameters that are supported by the driver and a brief
28  * explaination of all the variables.
29  *
30  * rx_ring_num : This can be used to program the number of receive rings used
31  * in the driver.
32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
33  *     This is also an array of size 8.
34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35  *              values are 1, 2.
36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
38  * Tx descriptors that can be associated with each corresponding FIFO.
39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40  *     2(MSI_X). Default value is '2(MSI_X)'
41  * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
42  *     Possible values '1' for enable '0' for disable. Default is '0'
43  * lro_max_pkts: This parameter defines maximum number of packets can be
44  *     aggregated as a single large packet
45  * napi: This parameter used to enable/disable NAPI (polling Rx)
46  *     Possible values '1' for enable and '0' for disable. Default is '1'
47  * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48  *      Possible values '1' for enable and '0' for disable. Default is '0'
49  * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50  *                 Possible values '1' for enable , '0' for disable.
51  *                 Default is '2' - which means disable in promisc mode
52  *                 and enable in non-promiscuous mode.
53  * multiq: This parameter used to enable/disable MULTIQUEUE support.
54  *      Possible values '1' for enable and '0' for disable. Default is '0'
55  ************************************************************************/
56
57 #include <linux/module.h>
58 #include <linux/types.h>
59 #include <linux/errno.h>
60 #include <linux/ioport.h>
61 #include <linux/pci.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/kernel.h>
64 #include <linux/netdevice.h>
65 #include <linux/etherdevice.h>
66 #include <linux/skbuff.h>
67 #include <linux/init.h>
68 #include <linux/delay.h>
69 #include <linux/stddef.h>
70 #include <linux/ioctl.h>
71 #include <linux/timex.h>
72 #include <linux/ethtool.h>
73 #include <linux/workqueue.h>
74 #include <linux/if_vlan.h>
75 #include <linux/ip.h>
76 #include <linux/tcp.h>
77 #include <net/tcp.h>
78
79 #include <asm/system.h>
80 #include <asm/uaccess.h>
81 #include <asm/io.h>
82 #include <asm/div64.h>
83 #include <asm/irq.h>
84
85 /* local include */
86 #include "s2io.h"
87 #include "s2io-regs.h"
88
89 #define DRV_VERSION "2.0.26.19"
90
91 /* S2io Driver name & version. */
92 static char s2io_driver_name[] = "Neterion";
93 static char s2io_driver_version[] = DRV_VERSION;
94
95 static int rxd_size[2] = {32,48};
96 static int rxd_count[2] = {127,85};
97
98 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
99 {
100         int ret;
101
102         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
103                 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
104
105         return ret;
106 }
107
108 /*
109  * Cards with following subsystem_id have a link state indication
110  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
111  * macro below identifies these cards given the subsystem_id.
112  */
113 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
114         (dev_type == XFRAME_I_DEVICE) ?                 \
115                 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
116                  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
117
118 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
119                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
120 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
121 #define PANIC   1
122 #define LOW     2
123 static inline int rx_buffer_level(struct s2io_nic * sp, int rxb_size, int ring)
124 {
125         struct mac_info *mac_control;
126
127         mac_control = &sp->mac_control;
128         if (rxb_size <= rxd_count[sp->rxd_mode])
129                 return PANIC;
130         else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
131                 return  LOW;
132         return 0;
133 }
134
135 static inline int is_s2io_card_up(const struct s2io_nic * sp)
136 {
137         return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
138 }
139
140 /* Ethtool related variables and Macros. */
141 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
142         "Register test\t(offline)",
143         "Eeprom test\t(offline)",
144         "Link test\t(online)",
145         "RLDRAM test\t(offline)",
146         "BIST Test\t(offline)"
147 };
148
149 static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
150         {"tmac_frms"},
151         {"tmac_data_octets"},
152         {"tmac_drop_frms"},
153         {"tmac_mcst_frms"},
154         {"tmac_bcst_frms"},
155         {"tmac_pause_ctrl_frms"},
156         {"tmac_ttl_octets"},
157         {"tmac_ucst_frms"},
158         {"tmac_nucst_frms"},
159         {"tmac_any_err_frms"},
160         {"tmac_ttl_less_fb_octets"},
161         {"tmac_vld_ip_octets"},
162         {"tmac_vld_ip"},
163         {"tmac_drop_ip"},
164         {"tmac_icmp"},
165         {"tmac_rst_tcp"},
166         {"tmac_tcp"},
167         {"tmac_udp"},
168         {"rmac_vld_frms"},
169         {"rmac_data_octets"},
170         {"rmac_fcs_err_frms"},
171         {"rmac_drop_frms"},
172         {"rmac_vld_mcst_frms"},
173         {"rmac_vld_bcst_frms"},
174         {"rmac_in_rng_len_err_frms"},
175         {"rmac_out_rng_len_err_frms"},
176         {"rmac_long_frms"},
177         {"rmac_pause_ctrl_frms"},
178         {"rmac_unsup_ctrl_frms"},
179         {"rmac_ttl_octets"},
180         {"rmac_accepted_ucst_frms"},
181         {"rmac_accepted_nucst_frms"},
182         {"rmac_discarded_frms"},
183         {"rmac_drop_events"},
184         {"rmac_ttl_less_fb_octets"},
185         {"rmac_ttl_frms"},
186         {"rmac_usized_frms"},
187         {"rmac_osized_frms"},
188         {"rmac_frag_frms"},
189         {"rmac_jabber_frms"},
190         {"rmac_ttl_64_frms"},
191         {"rmac_ttl_65_127_frms"},
192         {"rmac_ttl_128_255_frms"},
193         {"rmac_ttl_256_511_frms"},
194         {"rmac_ttl_512_1023_frms"},
195         {"rmac_ttl_1024_1518_frms"},
196         {"rmac_ip"},
197         {"rmac_ip_octets"},
198         {"rmac_hdr_err_ip"},
199         {"rmac_drop_ip"},
200         {"rmac_icmp"},
201         {"rmac_tcp"},
202         {"rmac_udp"},
203         {"rmac_err_drp_udp"},
204         {"rmac_xgmii_err_sym"},
205         {"rmac_frms_q0"},
206         {"rmac_frms_q1"},
207         {"rmac_frms_q2"},
208         {"rmac_frms_q3"},
209         {"rmac_frms_q4"},
210         {"rmac_frms_q5"},
211         {"rmac_frms_q6"},
212         {"rmac_frms_q7"},
213         {"rmac_full_q0"},
214         {"rmac_full_q1"},
215         {"rmac_full_q2"},
216         {"rmac_full_q3"},
217         {"rmac_full_q4"},
218         {"rmac_full_q5"},
219         {"rmac_full_q6"},
220         {"rmac_full_q7"},
221         {"rmac_pause_cnt"},
222         {"rmac_xgmii_data_err_cnt"},
223         {"rmac_xgmii_ctrl_err_cnt"},
224         {"rmac_accepted_ip"},
225         {"rmac_err_tcp"},
226         {"rd_req_cnt"},
227         {"new_rd_req_cnt"},
228         {"new_rd_req_rtry_cnt"},
229         {"rd_rtry_cnt"},
230         {"wr_rtry_rd_ack_cnt"},
231         {"wr_req_cnt"},
232         {"new_wr_req_cnt"},
233         {"new_wr_req_rtry_cnt"},
234         {"wr_rtry_cnt"},
235         {"wr_disc_cnt"},
236         {"rd_rtry_wr_ack_cnt"},
237         {"txp_wr_cnt"},
238         {"txd_rd_cnt"},
239         {"txd_wr_cnt"},
240         {"rxd_rd_cnt"},
241         {"rxd_wr_cnt"},
242         {"txf_rd_cnt"},
243         {"rxf_wr_cnt"}
244 };
245
246 static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
247         {"rmac_ttl_1519_4095_frms"},
248         {"rmac_ttl_4096_8191_frms"},
249         {"rmac_ttl_8192_max_frms"},
250         {"rmac_ttl_gt_max_frms"},
251         {"rmac_osized_alt_frms"},
252         {"rmac_jabber_alt_frms"},
253         {"rmac_gt_max_alt_frms"},
254         {"rmac_vlan_frms"},
255         {"rmac_len_discard"},
256         {"rmac_fcs_discard"},
257         {"rmac_pf_discard"},
258         {"rmac_da_discard"},
259         {"rmac_red_discard"},
260         {"rmac_rts_discard"},
261         {"rmac_ingm_full_discard"},
262         {"link_fault_cnt"}
263 };
264
265 static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
266         {"\n DRIVER STATISTICS"},
267         {"single_bit_ecc_errs"},
268         {"double_bit_ecc_errs"},
269         {"parity_err_cnt"},
270         {"serious_err_cnt"},
271         {"soft_reset_cnt"},
272         {"fifo_full_cnt"},
273         {"ring_0_full_cnt"},
274         {"ring_1_full_cnt"},
275         {"ring_2_full_cnt"},
276         {"ring_3_full_cnt"},
277         {"ring_4_full_cnt"},
278         {"ring_5_full_cnt"},
279         {"ring_6_full_cnt"},
280         {"ring_7_full_cnt"},
281         {"alarm_transceiver_temp_high"},
282         {"alarm_transceiver_temp_low"},
283         {"alarm_laser_bias_current_high"},
284         {"alarm_laser_bias_current_low"},
285         {"alarm_laser_output_power_high"},
286         {"alarm_laser_output_power_low"},
287         {"warn_transceiver_temp_high"},
288         {"warn_transceiver_temp_low"},
289         {"warn_laser_bias_current_high"},
290         {"warn_laser_bias_current_low"},
291         {"warn_laser_output_power_high"},
292         {"warn_laser_output_power_low"},
293         {"lro_aggregated_pkts"},
294         {"lro_flush_both_count"},
295         {"lro_out_of_sequence_pkts"},
296         {"lro_flush_due_to_max_pkts"},
297         {"lro_avg_aggr_pkts"},
298         {"mem_alloc_fail_cnt"},
299         {"pci_map_fail_cnt"},
300         {"watchdog_timer_cnt"},
301         {"mem_allocated"},
302         {"mem_freed"},
303         {"link_up_cnt"},
304         {"link_down_cnt"},
305         {"link_up_time"},
306         {"link_down_time"},
307         {"tx_tcode_buf_abort_cnt"},
308         {"tx_tcode_desc_abort_cnt"},
309         {"tx_tcode_parity_err_cnt"},
310         {"tx_tcode_link_loss_cnt"},
311         {"tx_tcode_list_proc_err_cnt"},
312         {"rx_tcode_parity_err_cnt"},
313         {"rx_tcode_abort_cnt"},
314         {"rx_tcode_parity_abort_cnt"},
315         {"rx_tcode_rda_fail_cnt"},
316         {"rx_tcode_unkn_prot_cnt"},
317         {"rx_tcode_fcs_err_cnt"},
318         {"rx_tcode_buf_size_err_cnt"},
319         {"rx_tcode_rxd_corrupt_cnt"},
320         {"rx_tcode_unkn_err_cnt"},
321         {"tda_err_cnt"},
322         {"pfc_err_cnt"},
323         {"pcc_err_cnt"},
324         {"tti_err_cnt"},
325         {"tpa_err_cnt"},
326         {"sm_err_cnt"},
327         {"lso_err_cnt"},
328         {"mac_tmac_err_cnt"},
329         {"mac_rmac_err_cnt"},
330         {"xgxs_txgxs_err_cnt"},
331         {"xgxs_rxgxs_err_cnt"},
332         {"rc_err_cnt"},
333         {"prc_pcix_err_cnt"},
334         {"rpa_err_cnt"},
335         {"rda_err_cnt"},
336         {"rti_err_cnt"},
337         {"mc_err_cnt"}
338 };
339
340 #define S2IO_XENA_STAT_LEN      ARRAY_SIZE(ethtool_xena_stats_keys)
341 #define S2IO_ENHANCED_STAT_LEN  ARRAY_SIZE(ethtool_enhanced_stats_keys)
342 #define S2IO_DRIVER_STAT_LEN    ARRAY_SIZE(ethtool_driver_stats_keys)
343
344 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
345 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
346
347 #define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
348 #define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
349
350 #define S2IO_TEST_LEN   ARRAY_SIZE(s2io_gstrings)
351 #define S2IO_STRINGS_LEN        S2IO_TEST_LEN * ETH_GSTRING_LEN
352
353 #define S2IO_TIMER_CONF(timer, handle, arg, exp)                \
354                         init_timer(&timer);                     \
355                         timer.function = handle;                \
356                         timer.data = (unsigned long) arg;       \
357                         mod_timer(&timer, (jiffies + exp))      \
358
359 /* copy mac addr to def_mac_addr array */
360 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
361 {
362         sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
363         sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
364         sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
365         sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
366         sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
367         sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
368 }
369 /* Add the vlan */
370 static void s2io_vlan_rx_register(struct net_device *dev,
371                                         struct vlan_group *grp)
372 {
373         int i;
374         struct s2io_nic *nic = dev->priv;
375         unsigned long flags[MAX_TX_FIFOS];
376         struct mac_info *mac_control = &nic->mac_control;
377         struct config_param *config = &nic->config;
378
379         for (i = 0; i < config->tx_fifo_num; i++)
380                 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
381
382         nic->vlgrp = grp;
383         for (i = config->tx_fifo_num - 1; i >= 0; i--)
384                 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
385                                 flags[i]);
386 }
387
388 /* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
389 static int vlan_strip_flag;
390
391 /* Unregister the vlan */
392 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
393 {
394         int i;
395         struct s2io_nic *nic = dev->priv;
396         unsigned long flags[MAX_TX_FIFOS];
397         struct mac_info *mac_control = &nic->mac_control;
398         struct config_param *config = &nic->config;
399
400         for (i = 0; i < config->tx_fifo_num; i++)
401                 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
402
403         if (nic->vlgrp)
404                 vlan_group_set_device(nic->vlgrp, vid, NULL);
405
406         for (i = config->tx_fifo_num - 1; i >= 0; i--)
407                 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
408                         flags[i]);
409 }
410
411 /*
412  * Constants to be programmed into the Xena's registers, to configure
413  * the XAUI.
414  */
415
416 #define END_SIGN        0x0
417 static const u64 herc_act_dtx_cfg[] = {
418         /* Set address */
419         0x8000051536750000ULL, 0x80000515367500E0ULL,
420         /* Write data */
421         0x8000051536750004ULL, 0x80000515367500E4ULL,
422         /* Set address */
423         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
424         /* Write data */
425         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
426         /* Set address */
427         0x801205150D440000ULL, 0x801205150D4400E0ULL,
428         /* Write data */
429         0x801205150D440004ULL, 0x801205150D4400E4ULL,
430         /* Set address */
431         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
432         /* Write data */
433         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
434         /* Done */
435         END_SIGN
436 };
437
438 static const u64 xena_dtx_cfg[] = {
439         /* Set address */
440         0x8000051500000000ULL, 0x80000515000000E0ULL,
441         /* Write data */
442         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
443         /* Set address */
444         0x8001051500000000ULL, 0x80010515000000E0ULL,
445         /* Write data */
446         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
447         /* Set address */
448         0x8002051500000000ULL, 0x80020515000000E0ULL,
449         /* Write data */
450         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
451         END_SIGN
452 };
453
454 /*
455  * Constants for Fixing the MacAddress problem seen mostly on
456  * Alpha machines.
457  */
458 static const u64 fix_mac[] = {
459         0x0060000000000000ULL, 0x0060600000000000ULL,
460         0x0040600000000000ULL, 0x0000600000000000ULL,
461         0x0020600000000000ULL, 0x0060600000000000ULL,
462         0x0020600000000000ULL, 0x0060600000000000ULL,
463         0x0020600000000000ULL, 0x0060600000000000ULL,
464         0x0020600000000000ULL, 0x0060600000000000ULL,
465         0x0020600000000000ULL, 0x0060600000000000ULL,
466         0x0020600000000000ULL, 0x0060600000000000ULL,
467         0x0020600000000000ULL, 0x0060600000000000ULL,
468         0x0020600000000000ULL, 0x0060600000000000ULL,
469         0x0020600000000000ULL, 0x0060600000000000ULL,
470         0x0020600000000000ULL, 0x0060600000000000ULL,
471         0x0020600000000000ULL, 0x0000600000000000ULL,
472         0x0040600000000000ULL, 0x0060600000000000ULL,
473         END_SIGN
474 };
475
476 MODULE_LICENSE("GPL");
477 MODULE_VERSION(DRV_VERSION);
478
479
480 /* Module Loadable parameters. */
481 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
482 S2IO_PARM_INT(rx_ring_num, 1);
483 S2IO_PARM_INT(multiq, 0);
484 S2IO_PARM_INT(rx_ring_mode, 1);
485 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
486 S2IO_PARM_INT(rmac_pause_time, 0x100);
487 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
488 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
489 S2IO_PARM_INT(shared_splits, 0);
490 S2IO_PARM_INT(tmac_util_period, 5);
491 S2IO_PARM_INT(rmac_util_period, 5);
492 S2IO_PARM_INT(l3l4hdr_size, 128);
493 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
494 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
495 /* Frequency of Rx desc syncs expressed as power of 2 */
496 S2IO_PARM_INT(rxsync_frequency, 3);
497 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
498 S2IO_PARM_INT(intr_type, 2);
499 /* Large receive offload feature */
500 static unsigned int lro_enable;
501 module_param_named(lro, lro_enable, uint, 0);
502
503 /* Max pkts to be aggregated by LRO at one time. If not specified,
504  * aggregation happens until we hit max IP pkt size(64K)
505  */
506 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
507 S2IO_PARM_INT(indicate_max_pkts, 0);
508
509 S2IO_PARM_INT(napi, 1);
510 S2IO_PARM_INT(ufo, 0);
511 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
512
513 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
514     {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
515 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
516     {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
517 static unsigned int rts_frm_len[MAX_RX_RINGS] =
518     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
519
520 module_param_array(tx_fifo_len, uint, NULL, 0);
521 module_param_array(rx_ring_sz, uint, NULL, 0);
522 module_param_array(rts_frm_len, uint, NULL, 0);
523
524 /*
525  * S2IO device table.
526  * This table lists all the devices that this driver supports.
527  */
528 static struct pci_device_id s2io_tbl[] __devinitdata = {
529         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
530          PCI_ANY_ID, PCI_ANY_ID},
531         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
532          PCI_ANY_ID, PCI_ANY_ID},
533         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
534          PCI_ANY_ID, PCI_ANY_ID},
535         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
536          PCI_ANY_ID, PCI_ANY_ID},
537         {0,}
538 };
539
540 MODULE_DEVICE_TABLE(pci, s2io_tbl);
541
542 static struct pci_error_handlers s2io_err_handler = {
543         .error_detected = s2io_io_error_detected,
544         .slot_reset = s2io_io_slot_reset,
545         .resume = s2io_io_resume,
546 };
547
548 static struct pci_driver s2io_driver = {
549       .name = "S2IO",
550       .id_table = s2io_tbl,
551       .probe = s2io_init_nic,
552       .remove = __devexit_p(s2io_rem_nic),
553       .err_handler = &s2io_err_handler,
554 };
555
556 /* A simplifier macro used both by init and free shared_mem Fns(). */
557 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
558
559 /* netqueue manipulation helper functions */
560 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
561 {
562         int i;
563 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
564         if (sp->config.multiq) {
565                 for (i = 0; i < sp->config.tx_fifo_num; i++)
566                         netif_stop_subqueue(sp->dev, i);
567         } else
568 #endif
569         {
570                 for (i = 0; i < sp->config.tx_fifo_num; i++)
571                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
572                 netif_stop_queue(sp->dev);
573         }
574 }
575
576 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
577 {
578 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
579         if (sp->config.multiq)
580                 netif_stop_subqueue(sp->dev, fifo_no);
581         else
582 #endif
583         {
584                 sp->mac_control.fifos[fifo_no].queue_state =
585                         FIFO_QUEUE_STOP;
586                 netif_stop_queue(sp->dev);
587         }
588 }
589
590 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
591 {
592         int i;
593 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
594         if (sp->config.multiq) {
595                 for (i = 0; i < sp->config.tx_fifo_num; i++)
596                         netif_start_subqueue(sp->dev, i);
597         } else
598 #endif
599         {
600                 for (i = 0; i < sp->config.tx_fifo_num; i++)
601                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
602                 netif_start_queue(sp->dev);
603         }
604 }
605
606 static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
607 {
608 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
609         if (sp->config.multiq)
610                 netif_start_subqueue(sp->dev, fifo_no);
611         else
612 #endif
613         {
614                 sp->mac_control.fifos[fifo_no].queue_state =
615                         FIFO_QUEUE_START;
616                 netif_start_queue(sp->dev);
617         }
618 }
619
620 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
621 {
622         int i;
623 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
624         if (sp->config.multiq) {
625                 for (i = 0; i < sp->config.tx_fifo_num; i++)
626                         netif_wake_subqueue(sp->dev, i);
627         } else
628 #endif
629         {
630                 for (i = 0; i < sp->config.tx_fifo_num; i++)
631                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
632                 netif_wake_queue(sp->dev);
633         }
634 }
635
636 static inline void s2io_wake_tx_queue(
637         struct fifo_info *fifo, int cnt, u8 multiq)
638 {
639
640 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
641         if (multiq) {
642                 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
643                         netif_wake_subqueue(fifo->dev, fifo->fifo_no);
644         } else
645 #endif
646         if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
647                 if (netif_queue_stopped(fifo->dev)) {
648                         fifo->queue_state = FIFO_QUEUE_START;
649                         netif_wake_queue(fifo->dev);
650                 }
651         }
652 }
653
654 /**
655  * init_shared_mem - Allocation and Initialization of Memory
656  * @nic: Device private variable.
657  * Description: The function allocates all the memory areas shared
658  * between the NIC and the driver. This includes Tx descriptors,
659  * Rx descriptors and the statistics block.
660  */
661
662 static int init_shared_mem(struct s2io_nic *nic)
663 {
664         u32 size;
665         void *tmp_v_addr, *tmp_v_addr_next;
666         dma_addr_t tmp_p_addr, tmp_p_addr_next;
667         struct RxD_block *pre_rxd_blk = NULL;
668         int i, j, blk_cnt;
669         int lst_size, lst_per_page;
670         struct net_device *dev = nic->dev;
671         unsigned long tmp;
672         struct buffAdd *ba;
673
674         struct mac_info *mac_control;
675         struct config_param *config;
676         unsigned long long mem_allocated = 0;
677
678         mac_control = &nic->mac_control;
679         config = &nic->config;
680
681
682         /* Allocation and initialization of TXDLs in FIOFs */
683         size = 0;
684         for (i = 0; i < config->tx_fifo_num; i++) {
685                 size += config->tx_cfg[i].fifo_len;
686         }
687         if (size > MAX_AVAILABLE_TXDS) {
688                 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
689                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
690                 return -EINVAL;
691         }
692
693         size = 0;
694         for (i = 0; i < config->tx_fifo_num; i++) {
695                 size = config->tx_cfg[i].fifo_len;
696                 /*
697                  * Legal values are from 2 to 8192
698                  */
699                 if (size < 2) {
700                         DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size);
701                         DBG_PRINT(ERR_DBG, "for fifo %d\n", i);
702                         DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len"
703                                 "are 2 to 8192\n");
704                         return -EINVAL;
705                 }
706         }
707
708         lst_size = (sizeof(struct TxD) * config->max_txds);
709         lst_per_page = PAGE_SIZE / lst_size;
710
711         for (i = 0; i < config->tx_fifo_num; i++) {
712                 int fifo_len = config->tx_cfg[i].fifo_len;
713                 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
714                 mac_control->fifos[i].list_info = kzalloc(list_holder_size,
715                                                           GFP_KERNEL);
716                 if (!mac_control->fifos[i].list_info) {
717                         DBG_PRINT(INFO_DBG,
718                                   "Malloc failed for list_info\n");
719                         return -ENOMEM;
720                 }
721                 mem_allocated += list_holder_size;
722         }
723         for (i = 0; i < config->tx_fifo_num; i++) {
724                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
725                                                 lst_per_page);
726                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
727                 mac_control->fifos[i].tx_curr_put_info.fifo_len =
728                     config->tx_cfg[i].fifo_len - 1;
729                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
730                 mac_control->fifos[i].tx_curr_get_info.fifo_len =
731                     config->tx_cfg[i].fifo_len - 1;
732                 mac_control->fifos[i].fifo_no = i;
733                 mac_control->fifos[i].nic = nic;
734                 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
735                 mac_control->fifos[i].dev = dev;
736
737                 for (j = 0; j < page_num; j++) {
738                         int k = 0;
739                         dma_addr_t tmp_p;
740                         void *tmp_v;
741                         tmp_v = pci_alloc_consistent(nic->pdev,
742                                                      PAGE_SIZE, &tmp_p);
743                         if (!tmp_v) {
744                                 DBG_PRINT(INFO_DBG,
745                                           "pci_alloc_consistent ");
746                                 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
747                                 return -ENOMEM;
748                         }
749                         /* If we got a zero DMA address(can happen on
750                          * certain platforms like PPC), reallocate.
751                          * Store virtual address of page we don't want,
752                          * to be freed later.
753                          */
754                         if (!tmp_p) {
755                                 mac_control->zerodma_virt_addr = tmp_v;
756                                 DBG_PRINT(INIT_DBG,
757                                 "%s: Zero DMA address for TxDL. ", dev->name);
758                                 DBG_PRINT(INIT_DBG,
759                                 "Virtual address %p\n", tmp_v);
760                                 tmp_v = pci_alloc_consistent(nic->pdev,
761                                                      PAGE_SIZE, &tmp_p);
762                                 if (!tmp_v) {
763                                         DBG_PRINT(INFO_DBG,
764                                           "pci_alloc_consistent ");
765                                         DBG_PRINT(INFO_DBG, "failed for TxDL\n");
766                                         return -ENOMEM;
767                                 }
768                                 mem_allocated += PAGE_SIZE;
769                         }
770                         while (k < lst_per_page) {
771                                 int l = (j * lst_per_page) + k;
772                                 if (l == config->tx_cfg[i].fifo_len)
773                                         break;
774                                 mac_control->fifos[i].list_info[l].list_virt_addr =
775                                     tmp_v + (k * lst_size);
776                                 mac_control->fifos[i].list_info[l].list_phy_addr =
777                                     tmp_p + (k * lst_size);
778                                 k++;
779                         }
780                 }
781         }
782
783         for (i = 0; i < config->tx_fifo_num; i++) {
784                 size = config->tx_cfg[i].fifo_len;
785                 mac_control->fifos[i].ufo_in_band_v
786                         = kcalloc(size, sizeof(u64), GFP_KERNEL);
787                 if (!mac_control->fifos[i].ufo_in_band_v)
788                         return -ENOMEM;
789                 mem_allocated += (size * sizeof(u64));
790         }
791
792         /* Allocation and initialization of RXDs in Rings */
793         size = 0;
794         for (i = 0; i < config->rx_ring_num; i++) {
795                 if (config->rx_cfg[i].num_rxd %
796                     (rxd_count[nic->rxd_mode] + 1)) {
797                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
798                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
799                                   i);
800                         DBG_PRINT(ERR_DBG, "RxDs per Block");
801                         return FAILURE;
802                 }
803                 size += config->rx_cfg[i].num_rxd;
804                 mac_control->rings[i].block_count =
805                         config->rx_cfg[i].num_rxd /
806                         (rxd_count[nic->rxd_mode] + 1 );
807                 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
808                         mac_control->rings[i].block_count;
809         }
810         if (nic->rxd_mode == RXD_MODE_1)
811                 size = (size * (sizeof(struct RxD1)));
812         else
813                 size = (size * (sizeof(struct RxD3)));
814
815         for (i = 0; i < config->rx_ring_num; i++) {
816                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
817                 mac_control->rings[i].rx_curr_get_info.offset = 0;
818                 mac_control->rings[i].rx_curr_get_info.ring_len =
819                     config->rx_cfg[i].num_rxd - 1;
820                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
821                 mac_control->rings[i].rx_curr_put_info.offset = 0;
822                 mac_control->rings[i].rx_curr_put_info.ring_len =
823                     config->rx_cfg[i].num_rxd - 1;
824                 mac_control->rings[i].nic = nic;
825                 mac_control->rings[i].ring_no = i;
826
827                 blk_cnt = config->rx_cfg[i].num_rxd /
828                                 (rxd_count[nic->rxd_mode] + 1);
829                 /*  Allocating all the Rx blocks */
830                 for (j = 0; j < blk_cnt; j++) {
831                         struct rx_block_info *rx_blocks;
832                         int l;
833
834                         rx_blocks = &mac_control->rings[i].rx_blocks[j];
835                         size = SIZE_OF_BLOCK; //size is always page size
836                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
837                                                           &tmp_p_addr);
838                         if (tmp_v_addr == NULL) {
839                                 /*
840                                  * In case of failure, free_shared_mem()
841                                  * is called, which should free any
842                                  * memory that was alloced till the
843                                  * failure happened.
844                                  */
845                                 rx_blocks->block_virt_addr = tmp_v_addr;
846                                 return -ENOMEM;
847                         }
848                         mem_allocated += size;
849                         memset(tmp_v_addr, 0, size);
850                         rx_blocks->block_virt_addr = tmp_v_addr;
851                         rx_blocks->block_dma_addr = tmp_p_addr;
852                         rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
853                                                   rxd_count[nic->rxd_mode],
854                                                   GFP_KERNEL);
855                         if (!rx_blocks->rxds)
856                                 return -ENOMEM;
857                         mem_allocated +=
858                         (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
859                         for (l=0; l<rxd_count[nic->rxd_mode];l++) {
860                                 rx_blocks->rxds[l].virt_addr =
861                                         rx_blocks->block_virt_addr +
862                                         (rxd_size[nic->rxd_mode] * l);
863                                 rx_blocks->rxds[l].dma_addr =
864                                         rx_blocks->block_dma_addr +
865                                         (rxd_size[nic->rxd_mode] * l);
866                         }
867                 }
868                 /* Interlinking all Rx Blocks */
869                 for (j = 0; j < blk_cnt; j++) {
870                         tmp_v_addr =
871                                 mac_control->rings[i].rx_blocks[j].block_virt_addr;
872                         tmp_v_addr_next =
873                                 mac_control->rings[i].rx_blocks[(j + 1) %
874                                               blk_cnt].block_virt_addr;
875                         tmp_p_addr =
876                                 mac_control->rings[i].rx_blocks[j].block_dma_addr;
877                         tmp_p_addr_next =
878                                 mac_control->rings[i].rx_blocks[(j + 1) %
879                                               blk_cnt].block_dma_addr;
880
881                         pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
882                         pre_rxd_blk->reserved_2_pNext_RxD_block =
883                             (unsigned long) tmp_v_addr_next;
884                         pre_rxd_blk->pNext_RxD_Blk_physical =
885                             (u64) tmp_p_addr_next;
886                 }
887         }
888         if (nic->rxd_mode == RXD_MODE_3B) {
889                 /*
890                  * Allocation of Storages for buffer addresses in 2BUFF mode
891                  * and the buffers as well.
892                  */
893                 for (i = 0; i < config->rx_ring_num; i++) {
894                         blk_cnt = config->rx_cfg[i].num_rxd /
895                            (rxd_count[nic->rxd_mode]+ 1);
896                         mac_control->rings[i].ba =
897                                 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
898                                      GFP_KERNEL);
899                         if (!mac_control->rings[i].ba)
900                                 return -ENOMEM;
901                         mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
902                         for (j = 0; j < blk_cnt; j++) {
903                                 int k = 0;
904                                 mac_control->rings[i].ba[j] =
905                                         kmalloc((sizeof(struct buffAdd) *
906                                                 (rxd_count[nic->rxd_mode] + 1)),
907                                                 GFP_KERNEL);
908                                 if (!mac_control->rings[i].ba[j])
909                                         return -ENOMEM;
910                                 mem_allocated += (sizeof(struct buffAdd) *  \
911                                         (rxd_count[nic->rxd_mode] + 1));
912                                 while (k != rxd_count[nic->rxd_mode]) {
913                                         ba = &mac_control->rings[i].ba[j][k];
914
915                                         ba->ba_0_org = (void *) kmalloc
916                                             (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
917                                         if (!ba->ba_0_org)
918                                                 return -ENOMEM;
919                                         mem_allocated +=
920                                                 (BUF0_LEN + ALIGN_SIZE);
921                                         tmp = (unsigned long)ba->ba_0_org;
922                                         tmp += ALIGN_SIZE;
923                                         tmp &= ~((unsigned long) ALIGN_SIZE);
924                                         ba->ba_0 = (void *) tmp;
925
926                                         ba->ba_1_org = (void *) kmalloc
927                                             (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
928                                         if (!ba->ba_1_org)
929                                                 return -ENOMEM;
930                                         mem_allocated
931                                                 += (BUF1_LEN + ALIGN_SIZE);
932                                         tmp = (unsigned long) ba->ba_1_org;
933                                         tmp += ALIGN_SIZE;
934                                         tmp &= ~((unsigned long) ALIGN_SIZE);
935                                         ba->ba_1 = (void *) tmp;
936                                         k++;
937                                 }
938                         }
939                 }
940         }
941
942         /* Allocation and initialization of Statistics block */
943         size = sizeof(struct stat_block);
944         mac_control->stats_mem = pci_alloc_consistent
945             (nic->pdev, size, &mac_control->stats_mem_phy);
946
947         if (!mac_control->stats_mem) {
948                 /*
949                  * In case of failure, free_shared_mem() is called, which
950                  * should free any memory that was alloced till the
951                  * failure happened.
952                  */
953                 return -ENOMEM;
954         }
955         mem_allocated += size;
956         mac_control->stats_mem_sz = size;
957
958         tmp_v_addr = mac_control->stats_mem;
959         mac_control->stats_info = (struct stat_block *) tmp_v_addr;
960         memset(tmp_v_addr, 0, size);
961         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
962                   (unsigned long long) tmp_p_addr);
963         mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
964         return SUCCESS;
965 }
966
967 /**
968  * free_shared_mem - Free the allocated Memory
969  * @nic:  Device private variable.
970  * Description: This function is to free all memory locations allocated by
971  * the init_shared_mem() function and return it to the kernel.
972  */
973
974 static void free_shared_mem(struct s2io_nic *nic)
975 {
976         int i, j, blk_cnt, size;
977         void *tmp_v_addr;
978         dma_addr_t tmp_p_addr;
979         struct mac_info *mac_control;
980         struct config_param *config;
981         int lst_size, lst_per_page;
982         struct net_device *dev;
983         int page_num = 0;
984
985         if (!nic)
986                 return;
987
988         dev = nic->dev;
989
990         mac_control = &nic->mac_control;
991         config = &nic->config;
992
993         lst_size = (sizeof(struct TxD) * config->max_txds);
994         lst_per_page = PAGE_SIZE / lst_size;
995
996         for (i = 0; i < config->tx_fifo_num; i++) {
997                 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
998                                                         lst_per_page);
999                 for (j = 0; j < page_num; j++) {
1000                         int mem_blks = (j * lst_per_page);
1001                         if (!mac_control->fifos[i].list_info)
1002                                 return;
1003                         if (!mac_control->fifos[i].list_info[mem_blks].
1004                                  list_virt_addr)
1005                                 break;
1006                         pci_free_consistent(nic->pdev, PAGE_SIZE,
1007                                             mac_control->fifos[i].
1008                                             list_info[mem_blks].
1009                                             list_virt_addr,
1010                                             mac_control->fifos[i].
1011                                             list_info[mem_blks].
1012                                             list_phy_addr);
1013                         nic->mac_control.stats_info->sw_stat.mem_freed
1014                                                 += PAGE_SIZE;
1015                 }
1016                 /* If we got a zero DMA address during allocation,
1017                  * free the page now
1018                  */
1019                 if (mac_control->zerodma_virt_addr) {
1020                         pci_free_consistent(nic->pdev, PAGE_SIZE,
1021                                             mac_control->zerodma_virt_addr,
1022                                             (dma_addr_t)0);
1023                         DBG_PRINT(INIT_DBG,
1024                                 "%s: Freeing TxDL with zero DMA addr. ",
1025                                 dev->name);
1026                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
1027                                 mac_control->zerodma_virt_addr);
1028                         nic->mac_control.stats_info->sw_stat.mem_freed
1029                                                 += PAGE_SIZE;
1030                 }
1031                 kfree(mac_control->fifos[i].list_info);
1032                 nic->mac_control.stats_info->sw_stat.mem_freed +=
1033                 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
1034         }
1035
1036         size = SIZE_OF_BLOCK;
1037         for (i = 0; i < config->rx_ring_num; i++) {
1038                 blk_cnt = mac_control->rings[i].block_count;
1039                 for (j = 0; j < blk_cnt; j++) {
1040                         tmp_v_addr = mac_control->rings[i].rx_blocks[j].
1041                                 block_virt_addr;
1042                         tmp_p_addr = mac_control->rings[i].rx_blocks[j].
1043                                 block_dma_addr;
1044                         if (tmp_v_addr == NULL)
1045                                 break;
1046                         pci_free_consistent(nic->pdev, size,
1047                                             tmp_v_addr, tmp_p_addr);
1048                         nic->mac_control.stats_info->sw_stat.mem_freed += size;
1049                         kfree(mac_control->rings[i].rx_blocks[j].rxds);
1050                         nic->mac_control.stats_info->sw_stat.mem_freed +=
1051                         ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
1052                 }
1053         }
1054
1055         if (nic->rxd_mode == RXD_MODE_3B) {
1056                 /* Freeing buffer storage addresses in 2BUFF mode. */
1057                 for (i = 0; i < config->rx_ring_num; i++) {
1058                         blk_cnt = config->rx_cfg[i].num_rxd /
1059                             (rxd_count[nic->rxd_mode] + 1);
1060                         for (j = 0; j < blk_cnt; j++) {
1061                                 int k = 0;
1062                                 if (!mac_control->rings[i].ba[j])
1063                                         continue;
1064                                 while (k != rxd_count[nic->rxd_mode]) {
1065                                         struct buffAdd *ba =
1066                                                 &mac_control->rings[i].ba[j][k];
1067                                         kfree(ba->ba_0_org);
1068                                         nic->mac_control.stats_info->sw_stat.\
1069                                         mem_freed += (BUF0_LEN + ALIGN_SIZE);
1070                                         kfree(ba->ba_1_org);
1071                                         nic->mac_control.stats_info->sw_stat.\
1072                                         mem_freed += (BUF1_LEN + ALIGN_SIZE);
1073                                         k++;
1074                                 }
1075                                 kfree(mac_control->rings[i].ba[j]);
1076                                 nic->mac_control.stats_info->sw_stat.mem_freed +=
1077                                         (sizeof(struct buffAdd) *
1078                                         (rxd_count[nic->rxd_mode] + 1));
1079                         }
1080                         kfree(mac_control->rings[i].ba);
1081                         nic->mac_control.stats_info->sw_stat.mem_freed +=
1082                         (sizeof(struct buffAdd *) * blk_cnt);
1083                 }
1084         }
1085
1086         for (i = 0; i < nic->config.tx_fifo_num; i++) {
1087                 if (mac_control->fifos[i].ufo_in_band_v) {
1088                         nic->mac_control.stats_info->sw_stat.mem_freed
1089                                 += (config->tx_cfg[i].fifo_len * sizeof(u64));
1090                         kfree(mac_control->fifos[i].ufo_in_band_v);
1091                 }
1092         }
1093
1094         if (mac_control->stats_mem) {
1095                 nic->mac_control.stats_info->sw_stat.mem_freed +=
1096                         mac_control->stats_mem_sz;
1097                 pci_free_consistent(nic->pdev,
1098                                     mac_control->stats_mem_sz,
1099                                     mac_control->stats_mem,
1100                                     mac_control->stats_mem_phy);
1101         }
1102 }
1103
1104 /**
1105  * s2io_verify_pci_mode -
1106  */
1107
1108 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1109 {
1110         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1111         register u64 val64 = 0;
1112         int     mode;
1113
1114         val64 = readq(&bar0->pci_mode);
1115         mode = (u8)GET_PCI_MODE(val64);
1116
1117         if ( val64 & PCI_MODE_UNKNOWN_MODE)
1118                 return -1;      /* Unknown PCI mode */
1119         return mode;
1120 }
1121
1122 #define NEC_VENID   0x1033
1123 #define NEC_DEVID   0x0125
1124 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1125 {
1126         struct pci_dev *tdev = NULL;
1127         while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1128                 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1129                         if (tdev->bus == s2io_pdev->bus->parent)
1130                                 pci_dev_put(tdev);
1131                                 return 1;
1132                 }
1133         }
1134         return 0;
1135 }
1136
1137 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1138 /**
1139  * s2io_print_pci_mode -
1140  */
1141 static int s2io_print_pci_mode(struct s2io_nic *nic)
1142 {
1143         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1144         register u64 val64 = 0;
1145         int     mode;
1146         struct config_param *config = &nic->config;
1147
1148         val64 = readq(&bar0->pci_mode);
1149         mode = (u8)GET_PCI_MODE(val64);
1150
1151         if ( val64 & PCI_MODE_UNKNOWN_MODE)
1152                 return -1;      /* Unknown PCI mode */
1153
1154         config->bus_speed = bus_speed[mode];
1155
1156         if (s2io_on_nec_bridge(nic->pdev)) {
1157                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1158                                                         nic->dev->name);
1159                 return mode;
1160         }
1161
1162         if (val64 & PCI_MODE_32_BITS) {
1163                 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
1164         } else {
1165                 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
1166         }
1167
1168         switch(mode) {
1169                 case PCI_MODE_PCI_33:
1170                         DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
1171                         break;
1172                 case PCI_MODE_PCI_66:
1173                         DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
1174                         break;
1175                 case PCI_MODE_PCIX_M1_66:
1176                         DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
1177                         break;
1178                 case PCI_MODE_PCIX_M1_100:
1179                         DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
1180                         break;
1181                 case PCI_MODE_PCIX_M1_133:
1182                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
1183                         break;
1184                 case PCI_MODE_PCIX_M2_66:
1185                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
1186                         break;
1187                 case PCI_MODE_PCIX_M2_100:
1188                         DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
1189                         break;
1190                 case PCI_MODE_PCIX_M2_133:
1191                         DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
1192                         break;
1193                 default:
1194                         return -1;      /* Unsupported bus speed */
1195         }
1196
1197         return mode;
1198 }
1199
1200 /**
1201  *  init_tti - Initialization transmit traffic interrupt scheme
1202  *  @nic: device private variable
1203  *  @link: link status (UP/DOWN) used to enable/disable continuous
1204  *  transmit interrupts
1205  *  Description: The function configures transmit traffic interrupts
1206  *  Return Value:  SUCCESS on success and
1207  *  '-1' on failure
1208  */
1209
1210 static int init_tti(struct s2io_nic *nic, int link)
1211 {
1212         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1213         register u64 val64 = 0;
1214         int i;
1215         struct config_param *config;
1216
1217         config = &nic->config;
1218
1219         for (i = 0; i < config->tx_fifo_num; i++) {
1220                 /*
1221                  * TTI Initialization. Default Tx timer gets us about
1222                  * 250 interrupts per sec. Continuous interrupts are enabled
1223                  * by default.
1224                  */
1225                 if (nic->device_type == XFRAME_II_DEVICE) {
1226                         int count = (nic->config.bus_speed * 125)/2;
1227                         val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1228                 } else
1229                         val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1230
1231                 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1232                                 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1233                                 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1234                                 TTI_DATA1_MEM_TX_TIMER_AC_EN;
1235
1236                 if (use_continuous_tx_intrs && (link == LINK_UP))
1237                         val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1238                 writeq(val64, &bar0->tti_data1_mem);
1239
1240                 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1241                                 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1242                                 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1243                                 TTI_DATA2_MEM_TX_UFC_D(0x80);
1244
1245                 writeq(val64, &bar0->tti_data2_mem);
1246
1247                 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD |
1248                                 TTI_CMD_MEM_OFFSET(i);
1249                 writeq(val64, &bar0->tti_command_mem);
1250
1251                 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1252                         TTI_CMD_MEM_STROBE_NEW_CMD, S2IO_BIT_RESET) != SUCCESS)
1253                         return FAILURE;
1254         }
1255
1256         return SUCCESS;
1257 }
1258
1259 /**
1260  *  init_nic - Initialization of hardware
1261  *  @nic: device private variable
1262  *  Description: The function sequentially configures every block
1263  *  of the H/W from their reset values.
1264  *  Return Value:  SUCCESS on success and
1265  *  '-1' on failure (endian settings incorrect).
1266  */
1267
1268 static int init_nic(struct s2io_nic *nic)
1269 {
1270         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1271         struct net_device *dev = nic->dev;
1272         register u64 val64 = 0;
1273         void __iomem *add;
1274         u32 time;
1275         int i, j;
1276         struct mac_info *mac_control;
1277         struct config_param *config;
1278         int dtx_cnt = 0;
1279         unsigned long long mem_share;
1280         int mem_size;
1281
1282         mac_control = &nic->mac_control;
1283         config = &nic->config;
1284
1285         /* to set the swapper controle on the card */
1286         if(s2io_set_swapper(nic)) {
1287                 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
1288                 return -EIO;
1289         }
1290
1291         /*
1292          * Herc requires EOI to be removed from reset before XGXS, so..
1293          */
1294         if (nic->device_type & XFRAME_II_DEVICE) {
1295                 val64 = 0xA500000000ULL;
1296                 writeq(val64, &bar0->sw_reset);
1297                 msleep(500);
1298                 val64 = readq(&bar0->sw_reset);
1299         }
1300
1301         /* Remove XGXS from reset state */
1302         val64 = 0;
1303         writeq(val64, &bar0->sw_reset);
1304         msleep(500);
1305         val64 = readq(&bar0->sw_reset);
1306
1307         /* Ensure that it's safe to access registers by checking
1308          * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1309          */
1310         if (nic->device_type == XFRAME_II_DEVICE) {
1311                 for (i = 0; i < 50; i++) {
1312                         val64 = readq(&bar0->adapter_status);
1313                         if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1314                                 break;
1315                         msleep(10);
1316                 }
1317                 if (i == 50)
1318                         return -ENODEV;
1319         }
1320
1321         /*  Enable Receiving broadcasts */
1322         add = &bar0->mac_cfg;
1323         val64 = readq(&bar0->mac_cfg);
1324         val64 |= MAC_RMAC_BCAST_ENABLE;
1325         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1326         writel((u32) val64, add);
1327         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1328         writel((u32) (val64 >> 32), (add + 4));
1329
1330         /* Read registers in all blocks */
1331         val64 = readq(&bar0->mac_int_mask);
1332         val64 = readq(&bar0->mc_int_mask);
1333         val64 = readq(&bar0->xgxs_int_mask);
1334
1335         /*  Set MTU */
1336         val64 = dev->mtu;
1337         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1338
1339         if (nic->device_type & XFRAME_II_DEVICE) {
1340                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1341                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1342                                           &bar0->dtx_control, UF);
1343                         if (dtx_cnt & 0x1)
1344                                 msleep(1); /* Necessary!! */
1345                         dtx_cnt++;
1346                 }
1347         } else {
1348                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1349                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1350                                           &bar0->dtx_control, UF);
1351                         val64 = readq(&bar0->dtx_control);
1352                         dtx_cnt++;
1353                 }
1354         }
1355
1356         /*  Tx DMA Initialization */
1357         val64 = 0;
1358         writeq(val64, &bar0->tx_fifo_partition_0);
1359         writeq(val64, &bar0->tx_fifo_partition_1);
1360         writeq(val64, &bar0->tx_fifo_partition_2);
1361         writeq(val64, &bar0->tx_fifo_partition_3);
1362
1363
1364         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1365                 val64 |=
1366                     vBIT(config->tx_cfg[i].fifo_len - 1, ((j * 32) + 19),
1367                          13) | vBIT(config->tx_cfg[i].fifo_priority,
1368                                     ((j * 32) + 5), 3);
1369
1370                 if (i == (config->tx_fifo_num - 1)) {
1371                         if (i % 2 == 0)
1372                                 i++;
1373                 }
1374
1375                 switch (i) {
1376                 case 1:
1377                         writeq(val64, &bar0->tx_fifo_partition_0);
1378                         val64 = 0;
1379                         j = 0;
1380                         break;
1381                 case 3:
1382                         writeq(val64, &bar0->tx_fifo_partition_1);
1383                         val64 = 0;
1384                         j = 0;
1385                         break;
1386                 case 5:
1387                         writeq(val64, &bar0->tx_fifo_partition_2);
1388                         val64 = 0;
1389                         j = 0;
1390                         break;
1391                 case 7:
1392                         writeq(val64, &bar0->tx_fifo_partition_3);
1393                         val64 = 0;
1394                         j = 0;
1395                         break;
1396                 default:
1397                         j++;
1398                         break;
1399                 }
1400         }
1401
1402         /*
1403          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1404          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1405          */
1406         if ((nic->device_type == XFRAME_I_DEVICE) &&
1407                 (nic->pdev->revision < 4))
1408                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1409
1410         val64 = readq(&bar0->tx_fifo_partition_0);
1411         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1412                   &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1413
1414         /*
1415          * Initialization of Tx_PA_CONFIG register to ignore packet
1416          * integrity checking.
1417          */
1418         val64 = readq(&bar0->tx_pa_cfg);
1419         val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1420             TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1421         writeq(val64, &bar0->tx_pa_cfg);
1422
1423         /* Rx DMA intialization. */
1424         val64 = 0;
1425         for (i = 0; i < config->rx_ring_num; i++) {
1426                 val64 |=
1427                     vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1428                          3);
1429         }
1430         writeq(val64, &bar0->rx_queue_priority);
1431
1432         /*
1433          * Allocating equal share of memory to all the
1434          * configured Rings.
1435          */
1436         val64 = 0;
1437         if (nic->device_type & XFRAME_II_DEVICE)
1438                 mem_size = 32;
1439         else
1440                 mem_size = 64;
1441
1442         for (i = 0; i < config->rx_ring_num; i++) {
1443                 switch (i) {
1444                 case 0:
1445                         mem_share = (mem_size / config->rx_ring_num +
1446                                      mem_size % config->rx_ring_num);
1447                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1448                         continue;
1449                 case 1:
1450                         mem_share = (mem_size / config->rx_ring_num);
1451                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1452                         continue;
1453                 case 2:
1454                         mem_share = (mem_size / config->rx_ring_num);
1455                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1456                         continue;
1457                 case 3:
1458                         mem_share = (mem_size / config->rx_ring_num);
1459                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1460                         continue;
1461                 case 4:
1462                         mem_share = (mem_size / config->rx_ring_num);
1463                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1464                         continue;
1465                 case 5:
1466                         mem_share = (mem_size / config->rx_ring_num);
1467                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1468                         continue;
1469                 case 6:
1470                         mem_share = (mem_size / config->rx_ring_num);
1471                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1472                         continue;
1473                 case 7:
1474                         mem_share = (mem_size / config->rx_ring_num);
1475                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1476                         continue;
1477                 }
1478         }
1479         writeq(val64, &bar0->rx_queue_cfg);
1480
1481         /*
1482          * Filling Tx round robin registers
1483          * as per the number of FIFOs for equal scheduling priority
1484          */
1485         switch (config->tx_fifo_num) {
1486         case 1:
1487                 val64 = 0x0;
1488                 writeq(val64, &bar0->tx_w_round_robin_0);
1489                 writeq(val64, &bar0->tx_w_round_robin_1);
1490                 writeq(val64, &bar0->tx_w_round_robin_2);
1491                 writeq(val64, &bar0->tx_w_round_robin_3);
1492                 writeq(val64, &bar0->tx_w_round_robin_4);
1493                 break;
1494         case 2:
1495                 val64 = 0x0001000100010001ULL;
1496                 writeq(val64, &bar0->tx_w_round_robin_0);
1497                 writeq(val64, &bar0->tx_w_round_robin_1);
1498                 writeq(val64, &bar0->tx_w_round_robin_2);
1499                 writeq(val64, &bar0->tx_w_round_robin_3);
1500                 val64 = 0x0001000100000000ULL;
1501                 writeq(val64, &bar0->tx_w_round_robin_4);
1502                 break;
1503         case 3:
1504                 val64 = 0x0001020001020001ULL;
1505                 writeq(val64, &bar0->tx_w_round_robin_0);
1506                 val64 = 0x0200010200010200ULL;
1507                 writeq(val64, &bar0->tx_w_round_robin_1);
1508                 val64 = 0x0102000102000102ULL;
1509                 writeq(val64, &bar0->tx_w_round_robin_2);
1510                 val64 = 0x0001020001020001ULL;
1511                 writeq(val64, &bar0->tx_w_round_robin_3);
1512                 val64 = 0x0200010200000000ULL;
1513                 writeq(val64, &bar0->tx_w_round_robin_4);
1514                 break;
1515         case 4:
1516                 val64 = 0x0001020300010203ULL;
1517                 writeq(val64, &bar0->tx_w_round_robin_0);
1518                 writeq(val64, &bar0->tx_w_round_robin_1);
1519                 writeq(val64, &bar0->tx_w_round_robin_2);
1520                 writeq(val64, &bar0->tx_w_round_robin_3);
1521                 val64 = 0x0001020300000000ULL;
1522                 writeq(val64, &bar0->tx_w_round_robin_4);
1523                 break;
1524         case 5:
1525                 val64 = 0x0001020304000102ULL;
1526                 writeq(val64, &bar0->tx_w_round_robin_0);
1527                 val64 = 0x0304000102030400ULL;
1528                 writeq(val64, &bar0->tx_w_round_robin_1);
1529                 val64 = 0x0102030400010203ULL;
1530                 writeq(val64, &bar0->tx_w_round_robin_2);
1531                 val64 = 0x0400010203040001ULL;
1532                 writeq(val64, &bar0->tx_w_round_robin_3);
1533                 val64 = 0x0203040000000000ULL;
1534                 writeq(val64, &bar0->tx_w_round_robin_4);
1535                 break;
1536         case 6:
1537                 val64 = 0x0001020304050001ULL;
1538                 writeq(val64, &bar0->tx_w_round_robin_0);
1539                 val64 = 0x0203040500010203ULL;
1540                 writeq(val64, &bar0->tx_w_round_robin_1);
1541                 val64 = 0x0405000102030405ULL;
1542                 writeq(val64, &bar0->tx_w_round_robin_2);
1543                 val64 = 0x0001020304050001ULL;
1544                 writeq(val64, &bar0->tx_w_round_robin_3);
1545                 val64 = 0x0203040500000000ULL;
1546                 writeq(val64, &bar0->tx_w_round_robin_4);
1547                 break;
1548         case 7:
1549                 val64 = 0x0001020304050600ULL;
1550                 writeq(val64, &bar0->tx_w_round_robin_0);
1551                 val64 = 0x0102030405060001ULL;
1552                 writeq(val64, &bar0->tx_w_round_robin_1);
1553                 val64 = 0x0203040506000102ULL;
1554                 writeq(val64, &bar0->tx_w_round_robin_2);
1555                 val64 = 0x0304050600010203ULL;
1556                 writeq(val64, &bar0->tx_w_round_robin_3);
1557                 val64 = 0x0405060000000000ULL;
1558                 writeq(val64, &bar0->tx_w_round_robin_4);
1559                 break;
1560         case 8:
1561                 val64 = 0x0001020304050607ULL;
1562                 writeq(val64, &bar0->tx_w_round_robin_0);
1563                 writeq(val64, &bar0->tx_w_round_robin_1);
1564                 writeq(val64, &bar0->tx_w_round_robin_2);
1565                 writeq(val64, &bar0->tx_w_round_robin_3);
1566                 val64 = 0x0001020300000000ULL;
1567                 writeq(val64, &bar0->tx_w_round_robin_4);
1568                 break;
1569         }
1570
1571         /* Enable all configured Tx FIFO partitions */
1572         val64 = readq(&bar0->tx_fifo_partition_0);
1573         val64 |= (TX_FIFO_PARTITION_EN);
1574         writeq(val64, &bar0->tx_fifo_partition_0);
1575
1576         /* Filling the Rx round robin registers as per the
1577          * number of Rings and steering based on QoS.
1578          */
1579         switch (config->rx_ring_num) {
1580         case 1:
1581                 val64 = 0x8080808080808080ULL;
1582                 writeq(val64, &bar0->rts_qos_steering);
1583                 break;
1584         case 2:
1585                 val64 = 0x0000010000010000ULL;
1586                 writeq(val64, &bar0->rx_w_round_robin_0);
1587                 val64 = 0x0100000100000100ULL;
1588                 writeq(val64, &bar0->rx_w_round_robin_1);
1589                 val64 = 0x0001000001000001ULL;
1590                 writeq(val64, &bar0->rx_w_round_robin_2);
1591                 val64 = 0x0000010000010000ULL;
1592                 writeq(val64, &bar0->rx_w_round_robin_3);
1593                 val64 = 0x0100000000000000ULL;
1594                 writeq(val64, &bar0->rx_w_round_robin_4);
1595
1596                 val64 = 0x8080808040404040ULL;
1597                 writeq(val64, &bar0->rts_qos_steering);
1598                 break;
1599         case 3:
1600                 val64 = 0x0001000102000001ULL;
1601                 writeq(val64, &bar0->rx_w_round_robin_0);
1602                 val64 = 0x0001020000010001ULL;
1603                 writeq(val64, &bar0->rx_w_round_robin_1);
1604                 val64 = 0x0200000100010200ULL;
1605                 writeq(val64, &bar0->rx_w_round_robin_2);
1606                 val64 = 0x0001000102000001ULL;
1607                 writeq(val64, &bar0->rx_w_round_robin_3);
1608                 val64 = 0x0001020000000000ULL;
1609                 writeq(val64, &bar0->rx_w_round_robin_4);
1610
1611                 val64 = 0x8080804040402020ULL;
1612                 writeq(val64, &bar0->rts_qos_steering);
1613                 break;
1614         case 4:
1615                 val64 = 0x0001020300010200ULL;
1616                 writeq(val64, &bar0->rx_w_round_robin_0);
1617                 val64 = 0x0100000102030001ULL;
1618                 writeq(val64, &bar0->rx_w_round_robin_1);
1619                 val64 = 0x0200010000010203ULL;
1620                 writeq(val64, &bar0->rx_w_round_robin_2);
1621                 val64 = 0x0001020001000001ULL;
1622                 writeq(val64, &bar0->rx_w_round_robin_3);
1623                 val64 = 0x0203000100000000ULL;
1624                 writeq(val64, &bar0->rx_w_round_robin_4);
1625
1626                 val64 = 0x8080404020201010ULL;
1627                 writeq(val64, &bar0->rts_qos_steering);
1628                 break;
1629         case 5:
1630                 val64 = 0x0001000203000102ULL;
1631                 writeq(val64, &bar0->rx_w_round_robin_0);
1632                 val64 = 0x0001020001030004ULL;
1633                 writeq(val64, &bar0->rx_w_round_robin_1);
1634                 val64 = 0x0001000203000102ULL;
1635                 writeq(val64, &bar0->rx_w_round_robin_2);
1636                 val64 = 0x0001020001030004ULL;
1637                 writeq(val64, &bar0->rx_w_round_robin_3);
1638                 val64 = 0x0001000000000000ULL;
1639                 writeq(val64, &bar0->rx_w_round_robin_4);
1640
1641                 val64 = 0x8080404020201008ULL;
1642                 writeq(val64, &bar0->rts_qos_steering);
1643                 break;
1644         case 6:
1645                 val64 = 0x0001020304000102ULL;
1646                 writeq(val64, &bar0->rx_w_round_robin_0);
1647                 val64 = 0x0304050001020001ULL;
1648                 writeq(val64, &bar0->rx_w_round_robin_1);
1649                 val64 = 0x0203000100000102ULL;
1650                 writeq(val64, &bar0->rx_w_round_robin_2);
1651                 val64 = 0x0304000102030405ULL;
1652                 writeq(val64, &bar0->rx_w_round_robin_3);
1653                 val64 = 0x0001000200000000ULL;
1654                 writeq(val64, &bar0->rx_w_round_robin_4);
1655
1656                 val64 = 0x8080404020100804ULL;
1657                 writeq(val64, &bar0->rts_qos_steering);
1658                 break;
1659         case 7:
1660                 val64 = 0x0001020001020300ULL;
1661                 writeq(val64, &bar0->rx_w_round_robin_0);
1662                 val64 = 0x0102030400010203ULL;
1663                 writeq(val64, &bar0->rx_w_round_robin_1);
1664                 val64 = 0x0405060001020001ULL;
1665                 writeq(val64, &bar0->rx_w_round_robin_2);
1666                 val64 = 0x0304050000010200ULL;
1667                 writeq(val64, &bar0->rx_w_round_robin_3);
1668                 val64 = 0x0102030000000000ULL;
1669                 writeq(val64, &bar0->rx_w_round_robin_4);
1670
1671                 val64 = 0x8080402010080402ULL;
1672                 writeq(val64, &bar0->rts_qos_steering);
1673                 break;
1674         case 8:
1675                 val64 = 0x0001020300040105ULL;
1676                 writeq(val64, &bar0->rx_w_round_robin_0);
1677                 val64 = 0x0200030106000204ULL;
1678                 writeq(val64, &bar0->rx_w_round_robin_1);
1679                 val64 = 0x0103000502010007ULL;
1680                 writeq(val64, &bar0->rx_w_round_robin_2);
1681                 val64 = 0x0304010002060500ULL;
1682                 writeq(val64, &bar0->rx_w_round_robin_3);
1683                 val64 = 0x0103020400000000ULL;
1684                 writeq(val64, &bar0->rx_w_round_robin_4);
1685
1686                 val64 = 0x8040201008040201ULL;
1687                 writeq(val64, &bar0->rts_qos_steering);
1688                 break;
1689         }
1690
1691         /* UDP Fix */
1692         val64 = 0;
1693         for (i = 0; i < 8; i++)
1694                 writeq(val64, &bar0->rts_frm_len_n[i]);
1695
1696         /* Set the default rts frame length for the rings configured */
1697         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1698         for (i = 0 ; i < config->rx_ring_num ; i++)
1699                 writeq(val64, &bar0->rts_frm_len_n[i]);
1700
1701         /* Set the frame length for the configured rings
1702          * desired by the user
1703          */
1704         for (i = 0; i < config->rx_ring_num; i++) {
1705                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1706                  * specified frame length steering.
1707                  * If the user provides the frame length then program
1708                  * the rts_frm_len register for those values or else
1709                  * leave it as it is.
1710                  */
1711                 if (rts_frm_len[i] != 0) {
1712                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1713                                 &bar0->rts_frm_len_n[i]);
1714                 }
1715         }
1716
1717         /* Disable differentiated services steering logic */
1718         for (i = 0; i < 64; i++) {
1719                 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1720                         DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1721                                 dev->name);
1722                         DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1723                         return -ENODEV;
1724                 }
1725         }
1726
1727         /* Program statistics memory */
1728         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1729
1730         if (nic->device_type == XFRAME_II_DEVICE) {
1731                 val64 = STAT_BC(0x320);
1732                 writeq(val64, &bar0->stat_byte_cnt);
1733         }
1734
1735         /*
1736          * Initializing the sampling rate for the device to calculate the
1737          * bandwidth utilization.
1738          */
1739         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1740             MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1741         writeq(val64, &bar0->mac_link_util);
1742
1743         /*
1744          * Initializing the Transmit and Receive Traffic Interrupt
1745          * Scheme.
1746          */
1747
1748         /* Initialize TTI */
1749         if (SUCCESS != init_tti(nic, nic->last_link_state))
1750                 return -ENODEV;
1751
1752         /* RTI Initialization */
1753         if (nic->device_type == XFRAME_II_DEVICE) {
1754                 /*
1755                  * Programmed to generate Apprx 500 Intrs per
1756                  * second
1757                  */
1758                 int count = (nic->config.bus_speed * 125)/4;
1759                 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1760         } else
1761                 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1762         val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1763                  RTI_DATA1_MEM_RX_URNG_B(0x10) |
1764                  RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1765
1766         writeq(val64, &bar0->rti_data1_mem);
1767
1768         val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1769                 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1770         if (nic->config.intr_type == MSI_X)
1771             val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1772                         RTI_DATA2_MEM_RX_UFC_D(0x40));
1773         else
1774             val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1775                         RTI_DATA2_MEM_RX_UFC_D(0x80));
1776         writeq(val64, &bar0->rti_data2_mem);
1777
1778         for (i = 0; i < config->rx_ring_num; i++) {
1779                 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1780                                 | RTI_CMD_MEM_OFFSET(i);
1781                 writeq(val64, &bar0->rti_command_mem);
1782
1783                 /*
1784                  * Once the operation completes, the Strobe bit of the
1785                  * command register will be reset. We poll for this
1786                  * particular condition. We wait for a maximum of 500ms
1787                  * for the operation to complete, if it's not complete
1788                  * by then we return error.
1789                  */
1790                 time = 0;
1791                 while (TRUE) {
1792                         val64 = readq(&bar0->rti_command_mem);
1793                         if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1794                                 break;
1795
1796                         if (time > 10) {
1797                                 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1798                                           dev->name);
1799                                 return -ENODEV;
1800                         }
1801                         time++;
1802                         msleep(50);
1803                 }
1804         }
1805
1806         /*
1807          * Initializing proper values as Pause threshold into all
1808          * the 8 Queues on Rx side.
1809          */
1810         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1811         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1812
1813         /* Disable RMAC PAD STRIPPING */
1814         add = &bar0->mac_cfg;
1815         val64 = readq(&bar0->mac_cfg);
1816         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1817         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1818         writel((u32) (val64), add);
1819         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1820         writel((u32) (val64 >> 32), (add + 4));
1821         val64 = readq(&bar0->mac_cfg);
1822
1823         /* Enable FCS stripping by adapter */
1824         add = &bar0->mac_cfg;
1825         val64 = readq(&bar0->mac_cfg);
1826         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1827         if (nic->device_type == XFRAME_II_DEVICE)
1828                 writeq(val64, &bar0->mac_cfg);
1829         else {
1830                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1831                 writel((u32) (val64), add);
1832                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1833                 writel((u32) (val64 >> 32), (add + 4));
1834         }
1835
1836         /*
1837          * Set the time value to be inserted in the pause frame
1838          * generated by xena.
1839          */
1840         val64 = readq(&bar0->rmac_pause_cfg);
1841         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1842         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1843         writeq(val64, &bar0->rmac_pause_cfg);
1844
1845         /*
1846          * Set the Threshold Limit for Generating the pause frame
1847          * If the amount of data in any Queue exceeds ratio of
1848          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1849          * pause frame is generated
1850          */
1851         val64 = 0;
1852         for (i = 0; i < 4; i++) {
1853                 val64 |=
1854                     (((u64) 0xFF00 | nic->mac_control.
1855                       mc_pause_threshold_q0q3)
1856                      << (i * 2 * 8));
1857         }
1858         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1859
1860         val64 = 0;
1861         for (i = 0; i < 4; i++) {
1862                 val64 |=
1863                     (((u64) 0xFF00 | nic->mac_control.
1864                       mc_pause_threshold_q4q7)
1865                      << (i * 2 * 8));
1866         }
1867         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1868
1869         /*
1870          * TxDMA will stop Read request if the number of read split has
1871          * exceeded the limit pointed by shared_splits
1872          */
1873         val64 = readq(&bar0->pic_control);
1874         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1875         writeq(val64, &bar0->pic_control);
1876
1877         if (nic->config.bus_speed == 266) {
1878                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1879                 writeq(0x0, &bar0->read_retry_delay);
1880                 writeq(0x0, &bar0->write_retry_delay);
1881         }
1882
1883         /*
1884          * Programming the Herc to split every write transaction
1885          * that does not start on an ADB to reduce disconnects.
1886          */
1887         if (nic->device_type == XFRAME_II_DEVICE) {
1888                 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1889                         MISC_LINK_STABILITY_PRD(3);
1890                 writeq(val64, &bar0->misc_control);
1891                 val64 = readq(&bar0->pic_control2);
1892                 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1893                 writeq(val64, &bar0->pic_control2);
1894         }
1895         if (strstr(nic->product_name, "CX4")) {
1896                 val64 = TMAC_AVG_IPG(0x17);
1897                 writeq(val64, &bar0->tmac_avg_ipg);
1898         }
1899
1900         return SUCCESS;
1901 }
1902 #define LINK_UP_DOWN_INTERRUPT          1
1903 #define MAC_RMAC_ERR_TIMER              2
1904
1905 static int s2io_link_fault_indication(struct s2io_nic *nic)
1906 {
1907         if (nic->config.intr_type != INTA)
1908                 return MAC_RMAC_ERR_TIMER;
1909         if (nic->device_type == XFRAME_II_DEVICE)
1910                 return LINK_UP_DOWN_INTERRUPT;
1911         else
1912                 return MAC_RMAC_ERR_TIMER;
1913 }
1914
1915 /**
1916  *  do_s2io_write_bits -  update alarm bits in alarm register
1917  *  @value: alarm bits
1918  *  @flag: interrupt status
1919  *  @addr: address value
1920  *  Description: update alarm bits in alarm register
1921  *  Return Value:
1922  *  NONE.
1923  */
1924 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1925 {
1926         u64 temp64;
1927
1928         temp64 = readq(addr);
1929
1930         if(flag == ENABLE_INTRS)
1931                 temp64 &= ~((u64) value);
1932         else
1933                 temp64 |= ((u64) value);
1934         writeq(temp64, addr);
1935 }
1936
1937 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1938 {
1939         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1940         register u64 gen_int_mask = 0;
1941
1942         if (mask & TX_DMA_INTR) {
1943
1944                 gen_int_mask |= TXDMA_INT_M;
1945
1946                 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1947                                 TXDMA_PCC_INT | TXDMA_TTI_INT |
1948                                 TXDMA_LSO_INT | TXDMA_TPA_INT |
1949                                 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1950
1951                 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1952                                 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1953                                 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1954                                 &bar0->pfc_err_mask);
1955
1956                 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1957                                 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1958                                 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1959
1960                 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1961                                 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1962                                 PCC_N_SERR | PCC_6_COF_OV_ERR |
1963                                 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1964                                 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1965                                 PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
1966
1967                 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1968                                 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1969
1970                 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1971                                 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1972                                 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1973                                 flag, &bar0->lso_err_mask);
1974
1975                 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1976                                 flag, &bar0->tpa_err_mask);
1977
1978                 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1979
1980         }
1981
1982         if (mask & TX_MAC_INTR) {
1983                 gen_int_mask |= TXMAC_INT_M;
1984                 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1985                                 &bar0->mac_int_mask);
1986                 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1987                                 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1988                                 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1989                                 flag, &bar0->mac_tmac_err_mask);
1990         }
1991
1992         if (mask & TX_XGXS_INTR) {
1993                 gen_int_mask |= TXXGXS_INT_M;
1994                 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1995                                 &bar0->xgxs_int_mask);
1996                 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1997                                 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1998                                 flag, &bar0->xgxs_txgxs_err_mask);
1999         }
2000
2001         if (mask & RX_DMA_INTR) {
2002                 gen_int_mask |= RXDMA_INT_M;
2003                 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
2004                                 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
2005                                 flag, &bar0->rxdma_int_mask);
2006                 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
2007                                 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
2008                                 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
2009                                 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
2010                 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
2011                                 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
2012                                 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
2013                                 &bar0->prc_pcix_err_mask);
2014                 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
2015                                 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
2016                                 &bar0->rpa_err_mask);
2017                 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
2018                                 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2019                                 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2020                                 RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
2021                                 flag, &bar0->rda_err_mask);
2022                 do_s2io_write_bits(RTI_SM_ERR_ALARM |
2023                                 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2024                                 flag, &bar0->rti_err_mask);
2025         }
2026
2027         if (mask & RX_MAC_INTR) {
2028                 gen_int_mask |= RXMAC_INT_M;
2029                 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2030                                 &bar0->mac_int_mask);
2031                 do_s2io_write_bits(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2032                                 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2033                                 RMAC_DOUBLE_ECC_ERR |
2034                                 RMAC_LINK_STATE_CHANGE_INT,
2035                                 flag, &bar0->mac_rmac_err_mask);
2036         }
2037
2038         if (mask & RX_XGXS_INTR)
2039         {
2040                 gen_int_mask |= RXXGXS_INT_M;
2041                 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2042                                 &bar0->xgxs_int_mask);
2043                 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2044                                 &bar0->xgxs_rxgxs_err_mask);
2045         }
2046
2047         if (mask & MC_INTR) {
2048                 gen_int_mask |= MC_INT_M;
2049                 do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
2050                 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2051                                 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2052                                 &bar0->mc_err_mask);
2053         }
2054         nic->general_int_mask = gen_int_mask;
2055
2056         /* Remove this line when alarm interrupts are enabled */
2057         nic->general_int_mask = 0;
2058 }
2059 /**
2060  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
2061  *  @nic: device private variable,
2062  *  @mask: A mask indicating which Intr block must be modified and,
2063  *  @flag: A flag indicating whether to enable or disable the Intrs.
2064  *  Description: This function will either disable or enable the interrupts
2065  *  depending on the flag argument. The mask argument can be used to
2066  *  enable/disable any Intr block.
2067  *  Return Value: NONE.
2068  */
2069
2070 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2071 {
2072         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2073         register u64 temp64 = 0, intr_mask = 0;
2074
2075         intr_mask = nic->general_int_mask;
2076
2077         /*  Top level interrupt classification */
2078         /*  PIC Interrupts */
2079         if (mask & TX_PIC_INTR) {
2080                 /*  Enable PIC Intrs in the general intr mask register */
2081                 intr_mask |= TXPIC_INT_M;
2082                 if (flag == ENABLE_INTRS) {
2083                         /*
2084                          * If Hercules adapter enable GPIO otherwise
2085                          * disable all PCIX, Flash, MDIO, IIC and GPIO
2086                          * interrupts for now.
2087                          * TODO
2088                          */
2089                         if (s2io_link_fault_indication(nic) ==
2090                                         LINK_UP_DOWN_INTERRUPT ) {
2091                                 do_s2io_write_bits(PIC_INT_GPIO, flag,
2092                                                 &bar0->pic_int_mask);
2093                                 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2094                                                 &bar0->gpio_int_mask);
2095                         } else
2096                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2097                 } else if (flag == DISABLE_INTRS) {
2098                         /*
2099                          * Disable PIC Intrs in the general
2100                          * intr mask register
2101                          */
2102                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2103                 }
2104         }
2105
2106         /*  Tx traffic interrupts */
2107         if (mask & TX_TRAFFIC_INTR) {
2108                 intr_mask |= TXTRAFFIC_INT_M;
2109                 if (flag == ENABLE_INTRS) {
2110                         /*
2111                          * Enable all the Tx side interrupts
2112                          * writing 0 Enables all 64 TX interrupt levels
2113                          */
2114                         writeq(0x0, &bar0->tx_traffic_mask);
2115                 } else if (flag == DISABLE_INTRS) {
2116                         /*
2117                          * Disable Tx Traffic Intrs in the general intr mask
2118                          * register.
2119                          */
2120                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2121                 }
2122         }
2123
2124         /*  Rx traffic interrupts */
2125         if (mask & RX_TRAFFIC_INTR) {
2126                 intr_mask |= RXTRAFFIC_INT_M;
2127                 if (flag == ENABLE_INTRS) {
2128                         /* writing 0 Enables all 8 RX interrupt levels */
2129                         writeq(0x0, &bar0->rx_traffic_mask);
2130                 } else if (flag == DISABLE_INTRS) {
2131                         /*
2132                          * Disable Rx Traffic Intrs in the general intr mask
2133                          * register.
2134                          */
2135                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2136                 }
2137         }
2138
2139         temp64 = readq(&bar0->general_int_mask);
2140         if (flag == ENABLE_INTRS)
2141                 temp64 &= ~((u64) intr_mask);
2142         else
2143                 temp64 = DISABLE_ALL_INTRS;
2144         writeq(temp64, &bar0->general_int_mask);
2145
2146         nic->general_int_mask = readq(&bar0->general_int_mask);
2147 }
2148
2149 /**
2150  *  verify_pcc_quiescent- Checks for PCC quiescent state
2151  *  Return: 1 If PCC is quiescence
2152  *          0 If PCC is not quiescence
2153  */
2154 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2155 {
2156         int ret = 0, herc;
2157         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2158         u64 val64 = readq(&bar0->adapter_status);
2159
2160         herc = (sp->device_type == XFRAME_II_DEVICE);
2161
2162         if (flag == FALSE) {
2163                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2164                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2165                                 ret = 1;
2166                 } else {
2167                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2168                                 ret = 1;
2169                 }
2170         } else {
2171                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2172                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2173                              ADAPTER_STATUS_RMAC_PCC_IDLE))
2174                                 ret = 1;
2175                 } else {
2176                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2177                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2178                                 ret = 1;
2179                 }
2180         }
2181
2182         return ret;
2183 }
2184 /**
2185  *  verify_xena_quiescence - Checks whether the H/W is ready
2186  *  Description: Returns whether the H/W is ready to go or not. Depending
2187  *  on whether adapter enable bit was written or not the comparison
2188  *  differs and the calling function passes the input argument flag to
2189  *  indicate this.
2190  *  Return: 1 If xena is quiescence
2191  *          0 If Xena is not quiescence
2192  */
2193
2194 static int verify_xena_quiescence(struct s2io_nic *sp)
2195 {
2196         int  mode;
2197         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2198         u64 val64 = readq(&bar0->adapter_status);
2199         mode = s2io_verify_pci_mode(sp);
2200
2201         if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2202                 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2203                 return 0;
2204         }
2205         if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2206         DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2207                 return 0;
2208         }
2209         if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2210                 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2211                 return 0;
2212         }
2213         if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2214                 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2215                 return 0;
2216         }
2217         if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2218                 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2219                 return 0;
2220         }
2221         if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2222                 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2223                 return 0;
2224         }
2225         if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2226                 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2227                 return 0;
2228         }
2229         if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2230                 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2231                 return 0;
2232         }
2233
2234         /*
2235          * In PCI 33 mode, the P_PLL is not used, and therefore,
2236          * the the P_PLL_LOCK bit in the adapter_status register will
2237          * not be asserted.
2238          */
2239         if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2240                 sp->device_type == XFRAME_II_DEVICE && mode !=
2241                 PCI_MODE_PCI_33) {
2242                 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2243                 return 0;
2244         }
2245         if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2246                         ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2247                 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2248                 return 0;
2249         }
2250         return 1;
2251 }
2252
2253 /**
2254  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
2255  * @sp: Pointer to device specifc structure
2256  * Description :
2257  * New procedure to clear mac address reading  problems on Alpha platforms
2258  *
2259  */
2260
2261 static void fix_mac_address(struct s2io_nic * sp)
2262 {
2263         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2264         u64 val64;
2265         int i = 0;
2266
2267         while (fix_mac[i] != END_SIGN) {
2268                 writeq(fix_mac[i++], &bar0->gpio_control);
2269                 udelay(10);
2270                 val64 = readq(&bar0->gpio_control);
2271         }
2272 }
2273
2274 /**
2275  *  start_nic - Turns the device on
2276  *  @nic : device private variable.
2277  *  Description:
2278  *  This function actually turns the device on. Before this  function is
2279  *  called,all Registers are configured from their reset states
2280  *  and shared memory is allocated but the NIC is still quiescent. On
2281  *  calling this function, the device interrupts are cleared and the NIC is
2282  *  literally switched on by writing into the adapter control register.
2283  *  Return Value:
2284  *  SUCCESS on success and -1 on failure.
2285  */
2286
2287 static int start_nic(struct s2io_nic *nic)
2288 {
2289         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2290         struct net_device *dev = nic->dev;
2291         register u64 val64 = 0;
2292         u16 subid, i;
2293         struct mac_info *mac_control;
2294         struct config_param *config;
2295
2296         mac_control = &nic->mac_control;
2297         config = &nic->config;
2298
2299         /*  PRC Initialization and configuration */
2300         for (i = 0; i < config->rx_ring_num; i++) {
2301                 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
2302                        &bar0->prc_rxd0_n[i]);
2303
2304                 val64 = readq(&bar0->prc_ctrl_n[i]);
2305                 if (nic->rxd_mode == RXD_MODE_1)
2306                         val64 |= PRC_CTRL_RC_ENABLED;
2307                 else
2308                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2309                 if (nic->device_type == XFRAME_II_DEVICE)
2310                         val64 |= PRC_CTRL_GROUP_READS;
2311                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2312                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2313                 writeq(val64, &bar0->prc_ctrl_n[i]);
2314         }
2315
2316         if (nic->rxd_mode == RXD_MODE_3B) {
2317                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2318                 val64 = readq(&bar0->rx_pa_cfg);
2319                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2320                 writeq(val64, &bar0->rx_pa_cfg);
2321         }
2322
2323         if (vlan_tag_strip == 0) {
2324                 val64 = readq(&bar0->rx_pa_cfg);
2325                 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2326                 writeq(val64, &bar0->rx_pa_cfg);
2327                 vlan_strip_flag = 0;
2328         }
2329
2330         /*
2331          * Enabling MC-RLDRAM. After enabling the device, we timeout
2332          * for around 100ms, which is approximately the time required
2333          * for the device to be ready for operation.
2334          */
2335         val64 = readq(&bar0->mc_rldram_mrs);
2336         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2337         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2338         val64 = readq(&bar0->mc_rldram_mrs);
2339
2340         msleep(100);    /* Delay by around 100 ms. */
2341
2342         /* Enabling ECC Protection. */
2343         val64 = readq(&bar0->adapter_control);
2344         val64 &= ~ADAPTER_ECC_EN;
2345         writeq(val64, &bar0->adapter_control);
2346
2347         /*
2348          * Verify if the device is ready to be enabled, if so enable
2349          * it.
2350          */
2351         val64 = readq(&bar0->adapter_status);
2352         if (!verify_xena_quiescence(nic)) {
2353                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2354                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2355                           (unsigned long long) val64);
2356                 return FAILURE;
2357         }
2358
2359         /*
2360          * With some switches, link might be already up at this point.
2361          * Because of this weird behavior, when we enable laser,
2362          * we may not get link. We need to handle this. We cannot
2363          * figure out which switch is misbehaving. So we are forced to
2364          * make a global change.
2365          */
2366
2367         /* Enabling Laser. */
2368         val64 = readq(&bar0->adapter_control);
2369         val64 |= ADAPTER_EOI_TX_ON;
2370         writeq(val64, &bar0->adapter_control);
2371
2372         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2373                 /*
2374                  * Dont see link state interrupts initally on some switches,
2375                  * so directly scheduling the link state task here.
2376                  */
2377                 schedule_work(&nic->set_link_task);
2378         }
2379         /* SXE-002: Initialize link and activity LED */
2380         subid = nic->pdev->subsystem_device;
2381         if (((subid & 0xFF) >= 0x07) &&
2382             (nic->device_type == XFRAME_I_DEVICE)) {
2383                 val64 = readq(&bar0->gpio_control);
2384                 val64 |= 0x0000800000000000ULL;
2385                 writeq(val64, &bar0->gpio_control);
2386                 val64 = 0x0411040400000000ULL;
2387                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2388         }
2389
2390         return SUCCESS;
2391 }
2392 /**
2393  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2394  */
2395 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2396                                         TxD *txdlp, int get_off)
2397 {
2398         struct s2io_nic *nic = fifo_data->nic;
2399         struct sk_buff *skb;
2400         struct TxD *txds;
2401         u16 j, frg_cnt;
2402
2403         txds = txdlp;
2404         if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2405                 pci_unmap_single(nic->pdev, (dma_addr_t)
2406                         txds->Buffer_Pointer, sizeof(u64),
2407                         PCI_DMA_TODEVICE);
2408                 txds++;
2409         }
2410
2411         skb = (struct sk_buff *) ((unsigned long)
2412                         txds->Host_Control);
2413         if (!skb) {
2414                 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2415                 return NULL;
2416         }
2417         pci_unmap_single(nic->pdev, (dma_addr_t)
2418                          txds->Buffer_Pointer,
2419                          skb->len - skb->data_len,
2420                          PCI_DMA_TODEVICE);
2421         frg_cnt = skb_shinfo(skb)->nr_frags;
2422         if (frg_cnt) {
2423                 txds++;
2424                 for (j = 0; j < frg_cnt; j++, txds++) {
2425                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2426                         if (!txds->Buffer_Pointer)
2427                                 break;
2428                         pci_unmap_page(nic->pdev, (dma_addr_t)
2429                                         txds->Buffer_Pointer,
2430                                        frag->size, PCI_DMA_TODEVICE);
2431                 }
2432         }
2433         memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
2434         return(skb);
2435 }
2436
2437 /**
2438  *  free_tx_buffers - Free all queued Tx buffers
2439  *  @nic : device private variable.
2440  *  Description:
2441  *  Free all queued Tx buffers.
2442  *  Return Value: void
2443 */
2444
2445 static void free_tx_buffers(struct s2io_nic *nic)
2446 {
2447         struct net_device *dev = nic->dev;
2448         struct sk_buff *skb;
2449         struct TxD *txdp;
2450         int i, j;
2451         struct mac_info *mac_control;
2452         struct config_param *config;
2453         int cnt = 0;
2454
2455         mac_control = &nic->mac_control;
2456         config = &nic->config;
2457
2458         for (i = 0; i < config->tx_fifo_num; i++) {
2459                 unsigned long flags;
2460                 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags);
2461                 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2462                         txdp = (struct TxD *) \
2463                         mac_control->fifos[i].list_info[j].list_virt_addr;
2464                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2465                         if (skb) {
2466                                 nic->mac_control.stats_info->sw_stat.mem_freed
2467                                         += skb->truesize;
2468                                 dev_kfree_skb(skb);
2469                                 cnt++;
2470                         }
2471                 }
2472                 DBG_PRINT(INTR_DBG,
2473                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2474                           dev->name, cnt, i);
2475                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2476                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2477                 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock, flags);
2478         }
2479 }
2480
2481 /**
2482  *   stop_nic -  To stop the nic
2483  *   @nic ; device private variable.
2484  *   Description:
2485  *   This function does exactly the opposite of what the start_nic()
2486  *   function does. This function is called to stop the device.
2487  *   Return Value:
2488  *   void.
2489  */
2490
2491 static void stop_nic(struct s2io_nic *nic)
2492 {
2493         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2494         register u64 val64 = 0;
2495         u16 interruptible;
2496         struct mac_info *mac_control;
2497         struct config_param *config;
2498
2499         mac_control = &nic->mac_control;
2500         config = &nic->config;
2501
2502         /*  Disable all interrupts */
2503         en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2504         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2505         interruptible |= TX_PIC_INTR;
2506         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2507
2508         /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2509         val64 = readq(&bar0->adapter_control);
2510         val64 &= ~(ADAPTER_CNTL_EN);
2511         writeq(val64, &bar0->adapter_control);
2512 }
2513
2514 /**
2515  *  fill_rx_buffers - Allocates the Rx side skbs
2516  *  @nic:  device private variable
2517  *  @ring_no: ring number
2518  *  Description:
2519  *  The function allocates Rx side skbs and puts the physical
2520  *  address of these buffers into the RxD buffer pointers, so that the NIC
2521  *  can DMA the received frame into these locations.
2522  *  The NIC supports 3 receive modes, viz
2523  *  1. single buffer,
2524  *  2. three buffer and
2525  *  3. Five buffer modes.
2526  *  Each mode defines how many fragments the received frame will be split
2527  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2528  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2529  *  is split into 3 fragments. As of now only single buffer mode is
2530  *  supported.
2531  *   Return Value:
2532  *  SUCCESS on success or an appropriate -ve value on failure.
2533  */
2534
2535 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2536 {
2537         struct net_device *dev = nic->dev;
2538         struct sk_buff *skb;
2539         struct RxD_t *rxdp;
2540         int off, off1, size, block_no, block_no1;
2541         u32 alloc_tab = 0;
2542         u32 alloc_cnt;
2543         struct mac_info *mac_control;
2544         struct config_param *config;
2545         u64 tmp;
2546         struct buffAdd *ba;
2547         unsigned long flags;
2548         struct RxD_t *first_rxdp = NULL;
2549         u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2550         struct RxD1 *rxdp1;
2551         struct RxD3 *rxdp3;
2552         struct swStat *stats = &nic->mac_control.stats_info->sw_stat;
2553
2554         mac_control = &nic->mac_control;
2555         config = &nic->config;
2556         alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2557             atomic_read(&nic->rx_bufs_left[ring_no]);
2558
2559         block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
2560         off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2561         while (alloc_tab < alloc_cnt) {
2562                 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2563                     block_index;
2564                 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2565
2566                 rxdp = mac_control->rings[ring_no].
2567                                 rx_blocks[block_no].rxds[off].virt_addr;
2568
2569                 if ((block_no == block_no1) && (off == off1) &&
2570                                         (rxdp->Host_Control)) {
2571                         DBG_PRINT(INTR_DBG, "%s: Get and Put",
2572                                   dev->name);
2573                         DBG_PRINT(INTR_DBG, " info equated\n");
2574                         goto end;
2575                 }
2576                 if (off && (off == rxd_count[nic->rxd_mode])) {
2577                         mac_control->rings[ring_no].rx_curr_put_info.
2578                             block_index++;
2579                         if (mac_control->rings[ring_no].rx_curr_put_info.
2580                             block_index == mac_control->rings[ring_no].
2581                                         block_count)
2582                                 mac_control->rings[ring_no].rx_curr_put_info.
2583                                         block_index = 0;
2584                         block_no = mac_control->rings[ring_no].
2585                                         rx_curr_put_info.block_index;
2586                         if (off == rxd_count[nic->rxd_mode])
2587                                 off = 0;
2588                         mac_control->rings[ring_no].rx_curr_put_info.
2589                                 offset = off;
2590                         rxdp = mac_control->rings[ring_no].
2591                                 rx_blocks[block_no].block_virt_addr;
2592                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2593                                   dev->name, rxdp);
2594                 }
2595                 if(!napi) {
2596                         spin_lock_irqsave(&nic->put_lock, flags);
2597                         mac_control->rings[ring_no].put_pos =
2598                         (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2599                         spin_unlock_irqrestore(&nic->put_lock, flags);
2600                 } else {
2601                         mac_control->rings[ring_no].put_pos =
2602                         (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2603                 }
2604                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2605                         ((nic->rxd_mode == RXD_MODE_3B) &&
2606                                 (rxdp->Control_2 & s2BIT(0)))) {
2607                         mac_control->rings[ring_no].rx_curr_put_info.
2608                                         offset = off;
2609                         goto end;
2610                 }
2611                 /* calculate size of skb based on ring mode */
2612                 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2613                                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2614                 if (nic->rxd_mode == RXD_MODE_1)
2615                         size += NET_IP_ALIGN;
2616                 else
2617                         size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2618
2619                 /* allocate skb */
2620                 skb = dev_alloc_skb(size);
2621                 if(!skb) {
2622                         DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
2623                         DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
2624                         if (first_rxdp) {
2625                                 wmb();
2626                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2627                         }
2628                         nic->mac_control.stats_info->sw_stat. \
2629                                 mem_alloc_fail_cnt++;
2630                         return -ENOMEM ;
2631                 }
2632                 nic->mac_control.stats_info->sw_stat.mem_allocated
2633                         += skb->truesize;
2634                 if (nic->rxd_mode == RXD_MODE_1) {
2635                         /* 1 buffer mode - normal operation mode */
2636                         rxdp1 = (struct RxD1*)rxdp;
2637                         memset(rxdp, 0, sizeof(struct RxD1));
2638                         skb_reserve(skb, NET_IP_ALIGN);
2639                         rxdp1->Buffer0_ptr = pci_map_single
2640                             (nic->pdev, skb->data, size - NET_IP_ALIGN,
2641                                 PCI_DMA_FROMDEVICE);
2642                         if( (rxdp1->Buffer0_ptr == 0) ||
2643                                 (rxdp1->Buffer0_ptr ==
2644                                 DMA_ERROR_CODE))
2645                                 goto pci_map_failed;
2646
2647                         rxdp->Control_2 =
2648                                 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2649
2650                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2651                         /*
2652                          * 2 buffer mode -
2653                          * 2 buffer mode provides 128
2654                          * byte aligned receive buffers.
2655                          */
2656
2657                         rxdp3 = (struct RxD3*)rxdp;
2658                         /* save buffer pointers to avoid frequent dma mapping */
2659                         Buffer0_ptr = rxdp3->Buffer0_ptr;
2660                         Buffer1_ptr = rxdp3->Buffer1_ptr;
2661                         memset(rxdp, 0, sizeof(struct RxD3));
2662                         /* restore the buffer pointers for dma sync*/
2663                         rxdp3->Buffer0_ptr = Buffer0_ptr;
2664                         rxdp3->Buffer1_ptr = Buffer1_ptr;
2665
2666                         ba = &mac_control->rings[ring_no].ba[block_no][off];
2667                         skb_reserve(skb, BUF0_LEN);
2668                         tmp = (u64)(unsigned long) skb->data;
2669                         tmp += ALIGN_SIZE;
2670                         tmp &= ~ALIGN_SIZE;
2671                         skb->data = (void *) (unsigned long)tmp;
2672                         skb_reset_tail_pointer(skb);
2673
2674                         if (!(rxdp3->Buffer0_ptr))
2675                                 rxdp3->Buffer0_ptr =
2676                                    pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2677                                            PCI_DMA_FROMDEVICE);
2678                         else
2679                                 pci_dma_sync_single_for_device(nic->pdev,
2680                                 (dma_addr_t) rxdp3->Buffer0_ptr,
2681                                     BUF0_LEN, PCI_DMA_FROMDEVICE);
2682                         if( (rxdp3->Buffer0_ptr == 0) ||
2683                                 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE))
2684                                 goto pci_map_failed;
2685
2686                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2687                         if (nic->rxd_mode == RXD_MODE_3B) {
2688                                 /* Two buffer mode */
2689
2690                                 /*
2691                                  * Buffer2 will have L3/L4 header plus
2692                                  * L4 payload
2693                                  */
2694                                 rxdp3->Buffer2_ptr = pci_map_single
2695                                 (nic->pdev, skb->data, dev->mtu + 4,
2696                                                 PCI_DMA_FROMDEVICE);
2697
2698                                 if( (rxdp3->Buffer2_ptr == 0) ||
2699                                         (rxdp3->Buffer2_ptr == DMA_ERROR_CODE))
2700                                         goto pci_map_failed;
2701
2702                                 rxdp3->Buffer1_ptr =
2703                                                 pci_map_single(nic->pdev,
2704                                                 ba->ba_1, BUF1_LEN,
2705                                                 PCI_DMA_FROMDEVICE);
2706                                 if( (rxdp3->Buffer1_ptr == 0) ||
2707                                         (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
2708                                         pci_unmap_single
2709                                                 (nic->pdev,
2710                                                 (dma_addr_t)rxdp3->Buffer2_ptr,
2711                                                 dev->mtu + 4,
2712                                                 PCI_DMA_FROMDEVICE);
2713                                         goto pci_map_failed;
2714                                 }
2715                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2716                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2717                                                                 (dev->mtu + 4);
2718                         }
2719                         rxdp->Control_2 |= s2BIT(0);
2720                 }
2721                 rxdp->Host_Control = (unsigned long) (skb);
2722                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2723                         rxdp->Control_1 |= RXD_OWN_XENA;
2724                 off++;
2725                 if (off == (rxd_count[nic->rxd_mode] + 1))
2726                         off = 0;
2727                 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2728
2729                 rxdp->Control_2 |= SET_RXD_MARKER;
2730                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2731                         if (first_rxdp) {
2732                                 wmb();
2733                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2734                         }
2735                         first_rxdp = rxdp;
2736                 }
2737                 atomic_inc(&nic->rx_bufs_left[ring_no]);
2738                 alloc_tab++;
2739         }
2740
2741       end:
2742         /* Transfer ownership of first descriptor to adapter just before
2743          * exiting. Before that, use memory barrier so that ownership
2744          * and other fields are seen by adapter correctly.
2745          */
2746         if (first_rxdp) {
2747                 wmb();
2748                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2749         }
2750
2751         return SUCCESS;
2752 pci_map_failed:
2753         stats->pci_map_fail_cnt++;
2754         stats->mem_freed += skb->truesize;
2755         dev_kfree_skb_irq(skb);
2756         return -ENOMEM;
2757 }
2758
2759 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2760 {
2761         struct net_device *dev = sp->dev;
2762         int j;
2763         struct sk_buff *skb;
2764         struct RxD_t *rxdp;
2765         struct mac_info *mac_control;
2766         struct buffAdd *ba;
2767         struct RxD1 *rxdp1;
2768         struct RxD3 *rxdp3;
2769
2770         mac_control = &sp->mac_control;
2771         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2772                 rxdp = mac_control->rings[ring_no].
2773                                 rx_blocks[blk].rxds[j].virt_addr;
2774                 skb = (struct sk_buff *)
2775                         ((unsigned long) rxdp->Host_Control);
2776                 if (!skb) {
2777                         continue;
2778                 }
2779                 if (sp->rxd_mode == RXD_MODE_1) {
2780                         rxdp1 = (struct RxD1*)rxdp;
2781                         pci_unmap_single(sp->pdev, (dma_addr_t)
2782                                 rxdp1->Buffer0_ptr,
2783                                 dev->mtu +
2784                                 HEADER_ETHERNET_II_802_3_SIZE
2785                                 + HEADER_802_2_SIZE +
2786                                 HEADER_SNAP_SIZE,
2787                                 PCI_DMA_FROMDEVICE);
2788                         memset(rxdp, 0, sizeof(struct RxD1));
2789                 } else if(sp->rxd_mode == RXD_MODE_3B) {
2790                         rxdp3 = (struct RxD3*)rxdp;
2791                         ba = &mac_control->rings[ring_no].
2792                                 ba[blk][j];
2793                         pci_unmap_single(sp->pdev, (dma_addr_t)
2794                                 rxdp3->Buffer0_ptr,
2795                                 BUF0_LEN,
2796                                 PCI_DMA_FROMDEVICE);
2797                         pci_unmap_single(sp->pdev, (dma_addr_t)
2798                                 rxdp3->Buffer1_ptr,
2799                                 BUF1_LEN,
2800                                 PCI_DMA_FROMDEVICE);
2801                         pci_unmap_single(sp->pdev, (dma_addr_t)
2802                                 rxdp3->Buffer2_ptr,
2803                                 dev->mtu + 4,
2804                                 PCI_DMA_FROMDEVICE);
2805                         memset(rxdp, 0, sizeof(struct RxD3));
2806                 }
2807                 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
2808                 dev_kfree_skb(skb);
2809                 atomic_dec(&sp->rx_bufs_left[ring_no]);
2810         }
2811 }
2812
2813 /**
2814  *  free_rx_buffers - Frees all Rx buffers
2815  *  @sp: device private variable.
2816  *  Description:
2817  *  This function will free all Rx buffers allocated by host.
2818  *  Return Value:
2819  *  NONE.
2820  */
2821
2822 static void free_rx_buffers(struct s2io_nic *sp)
2823 {
2824         struct net_device *dev = sp->dev;
2825         int i, blk = 0, buf_cnt = 0;
2826         struct mac_info *mac_control;
2827         struct config_param *config;
2828
2829         mac_control = &sp->mac_control;
2830         config = &sp->config;
2831
2832         for (i = 0; i < config->rx_ring_num; i++) {
2833                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2834                         free_rxd_blk(sp,i,blk);
2835
2836                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2837                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2838                 mac_control->rings[i].rx_curr_put_info.offset = 0;
2839                 mac_control->rings[i].rx_curr_get_info.offset = 0;
2840                 atomic_set(&sp->rx_bufs_left[i], 0);
2841                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2842                           dev->name, buf_cnt, i);
2843         }
2844 }
2845
2846 /**
2847  * s2io_poll - Rx interrupt handler for NAPI support
2848  * @napi : pointer to the napi structure.
2849  * @budget : The number of packets that were budgeted to be processed
2850  * during  one pass through the 'Poll" function.
2851  * Description:
2852  * Comes into picture only if NAPI support has been incorporated. It does
2853  * the same thing that rx_intr_handler does, but not in a interrupt context
2854  * also It will process only a given number of packets.
2855  * Return value:
2856  * 0 on success and 1 if there are No Rx packets to be processed.
2857  */
2858
2859 static int s2io_poll(struct napi_struct *napi, int budget)
2860 {
2861         struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2862         struct net_device *dev = nic->dev;
2863         int pkt_cnt = 0, org_pkts_to_process;
2864         struct mac_info *mac_control;
2865         struct config_param *config;
2866         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2867         int i;
2868
2869         mac_control = &nic->mac_control;
2870         config = &nic->config;
2871
2872         nic->pkts_to_process = budget;
2873         org_pkts_to_process = nic->pkts_to_process;
2874
2875         writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2876         readl(&bar0->rx_traffic_int);
2877
2878         for (i = 0; i < config->rx_ring_num; i++) {
2879                 rx_intr_handler(&mac_control->rings[i]);
2880                 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2881                 if (!nic->pkts_to_process) {
2882                         /* Quota for the current iteration has been met */
2883                         goto no_rx;
2884                 }
2885         }
2886
2887         netif_rx_complete(dev, napi);
2888
2889         for (i = 0; i < config->rx_ring_num; i++) {
2890                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2891                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2892                         DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
2893                         break;
2894                 }
2895         }
2896         /* Re enable the Rx interrupts. */
2897         writeq(0x0, &bar0->rx_traffic_mask);
2898         readl(&bar0->rx_traffic_mask);
2899         return pkt_cnt;
2900
2901 no_rx:
2902         for (i = 0; i < config->rx_ring_num; i++) {
2903                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2904                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2905                         DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
2906                         break;
2907                 }
2908         }
2909         return pkt_cnt;
2910 }
2911
2912 #ifdef CONFIG_NET_POLL_CONTROLLER
2913 /**
2914  * s2io_netpoll - netpoll event handler entry point
2915  * @dev : pointer to the device structure.
2916  * Description:
2917  *      This function will be called by upper layer to check for events on the
2918  * interface in situations where interrupts are disabled. It is used for
2919  * specific in-kernel networking tasks, such as remote consoles and kernel
2920  * debugging over the network (example netdump in RedHat).
2921  */
2922 static void s2io_netpoll(struct net_device *dev)
2923 {
2924         struct s2io_nic *nic = dev->priv;
2925         struct mac_info *mac_control;
2926         struct config_param *config;
2927         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2928         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2929         int i;
2930
2931         if (pci_channel_offline(nic->pdev))
2932                 return;
2933
2934         disable_irq(dev->irq);
2935
2936         mac_control = &nic->mac_control;
2937         config = &nic->config;
2938
2939         writeq(val64, &bar0->rx_traffic_int);
2940         writeq(val64, &bar0->tx_traffic_int);
2941
2942         /* we need to free up the transmitted skbufs or else netpoll will
2943          * run out of skbs and will fail and eventually netpoll application such
2944          * as netdump will fail.
2945          */
2946         for (i = 0; i < config->tx_fifo_num; i++)
2947                 tx_intr_handler(&mac_control->fifos[i]);
2948
2949         /* check for received packet and indicate up to network */
2950         for (i = 0; i < config->rx_ring_num; i++)
2951                 rx_intr_handler(&mac_control->rings[i]);
2952
2953         for (i = 0; i < config->rx_ring_num; i++) {
2954                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2955                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2956                         DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
2957                         break;
2958                 }
2959         }
2960         enable_irq(dev->irq);
2961         return;
2962 }
2963 #endif
2964
2965 /**
2966  *  rx_intr_handler - Rx interrupt handler
2967  *  @nic: device private variable.
2968  *  Description:
2969  *  If the interrupt is because of a received frame or if the
2970  *  receive ring contains fresh as yet un-processed frames,this function is
2971  *  called. It picks out the RxD at which place the last Rx processing had
2972  *  stopped and sends the skb to the OSM's Rx handler and then increments
2973  *  the offset.
2974  *  Return Value:
2975  *  NONE.
2976  */
2977 static void rx_intr_handler(struct ring_info *ring_data)
2978 {
2979         struct s2io_nic *nic = ring_data->nic;
2980         struct net_device *dev = (struct net_device *) nic->dev;
2981         int get_block, put_block, put_offset;
2982         struct rx_curr_get_info get_info, put_info;
2983         struct RxD_t *rxdp;
2984         struct sk_buff *skb;
2985         int pkt_cnt = 0;
2986         int i;
2987         struct RxD1* rxdp1;
2988         struct RxD3* rxdp3;
2989
2990         spin_lock(&nic->rx_lock);
2991
2992         get_info = ring_data->rx_curr_get_info;
2993         get_block = get_info.block_index;
2994         memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2995         put_block = put_info.block_index;
2996         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2997         if (!napi) {
2998                 spin_lock(&nic->put_lock);
2999                 put_offset = ring_data->put_pos;
3000                 spin_unlock(&nic->put_lock);
3001         } else
3002                 put_offset = ring_data->put_pos;
3003
3004         while (RXD_IS_UP2DT(rxdp)) {
3005                 /*
3006                  * If your are next to put index then it's
3007                  * FIFO full condition
3008                  */
3009                 if ((get_block == put_block) &&
3010                     (get_info.offset + 1) == put_info.offset) {
3011                         DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
3012                         break;
3013                 }
3014                 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
3015                 if (skb == NULL) {
3016                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
3017                                   dev->name);
3018                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
3019                         spin_unlock(&nic->rx_lock);
3020                         return;
3021                 }
3022                 if (nic->rxd_mode == RXD_MODE_1) {
3023                         rxdp1 = (struct RxD1*)rxdp;
3024                         pci_unmap_single(nic->pdev, (dma_addr_t)
3025                                 rxdp1->Buffer0_ptr,
3026                                 dev->mtu +
3027                                 HEADER_ETHERNET_II_802_3_SIZE +
3028                                 HEADER_802_2_SIZE +
3029                                 HEADER_SNAP_SIZE,
3030                                 PCI_DMA_FROMDEVICE);
3031                 } else if (nic->rxd_mode == RXD_MODE_3B) {
3032                         rxdp3 = (struct RxD3*)rxdp;
3033                         pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
3034                                 rxdp3->Buffer0_ptr,
3035                                 BUF0_LEN, PCI_DMA_FROMDEVICE);
3036                         pci_unmap_single(nic->pdev, (dma_addr_t)
3037                                 rxdp3->Buffer2_ptr,
3038                                 dev->mtu + 4,
3039                                 PCI_DMA_FROMDEVICE);
3040                 }
3041                 prefetch(skb->data);
3042                 rx_osm_handler(ring_data, rxdp);
3043                 get_info.offset++;
3044                 ring_data->rx_curr_get_info.offset = get_info.offset;
3045                 rxdp = ring_data->rx_blocks[get_block].
3046                                 rxds[get_info.offset].virt_addr;
3047                 if (get_info.offset == rxd_count[nic->rxd_mode]) {
3048                         get_info.offset = 0;
3049                         ring_data->rx_curr_get_info.offset = get_info.offset;
3050                         get_block++;
3051                         if (get_block == ring_data->block_count)
3052                                 get_block = 0;
3053                         ring_data->rx_curr_get_info.block_index = get_block;
3054                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3055                 }
3056
3057                 nic->pkts_to_process -= 1;
3058                 if ((napi) && (!nic->pkts_to_process))
3059                         break;
3060                 pkt_cnt++;
3061                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3062                         break;
3063         }
3064         if (nic->lro) {
3065                 /* Clear all LRO sessions before exiting */
3066                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
3067                         struct lro *lro = &nic->lro0_n[i];
3068                         if (lro->in_use) {
3069                                 update_L3L4_header(nic, lro);
3070                                 queue_rx_frame(lro->parent, lro->vlan_tag);
3071                                 clear_lro_session(lro);
3072                         }
3073                 }
3074         }
3075
3076         spin_unlock(&nic->rx_lock);
3077 }
3078
3079 /**
3080  *  tx_intr_handler - Transmit interrupt handler
3081  *  @nic : device private variable
3082  *  Description:
3083  *  If an interrupt was raised to indicate DMA complete of the
3084  *  Tx packet, this function is called. It identifies the last TxD
3085  *  whose buffer was freed and frees all skbs whose data have already
3086  *  DMA'ed into the NICs internal memory.
3087  *  Return Value:
3088  *  NONE
3089  */
3090
3091 static void tx_intr_handler(struct fifo_info *fifo_data)
3092 {
3093         struct s2io_nic *nic = fifo_data->nic;
3094         struct tx_curr_get_info get_info, put_info;
3095         struct sk_buff *skb = NULL;
3096         struct TxD *txdlp;
3097         int pkt_cnt = 0;
3098         unsigned long flags = 0;
3099         u8 err_mask;
3100
3101         if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3102                         return;
3103
3104         get_info = fifo_data->tx_curr_get_info;
3105         memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3106         txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
3107             list_virt_addr;
3108         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3109                (get_info.offset != put_info.offset) &&
3110                (txdlp->Host_Control)) {
3111                 /* Check for TxD errors */
3112                 if (txdlp->Control_1 & TXD_T_CODE) {
3113                         unsigned long long err;
3114                         err = txdlp->Control_1 & TXD_T_CODE;
3115                         if (err & 0x1) {
3116                                 nic->mac_control.stats_info->sw_stat.
3117                                                 parity_err_cnt++;
3118                         }
3119
3120                         /* update t_code statistics */
3121                         err_mask = err >> 48;
3122                         switch(err_mask) {
3123                                 case 2:
3124                                         nic->mac_control.stats_info->sw_stat.
3125                                                         tx_buf_abort_cnt++;
3126                                 break;
3127
3128                                 case 3:
3129                                         nic->mac_control.stats_info->sw_stat.
3130                                                         tx_desc_abort_cnt++;
3131                                 break;
3132
3133                                 case 7:
3134                                         nic->mac_control.stats_info->sw_stat.
3135                                                         tx_parity_err_cnt++;
3136                                 break;
3137
3138                                 case 10:
3139                                         nic->mac_control.stats_info->sw_stat.
3140                                                         tx_link_loss_cnt++;
3141                                 break;
3142
3143                                 case 15:
3144                                         nic->mac_control.stats_info->sw_stat.
3145                                                         tx_list_proc_err_cnt++;
3146                                 break;
3147                         }
3148                 }
3149
3150                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3151                 if (skb == NULL) {
3152                         spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3153                         DBG_PRINT(ERR_DBG, "%s: Null skb ",
3154                         __FUNCTION__);
3155                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
3156                         return;
3157                 }
3158                 pkt_cnt++;
3159
3160                 /* Updating the statistics block */
3161                 nic->stats.tx_bytes += skb->len;
3162                 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
3163                 dev_kfree_skb_irq(skb);
3164
3165                 get_info.offset++;
3166                 if (get_info.offset == get_info.fifo_len + 1)
3167                         get_info.offset = 0;
3168                 txdlp = (struct TxD *) fifo_data->list_info
3169                     [get_info.offset].list_virt_addr;
3170                 fifo_data->tx_curr_get_info.offset =
3171                     get_info.offset;
3172         }
3173
3174         s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3175
3176         spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3177 }
3178
3179 /**
3180  *  s2io_mdio_write - Function to write in to MDIO registers
3181  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3182  *  @addr     : address value
3183  *  @value    : data value
3184  *  @dev      : pointer to net_device structure
3185  *  Description:
3186  *  This function is used to write values to the MDIO registers
3187  *  NONE
3188  */
3189 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
3190 {
3191         u64 val64 = 0x0;
3192         struct s2io_nic *sp = dev->priv;
3193         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3194
3195         //address transaction
3196         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3197                         | MDIO_MMD_DEV_ADDR(mmd_type)
3198                         | MDIO_MMS_PRT_ADDR(0x0);
3199         writeq(val64, &bar0->mdio_control);
3200         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3201         writeq(val64, &bar0->mdio_control);
3202         udelay(100);
3203
3204         //Data transaction
3205         val64 = 0x0;
3206         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3207                         | MDIO_MMD_DEV_ADDR(mmd_type)
3208                         | MDIO_MMS_PRT_ADDR(0x0)
3209                         | MDIO_MDIO_DATA(value)
3210                         | MDIO_OP(MDIO_OP_WRITE_TRANS);
3211         writeq(val64, &bar0->mdio_control);
3212         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3213         writeq(val64, &bar0->mdio_control);
3214         udelay(100);
3215
3216         val64 = 0x0;
3217         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3218         | MDIO_MMD_DEV_ADDR(mmd_type)
3219         | MDIO_MMS_PRT_ADDR(0x0)
3220         | MDIO_OP(MDIO_OP_READ_TRANS);
3221         writeq(val64, &bar0->mdio_control);
3222         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3223         writeq(val64, &bar0->mdio_control);
3224         udelay(100);
3225
3226 }
3227
3228 /**
3229  *  s2io_mdio_read - Function to write in to MDIO registers
3230  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3231  *  @addr     : address value
3232  *  @dev      : pointer to net_device structure
3233  *  Description:
3234  *  This function is used to read values to the MDIO registers
3235  *  NONE
3236  */
3237 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3238 {
3239         u64 val64 = 0x0;
3240         u64 rval64 = 0x0;
3241         struct s2io_nic *sp = dev->priv;
3242         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3243
3244         /* address transaction */
3245         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3246                         | MDIO_MMD_DEV_ADDR(mmd_type)
3247                         | MDIO_MMS_PRT_ADDR(0x0);
3248         writeq(val64, &bar0->mdio_control);
3249         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3250         writeq(val64, &bar0->mdio_control);
3251         udelay(100);
3252
3253         /* Data transaction */
3254         val64 = 0x0;
3255         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3256                         | MDIO_MMD_DEV_ADDR(mmd_type)
3257                         | MDIO_MMS_PRT_ADDR(0x0)
3258                         | MDIO_OP(MDIO_OP_READ_TRANS);
3259         writeq(val64, &bar0->mdio_control);
3260         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3261         writeq(val64, &bar0->mdio_control);
3262         udelay(100);
3263
3264         /* Read the value from regs */
3265         rval64 = readq(&bar0->mdio_control);
3266         rval64 = rval64 & 0xFFFF0000;
3267         rval64 = rval64 >> 16;
3268         return rval64;
3269 }
3270 /**
3271  *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
3272  *  @counter      : couter value to be updated
3273  *  @flag         : flag to indicate the status
3274  *  @type         : counter type
3275  *  Description:
3276  *  This function is to check the status of the xpak counters value
3277  *  NONE
3278  */
3279
3280 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3281 {
3282         u64 mask = 0x3;
3283         u64 val64;
3284         int i;
3285         for(i = 0; i <index; i++)
3286                 mask = mask << 0x2;
3287
3288         if(flag > 0)
3289         {
3290                 *counter = *counter + 1;
3291                 val64 = *regs_stat & mask;
3292                 val64 = val64 >> (index * 0x2);
3293                 val64 = val64 + 1;
3294                 if(val64 == 3)
3295                 {
3296                         switch(type)
3297                         {
3298                         case 1:
3299                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3300                                           "service. Excessive temperatures may "
3301                                           "result in premature transceiver "
3302                                           "failure \n");
3303                         break;
3304                         case 2:
3305                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3306                                           "service Excessive bias currents may "
3307                                           "indicate imminent laser diode "
3308                                           "failure \n");
3309                         break;
3310                         case 3:
3311                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3312                                           "service Excessive laser output "
3313                                           "power may saturate far-end "
3314                                           "receiver\n");
3315                         break;
3316                         default:
3317                                 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3318                                           "type \n");
3319                         }
3320                         val64 = 0x0;
3321                 }
3322                 val64 = val64 << (index * 0x2);
3323                 *regs_stat = (*regs_stat & (~mask)) | (val64);
3324
3325         } else {
3326                 *regs_stat = *regs_stat & (~mask);
3327         }
3328 }
3329
3330 /**
3331  *  s2io_updt_xpak_counter - Function to update the xpak counters
3332  *  @dev         : pointer to net_device struct
3333  *  Description:
3334  *  This function is to upate the status of the xpak counters value
3335  *  NONE
3336  */
3337 static void s2io_updt_xpak_counter(struct net_device *dev)
3338 {
3339         u16 flag  = 0x0;
3340         u16 type  = 0x0;
3341         u16 val16 = 0x0;
3342         u64 val64 = 0x0;
3343         u64 addr  = 0x0;
3344
3345         struct s2io_nic *sp = dev->priv;
3346         struct stat_block *stat_info = sp->mac_control.stats_info;
3347
3348         /* Check the communication with the MDIO slave */
3349         addr = 0x0000;
3350         val64 = 0x0;
3351         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3352         if((val64 == 0xFFFF) || (val64 == 0x0000))
3353         {
3354                 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3355                           "Returned %llx\n", (unsigned long long)val64);
3356                 return;
3357         }
3358
3359         /* Check for the expecte value of 2040 at PMA address 0x0000 */
3360         if(val64 != 0x2040)
3361         {
3362                 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3363                 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3364                           (unsigned long long)val64);
3365                 return;
3366         }
3367
3368         /* Loading the DOM register to MDIO register */
3369         addr = 0xA100;
3370         s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3371         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3372
3373         /* Reading the Alarm flags */
3374         addr = 0xA070;
3375         val64 = 0x0;
3376         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3377
3378         flag = CHECKBIT(val64, 0x7);
3379         type = 1;
3380         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3381                                 &stat_info->xpak_stat.xpak_regs_stat,
3382                                 0x0, flag, type);
3383
3384         if(CHECKBIT(val64, 0x6))
3385                 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3386
3387         flag = CHECKBIT(val64, 0x3);
3388         type = 2;
3389         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3390                                 &stat_info->xpak_stat.xpak_regs_stat,
3391                                 0x2, flag, type);
3392
3393         if(CHECKBIT(val64, 0x2))
3394                 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3395
3396         flag = CHECKBIT(val64, 0x1);
3397         type = 3;
3398         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3399                                 &stat_info->xpak_stat.xpak_regs_stat,
3400                                 0x4, flag, type);
3401
3402         if(CHECKBIT(val64, 0x0))
3403                 stat_info->xpak_stat.alarm_laser_output_power_low++;
3404
3405         /* Reading the Warning flags */
3406         addr = 0xA074;
3407         val64 = 0x0;
3408         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3409
3410         if(CHECKBIT(val64, 0x7))
3411                 stat_info->xpak_stat.warn_transceiver_temp_high++;
3412
3413         if(CHECKBIT(val64, 0x6))
3414                 stat_info->xpak_stat.warn_transceiver_temp_low++;
3415
3416         if(CHECKBIT(val64, 0x3))
3417                 stat_info->xpak_stat.warn_laser_bias_current_high++;
3418
3419         if(CHECKBIT(val64, 0x2))
3420                 stat_info->xpak_stat.warn_laser_bias_current_low++;
3421
3422         if(CHECKBIT(val64, 0x1))
3423                 stat_info->xpak_stat.warn_laser_output_power_high++;
3424
3425         if(CHECKBIT(val64, 0x0))
3426                 stat_info->xpak_stat.warn_laser_output_power_low++;
3427 }
3428
3429 /**
3430  *  wait_for_cmd_complete - waits for a command to complete.
3431  *  @sp : private member of the device structure, which is a pointer to the
3432  *  s2io_nic structure.
3433  *  Description: Function that waits for a command to Write into RMAC
3434  *  ADDR DATA registers to be completed and returns either success or
3435  *  error depending on whether the command was complete or not.
3436  *  Return value:
3437  *   SUCCESS on success and FAILURE on failure.
3438  */
3439
3440 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3441                                 int bit_state)
3442 {
3443         int ret = FAILURE, cnt = 0, delay = 1;
3444         u64 val64;
3445
3446         if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3447                 return FAILURE;
3448
3449         do {
3450                 val64 = readq(addr);
3451                 if (bit_state == S2IO_BIT_RESET) {
3452                         if (!(val64 & busy_bit)) {
3453                                 ret = SUCCESS;
3454                                 break;
3455                         }
3456                 } else {
3457                         if (!(val64 & busy_bit)) {
3458                                 ret = SUCCESS;
3459                                 break;
3460                         }
3461                 }
3462
3463                 if(in_interrupt())
3464                         mdelay(delay);
3465                 else
3466                         msleep(delay);
3467
3468                 if (++cnt >= 10)
3469                         delay = 50;
3470         } while (cnt < 20);
3471         return ret;
3472 }
3473 /*
3474  * check_pci_device_id - Checks if the device id is supported
3475  * @id : device id
3476  * Description: Function to check if the pci device id is supported by driver.
3477  * Return value: Actual device id if supported else PCI_ANY_ID
3478  */
3479 static u16 check_pci_device_id(u16 id)
3480 {
3481         switch (id) {
3482         case PCI_DEVICE_ID_HERC_WIN:
3483         case PCI_DEVICE_ID_HERC_UNI:
3484                 return XFRAME_II_DEVICE;
3485         case PCI_DEVICE_ID_S2IO_UNI:
3486         case PCI_DEVICE_ID_S2IO_WIN:
3487                 return XFRAME_I_DEVICE;
3488         default:
3489                 return PCI_ANY_ID;
3490         }
3491 }
3492
3493 /**
3494  *  s2io_reset - Resets the card.
3495  *  @sp : private member of the device structure.
3496  *  Description: Function to Reset the card. This function then also
3497  *  restores the previously saved PCI configuration space registers as
3498  *  the card reset also resets the configuration space.
3499  *  Return value:
3500  *  void.
3501  */
3502
3503 static void s2io_reset(struct s2io_nic * sp)
3504 {
3505         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3506         u64 val64;
3507         u16 subid, pci_cmd;
3508         int i;
3509         u16 val16;
3510         unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3511         unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3512
3513         DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3514                         __FUNCTION__, sp->dev->name);
3515
3516         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3517         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3518
3519         val64 = SW_RESET_ALL;
3520         writeq(val64, &bar0->sw_reset);
3521         if (strstr(sp->product_name, "CX4")) {
3522                 msleep(750);
3523         }
3524         msleep(250);
3525         for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3526
3527                 /* Restore the PCI state saved during initialization. */
3528                 pci_restore_state(sp->pdev);
3529                 pci_read_config_word(sp->pdev, 0x2, &val16);
3530                 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3531                         break;
3532                 msleep(200);
3533         }
3534
3535         if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3536                 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3537         }
3538
3539         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3540
3541         s2io_init_pci(sp);
3542
3543         /* Set swapper to enable I/O register access */
3544         s2io_set_swapper(sp);
3545
3546         /* restore mac_addr entries */
3547         do_s2io_restore_unicast_mc(sp);
3548
3549         /* Restore the MSIX table entries from local variables */
3550         restore_xmsi_data(sp);
3551
3552         /* Clear certain PCI/PCI-X fields after reset */
3553         if (sp->device_type == XFRAME_II_DEVICE) {
3554                 /* Clear "detected parity error" bit */
3555                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3556
3557                 /* Clearing PCIX Ecc status register */
3558                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3559
3560                 /* Clearing PCI_STATUS error reflected here */
3561                 writeq(s2BIT(62), &bar0->txpic_int_reg);
3562         }
3563
3564         /* Reset device statistics maintained by OS */
3565         memset(&sp->stats, 0, sizeof (struct net_device_stats));
3566
3567         up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3568         down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3569         up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3570         down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
3571         reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
3572         mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3573         mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3574         watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3575         /* save link up/down time/cnt, reset/memory/watchdog cnt */
3576         memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
3577         /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3578         sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3579         sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3580         sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3581         sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
3582         sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
3583         sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3584         sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3585         sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
3586
3587         /* SXE-002: Configure link and activity LED to turn it off */
3588         subid = sp->pdev->subsystem_device;
3589         if (((subid & 0xFF) >= 0x07) &&
3590             (sp->device_type == XFRAME_I_DEVICE)) {
3591                 val64 = readq(&bar0->gpio_control);
3592                 val64 |= 0x0000800000000000ULL;
3593                 writeq(val64, &bar0->gpio_control);
3594                 val64 = 0x0411040400000000ULL;
3595                 writeq(val64, (void __iomem *)bar0 + 0x2700);
3596         }
3597
3598         /*
3599          * Clear spurious ECC interrupts that would have occured on
3600          * XFRAME II cards after reset.
3601          */
3602         if (sp->device_type == XFRAME_II_DEVICE) {
3603                 val64 = readq(&bar0->pcc_err_reg);
3604                 writeq(val64, &bar0->pcc_err_reg);
3605         }
3606
3607         sp->device_enabled_once = FALSE;
3608 }
3609
3610 /**
3611  *  s2io_set_swapper - to set the swapper controle on the card
3612  *  @sp : private member of the device structure,
3613  *  pointer to the s2io_nic structure.
3614  *  Description: Function to set the swapper control on the card
3615  *  correctly depending on the 'endianness' of the system.
3616  *  Return value:
3617  *  SUCCESS on success and FAILURE on failure.
3618  */
3619
3620 static int s2io_set_swapper(struct s2io_nic * sp)
3621 {
3622         struct net_device *dev = sp->dev;
3623         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3624         u64 val64, valt, valr;
3625
3626         /*
3627          * Set proper endian settings and verify the same by reading
3628          * the PIF Feed-back register.
3629          */
3630
3631         val64 = readq(&bar0->pif_rd_swapper_fb);
3632         if (val64 != 0x0123456789ABCDEFULL) {
3633                 int i = 0;
3634                 u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
3635                                 0x8100008181000081ULL,  /* FE=1, SE=0 */
3636                                 0x4200004242000042ULL,  /* FE=0, SE=1 */
3637                                 0};                     /* FE=0, SE=0 */
3638
3639                 while(i<4) {
3640                         writeq(value[i], &bar0->swapper_ctrl);
3641                         val64 = readq(&bar0->pif_rd_swapper_fb);
3642                         if (val64 == 0x0123456789ABCDEFULL)
3643                                 break;
3644                         i++;
3645                 }
3646                 if (i == 4) {
3647                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3648                                 dev->name);
3649                         DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3650                                 (unsigned long long) val64);
3651                         return FAILURE;
3652                 }
3653                 valr = value[i];
3654         } else {
3655                 valr = readq(&bar0->swapper_ctrl);
3656         }
3657
3658         valt = 0x0123456789ABCDEFULL;
3659         writeq(valt, &bar0->xmsi_address);
3660         val64 = readq(&bar0->xmsi_address);
3661
3662         if(val64 != valt) {
3663                 int i = 0;
3664                 u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
3665                                 0x0081810000818100ULL,  /* FE=1, SE=0 */
3666                                 0x0042420000424200ULL,  /* FE=0, SE=1 */
3667                                 0};                     /* FE=0, SE=0 */
3668
3669                 while(i<4) {
3670                         writeq((value[i] | valr), &bar0->swapper_ctrl);
3671                         writeq(valt, &bar0->xmsi_address);
3672                         val64 = readq(&bar0->xmsi_address);
3673                         if(val64 == valt)
3674                                 break;
3675                         i++;
3676                 }
3677                 if(i == 4) {
3678                         unsigned long long x = val64;
3679                         DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3680                         DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3681                         return FAILURE;
3682                 }
3683         }
3684         val64 = readq(&bar0->swapper_ctrl);
3685         val64 &= 0xFFFF000000000000ULL;
3686
3687 #ifdef  __BIG_ENDIAN
3688         /*
3689          * The device by default set to a big endian format, so a
3690          * big endian driver need not set anything.
3691          */
3692         val64 |= (SWAPPER_CTRL_TXP_FE |
3693                  SWAPPER_CTRL_TXP_SE |
3694                  SWAPPER_CTRL_TXD_R_FE |
3695                  SWAPPER_CTRL_TXD_W_FE |
3696                  SWAPPER_CTRL_TXF_R_FE |
3697                  SWAPPER_CTRL_RXD_R_FE |
3698                  SWAPPER_CTRL_RXD_W_FE |
3699                  SWAPPER_CTRL_RXF_W_FE |
3700                  SWAPPER_CTRL_XMSI_FE |
3701                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3702         if (sp->config.intr_type == INTA)
3703                 val64 |= SWAPPER_CTRL_XMSI_SE;
3704         writeq(val64, &bar0->swapper_ctrl);
3705 #else
3706         /*
3707          * Initially we enable all bits to make it accessible by the
3708          * driver, then we selectively enable only those bits that
3709          * we want to set.
3710          */
3711         val64 |= (SWAPPER_CTRL_TXP_FE |
3712                  SWAPPER_CTRL_TXP_SE |
3713                  SWAPPER_CTRL_TXD_R_FE |
3714                  SWAPPER_CTRL_TXD_R_SE |
3715                  SWAPPER_CTRL_TXD_W_FE |
3716                  SWAPPER_CTRL_TXD_W_SE |
3717                  SWAPPER_CTRL_TXF_R_FE |
3718                  SWAPPER_CTRL_RXD_R_FE |
3719                  SWAPPER_CTRL_RXD_R_SE |
3720                  SWAPPER_CTRL_RXD_W_FE |
3721                  SWAPPER_CTRL_RXD_W_SE |
3722                  SWAPPER_CTRL_RXF_W_FE |
3723                  SWAPPER_CTRL_XMSI_FE |
3724                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3725         if (sp->config.intr_type == INTA)
3726                 val64 |= SWAPPER_CTRL_XMSI_SE;
3727         writeq(val64, &bar0->swapper_ctrl);
3728 #endif
3729         val64 = readq(&bar0->swapper_ctrl);
3730
3731         /*
3732          * Verifying if endian settings are accurate by reading a
3733          * feedback register.
3734          */
3735         val64 = readq(&bar0->pif_rd_swapper_fb);
3736         if (val64 != 0x0123456789ABCDEFULL) {
3737                 /* Endian settings are incorrect, calls for another dekko. */
3738                 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3739                           dev->name);
3740                 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3741                           (unsigned long long) val64);
3742                 return FAILURE;
3743         }
3744
3745         return SUCCESS;
3746 }
3747
3748 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3749 {
3750         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3751         u64 val64;
3752         int ret = 0, cnt = 0;
3753
3754         do {
3755                 val64 = readq(&bar0->xmsi_access);
3756                 if (!(val64 & s2BIT(15)))
3757                         break;
3758                 mdelay(1);
3759                 cnt++;
3760         } while(cnt < 5);
3761         if (cnt == 5) {
3762                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3763                 ret = 1;
3764         }
3765
3766         return ret;
3767 }
3768
3769 static void restore_xmsi_data(struct s2io_nic *nic)
3770 {
3771         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3772         u64 val64;
3773         int i;
3774
3775         for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3776                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3777                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3778                 val64 = (s2BIT(7) | s2BIT(15) | vBIT(i, 26, 6));
3779                 writeq(val64, &bar0->xmsi_access);
3780                 if (wait_for_msix_trans(nic, i)) {
3781                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3782                         continue;
3783                 }
3784         }
3785 }
3786
3787 static void store_xmsi_data(struct s2io_nic *nic)
3788 {
3789         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3790         u64 val64, addr, data;
3791         int i;
3792
3793         /* Store and display */
3794         for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3795                 val64 = (s2BIT(15) | vBIT(i, 26, 6));
3796                 writeq(val64, &bar0->xmsi_access);
3797                 if (wait_for_msix_trans(nic, i)) {
3798                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3799                         continue;
3800                 }
3801                 addr = readq(&bar0->xmsi_address);
3802                 data = readq(&bar0->xmsi_data);
3803                 if (addr && data) {
3804                         nic->msix_info[i].addr = addr;
3805                         nic->msix_info[i].data = data;
3806                 }
3807         }
3808 }
3809
3810 static int s2io_enable_msi_x(struct s2io_nic *nic)
3811 {
3812         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3813         u64 tx_mat, rx_mat;
3814         u16 msi_control; /* Temp variable */
3815         int ret, i, j, msix_indx = 1;
3816
3817         nic->entries = kcalloc(MAX_REQUESTED_MSI_X, sizeof(struct msix_entry),
3818                                GFP_KERNEL);
3819         if (!nic->entries) {
3820                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
3821                         __FUNCTION__);
3822                 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3823                 return -ENOMEM;
3824         }
3825         nic->mac_control.stats_info->sw_stat.mem_allocated
3826                 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3827
3828         nic->s2io_entries =
3829                 kcalloc(MAX_REQUESTED_MSI_X, sizeof(struct s2io_msix_entry),
3830                                    GFP_KERNEL);
3831         if (!nic->s2io_entries) {
3832                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3833                         __FUNCTION__);
3834                 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3835                 kfree(nic->entries);
3836                 nic->mac_control.stats_info->sw_stat.mem_freed
3837                         += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3838                 return -ENOMEM;
3839         }
3840          nic->mac_control.stats_info->sw_stat.mem_allocated
3841                 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3842
3843         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3844                 nic->entries[i].entry = i;
3845                 nic->s2io_entries[i].entry = i;
3846                 nic->s2io_entries[i].arg = NULL;
3847                 nic->s2io_entries[i].in_use = 0;
3848         }
3849
3850         tx_mat = readq(&bar0->tx_mat0_n[0]);
3851         for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3852                 tx_mat |= TX_MAT_SET(i, msix_indx);
3853                 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3854                 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3855                 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3856         }
3857         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3858
3859         rx_mat = readq(&bar0->rx_mat);
3860         for (j = 0; j < nic->config.rx_ring_num; j++, msix_indx++) {
3861                 rx_mat |= RX_MAT_SET(j, msix_indx);
3862                 nic->s2io_entries[msix_indx].arg
3863                         = &nic->mac_control.rings[j];
3864                 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3865                 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3866         }
3867         writeq(rx_mat, &bar0->rx_mat);
3868
3869         nic->avail_msix_vectors = 0;
3870         ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
3871         /* We fail init if error or we get less vectors than min required */
3872         if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3873                 nic->avail_msix_vectors = ret;
3874                 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3875         }
3876         if (ret) {
3877                 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3878                 kfree(nic->entries);
3879                 nic->mac_control.stats_info->sw_stat.mem_freed
3880                         += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3881                 kfree(nic->s2io_entries);
3882                 nic->mac_control.stats_info->sw_stat.mem_freed
3883                 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3884                 nic->entries = NULL;
3885                 nic->s2io_entries = NULL;
3886                 nic->avail_msix_vectors = 0;
3887                 return -ENOMEM;
3888         }
3889         if (!nic->avail_msix_vectors)
3890                 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
3891
3892         /*
3893          * To enable MSI-X, MSI also needs to be enabled, due to a bug
3894          * in the herc NIC. (Temp change, needs to be removed later)
3895          */
3896         pci_read_config_word(nic->pdev, 0x42, &msi_control);
3897         msi_control |= 0x1; /* Enable MSI */
3898         pci_write_config_word(nic->pdev, 0x42, msi_control);
3899
3900         return 0;
3901 }
3902
3903 /* Handle software interrupt used during MSI(X) test */
3904 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3905 {
3906         struct s2io_nic *sp = dev_id;
3907
3908         sp->msi_detected = 1;
3909         wake_up(&sp->msi_wait);
3910
3911         return IRQ_HANDLED;
3912 }
3913
3914 /* Test interrupt path by forcing a a software IRQ */
3915 static int s2io_test_msi(struct s2io_nic *sp)
3916 {
3917         struct pci_dev *pdev = sp->pdev;
3918         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3919         int err;
3920         u64 val64, saved64;
3921
3922         err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3923                         sp->name, sp);
3924         if (err) {
3925                 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3926                        sp->dev->name, pci_name(pdev), pdev->irq);
3927                 return err;
3928         }
3929
3930         init_waitqueue_head (&sp->msi_wait);
3931         sp->msi_detected = 0;
3932
3933         saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3934         val64 |= SCHED_INT_CTRL_ONE_SHOT;
3935         val64 |= SCHED_INT_CTRL_TIMER_EN;
3936         val64 |= SCHED_INT_CTRL_INT2MSI(1);
3937         writeq(val64, &bar0->scheduled_int_ctrl);
3938
3939         wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3940
3941         if (!sp->msi_detected) {
3942                 /* MSI(X) test failed, go back to INTx mode */
3943                 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3944                         "using MSI(X) during test\n", sp->dev->name,
3945                         pci_name(pdev));
3946
3947                 err = -EOPNOTSUPP;
3948         }
3949
3950         free_irq(sp->entries[1].vector, sp);
3951
3952         writeq(saved64, &bar0->scheduled_int_ctrl);
3953
3954         return err;
3955 }
3956
3957 static void remove_msix_isr(struct s2io_nic *sp)
3958 {
3959         int i;
3960         u16 msi_control;
3961
3962         for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3963                 if (sp->s2io_entries[i].in_use ==
3964                         MSIX_REGISTERED_SUCCESS) {
3965                         int vector = sp->entries[i].vector;
3966                         void *arg = sp->s2io_entries[i].arg;
3967                         free_irq(vector, arg);
3968                 }
3969         }
3970
3971         kfree(sp->entries);
3972         kfree(sp->s2io_entries);
3973         sp->entries = NULL;
3974         sp->s2io_entries = NULL;
3975
3976         pci_read_config_word(sp->pdev, 0x42, &msi_control);
3977         msi_control &= 0xFFFE; /* Disable MSI */
3978         pci_write_config_word(sp->pdev, 0x42, msi_control);
3979
3980         pci_disable_msix(sp->pdev);
3981 }
3982
3983 static void remove_inta_isr(struct s2io_nic *sp)
3984 {
3985         struct net_device *dev = sp->dev;
3986
3987         free_irq(sp->pdev->irq, dev);
3988 }
3989
3990 /* ********************************************************* *
3991  * Functions defined below concern the OS part of the driver *
3992  * ********************************************************* */
3993
3994 /**
3995  *  s2io_open - open entry point of the driver
3996  *  @dev : pointer to the device structure.
3997  *  Description:
3998  *  This function is the open entry point of the driver. It mainly calls a
3999  *  function to allocate Rx buffers and inserts them into the buffer
4000  *  descriptors and then enables the Rx part of the NIC.
4001  *  Return value:
4002  *  0 on success and an appropriate (-)ve integer as defined in errno.h
4003  *   file on failure.
4004  */
4005
4006 static int s2io_open(struct net_device *dev)
4007 {
4008         struct s2io_nic *sp = dev->priv;
4009         int err = 0;
4010
4011         /*
4012          * Make sure you have link off by default every time
4013          * Nic is initialized
4014          */
4015         netif_carrier_off(dev);
4016         sp->last_link_state = 0;
4017
4018         if (sp->config.intr_type == MSI_X) {
4019                 int ret = s2io_enable_msi_x(sp);
4020
4021                 if (!ret) {
4022                         ret = s2io_test_msi(sp);
4023                         /* rollback MSI-X, will re-enable during add_isr() */
4024                         remove_msix_isr(sp);
4025                 }
4026                 if (ret) {
4027
4028                         DBG_PRINT(ERR_DBG,
4029                           "%s: MSI-X requested but failed to enable\n",
4030                           dev->name);
4031                         sp->config.intr_type = INTA;
4032                 }
4033         }
4034
4035         /* NAPI doesn't work well with MSI(X) */
4036          if (sp->config.intr_type != INTA) {
4037                 if(sp->config.napi)
4038                         sp->config.napi = 0;
4039         }
4040
4041         /* Initialize H/W and enable interrupts */
4042         err = s2io_card_up(sp);
4043         if (err) {
4044                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
4045                           dev->name);
4046                 goto hw_init_failed;
4047         }
4048
4049         if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
4050                 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
4051                 s2io_card_down(sp);
4052                 err = -ENODEV;
4053                 goto hw_init_failed;
4054         }
4055         s2io_start_all_tx_queue(sp);
4056         return 0;
4057
4058 hw_init_failed:
4059         if (sp->config.intr_type == MSI_X) {
4060                 if (sp->entries) {
4061                         kfree(sp->entries);
4062                         sp->mac_control.stats_info->sw_stat.mem_freed
4063                         += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
4064                 }
4065                 if (sp->s2io_entries) {
4066                         kfree(sp->s2io_entries);
4067                         sp->mac_control.stats_info->sw_stat.mem_freed
4068                         += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
4069                 }
4070         }
4071         return err;
4072 }
4073
4074 /**
4075  *  s2io_close -close entry point of the driver
4076  *  @dev : device pointer.
4077  *  Description:
4078  *  This is the stop entry point of the driver. It needs to undo exactly
4079  *  whatever was done by the open entry point,thus it's usually referred to
4080  *  as the close function.Among other things this function mainly stops the
4081  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4082  *  Return value:
4083  *  0 on success and an appropriate (-)ve integer as defined in errno.h
4084  *  file on failure.
4085  */
4086
4087 static int s2io_close(struct net_device *dev)
4088 {
4089         struct s2io_nic *sp = dev->priv;
4090         struct config_param *config = &sp->config;
4091         u64 tmp64;
4092         int offset;
4093
4094         /* Return if the device is already closed               *
4095         *  Can happen when s2io_card_up failed in change_mtu    *
4096         */
4097         if (!is_s2io_card_up(sp))
4098                 return 0;
4099
4100         s2io_stop_all_tx_queue(sp);
4101         /* delete all populated mac entries */
4102         for (offset = 1; offset < config->max_mc_addr; offset++) {
4103                 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4104                 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4105                         do_s2io_delete_unicast_mc(sp, tmp64);
4106         }
4107
4108         /* Reset card, kill tasklet and free Tx and Rx buffers. */
4109         s2io_card_down(sp);
4110
4111         return 0;
4112 }
4113
4114 /**
4115  *  s2io_xmit - Tx entry point of te driver
4116  *  @skb : the socket buffer containing the Tx data.
4117  *  @dev : device pointer.
4118  *  Description :
4119  *  This function is the Tx entry point of the driver. S2IO NIC supports
4120  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
4121  *  NOTE: when device cant queue the pkt,just the trans_start variable will
4122  *  not be upadted.
4123  *  Return value:
4124  *  0 on success & 1 on failure.
4125  */
4126
4127 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4128 {
4129         struct s2io_nic *sp = dev->priv;
4130         u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4131         register u64 val64;
4132         struct TxD *txdp;
4133         struct TxFIFO_element __iomem *tx_fifo;
4134         unsigned long flags = 0;
4135         u16 vlan_tag = 0;
4136         struct fifo_info *fifo = NULL;
4137         struct mac_info *mac_control;
4138         struct config_param *config;
4139         int do_spin_lock = 1;
4140         int offload_type;
4141         int enable_per_list_interrupt = 0;
4142         struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
4143
4144         mac_control = &sp->mac_control;
4145         config = &sp->config;
4146
4147         DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4148
4149         if (unlikely(skb->len <= 0)) {
4150                 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
4151                 dev_kfree_skb_any(skb);
4152                 return 0;
4153         }
4154
4155         if (!is_s2io_card_up(sp)) {
4156                 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4157                           dev->name);
4158                 dev_kfree_skb(skb);
4159                 return 0;
4160         }
4161
4162         queue = 0;
4163         if (sp->vlgrp && vlan_tx_tag_present(skb))
4164                 vlan_tag = vlan_tx_tag_get(skb);
4165         if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4166                 if (skb->protocol == htons(ETH_P_IP)) {
4167                         struct iphdr *ip;
4168                         struct tcphdr *th;
4169                         ip = ip_hdr(skb);
4170
4171                         if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4172                                 th = (struct tcphdr *)(((unsigned char *)ip) +
4173                                                 ip->ihl*4);
4174
4175                                 if (ip->protocol == IPPROTO_TCP) {
4176                                         queue_len = sp->total_tcp_fifos;
4177                                         queue = (ntohs(th->source) +
4178                                                         ntohs(th->dest)) &
4179                                             sp->fifo_selector[queue_len - 1];
4180                                         if (queue >= queue_len)
4181                                                 queue = queue_len - 1;
4182                                 } else if (ip->protocol == IPPROTO_UDP) {
4183                                         queue_len = sp->total_udp_fifos;
4184                                         queue = (ntohs(th->source) +
4185                                                         ntohs(th->dest)) &
4186                                             sp->fifo_selector[queue_len - 1];
4187                                         if (queue >= queue_len)
4188                                                 queue = queue_len - 1;
4189                                         queue += sp->udp_fifo_idx;
4190                                         if (skb->len > 1024)
4191                                                 enable_per_list_interrupt = 1;
4192                                         do_spin_lock = 0;
4193                                 }
4194                         }
4195                 }
4196         } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4197                 /* get fifo number based on skb->priority value */
4198                 queue = config->fifo_mapping
4199                                         [skb->priority & (MAX_TX_FIFOS - 1)];
4200         fifo = &mac_control->fifos[queue];
4201
4202         if (do_spin_lock)
4203                 spin_lock_irqsave(&fifo->tx_lock, flags);
4204         else {
4205                 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4206                         return NETDEV_TX_LOCKED;
4207         }
4208
4209 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
4210         if (sp->config.multiq) {
4211                 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4212                         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4213                         return NETDEV_TX_BUSY;
4214                 }
4215         } else
4216 #endif
4217         if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4218                 if (netif_queue_stopped(dev)) {
4219                         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4220                         return NETDEV_TX_BUSY;
4221                 }
4222         }
4223
4224         put_off = (u16) fifo->tx_curr_put_info.offset;
4225         get_off = (u16) fifo->tx_curr_get_info.offset;
4226         txdp = (struct TxD *) fifo->list_info[put_off].list_virt_addr;
4227
4228         queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4229         /* Avoid "put" pointer going beyond "get" pointer */
4230         if (txdp->Host_Control ||
4231                    ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4232                 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4233                 s2io_stop_tx_queue(sp, fifo->fifo_no);
4234                 dev_kfree_skb(skb);
4235                 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4236                 return 0;
4237         }
4238
4239         offload_type = s2io_offload_type(skb);
4240         if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4241                 txdp->Control_1 |= TXD_TCP_LSO_EN;
4242                 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4243         }
4244         if (skb->ip_summed == CHECKSUM_PARTIAL) {
4245                 txdp->Control_2 |=
4246                     (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
4247                      TXD_TX_CKO_UDP_EN);
4248         }
4249         txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4250         txdp->Control_1 |= TXD_LIST_OWN_XENA;
4251         txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4252         if (enable_per_list_interrupt)
4253                 if (put_off & (queue_len >> 5))
4254                         txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4255         if (vlan_tag) {
4256                 txdp->Control_2 |= TXD_VLAN_ENABLE;
4257                 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4258         }
4259
4260         frg_len = skb->len - skb->data_len;
4261         if (offload_type == SKB_GSO_UDP) {
4262                 int ufo_size;
4263
4264                 ufo_size = s2io_udp_mss(skb);
4265                 ufo_size &= ~7;
4266                 txdp->Control_1 |= TXD_UFO_EN;
4267                 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4268                 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4269 #ifdef __BIG_ENDIAN
4270                 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4271                 fifo->ufo_in_band_v[put_off] =
4272                                 (__force u64)skb_shinfo(skb)->ip6_frag_id;
4273 #else
4274                 fifo->ufo_in_band_v[put_off] =
4275                                 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
4276 #endif
4277                 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4278                 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4279                                         fifo->ufo_in_band_v,
4280                                         sizeof(u64), PCI_DMA_TODEVICE);
4281                 if((txdp->Buffer_Pointer == 0) ||
4282                         (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4283                         goto pci_map_failed;
4284                 txdp++;
4285         }
4286
4287         txdp->Buffer_Pointer = pci_map_single
4288             (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
4289         if((txdp->Buffer_Pointer == 0) ||
4290                 (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4291                 goto pci_map_failed;
4292
4293         txdp->Host_Control = (unsigned long) skb;
4294         txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4295         if (offload_type == SKB_GSO_UDP)
4296                 txdp->Control_1 |= TXD_UFO_EN;
4297
4298         frg_cnt = skb_shinfo(skb)->nr_frags;
4299         /* For fragmented SKB. */
4300         for (i = 0; i < frg_cnt; i++) {
4301                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4302                 /* A '0' length fragment will be ignored */
4303                 if (!frag->size)
4304                         continue;
4305                 txdp++;
4306                 txdp->Buffer_Pointer = (u64) pci_map_page
4307                     (sp->pdev, frag->page, frag->page_offset,
4308                      frag->size, PCI_DMA_TODEVICE);
4309                 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4310                 if (offload_type == SKB_GSO_UDP)
4311                         txdp->Control_1 |= TXD_UFO_EN;
4312         }
4313         txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4314
4315         if (offload_type == SKB_GSO_UDP)
4316                 frg_cnt++; /* as Txd0 was used for inband header */
4317
4318         tx_fifo = mac_control->tx_FIFO_start[queue];
4319         val64 = fifo->list_info[put_off].list_phy_addr;
4320         writeq(val64, &tx_fifo->TxDL_Pointer);
4321
4322         val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4323                  TX_FIFO_LAST_LIST);
4324         if (offload_type)
4325                 val64 |= TX_FIFO_SPECIAL_FUNC;
4326
4327         writeq(val64, &tx_fifo->List_Control);
4328
4329         mmiowb();
4330
4331         put_off++;
4332         if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4333                 put_off = 0;
4334         fifo->tx_curr_put_info.offset = put_off;
4335
4336         /* Avoid "put" pointer going beyond "get" pointer */
4337         if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4338                 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
4339                 DBG_PRINT(TX_DBG,
4340                           "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4341                           put_off, get_off);
4342                 s2io_stop_tx_queue(sp, fifo->fifo_no);
4343         }
4344         mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
4345         dev->trans_start = jiffies;
4346         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4347
4348         return 0;
4349 pci_map_failed:
4350         stats->pci_map_fail_cnt++;
4351         s2io_stop_tx_queue(sp, fifo->fifo_no);
4352         stats->mem_freed += skb->truesize;
4353         dev_kfree_skb(skb);
4354         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4355         return 0;
4356 }
4357
4358 static void
4359 s2io_alarm_handle(unsigned long data)
4360 {
4361         struct s2io_nic *sp = (struct s2io_nic *)data;
4362         struct net_device *dev = sp->dev;
4363
4364         s2io_handle_errors(dev);
4365         mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4366 }
4367
4368 static int s2io_chk_rx_buffers(struct s2io_nic *sp, int rng_n)
4369 {
4370         int rxb_size, level;
4371
4372         if (!sp->lro) {
4373                 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4374                 level = rx_buffer_level(sp, rxb_size, rng_n);
4375
4376                 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4377                         int ret;
4378                         DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4379                         DBG_PRINT(INTR_DBG, "PANIC levels\n");
4380                         if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
4381                                 DBG_PRINT(INFO_DBG, "Out of memory in %s",
4382                                           __FUNCTION__);
4383                                 clear_bit(0, (&sp->tasklet_status));
4384                                 return -1;
4385                         }
4386                         clear_bit(0, (&sp->tasklet_status));
4387                 } else if (level == LOW)
4388                         tasklet_schedule(&sp->task);
4389
4390         } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
4391                         DBG_PRINT(INFO_DBG, "%s:Out of memory", sp->dev->name);
4392                         DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
4393         }
4394         return 0;
4395 }
4396
4397 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4398 {
4399         struct ring_info *ring = (struct ring_info *)dev_id;
4400         struct s2io_nic *sp = ring->nic;
4401
4402         if (!is_s2io_card_up(sp))
4403                 return IRQ_HANDLED;
4404
4405         rx_intr_handler(ring);
4406         s2io_chk_rx_buffers(sp, ring->ring_no);
4407
4408         return IRQ_HANDLED;
4409 }
4410
4411 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4412 {
4413         struct fifo_info *fifo = (struct fifo_info *)dev_id;
4414         struct s2io_nic *sp = fifo->nic;
4415
4416         if (!is_s2io_card_up(sp))
4417                 return IRQ_HANDLED;
4418
4419         tx_intr_handler(fifo);
4420         return IRQ_HANDLED;
4421 }
4422 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4423 {
4424         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4425         u64 val64;
4426
4427         val64 = readq(&bar0->pic_int_status);
4428         if (val64 & PIC_INT_GPIO) {
4429                 val64 = readq(&bar0->gpio_int_reg);
4430                 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4431                     (val64 & GPIO_INT_REG_LINK_UP)) {
4432                         /*
4433                          * This is unstable state so clear both up/down
4434                          * interrupt and adapter to re-evaluate the link state.
4435                          */
4436                         val64 |=  GPIO_INT_REG_LINK_DOWN;
4437                         val64 |= GPIO_INT_REG_LINK_UP;
4438                         writeq(val64, &bar0->gpio_int_reg);
4439                         val64 = readq(&bar0->gpio_int_mask);
4440                         val64 &= ~(GPIO_INT_MASK_LINK_UP |
4441                                    GPIO_INT_MASK_LINK_DOWN);
4442                         writeq(val64, &bar0->gpio_int_mask);
4443                 }
4444                 else if (val64 & GPIO_INT_REG_LINK_UP) {
4445                         val64 = readq(&bar0->adapter_status);
4446                                 /* Enable Adapter */
4447                         val64 = readq(&bar0->adapter_control);
4448                         val64 |= ADAPTER_CNTL_EN;
4449                         writeq(val64, &bar0->adapter_control);
4450                         val64 |= ADAPTER_LED_ON;
4451                         writeq(val64, &bar0->adapter_control);
4452                         if (!sp->device_enabled_once)
4453                                 sp->device_enabled_once = 1;
4454
4455                         s2io_link(sp, LINK_UP);
4456                         /*
4457                          * unmask link down interrupt and mask link-up
4458                          * intr
4459                          */
4460                         val64 = readq(&bar0->gpio_int_mask);
4461                         val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4462                         val64 |= GPIO_INT_MASK_LINK_UP;
4463                         writeq(val64, &bar0->gpio_int_mask);
4464
4465                 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4466                         val64 = readq(&bar0->adapter_status);
4467                         s2io_link(sp, LINK_DOWN);
4468                         /* Link is down so unmaks link up interrupt */
4469                         val64 = readq(&bar0->gpio_int_mask);
4470                         val64 &= ~GPIO_INT_MASK_LINK_UP;
4471                         val64 |= GPIO_INT_MASK_LINK_DOWN;
4472                         writeq(val64, &bar0->gpio_int_mask);
4473
4474                         /* turn off LED */
4475                         val64 = readq(&bar0->adapter_control);
4476                         val64 = val64 &(~ADAPTER_LED_ON);
4477                         writeq(val64, &bar0->adapter_control);
4478                 }
4479         }
4480         val64 = readq(&bar0->gpio_int_mask);
4481 }
4482
4483 /**
4484  *  do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4485  *  @value: alarm bits
4486  *  @addr: address value
4487  *  @cnt: counter variable
4488  *  Description: Check for alarm and increment the counter
4489  *  Return Value:
4490  *  1 - if alarm bit set
4491  *  0 - if alarm bit is not set
4492  */
4493 static int do_s2io_chk_alarm_bit(u64 value, void __iomem * addr,
4494                           unsigned long long *cnt)
4495 {
4496         u64 val64;
4497         val64 = readq(addr);
4498         if ( val64 & value ) {
4499                 writeq(val64, addr);
4500                 (*cnt)++;
4501                 return 1;
4502         }
4503         return 0;
4504
4505 }
4506
4507 /**
4508  *  s2io_handle_errors - Xframe error indication handler
4509  *  @nic: device private variable
4510  *  Description: Handle alarms such as loss of link, single or
4511  *  double ECC errors, critical and serious errors.
4512  *  Return Value:
4513  *  NONE
4514  */
4515 static void s2io_handle_errors(void * dev_id)
4516 {
4517         struct net_device *dev = (struct net_device *) dev_id;
4518         struct s2io_nic *sp = dev->priv;
4519         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4520         u64 temp64 = 0,val64=0;
4521         int i = 0;
4522
4523         struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4524         struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4525
4526         if (!is_s2io_card_up(sp))
4527                 return;
4528
4529         if (pci_channel_offline(sp->pdev))
4530                 return;
4531
4532         memset(&sw_stat->ring_full_cnt, 0,
4533                 sizeof(sw_stat->ring_full_cnt));
4534
4535         /* Handling the XPAK counters update */
4536         if(stats->xpak_timer_count < 72000) {
4537                 /* waiting for an hour */
4538                 stats->xpak_timer_count++;
4539         } else {
4540                 s2io_updt_xpak_counter(dev);
4541                 /* reset the count to zero */
4542                 stats->xpak_timer_count = 0;
4543         }
4544
4545         /* Handling link status change error Intr */
4546         if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4547                 val64 = readq(&bar0->mac_rmac_err_reg);
4548                 writeq(val64, &bar0->mac_rmac_err_reg);
4549                 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4550                         schedule_work(&sp->set_link_task);
4551         }
4552
4553         /* In case of a serious error, the device will be Reset. */
4554         if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4555                                 &sw_stat->serious_err_cnt))
4556                 goto reset;
4557
4558         /* Check for data parity error */
4559         if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4560                                 &sw_stat->parity_err_cnt))
4561                 goto reset;
4562
4563         /* Check for ring full counter */
4564         if (sp->device_type == XFRAME_II_DEVICE) {
4565                 val64 = readq(&bar0->ring_bump_counter1);
4566                 for (i=0; i<4; i++) {
4567                         temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4568                         temp64 >>= 64 - ((i+1)*16);
4569                         sw_stat->ring_full_cnt[i] += temp64;
4570                 }
4571
4572                 val64 = readq(&bar0->ring_bump_counter2);
4573                 for (i=0; i<4; i++) {
4574                         temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4575                         temp64 >>= 64 - ((i+1)*16);
4576                          sw_stat->ring_full_cnt[i+4] += temp64;
4577                 }
4578         }
4579
4580         val64 = readq(&bar0->txdma_int_status);
4581         /*check for pfc_err*/
4582         if (val64 & TXDMA_PFC_INT) {
4583                 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM|
4584                                 PFC_MISC_0_ERR | PFC_MISC_1_ERR|
4585                                 PFC_PCIX_ERR, &bar0->pfc_err_reg,
4586                                 &sw_stat->pfc_err_cnt))
4587                         goto reset;
4588                 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, &bar0->pfc_err_reg,
4589                                 &sw_stat->pfc_err_cnt);
4590         }
4591
4592         /*check for tda_err*/
4593         if (val64 & TXDMA_TDA_INT) {
4594                 if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
4595                                 TDA_SM1_ERR_ALARM, &bar0->tda_err_reg,
4596                                 &sw_stat->tda_err_cnt))
4597                         goto reset;
4598                 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4599                                 &bar0->tda_err_reg, &sw_stat->tda_err_cnt);
4600         }
4601         /*check for pcc_err*/
4602         if (val64 & TXDMA_PCC_INT) {
4603                 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM
4604                                 | PCC_N_SERR | PCC_6_COF_OV_ERR
4605                                 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR
4606                                 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR
4607                                 | PCC_TXB_ECC_DB_ERR, &bar0->pcc_err_reg,
4608                                 &sw_stat->pcc_err_cnt))
4609                         goto reset;
4610                 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4611                                 &bar0->pcc_err_reg, &sw_stat->pcc_err_cnt);
4612         }
4613
4614         /*check for tti_err*/
4615         if (val64 & TXDMA_TTI_INT) {
4616                 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, &bar0->tti_err_reg,
4617                                 &sw_stat->tti_err_cnt))
4618                         goto reset;
4619                 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4620                                 &bar0->tti_err_reg, &sw_stat->tti_err_cnt);
4621         }
4622
4623         /*check for lso_err*/
4624         if (val64 & TXDMA_LSO_INT) {
4625                 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT
4626                                 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4627                                 &bar0->lso_err_reg, &sw_stat->lso_err_cnt))
4628                         goto reset;
4629                 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4630                                 &bar0->lso_err_reg, &sw_stat->lso_err_cnt);
4631         }
4632
4633         /*check for tpa_err*/
4634         if (val64 & TXDMA_TPA_INT) {
4635                 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, &bar0->tpa_err_reg,
4636                         &sw_stat->tpa_err_cnt))
4637                         goto reset;
4638                 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, &bar0->tpa_err_reg,
4639                         &sw_stat->tpa_err_cnt);
4640         }
4641
4642         /*check for sm_err*/
4643         if (val64 & TXDMA_SM_INT) {
4644                 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, &bar0->sm_err_reg,
4645                         &sw_stat->sm_err_cnt))
4646                         goto reset;
4647         }
4648
4649         val64 = readq(&bar0->mac_int_status);
4650         if (val64 & MAC_INT_STATUS_TMAC_INT) {
4651                 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4652                                 &bar0->mac_tmac_err_reg,
4653                                 &sw_stat->mac_tmac_err_cnt))
4654                         goto reset;
4655                 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR
4656                                 | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
4657                                 &bar0->mac_tmac_err_reg,
4658                                 &sw_stat->mac_tmac_err_cnt);
4659         }
4660
4661         val64 = readq(&bar0->xgxs_int_status);
4662         if (val64 & XGXS_INT_STATUS_TXGXS) {
4663                 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4664                                 &bar0->xgxs_txgxs_err_reg,
4665                                 &sw_stat->xgxs_txgxs_err_cnt))
4666                         goto reset;
4667                 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4668                                 &bar0->xgxs_txgxs_err_reg,
4669                                 &sw_stat->xgxs_txgxs_err_cnt);
4670         }
4671
4672         val64 = readq(&bar0->rxdma_int_status);
4673         if (val64 & RXDMA_INT_RC_INT_M) {
4674                 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR
4675                                 | RC_PRCn_SM_ERR_ALARM |RC_FTC_SM_ERR_ALARM,
4676                                 &bar0->rc_err_reg, &sw_stat->rc_err_cnt))
4677                         goto reset;
4678                 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR
4679                                 | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4680                                 &sw_stat->rc_err_cnt);
4681                 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn
4682                                 | PRC_PCI_AB_F_WR_Rn, &bar0->prc_pcix_err_reg,
4683                                 &sw_stat->prc_pcix_err_cnt))
4684                         goto reset;
4685                 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | PRC_PCI_DP_WR_Rn
4686                                 | PRC_PCI_DP_F_WR_Rn, &bar0->prc_pcix_err_reg,
4687                                 &sw_stat->prc_pcix_err_cnt);
4688         }
4689
4690         if (val64 & RXDMA_INT_RPA_INT_M) {
4691                 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4692                                 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt))
4693                         goto reset;
4694                 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4695                                 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt);
4696         }
4697
4698         if (val64 & RXDMA_INT_RDA_INT_M) {
4699                 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
4700                                 | RDA_FRM_ECC_DB_N_AERR | RDA_SM1_ERR_ALARM
4701                                 | RDA_SM0_ERR_ALARM | RDA_RXD_ECC_DB_SERR,
4702                                 &bar0->rda_err_reg, &sw_stat->rda_err_cnt))
4703                         goto reset;
4704                 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | RDA_FRM_ECC_SG_ERR
4705                                 | RDA_MISC_ERR | RDA_PCIX_ERR,
4706                                 &bar0->rda_err_reg, &sw_stat->rda_err_cnt);
4707         }
4708
4709         if (val64 & RXDMA_INT_RTI_INT_M) {
4710                 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, &bar0->rti_err_reg,
4711                                 &sw_stat->rti_err_cnt))
4712                         goto reset;
4713                 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4714                                 &bar0->rti_err_reg, &sw_stat->rti_err_cnt);
4715         }
4716
4717         val64 = readq(&bar0->mac_int_status);
4718         if (val64 & MAC_INT_STATUS_RMAC_INT) {
4719                 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4720                                 &bar0->mac_rmac_err_reg,
4721                                 &sw_stat->mac_rmac_err_cnt))
4722                         goto reset;
4723                 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT|RMAC_SINGLE_ECC_ERR|
4724                                 RMAC_DOUBLE_ECC_ERR, &bar0->mac_rmac_err_reg,
4725                                 &sw_stat->mac_rmac_err_cnt);
4726         }
4727
4728         val64 = readq(&bar0->xgxs_int_status);
4729         if (val64 & XGXS_INT_STATUS_RXGXS) {
4730                 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4731                                 &bar0->xgxs_rxgxs_err_reg,
4732                                 &sw_stat->xgxs_rxgxs_err_cnt))
4733                         goto reset;
4734         }
4735
4736         val64 = readq(&bar0->mc_int_status);
4737         if(val64 & MC_INT_STATUS_MC_INT) {
4738                 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, &bar0->mc_err_reg,
4739                                 &sw_stat->mc_err_cnt))
4740                         goto reset;
4741
4742                 /* Handling Ecc errors */
4743                 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4744                         writeq(val64, &bar0->mc_err_reg);
4745                         if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4746                                 sw_stat->double_ecc_errs++;
4747                                 if (sp->device_type != XFRAME_II_DEVICE) {
4748                                         /*
4749                                          * Reset XframeI only if critical error
4750                                          */
4751                                         if (val64 &
4752                                                 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4753                                                 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4754                                                                 goto reset;
4755                                         }
4756                         } else
4757                                 sw_stat->single_ecc_errs++;
4758                 }
4759         }
4760         return;
4761
4762 reset:
4763         s2io_stop_all_tx_queue(sp);
4764         schedule_work(&sp->rst_timer_task);
4765         sw_stat->soft_reset_cnt++;
4766         return;
4767 }
4768
4769 /**
4770  *  s2io_isr - ISR handler of the device .
4771  *  @irq: the irq of the device.
4772  *  @dev_id: a void pointer to the dev structure of the NIC.
4773  *  Description:  This function is the ISR handler of the device. It
4774  *  identifies the reason for the interrupt and calls the relevant
4775  *  service routines. As a contongency measure, this ISR allocates the
4776  *  recv buffers, if their numbers are below the panic value which is
4777  *  presently set to 25% of the original number of rcv buffers allocated.
4778  *  Return value:
4779  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
4780  *   IRQ_NONE: will be returned if interrupt is not from our device
4781  */
4782 static irqreturn_t s2io_isr(int irq, void *dev_id)
4783 {
4784         struct net_device *dev = (struct net_device *) dev_id;
4785         struct s2io_nic *sp = dev->priv;
4786         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4787         int i;
4788         u64 reason = 0;
4789         struct mac_info *mac_control;
4790         struct config_param *config;
4791
4792         /* Pretend we handled any irq's from a disconnected card */
4793         if (pci_channel_offline(sp->pdev))
4794                 return IRQ_NONE;
4795
4796         if (!is_s2io_card_up(sp))
4797                 return IRQ_NONE;
4798
4799         mac_control = &sp->mac_control;
4800         config = &sp->config;
4801
4802         /*
4803          * Identify the cause for interrupt and call the appropriate
4804          * interrupt handler. Causes for the interrupt could be;
4805          * 1. Rx of packet.
4806          * 2. Tx complete.
4807          * 3. Link down.
4808          */
4809         reason = readq(&bar0->general_int_status);
4810
4811         if (unlikely(reason == S2IO_MINUS_ONE) ) {
4812                 /* Nothing much can be done. Get out */
4813                 return IRQ_HANDLED;
4814         }
4815
4816         if (reason & (GEN_INTR_RXTRAFFIC |
4817                 GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC))
4818         {
4819                 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4820
4821                 if (config->napi) {
4822                         if (reason & GEN_INTR_RXTRAFFIC) {
4823                                 if (likely(netif_rx_schedule_prep(dev,
4824                                                         &sp->napi))) {
4825                                         __netif_rx_schedule(dev, &sp->napi);
4826                                         writeq(S2IO_MINUS_ONE,
4827                                                &bar0->rx_traffic_mask);
4828                                 } else
4829                                         writeq(S2IO_MINUS_ONE,
4830                                                &bar0->rx_traffic_int);
4831                         }
4832                 } else {
4833                         /*
4834                          * rx_traffic_int reg is an R1 register, writing all 1's
4835                          * will ensure that the actual interrupt causing bit
4836                          * get's cleared and hence a read can be avoided.
4837                          */
4838                         if (reason & GEN_INTR_RXTRAFFIC)
4839                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4840
4841                         for (i = 0; i < config->rx_ring_num; i++)
4842                                 rx_intr_handler(&mac_control->rings[i]);
4843                 }
4844
4845                 /*
4846                  * tx_traffic_int reg is an R1 register, writing all 1's
4847                  * will ensure that the actual interrupt causing bit get's
4848                  * cleared and hence a read can be avoided.
4849                  */
4850                 if (reason & GEN_INTR_TXTRAFFIC)
4851                         writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4852
4853                 for (i = 0; i < config->tx_fifo_num; i++)
4854                         tx_intr_handler(&mac_control->fifos[i]);
4855
4856                 if (reason & GEN_INTR_TXPIC)
4857                         s2io_txpic_intr_handle(sp);
4858
4859                 /*
4860                  * Reallocate the buffers from the interrupt handler itself.
4861                  */
4862                 if (!config->napi) {
4863                         for (i = 0; i < config->rx_ring_num; i++)
4864                                 s2io_chk_rx_buffers(sp, i);
4865                 }
4866                 writeq(sp->general_int_mask, &bar0->general_int_mask);
4867                 readl(&bar0->general_int_status);
4868
4869                 return IRQ_HANDLED;
4870
4871         }
4872         else if (!reason) {
4873                 /* The interrupt was not raised by us */
4874                 return IRQ_NONE;
4875         }
4876
4877         return IRQ_HANDLED;
4878 }
4879
4880 /**
4881  * s2io_updt_stats -
4882  */
4883 static void s2io_updt_stats(struct s2io_nic *sp)
4884 {
4885         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4886         u64 val64;
4887         int cnt = 0;
4888
4889         if (is_s2io_card_up(sp)) {
4890                 /* Apprx 30us on a 133 MHz bus */
4891                 val64 = SET_UPDT_CLICKS(10) |
4892                         STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4893                 writeq(val64, &bar0->stat_cfg);
4894                 do {
4895                         udelay(100);
4896                         val64 = readq(&bar0->stat_cfg);
4897                         if (!(val64 & s2BIT(0)))
4898                                 break;
4899                         cnt++;
4900                         if (cnt == 5)
4901                                 break; /* Updt failed */
4902                 } while(1);
4903         }
4904 }
4905
4906 /**
4907  *  s2io_get_stats - Updates the device statistics structure.
4908  *  @dev : pointer to the device structure.
4909  *  Description:
4910  *  This function updates the device statistics structure in the s2io_nic
4911  *  structure and returns a pointer to the same.
4912  *  Return value:
4913  *  pointer to the updated net_device_stats structure.
4914  */
4915
4916 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4917 {
4918         struct s2io_nic *sp = dev->priv;
4919         struct mac_info *mac_control;
4920         struct config_param *config;
4921
4922
4923         mac_control = &sp->mac_control;
4924         config = &sp->config;
4925
4926         /* Configure Stats for immediate updt */
4927         s2io_updt_stats(sp);
4928
4929         sp->stats.tx_packets =
4930                 le32_to_cpu(mac_control->stats_info->tmac_frms);
4931         sp->stats.tx_errors =
4932                 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4933         sp->stats.rx_errors =
4934                 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
4935         sp->stats.multicast =
4936                 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
4937         sp->stats.rx_length_errors =
4938                 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
4939
4940         return (&sp->stats);
4941 }
4942
4943 /**
4944  *  s2io_set_multicast - entry point for multicast address enable/disable.
4945  *  @dev : pointer to the device structure
4946  *  Description:
4947  *  This function is a driver entry point which gets called by the kernel
4948  *  whenever multicast addresses must be enabled/disabled. This also gets
4949  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
4950  *  determine, if multicast address must be enabled or if promiscuous mode
4951  *  is to be disabled etc.
4952  *  Return value:
4953  *  void.
4954  */
4955
4956 static void s2io_set_multicast(struct net_device *dev)
4957 {
4958         int i, j, prev_cnt;
4959         struct dev_mc_list *mclist;
4960         struct s2io_nic *sp = dev->priv;
4961         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4962         u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4963             0xfeffffffffffULL;
4964         u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
4965         void __iomem *add;
4966         struct config_param *config = &sp->config;
4967
4968         if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4969                 /*  Enable all Multicast addresses */
4970                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4971                        &bar0->rmac_addr_data0_mem);
4972                 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4973                        &bar0->rmac_addr_data1_mem);
4974                 val64 = RMAC_ADDR_CMD_MEM_WE |
4975                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4976                     RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
4977                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4978                 /* Wait till command completes */
4979                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4980                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4981                                         S2IO_BIT_RESET);
4982
4983                 sp->m_cast_flg = 1;
4984                 sp->all_multi_pos = config->max_mc_addr - 1;
4985         } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4986                 /*  Disable all Multicast addresses */
4987                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4988                        &bar0->rmac_addr_data0_mem);
4989                 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4990                        &bar0->rmac_addr_data1_mem);
4991                 val64 = RMAC_ADDR_CMD_MEM_WE |
4992                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4993                     RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4994                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4995                 /* Wait till command completes */
4996                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4997                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4998                                         S2IO_BIT_RESET);
4999
5000                 sp->m_cast_flg = 0;
5001                 sp->all_multi_pos = 0;
5002         }
5003
5004         if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5005                 /*  Put the NIC into promiscuous mode */
5006                 add = &bar0->mac_cfg;
5007                 val64 = readq(&bar0->mac_cfg);
5008                 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5009
5010                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5011                 writel((u32) val64, add);
5012                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5013                 writel((u32) (val64 >> 32), (add + 4));
5014
5015                 if (vlan_tag_strip != 1) {
5016                         val64 = readq(&bar0->rx_pa_cfg);
5017                         val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5018                         writeq(val64, &bar0->rx_pa_cfg);
5019                         vlan_strip_flag = 0;
5020                 }
5021
5022                 val64 = readq(&bar0->mac_cfg);
5023                 sp->promisc_flg = 1;
5024                 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
5025                           dev->name);
5026         } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5027                 /*  Remove the NIC from promiscuous mode */
5028                 add = &bar0->mac_cfg;
5029                 val64 = readq(&bar0->mac_cfg);
5030                 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5031
5032                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5033                 writel((u32) val64, add);
5034                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5035                 writel((u32) (val64 >> 32), (add + 4));
5036
5037                 if (vlan_tag_strip != 0) {
5038                         val64 = readq(&bar0->rx_pa_cfg);
5039                         val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5040                         writeq(val64, &bar0->rx_pa_cfg);
5041                         vlan_strip_flag = 1;
5042                 }
5043
5044                 val64 = readq(&bar0->mac_cfg);
5045                 sp->promisc_flg = 0;
5046                 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
5047                           dev->name);
5048         }
5049
5050         /*  Update individual M_CAST address list */
5051         if ((!sp->m_cast_flg) && dev->mc_count) {
5052                 if (dev->mc_count >
5053                     (config->max_mc_addr - config->max_mac_addr)) {
5054                         DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
5055                                   dev->name);
5056                         DBG_PRINT(ERR_DBG, "can be added, please enable ");
5057                         DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
5058                         return;
5059                 }
5060
5061                 prev_cnt = sp->mc_addr_count;
5062                 sp->mc_addr_count = dev->mc_count;
5063
5064                 /* Clear out the previous list of Mc in the H/W. */
5065                 for (i = 0; i < prev_cnt; i++) {
5066                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5067                                &bar0->rmac_addr_data0_mem);
5068                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5069                                 &bar0->rmac_addr_data1_mem);
5070                         val64 = RMAC_ADDR_CMD_MEM_WE |
5071                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5072                             RMAC_ADDR_CMD_MEM_OFFSET
5073                             (config->mc_start_offset + i);
5074                         writeq(val64, &bar0->rmac_addr_cmd_mem);
5075
5076                         /* Wait for command completes */
5077                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5078                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5079                                         S2IO_BIT_RESET)) {
5080                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
5081                                           dev->name);
5082                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5083                                 return;
5084                         }
5085                 }
5086
5087                 /* Create the new Rx filter list and update the same in H/W. */
5088                 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
5089                      i++, mclist = mclist->next) {
5090                         memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
5091                                ETH_ALEN);
5092                         mac_addr = 0;
5093                         for (j = 0; j < ETH_ALEN; j++) {
5094                                 mac_addr |= mclist->dmi_addr[j];
5095                                 mac_addr <<= 8;
5096                         }
5097                         mac_addr >>= 8;
5098                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5099                                &bar0->rmac_addr_data0_mem);
5100                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5101                                 &bar0->rmac_addr_data1_mem);
5102                         val64 = RMAC_ADDR_CMD_MEM_WE |
5103                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5104                             RMAC_ADDR_CMD_MEM_OFFSET
5105                             (i + config->mc_start_offset);
5106                         writeq(val64, &bar0->rmac_addr_cmd_mem);
5107
5108                         /* Wait for command completes */
5109                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5110                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5111                                         S2IO_BIT_RESET)) {
5112                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
5113                                           dev->name);
5114                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5115                                 return;
5116                         }
5117                 }
5118         }
5119 }
5120
5121 /* read from CAM unicast & multicast addresses and store it in
5122  * def_mac_addr structure
5123  */
5124 void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5125 {
5126         int offset;
5127         u64 mac_addr = 0x0;
5128         struct config_param *config = &sp->config;
5129
5130         /* store unicast & multicast mac addresses */
5131         for (offset = 0; offset < config->max_mc_addr; offset++) {
5132                 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5133                 /* if read fails disable the entry */
5134                 if (mac_addr == FAILURE)
5135                         mac_addr = S2IO_DISABLE_MAC_ENTRY;
5136                 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5137         }
5138 }
5139
5140 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5141 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5142 {
5143         int offset;
5144         struct config_param *config = &sp->config;
5145         /* restore unicast mac address */
5146         for (offset = 0; offset < config->max_mac_addr; offset++)
5147                 do_s2io_prog_unicast(sp->dev,
5148                         sp->def_mac_addr[offset].mac_addr);
5149
5150         /* restore multicast mac address */
5151         for (offset = config->mc_start_offset;
5152                 offset < config->max_mc_addr; offset++)
5153                 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5154 }
5155
5156 /* add a multicast MAC address to CAM */
5157 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5158 {
5159         int i;
5160         u64 mac_addr = 0;
5161         struct config_param *config = &sp->config;
5162
5163         for (i = 0; i < ETH_ALEN; i++) {
5164                 mac_addr <<= 8;
5165                 mac_addr |= addr[i];
5166         }
5167         if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5168                 return SUCCESS;
5169
5170         /* check if the multicast mac already preset in CAM */
5171         for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5172                 u64 tmp64;
5173                 tmp64 = do_s2io_read_unicast_mc(sp, i);
5174                 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5175                         break;
5176
5177                 if (tmp64 == mac_addr)
5178                         return SUCCESS;
5179         }
5180         if (i == config->max_mc_addr) {
5181                 DBG_PRINT(ERR_DBG,
5182                         "CAM full no space left for multicast MAC\n");
5183                 return FAILURE;
5184         }
5185         /* Update the internal structure with this new mac address */
5186         do_s2io_copy_mac_addr(sp, i, mac_addr);
5187
5188         return (do_s2io_add_mac(sp, mac_addr, i));
5189 }
5190
5191 /* add MAC address to CAM */
5192 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5193 {
5194         u64 val64;
5195         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5196
5197         writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5198                 &bar0->rmac_addr_data0_mem);
5199
5200         val64 =
5201                 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5202                 RMAC_ADDR_CMD_MEM_OFFSET(off);
5203         writeq(val64, &bar0->rmac_addr_cmd_mem);
5204
5205         /* Wait till command completes */
5206         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5207                 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5208                 S2IO_BIT_RESET)) {
5209                 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5210                 return FAILURE;
5211         }
5212         return SUCCESS;
5213 }
5214 /* deletes a specified unicast/multicast mac entry from CAM */
5215 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5216 {
5217         int offset;
5218         u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5219         struct config_param *config = &sp->config;
5220
5221         for (offset = 1;
5222                 offset < config->max_mc_addr; offset++) {
5223                 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5224                 if (tmp64 == addr) {
5225                         /* disable the entry by writing  0xffffffffffffULL */
5226                         if (do_s2io_add_mac(sp, dis_addr, offset) ==  FAILURE)
5227                                 return FAILURE;
5228                         /* store the new mac list from CAM */
5229                         do_s2io_store_unicast_mc(sp);
5230                         return SUCCESS;
5231                 }
5232         }
5233         DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5234                         (unsigned long long)addr);
5235         return FAILURE;
5236 }
5237
5238 /* read mac entries from CAM */
5239 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5240 {
5241         u64 tmp64 = 0xffffffffffff0000ULL, val64;
5242         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5243
5244         /* read mac addr */
5245         val64 =
5246                 RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5247                 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5248         writeq(val64, &bar0->rmac_addr_cmd_mem);
5249
5250         /* Wait till command completes */
5251         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5252                 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5253                 S2IO_BIT_RESET)) {
5254                 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5255                 return FAILURE;
5256         }
5257         tmp64 = readq(&bar0->rmac_addr_data0_mem);
5258         return (tmp64 >> 16);
5259 }
5260
5261 /**
5262  * s2io_set_mac_addr driver entry point
5263  */
5264
5265 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5266 {
5267         struct sockaddr *addr = p;
5268
5269         if (!is_valid_ether_addr(addr->sa_data))
5270                 return -EINVAL;
5271
5272         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5273
5274         /* store the MAC address in CAM */
5275         return (do_s2io_prog_unicast(dev, dev->dev_addr));
5276 }
5277 /**
5278  *  do_s2io_prog_unicast - Programs the Xframe mac address
5279  *  @dev : pointer to the device structure.
5280  *  @addr: a uchar pointer to the new mac address which is to be set.
5281  *  Description : This procedure will program the Xframe to receive
5282  *  frames with new Mac Address
5283  *  Return value: SUCCESS on success and an appropriate (-)ve integer
5284  *  as defined in errno.h file on failure.
5285  */
5286
5287 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5288 {
5289         struct s2io_nic *sp = dev->priv;
5290         register u64 mac_addr = 0, perm_addr = 0;
5291         int i;
5292         u64 tmp64;
5293         struct config_param *config = &sp->config;
5294
5295         /*
5296         * Set the new MAC address as the new unicast filter and reflect this
5297         * change on the device address registered with the OS. It will be
5298         * at offset 0.
5299         */
5300         for (i = 0; i < ETH_ALEN; i++) {
5301                 mac_addr <<= 8;
5302                 mac_addr |= addr[i];
5303                 perm_addr <<= 8;
5304                 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5305         }
5306
5307         /* check if the dev_addr is different than perm_addr */
5308         if (mac_addr == perm_addr)
5309                 return SUCCESS;
5310
5311         /* check if the mac already preset in CAM */
5312         for (i = 1; i < config->max_mac_addr; i++) {
5313                 tmp64 = do_s2io_read_unicast_mc(sp, i);
5314                 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5315                         break;
5316
5317                 if (tmp64 == mac_addr) {
5318                         DBG_PRINT(INFO_DBG,
5319                         "MAC addr:0x%llx already present in CAM\n",
5320                         (unsigned long long)mac_addr);
5321                         return SUCCESS;
5322                 }
5323         }
5324         if (i == config->max_mac_addr) {
5325                 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5326                 return FAILURE;
5327         }
5328         /* Update the internal structure with this new mac address */
5329         do_s2io_copy_mac_addr(sp, i, mac_addr);
5330         return (do_s2io_add_mac(sp, mac_addr, i));
5331 }
5332
5333 /**
5334  * s2io_ethtool_sset - Sets different link parameters.
5335  * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
5336  * @info: pointer to the structure with parameters given by ethtool to set
5337  * link information.
5338  * Description:
5339  * The function sets different link parameters provided by the user onto
5340  * the NIC.
5341  * Return value:
5342  * 0 on success.
5343 */
5344
5345 static int s2io_ethtool_sset(struct net_device *dev,
5346                              struct ethtool_cmd *info)
5347 {
5348         struct s2io_nic *sp = dev->priv;
5349         if ((info->autoneg == AUTONEG_ENABLE) ||
5350             (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
5351                 return -EINVAL;
5352         else {
5353                 s2io_close(sp->dev);
5354                 s2io_open(sp->dev);
5355         }
5356
5357         return 0;
5358 }
5359
5360 /**
5361  * s2io_ethtol_gset - Return link specific information.
5362  * @sp : private member of the device structure, pointer to the
5363  *      s2io_nic structure.
5364  * @info : pointer to the structure with parameters given by ethtool
5365  * to return link information.
5366  * Description:
5367  * Returns link specific information like speed, duplex etc.. to ethtool.
5368  * Return value :
5369  * return 0 on success.
5370  */
5371
5372 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5373 {
5374         struct s2io_nic *sp = dev->priv;
5375         info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5376         info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5377         info->port = PORT_FIBRE;
5378
5379         /* info->transceiver */
5380         info->transceiver = XCVR_EXTERNAL;
5381
5382         if (netif_carrier_ok(sp->dev)) {
5383                 info->speed = 10000;
5384                 info->duplex = DUPLEX_FULL;
5385         } else {
5386                 info->speed = -1;
5387                 info->duplex = -1;
5388         }
5389
5390         info->autoneg = AUTONEG_DISABLE;
5391         return 0;
5392 }
5393
5394 /**
5395  * s2io_ethtool_gdrvinfo - Returns driver specific information.
5396  * @sp : private member of the device structure, which is a pointer to the
5397  * s2io_nic structure.
5398  * @info : pointer to the structure with parameters given by ethtool to
5399  * return driver information.
5400  * Description:
5401  * Returns driver specefic information like name, version etc.. to ethtool.
5402  * Return value:
5403  *  void
5404  */
5405
5406 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5407                                   struct ethtool_drvinfo *info)
5408 {
5409         struct s2io_nic *sp = dev->priv;
5410
5411         strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5412         strncpy(info->version, s2io_driver_version, sizeof(info->version));
5413         strncpy(info->fw_version, "", sizeof(info->fw_version));
5414         strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5415         info->regdump_len = XENA_REG_SPACE;
5416         info->eedump_len = XENA_EEPROM_SPACE;
5417 }
5418
5419 /**
5420  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5421  *  @sp: private member of the device structure, which is a pointer to the
5422  *  s2io_nic structure.
5423  *  @regs : pointer to the structure with parameters given by ethtool for
5424  *  dumping the registers.
5425  *  @reg_space: The input argumnet into which all the registers are dumped.
5426  *  Description:
5427  *  Dumps the entire register space of xFrame NIC into the user given
5428  *  buffer area.
5429  * Return value :
5430  * void .
5431 */
5432
5433 static void s2io_ethtool_gregs(struct net_device *dev,
5434                                struct ethtool_regs *regs, void *space)
5435 {
5436         int i;
5437         u64 reg;
5438         u8 *reg_space = (u8 *) space;
5439         struct s2io_nic *sp = dev->priv;
5440
5441         regs->len = XENA_REG_SPACE;
5442         regs->version = sp->pdev->subsystem_device;
5443
5444         for (i = 0; i < regs->len; i += 8) {
5445                 reg = readq(sp->bar0 + i);
5446                 memcpy((reg_space + i), &reg, 8);
5447         }
5448 }
5449
5450 /**
5451  *  s2io_phy_id  - timer function that alternates adapter LED.
5452  *  @data : address of the private member of the device structure, which
5453  *  is a pointer to the s2io_nic structure, provided as an u32.
5454  * Description: This is actually the timer function that alternates the
5455  * adapter LED bit of the adapter control bit to set/reset every time on
5456  * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
5457  *  once every second.
5458 */
5459 static void s2io_phy_id(unsigned long data)
5460 {
5461         struct s2io_nic *sp = (struct s2io_nic *) data;
5462         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5463         u64 val64 = 0;
5464         u16 subid;
5465
5466         subid = sp->pdev->subsystem_device;
5467         if ((sp->device_type == XFRAME_II_DEVICE) ||
5468                    ((subid & 0xFF) >= 0x07)) {
5469                 val64 = readq(&bar0->gpio_control);
5470                 val64 ^= GPIO_CTRL_GPIO_0;
5471                 writeq(val64, &bar0->gpio_control);
5472         } else {
5473                 val64 = readq(&bar0->adapter_control);
5474                 val64 ^= ADAPTER_LED_ON;
5475                 writeq(val64, &bar0->adapter_control);
5476         }
5477
5478         mod_timer(&sp->id_timer, jiffies + HZ / 2);
5479 }
5480
5481 /**
5482  * s2io_ethtool_idnic - To physically identify the nic on the system.
5483  * @sp : private member of the device structure, which is a pointer to the
5484  * s2io_nic structure.
5485  * @id : pointer to the structure with identification parameters given by
5486  * ethtool.
5487  * Description: Used to physically identify the NIC on the system.
5488  * The Link LED will blink for a time specified by the user for
5489  * identification.
5490  * NOTE: The Link has to be Up to be able to blink the LED. Hence
5491  * identification is possible only if it's link is up.
5492  * Return value:
5493  * int , returns 0 on success
5494  */
5495
5496 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5497 {
5498         u64 val64 = 0, last_gpio_ctrl_val;
5499         struct s2io_nic *sp = dev->priv;
5500         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5501         u16 subid;
5502
5503         subid = sp->pdev->subsystem_device;
5504         last_gpio_ctrl_val = readq(&bar0->gpio_control);
5505         if ((sp->device_type == XFRAME_I_DEVICE) &&
5506                 ((subid & 0xFF) < 0x07)) {
5507                 val64 = readq(&bar0->adapter_control);
5508                 if (!(val64 & ADAPTER_CNTL_EN)) {
5509                         printk(KERN_ERR
5510                                "Adapter Link down, cannot blink LED\n");
5511                         return -EFAULT;
5512                 }
5513         }
5514         if (sp->id_timer.function == NULL) {
5515                 init_timer(&sp->id_timer);
5516                 sp->id_timer.function = s2io_phy_id;
5517                 sp->id_timer.data = (unsigned long) sp;
5518         }
5519         mod_timer(&sp->id_timer, jiffies);
5520         if (data)
5521                 msleep_interruptible(data * HZ);
5522         else
5523                 msleep_interruptible(MAX_FLICKER_TIME);
5524         del_timer_sync(&sp->id_timer);
5525
5526         if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
5527                 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5528                 last_gpio_ctrl_val = readq(&bar0->gpio_control);