net: wireless: sd8797: Marvell sd8797 Wi-Fi driver
[linux-2.6.git] / drivers / net / s2io.c
1 /************************************************************************
2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3  * Copyright(c) 2002-2010 Exar Corp.
4  *
5  * This software may be used and distributed according to the terms of
6  * the GNU General Public License (GPL), incorporated herein by reference.
7  * Drivers based on or derived from this code fall under the GPL and must
8  * retain the authorship, copyright and license notice.  This file is not
9  * a complete program and may only be used when the entire operating
10  * system is licensed under the GPL.
11  * See the file COPYING in this distribution for more information.
12  *
13  * Credits:
14  * Jeff Garzik          : For pointing out the improper error condition
15  *                        check in the s2io_xmit routine and also some
16  *                        issues in the Tx watch dog function. Also for
17  *                        patiently answering all those innumerable
18  *                        questions regaring the 2.6 porting issues.
19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
20  *                        macros available only in 2.6 Kernel.
21  * Francois Romieu      : For pointing out all code part that were
22  *                        deprecated and also styling related comments.
23  * Grant Grundler       : For helping me get rid of some Architecture
24  *                        dependent code.
25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
26  *
27  * The module loadable parameters that are supported by the driver and a brief
28  * explanation of all the variables.
29  *
30  * rx_ring_num : This can be used to program the number of receive rings used
31  * in the driver.
32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
33  *     This is also an array of size 8.
34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35  *              values are 1, 2.
36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
38  * Tx descriptors that can be associated with each corresponding FIFO.
39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40  *     2(MSI_X). Default value is '2(MSI_X)'
41  * lro_max_pkts: This parameter defines maximum number of packets can be
42  *     aggregated as a single large packet
43  * napi: This parameter used to enable/disable NAPI (polling Rx)
44  *     Possible values '1' for enable and '0' for disable. Default is '1'
45  * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
46  *      Possible values '1' for enable and '0' for disable. Default is '0'
47  * vlan_tag_strip: This can be used to enable or disable vlan stripping.
48  *                 Possible values '1' for enable , '0' for disable.
49  *                 Default is '2' - which means disable in promisc mode
50  *                 and enable in non-promiscuous mode.
51  * multiq: This parameter used to enable/disable MULTIQUEUE support.
52  *      Possible values '1' for enable and '0' for disable. Default is '0'
53  ************************************************************************/
54
55 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
56
57 #include <linux/module.h>
58 #include <linux/types.h>
59 #include <linux/errno.h>
60 #include <linux/ioport.h>
61 #include <linux/pci.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/kernel.h>
64 #include <linux/netdevice.h>
65 #include <linux/etherdevice.h>
66 #include <linux/mdio.h>
67 #include <linux/skbuff.h>
68 #include <linux/init.h>
69 #include <linux/delay.h>
70 #include <linux/stddef.h>
71 #include <linux/ioctl.h>
72 #include <linux/timex.h>
73 #include <linux/ethtool.h>
74 #include <linux/workqueue.h>
75 #include <linux/if_vlan.h>
76 #include <linux/ip.h>
77 #include <linux/tcp.h>
78 #include <linux/uaccess.h>
79 #include <linux/io.h>
80 #include <linux/slab.h>
81 #include <linux/prefetch.h>
82 #include <net/tcp.h>
83
84 #include <asm/system.h>
85 #include <asm/div64.h>
86 #include <asm/irq.h>
87
88 /* local include */
89 #include "s2io.h"
90 #include "s2io-regs.h"
91
92 #define DRV_VERSION "2.0.26.28"
93
94 /* S2io Driver name & version. */
95 static const char s2io_driver_name[] = "Neterion";
96 static const char s2io_driver_version[] = DRV_VERSION;
97
98 static const int rxd_size[2] = {32, 48};
99 static const int rxd_count[2] = {127, 85};
100
101 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
102 {
103         int ret;
104
105         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
106                (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
107
108         return ret;
109 }
110
111 /*
112  * Cards with following subsystem_id have a link state indication
113  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
114  * macro below identifies these cards given the subsystem_id.
115  */
116 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid)              \
117         (dev_type == XFRAME_I_DEVICE) ?                                 \
118         ((((subid >= 0x600B) && (subid <= 0x600D)) ||                   \
119           ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
120
121 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
122                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
123
124 static inline int is_s2io_card_up(const struct s2io_nic *sp)
125 {
126         return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
127 }
128
129 /* Ethtool related variables and Macros. */
130 static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
131         "Register test\t(offline)",
132         "Eeprom test\t(offline)",
133         "Link test\t(online)",
134         "RLDRAM test\t(offline)",
135         "BIST Test\t(offline)"
136 };
137
138 static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
139         {"tmac_frms"},
140         {"tmac_data_octets"},
141         {"tmac_drop_frms"},
142         {"tmac_mcst_frms"},
143         {"tmac_bcst_frms"},
144         {"tmac_pause_ctrl_frms"},
145         {"tmac_ttl_octets"},
146         {"tmac_ucst_frms"},
147         {"tmac_nucst_frms"},
148         {"tmac_any_err_frms"},
149         {"tmac_ttl_less_fb_octets"},
150         {"tmac_vld_ip_octets"},
151         {"tmac_vld_ip"},
152         {"tmac_drop_ip"},
153         {"tmac_icmp"},
154         {"tmac_rst_tcp"},
155         {"tmac_tcp"},
156         {"tmac_udp"},
157         {"rmac_vld_frms"},
158         {"rmac_data_octets"},
159         {"rmac_fcs_err_frms"},
160         {"rmac_drop_frms"},
161         {"rmac_vld_mcst_frms"},
162         {"rmac_vld_bcst_frms"},
163         {"rmac_in_rng_len_err_frms"},
164         {"rmac_out_rng_len_err_frms"},
165         {"rmac_long_frms"},
166         {"rmac_pause_ctrl_frms"},
167         {"rmac_unsup_ctrl_frms"},
168         {"rmac_ttl_octets"},
169         {"rmac_accepted_ucst_frms"},
170         {"rmac_accepted_nucst_frms"},
171         {"rmac_discarded_frms"},
172         {"rmac_drop_events"},
173         {"rmac_ttl_less_fb_octets"},
174         {"rmac_ttl_frms"},
175         {"rmac_usized_frms"},
176         {"rmac_osized_frms"},
177         {"rmac_frag_frms"},
178         {"rmac_jabber_frms"},
179         {"rmac_ttl_64_frms"},
180         {"rmac_ttl_65_127_frms"},
181         {"rmac_ttl_128_255_frms"},
182         {"rmac_ttl_256_511_frms"},
183         {"rmac_ttl_512_1023_frms"},
184         {"rmac_ttl_1024_1518_frms"},
185         {"rmac_ip"},
186         {"rmac_ip_octets"},
187         {"rmac_hdr_err_ip"},
188         {"rmac_drop_ip"},
189         {"rmac_icmp"},
190         {"rmac_tcp"},
191         {"rmac_udp"},
192         {"rmac_err_drp_udp"},
193         {"rmac_xgmii_err_sym"},
194         {"rmac_frms_q0"},
195         {"rmac_frms_q1"},
196         {"rmac_frms_q2"},
197         {"rmac_frms_q3"},
198         {"rmac_frms_q4"},
199         {"rmac_frms_q5"},
200         {"rmac_frms_q6"},
201         {"rmac_frms_q7"},
202         {"rmac_full_q0"},
203         {"rmac_full_q1"},
204         {"rmac_full_q2"},
205         {"rmac_full_q3"},
206         {"rmac_full_q4"},
207         {"rmac_full_q5"},
208         {"rmac_full_q6"},
209         {"rmac_full_q7"},
210         {"rmac_pause_cnt"},
211         {"rmac_xgmii_data_err_cnt"},
212         {"rmac_xgmii_ctrl_err_cnt"},
213         {"rmac_accepted_ip"},
214         {"rmac_err_tcp"},
215         {"rd_req_cnt"},
216         {"new_rd_req_cnt"},
217         {"new_rd_req_rtry_cnt"},
218         {"rd_rtry_cnt"},
219         {"wr_rtry_rd_ack_cnt"},
220         {"wr_req_cnt"},
221         {"new_wr_req_cnt"},
222         {"new_wr_req_rtry_cnt"},
223         {"wr_rtry_cnt"},
224         {"wr_disc_cnt"},
225         {"rd_rtry_wr_ack_cnt"},
226         {"txp_wr_cnt"},
227         {"txd_rd_cnt"},
228         {"txd_wr_cnt"},
229         {"rxd_rd_cnt"},
230         {"rxd_wr_cnt"},
231         {"txf_rd_cnt"},
232         {"rxf_wr_cnt"}
233 };
234
235 static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
236         {"rmac_ttl_1519_4095_frms"},
237         {"rmac_ttl_4096_8191_frms"},
238         {"rmac_ttl_8192_max_frms"},
239         {"rmac_ttl_gt_max_frms"},
240         {"rmac_osized_alt_frms"},
241         {"rmac_jabber_alt_frms"},
242         {"rmac_gt_max_alt_frms"},
243         {"rmac_vlan_frms"},
244         {"rmac_len_discard"},
245         {"rmac_fcs_discard"},
246         {"rmac_pf_discard"},
247         {"rmac_da_discard"},
248         {"rmac_red_discard"},
249         {"rmac_rts_discard"},
250         {"rmac_ingm_full_discard"},
251         {"link_fault_cnt"}
252 };
253
254 static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
255         {"\n DRIVER STATISTICS"},
256         {"single_bit_ecc_errs"},
257         {"double_bit_ecc_errs"},
258         {"parity_err_cnt"},
259         {"serious_err_cnt"},
260         {"soft_reset_cnt"},
261         {"fifo_full_cnt"},
262         {"ring_0_full_cnt"},
263         {"ring_1_full_cnt"},
264         {"ring_2_full_cnt"},
265         {"ring_3_full_cnt"},
266         {"ring_4_full_cnt"},
267         {"ring_5_full_cnt"},
268         {"ring_6_full_cnt"},
269         {"ring_7_full_cnt"},
270         {"alarm_transceiver_temp_high"},
271         {"alarm_transceiver_temp_low"},
272         {"alarm_laser_bias_current_high"},
273         {"alarm_laser_bias_current_low"},
274         {"alarm_laser_output_power_high"},
275         {"alarm_laser_output_power_low"},
276         {"warn_transceiver_temp_high"},
277         {"warn_transceiver_temp_low"},
278         {"warn_laser_bias_current_high"},
279         {"warn_laser_bias_current_low"},
280         {"warn_laser_output_power_high"},
281         {"warn_laser_output_power_low"},
282         {"lro_aggregated_pkts"},
283         {"lro_flush_both_count"},
284         {"lro_out_of_sequence_pkts"},
285         {"lro_flush_due_to_max_pkts"},
286         {"lro_avg_aggr_pkts"},
287         {"mem_alloc_fail_cnt"},
288         {"pci_map_fail_cnt"},
289         {"watchdog_timer_cnt"},
290         {"mem_allocated"},
291         {"mem_freed"},
292         {"link_up_cnt"},
293         {"link_down_cnt"},
294         {"link_up_time"},
295         {"link_down_time"},
296         {"tx_tcode_buf_abort_cnt"},
297         {"tx_tcode_desc_abort_cnt"},
298         {"tx_tcode_parity_err_cnt"},
299         {"tx_tcode_link_loss_cnt"},
300         {"tx_tcode_list_proc_err_cnt"},
301         {"rx_tcode_parity_err_cnt"},
302         {"rx_tcode_abort_cnt"},
303         {"rx_tcode_parity_abort_cnt"},
304         {"rx_tcode_rda_fail_cnt"},
305         {"rx_tcode_unkn_prot_cnt"},
306         {"rx_tcode_fcs_err_cnt"},
307         {"rx_tcode_buf_size_err_cnt"},
308         {"rx_tcode_rxd_corrupt_cnt"},
309         {"rx_tcode_unkn_err_cnt"},
310         {"tda_err_cnt"},
311         {"pfc_err_cnt"},
312         {"pcc_err_cnt"},
313         {"tti_err_cnt"},
314         {"tpa_err_cnt"},
315         {"sm_err_cnt"},
316         {"lso_err_cnt"},
317         {"mac_tmac_err_cnt"},
318         {"mac_rmac_err_cnt"},
319         {"xgxs_txgxs_err_cnt"},
320         {"xgxs_rxgxs_err_cnt"},
321         {"rc_err_cnt"},
322         {"prc_pcix_err_cnt"},
323         {"rpa_err_cnt"},
324         {"rda_err_cnt"},
325         {"rti_err_cnt"},
326         {"mc_err_cnt"}
327 };
328
329 #define S2IO_XENA_STAT_LEN      ARRAY_SIZE(ethtool_xena_stats_keys)
330 #define S2IO_ENHANCED_STAT_LEN  ARRAY_SIZE(ethtool_enhanced_stats_keys)
331 #define S2IO_DRIVER_STAT_LEN    ARRAY_SIZE(ethtool_driver_stats_keys)
332
333 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
334 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
335
336 #define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
337 #define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
338
339 #define S2IO_TEST_LEN   ARRAY_SIZE(s2io_gstrings)
340 #define S2IO_STRINGS_LEN        (S2IO_TEST_LEN * ETH_GSTRING_LEN)
341
342 #define S2IO_TIMER_CONF(timer, handle, arg, exp)        \
343         init_timer(&timer);                             \
344         timer.function = handle;                        \
345         timer.data = (unsigned long)arg;                \
346         mod_timer(&timer, (jiffies + exp))              \
347
348 /* copy mac addr to def_mac_addr array */
349 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
350 {
351         sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
352         sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
353         sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
354         sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
355         sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
356         sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
357 }
358
359 /*
360  * Constants to be programmed into the Xena's registers, to configure
361  * the XAUI.
362  */
363
364 #define END_SIGN        0x0
365 static const u64 herc_act_dtx_cfg[] = {
366         /* Set address */
367         0x8000051536750000ULL, 0x80000515367500E0ULL,
368         /* Write data */
369         0x8000051536750004ULL, 0x80000515367500E4ULL,
370         /* Set address */
371         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
372         /* Write data */
373         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
374         /* Set address */
375         0x801205150D440000ULL, 0x801205150D4400E0ULL,
376         /* Write data */
377         0x801205150D440004ULL, 0x801205150D4400E4ULL,
378         /* Set address */
379         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
380         /* Write data */
381         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
382         /* Done */
383         END_SIGN
384 };
385
386 static const u64 xena_dtx_cfg[] = {
387         /* Set address */
388         0x8000051500000000ULL, 0x80000515000000E0ULL,
389         /* Write data */
390         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
391         /* Set address */
392         0x8001051500000000ULL, 0x80010515000000E0ULL,
393         /* Write data */
394         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
395         /* Set address */
396         0x8002051500000000ULL, 0x80020515000000E0ULL,
397         /* Write data */
398         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
399         END_SIGN
400 };
401
402 /*
403  * Constants for Fixing the MacAddress problem seen mostly on
404  * Alpha machines.
405  */
406 static const u64 fix_mac[] = {
407         0x0060000000000000ULL, 0x0060600000000000ULL,
408         0x0040600000000000ULL, 0x0000600000000000ULL,
409         0x0020600000000000ULL, 0x0060600000000000ULL,
410         0x0020600000000000ULL, 0x0060600000000000ULL,
411         0x0020600000000000ULL, 0x0060600000000000ULL,
412         0x0020600000000000ULL, 0x0060600000000000ULL,
413         0x0020600000000000ULL, 0x0060600000000000ULL,
414         0x0020600000000000ULL, 0x0060600000000000ULL,
415         0x0020600000000000ULL, 0x0060600000000000ULL,
416         0x0020600000000000ULL, 0x0060600000000000ULL,
417         0x0020600000000000ULL, 0x0060600000000000ULL,
418         0x0020600000000000ULL, 0x0060600000000000ULL,
419         0x0020600000000000ULL, 0x0000600000000000ULL,
420         0x0040600000000000ULL, 0x0060600000000000ULL,
421         END_SIGN
422 };
423
424 MODULE_LICENSE("GPL");
425 MODULE_VERSION(DRV_VERSION);
426
427
428 /* Module Loadable parameters. */
429 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
430 S2IO_PARM_INT(rx_ring_num, 1);
431 S2IO_PARM_INT(multiq, 0);
432 S2IO_PARM_INT(rx_ring_mode, 1);
433 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
434 S2IO_PARM_INT(rmac_pause_time, 0x100);
435 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
436 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
437 S2IO_PARM_INT(shared_splits, 0);
438 S2IO_PARM_INT(tmac_util_period, 5);
439 S2IO_PARM_INT(rmac_util_period, 5);
440 S2IO_PARM_INT(l3l4hdr_size, 128);
441 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
442 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
443 /* Frequency of Rx desc syncs expressed as power of 2 */
444 S2IO_PARM_INT(rxsync_frequency, 3);
445 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
446 S2IO_PARM_INT(intr_type, 2);
447 /* Large receive offload feature */
448
449 /* Max pkts to be aggregated by LRO at one time. If not specified,
450  * aggregation happens until we hit max IP pkt size(64K)
451  */
452 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
453 S2IO_PARM_INT(indicate_max_pkts, 0);
454
455 S2IO_PARM_INT(napi, 1);
456 S2IO_PARM_INT(ufo, 0);
457 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
458
459 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
460 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
461 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
462 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
463 static unsigned int rts_frm_len[MAX_RX_RINGS] =
464 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
465
466 module_param_array(tx_fifo_len, uint, NULL, 0);
467 module_param_array(rx_ring_sz, uint, NULL, 0);
468 module_param_array(rts_frm_len, uint, NULL, 0);
469
470 /*
471  * S2IO device table.
472  * This table lists all the devices that this driver supports.
473  */
474 static DEFINE_PCI_DEVICE_TABLE(s2io_tbl) = {
475         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
476          PCI_ANY_ID, PCI_ANY_ID},
477         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
478          PCI_ANY_ID, PCI_ANY_ID},
479         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
480          PCI_ANY_ID, PCI_ANY_ID},
481         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
482          PCI_ANY_ID, PCI_ANY_ID},
483         {0,}
484 };
485
486 MODULE_DEVICE_TABLE(pci, s2io_tbl);
487
488 static struct pci_error_handlers s2io_err_handler = {
489         .error_detected = s2io_io_error_detected,
490         .slot_reset = s2io_io_slot_reset,
491         .resume = s2io_io_resume,
492 };
493
494 static struct pci_driver s2io_driver = {
495         .name = "S2IO",
496         .id_table = s2io_tbl,
497         .probe = s2io_init_nic,
498         .remove = __devexit_p(s2io_rem_nic),
499         .err_handler = &s2io_err_handler,
500 };
501
502 /* A simplifier macro used both by init and free shared_mem Fns(). */
503 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
504
505 /* netqueue manipulation helper functions */
506 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
507 {
508         if (!sp->config.multiq) {
509                 int i;
510
511                 for (i = 0; i < sp->config.tx_fifo_num; i++)
512                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
513         }
514         netif_tx_stop_all_queues(sp->dev);
515 }
516
517 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
518 {
519         if (!sp->config.multiq)
520                 sp->mac_control.fifos[fifo_no].queue_state =
521                         FIFO_QUEUE_STOP;
522
523         netif_tx_stop_all_queues(sp->dev);
524 }
525
526 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
527 {
528         if (!sp->config.multiq) {
529                 int i;
530
531                 for (i = 0; i < sp->config.tx_fifo_num; i++)
532                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
533         }
534         netif_tx_start_all_queues(sp->dev);
535 }
536
537 static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
538 {
539         if (!sp->config.multiq)
540                 sp->mac_control.fifos[fifo_no].queue_state =
541                         FIFO_QUEUE_START;
542
543         netif_tx_start_all_queues(sp->dev);
544 }
545
546 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
547 {
548         if (!sp->config.multiq) {
549                 int i;
550
551                 for (i = 0; i < sp->config.tx_fifo_num; i++)
552                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
553         }
554         netif_tx_wake_all_queues(sp->dev);
555 }
556
557 static inline void s2io_wake_tx_queue(
558         struct fifo_info *fifo, int cnt, u8 multiq)
559 {
560
561         if (multiq) {
562                 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
563                         netif_wake_subqueue(fifo->dev, fifo->fifo_no);
564         } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
565                 if (netif_queue_stopped(fifo->dev)) {
566                         fifo->queue_state = FIFO_QUEUE_START;
567                         netif_wake_queue(fifo->dev);
568                 }
569         }
570 }
571
572 /**
573  * init_shared_mem - Allocation and Initialization of Memory
574  * @nic: Device private variable.
575  * Description: The function allocates all the memory areas shared
576  * between the NIC and the driver. This includes Tx descriptors,
577  * Rx descriptors and the statistics block.
578  */
579
580 static int init_shared_mem(struct s2io_nic *nic)
581 {
582         u32 size;
583         void *tmp_v_addr, *tmp_v_addr_next;
584         dma_addr_t tmp_p_addr, tmp_p_addr_next;
585         struct RxD_block *pre_rxd_blk = NULL;
586         int i, j, blk_cnt;
587         int lst_size, lst_per_page;
588         struct net_device *dev = nic->dev;
589         unsigned long tmp;
590         struct buffAdd *ba;
591         struct config_param *config = &nic->config;
592         struct mac_info *mac_control = &nic->mac_control;
593         unsigned long long mem_allocated = 0;
594
595         /* Allocation and initialization of TXDLs in FIFOs */
596         size = 0;
597         for (i = 0; i < config->tx_fifo_num; i++) {
598                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
599
600                 size += tx_cfg->fifo_len;
601         }
602         if (size > MAX_AVAILABLE_TXDS) {
603                 DBG_PRINT(ERR_DBG,
604                           "Too many TxDs requested: %d, max supported: %d\n",
605                           size, MAX_AVAILABLE_TXDS);
606                 return -EINVAL;
607         }
608
609         size = 0;
610         for (i = 0; i < config->tx_fifo_num; i++) {
611                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
612
613                 size = tx_cfg->fifo_len;
614                 /*
615                  * Legal values are from 2 to 8192
616                  */
617                 if (size < 2) {
618                         DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
619                                   "Valid lengths are 2 through 8192\n",
620                                   i, size);
621                         return -EINVAL;
622                 }
623         }
624
625         lst_size = (sizeof(struct TxD) * config->max_txds);
626         lst_per_page = PAGE_SIZE / lst_size;
627
628         for (i = 0; i < config->tx_fifo_num; i++) {
629                 struct fifo_info *fifo = &mac_control->fifos[i];
630                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
631                 int fifo_len = tx_cfg->fifo_len;
632                 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
633
634                 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
635                 if (!fifo->list_info) {
636                         DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
637                         return -ENOMEM;
638                 }
639                 mem_allocated += list_holder_size;
640         }
641         for (i = 0; i < config->tx_fifo_num; i++) {
642                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
643                                                 lst_per_page);
644                 struct fifo_info *fifo = &mac_control->fifos[i];
645                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
646
647                 fifo->tx_curr_put_info.offset = 0;
648                 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
649                 fifo->tx_curr_get_info.offset = 0;
650                 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
651                 fifo->fifo_no = i;
652                 fifo->nic = nic;
653                 fifo->max_txds = MAX_SKB_FRAGS + 2;
654                 fifo->dev = dev;
655
656                 for (j = 0; j < page_num; j++) {
657                         int k = 0;
658                         dma_addr_t tmp_p;
659                         void *tmp_v;
660                         tmp_v = pci_alloc_consistent(nic->pdev,
661                                                      PAGE_SIZE, &tmp_p);
662                         if (!tmp_v) {
663                                 DBG_PRINT(INFO_DBG,
664                                           "pci_alloc_consistent failed for TxDL\n");
665                                 return -ENOMEM;
666                         }
667                         /* If we got a zero DMA address(can happen on
668                          * certain platforms like PPC), reallocate.
669                          * Store virtual address of page we don't want,
670                          * to be freed later.
671                          */
672                         if (!tmp_p) {
673                                 mac_control->zerodma_virt_addr = tmp_v;
674                                 DBG_PRINT(INIT_DBG,
675                                           "%s: Zero DMA address for TxDL. "
676                                           "Virtual address %p\n",
677                                           dev->name, tmp_v);
678                                 tmp_v = pci_alloc_consistent(nic->pdev,
679                                                              PAGE_SIZE, &tmp_p);
680                                 if (!tmp_v) {
681                                         DBG_PRINT(INFO_DBG,
682                                                   "pci_alloc_consistent failed for TxDL\n");
683                                         return -ENOMEM;
684                                 }
685                                 mem_allocated += PAGE_SIZE;
686                         }
687                         while (k < lst_per_page) {
688                                 int l = (j * lst_per_page) + k;
689                                 if (l == tx_cfg->fifo_len)
690                                         break;
691                                 fifo->list_info[l].list_virt_addr =
692                                         tmp_v + (k * lst_size);
693                                 fifo->list_info[l].list_phy_addr =
694                                         tmp_p + (k * lst_size);
695                                 k++;
696                         }
697                 }
698         }
699
700         for (i = 0; i < config->tx_fifo_num; i++) {
701                 struct fifo_info *fifo = &mac_control->fifos[i];
702                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
703
704                 size = tx_cfg->fifo_len;
705                 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
706                 if (!fifo->ufo_in_band_v)
707                         return -ENOMEM;
708                 mem_allocated += (size * sizeof(u64));
709         }
710
711         /* Allocation and initialization of RXDs in Rings */
712         size = 0;
713         for (i = 0; i < config->rx_ring_num; i++) {
714                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
715                 struct ring_info *ring = &mac_control->rings[i];
716
717                 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
718                         DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
719                                   "multiple of RxDs per Block\n",
720                                   dev->name, i);
721                         return FAILURE;
722                 }
723                 size += rx_cfg->num_rxd;
724                 ring->block_count = rx_cfg->num_rxd /
725                         (rxd_count[nic->rxd_mode] + 1);
726                 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
727         }
728         if (nic->rxd_mode == RXD_MODE_1)
729                 size = (size * (sizeof(struct RxD1)));
730         else
731                 size = (size * (sizeof(struct RxD3)));
732
733         for (i = 0; i < config->rx_ring_num; i++) {
734                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
735                 struct ring_info *ring = &mac_control->rings[i];
736
737                 ring->rx_curr_get_info.block_index = 0;
738                 ring->rx_curr_get_info.offset = 0;
739                 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
740                 ring->rx_curr_put_info.block_index = 0;
741                 ring->rx_curr_put_info.offset = 0;
742                 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
743                 ring->nic = nic;
744                 ring->ring_no = i;
745
746                 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
747                 /*  Allocating all the Rx blocks */
748                 for (j = 0; j < blk_cnt; j++) {
749                         struct rx_block_info *rx_blocks;
750                         int l;
751
752                         rx_blocks = &ring->rx_blocks[j];
753                         size = SIZE_OF_BLOCK;   /* size is always page size */
754                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
755                                                           &tmp_p_addr);
756                         if (tmp_v_addr == NULL) {
757                                 /*
758                                  * In case of failure, free_shared_mem()
759                                  * is called, which should free any
760                                  * memory that was alloced till the
761                                  * failure happened.
762                                  */
763                                 rx_blocks->block_virt_addr = tmp_v_addr;
764                                 return -ENOMEM;
765                         }
766                         mem_allocated += size;
767                         memset(tmp_v_addr, 0, size);
768
769                         size = sizeof(struct rxd_info) *
770                                 rxd_count[nic->rxd_mode];
771                         rx_blocks->block_virt_addr = tmp_v_addr;
772                         rx_blocks->block_dma_addr = tmp_p_addr;
773                         rx_blocks->rxds = kmalloc(size,  GFP_KERNEL);
774                         if (!rx_blocks->rxds)
775                                 return -ENOMEM;
776                         mem_allocated += size;
777                         for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
778                                 rx_blocks->rxds[l].virt_addr =
779                                         rx_blocks->block_virt_addr +
780                                         (rxd_size[nic->rxd_mode] * l);
781                                 rx_blocks->rxds[l].dma_addr =
782                                         rx_blocks->block_dma_addr +
783                                         (rxd_size[nic->rxd_mode] * l);
784                         }
785                 }
786                 /* Interlinking all Rx Blocks */
787                 for (j = 0; j < blk_cnt; j++) {
788                         int next = (j + 1) % blk_cnt;
789                         tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
790                         tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
791                         tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
792                         tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
793
794                         pre_rxd_blk = tmp_v_addr;
795                         pre_rxd_blk->reserved_2_pNext_RxD_block =
796                                 (unsigned long)tmp_v_addr_next;
797                         pre_rxd_blk->pNext_RxD_Blk_physical =
798                                 (u64)tmp_p_addr_next;
799                 }
800         }
801         if (nic->rxd_mode == RXD_MODE_3B) {
802                 /*
803                  * Allocation of Storages for buffer addresses in 2BUFF mode
804                  * and the buffers as well.
805                  */
806                 for (i = 0; i < config->rx_ring_num; i++) {
807                         struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
808                         struct ring_info *ring = &mac_control->rings[i];
809
810                         blk_cnt = rx_cfg->num_rxd /
811                                 (rxd_count[nic->rxd_mode] + 1);
812                         size = sizeof(struct buffAdd *) * blk_cnt;
813                         ring->ba = kmalloc(size, GFP_KERNEL);
814                         if (!ring->ba)
815                                 return -ENOMEM;
816                         mem_allocated += size;
817                         for (j = 0; j < blk_cnt; j++) {
818                                 int k = 0;
819
820                                 size = sizeof(struct buffAdd) *
821                                         (rxd_count[nic->rxd_mode] + 1);
822                                 ring->ba[j] = kmalloc(size, GFP_KERNEL);
823                                 if (!ring->ba[j])
824                                         return -ENOMEM;
825                                 mem_allocated += size;
826                                 while (k != rxd_count[nic->rxd_mode]) {
827                                         ba = &ring->ba[j][k];
828                                         size = BUF0_LEN + ALIGN_SIZE;
829                                         ba->ba_0_org = kmalloc(size, GFP_KERNEL);
830                                         if (!ba->ba_0_org)
831                                                 return -ENOMEM;
832                                         mem_allocated += size;
833                                         tmp = (unsigned long)ba->ba_0_org;
834                                         tmp += ALIGN_SIZE;
835                                         tmp &= ~((unsigned long)ALIGN_SIZE);
836                                         ba->ba_0 = (void *)tmp;
837
838                                         size = BUF1_LEN + ALIGN_SIZE;
839                                         ba->ba_1_org = kmalloc(size, GFP_KERNEL);
840                                         if (!ba->ba_1_org)
841                                                 return -ENOMEM;
842                                         mem_allocated += size;
843                                         tmp = (unsigned long)ba->ba_1_org;
844                                         tmp += ALIGN_SIZE;
845                                         tmp &= ~((unsigned long)ALIGN_SIZE);
846                                         ba->ba_1 = (void *)tmp;
847                                         k++;
848                                 }
849                         }
850                 }
851         }
852
853         /* Allocation and initialization of Statistics block */
854         size = sizeof(struct stat_block);
855         mac_control->stats_mem =
856                 pci_alloc_consistent(nic->pdev, size,
857                                      &mac_control->stats_mem_phy);
858
859         if (!mac_control->stats_mem) {
860                 /*
861                  * In case of failure, free_shared_mem() is called, which
862                  * should free any memory that was alloced till the
863                  * failure happened.
864                  */
865                 return -ENOMEM;
866         }
867         mem_allocated += size;
868         mac_control->stats_mem_sz = size;
869
870         tmp_v_addr = mac_control->stats_mem;
871         mac_control->stats_info = tmp_v_addr;
872         memset(tmp_v_addr, 0, size);
873         DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n",
874                 dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr);
875         mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
876         return SUCCESS;
877 }
878
879 /**
880  * free_shared_mem - Free the allocated Memory
881  * @nic:  Device private variable.
882  * Description: This function is to free all memory locations allocated by
883  * the init_shared_mem() function and return it to the kernel.
884  */
885
886 static void free_shared_mem(struct s2io_nic *nic)
887 {
888         int i, j, blk_cnt, size;
889         void *tmp_v_addr;
890         dma_addr_t tmp_p_addr;
891         int lst_size, lst_per_page;
892         struct net_device *dev;
893         int page_num = 0;
894         struct config_param *config;
895         struct mac_info *mac_control;
896         struct stat_block *stats;
897         struct swStat *swstats;
898
899         if (!nic)
900                 return;
901
902         dev = nic->dev;
903
904         config = &nic->config;
905         mac_control = &nic->mac_control;
906         stats = mac_control->stats_info;
907         swstats = &stats->sw_stat;
908
909         lst_size = sizeof(struct TxD) * config->max_txds;
910         lst_per_page = PAGE_SIZE / lst_size;
911
912         for (i = 0; i < config->tx_fifo_num; i++) {
913                 struct fifo_info *fifo = &mac_control->fifos[i];
914                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
915
916                 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
917                 for (j = 0; j < page_num; j++) {
918                         int mem_blks = (j * lst_per_page);
919                         struct list_info_hold *fli;
920
921                         if (!fifo->list_info)
922                                 return;
923
924                         fli = &fifo->list_info[mem_blks];
925                         if (!fli->list_virt_addr)
926                                 break;
927                         pci_free_consistent(nic->pdev, PAGE_SIZE,
928                                             fli->list_virt_addr,
929                                             fli->list_phy_addr);
930                         swstats->mem_freed += PAGE_SIZE;
931                 }
932                 /* If we got a zero DMA address during allocation,
933                  * free the page now
934                  */
935                 if (mac_control->zerodma_virt_addr) {
936                         pci_free_consistent(nic->pdev, PAGE_SIZE,
937                                             mac_control->zerodma_virt_addr,
938                                             (dma_addr_t)0);
939                         DBG_PRINT(INIT_DBG,
940                                   "%s: Freeing TxDL with zero DMA address. "
941                                   "Virtual address %p\n",
942                                   dev->name, mac_control->zerodma_virt_addr);
943                         swstats->mem_freed += PAGE_SIZE;
944                 }
945                 kfree(fifo->list_info);
946                 swstats->mem_freed += tx_cfg->fifo_len *
947                         sizeof(struct list_info_hold);
948         }
949
950         size = SIZE_OF_BLOCK;
951         for (i = 0; i < config->rx_ring_num; i++) {
952                 struct ring_info *ring = &mac_control->rings[i];
953
954                 blk_cnt = ring->block_count;
955                 for (j = 0; j < blk_cnt; j++) {
956                         tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
957                         tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
958                         if (tmp_v_addr == NULL)
959                                 break;
960                         pci_free_consistent(nic->pdev, size,
961                                             tmp_v_addr, tmp_p_addr);
962                         swstats->mem_freed += size;
963                         kfree(ring->rx_blocks[j].rxds);
964                         swstats->mem_freed += sizeof(struct rxd_info) *
965                                 rxd_count[nic->rxd_mode];
966                 }
967         }
968
969         if (nic->rxd_mode == RXD_MODE_3B) {
970                 /* Freeing buffer storage addresses in 2BUFF mode. */
971                 for (i = 0; i < config->rx_ring_num; i++) {
972                         struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
973                         struct ring_info *ring = &mac_control->rings[i];
974
975                         blk_cnt = rx_cfg->num_rxd /
976                                 (rxd_count[nic->rxd_mode] + 1);
977                         for (j = 0; j < blk_cnt; j++) {
978                                 int k = 0;
979                                 if (!ring->ba[j])
980                                         continue;
981                                 while (k != rxd_count[nic->rxd_mode]) {
982                                         struct buffAdd *ba = &ring->ba[j][k];
983                                         kfree(ba->ba_0_org);
984                                         swstats->mem_freed +=
985                                                 BUF0_LEN + ALIGN_SIZE;
986                                         kfree(ba->ba_1_org);
987                                         swstats->mem_freed +=
988                                                 BUF1_LEN + ALIGN_SIZE;
989                                         k++;
990                                 }
991                                 kfree(ring->ba[j]);
992                                 swstats->mem_freed += sizeof(struct buffAdd) *
993                                         (rxd_count[nic->rxd_mode] + 1);
994                         }
995                         kfree(ring->ba);
996                         swstats->mem_freed += sizeof(struct buffAdd *) *
997                                 blk_cnt;
998                 }
999         }
1000
1001         for (i = 0; i < nic->config.tx_fifo_num; i++) {
1002                 struct fifo_info *fifo = &mac_control->fifos[i];
1003                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1004
1005                 if (fifo->ufo_in_band_v) {
1006                         swstats->mem_freed += tx_cfg->fifo_len *
1007                                 sizeof(u64);
1008                         kfree(fifo->ufo_in_band_v);
1009                 }
1010         }
1011
1012         if (mac_control->stats_mem) {
1013                 swstats->mem_freed += mac_control->stats_mem_sz;
1014                 pci_free_consistent(nic->pdev,
1015                                     mac_control->stats_mem_sz,
1016                                     mac_control->stats_mem,
1017                                     mac_control->stats_mem_phy);
1018         }
1019 }
1020
1021 /**
1022  * s2io_verify_pci_mode -
1023  */
1024
1025 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1026 {
1027         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1028         register u64 val64 = 0;
1029         int     mode;
1030
1031         val64 = readq(&bar0->pci_mode);
1032         mode = (u8)GET_PCI_MODE(val64);
1033
1034         if (val64 & PCI_MODE_UNKNOWN_MODE)
1035                 return -1;      /* Unknown PCI mode */
1036         return mode;
1037 }
1038
1039 #define NEC_VENID   0x1033
1040 #define NEC_DEVID   0x0125
1041 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1042 {
1043         struct pci_dev *tdev = NULL;
1044         while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1045                 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1046                         if (tdev->bus == s2io_pdev->bus->parent) {
1047                                 pci_dev_put(tdev);
1048                                 return 1;
1049                         }
1050                 }
1051         }
1052         return 0;
1053 }
1054
1055 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1056 /**
1057  * s2io_print_pci_mode -
1058  */
1059 static int s2io_print_pci_mode(struct s2io_nic *nic)
1060 {
1061         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1062         register u64 val64 = 0;
1063         int     mode;
1064         struct config_param *config = &nic->config;
1065         const char *pcimode;
1066
1067         val64 = readq(&bar0->pci_mode);
1068         mode = (u8)GET_PCI_MODE(val64);
1069
1070         if (val64 & PCI_MODE_UNKNOWN_MODE)
1071                 return -1;      /* Unknown PCI mode */
1072
1073         config->bus_speed = bus_speed[mode];
1074
1075         if (s2io_on_nec_bridge(nic->pdev)) {
1076                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1077                           nic->dev->name);
1078                 return mode;
1079         }
1080
1081         switch (mode) {
1082         case PCI_MODE_PCI_33:
1083                 pcimode = "33MHz PCI bus";
1084                 break;
1085         case PCI_MODE_PCI_66:
1086                 pcimode = "66MHz PCI bus";
1087                 break;
1088         case PCI_MODE_PCIX_M1_66:
1089                 pcimode = "66MHz PCIX(M1) bus";
1090                 break;
1091         case PCI_MODE_PCIX_M1_100:
1092                 pcimode = "100MHz PCIX(M1) bus";
1093                 break;
1094         case PCI_MODE_PCIX_M1_133:
1095                 pcimode = "133MHz PCIX(M1) bus";
1096                 break;
1097         case PCI_MODE_PCIX_M2_66:
1098                 pcimode = "133MHz PCIX(M2) bus";
1099                 break;
1100         case PCI_MODE_PCIX_M2_100:
1101                 pcimode = "200MHz PCIX(M2) bus";
1102                 break;
1103         case PCI_MODE_PCIX_M2_133:
1104                 pcimode = "266MHz PCIX(M2) bus";
1105                 break;
1106         default:
1107                 pcimode = "unsupported bus!";
1108                 mode = -1;
1109         }
1110
1111         DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1112                   nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1113
1114         return mode;
1115 }
1116
1117 /**
1118  *  init_tti - Initialization transmit traffic interrupt scheme
1119  *  @nic: device private variable
1120  *  @link: link status (UP/DOWN) used to enable/disable continuous
1121  *  transmit interrupts
1122  *  Description: The function configures transmit traffic interrupts
1123  *  Return Value:  SUCCESS on success and
1124  *  '-1' on failure
1125  */
1126
1127 static int init_tti(struct s2io_nic *nic, int link)
1128 {
1129         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1130         register u64 val64 = 0;
1131         int i;
1132         struct config_param *config = &nic->config;
1133
1134         for (i = 0; i < config->tx_fifo_num; i++) {
1135                 /*
1136                  * TTI Initialization. Default Tx timer gets us about
1137                  * 250 interrupts per sec. Continuous interrupts are enabled
1138                  * by default.
1139                  */
1140                 if (nic->device_type == XFRAME_II_DEVICE) {
1141                         int count = (nic->config.bus_speed * 125)/2;
1142                         val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1143                 } else
1144                         val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1145
1146                 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1147                         TTI_DATA1_MEM_TX_URNG_B(0x10) |
1148                         TTI_DATA1_MEM_TX_URNG_C(0x30) |
1149                         TTI_DATA1_MEM_TX_TIMER_AC_EN;
1150                 if (i == 0)
1151                         if (use_continuous_tx_intrs && (link == LINK_UP))
1152                                 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1153                 writeq(val64, &bar0->tti_data1_mem);
1154
1155                 if (nic->config.intr_type == MSI_X) {
1156                         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1157                                 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1158                                 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1159                                 TTI_DATA2_MEM_TX_UFC_D(0x300);
1160                 } else {
1161                         if ((nic->config.tx_steering_type ==
1162                              TX_DEFAULT_STEERING) &&
1163                             (config->tx_fifo_num > 1) &&
1164                             (i >= nic->udp_fifo_idx) &&
1165                             (i < (nic->udp_fifo_idx +
1166                                   nic->total_udp_fifos)))
1167                                 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1168                                         TTI_DATA2_MEM_TX_UFC_B(0x80) |
1169                                         TTI_DATA2_MEM_TX_UFC_C(0x100) |
1170                                         TTI_DATA2_MEM_TX_UFC_D(0x120);
1171                         else
1172                                 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1173                                         TTI_DATA2_MEM_TX_UFC_B(0x20) |
1174                                         TTI_DATA2_MEM_TX_UFC_C(0x40) |
1175                                         TTI_DATA2_MEM_TX_UFC_D(0x80);
1176                 }
1177
1178                 writeq(val64, &bar0->tti_data2_mem);
1179
1180                 val64 = TTI_CMD_MEM_WE |
1181                         TTI_CMD_MEM_STROBE_NEW_CMD |
1182                         TTI_CMD_MEM_OFFSET(i);
1183                 writeq(val64, &bar0->tti_command_mem);
1184
1185                 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1186                                           TTI_CMD_MEM_STROBE_NEW_CMD,
1187                                           S2IO_BIT_RESET) != SUCCESS)
1188                         return FAILURE;
1189         }
1190
1191         return SUCCESS;
1192 }
1193
1194 /**
1195  *  init_nic - Initialization of hardware
1196  *  @nic: device private variable
1197  *  Description: The function sequentially configures every block
1198  *  of the H/W from their reset values.
1199  *  Return Value:  SUCCESS on success and
1200  *  '-1' on failure (endian settings incorrect).
1201  */
1202
1203 static int init_nic(struct s2io_nic *nic)
1204 {
1205         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1206         struct net_device *dev = nic->dev;
1207         register u64 val64 = 0;
1208         void __iomem *add;
1209         u32 time;
1210         int i, j;
1211         int dtx_cnt = 0;
1212         unsigned long long mem_share;
1213         int mem_size;
1214         struct config_param *config = &nic->config;
1215         struct mac_info *mac_control = &nic->mac_control;
1216
1217         /* to set the swapper controle on the card */
1218         if (s2io_set_swapper(nic)) {
1219                 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
1220                 return -EIO;
1221         }
1222
1223         /*
1224          * Herc requires EOI to be removed from reset before XGXS, so..
1225          */
1226         if (nic->device_type & XFRAME_II_DEVICE) {
1227                 val64 = 0xA500000000ULL;
1228                 writeq(val64, &bar0->sw_reset);
1229                 msleep(500);
1230                 val64 = readq(&bar0->sw_reset);
1231         }
1232
1233         /* Remove XGXS from reset state */
1234         val64 = 0;
1235         writeq(val64, &bar0->sw_reset);
1236         msleep(500);
1237         val64 = readq(&bar0->sw_reset);
1238
1239         /* Ensure that it's safe to access registers by checking
1240          * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1241          */
1242         if (nic->device_type == XFRAME_II_DEVICE) {
1243                 for (i = 0; i < 50; i++) {
1244                         val64 = readq(&bar0->adapter_status);
1245                         if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1246                                 break;
1247                         msleep(10);
1248                 }
1249                 if (i == 50)
1250                         return -ENODEV;
1251         }
1252
1253         /*  Enable Receiving broadcasts */
1254         add = &bar0->mac_cfg;
1255         val64 = readq(&bar0->mac_cfg);
1256         val64 |= MAC_RMAC_BCAST_ENABLE;
1257         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1258         writel((u32)val64, add);
1259         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1260         writel((u32) (val64 >> 32), (add + 4));
1261
1262         /* Read registers in all blocks */
1263         val64 = readq(&bar0->mac_int_mask);
1264         val64 = readq(&bar0->mc_int_mask);
1265         val64 = readq(&bar0->xgxs_int_mask);
1266
1267         /*  Set MTU */
1268         val64 = dev->mtu;
1269         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1270
1271         if (nic->device_type & XFRAME_II_DEVICE) {
1272                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1273                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1274                                           &bar0->dtx_control, UF);
1275                         if (dtx_cnt & 0x1)
1276                                 msleep(1); /* Necessary!! */
1277                         dtx_cnt++;
1278                 }
1279         } else {
1280                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1281                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1282                                           &bar0->dtx_control, UF);
1283                         val64 = readq(&bar0->dtx_control);
1284                         dtx_cnt++;
1285                 }
1286         }
1287
1288         /*  Tx DMA Initialization */
1289         val64 = 0;
1290         writeq(val64, &bar0->tx_fifo_partition_0);
1291         writeq(val64, &bar0->tx_fifo_partition_1);
1292         writeq(val64, &bar0->tx_fifo_partition_2);
1293         writeq(val64, &bar0->tx_fifo_partition_3);
1294
1295         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1296                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1297
1298                 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1299                         vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1300
1301                 if (i == (config->tx_fifo_num - 1)) {
1302                         if (i % 2 == 0)
1303                                 i++;
1304                 }
1305
1306                 switch (i) {
1307                 case 1:
1308                         writeq(val64, &bar0->tx_fifo_partition_0);
1309                         val64 = 0;
1310                         j = 0;
1311                         break;
1312                 case 3:
1313                         writeq(val64, &bar0->tx_fifo_partition_1);
1314                         val64 = 0;
1315                         j = 0;
1316                         break;
1317                 case 5:
1318                         writeq(val64, &bar0->tx_fifo_partition_2);
1319                         val64 = 0;
1320                         j = 0;
1321                         break;
1322                 case 7:
1323                         writeq(val64, &bar0->tx_fifo_partition_3);
1324                         val64 = 0;
1325                         j = 0;
1326                         break;
1327                 default:
1328                         j++;
1329                         break;
1330                 }
1331         }
1332
1333         /*
1334          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1335          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1336          */
1337         if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
1338                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1339
1340         val64 = readq(&bar0->tx_fifo_partition_0);
1341         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1342                   &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1343
1344         /*
1345          * Initialization of Tx_PA_CONFIG register to ignore packet
1346          * integrity checking.
1347          */
1348         val64 = readq(&bar0->tx_pa_cfg);
1349         val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1350                 TX_PA_CFG_IGNORE_SNAP_OUI |
1351                 TX_PA_CFG_IGNORE_LLC_CTRL |
1352                 TX_PA_CFG_IGNORE_L2_ERR;
1353         writeq(val64, &bar0->tx_pa_cfg);
1354
1355         /* Rx DMA intialization. */
1356         val64 = 0;
1357         for (i = 0; i < config->rx_ring_num; i++) {
1358                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1359
1360                 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1361         }
1362         writeq(val64, &bar0->rx_queue_priority);
1363
1364         /*
1365          * Allocating equal share of memory to all the
1366          * configured Rings.
1367          */
1368         val64 = 0;
1369         if (nic->device_type & XFRAME_II_DEVICE)
1370                 mem_size = 32;
1371         else
1372                 mem_size = 64;
1373
1374         for (i = 0; i < config->rx_ring_num; i++) {
1375                 switch (i) {
1376                 case 0:
1377                         mem_share = (mem_size / config->rx_ring_num +
1378                                      mem_size % config->rx_ring_num);
1379                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1380                         continue;
1381                 case 1:
1382                         mem_share = (mem_size / config->rx_ring_num);
1383                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1384                         continue;
1385                 case 2:
1386                         mem_share = (mem_size / config->rx_ring_num);
1387                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1388                         continue;
1389                 case 3:
1390                         mem_share = (mem_size / config->rx_ring_num);
1391                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1392                         continue;
1393                 case 4:
1394                         mem_share = (mem_size / config->rx_ring_num);
1395                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1396                         continue;
1397                 case 5:
1398                         mem_share = (mem_size / config->rx_ring_num);
1399                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1400                         continue;
1401                 case 6:
1402                         mem_share = (mem_size / config->rx_ring_num);
1403                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1404                         continue;
1405                 case 7:
1406                         mem_share = (mem_size / config->rx_ring_num);
1407                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1408                         continue;
1409                 }
1410         }
1411         writeq(val64, &bar0->rx_queue_cfg);
1412
1413         /*
1414          * Filling Tx round robin registers
1415          * as per the number of FIFOs for equal scheduling priority
1416          */
1417         switch (config->tx_fifo_num) {
1418         case 1:
1419                 val64 = 0x0;
1420                 writeq(val64, &bar0->tx_w_round_robin_0);
1421                 writeq(val64, &bar0->tx_w_round_robin_1);
1422                 writeq(val64, &bar0->tx_w_round_robin_2);
1423                 writeq(val64, &bar0->tx_w_round_robin_3);
1424                 writeq(val64, &bar0->tx_w_round_robin_4);
1425                 break;
1426         case 2:
1427                 val64 = 0x0001000100010001ULL;
1428                 writeq(val64, &bar0->tx_w_round_robin_0);
1429                 writeq(val64, &bar0->tx_w_round_robin_1);
1430                 writeq(val64, &bar0->tx_w_round_robin_2);
1431                 writeq(val64, &bar0->tx_w_round_robin_3);
1432                 val64 = 0x0001000100000000ULL;
1433                 writeq(val64, &bar0->tx_w_round_robin_4);
1434                 break;
1435         case 3:
1436                 val64 = 0x0001020001020001ULL;
1437                 writeq(val64, &bar0->tx_w_round_robin_0);
1438                 val64 = 0x0200010200010200ULL;
1439                 writeq(val64, &bar0->tx_w_round_robin_1);
1440                 val64 = 0x0102000102000102ULL;
1441                 writeq(val64, &bar0->tx_w_round_robin_2);
1442                 val64 = 0x0001020001020001ULL;
1443                 writeq(val64, &bar0->tx_w_round_robin_3);
1444                 val64 = 0x0200010200000000ULL;
1445                 writeq(val64, &bar0->tx_w_round_robin_4);
1446                 break;
1447         case 4:
1448                 val64 = 0x0001020300010203ULL;
1449                 writeq(val64, &bar0->tx_w_round_robin_0);
1450                 writeq(val64, &bar0->tx_w_round_robin_1);
1451                 writeq(val64, &bar0->tx_w_round_robin_2);
1452                 writeq(val64, &bar0->tx_w_round_robin_3);
1453                 val64 = 0x0001020300000000ULL;
1454                 writeq(val64, &bar0->tx_w_round_robin_4);
1455                 break;
1456         case 5:
1457                 val64 = 0x0001020304000102ULL;
1458                 writeq(val64, &bar0->tx_w_round_robin_0);
1459                 val64 = 0x0304000102030400ULL;
1460                 writeq(val64, &bar0->tx_w_round_robin_1);
1461                 val64 = 0x0102030400010203ULL;
1462                 writeq(val64, &bar0->tx_w_round_robin_2);
1463                 val64 = 0x0400010203040001ULL;
1464                 writeq(val64, &bar0->tx_w_round_robin_3);
1465                 val64 = 0x0203040000000000ULL;
1466                 writeq(val64, &bar0->tx_w_round_robin_4);
1467                 break;
1468         case 6:
1469                 val64 = 0x0001020304050001ULL;
1470                 writeq(val64, &bar0->tx_w_round_robin_0);
1471                 val64 = 0x0203040500010203ULL;
1472                 writeq(val64, &bar0->tx_w_round_robin_1);
1473                 val64 = 0x0405000102030405ULL;
1474                 writeq(val64, &bar0->tx_w_round_robin_2);
1475                 val64 = 0x0001020304050001ULL;
1476                 writeq(val64, &bar0->tx_w_round_robin_3);
1477                 val64 = 0x0203040500000000ULL;
1478                 writeq(val64, &bar0->tx_w_round_robin_4);
1479                 break;
1480         case 7:
1481                 val64 = 0x0001020304050600ULL;
1482                 writeq(val64, &bar0->tx_w_round_robin_0);
1483                 val64 = 0x0102030405060001ULL;
1484                 writeq(val64, &bar0->tx_w_round_robin_1);
1485                 val64 = 0x0203040506000102ULL;
1486                 writeq(val64, &bar0->tx_w_round_robin_2);
1487                 val64 = 0x0304050600010203ULL;
1488                 writeq(val64, &bar0->tx_w_round_robin_3);
1489                 val64 = 0x0405060000000000ULL;
1490                 writeq(val64, &bar0->tx_w_round_robin_4);
1491                 break;
1492         case 8:
1493                 val64 = 0x0001020304050607ULL;
1494                 writeq(val64, &bar0->tx_w_round_robin_0);
1495                 writeq(val64, &bar0->tx_w_round_robin_1);
1496                 writeq(val64, &bar0->tx_w_round_robin_2);
1497                 writeq(val64, &bar0->tx_w_round_robin_3);
1498                 val64 = 0x0001020300000000ULL;
1499                 writeq(val64, &bar0->tx_w_round_robin_4);
1500                 break;
1501         }
1502
1503         /* Enable all configured Tx FIFO partitions */
1504         val64 = readq(&bar0->tx_fifo_partition_0);
1505         val64 |= (TX_FIFO_PARTITION_EN);
1506         writeq(val64, &bar0->tx_fifo_partition_0);
1507
1508         /* Filling the Rx round robin registers as per the
1509          * number of Rings and steering based on QoS with
1510          * equal priority.
1511          */
1512         switch (config->rx_ring_num) {
1513         case 1:
1514                 val64 = 0x0;
1515                 writeq(val64, &bar0->rx_w_round_robin_0);
1516                 writeq(val64, &bar0->rx_w_round_robin_1);
1517                 writeq(val64, &bar0->rx_w_round_robin_2);
1518                 writeq(val64, &bar0->rx_w_round_robin_3);
1519                 writeq(val64, &bar0->rx_w_round_robin_4);
1520
1521                 val64 = 0x8080808080808080ULL;
1522                 writeq(val64, &bar0->rts_qos_steering);
1523                 break;
1524         case 2:
1525                 val64 = 0x0001000100010001ULL;
1526                 writeq(val64, &bar0->rx_w_round_robin_0);
1527                 writeq(val64, &bar0->rx_w_round_robin_1);
1528                 writeq(val64, &bar0->rx_w_round_robin_2);
1529                 writeq(val64, &bar0->rx_w_round_robin_3);
1530                 val64 = 0x0001000100000000ULL;
1531                 writeq(val64, &bar0->rx_w_round_robin_4);
1532
1533                 val64 = 0x8080808040404040ULL;
1534                 writeq(val64, &bar0->rts_qos_steering);
1535                 break;
1536         case 3:
1537                 val64 = 0x0001020001020001ULL;
1538                 writeq(val64, &bar0->rx_w_round_robin_0);
1539                 val64 = 0x0200010200010200ULL;
1540                 writeq(val64, &bar0->rx_w_round_robin_1);
1541                 val64 = 0x0102000102000102ULL;
1542                 writeq(val64, &bar0->rx_w_round_robin_2);
1543                 val64 = 0x0001020001020001ULL;
1544                 writeq(val64, &bar0->rx_w_round_robin_3);
1545                 val64 = 0x0200010200000000ULL;
1546                 writeq(val64, &bar0->rx_w_round_robin_4);
1547
1548                 val64 = 0x8080804040402020ULL;
1549                 writeq(val64, &bar0->rts_qos_steering);
1550                 break;
1551         case 4:
1552                 val64 = 0x0001020300010203ULL;
1553                 writeq(val64, &bar0->rx_w_round_robin_0);
1554                 writeq(val64, &bar0->rx_w_round_robin_1);
1555                 writeq(val64, &bar0->rx_w_round_robin_2);
1556                 writeq(val64, &bar0->rx_w_round_robin_3);
1557                 val64 = 0x0001020300000000ULL;
1558                 writeq(val64, &bar0->rx_w_round_robin_4);
1559
1560                 val64 = 0x8080404020201010ULL;
1561                 writeq(val64, &bar0->rts_qos_steering);
1562                 break;
1563         case 5:
1564                 val64 = 0x0001020304000102ULL;
1565                 writeq(val64, &bar0->rx_w_round_robin_0);
1566                 val64 = 0x0304000102030400ULL;
1567                 writeq(val64, &bar0->rx_w_round_robin_1);
1568                 val64 = 0x0102030400010203ULL;
1569                 writeq(val64, &bar0->rx_w_round_robin_2);
1570                 val64 = 0x0400010203040001ULL;
1571                 writeq(val64, &bar0->rx_w_round_robin_3);
1572                 val64 = 0x0203040000000000ULL;
1573                 writeq(val64, &bar0->rx_w_round_robin_4);
1574
1575                 val64 = 0x8080404020201008ULL;
1576                 writeq(val64, &bar0->rts_qos_steering);
1577                 break;
1578         case 6:
1579                 val64 = 0x0001020304050001ULL;
1580                 writeq(val64, &bar0->rx_w_round_robin_0);
1581                 val64 = 0x0203040500010203ULL;
1582                 writeq(val64, &bar0->rx_w_round_robin_1);
1583                 val64 = 0x0405000102030405ULL;
1584                 writeq(val64, &bar0->rx_w_round_robin_2);
1585                 val64 = 0x0001020304050001ULL;
1586                 writeq(val64, &bar0->rx_w_round_robin_3);
1587                 val64 = 0x0203040500000000ULL;
1588                 writeq(val64, &bar0->rx_w_round_robin_4);
1589
1590                 val64 = 0x8080404020100804ULL;
1591                 writeq(val64, &bar0->rts_qos_steering);
1592                 break;
1593         case 7:
1594                 val64 = 0x0001020304050600ULL;
1595                 writeq(val64, &bar0->rx_w_round_robin_0);
1596                 val64 = 0x0102030405060001ULL;
1597                 writeq(val64, &bar0->rx_w_round_robin_1);
1598                 val64 = 0x0203040506000102ULL;
1599                 writeq(val64, &bar0->rx_w_round_robin_2);
1600                 val64 = 0x0304050600010203ULL;
1601                 writeq(val64, &bar0->rx_w_round_robin_3);
1602                 val64 = 0x0405060000000000ULL;
1603                 writeq(val64, &bar0->rx_w_round_robin_4);
1604
1605                 val64 = 0x8080402010080402ULL;
1606                 writeq(val64, &bar0->rts_qos_steering);
1607                 break;
1608         case 8:
1609                 val64 = 0x0001020304050607ULL;
1610                 writeq(val64, &bar0->rx_w_round_robin_0);
1611                 writeq(val64, &bar0->rx_w_round_robin_1);
1612                 writeq(val64, &bar0->rx_w_round_robin_2);
1613                 writeq(val64, &bar0->rx_w_round_robin_3);
1614                 val64 = 0x0001020300000000ULL;
1615                 writeq(val64, &bar0->rx_w_round_robin_4);
1616
1617                 val64 = 0x8040201008040201ULL;
1618                 writeq(val64, &bar0->rts_qos_steering);
1619                 break;
1620         }
1621
1622         /* UDP Fix */
1623         val64 = 0;
1624         for (i = 0; i < 8; i++)
1625                 writeq(val64, &bar0->rts_frm_len_n[i]);
1626
1627         /* Set the default rts frame length for the rings configured */
1628         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1629         for (i = 0 ; i < config->rx_ring_num ; i++)
1630                 writeq(val64, &bar0->rts_frm_len_n[i]);
1631
1632         /* Set the frame length for the configured rings
1633          * desired by the user
1634          */
1635         for (i = 0; i < config->rx_ring_num; i++) {
1636                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1637                  * specified frame length steering.
1638                  * If the user provides the frame length then program
1639                  * the rts_frm_len register for those values or else
1640                  * leave it as it is.
1641                  */
1642                 if (rts_frm_len[i] != 0) {
1643                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1644                                &bar0->rts_frm_len_n[i]);
1645                 }
1646         }
1647
1648         /* Disable differentiated services steering logic */
1649         for (i = 0; i < 64; i++) {
1650                 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1651                         DBG_PRINT(ERR_DBG,
1652                                   "%s: rts_ds_steer failed on codepoint %d\n",
1653                                   dev->name, i);
1654                         return -ENODEV;
1655                 }
1656         }
1657
1658         /* Program statistics memory */
1659         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1660
1661         if (nic->device_type == XFRAME_II_DEVICE) {
1662                 val64 = STAT_BC(0x320);
1663                 writeq(val64, &bar0->stat_byte_cnt);
1664         }
1665
1666         /*
1667          * Initializing the sampling rate for the device to calculate the
1668          * bandwidth utilization.
1669          */
1670         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1671                 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1672         writeq(val64, &bar0->mac_link_util);
1673
1674         /*
1675          * Initializing the Transmit and Receive Traffic Interrupt
1676          * Scheme.
1677          */
1678
1679         /* Initialize TTI */
1680         if (SUCCESS != init_tti(nic, nic->last_link_state))
1681                 return -ENODEV;
1682
1683         /* RTI Initialization */
1684         if (nic->device_type == XFRAME_II_DEVICE) {
1685                 /*
1686                  * Programmed to generate Apprx 500 Intrs per
1687                  * second
1688                  */
1689                 int count = (nic->config.bus_speed * 125)/4;
1690                 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1691         } else
1692                 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1693         val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1694                 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1695                 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1696                 RTI_DATA1_MEM_RX_TIMER_AC_EN;
1697
1698         writeq(val64, &bar0->rti_data1_mem);
1699
1700         val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1701                 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1702         if (nic->config.intr_type == MSI_X)
1703                 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1704                           RTI_DATA2_MEM_RX_UFC_D(0x40));
1705         else
1706                 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1707                           RTI_DATA2_MEM_RX_UFC_D(0x80));
1708         writeq(val64, &bar0->rti_data2_mem);
1709
1710         for (i = 0; i < config->rx_ring_num; i++) {
1711                 val64 = RTI_CMD_MEM_WE |
1712                         RTI_CMD_MEM_STROBE_NEW_CMD |
1713                         RTI_CMD_MEM_OFFSET(i);
1714                 writeq(val64, &bar0->rti_command_mem);
1715
1716                 /*
1717                  * Once the operation completes, the Strobe bit of the
1718                  * command register will be reset. We poll for this
1719                  * particular condition. We wait for a maximum of 500ms
1720                  * for the operation to complete, if it's not complete
1721                  * by then we return error.
1722                  */
1723                 time = 0;
1724                 while (true) {
1725                         val64 = readq(&bar0->rti_command_mem);
1726                         if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1727                                 break;
1728
1729                         if (time > 10) {
1730                                 DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
1731                                           dev->name);
1732                                 return -ENODEV;
1733                         }
1734                         time++;
1735                         msleep(50);
1736                 }
1737         }
1738
1739         /*
1740          * Initializing proper values as Pause threshold into all
1741          * the 8 Queues on Rx side.
1742          */
1743         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1744         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1745
1746         /* Disable RMAC PAD STRIPPING */
1747         add = &bar0->mac_cfg;
1748         val64 = readq(&bar0->mac_cfg);
1749         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1750         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1751         writel((u32) (val64), add);
1752         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1753         writel((u32) (val64 >> 32), (add + 4));
1754         val64 = readq(&bar0->mac_cfg);
1755
1756         /* Enable FCS stripping by adapter */
1757         add = &bar0->mac_cfg;
1758         val64 = readq(&bar0->mac_cfg);
1759         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1760         if (nic->device_type == XFRAME_II_DEVICE)
1761                 writeq(val64, &bar0->mac_cfg);
1762         else {
1763                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1764                 writel((u32) (val64), add);
1765                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1766                 writel((u32) (val64 >> 32), (add + 4));
1767         }
1768
1769         /*
1770          * Set the time value to be inserted in the pause frame
1771          * generated by xena.
1772          */
1773         val64 = readq(&bar0->rmac_pause_cfg);
1774         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1775         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1776         writeq(val64, &bar0->rmac_pause_cfg);
1777
1778         /*
1779          * Set the Threshold Limit for Generating the pause frame
1780          * If the amount of data in any Queue exceeds ratio of
1781          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1782          * pause frame is generated
1783          */
1784         val64 = 0;
1785         for (i = 0; i < 4; i++) {
1786                 val64 |= (((u64)0xFF00 |
1787                            nic->mac_control.mc_pause_threshold_q0q3)
1788                           << (i * 2 * 8));
1789         }
1790         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1791
1792         val64 = 0;
1793         for (i = 0; i < 4; i++) {
1794                 val64 |= (((u64)0xFF00 |
1795                            nic->mac_control.mc_pause_threshold_q4q7)
1796                           << (i * 2 * 8));
1797         }
1798         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1799
1800         /*
1801          * TxDMA will stop Read request if the number of read split has
1802          * exceeded the limit pointed by shared_splits
1803          */
1804         val64 = readq(&bar0->pic_control);
1805         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1806         writeq(val64, &bar0->pic_control);
1807
1808         if (nic->config.bus_speed == 266) {
1809                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1810                 writeq(0x0, &bar0->read_retry_delay);
1811                 writeq(0x0, &bar0->write_retry_delay);
1812         }
1813
1814         /*
1815          * Programming the Herc to split every write transaction
1816          * that does not start on an ADB to reduce disconnects.
1817          */
1818         if (nic->device_type == XFRAME_II_DEVICE) {
1819                 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1820                         MISC_LINK_STABILITY_PRD(3);
1821                 writeq(val64, &bar0->misc_control);
1822                 val64 = readq(&bar0->pic_control2);
1823                 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1824                 writeq(val64, &bar0->pic_control2);
1825         }
1826         if (strstr(nic->product_name, "CX4")) {
1827                 val64 = TMAC_AVG_IPG(0x17);
1828                 writeq(val64, &bar0->tmac_avg_ipg);
1829         }
1830
1831         return SUCCESS;
1832 }
1833 #define LINK_UP_DOWN_INTERRUPT          1
1834 #define MAC_RMAC_ERR_TIMER              2
1835
1836 static int s2io_link_fault_indication(struct s2io_nic *nic)
1837 {
1838         if (nic->device_type == XFRAME_II_DEVICE)
1839                 return LINK_UP_DOWN_INTERRUPT;
1840         else
1841                 return MAC_RMAC_ERR_TIMER;
1842 }
1843
1844 /**
1845  *  do_s2io_write_bits -  update alarm bits in alarm register
1846  *  @value: alarm bits
1847  *  @flag: interrupt status
1848  *  @addr: address value
1849  *  Description: update alarm bits in alarm register
1850  *  Return Value:
1851  *  NONE.
1852  */
1853 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1854 {
1855         u64 temp64;
1856
1857         temp64 = readq(addr);
1858
1859         if (flag == ENABLE_INTRS)
1860                 temp64 &= ~((u64)value);
1861         else
1862                 temp64 |= ((u64)value);
1863         writeq(temp64, addr);
1864 }
1865
1866 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1867 {
1868         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1869         register u64 gen_int_mask = 0;
1870         u64 interruptible;
1871
1872         writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1873         if (mask & TX_DMA_INTR) {
1874                 gen_int_mask |= TXDMA_INT_M;
1875
1876                 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1877                                    TXDMA_PCC_INT | TXDMA_TTI_INT |
1878                                    TXDMA_LSO_INT | TXDMA_TPA_INT |
1879                                    TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1880
1881                 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1882                                    PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1883                                    PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1884                                    &bar0->pfc_err_mask);
1885
1886                 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1887                                    TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1888                                    TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1889
1890                 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1891                                    PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1892                                    PCC_N_SERR | PCC_6_COF_OV_ERR |
1893                                    PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1894                                    PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1895                                    PCC_TXB_ECC_SG_ERR,
1896                                    flag, &bar0->pcc_err_mask);
1897
1898                 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1899                                    TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1900
1901                 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1902                                    LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1903                                    LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1904                                    flag, &bar0->lso_err_mask);
1905
1906                 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1907                                    flag, &bar0->tpa_err_mask);
1908
1909                 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1910         }
1911
1912         if (mask & TX_MAC_INTR) {
1913                 gen_int_mask |= TXMAC_INT_M;
1914                 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1915                                    &bar0->mac_int_mask);
1916                 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1917                                    TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1918                                    TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1919                                    flag, &bar0->mac_tmac_err_mask);
1920         }
1921
1922         if (mask & TX_XGXS_INTR) {
1923                 gen_int_mask |= TXXGXS_INT_M;
1924                 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1925                                    &bar0->xgxs_int_mask);
1926                 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1927                                    TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1928                                    flag, &bar0->xgxs_txgxs_err_mask);
1929         }
1930
1931         if (mask & RX_DMA_INTR) {
1932                 gen_int_mask |= RXDMA_INT_M;
1933                 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1934                                    RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1935                                    flag, &bar0->rxdma_int_mask);
1936                 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1937                                    RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1938                                    RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1939                                    RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1940                 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1941                                    PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1942                                    PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1943                                    &bar0->prc_pcix_err_mask);
1944                 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1945                                    RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1946                                    &bar0->rpa_err_mask);
1947                 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1948                                    RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1949                                    RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1950                                    RDA_FRM_ECC_SG_ERR |
1951                                    RDA_MISC_ERR|RDA_PCIX_ERR,
1952                                    flag, &bar0->rda_err_mask);
1953                 do_s2io_write_bits(RTI_SM_ERR_ALARM |
1954                                    RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
1955                                    flag, &bar0->rti_err_mask);
1956         }
1957
1958         if (mask & RX_MAC_INTR) {
1959                 gen_int_mask |= RXMAC_INT_M;
1960                 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
1961                                    &bar0->mac_int_mask);
1962                 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
1963                                  RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
1964                                  RMAC_DOUBLE_ECC_ERR);
1965                 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
1966                         interruptible |= RMAC_LINK_STATE_CHANGE_INT;
1967                 do_s2io_write_bits(interruptible,
1968                                    flag, &bar0->mac_rmac_err_mask);
1969         }
1970
1971         if (mask & RX_XGXS_INTR) {
1972                 gen_int_mask |= RXXGXS_INT_M;
1973                 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
1974                                    &bar0->xgxs_int_mask);
1975                 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
1976                                    &bar0->xgxs_rxgxs_err_mask);
1977         }
1978
1979         if (mask & MC_INTR) {
1980                 gen_int_mask |= MC_INT_M;
1981                 do_s2io_write_bits(MC_INT_MASK_MC_INT,
1982                                    flag, &bar0->mc_int_mask);
1983                 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
1984                                    MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
1985                                    &bar0->mc_err_mask);
1986         }
1987         nic->general_int_mask = gen_int_mask;
1988
1989         /* Remove this line when alarm interrupts are enabled */
1990         nic->general_int_mask = 0;
1991 }
1992
1993 /**
1994  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1995  *  @nic: device private variable,
1996  *  @mask: A mask indicating which Intr block must be modified and,
1997  *  @flag: A flag indicating whether to enable or disable the Intrs.
1998  *  Description: This function will either disable or enable the interrupts
1999  *  depending on the flag argument. The mask argument can be used to
2000  *  enable/disable any Intr block.
2001  *  Return Value: NONE.
2002  */
2003
2004 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2005 {
2006         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2007         register u64 temp64 = 0, intr_mask = 0;
2008
2009         intr_mask = nic->general_int_mask;
2010
2011         /*  Top level interrupt classification */
2012         /*  PIC Interrupts */
2013         if (mask & TX_PIC_INTR) {
2014                 /*  Enable PIC Intrs in the general intr mask register */
2015                 intr_mask |= TXPIC_INT_M;
2016                 if (flag == ENABLE_INTRS) {
2017                         /*
2018                          * If Hercules adapter enable GPIO otherwise
2019                          * disable all PCIX, Flash, MDIO, IIC and GPIO
2020                          * interrupts for now.
2021                          * TODO
2022                          */
2023                         if (s2io_link_fault_indication(nic) ==
2024                             LINK_UP_DOWN_INTERRUPT) {
2025                                 do_s2io_write_bits(PIC_INT_GPIO, flag,
2026                                                    &bar0->pic_int_mask);
2027                                 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2028                                                    &bar0->gpio_int_mask);
2029                         } else
2030                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2031                 } else if (flag == DISABLE_INTRS) {
2032                         /*
2033                          * Disable PIC Intrs in the general
2034                          * intr mask register
2035                          */
2036                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2037                 }
2038         }
2039
2040         /*  Tx traffic interrupts */
2041         if (mask & TX_TRAFFIC_INTR) {
2042                 intr_mask |= TXTRAFFIC_INT_M;
2043                 if (flag == ENABLE_INTRS) {
2044                         /*
2045                          * Enable all the Tx side interrupts
2046                          * writing 0 Enables all 64 TX interrupt levels
2047                          */
2048                         writeq(0x0, &bar0->tx_traffic_mask);
2049                 } else if (flag == DISABLE_INTRS) {
2050                         /*
2051                          * Disable Tx Traffic Intrs in the general intr mask
2052                          * register.
2053                          */
2054                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2055                 }
2056         }
2057
2058         /*  Rx traffic interrupts */
2059         if (mask & RX_TRAFFIC_INTR) {
2060                 intr_mask |= RXTRAFFIC_INT_M;
2061                 if (flag == ENABLE_INTRS) {
2062                         /* writing 0 Enables all 8 RX interrupt levels */
2063                         writeq(0x0, &bar0->rx_traffic_mask);
2064                 } else if (flag == DISABLE_INTRS) {
2065                         /*
2066                          * Disable Rx Traffic Intrs in the general intr mask
2067                          * register.
2068                          */
2069                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2070                 }
2071         }
2072
2073         temp64 = readq(&bar0->general_int_mask);
2074         if (flag == ENABLE_INTRS)
2075                 temp64 &= ~((u64)intr_mask);
2076         else
2077                 temp64 = DISABLE_ALL_INTRS;
2078         writeq(temp64, &bar0->general_int_mask);
2079
2080         nic->general_int_mask = readq(&bar0->general_int_mask);
2081 }
2082
2083 /**
2084  *  verify_pcc_quiescent- Checks for PCC quiescent state
2085  *  Return: 1 If PCC is quiescence
2086  *          0 If PCC is not quiescence
2087  */
2088 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2089 {
2090         int ret = 0, herc;
2091         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2092         u64 val64 = readq(&bar0->adapter_status);
2093
2094         herc = (sp->device_type == XFRAME_II_DEVICE);
2095
2096         if (flag == false) {
2097                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2098                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2099                                 ret = 1;
2100                 } else {
2101                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2102                                 ret = 1;
2103                 }
2104         } else {
2105                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2106                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2107                              ADAPTER_STATUS_RMAC_PCC_IDLE))
2108                                 ret = 1;
2109                 } else {
2110                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2111                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2112                                 ret = 1;
2113                 }
2114         }
2115
2116         return ret;
2117 }
2118 /**
2119  *  verify_xena_quiescence - Checks whether the H/W is ready
2120  *  Description: Returns whether the H/W is ready to go or not. Depending
2121  *  on whether adapter enable bit was written or not the comparison
2122  *  differs and the calling function passes the input argument flag to
2123  *  indicate this.
2124  *  Return: 1 If xena is quiescence
2125  *          0 If Xena is not quiescence
2126  */
2127
2128 static int verify_xena_quiescence(struct s2io_nic *sp)
2129 {
2130         int  mode;
2131         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2132         u64 val64 = readq(&bar0->adapter_status);
2133         mode = s2io_verify_pci_mode(sp);
2134
2135         if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2136                 DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
2137                 return 0;
2138         }
2139         if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2140                 DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
2141                 return 0;
2142         }
2143         if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2144                 DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
2145                 return 0;
2146         }
2147         if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2148                 DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
2149                 return 0;
2150         }
2151         if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2152                 DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
2153                 return 0;
2154         }
2155         if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2156                 DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
2157                 return 0;
2158         }
2159         if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2160                 DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
2161                 return 0;
2162         }
2163         if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2164                 DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
2165                 return 0;
2166         }
2167
2168         /*
2169          * In PCI 33 mode, the P_PLL is not used, and therefore,
2170          * the the P_PLL_LOCK bit in the adapter_status register will
2171          * not be asserted.
2172          */
2173         if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2174             sp->device_type == XFRAME_II_DEVICE &&
2175             mode != PCI_MODE_PCI_33) {
2176                 DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
2177                 return 0;
2178         }
2179         if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2180               ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2181                 DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
2182                 return 0;
2183         }
2184         return 1;
2185 }
2186
2187 /**
2188  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
2189  * @sp: Pointer to device specifc structure
2190  * Description :
2191  * New procedure to clear mac address reading  problems on Alpha platforms
2192  *
2193  */
2194
2195 static void fix_mac_address(struct s2io_nic *sp)
2196 {
2197         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2198         int i = 0;
2199
2200         while (fix_mac[i] != END_SIGN) {
2201                 writeq(fix_mac[i++], &bar0->gpio_control);
2202                 udelay(10);
2203                 (void) readq(&bar0->gpio_control);
2204         }
2205 }
2206
2207 /**
2208  *  start_nic - Turns the device on
2209  *  @nic : device private variable.
2210  *  Description:
2211  *  This function actually turns the device on. Before this  function is
2212  *  called,all Registers are configured from their reset states
2213  *  and shared memory is allocated but the NIC is still quiescent. On
2214  *  calling this function, the device interrupts are cleared and the NIC is
2215  *  literally switched on by writing into the adapter control register.
2216  *  Return Value:
2217  *  SUCCESS on success and -1 on failure.
2218  */
2219
2220 static int start_nic(struct s2io_nic *nic)
2221 {
2222         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2223         struct net_device *dev = nic->dev;
2224         register u64 val64 = 0;
2225         u16 subid, i;
2226         struct config_param *config = &nic->config;
2227         struct mac_info *mac_control = &nic->mac_control;
2228
2229         /*  PRC Initialization and configuration */
2230         for (i = 0; i < config->rx_ring_num; i++) {
2231                 struct ring_info *ring = &mac_control->rings[i];
2232
2233                 writeq((u64)ring->rx_blocks[0].block_dma_addr,
2234                        &bar0->prc_rxd0_n[i]);
2235
2236                 val64 = readq(&bar0->prc_ctrl_n[i]);
2237                 if (nic->rxd_mode == RXD_MODE_1)
2238                         val64 |= PRC_CTRL_RC_ENABLED;
2239                 else
2240                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2241                 if (nic->device_type == XFRAME_II_DEVICE)
2242                         val64 |= PRC_CTRL_GROUP_READS;
2243                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2244                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2245                 writeq(val64, &bar0->prc_ctrl_n[i]);
2246         }
2247
2248         if (nic->rxd_mode == RXD_MODE_3B) {
2249                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2250                 val64 = readq(&bar0->rx_pa_cfg);
2251                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2252                 writeq(val64, &bar0->rx_pa_cfg);
2253         }
2254
2255         if (vlan_tag_strip == 0) {
2256                 val64 = readq(&bar0->rx_pa_cfg);
2257                 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2258                 writeq(val64, &bar0->rx_pa_cfg);
2259                 nic->vlan_strip_flag = 0;
2260         }
2261
2262         /*
2263          * Enabling MC-RLDRAM. After enabling the device, we timeout
2264          * for around 100ms, which is approximately the time required
2265          * for the device to be ready for operation.
2266          */
2267         val64 = readq(&bar0->mc_rldram_mrs);
2268         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2269         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2270         val64 = readq(&bar0->mc_rldram_mrs);
2271
2272         msleep(100);    /* Delay by around 100 ms. */
2273
2274         /* Enabling ECC Protection. */
2275         val64 = readq(&bar0->adapter_control);
2276         val64 &= ~ADAPTER_ECC_EN;
2277         writeq(val64, &bar0->adapter_control);
2278
2279         /*
2280          * Verify if the device is ready to be enabled, if so enable
2281          * it.
2282          */
2283         val64 = readq(&bar0->adapter_status);
2284         if (!verify_xena_quiescence(nic)) {
2285                 DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2286                           "Adapter status reads: 0x%llx\n",
2287                           dev->name, (unsigned long long)val64);
2288                 return FAILURE;
2289         }
2290
2291         /*
2292          * With some switches, link might be already up at this point.
2293          * Because of this weird behavior, when we enable laser,
2294          * we may not get link. We need to handle this. We cannot
2295          * figure out which switch is misbehaving. So we are forced to
2296          * make a global change.
2297          */
2298
2299         /* Enabling Laser. */
2300         val64 = readq(&bar0->adapter_control);
2301         val64 |= ADAPTER_EOI_TX_ON;
2302         writeq(val64, &bar0->adapter_control);
2303
2304         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2305                 /*
2306                  * Dont see link state interrupts initially on some switches,
2307                  * so directly scheduling the link state task here.
2308                  */
2309                 schedule_work(&nic->set_link_task);
2310         }
2311         /* SXE-002: Initialize link and activity LED */
2312         subid = nic->pdev->subsystem_device;
2313         if (((subid & 0xFF) >= 0x07) &&
2314             (nic->device_type == XFRAME_I_DEVICE)) {
2315                 val64 = readq(&bar0->gpio_control);
2316                 val64 |= 0x0000800000000000ULL;
2317                 writeq(val64, &bar0->gpio_control);
2318                 val64 = 0x0411040400000000ULL;
2319                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2320         }
2321
2322         return SUCCESS;
2323 }
2324 /**
2325  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2326  */
2327 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2328                                         struct TxD *txdlp, int get_off)
2329 {
2330         struct s2io_nic *nic = fifo_data->nic;
2331         struct sk_buff *skb;
2332         struct TxD *txds;
2333         u16 j, frg_cnt;
2334
2335         txds = txdlp;
2336         if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2337                 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2338                                  sizeof(u64), PCI_DMA_TODEVICE);
2339                 txds++;
2340         }
2341
2342         skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
2343         if (!skb) {
2344                 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2345                 return NULL;
2346         }
2347         pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2348                          skb_headlen(skb), PCI_DMA_TODEVICE);
2349         frg_cnt = skb_shinfo(skb)->nr_frags;
2350         if (frg_cnt) {
2351                 txds++;
2352                 for (j = 0; j < frg_cnt; j++, txds++) {
2353                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2354                         if (!txds->Buffer_Pointer)
2355                                 break;
2356                         pci_unmap_page(nic->pdev,
2357                                        (dma_addr_t)txds->Buffer_Pointer,
2358                                        frag->size, PCI_DMA_TODEVICE);
2359                 }
2360         }
2361         memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2362         return skb;
2363 }
2364
2365 /**
2366  *  free_tx_buffers - Free all queued Tx buffers
2367  *  @nic : device private variable.
2368  *  Description:
2369  *  Free all queued Tx buffers.
2370  *  Return Value: void
2371  */
2372
2373 static void free_tx_buffers(struct s2io_nic *nic)
2374 {
2375         struct net_device *dev = nic->dev;
2376         struct sk_buff *skb;
2377         struct TxD *txdp;
2378         int i, j;
2379         int cnt = 0;
2380         struct config_param *config = &nic->config;
2381         struct mac_info *mac_control = &nic->mac_control;
2382         struct stat_block *stats = mac_control->stats_info;
2383         struct swStat *swstats = &stats->sw_stat;
2384
2385         for (i = 0; i < config->tx_fifo_num; i++) {
2386                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2387                 struct fifo_info *fifo = &mac_control->fifos[i];
2388                 unsigned long flags;
2389
2390                 spin_lock_irqsave(&fifo->tx_lock, flags);
2391                 for (j = 0; j < tx_cfg->fifo_len; j++) {
2392                         txdp = fifo->list_info[j].list_virt_addr;
2393                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2394                         if (skb) {
2395                                 swstats->mem_freed += skb->truesize;
2396                                 dev_kfree_skb(skb);
2397                                 cnt++;
2398                         }
2399                 }
2400                 DBG_PRINT(INTR_DBG,
2401                           "%s: forcibly freeing %d skbs on FIFO%d\n",
2402                           dev->name, cnt, i);
2403                 fifo->tx_curr_get_info.offset = 0;
2404                 fifo->tx_curr_put_info.offset = 0;
2405                 spin_unlock_irqrestore(&fifo->tx_lock, flags);
2406         }
2407 }
2408
2409 /**
2410  *   stop_nic -  To stop the nic
2411  *   @nic ; device private variable.
2412  *   Description:
2413  *   This function does exactly the opposite of what the start_nic()
2414  *   function does. This function is called to stop the device.
2415  *   Return Value:
2416  *   void.
2417  */
2418
2419 static void stop_nic(struct s2io_nic *nic)
2420 {
2421         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2422         register u64 val64 = 0;
2423         u16 interruptible;
2424
2425         /*  Disable all interrupts */
2426         en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2427         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2428         interruptible |= TX_PIC_INTR;
2429         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2430
2431         /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2432         val64 = readq(&bar0->adapter_control);
2433         val64 &= ~(ADAPTER_CNTL_EN);
2434         writeq(val64, &bar0->adapter_control);
2435 }
2436
2437 /**
2438  *  fill_rx_buffers - Allocates the Rx side skbs
2439  *  @ring_info: per ring structure
2440  *  @from_card_up: If this is true, we will map the buffer to get
2441  *     the dma address for buf0 and buf1 to give it to the card.
2442  *     Else we will sync the already mapped buffer to give it to the card.
2443  *  Description:
2444  *  The function allocates Rx side skbs and puts the physical
2445  *  address of these buffers into the RxD buffer pointers, so that the NIC
2446  *  can DMA the received frame into these locations.
2447  *  The NIC supports 3 receive modes, viz
2448  *  1. single buffer,
2449  *  2. three buffer and
2450  *  3. Five buffer modes.
2451  *  Each mode defines how many fragments the received frame will be split
2452  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2453  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2454  *  is split into 3 fragments. As of now only single buffer mode is
2455  *  supported.
2456  *   Return Value:
2457  *  SUCCESS on success or an appropriate -ve value on failure.
2458  */
2459 static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2460                            int from_card_up)
2461 {
2462         struct sk_buff *skb;
2463         struct RxD_t *rxdp;
2464         int off, size, block_no, block_no1;
2465         u32 alloc_tab = 0;
2466         u32 alloc_cnt;
2467         u64 tmp;
2468         struct buffAdd *ba;
2469         struct RxD_t *first_rxdp = NULL;
2470         u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2471         int rxd_index = 0;
2472         struct RxD1 *rxdp1;
2473         struct RxD3 *rxdp3;
2474         struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
2475
2476         alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2477
2478         block_no1 = ring->rx_curr_get_info.block_index;
2479         while (alloc_tab < alloc_cnt) {
2480                 block_no = ring->rx_curr_put_info.block_index;
2481
2482                 off = ring->rx_curr_put_info.offset;
2483
2484                 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2485
2486                 rxd_index = off + 1;
2487                 if (block_no)
2488                         rxd_index += (block_no * ring->rxd_count);
2489
2490                 if ((block_no == block_no1) &&
2491                     (off == ring->rx_curr_get_info.offset) &&
2492                     (rxdp->Host_Control)) {
2493                         DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2494                                   ring->dev->name);
2495                         goto end;
2496                 }
2497                 if (off && (off == ring->rxd_count)) {
2498                         ring->rx_curr_put_info.block_index++;
2499                         if (ring->rx_curr_put_info.block_index ==
2500                             ring->block_count)
2501                                 ring->rx_curr_put_info.block_index = 0;
2502                         block_no = ring->rx_curr_put_info.block_index;
2503                         off = 0;
2504                         ring->rx_curr_put_info.offset = off;
2505                         rxdp = ring->rx_blocks[block_no].block_virt_addr;
2506                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2507                                   ring->dev->name, rxdp);
2508
2509                 }
2510
2511                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2512                     ((ring->rxd_mode == RXD_MODE_3B) &&
2513                      (rxdp->Control_2 & s2BIT(0)))) {
2514                         ring->rx_curr_put_info.offset = off;
2515                         goto end;
2516                 }
2517                 /* calculate size of skb based on ring mode */
2518                 size = ring->mtu +
2519                         HEADER_ETHERNET_II_802_3_SIZE +
2520                         HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2521                 if (ring->rxd_mode == RXD_MODE_1)
2522                         size += NET_IP_ALIGN;
2523                 else
2524                         size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2525
2526                 /* allocate skb */
2527                 skb = dev_alloc_skb(size);
2528                 if (!skb) {
2529                         DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2530                                   ring->dev->name);
2531                         if (first_rxdp) {
2532                                 wmb();
2533                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2534                         }
2535                         swstats->mem_alloc_fail_cnt++;
2536
2537                         return -ENOMEM ;
2538                 }
2539                 swstats->mem_allocated += skb->truesize;
2540
2541                 if (ring->rxd_mode == RXD_MODE_1) {
2542                         /* 1 buffer mode - normal operation mode */
2543                         rxdp1 = (struct RxD1 *)rxdp;
2544                         memset(rxdp, 0, sizeof(struct RxD1));
2545                         skb_reserve(skb, NET_IP_ALIGN);
2546                         rxdp1->Buffer0_ptr =
2547                                 pci_map_single(ring->pdev, skb->data,
2548                                                size - NET_IP_ALIGN,
2549                                                PCI_DMA_FROMDEVICE);
2550                         if (pci_dma_mapping_error(nic->pdev,
2551                                                   rxdp1->Buffer0_ptr))
2552                                 goto pci_map_failed;
2553
2554                         rxdp->Control_2 =
2555                                 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2556                         rxdp->Host_Control = (unsigned long)skb;
2557                 } else if (ring->rxd_mode == RXD_MODE_3B) {
2558                         /*
2559                          * 2 buffer mode -
2560                          * 2 buffer mode provides 128
2561                          * byte aligned receive buffers.
2562                          */
2563
2564                         rxdp3 = (struct RxD3 *)rxdp;
2565                         /* save buffer pointers to avoid frequent dma mapping */
2566                         Buffer0_ptr = rxdp3->Buffer0_ptr;
2567                         Buffer1_ptr = rxdp3->Buffer1_ptr;
2568                         memset(rxdp, 0, sizeof(struct RxD3));
2569                         /* restore the buffer pointers for dma sync*/
2570                         rxdp3->Buffer0_ptr = Buffer0_ptr;
2571                         rxdp3->Buffer1_ptr = Buffer1_ptr;
2572
2573                         ba = &ring->ba[block_no][off];
2574                         skb_reserve(skb, BUF0_LEN);
2575                         tmp = (u64)(unsigned long)skb->data;
2576                         tmp += ALIGN_SIZE;
2577                         tmp &= ~ALIGN_SIZE;
2578                         skb->data = (void *) (unsigned long)tmp;
2579                         skb_reset_tail_pointer(skb);
2580
2581                         if (from_card_up) {
2582                                 rxdp3->Buffer0_ptr =
2583                                         pci_map_single(ring->pdev, ba->ba_0,
2584                                                        BUF0_LEN,
2585                                                        PCI_DMA_FROMDEVICE);
2586                                 if (pci_dma_mapping_error(nic->pdev,
2587                                                           rxdp3->Buffer0_ptr))
2588                                         goto pci_map_failed;
2589                         } else
2590                                 pci_dma_sync_single_for_device(ring->pdev,
2591                                                                (dma_addr_t)rxdp3->Buffer0_ptr,
2592                                                                BUF0_LEN,
2593                                                                PCI_DMA_FROMDEVICE);
2594
2595                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2596                         if (ring->rxd_mode == RXD_MODE_3B) {
2597                                 /* Two buffer mode */
2598
2599                                 /*
2600                                  * Buffer2 will have L3/L4 header plus
2601                                  * L4 payload
2602                                  */
2603                                 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2604                                                                     skb->data,
2605                                                                     ring->mtu + 4,
2606                                                                     PCI_DMA_FROMDEVICE);
2607
2608                                 if (pci_dma_mapping_error(nic->pdev,
2609                                                           rxdp3->Buffer2_ptr))
2610                                         goto pci_map_failed;
2611
2612                                 if (from_card_up) {
2613                                         rxdp3->Buffer1_ptr =
2614                                                 pci_map_single(ring->pdev,
2615                                                                ba->ba_1,
2616                                                                BUF1_LEN,
2617                                                                PCI_DMA_FROMDEVICE);
2618
2619                                         if (pci_dma_mapping_error(nic->pdev,
2620                                                                   rxdp3->Buffer1_ptr)) {
2621                                                 pci_unmap_single(ring->pdev,
2622                                                                  (dma_addr_t)(unsigned long)
2623                                                                  skb->data,
2624                                                                  ring->mtu + 4,
2625                                                                  PCI_DMA_FROMDEVICE);
2626                                                 goto pci_map_failed;
2627                                         }
2628                                 }
2629                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2630                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2631                                         (ring->mtu + 4);
2632                         }
2633                         rxdp->Control_2 |= s2BIT(0);
2634                         rxdp->Host_Control = (unsigned long) (skb);
2635                 }
2636                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2637                         rxdp->Control_1 |= RXD_OWN_XENA;
2638                 off++;
2639                 if (off == (ring->rxd_count + 1))
2640                         off = 0;
2641                 ring->rx_curr_put_info.offset = off;
2642
2643                 rxdp->Control_2 |= SET_RXD_MARKER;
2644                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2645                         if (first_rxdp) {
2646                                 wmb();
2647                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2648                         }
2649                         first_rxdp = rxdp;
2650                 }
2651                 ring->rx_bufs_left += 1;
2652                 alloc_tab++;
2653         }
2654
2655 end:
2656         /* Transfer ownership of first descriptor to adapter just before
2657          * exiting. Before that, use memory barrier so that ownership
2658          * and other fields are seen by adapter correctly.
2659          */
2660         if (first_rxdp) {
2661                 wmb();
2662                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2663         }
2664
2665         return SUCCESS;
2666
2667 pci_map_failed:
2668         swstats->pci_map_fail_cnt++;
2669         swstats->mem_freed += skb->truesize;
2670         dev_kfree_skb_irq(skb);
2671         return -ENOMEM;
2672 }
2673
2674 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2675 {
2676         struct net_device *dev = sp->dev;
2677         int j;
2678         struct sk_buff *skb;
2679         struct RxD_t *rxdp;
2680         struct RxD1 *rxdp1;
2681         struct RxD3 *rxdp3;
2682         struct mac_info *mac_control = &sp->mac_control;
2683         struct stat_block *stats = mac_control->stats_info;
2684         struct swStat *swstats = &stats->sw_stat;
2685
2686         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2687                 rxdp = mac_control->rings[ring_no].
2688                         rx_blocks[blk].rxds[j].virt_addr;
2689                 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2690                 if (!skb)
2691                         continue;
2692                 if (sp->rxd_mode == RXD_MODE_1) {
2693                         rxdp1 = (struct RxD1 *)rxdp;
2694                         pci_unmap_single(sp->pdev,
2695                                          (dma_addr_t)rxdp1->Buffer0_ptr,
2696                                          dev->mtu +
2697                                          HEADER_ETHERNET_II_802_3_SIZE +
2698                                          HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2699                                          PCI_DMA_FROMDEVICE);
2700                         memset(rxdp, 0, sizeof(struct RxD1));
2701                 } else if (sp->rxd_mode == RXD_MODE_3B) {
2702                         rxdp3 = (struct RxD3 *)rxdp;
2703                         pci_unmap_single(sp->pdev,
2704                                          (dma_addr_t)rxdp3->Buffer0_ptr,
2705                                          BUF0_LEN,
2706                                          PCI_DMA_FROMDEVICE);
2707                         pci_unmap_single(sp->pdev,
2708                                          (dma_addr_t)rxdp3->Buffer1_ptr,
2709                                          BUF1_LEN,
2710                                          PCI_DMA_FROMDEVICE);
2711                         pci_unmap_single(sp->pdev,
2712                                          (dma_addr_t)rxdp3->Buffer2_ptr,
2713                                          dev->mtu + 4,
2714                                          PCI_DMA_FROMDEVICE);
2715                         memset(rxdp, 0, sizeof(struct RxD3));
2716                 }
2717                 swstats->mem_freed += skb->truesize;
2718                 dev_kfree_skb(skb);
2719                 mac_control->rings[ring_no].rx_bufs_left -= 1;
2720         }
2721 }
2722
2723 /**
2724  *  free_rx_buffers - Frees all Rx buffers
2725  *  @sp: device private variable.
2726  *  Description:
2727  *  This function will free all Rx buffers allocated by host.
2728  *  Return Value:
2729  *  NONE.
2730  */
2731
2732 static void free_rx_buffers(struct s2io_nic *sp)
2733 {
2734         struct net_device *dev = sp->dev;
2735         int i, blk = 0, buf_cnt = 0;
2736         struct config_param *config = &sp->config;
2737         struct mac_info *mac_control = &sp->mac_control;
2738
2739         for (i = 0; i < config->rx_ring_num; i++) {
2740                 struct ring_info *ring = &mac_control->rings[i];
2741
2742                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2743                         free_rxd_blk(sp, i, blk);
2744
2745                 ring->rx_curr_put_info.block_index = 0;
2746                 ring->rx_curr_get_info.block_index = 0;
2747                 ring->rx_curr_put_info.offset = 0;
2748                 ring->rx_curr_get_info.offset = 0;
2749                 ring->rx_bufs_left = 0;
2750                 DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
2751                           dev->name, buf_cnt, i);
2752         }
2753 }
2754
2755 static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2756 {
2757         if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2758                 DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2759                           ring->dev->name);
2760         }
2761         return 0;
2762 }
2763
2764 /**
2765  * s2io_poll - Rx interrupt handler for NAPI support
2766  * @napi : pointer to the napi structure.
2767  * @budget : The number of packets that were budgeted to be processed
2768  * during  one pass through the 'Poll" function.
2769  * Description:
2770  * Comes into picture only if NAPI support has been incorporated. It does
2771  * the same thing that rx_intr_handler does, but not in a interrupt context
2772  * also It will process only a given number of packets.
2773  * Return value:
2774  * 0 on success and 1 if there are No Rx packets to be processed.
2775  */
2776
2777 static int s2io_poll_msix(struct napi_struct *napi, int budget)
2778 {
2779         struct ring_info *ring = container_of(napi, struct ring_info, napi);
2780         struct net_device *dev = ring->dev;
2781         int pkts_processed = 0;
2782         u8 __iomem *addr = NULL;
2783         u8 val8 = 0;
2784         struct s2io_nic *nic = netdev_priv(dev);
2785         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2786         int budget_org = budget;
2787
2788         if (unlikely(!is_s2io_card_up(nic)))
2789                 return 0;
2790
2791         pkts_processed = rx_intr_handler(ring, budget);
2792         s2io_chk_rx_buffers(nic, ring);
2793
2794         if (pkts_processed < budget_org) {
2795                 napi_complete(napi);
2796                 /*Re Enable MSI-Rx Vector*/
2797                 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2798                 addr += 7 - ring->ring_no;
2799                 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2800                 writeb(val8, addr);
2801                 val8 = readb(addr);
2802         }
2803         return pkts_processed;
2804 }
2805
2806 static int s2io_poll_inta(struct napi_struct *napi, int budget)
2807 {
2808         struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2809         int pkts_processed = 0;
2810         int ring_pkts_processed, i;
2811         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2812         int budget_org = budget;
2813         struct config_param *config = &nic->config;
2814         struct mac_info *mac_control = &nic->mac_control;
2815
2816         if (unlikely(!is_s2io_card_up(nic)))
2817                 return 0;
2818
2819         for (i = 0; i < config->rx_ring_num; i++) {
2820                 struct ring_info *ring = &mac_control->rings[i];
2821                 ring_pkts_processed = rx_intr_handler(ring, budget);
2822                 s2io_chk_rx_buffers(nic, ring);
2823                 pkts_processed += ring_pkts_processed;
2824                 budget -= ring_pkts_processed;
2825                 if (budget <= 0)
2826                         break;
2827         }
2828         if (pkts_processed < budget_org) {
2829                 napi_complete(napi);
2830                 /* Re enable the Rx interrupts for the ring */
2831                 writeq(0, &bar0->rx_traffic_mask);
2832                 readl(&bar0->rx_traffic_mask);
2833         }
2834         return pkts_processed;
2835 }
2836
2837 #ifdef CONFIG_NET_POLL_CONTROLLER
2838 /**
2839  * s2io_netpoll - netpoll event handler entry point
2840  * @dev : pointer to the device structure.
2841  * Description:
2842  *      This function will be called by upper layer to check for events on the
2843  * interface in situations where interrupts are disabled. It is used for
2844  * specific in-kernel networking tasks, such as remote consoles and kernel
2845  * debugging over the network (example netdump in RedHat).
2846  */
2847 static void s2io_netpoll(struct net_device *dev)
2848 {
2849         struct s2io_nic *nic = netdev_priv(dev);
2850         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2851         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2852         int i;
2853         struct config_param *config = &nic->config;
2854         struct mac_info *mac_control = &nic->mac_control;
2855
2856         if (pci_channel_offline(nic->pdev))
2857                 return;
2858
2859         disable_irq(dev->irq);
2860
2861         writeq(val64, &bar0->rx_traffic_int);
2862         writeq(val64, &bar0->tx_traffic_int);
2863
2864         /* we need to free up the transmitted skbufs or else netpoll will
2865          * run out of skbs and will fail and eventually netpoll application such
2866          * as netdump will fail.
2867          */
2868         for (i = 0; i < config->tx_fifo_num; i++)
2869                 tx_intr_handler(&mac_control->fifos[i]);
2870
2871         /* check for received packet and indicate up to network */
2872         for (i = 0; i < config->rx_ring_num; i++) {
2873                 struct ring_info *ring = &mac_control->rings[i];
2874
2875                 rx_intr_handler(ring, 0);
2876         }
2877
2878         for (i = 0; i < config->rx_ring_num; i++) {
2879                 struct ring_info *ring = &mac_control->rings[i];
2880
2881                 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2882                         DBG_PRINT(INFO_DBG,
2883                                   "%s: Out of memory in Rx Netpoll!!\n",
2884                                   dev->name);
2885                         break;
2886                 }
2887         }
2888         enable_irq(dev->irq);
2889 }
2890 #endif
2891
2892 /**
2893  *  rx_intr_handler - Rx interrupt handler
2894  *  @ring_info: per ring structure.
2895  *  @budget: budget for napi processing.
2896  *  Description:
2897  *  If the interrupt is because of a received frame or if the
2898  *  receive ring contains fresh as yet un-processed frames,this function is
2899  *  called. It picks out the RxD at which place the last Rx processing had
2900  *  stopped and sends the skb to the OSM's Rx handler and then increments
2901  *  the offset.
2902  *  Return Value:
2903  *  No. of napi packets processed.
2904  */
2905 static int rx_intr_handler(struct ring_info *ring_data, int budget)
2906 {
2907         int get_block, put_block;
2908         struct rx_curr_get_info get_info, put_info;
2909         struct RxD_t *rxdp;
2910         struct sk_buff *skb;
2911         int pkt_cnt = 0, napi_pkts = 0;
2912         int i;
2913         struct RxD1 *rxdp1;
2914         struct RxD3 *rxdp3;
2915
2916         get_info = ring_data->rx_curr_get_info;
2917         get_block = get_info.block_index;
2918         memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2919         put_block = put_info.block_index;
2920         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2921
2922         while (RXD_IS_UP2DT(rxdp)) {
2923                 /*
2924                  * If your are next to put index then it's
2925                  * FIFO full condition
2926                  */
2927                 if ((get_block == put_block) &&
2928                     (get_info.offset + 1) == put_info.offset) {
2929                         DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2930                                   ring_data->dev->name);
2931                         break;
2932                 }
2933                 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2934                 if (skb == NULL) {
2935                         DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
2936                                   ring_data->dev->name);
2937                         return 0;
2938                 }
2939                 if (ring_data->rxd_mode == RXD_MODE_1) {
2940                         rxdp1 = (struct RxD1 *)rxdp;
2941                         pci_unmap_single(ring_data->pdev, (dma_addr_t)
2942                                          rxdp1->Buffer0_ptr,
2943                                          ring_data->mtu +
2944                                          HEADER_ETHERNET_II_802_3_SIZE +
2945                                          HEADER_802_2_SIZE +
2946                                          HEADER_SNAP_SIZE,
2947                                          PCI_DMA_FROMDEVICE);
2948                 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
2949                         rxdp3 = (struct RxD3 *)rxdp;
2950                         pci_dma_sync_single_for_cpu(ring_data->pdev,
2951                                                     (dma_addr_t)rxdp3->Buffer0_ptr,
2952                                                     BUF0_LEN,
2953                                                     PCI_DMA_FROMDEVICE);
2954                         pci_unmap_single(ring_data->pdev,
2955                                          (dma_addr_t)rxdp3->Buffer2_ptr,
2956                                          ring_data->mtu + 4,
2957                                          PCI_DMA_FROMDEVICE);
2958                 }
2959                 prefetch(skb->data);
2960                 rx_osm_handler(ring_data, rxdp);
2961                 get_info.offset++;
2962                 ring_data->rx_curr_get_info.offset = get_info.offset;
2963                 rxdp = ring_data->rx_blocks[get_block].
2964                         rxds[get_info.offset].virt_addr;
2965                 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
2966                         get_info.offset = 0;
2967                         ring_data->rx_curr_get_info.offset = get_info.offset;
2968                         get_block++;
2969                         if (get_block == ring_data->block_count)
2970                                 get_block = 0;
2971                         ring_data->rx_curr_get_info.block_index = get_block;
2972                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2973                 }
2974
2975                 if (ring_data->nic->config.napi) {
2976                         budget--;
2977                         napi_pkts++;
2978                         if (!budget)
2979                                 break;
2980                 }
2981                 pkt_cnt++;
2982                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2983                         break;
2984         }
2985         if (ring_data->lro) {
2986                 /* Clear all LRO sessions before exiting */
2987                 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
2988                         struct lro *lro = &ring_data->lro0_n[i];
2989                         if (lro->in_use) {
2990                                 update_L3L4_header(ring_data->nic, lro);
2991                                 queue_rx_frame(lro->parent, lro->vlan_tag);
2992                                 clear_lro_session(lro);
2993                         }
2994                 }
2995         }
2996         return napi_pkts;
2997 }
2998
2999 /**
3000  *  tx_intr_handler - Transmit interrupt handler
3001  *  @nic : device private variable
3002  *  Description:
3003  *  If an interrupt was raised to indicate DMA complete of the
3004  *  Tx packet, this function is called. It identifies the last TxD
3005  *  whose buffer was freed and frees all skbs whose data have already
3006  *  DMA'ed into the NICs internal memory.
3007  *  Return Value:
3008  *  NONE
3009  */
3010
3011 static void tx_intr_handler(struct fifo_info *fifo_data)
3012 {
3013         struct s2io_nic *nic = fifo_data->nic;
3014         struct tx_curr_get_info get_info, put_info;
3015         struct sk_buff *skb = NULL;
3016         struct TxD *txdlp;
3017         int pkt_cnt = 0;
3018         unsigned long flags = 0;
3019         u8 err_mask;
3020         struct stat_block *stats = nic->mac_control.stats_info;
3021         struct swStat *swstats = &stats->sw_stat;
3022
3023         if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3024                 return;
3025
3026         get_info = fifo_data->tx_curr_get_info;
3027         memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3028         txdlp = fifo_data->list_info[get_info.offset].list_virt_addr;
3029         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3030                (get_info.offset != put_info.offset) &&
3031                (txdlp->Host_Control)) {
3032                 /* Check for TxD errors */
3033                 if (txdlp->Control_1 & TXD_T_CODE) {
3034                         unsigned long long err;
3035                         err = txdlp->Control_1 & TXD_T_CODE;
3036                         if (err & 0x1) {
3037                                 swstats->parity_err_cnt++;
3038                         }
3039
3040                         /* update t_code statistics */
3041                         err_mask = err >> 48;
3042                         switch (err_mask) {
3043                         case 2:
3044                                 swstats->tx_buf_abort_cnt++;
3045                                 break;
3046
3047                         case 3:
3048                                 swstats->tx_desc_abort_cnt++;
3049                                 break;
3050
3051                         case 7:
3052                                 swstats->tx_parity_err_cnt++;
3053                                 break;
3054
3055                         case 10:
3056                                 swstats->tx_link_loss_cnt++;
3057                                 break;
3058
3059                         case 15:
3060                                 swstats->tx_list_proc_err_cnt++;
3061                                 break;
3062                         }
3063                 }
3064
3065                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3066                 if (skb == NULL) {
3067                         spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3068                         DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3069                                   __func__);
3070                         return;
3071                 }
3072                 pkt_cnt++;
3073
3074                 /* Updating the statistics block */
3075                 swstats->mem_freed += skb->truesize;
3076                 dev_kfree_skb_irq(skb);
3077
3078                 get_info.offset++;
3079                 if (get_info.offset == get_info.fifo_len + 1)
3080                         get_info.offset = 0;
3081                 txdlp = fifo_data->list_info[get_info.offset].list_virt_addr;
3082                 fifo_data->tx_curr_get_info.offset = get_info.offset;
3083         }
3084
3085         s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3086
3087         spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3088 }
3089
3090 /**
3091  *  s2io_mdio_write - Function to write in to MDIO registers
3092  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3093  *  @addr     : address value
3094  *  @value    : data value
3095  *  @dev      : pointer to net_device structure
3096  *  Description:
3097  *  This function is used to write values to the MDIO registers
3098  *  NONE
3099  */
3100 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3101                             struct net_device *dev)
3102 {
3103         u64 val64;
3104         struct s2io_nic *sp = netdev_priv(dev);
3105         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3106
3107         /* address transaction */
3108         val64 = MDIO_MMD_INDX_ADDR(addr) |
3109                 MDIO_MMD_DEV_ADDR(mmd_type) |
3110                 MDIO_MMS_PRT_ADDR(0x0);
3111         writeq(val64, &bar0->mdio_control);
3112         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3113         writeq(val64, &bar0->mdio_control);
3114         udelay(100);
3115
3116         /* Data transaction */
3117         val64 = MDIO_MMD_INDX_ADDR(addr) |
3118                 MDIO_MMD_DEV_ADDR(mmd_type) |
3119                 MDIO_MMS_PRT_ADDR(0x0) |
3120                 MDIO_MDIO_DATA(value) |
3121                 MDIO_OP(MDIO_OP_WRITE_TRANS);
3122         writeq(val64, &bar0->mdio_control);
3123         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3124         writeq(val64, &bar0->mdio_control);
3125         udelay(100);
3126
3127         val64 = MDIO_MMD_INDX_ADDR(addr) |
3128                 MDIO_MMD_DEV_ADDR(mmd_type) |
3129                 MDIO_MMS_PRT_ADDR(0x0) |
3130                 MDIO_OP(MDIO_OP_READ_TRANS);
3131         writeq(val64, &bar0->mdio_control);
3132         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3133         writeq(val64, &bar0->mdio_control);
3134         udelay(100);
3135 }
3136
3137 /**
3138  *  s2io_mdio_read - Function to write in to MDIO registers
3139  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3140  *  @addr     : address value
3141  *  @dev      : pointer to net_device structure
3142  *  Description:
3143  *  This function is used to read values to the MDIO registers
3144  *  NONE
3145  */
3146 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3147 {
3148         u64 val64 = 0x0;
3149         u64 rval64 = 0x0;
3150         struct s2io_nic *sp = netdev_priv(dev);
3151         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3152
3153         /* address transaction */
3154         val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3155                          | MDIO_MMD_DEV_ADDR(mmd_type)
3156                          | MDIO_MMS_PRT_ADDR(0x0));
3157         writeq(val64, &bar0->mdio_control);
3158         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3159         writeq(val64, &bar0->mdio_control);
3160         udelay(100);
3161
3162         /* Data transaction */
3163         val64 = MDIO_MMD_INDX_ADDR(addr) |
3164                 MDIO_MMD_DEV_ADDR(mmd_type) |
3165                 MDIO_MMS_PRT_ADDR(0x0) |
3166                 MDIO_OP(MDIO_OP_READ_TRANS);
3167         writeq(val64, &bar0->mdio_control);
3168         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3169         writeq(val64, &bar0->mdio_control);
3170         udelay(100);
3171
3172         /* Read the value from regs */
3173         rval64 = readq(&bar0->mdio_control);
3174         rval64 = rval64 & 0xFFFF0000;
3175         rval64 = rval64 >> 16;
3176         return rval64;
3177 }
3178
3179 /**
3180  *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
3181  *  @counter      : counter value to be updated
3182  *  @flag         : flag to indicate the status
3183  *  @type         : counter type
3184  *  Description:
3185  *  This function is to check the status of the xpak counters value
3186  *  NONE
3187  */
3188
3189 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3190                                   u16 flag, u16 type)
3191 {
3192         u64 mask = 0x3;
3193         u64 val64;
3194         int i;
3195         for (i = 0; i < index; i++)
3196                 mask = mask << 0x2;
3197
3198         if (flag > 0) {
3199                 *counter = *counter + 1;
3200                 val64 = *regs_stat & mask;
3201                 val64 = val64 >> (index * 0x2);
3202                 val64 = val64 + 1;
3203                 if (val64 == 3) {
3204                         switch (type) {
3205                         case 1:
3206                                 DBG_PRINT(ERR_DBG,
3207                                           "Take Xframe NIC out of service.\n");
3208                                 DBG_PRINT(ERR_DBG,
3209 "Excessive temperatures may result in premature transceiver failure.\n");
3210                                 break;
3211                         case 2:
3212                                 DBG_PRINT(ERR_DBG,
3213                                           "Take Xframe NIC out of service.\n");
3214                                 DBG_PRINT(ERR_DBG,
3215 "Excessive bias currents may indicate imminent laser diode failure.\n");
3216                                 break;
3217                         case 3:
3218                                 DBG_PRINT(ERR_DBG,
3219                                           "Take Xframe NIC out of service.\n");
3220                                 DBG_PRINT(ERR_DBG,
3221 "Excessive laser output power may saturate far-end receiver.\n");
3222                                 break;
3223                         default:
3224                                 DBG_PRINT(ERR_DBG,
3225                                           "Incorrect XPAK Alarm type\n");
3226                         }
3227                         val64 = 0x0;
3228                 }
3229                 val64 = val64 << (index * 0x2);
3230                 *regs_stat = (*regs_stat & (~mask)) | (val64);
3231
3232         } else {
3233                 *regs_stat = *regs_stat & (~mask);
3234         }
3235 }
3236
3237 /**
3238  *  s2io_updt_xpak_counter - Function to update the xpak counters
3239  *  @dev         : pointer to net_device struct
3240  *  Description:
3241  *  This function is to upate the status of the xpak counters value
3242  *  NONE
3243  */
3244 static void s2io_updt_xpak_counter(struct net_device *dev)
3245 {
3246         u16 flag  = 0x0;
3247         u16 type  = 0x0;
3248         u16 val16 = 0x0;
3249         u64 val64 = 0x0;
3250         u64 addr  = 0x0;
3251
3252         struct s2io_nic *sp = netdev_priv(dev);
3253         struct stat_block *stats = sp->mac_control.stats_info;
3254         struct xpakStat *xstats = &stats->xpak_stat;
3255
3256         /* Check the communication with the MDIO slave */
3257         addr = MDIO_CTRL1;
3258         val64 = 0x0;
3259         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3260         if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
3261                 DBG_PRINT(ERR_DBG,
3262                           "ERR: MDIO slave access failed - Returned %llx\n",
3263                           (unsigned long long)val64);
3264                 return;
3265         }
3266
3267         /* Check for the expected value of control reg 1 */
3268         if (val64 != MDIO_CTRL1_SPEED10G) {
3269                 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3270                           "Returned: %llx- Expected: 0x%x\n",
3271                           (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
3272                 return;
3273         }
3274
3275         /* Loading the DOM register to MDIO register */
3276         addr = 0xA100;
3277         s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3278         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3279
3280         /* Reading the Alarm flags */
3281         addr = 0xA070;
3282         val64 = 0x0;
3283         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3284
3285         flag = CHECKBIT(val64, 0x7);
3286         type = 1;
3287         s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3288                               &xstats->xpak_regs_stat,
3289                               0x0, flag, type);
3290
3291         if (CHECKBIT(val64, 0x6))
3292                 xstats->alarm_transceiver_temp_low++;
3293
3294         flag = CHECKBIT(val64, 0x3);
3295         type = 2;
3296         s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3297                               &xstats->xpak_regs_stat,
3298                               0x2, flag, type);
3299
3300         if (CHECKBIT(val64, 0x2))
3301                 xstats->alarm_laser_bias_current_low++;
3302
3303         flag = CHECKBIT(val64, 0x1);
3304         type = 3;
3305         s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3306                               &xstats->xpak_regs_stat,
3307                               0x4, flag, type);
3308
3309         if (CHECKBIT(val64, 0x0))
3310                 xstats->alarm_laser_output_power_low++;
3311
3312         /* Reading the Warning flags */
3313         addr = 0xA074;
3314         val64 = 0x0;
3315         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3316
3317         if (CHECKBIT(val64, 0x7))
3318                 xstats->warn_transceiver_temp_high++;
3319
3320         if (CHECKBIT(val64, 0x6))
3321                 xstats->warn_transceiver_temp_low++;
3322
3323         if (CHECKBIT(val64, 0x3))
3324                 xstats->warn_laser_bias_current_high++;
3325
3326         if (CHECKBIT(val64, 0x2))
3327                 xstats->warn_laser_bias_current_low++;
3328
3329         if (CHECKBIT(val64, 0x1))
3330                 xstats->warn_laser_output_power_high++;
3331
3332         if (CHECKBIT(val64, 0x0))
3333                 xstats->warn_laser_output_power_low++;
3334 }
3335
3336 /**
3337  *  wait_for_cmd_complete - waits for a command to complete.
3338  *  @sp : private member of the device structure, which is a pointer to the
3339  *  s2io_nic structure.
3340  *  Description: Function that waits for a command to Write into RMAC
3341  *  ADDR DATA registers to be completed and returns either success or
3342  *  error depending on whether the command was complete or not.
3343  *  Return value:
3344  *   SUCCESS on success and FAILURE on failure.
3345  */
3346
3347 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3348                                  int bit_state)
3349 {
3350         int ret = FAILURE, cnt = 0, delay = 1;
3351         u64 val64;
3352
3353         if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3354                 return FAILURE;
3355
3356         do {
3357                 val64 = readq(addr);
3358                 if (bit_state == S2IO_BIT_RESET) {
3359                         if (!(val64 & busy_bit)) {
3360                                 ret = SUCCESS;
3361                                 break;
3362                         }
3363                 } else {
3364                         if (val64 & busy_bit) {
3365                                 ret = SUCCESS;
3366                                 break;
3367                         }
3368                 }
3369
3370                 if (in_interrupt())
3371                         mdelay(delay);
3372                 else
3373                         msleep(delay);
3374
3375                 if (++cnt >= 10)
3376                         delay = 50;
3377         } while (cnt < 20);
3378         return ret;
3379 }
3380 /*
3381  * check_pci_device_id - Checks if the device id is supported
3382  * @id : device id
3383  * Description: Function to check if the pci device id is supported by driver.
3384  * Return value: Actual device id if supported else PCI_ANY_ID
3385  */
3386 static u16 check_pci_device_id(u16 id)
3387 {
3388         switch (id) {
3389         case PCI_DEVICE_ID_HERC_WIN:
3390         case PCI_DEVICE_ID_HERC_UNI:
3391                 return XFRAME_II_DEVICE;
3392         case PCI_DEVICE_ID_S2IO_UNI:
3393         case PCI_DEVICE_ID_S2IO_WIN:
3394                 return XFRAME_I_DEVICE;
3395         default:
3396                 return PCI_ANY_ID;
3397         }
3398 }
3399
3400 /**
3401  *  s2io_reset - Resets the card.
3402  *  @sp : private member of the device structure.
3403  *  Description: Function to Reset the card. This function then also
3404  *  restores the previously saved PCI configuration space registers as
3405  *  the card reset also resets the configuration space.
3406  *  Return value:
3407  *  void.
3408  */
3409
3410 static void s2io_reset(struct s2io_nic *sp)
3411 {
3412         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3413         u64 val64;
3414         u16 subid, pci_cmd;
3415         int i;
3416         u16 val16;
3417         unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3418         unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3419         struct stat_block *stats;
3420         struct swStat *swstats;
3421
3422         DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3423                   __func__, pci_name(sp->pdev));
3424
3425         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3426         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3427
3428         val64 = SW_RESET_ALL;
3429         writeq(val64, &bar0->sw_reset);
3430         if (strstr(sp->product_name, "CX4"))
3431                 msleep(750);
3432         msleep(250);
3433         for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3434
3435                 /* Restore the PCI state saved during initialization. */
3436                 pci_restore_state(sp->pdev);
3437                 pci_save_state(sp->pdev);
3438                 pci_read_config_word(sp->pdev, 0x2, &val16);
3439                 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3440                         break;
3441                 msleep(200);
3442         }
3443
3444         if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3445                 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
3446
3447         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3448
3449         s2io_init_pci(sp);
3450
3451         /* Set swapper to enable I/O register access */
3452         s2io_set_swapper(sp);
3453
3454         /* restore mac_addr entries */
3455         do_s2io_restore_unicast_mc(sp);
3456
3457         /* Restore the MSIX table entries from local variables */
3458         restore_xmsi_data(sp);
3459
3460         /* Clear certain PCI/PCI-X fields after reset */
3461         if (sp->device_type == XFRAME_II_DEVICE) {
3462                 /* Clear "detected parity error" bit */
3463                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3464
3465                 /* Clearing PCIX Ecc status register */
3466                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3467
3468                 /* Clearing PCI_STATUS error reflected here */
3469                 writeq(s2BIT(62), &bar0->txpic_int_reg);
3470         }
3471
3472         /* Reset device statistics maintained by OS */
3473         memset(&sp->stats, 0, sizeof(struct net_device_stats));
3474
3475         stats = sp->mac_control.stats_info;
3476         swstats = &stats->sw_stat;
3477
3478         /* save link up/down time/cnt, reset/memory/watchdog cnt */
3479         up_cnt = swstats->link_up_cnt;
3480         down_cnt = swstats->link_down_cnt;
3481         up_time = swstats->link_up_time;
3482         down_time = swstats->link_down_time;
3483         reset_cnt = swstats->soft_reset_cnt;
3484         mem_alloc_cnt = swstats->mem_allocated;
3485         mem_free_cnt = swstats->mem_freed;
3486         watchdog_cnt = swstats->watchdog_timer_cnt;
3487
3488         memset(stats, 0, sizeof(struct stat_block));
3489
3490         /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3491         swstats->link_up_cnt = up_cnt;
3492         swstats->link_down_cnt = down_cnt;
3493         swstats->link_up_time = up_time;
3494         swstats->link_down_time = down_time;
3495         swstats->soft_reset_cnt = reset_cnt;
3496         swstats->mem_allocated = mem_alloc_cnt;
3497         swstats->mem_freed = mem_free_cnt;
3498         swstats->watchdog_timer_cnt = watchdog_cnt;
3499
3500         /* SXE-002: Configure link and activity LED to turn it off */
3501         subid = sp->pdev->subsystem_device;
3502         if (((subid & 0xFF) >= 0x07) &&
3503             (sp->device_type == XFRAME_I_DEVICE)) {
3504                 val64 = readq(&bar0->gpio_control);
3505                 val64 |= 0x0000800000000000ULL;
3506                 writeq(val64, &bar0->gpio_control);
3507                 val64 = 0x0411040400000000ULL;
3508                 writeq(val64, (void __iomem *)bar0 + 0x2700);
3509         }
3510
3511         /*
3512          * Clear spurious ECC interrupts that would have occurred on
3513          * XFRAME II cards after reset.
3514          */
3515         if (sp->device_type == XFRAME_II_DEVICE) {
3516                 val64 = readq(&bar0->pcc_err_reg);
3517                 writeq(val64, &bar0->pcc_err_reg);
3518         }
3519
3520         sp->device_enabled_once = false;
3521 }
3522
3523 /**
3524  *  s2io_set_swapper - to set the swapper controle on the card
3525  *  @sp : private member of the device structure,
3526  *  pointer to the s2io_nic structure.
3527  *  Description: Function to set the swapper control on the card
3528  *  correctly depending on the 'endianness' of the system.
3529  *  Return value:
3530  *  SUCCESS on success and FAILURE on failure.
3531  */
3532
3533 static int s2io_set_swapper(struct s2io_nic *sp)
3534 {
3535         struct net_device *dev = sp->dev;
3536         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3537         u64 val64, valt, valr;
3538
3539         /*
3540          * Set proper endian settings and verify the same by reading
3541          * the PIF Feed-back register.
3542          */
3543
3544         val64 = readq(&bar0->pif_rd_swapper_fb);
3545         if (val64 != 0x0123456789ABCDEFULL) {
3546                 int i = 0;
3547                 static const u64 value[] = {
3548                         0xC30000C3C30000C3ULL,  /* FE=1, SE=1 */
3549                         0x8100008181000081ULL,  /* FE=1, SE=0 */
3550                         0x4200004242000042ULL,  /* FE=0, SE=1 */
3551                         0                       /* FE=0, SE=0 */
3552                 };
3553
3554                 while (i < 4) {
3555                         writeq(value[i], &bar0->swapper_ctrl);
3556                         val64 = readq(&bar0->pif_rd_swapper_fb);
3557                         if (val64 == 0x0123456789ABCDEFULL)
3558                                 break;
3559                         i++;
3560                 }
3561                 if (i == 4) {
3562                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3563                                   "feedback read %llx\n",
3564                                   dev->name, (unsigned long long)val64);
3565                         return FAILURE;
3566                 }
3567                 valr = value[i];
3568         } else {
3569                 valr = readq(&bar0->swapper_ctrl);
3570         }
3571
3572         valt = 0x0123456789ABCDEFULL;
3573         writeq(valt, &bar0->xmsi_address);
3574         val64 = readq(&bar0->xmsi_address);
3575
3576         if (val64 != valt) {
3577                 int i = 0;
3578                 static const u64 value[] = {
3579                         0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
3580                         0x0081810000818100ULL,  /* FE=1, SE=0 */
3581                         0x0042420000424200ULL,  /* FE=0, SE=1 */
3582                         0                       /* FE=0, SE=0 */
3583                 };
3584
3585                 while (i < 4) {
3586                         writeq((value[i] | valr), &bar0->swapper_ctrl);
3587                         writeq(valt, &bar0->xmsi_address);
3588                         val64 = readq(&bar0->xmsi_address);
3589                         if (val64 == valt)
3590                                 break;
3591                         i++;
3592                 }
3593                 if (i == 4) {
3594                         unsigned long long x = val64;
3595                         DBG_PRINT(ERR_DBG,
3596                                   "Write failed, Xmsi_addr reads:0x%llx\n", x);
3597                         return FAILURE;
3598                 }
3599         }
3600         val64 = readq(&bar0->swapper_ctrl);
3601         val64 &= 0xFFFF000000000000ULL;
3602
3603 #ifdef __BIG_ENDIAN
3604         /*
3605          * The device by default set to a big endian format, so a
3606          * big endian driver need not set anything.
3607          */
3608         val64 |= (SWAPPER_CTRL_TXP_FE |
3609                   SWAPPER_CTRL_TXP_SE |
3610                   SWAPPER_CTRL_TXD_R_FE |
3611                   SWAPPER_CTRL_TXD_W_FE |
3612                   SWAPPER_CTRL_TXF_R_FE |
3613                   SWAPPER_CTRL_RXD_R_FE |
3614                   SWAPPER_CTRL_RXD_W_FE |
3615                   SWAPPER_CTRL_RXF_W_FE |
3616                   SWAPPER_CTRL_XMSI_FE |
3617                   SWAPPER_CTRL_STATS_FE |
3618                   SWAPPER_CTRL_STATS_SE);
3619         if (sp->config.intr_type == INTA)
3620                 val64 |= SWAPPER_CTRL_XMSI_SE;
3621         writeq(val64, &bar0->swapper_ctrl);
3622 #else
3623         /*
3624          * Initially we enable all bits to make it accessible by the
3625          * driver, then we selectively enable only those bits that
3626          * we want to set.
3627          */
3628         val64 |= (SWAPPER_CTRL_TXP_FE |
3629                   SWAPPER_CTRL_TXP_SE |
3630                   SWAPPER_CTRL_TXD_R_FE |
3631                   SWAPPER_CTRL_TXD_R_SE |
3632                   SWAPPER_CTRL_TXD_W_FE |
3633                   SWAPPER_CTRL_TXD_W_SE |
3634                   SWAPPER_CTRL_TXF_R_FE |
3635                   SWAPPER_CTRL_RXD_R_FE |
3636                   SWAPPER_CTRL_RXD_R_SE |
3637                   SWAPPER_CTRL_RXD_W_FE |
3638                   SWAPPER_CTRL_RXD_W_SE |
3639                   SWAPPER_CTRL_RXF_W_FE |
3640                   SWAPPER_CTRL_XMSI_FE |
3641                   SWAPPER_CTRL_STATS_FE |
3642                   SWAPPER_CTRL_STATS_SE);
3643         if (sp->config.intr_type == INTA)
3644                 val64 |= SWAPPER_CTRL_XMSI_SE;
3645         writeq(val64, &bar0->swapper_ctrl);
3646 #endif
3647         val64 = readq(&bar0->swapper_ctrl);
3648
3649         /*
3650          * Verifying if endian settings are accurate by reading a
3651          * feedback register.
3652          */
3653         val64 = readq(&bar0->pif_rd_swapper_fb);
3654         if (val64 != 0x0123456789ABCDEFULL) {
3655                 /* Endian settings are incorrect, calls for another dekko. */
3656                 DBG_PRINT(ERR_DBG,
3657                           "%s: Endian settings are wrong, feedback read %llx\n",
3658                           dev->name, (unsigned long long)val64);
3659                 return FAILURE;
3660         }
3661
3662         return SUCCESS;
3663 }
3664
3665 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3666 {
3667         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3668         u64 val64;
3669         int ret = 0, cnt = 0;
3670
3671         do {
3672                 val64 = readq(&bar0->xmsi_access);
3673                 if (!(val64 & s2BIT(15)))
3674                         break;
3675                 mdelay(1);
3676                 cnt++;
3677         } while (cnt < 5);
3678         if (cnt == 5) {
3679                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3680                 ret = 1;
3681         }
3682
3683         return ret;
3684 }
3685
3686 static void restore_xmsi_data(struct s2io_nic *nic)
3687 {
3688         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3689         u64 val64;
3690         int i, msix_index;
3691
3692         if (nic->device_type == XFRAME_I_DEVICE)
3693                 return;
3694
3695         for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3696                 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3697                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3698                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3699                 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3700                 writeq(val64, &bar0->xmsi_access);
3701                 if (wait_for_msix_trans(nic, msix_index)) {
3702                         DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3703                                   __func__, msix_index);
3704                         continue;
3705                 }
3706         }
3707 }
3708
3709 static void store_xmsi_data(struct s2io_nic *nic)
3710 {
3711         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3712         u64 val64, addr, data;
3713         int i, msix_index;
3714
3715         if (nic->device_type == XFRAME_I_DEVICE)
3716                 return;
3717
3718         /* Store and display */
3719         for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3720                 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3721                 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3722                 writeq(val64, &bar0->xmsi_access);
3723                 if (wait_for_msix_trans(nic, msix_index)) {
3724                         DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3725                                   __func__, msix_index);
3726                         continue;
3727                 }
3728                 addr = readq(&bar0->xmsi_address);
3729                 data = readq(&bar0->xmsi_data);
3730                 if (addr && data) {
3731                         nic->msix_info[i].addr = addr;
3732                         nic->msix_info[i].data = data;
3733                 }
3734         }
3735 }
3736
3737 static int s2io_enable_msi_x(struct s2io_nic *nic)
3738 {
3739         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3740         u64 rx_mat;
3741         u16 msi_control; /* Temp variable */
3742         int ret, i, j, msix_indx = 1;
3743         int size;
3744         struct stat_block *stats = nic->mac_control.stats_info;
3745         struct swStat *swstats = &stats->sw_stat;
3746
3747         size = nic->num_entries * sizeof(struct msix_entry);
3748         nic->entries = kzalloc(size, GFP_KERNEL);
3749         if (!nic->entries) {
3750                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3751                           __func__);
3752                 swstats->mem_alloc_fail_cnt++;
3753                 return -ENOMEM;
3754         }
3755         swstats->mem_allocated += size;
3756
3757         size = nic->num_entries * sizeof(struct s2io_msix_entry);
3758         nic->s2io_entries = kzalloc(size, GFP_KERNEL);
3759         if (!nic->s2io_entries) {
3760                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3761                           __func__);
3762                 swstats->mem_alloc_fail_cnt++;
3763                 kfree(nic->entries);
3764                 swstats->mem_freed
3765                         += (nic->num_entries * sizeof(struct msix_entry));
3766                 return -ENOMEM;
3767         }
3768         swstats->mem_allocated += size;
3769
3770         nic->entries[0].entry = 0;
3771         nic->s2io_entries[0].entry = 0;
3772         nic->s2io_entries[0].in_use = MSIX_FLG;
3773         nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3774         nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3775
3776         for (i = 1; i < nic->num_entries; i++) {
3777                 nic->entries[i].entry = ((i - 1) * 8) + 1;
3778                 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3779                 nic->s2io_entries[i].arg = NULL;
3780                 nic->s2io_entries[i].in_use = 0;
3781         }
3782
3783         rx_mat = readq(&bar0->rx_mat);
3784         for (j = 0; j < nic->config.rx_ring_num; j++) {
3785                 rx_mat |= RX_MAT_SET(j, msix_indx);
3786                 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3787                 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3788                 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3789                 msix_indx += 8;
3790         }
3791         writeq(rx_mat, &bar0->rx_mat);
3792         readq(&bar0->rx_mat);
3793
3794         ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
3795         /* We fail init if error or we get less vectors than min required */
3796         if (ret) {
3797                 DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
3798                 kfree(nic->entries);
3799                 swstats->mem_freed += nic->num_entries *
3800                         sizeof(struct msix_entry);
3801                 kfree(nic->s2io_entries);
3802                 swstats->mem_freed += nic->num_entries *
3803                         sizeof(struct s2io_msix_entry);
3804                 nic->entries = NULL;
3805                 nic->s2io_entries = NULL;
3806                 return -ENOMEM;
3807         }
3808
3809         /*
3810          * To enable MSI-X, MSI also needs to be enabled, due to a bug
3811          * in the herc NIC. (Temp change, needs to be removed later)
3812          */
3813         pci_read_config_word(nic->pdev, 0x42, &msi_control);
3814         msi_control |= 0x1; /* Enable MSI */
3815         pci_write_config_word(nic->pdev, 0x42, msi_control);
3816
3817         return 0;
3818 }
3819
3820 /* Handle software interrupt used during MSI(X) test */
3821 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3822 {
3823         struct s2io_nic *sp = dev_id;
3824
3825         sp->msi_detected = 1;
3826         wake_up(&sp->msi_wait);
3827
3828         return IRQ_HANDLED;
3829 }
3830
3831 /* Test interrupt path by forcing a a software IRQ */
3832 static int s2io_test_msi(struct s2io_nic *sp)
3833 {
3834         struct pci_dev *pdev = sp->pdev;
3835         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3836         int err;
3837         u64 val64, saved64;
3838
3839         err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3840                           sp->name, sp);
3841         if (err) {
3842                 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3843                           sp->dev->name, pci_name(pdev), pdev->irq);
3844                 return err;
3845         }
3846
3847         init_waitqueue_head(&sp->msi_wait);
3848         sp->msi_detected = 0;
3849
3850         saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3851         val64 |= SCHED_INT_CTRL_ONE_SHOT;
3852         val64 |= SCHED_INT_CTRL_TIMER_EN;
3853         val64 |= SCHED_INT_CTRL_INT2MSI(1);
3854         writeq(val64, &bar0->scheduled_int_ctrl);
3855
3856         wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3857
3858         if (!sp->msi_detected) {
3859                 /* MSI(X) test failed, go back to INTx mode */
3860                 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3861                           "using MSI(X) during test\n",
3862                           sp->dev->name, pci_name(pdev));
3863
3864                 err = -EOPNOTSUPP;
3865         }
3866
3867         free_irq(sp->entries[1].vector, sp);
3868
3869         writeq(saved64, &bar0->scheduled_int_ctrl);
3870
3871         return err;
3872 }
3873
3874 static void remove_msix_isr(struct s2io_nic *sp)
3875 {
3876         int i;
3877         u16 msi_control;
3878
3879         for (i = 0; i < sp->num_entries; i++) {
3880                 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
3881                         int vector = sp->entries[i].vector;
3882                         void *arg = sp->s2io_entries[i].arg;
3883                         free_irq(vector, arg);
3884                 }
3885         }
3886
3887         kfree(sp->entries);
3888         kfree(sp->s2io_entries);
3889         sp->entries = NULL;
3890         sp->s2io_entries = NULL;
3891
3892         pci_read_config_word(sp->pdev, 0x42, &msi_control);
3893         msi_control &= 0xFFFE; /* Disable MSI */
3894         pci_write_config_word(sp->pdev, 0x42, msi_control);
3895
3896         pci_disable_msix(sp->pdev);
3897 }
3898
3899 static void remove_inta_isr(struct s2io_nic *sp)
3900 {
3901         struct net_device *dev = sp->dev;
3902
3903         free_irq(sp->pdev->irq, dev);
3904 }
3905
3906 /* ********************************************************* *
3907  * Functions defined below concern the OS part of the driver *
3908  * ********************************************************* */
3909
3910 /**
3911  *  s2io_open - open entry point of the driver
3912  *  @dev : pointer to the device structure.
3913  *  Description:
3914  *  This function is the open entry point of the driver. It mainly calls a
3915  *  function to allocate Rx buffers and inserts them into the buffer
3916  *  descriptors and then enables the Rx part of the NIC.
3917  *  Return value:
3918  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3919  *   file on failure.
3920  */
3921
3922 static int s2io_open(struct net_device *dev)
3923 {
3924         struct s2io_nic *sp = netdev_priv(dev);
3925         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
3926         int err = 0;
3927
3928         /*
3929          * Make sure you have link off by default every time
3930          * Nic is initialized
3931          */
3932         netif_carrier_off(dev);
3933         sp->last_link_state = 0;
3934
3935         /* Initialize H/W and enable interrupts */
3936         err = s2io_card_up(sp);
3937         if (err) {
3938                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3939                           dev->name);
3940                 goto hw_init_failed;
3941         }
3942
3943         if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
3944                 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3945                 s2io_card_down(sp);
3946                 err = -ENODEV;
3947                 goto hw_init_failed;
3948         }
3949         s2io_start_all_tx_queue(sp);
3950         return 0;
3951
3952 hw_init_failed:
3953         if (sp->config.intr_type == MSI_X) {
3954                 if (sp->entries) {
3955                         kfree(sp->entries);
3956                         swstats->mem_freed += sp->num_entries *
3957                                 sizeof(struct msix_entry);
3958                 }
3959                 if (sp->s2io_entries) {
3960                         kfree(sp->s2io_entries);
3961                         swstats->mem_freed += sp->num_entries *
3962                                 sizeof(struct s2io_msix_entry);
3963                 }
3964         }
3965         return err;
3966 }
3967
3968 /**
3969  *  s2io_close -close entry point of the driver
3970  *  @dev : device pointer.
3971  *  Description:
3972  *  This is the stop entry point of the driver. It needs to undo exactly
3973  *  whatever was done by the open entry point,thus it's usually referred to
3974  *  as the close function.Among other things this function mainly stops the
3975  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3976  *  Return value:
3977  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3978  *  file on failure.
3979  */
3980
3981 static int s2io_close(struct net_device *dev)
3982 {
3983         struct s2io_nic *sp = netdev_priv(dev);
3984         struct config_param *config = &sp->config;
3985         u64 tmp64;
3986         int offset;
3987
3988         /* Return if the device is already closed               *
3989          *  Can happen when s2io_card_up failed in change_mtu    *
3990          */
3991         if (!is_s2io_card_up(sp))
3992                 return 0;
3993
3994         s2io_stop_all_tx_queue(sp);
3995         /* delete all populated mac entries */
3996         for (offset = 1; offset < config->max_mc_addr; offset++) {
3997                 tmp64 = do_s2io_read_unicast_mc(sp, offset);
3998                 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
3999                         do_s2io_delete_unicast_mc(sp, tmp64);
4000         }
4001
4002         s2io_card_down(sp);
4003
4004         return 0;
4005 }
4006
4007 /**
4008  *  s2io_xmit - Tx entry point of te driver
4009  *  @skb : the socket buffer containing the Tx data.
4010  *  @dev : device pointer.
4011  *  Description :
4012  *  This function is the Tx entry point of the driver. S2IO NIC supports
4013  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
4014  *  NOTE: when device can't queue the pkt,just the trans_start variable will
4015  *  not be upadted.
4016  *  Return value:
4017  *  0 on success & 1 on failure.
4018  */
4019
4020 static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4021 {
4022         struct s2io_nic *sp = netdev_priv(dev);
4023         u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4024         register u64 val64;
4025         struct TxD *txdp;
4026         struct TxFIFO_element __iomem *tx_fifo;
4027         unsigned long flags = 0;
4028         u16 vlan_tag = 0;
4029         struct fifo_info *fifo = NULL;
4030         int do_spin_lock = 1;
4031         int offload_type;
4032         int enable_per_list_interrupt = 0;
4033         struct config_param *config = &sp->config;
4034         struct mac_info *mac_control = &sp->mac_control;
4035         struct stat_block *stats = mac_control->stats_info;
4036         struct swStat *swstats = &stats->sw_stat;
4037
4038         DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4039
4040         if (unlikely(skb->len <= 0)) {
4041                 DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
4042                 dev_kfree_skb_any(skb);
4043                 return NETDEV_TX_OK;
4044         }
4045
4046         if (!is_s2io_card_up(sp)) {
4047                 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4048                           dev->name);
4049                 dev_kfree_skb(skb);
4050                 return NETDEV_TX_OK;
4051         }
4052
4053         queue = 0;
4054         if (vlan_tx_tag_present(skb))
4055                 vlan_tag = vlan_tx_tag_get(skb);
4056         if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4057                 if (skb->protocol == htons(ETH_P_IP)) {
4058                         struct iphdr *ip;
4059                         struct tcphdr *th;
4060                         ip = ip_hdr(skb);
4061
4062                         if (!ip_is_fragment(ip)) {
4063                                 th = (struct tcphdr *)(((unsigned char *)ip) +
4064                                                        ip->ihl*4);
4065
4066                                 if (ip->protocol == IPPROTO_TCP) {
4067                                         queue_len = sp->total_tcp_fifos;
4068                                         queue = (ntohs(th->source) +
4069                                                  ntohs(th->dest)) &
4070                                                 sp->fifo_selector[queue_len - 1];
4071                                         if (queue >= queue_len)
4072                                                 queue = queue_len - 1;
4073                                 } else if (ip->protocol == IPPROTO_UDP) {
4074                                         queue_len = sp->total_udp_fifos;
4075                                         queue = (ntohs(th->source) +
4076                                                  ntohs(th->dest)) &
4077                                                 sp->fifo_selector[queue_len - 1];
4078                                         if (queue >= queue_len)
4079                                                 queue = queue_len - 1;
4080                                         queue += sp->udp_fifo_idx;
4081                                         if (skb->len > 1024)
4082                                                 enable_per_list_interrupt = 1;
4083                                         do_spin_lock = 0;
4084                                 }
4085                         }
4086                 }
4087         } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4088                 /* get fifo number based on skb->priority value */
4089                 queue = config->fifo_mapping
4090                         [skb->priority & (MAX_TX_FIFOS - 1)];
4091         fifo = &mac_control->fifos[queue];
4092
4093         if (do_spin_lock)
4094                 spin_lock_irqsave(&fifo->tx_lock, flags);
4095         else {
4096                 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4097                         return NETDEV_TX_LOCKED;
4098         }
4099
4100         if (sp->config.multiq) {
4101                 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4102                         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4103                         return NETDEV_TX_BUSY;
4104                 }
4105         } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4106                 if (netif_queue_stopped(dev)) {
4107                         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4108                         return NETDEV_TX_BUSY;
4109                 }
4110         }
4111
4112         put_off = (u16)fifo->tx_curr_put_info.offset;
4113         get_off = (u16)fifo->tx_curr_get_info.offset;
4114         txdp = fifo->list_info[put_off].list_virt_addr;
4115
4116         queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4117         /* Avoid "put" pointer going beyond "get" pointer */
4118         if (txdp->Host_Control ||
4119             ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4120                 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4121                 s2io_stop_tx_queue(sp, fifo->fifo_no);
4122                 dev_kfree_skb(skb);
4123                 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4124                 return NETDEV_TX_OK;
4125         }
4126
4127         offload_type = s2io_offload_type(skb);
4128         if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4129                 txdp->Control_1 |= TXD_TCP_LSO_EN;
4130                 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4131         }
4132         if (skb->ip_summed == CHECKSUM_PARTIAL) {
4133                 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4134                                     TXD_TX_CKO_TCP_EN |
4135                                     TXD_TX_CKO_UDP_EN);
4136         }
4137         txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4138         txdp->Control_1 |= TXD_LIST_OWN_XENA;
4139         txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4140         if (enable_per_list_interrupt)
4141                 if (put_off & (queue_len >> 5))
4142                         txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4143         if (vlan_tag) {
4144                 txdp->Control_2 |= TXD_VLAN_ENABLE;
4145                 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4146         }
4147
4148         frg_len = skb_headlen(skb);
4149         if (offload_type == SKB_GSO_UDP) {
4150                 int ufo_size;
4151
4152                 ufo_size = s2io_udp_mss(skb);
4153                 ufo_size &= ~7;
4154                 txdp->Control_1 |= TXD_UFO_EN;
4155                 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4156                 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4157 #ifdef __BIG_ENDIAN
4158                 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4159                 fifo->ufo_in_band_v[put_off] =
4160                         (__force u64)skb_shinfo(skb)->ip6_frag_id;
4161 #else
4162                 fifo->ufo_in_band_v[put_off] =
4163                         (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
4164 #endif
4165                 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4166                 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4167                                                       fifo->ufo_in_band_v,
4168                                                       sizeof(u64),
4169                                                       PCI_DMA_TODEVICE);
4170                 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4171                         goto pci_map_failed;
4172                 txdp++;
4173         }
4174
4175         txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4176                                               frg_len, PCI_DMA_TODEVICE);
4177         if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4178                 goto pci_map_failed;
4179
4180         txdp->Host_Control = (unsigned long)skb;
4181         txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4182         if (offload_type == SKB_GSO_UDP)
4183                 txdp->Control_1 |= TXD_UFO_EN;
4184
4185         frg_cnt = skb_shinfo(skb)->nr_frags;
4186         /* For fragmented SKB. */
4187         for (i = 0; i < frg_cnt; i++) {
4188                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4189                 /* A '0' length fragment will be ignored */
4190                 if (!frag->size)
4191                         continue;
4192                 txdp++;
4193                 txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4194                                                          frag->page_offset,
4195                                                          frag->size,
4196                                                          PCI_DMA_TODEVICE);
4197                 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4198                 if (offload_type == SKB_GSO_UDP)
4199                         txdp->Control_1 |= TXD_UFO_EN;
4200         }
4201         txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4202
4203         if (offload_type == SKB_GSO_UDP)
4204                 frg_cnt++; /* as Txd0 was used for inband header */
4205
4206         tx_fifo = mac_control->tx_FIFO_start[queue];
4207         val64 = fifo->list_info[put_off].list_phy_addr;
4208         writeq(val64, &tx_fifo->TxDL_Pointer);
4209
4210         val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4211                  TX_FIFO_LAST_LIST);
4212         if (offload_type)
4213                 val64 |= TX_FIFO_SPECIAL_FUNC;
4214
4215         writeq(val64, &tx_fifo->List_Control);
4216
4217         mmiowb();
4218
4219         put_off++;
4220         if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4221                 put_off = 0;
4222         fifo->tx_curr_put_info.offset = put_off;
4223
4224         /* Avoid "put" pointer going beyond "get" pointer */
4225         if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4226                 swstats->fifo_full_cnt++;
4227                 DBG_PRINT(TX_DBG,
4228                           "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4229                           put_off, get_off);
4230                 s2io_stop_tx_queue(sp, fifo->fifo_no);
4231         }
4232         swstats->mem_allocated += skb->truesize;
4233         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4234
4235         if (sp->config.intr_type == MSI_X)
4236                 tx_intr_handler(fifo);
4237
4238         return NETDEV_TX_OK;
4239
4240 pci_map_failed:
4241         swstats->pci_map_fail_cnt++;
4242         s2io_stop_tx_queue(sp, fifo->fifo_no);
4243         swstats->mem_freed += skb->truesize;
4244         dev_kfree_skb(skb);
4245         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4246         return NETDEV_TX_OK;
4247 }
4248
4249 static void
4250 s2io_alarm_handle(unsigned long data)
4251 {
4252         struct s2io_nic *sp = (struct s2io_nic *)data;
4253         struct net_device *dev = sp->dev;
4254
4255         s2io_handle_errors(dev);
4256         mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4257 }
4258
4259 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4260 {
4261         struct ring_info *ring = (struct ring_info *)dev_id;
4262         struct s2io_nic *sp = ring->nic;
4263         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4264
4265         if (unlikely(!is_s2io_card_up(sp)))
4266                 return IRQ_HANDLED;
4267
4268         if (sp->config.napi) {
4269                 u8 __iomem *addr = NULL;
4270                 u8 val8 = 0;
4271
4272                 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4273                 addr += (7 - ring->ring_no);
4274                 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4275                 writeb(val8, addr);
4276                 val8 = readb(addr);
4277                 napi_schedule(&ring->napi);
4278         } else {
4279                 rx_intr_handler(ring, 0);
4280                 s2io_chk_rx_buffers(sp, ring);
4281         }
4282
4283         return IRQ_HANDLED;
4284 }
4285
4286 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4287 {
4288         int i;
4289         struct fifo_info *fifos = (struct fifo_info *)dev_id;
4290         struct s2io_nic *sp = fifos->nic;
4291         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4292         struct config_param *config  = &sp->config;
4293         u64 reason;
4294
4295         if (unlikely(!is_s2io_card_up(sp)))
4296                 return IRQ_NONE;
4297
4298         reason = readq(&bar0->general_int_status);
4299         if (unlikely(reason == S2IO_MINUS_ONE))
4300                 /* Nothing much can be done. Get out */
4301                 return IRQ_HANDLED;
4302
4303         if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4304                 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4305
4306                 if (reason & GEN_INTR_TXPIC)
4307                         s2io_txpic_intr_handle(sp);
4308
4309                 if (reason & GEN_INTR_TXTRAFFIC)
4310                         writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4311
4312                 for (i = 0; i < config->tx_fifo_num; i++)
4313                         tx_intr_handler(&fifos[i]);
4314
4315                 writeq(sp->general_int_mask, &bar0->general_int_mask);
4316                 readl(&bar0->general_int_status);
4317                 return IRQ_HANDLED;
4318         }
4319         /* The interrupt was not raised by us */
4320         return IRQ_NONE;
4321 }
4322
4323 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4324 {
4325         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4326         u64 val64;
4327
4328         val64 = readq(&bar0->pic_int_status);
4329         if (val64 & PIC_INT_GPIO) {
4330                 val64 = readq(&bar0->gpio_int_reg);
4331                 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4332                     (val64 & GPIO_INT_REG_LINK_UP)) {
4333                         /*
4334                          * This is unstable state so clear both up/down
4335                          * interrupt and adapter to re-evaluate the link state.
4336                          */
4337                         val64 |= GPIO_INT_REG_LINK_DOWN;
4338                         val64 |= GPIO_INT_REG_LINK_UP;
4339                         writeq(val64, &bar0->gpio_int_reg);
4340                         val64 = readq(&bar0->gpio_int_mask);
4341                         val64 &= ~(GPIO_INT_MASK_LINK_UP |
4342                                    GPIO_INT_MASK_LINK_DOWN);
4343                         writeq(val64, &bar0->gpio_int_mask);
4344                 } else if (val64 & GPIO_INT_REG_LINK_UP) {
4345                         val64 = readq(&bar0->adapter_status);
4346                         /* Enable Adapter */
4347                         val64 = readq(&bar0->adapter_control);
4348                         val64 |= ADAPTER_CNTL_EN;
4349                         writeq(val64, &bar0->adapter_control);
4350                         val64 |= ADAPTER_LED_ON;
4351                         writeq(val64, &bar0->adapter_control);
4352                         if (!sp->device_enabled_once)
4353                                 sp->device_enabled_once = 1;
4354
4355                         s2io_link(sp, LINK_UP);
4356                         /*
4357                          * unmask link down interrupt and mask link-up
4358                          * intr
4359                          */
4360                         val64 = readq(&bar0->gpio_int_mask);
4361                         val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4362                         val64 |= GPIO_INT_MASK_LINK_UP;
4363                         writeq(val64, &bar0->gpio_int_mask);
4364
4365                 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4366                         val64 = readq(&bar0->adapter_status);
4367                         s2io_link(sp, LINK_DOWN);
4368                         /* Link is down so unmaks link up interrupt */
4369                         val64 = readq(&bar0->gpio_int_mask);
4370                         val64 &= ~GPIO_INT_MASK_LINK_UP;
4371                         val64 |= GPIO_INT_MASK_LINK_DOWN;
4372                         writeq(val64, &bar0->gpio_int_mask);
4373
4374                         /* turn off LED */
4375                         val64 = readq(&bar0->adapter_control);
4376                         val64 = val64 & (~ADAPTER_LED_ON);
4377                         writeq(val64, &bar0->adapter_control);
4378                 }
4379         }
4380         val64 = readq(&bar0->gpio_int_mask);
4381 }
4382
4383 /**
4384  *  do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4385  *  @value: alarm bits
4386  *  @addr: address value
4387  *  @cnt: counter variable
4388  *  Description: Check for alarm and increment the counter
4389  *  Return Value:
4390  *  1 - if alarm bit set
4391  *  0 - if alarm bit is not set
4392  */
4393 static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4394                                  unsigned long long *cnt)
4395 {
4396         u64 val64;
4397         val64 = readq(addr);
4398         if (val64 & value) {
4399                 writeq(val64, addr);
4400                 (*cnt)++;
4401                 return 1;
4402         }
4403         return 0;
4404
4405 }
4406
4407 /**
4408  *  s2io_handle_errors - Xframe error indication handler
4409  *  @nic: device private variable
4410  *  Description: Handle alarms such as loss of link, single or
4411  *  double ECC errors, critical and serious errors.
4412  *  Return Value:
4413  *  NONE
4414  */
4415 static void s2io_handle_errors(void *dev_id)
4416 {
4417         struct net_device *dev = (struct net_device *)dev_id;
4418         struct s2io_nic *sp = netdev_priv(dev);
4419         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4420         u64 temp64 = 0, val64 = 0;
4421         int i = 0;
4422
4423         struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4424         struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4425
4426         if (!is_s2io_card_up(sp))
4427                 return;
4428
4429         if (pci_channel_offline(sp->pdev))
4430                 return;
4431
4432         memset(&sw_stat->ring_full_cnt, 0,
4433                sizeof(sw_stat->ring_full_cnt));
4434
4435         /* Handling the XPAK counters update */
4436         if (stats->xpak_timer_count < 72000) {
4437                 /* waiting for an hour */
4438                 stats->xpak_timer_count++;
4439         } else {
4440                 s2io_updt_xpak_counter(dev);
4441                 /* reset the count to zero */
4442                 stats->xpak_timer_count = 0;
4443         }
4444
4445         /* Handling link status change error Intr */
4446         if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4447                 val64 = readq(&bar0->mac_rmac_err_reg);
4448                 writeq(val64, &bar0->mac_rmac_err_reg);
4449                 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4450                         schedule_work(&sp->set_link_task);
4451         }
4452
4453         /* In case of a serious error, the device will be Reset. */
4454         if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4455                                   &sw_stat->serious_err_cnt))
4456                 goto reset;
4457
4458         /* Check for data parity error */
4459         if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4460                                   &sw_stat->parity_err_cnt))
4461                 goto reset;
4462
4463         /* Check for ring full counter */
4464         if (sp->device_type == XFRAME_II_DEVICE) {
4465                 val64 = readq(&bar0->ring_bump_counter1);
4466                 for (i = 0; i < 4; i++) {
4467                         temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4468                         temp64 >>= 64 - ((i+1)*16);
4469                         sw_stat->ring_full_cnt[i] += temp64;
4470                 }
4471
4472                 val64 = readq(&bar0->ring_bump_counter2);
4473                 for (i = 0; i < 4; i++) {
4474                         temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4475                         temp64 >>= 64 - ((i+1)*16);
4476                         sw_stat->ring_full_cnt[i+4] += temp64;
4477                 }
4478         }
4479
4480         val64 = readq(&bar0->txdma_int_status);
4481         /*check for pfc_err*/
4482         if (val64 & TXDMA_PFC_INT) {
4483                 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4484                                           PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4485                                           PFC_PCIX_ERR,
4486                                           &bar0->pfc_err_reg,
4487                                           &sw_stat->pfc_err_cnt))
4488                         goto reset;
4489                 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4490                                       &bar0->pfc_err_reg,
4491                                       &sw_stat->pfc_err_cnt);
4492         }
4493
4494         /*check for tda_err*/
4495         if (val64 & TXDMA_TDA_INT) {
4496                 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4497                                           TDA_SM0_ERR_ALARM |
4498                                           TDA_SM1_ERR_ALARM,
4499                                           &bar0->tda_err_reg,
4500                                           &sw_stat->tda_err_cnt))
4501                         goto reset;
4502                 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4503                                       &bar0->tda_err_reg,
4504                                       &sw_stat->tda_err_cnt);
4505         }
4506         /*check for pcc_err*/
4507         if (val64 & TXDMA_PCC_INT) {
4508                 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4509                                           PCC_N_SERR | PCC_6_COF_OV_ERR |
4510                                           PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4511                                           PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4512                                           PCC_TXB_ECC_DB_ERR,
4513                                           &bar0->pcc_err_reg,
4514                                           &sw_stat->pcc_err_cnt))
4515                         goto reset;
4516                 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4517                                       &bar0->pcc_err_reg,
4518                                       &sw_stat->pcc_err_cnt);
4519         }
4520
4521         /*check for tti_err*/
4522         if (val64 & TXDMA_TTI_INT) {
4523                 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4524                                           &bar0->tti_err_reg,
4525                                           &sw_stat->tti_err_cnt))
4526                         goto reset;
4527                 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4528                                       &bar0->tti_err_reg,
4529                                       &sw_stat->tti_err_cnt);
4530         }
4531
4532         /*check for lso_err*/
4533         if (val64 & TXDMA_LSO_INT) {
4534                 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4535                                           LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4536                                           &bar0->lso_err_reg,
4537                                           &sw_stat->lso_err_cnt))
4538                         goto reset;
4539                 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4540                                       &bar0->lso_err_reg,
4541                                       &sw_stat->lso_err_cnt);
4542         }
4543
4544         /*check for tpa_err*/
4545         if (val64 & TXDMA_TPA_INT) {
4546                 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4547                                           &bar0->tpa_err_reg,
4548                                           &sw_stat->tpa_err_cnt))
4549                         goto reset;
4550                 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4551                                       &bar0->tpa_err_reg,
4552                                       &sw_stat->tpa_err_cnt);
4553         }
4554
4555         /*check for sm_err*/
4556         if (val64 & TXDMA_SM_INT) {
4557                 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4558                                           &bar0->sm_err_reg,
4559                                           &sw_stat->sm_err_cnt))
4560                         goto reset;
4561         }
4562
4563         val64 = readq(&bar0->mac_int_status);
4564         if (val64 & MAC_INT_STATUS_TMAC_INT) {
4565                 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4566                                           &bar0->mac_tmac_err_reg,
4567                                           &sw_stat->mac_tmac_err_cnt))
4568                         goto reset;
4569                 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4570                                       TMAC_DESC_ECC_SG_ERR |
4571                                       TMAC_DESC_ECC_DB_ERR,
4572                                       &bar0->mac_tmac_err_reg,
4573                                       &sw_stat->mac_tmac_err_cnt);
4574         }
4575
4576         val64 = readq(&bar0->xgxs_int_status);
4577         if (val64 & XGXS_INT_STATUS_TXGXS) {
4578                 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4579                                           &bar0->xgxs_txgxs_err_reg,
4580                                           &sw_stat->xgxs_txgxs_err_cnt))
4581                         goto reset;
4582                 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4583                                       &bar0->xgxs_txgxs_err_reg,
4584                                       &sw_stat->xgxs_txgxs_err_cnt);
4585         }
4586
4587         val64 = readq(&bar0->rxdma_int_status);
4588         if (val64 & RXDMA_INT_RC_INT_M) {
4589                 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4590                                           RC_FTC_ECC_DB_ERR |
4591                                           RC_PRCn_SM_ERR_ALARM |
4592                                           RC_FTC_SM_ERR_ALARM,
4593                                           &bar0->rc_err_reg,
4594                                           &sw_stat->rc_err_cnt))
4595                         goto reset;
4596                 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4597                                       RC_FTC_ECC_SG_ERR |
4598                                       RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4599                                       &sw_stat->rc_err_cnt);
4600                 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4601                                           PRC_PCI_AB_WR_Rn |
4602                                           PRC_PCI_AB_F_WR_Rn,
4603                                           &bar0->prc_pcix_err_reg,
4604                                           &sw_stat->prc_pcix_err_cnt))
4605                         goto reset;
4606                 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4607                                       PRC_PCI_DP_WR_Rn |
4608                                       PRC_PCI_DP_F_WR_Rn,
4609                                       &bar0->prc_pcix_err_reg,
4610                                       &sw_stat->prc_pcix_err_cnt);
4611         }
4612
4613         if (val64 & RXDMA_INT_RPA_INT_M) {
4614                 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4615                                           &bar0->rpa_err_reg,
4616                                           &sw_stat->rpa_err_cnt))
4617                         goto reset;
4618                 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4619                                       &bar0->rpa_err_reg,
4620                                       &sw_stat->rpa_err_cnt);
4621         }
4622
4623         if (val64 & RXDMA_INT_RDA_INT_M) {
4624                 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4625                                           RDA_FRM_ECC_DB_N_AERR |
4626                                           RDA_SM1_ERR_ALARM |
4627                                           RDA_SM0_ERR_ALARM |
4628                                           RDA_RXD_ECC_DB_SERR,
4629                                           &bar0->rda_err_reg,
4630                                           &sw_stat->rda_err_cnt))
4631                         goto reset;
4632                 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4633                                       RDA_FRM_ECC_SG_ERR |
4634                                       RDA_MISC_ERR |
4635                                       RDA_PCIX_ERR,
4636                                       &bar0->rda_err_reg,
4637                                       &sw_stat->rda_err_cnt);
4638         }
4639
4640         if (val64 & RXDMA_INT_RTI_INT_M) {
4641                 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4642                                           &bar0->rti_err_reg,
4643                                           &sw_stat->rti_err_cnt))
4644                         goto reset;
4645                 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4646                                       &bar0->rti_err_reg,
4647                                       &sw_stat->rti_err_cnt);
4648         }
4649
4650         val64 = readq(&bar0->mac_int_status);
4651         if (val64 & MAC_INT_STATUS_RMAC_INT) {
4652                 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4653                                           &bar0->mac_rmac_err_reg,
4654                                           &sw_stat->mac_rmac_err_cnt))
4655                         goto reset;
4656                 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4657                                       RMAC_SINGLE_ECC_ERR |
4658                                       RMAC_DOUBLE_ECC_ERR,
4659                                       &bar0->mac_rmac_err_reg,
4660                                       &sw_stat->mac_rmac_err_cnt);
4661         }
4662
4663         val64 = readq(&bar0->xgxs_int_status);
4664         if (val64 & XGXS_INT_STATUS_RXGXS) {
4665                 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4666                                           &bar0->xgxs_rxgxs_err_reg,
4667                                           &sw_stat->xgxs_rxgxs_err_cnt))
4668                         goto reset;
4669         }
4670
4671         val64 = readq(&bar0->mc_int_status);
4672         if (val64 & MC_INT_STATUS_MC_INT) {
4673                 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4674                                           &bar0->mc_err_reg,
4675                                           &sw_stat->mc_err_cnt))
4676                         goto reset;
4677
4678                 /* Handling Ecc errors */
4679                 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4680                         writeq(val64, &bar0->mc_err_reg);
4681                         if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4682                                 sw_stat->double_ecc_errs++;
4683                                 if (sp->device_type != XFRAME_II_DEVICE) {
4684                                         /*
4685                                          * Reset XframeI only if critical error
4686                                          */
4687                                         if (val64 &
4688                                             (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4689                                              MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4690                                                 goto reset;
4691                                 }
4692                         } else
4693                                 sw_stat->single_ecc_errs++;
4694                 }
4695         }
4696         return;
4697
4698 reset:
4699         s2io_stop_all_tx_queue(sp);
4700         schedule_work(&sp->rst_timer_task);
4701         sw_stat->soft_reset_cnt++;
4702 }
4703
4704 /**
4705  *  s2io_isr - ISR handler of the device .
4706  *  @irq: the irq of the device.
4707  *  @dev_id: a void pointer to the dev structure of the NIC.
4708  *  Description:  This function is the ISR handler of the device. It
4709  *  identifies the reason for the interrupt and calls the relevant
4710  *  service routines. As a contongency measure, this ISR allocates the
4711  *  recv buffers, if their numbers are below the panic value which is
4712  *  presently set to 25% of the original number of rcv buffers allocated.
4713  *  Return value:
4714  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
4715  *   IRQ_NONE: will be returned if interrupt is not from our device
4716  */
4717 static irqreturn_t s2io_isr(int irq, void *dev_id)
4718 {
4719         struct net_device *dev = (struct net_device *)dev_id;
4720         struct s2io_nic *sp = netdev_priv(dev);
4721         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4722         int i;
4723         u64 reason = 0;
4724         struct mac_info *mac_control;
4725         struct config_param *config;
4726
4727         /* Pretend we handled any irq's from a disconnected card */
4728         if (pci_channel_offline(sp->pdev))
4729                 return IRQ_NONE;
4730
4731         if (!is_s2io_card_up(sp))
4732                 return IRQ_NONE;
4733
4734         config = &sp->config;
4735         mac_control = &sp->mac_control;
4736
4737         /*
4738          * Identify the cause for interrupt and call the appropriate
4739          * interrupt handler. Causes for the interrupt could be;
4740          * 1. Rx of packet.
4741          * 2. Tx complete.
4742          * 3. Link down.
4743          */
4744         reason = readq(&bar0->general_int_status);
4745
4746         if (unlikely(reason == S2IO_MINUS_ONE))
4747                 return IRQ_HANDLED;     /* Nothing much can be done. Get out */
4748
4749         if (reason &
4750             (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
4751                 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4752
4753                 if (config->napi) {
4754                         if (reason & GEN_INTR_RXTRAFFIC) {
4755                                 napi_schedule(&sp->napi);
4756                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4757                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4758                                 readl(&bar0->rx_traffic_int);
4759                         }
4760                 } else {
4761                         /*
4762                          * rx_traffic_int reg is an R1 register, writing all 1's
4763                          * will ensure that the actual interrupt causing bit
4764                          * get's cleared and hence a read can be avoided.
4765                          */
4766                         if (reason & GEN_INTR_RXTRAFFIC)
4767                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4768
4769                         for (i = 0; i < config->rx_ring_num; i++) {
4770                                 struct ring_info *ring = &mac_control->rings[i];
4771
4772                                 rx_intr_handler(ring, 0);
4773                         }
4774                 }
4775
4776                 /*
4777                  * tx_traffic_int reg is an R1 register, writing all 1's
4778                  * will ensure that the actual interrupt causing bit get's
4779                  * cleared and hence a read can be avoided.
4780                  */
4781                 if (reason & GEN_INTR_TXTRAFFIC)
4782                         writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4783
4784                 for (i = 0; i < config->tx_fifo_num; i++)
4785                         tx_intr_handler(&mac_control->fifos[i]);
4786
4787                 if (reason & GEN_INTR_TXPIC)
4788                         s2io_txpic_intr_handle(sp);
4789
4790                 /*
4791                  * Reallocate the buffers from the interrupt handler itself.
4792                  */
4793                 if (!config->napi) {
4794                         for (i = 0; i < config->rx_ring_num; i++) {
4795                                 struct ring_info *ring = &mac_control->rings[i];
4796
4797                                 s2io_chk_rx_buffers(sp, ring);
4798                         }
4799                 }
4800                 writeq(sp->general_int_mask, &bar0->general_int_mask);
4801                 readl(&bar0->general_int_status);
4802
4803                 return IRQ_HANDLED;
4804
4805         } else if (!reason) {
4806                 /* The interrupt was not raised by us */
4807                 return IRQ_NONE;
4808         }
4809
4810         return IRQ_HANDLED;
4811 }
4812
4813 /**
4814  * s2io_updt_stats -
4815  */
4816 static void s2io_updt_stats(struct s2io_nic *sp)
4817 {
4818         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4819         u64 val64;
4820         int cnt = 0;
4821
4822         if (is_s2io_card_up(sp)) {
4823                 /* Apprx 30us on a 133 MHz bus */
4824                 val64 = SET_UPDT_CLICKS(10) |
4825                         STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4826                 writeq(val64, &bar0->stat_cfg);
4827                 do {
4828                         udelay(100);
4829                         val64 = readq(&bar0->stat_cfg);
4830                         if (!(val64 & s2BIT(0)))
4831                                 break;
4832                         cnt++;
4833                         if (cnt == 5)
4834                                 break; /* Updt failed */
4835                 } while (1);
4836         }
4837 }
4838
4839 /**
4840  *  s2io_get_stats - Updates the device statistics structure.
4841  *  @dev : pointer to the device structure.
4842  *  Description:
4843  *  This function updates the device statistics structure in the s2io_nic
4844  *  structure and returns a pointer to the same.
4845  *  Return value:
4846  *  pointer to the updated net_device_stats structure.
4847  */
4848 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4849 {
4850         struct s2io_nic *sp = netdev_priv(dev);
4851         struct mac_info *mac_control = &sp->mac_control;
4852         struct stat_block *stats = mac_control->stats_info;
4853         u64 delta;
4854
4855         /* Configure Stats for immediate updt */
4856         s2io_updt_stats(sp);
4857
4858         /* A device reset will cause the on-adapter statistics to be zero'ed.
4859          * This can be done while running by changing the MTU.  To prevent the
4860          * system from having the stats zero'ed, the driver keeps a copy of the
4861          * last update to the system (which is also zero'ed on reset).  This
4862          * enables the driver to accurately know the delta between the last
4863          * update and the current update.
4864          */
4865         delta = ((u64) le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
4866                 le32_to_cpu(stats->rmac_vld_frms)) - sp->stats.rx_packets;
4867         sp->stats.rx_packets += delta;
4868         dev->stats.rx_packets += delta;
4869
4870         delta = ((u64) le32_to_cpu(stats->tmac_frms_oflow) << 32 |
4871                 le32_to_cpu(stats->tmac_frms)) - sp->stats.tx_packets;
4872         sp->stats.tx_packets += delta;
4873         dev->stats.tx_packets += delta;
4874
4875         delta = ((u64) le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
4876                 le32_to_cpu(stats->rmac_data_octets)) - sp->stats.rx_bytes;
4877         sp->stats.rx_bytes += delta;
4878         dev->stats.rx_bytes += delta;
4879
4880         delta = ((u64) le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
4881                 le32_to_cpu(stats->tmac_data_octets)) - sp->stats.tx_bytes;
4882         sp->stats.tx_bytes += delta;
4883         dev->stats.tx_bytes += delta;
4884
4885         delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_errors;
4886         sp->stats.rx_errors += delta;
4887         dev->stats.rx_errors += delta;
4888
4889         delta = ((u64) le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
4890                 le32_to_cpu(stats->tmac_any_err_frms)) - sp->stats.tx_errors;
4891         sp->stats.tx_errors += delta;
4892         dev->stats.tx_errors += delta;
4893
4894         delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_dropped;
4895         sp->stats.rx_dropped += delta;
4896         dev->stats.rx_dropped += delta;
4897
4898         delta = le64_to_cpu(stats->tmac_drop_frms) - sp->stats.tx_dropped;
4899         sp->stats.tx_dropped += delta;
4900         dev->stats.tx_dropped += delta;
4901
4902         /* The adapter MAC interprets pause frames as multicast packets, but
4903          * does not pass them up.  This erroneously increases the multicast
4904          * packet count and needs to be deducted when the multicast frame count
4905          * is queried.
4906          */
4907         delta = (u64) le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
4908                 le32_to_cpu(stats->rmac_vld_mcst_frms);
4909         delta -= le64_to_cpu(stats->rmac_pause_ctrl_frms);
4910         delta -= sp->stats.multicast;
4911         sp->stats.multicast += delta;
4912         dev->stats.multicast += delta;
4913
4914         delta = ((u64) le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
4915                 le32_to_cpu(stats->rmac_usized_frms)) +
4916                 le64_to_cpu(stats->rmac_long_frms) - sp->stats.rx_length_errors;
4917         sp->stats.rx_length_errors += delta;
4918         dev->stats.rx_length_errors += delta;
4919
4920         delta = le64_to_cpu(stats->rmac_fcs_err_frms) - sp->stats.rx_crc_errors;
4921         sp->stats.rx_crc_errors += delta;
4922         dev->stats.rx_crc_errors += delta;
4923
4924         return &dev->stats;
4925 }
4926
4927 /**
4928  *  s2io_set_multicast - entry point for multicast address enable/disable.
4929  *  @dev : pointer to the device structure
4930  *  Description:
4931  *  This function is a driver entry point which gets called by the kernel
4932  *  whenever multicast addresses must be enabled/disabled. This also gets
4933  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
4934  *  determine, if multicast address must be enabled or if promiscuous mode
4935  *  is to be disabled etc.
4936  *  Return value:
4937  *  void.
4938  */
4939
4940 static void s2io_set_multicast(struct net_device *dev)
4941 {
4942         int i, j, prev_cnt;
4943         struct netdev_hw_addr *ha;
4944         struct s2io_nic *sp = netdev_priv(dev);
4945         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4946         u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4947                 0xfeffffffffffULL;
4948         u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
4949         void __iomem *add;
4950         struct config_param *config = &sp->config;
4951
4952         if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4953                 /*  Enable all Multicast addresses */
4954                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4955                        &bar0->rmac_addr_data0_mem);
4956                 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4957                        &bar0->rmac_addr_data1_mem);
4958                 val64 = RMAC_ADDR_CMD_MEM_WE |
4959                         RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4960                         RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
4961                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4962                 /* Wait till command completes */
4963                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4964                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4965                                       S2IO_BIT_RESET);
4966
4967                 sp->m_cast_flg = 1;
4968                 sp->all_multi_pos = config->max_mc_addr - 1;
4969         } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4970                 /*  Disable all Multicast addresses */
4971                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4972                        &bar0->rmac_addr_data0_mem);
4973                 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4974                        &bar0->rmac_addr_data1_mem);
4975                 val64 = RMAC_ADDR_CMD_MEM_WE |
4976                         RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4977                         RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4978                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4979                 /* Wait till command completes */
4980                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4981                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4982                                       S2IO_BIT_RESET);
4983
4984                 sp->m_cast_flg = 0;
4985                 sp->all_multi_pos = 0;
4986         }
4987
4988         if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4989                 /*  Put the NIC into promiscuous mode */
4990                 add = &bar0->mac_cfg;
4991                 val64 = readq(&bar0->mac_cfg);
4992                 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4993
4994                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4995                 writel((u32)val64, add);
4996                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4997                 writel((u32) (val64 >> 32), (add + 4));
4998
4999                 if (vlan_tag_strip != 1) {
5000                         val64 = readq(&bar0->rx_pa_cfg);
5001                         val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5002                         writeq(val64, &bar0->rx_pa_cfg);
5003                         sp->vlan_strip_flag = 0;
5004                 }
5005
5006                 val64 = readq(&bar0->mac_cfg);
5007                 sp->promisc_flg = 1;
5008                 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
5009                           dev->name);
5010         } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5011                 /*  Remove the NIC from promiscuous mode */
5012                 add = &bar0->mac_cfg;
5013                 val64 = readq(&bar0->mac_cfg);
5014                 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5015
5016                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5017                 writel((u32)val64, add);
5018                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5019                 writel((u32) (val64 >> 32), (add + 4));
5020
5021                 if (vlan_tag_strip != 0) {
5022                         val64 = readq(&bar0->rx_pa_cfg);
5023                         val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5024                         writeq(val64, &bar0->rx_pa_cfg);
5025                         sp->vlan_strip_flag = 1;
5026                 }
5027
5028                 val64 = readq(&bar0->mac_cfg);
5029                 sp->promisc_flg = 0;
5030                 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
5031         }
5032
5033         /*  Update individual M_CAST address list */
5034         if ((!sp->m_cast_flg) && netdev_mc_count(dev)) {
5035                 if (netdev_mc_count(dev) >
5036                     (config->max_mc_addr - config->max_mac_addr)) {
5037                         DBG_PRINT(ERR_DBG,
5038                                   "%s: No more Rx filters can be added - "
5039                                   "please enable ALL_MULTI instead\n",
5040                                   dev->name);
5041                         return;
5042                 }
5043
5044                 prev_cnt = sp->mc_addr_count;
5045                 sp->mc_addr_count = netdev_mc_count(dev);
5046
5047                 /* Clear out the previous list of Mc in the H/W. */
5048                 for (i = 0; i < prev_cnt; i++) {
5049                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5050                                &bar0->rmac_addr_data0_mem);
5051                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5052                                &bar0->rmac_addr_data1_mem);
5053                         val64 = RMAC_ADDR_CMD_MEM_WE |
5054                                 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5055                                 RMAC_ADDR_CMD_MEM_OFFSET
5056                                 (config->mc_start_offset + i);
5057                         writeq(val64, &bar0->rmac_addr_cmd_mem);
5058
5059                         /* Wait for command completes */
5060                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5061                                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5062                                                   S2IO_BIT_RESET)) {
5063                                 DBG_PRINT(ERR_DBG,
5064                                           "%s: Adding Multicasts failed\n",
5065                                           dev->name);
5066                                 return;
5067                         }
5068                 }
5069
5070                 /* Create the new Rx filter list and update the same in H/W. */
5071                 i = 0;
5072                 netdev_for_each_mc_addr(ha, dev) {
5073                         mac_addr = 0;
5074                         for (j = 0; j < ETH_ALEN; j++) {
5075                                 mac_addr |= ha->addr[j];
5076                                 mac_addr <<= 8;
5077                         }
5078                         mac_addr >>= 8;
5079                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5080                                &bar0->rmac_addr_data0_mem);
5081                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5082                                &bar0->rmac_addr_data1_mem);
5083                         val64 = RMAC_ADDR_CMD_MEM_WE |
5084                                 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5085                                 RMAC_ADDR_CMD_MEM_OFFSET
5086                                 (i + config->mc_start_offset);
5087                         writeq(val64, &bar0->rmac_addr_cmd_mem);
5088
5089                         /* Wait for command completes */
5090                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5091                                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5092                                                   S2IO_BIT_RESET)) {
5093                                 DBG_PRINT(ERR_DBG,
5094                                           "%s: Adding Multicasts failed\n",
5095                                           dev->name);
5096                                 return;
5097                         }
5098                         i++;
5099                 }
5100         }
5101 }
5102
5103 /* read from CAM unicast & multicast addresses and store it in
5104  * def_mac_addr structure
5105  */
5106 static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5107 {
5108         int offset;
5109         u64 mac_addr = 0x0;
5110         struct config_param *config = &sp->config;
5111
5112         /* store unicast & multicast mac addresses */
5113         for (offset = 0; offset < config->max_mc_addr; offset++) {
5114                 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5115                 /* if read fails disable the entry */
5116                 if (mac_addr == FAILURE)
5117                         mac_addr = S2IO_DISABLE_MAC_ENTRY;
5118                 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5119         }
5120 }
5121
5122 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5123 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5124 {
5125         int offset;
5126         struct config_param *config = &sp->config;
5127         /* restore unicast mac address */
5128         for (offset = 0; offset < config->max_mac_addr; offset++)
5129                 do_s2io_prog_unicast(sp->dev,
5130                                      sp->def_mac_addr[offset].mac_addr);
5131
5132         /* restore multicast mac address */
5133         for (offset = config->mc_start_offset;
5134              offset < config->max_mc_addr; offset++)
5135                 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5136 }
5137
5138 /* add a multicast MAC address to CAM */
5139 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5140 {
5141         int i;
5142         u64 mac_addr = 0;
5143         struct config_param *config = &sp->config;
5144
5145         for (i = 0; i < ETH_ALEN; i++) {
5146                 mac_addr <<= 8;
5147                 mac_addr |= addr[i];
5148         }
5149         if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5150                 return SUCCESS;
5151
5152         /* check if the multicast mac already preset in CAM */
5153         for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5154                 u64 tmp64;
5155                 tmp64 = do_s2io_read_unicast_mc(sp, i);
5156                 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5157                         break;
5158
5159                 if (tmp64 == mac_addr)
5160                         return SUCCESS;
5161         }
5162         if (i == config->max_mc_addr) {
5163                 DBG_PRINT(ERR_DBG,
5164                           "CAM full no space left for multicast MAC\n");
5165                 return FAILURE;
5166         }
5167         /* Update the internal structure with this new mac address */
5168         do_s2io_copy_mac_addr(sp, i, mac_addr);
5169
5170         return do_s2io_add_mac(sp, mac_addr, i);
5171 }
5172
5173 /* add MAC address to CAM */
5174 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5175 {
5176         u64 val64;
5177         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5178
5179         writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5180                &bar0->rmac_addr_data0_mem);
5181
5182         val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5183                 RMAC_ADDR_CMD_MEM_OFFSET(off);
5184         writeq(val64, &bar0->rmac_addr_cmd_mem);
5185
5186         /* Wait till command completes */
5187         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5188                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5189                                   S2IO_BIT_RESET)) {
5190                 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5191                 return FAILURE;
5192         }
5193         return SUCCESS;
5194 }
5195 /* deletes a specified unicast/multicast mac entry from CAM */
5196 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5197 {
5198         int offset;
5199         u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5200         struct config_param *config = &sp->config;
5201
5202         for (offset = 1;
5203              offset < config->max_mc_addr; offset++) {
5204                 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5205                 if (tmp64 == addr) {
5206                         /* disable the entry by writing  0xffffffffffffULL */
5207                         if (do_s2io_add_mac(sp, dis_addr, offset) ==  FAILURE)
5208                                 return FAILURE;
5209                         /* store the new mac list from CAM */
5210                         do_s2io_store_unicast_mc(sp);
5211                         return SUCCESS;
5212                 }
5213         }
5214         DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5215                   (unsigned long long)addr);
5216         return FAILURE;
5217 }
5218
5219 /* read mac entries from CAM */
5220 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5221 {
5222         u64 tmp64 = 0xffffffffffff0000ULL, val64;
5223         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5224
5225         /* read mac addr */
5226         val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5227                 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5228         writeq(val64, &bar0->rmac_addr_cmd_mem);
5229
5230         /* Wait till command completes */
5231         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5232                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5233                                   S2IO_BIT_RESET)) {
5234                 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5235                 return FAILURE;
5236         }
5237         tmp64 = readq(&bar0->rmac_addr_data0_mem);
5238
5239         return tmp64 >> 16;
5240 }
5241
5242 /**
5243  * s2io_set_mac_addr driver entry point
5244  */
5245
5246 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5247 {
5248         struct sockaddr *addr = p;
5249
5250         if (!is_valid_ether_addr(addr->sa_data))
5251                 return -EINVAL;
5252
5253         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5254
5255         /* store the MAC address in CAM */
5256         return do_s2io_prog_unicast(dev, dev->dev_addr);
5257 }
5258 /**
5259  *  do_s2io_prog_unicast - Programs the Xframe mac address
5260  *  @dev : pointer to the device structure.
5261  *  @addr: a uchar pointer to the new mac address which is to be set.
5262  *  Description : This procedure will program the Xframe to receive
5263  *  frames with new Mac Address
5264  *  Return value: SUCCESS on success and an appropriate (-)ve integer
5265  *  as defined in errno.h file on failure.
5266  */
5267
5268 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5269 {
5270         struct s2io_nic *sp = netdev_priv(dev);
5271         register u64 mac_addr = 0, perm_addr = 0;
5272         int i;
5273         u64 tmp64;
5274         struct config_param *config = &sp->config;
5275
5276         /*
5277          * Set the new MAC address as the new unicast filter and reflect this
5278          * change on the device address registered with the OS. It will be
5279          * at offset 0.
5280          */
5281         for (i = 0; i < ETH_ALEN; i++) {
5282                 mac_addr <<= 8;
5283                 mac_addr |= addr[i];
5284                 perm_addr <<= 8;
5285                 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5286         }
5287
5288         /* check if the dev_addr is different than perm_addr */
5289         if (mac_addr == perm_addr)
5290                 return SUCCESS;
5291
5292         /* check if the mac already preset in CAM */
5293         for (i = 1; i < config->max_mac_addr; i++) {
5294                 tmp64 = do_s2io_read_unicast_mc(sp, i);
5295                 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5296                         break;
5297
5298                 if (tmp64 == mac_addr) {
5299                         DBG_PRINT(INFO_DBG,
5300                                   "MAC addr:0x%llx already present in CAM\n",
5301                                   (unsigned long long)mac_addr);
5302                         return SUCCESS;
5303                 }
5304         }
5305         if (i == config->max_mac_addr) {
5306                 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5307                 return FAILURE;
5308         }
5309         /* Update the internal structure with this new mac address */
5310         do_s2io_copy_mac_addr(sp, i, mac_addr);
5311
5312         return do_s2io_add_mac(sp, mac_addr, i);
5313 }
5314
5315 /**
5316  * s2io_ethtool_sset - Sets different link parameters.
5317  * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
5318  * @info: pointer to the structure with parameters given by ethtool to set
5319  * link information.
5320  * Description:
5321  * The function sets different link parameters provided by the user onto
5322  * the NIC.
5323  * Return value:
5324  * 0 on success.
5325  */
5326
5327 static int s2io_ethtool_sset(struct net_device *dev,
5328                              struct ethtool_cmd *info)
5329 {
5330         struct s2io_nic *sp = netdev_priv(dev);
5331         if ((info->autoneg == AUTONEG_ENABLE) ||
5332             (ethtool_cmd_speed(info) != SPEED_10000) ||
5333             (info->duplex != DUPLEX_FULL))
5334                 return -EINVAL;
5335         else {
5336                 s2io_close(sp->dev);
5337                 s2io_open(sp->dev);
5338         }
5339
5340         return 0;
5341 }
5342
5343 /**
5344  * s2io_ethtol_gset - Return link specific information.
5345  * @sp : private member of the device structure, pointer to the
5346  *      s2io_nic structure.
5347  * @info : pointer to the structure with parameters given by ethtool
5348  * to return link information.
5349  * Description:
5350  * Returns link specific information like speed, duplex etc.. to ethtool.
5351  * Return value :
5352  * return 0 on success.
5353  */
5354
5355 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5356 {
5357         struct s2io_nic *sp = netdev_priv(dev);
5358         info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5359         info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5360         info->port = PORT_FIBRE;
5361
5362         /* info->transceiver */
5363         info->transceiver = XCVR_EXTERNAL;
5364
5365         if (netif_carrier_ok(sp->dev)) {
5366                 ethtool_cmd_speed_set(info, SPEED_10000);
5367                 info->duplex = DUPLEX_FULL;
5368         } else {
5369                 ethtool_cmd_speed_set(info, -1);
5370                 info->duplex = -1;
5371         }
5372
5373         info->autoneg = AUTONEG_DISABLE;
5374         return 0;
5375 }
5376
5377 /**
5378  * s2io_ethtool_gdrvinfo - Returns driver specific information.
5379  * @sp : private member of the device structure, which is a pointer to the
5380  * s2io_nic structure.
5381  * @info : pointer to the structure with parameters given by ethtool to
5382  * return driver information.
5383  * Description:
5384  * Returns driver specefic information like name, version etc.. to ethtool.
5385  * Return value:
5386  *  void
5387  */
5388
5389 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5390                                   struct ethtool_drvinfo *info)
5391 {
5392         struct s2io_nic *sp = netdev_priv(dev);
5393
5394         strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5395         strncpy(info->version, s2io_driver_version, sizeof(info->version));
5396         strncpy(info->fw_version, "", sizeof(info->fw_version));
5397         strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5398         info->regdump_len = XENA_REG_SPACE;
5399         info->eedump_len = XENA_EEPROM_SPACE;
5400 }
5401
5402 /**
5403  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5404  *  @sp: private member of the device structure, which is a pointer to the
5405  *  s2io_nic structure.
5406  *  @regs : pointer to the structure with parameters given by ethtool for
5407  *  dumping the registers.
5408  *  @reg_space: The input argumnet into which all the registers are dumped.
5409  *  Description:
5410  *  Dumps the entire register space of xFrame NIC into the user given
5411  *  buffer area.
5412  * Return value :
5413  * void .
5414  */
5415
5416 static void s2io_ethtool_gregs(struct net_device *dev,
5417                                struct ethtool_regs *regs, void *space)
5418 {
5419         int i;
5420         u64 reg;
5421         u8 *reg_space = (u8 *)space;
5422         struct s2io_nic *sp = netdev_priv(dev);
5423
5424         regs->len = XENA_REG_SPACE;
5425         regs->version = sp->pdev->subsystem_device;
5426
5427         for (i = 0; i < regs->len; i += 8) {
5428                 reg = readq(sp->bar0 + i);
5429                 memcpy((reg_space + i), &reg, 8);
5430         }
5431 }
5432
5433 /*
5434  *  s2io_set_led - control NIC led
5435  */
5436 static void s2io_set_led(struct s2io_nic *sp, bool on)
5437 {
5438         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5439         u16 subid = sp->pdev->subsystem_device;
5440         u64 val64;
5441
5442         if ((sp->device_type == XFRAME_II_DEVICE) ||
5443             ((subid & 0xFF) >= 0x07)) {
5444                 val64 = readq(&bar0->gpio_control);
5445                 if (on)
5446                         val64 |= GPIO_CTRL_GPIO_0;
5447                 else
5448                         val64 &= ~GPIO_CTRL_GPIO_0;
5449
5450                 writeq(val64, &bar0->gpio_control);
5451         } else {
5452                 val64 = readq(&bar0->adapter_control);
5453                 if (on)
5454                         val64 |= ADAPTER_LED_ON;
5455                 else
5456                         val64 &= ~ADAPTER_LED_ON;
5457
5458                 writeq(val64, &bar0->adapter_control);
5459         }
5460
5461 }
5462
5463 /**
5464  * s2io_ethtool_set_led - To physically identify the nic on the system.
5465  * @dev : network device
5466  * @state: led setting
5467  *
5468  * Description: Used to physically identify the NIC on the system.
5469  * The Link LED will blink for a time specified by the user for
5470  * identification.
5471  * NOTE: The Link has to be Up to be able to blink the LED. Hence
5472  * identification is possible only if it's link is up.
5473  */
5474
5475 static int s2io_ethtool_set_led(struct net_device *dev,
5476                                 enum ethtool_phys_id_state state)
5477 {
5478         struct s2io_nic *sp = netdev_priv(dev);
5479         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5480         u16 subid = sp->pdev->subsystem_device;
5481
5482         if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
5483                 u64 val64 = readq(&bar0->adapter_control);
5484                 if (!(val64 & ADAPTER_CNTL_EN)) {
5485                         pr_err("Adapter Link down, cannot blink LED\n");
5486                         return -EAGAIN;
5487                 }
5488         }
5489
5490         switch (state) {
5491         case ETHTOOL_ID_ACTIVE:
5492                 sp->adapt_ctrl_org = readq(&bar0->gpio_control);
5493                 return 1;       /* cycle on/off once per second */
5494
5495         case ETHTOOL_ID_ON:
5496                 s2io_set_led(sp, true);
5497                 break;
5498
5499         case ETHTOOL_ID_OFF:
5500                 s2io_set_led(sp, false);
5501                 break;