s2io.c: Standardize statistics accessors
[linux-2.6.git] / drivers / net / s2io.c
1 /************************************************************************
2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3  * Copyright(c) 2002-2007 Neterion Inc.
4  *
5  * This software may be used and distributed according to the terms of
6  * the GNU General Public License (GPL), incorporated herein by reference.
7  * Drivers based on or derived from this code fall under the GPL and must
8  * retain the authorship, copyright and license notice.  This file is not
9  * a complete program and may only be used when the entire operating
10  * system is licensed under the GPL.
11  * See the file COPYING in this distribution for more information.
12  *
13  * Credits:
14  * Jeff Garzik          : For pointing out the improper error condition
15  *                        check in the s2io_xmit routine and also some
16  *                        issues in the Tx watch dog function. Also for
17  *                        patiently answering all those innumerable
18  *                        questions regaring the 2.6 porting issues.
19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
20  *                        macros available only in 2.6 Kernel.
21  * Francois Romieu      : For pointing out all code part that were
22  *                        deprecated and also styling related comments.
23  * Grant Grundler       : For helping me get rid of some Architecture
24  *                        dependent code.
25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
26  *
27  * The module loadable parameters that are supported by the driver and a brief
28  * explanation of all the variables.
29  *
30  * rx_ring_num : This can be used to program the number of receive rings used
31  * in the driver.
32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
33  *     This is also an array of size 8.
34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35  *              values are 1, 2.
36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
38  * Tx descriptors that can be associated with each corresponding FIFO.
39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40  *     2(MSI_X). Default value is '2(MSI_X)'
41  * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
42  *     Possible values '1' for enable '0' for disable. Default is '0'
43  * lro_max_pkts: This parameter defines maximum number of packets can be
44  *     aggregated as a single large packet
45  * napi: This parameter used to enable/disable NAPI (polling Rx)
46  *     Possible values '1' for enable and '0' for disable. Default is '1'
47  * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48  *      Possible values '1' for enable and '0' for disable. Default is '0'
49  * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50  *                 Possible values '1' for enable , '0' for disable.
51  *                 Default is '2' - which means disable in promisc mode
52  *                 and enable in non-promiscuous mode.
53  * multiq: This parameter used to enable/disable MULTIQUEUE support.
54  *      Possible values '1' for enable and '0' for disable. Default is '0'
55  ************************************************************************/
56
57 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
58
59 #include <linux/module.h>
60 #include <linux/types.h>
61 #include <linux/errno.h>
62 #include <linux/ioport.h>
63 #include <linux/pci.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/kernel.h>
66 #include <linux/netdevice.h>
67 #include <linux/etherdevice.h>
68 #include <linux/mdio.h>
69 #include <linux/skbuff.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/stddef.h>
73 #include <linux/ioctl.h>
74 #include <linux/timex.h>
75 #include <linux/ethtool.h>
76 #include <linux/workqueue.h>
77 #include <linux/if_vlan.h>
78 #include <linux/ip.h>
79 #include <linux/tcp.h>
80 #include <linux/uaccess.h>
81 #include <linux/io.h>
82 #include <net/tcp.h>
83
84 #include <asm/system.h>
85 #include <asm/div64.h>
86 #include <asm/irq.h>
87
88 /* local include */
89 #include "s2io.h"
90 #include "s2io-regs.h"
91
92 #define DRV_VERSION "2.0.26.25"
93
94 /* S2io Driver name & version. */
95 static char s2io_driver_name[] = "Neterion";
96 static char s2io_driver_version[] = DRV_VERSION;
97
98 static int rxd_size[2] = {32, 48};
99 static int rxd_count[2] = {127, 85};
100
101 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
102 {
103         int ret;
104
105         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
106                (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
107
108         return ret;
109 }
110
111 /*
112  * Cards with following subsystem_id have a link state indication
113  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
114  * macro below identifies these cards given the subsystem_id.
115  */
116 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid)              \
117         (dev_type == XFRAME_I_DEVICE) ?                                 \
118         ((((subid >= 0x600B) && (subid <= 0x600D)) ||                   \
119           ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
120
121 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
122                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
123
124 static inline int is_s2io_card_up(const struct s2io_nic *sp)
125 {
126         return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
127 }
128
129 /* Ethtool related variables and Macros. */
130 static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
131         "Register test\t(offline)",
132         "Eeprom test\t(offline)",
133         "Link test\t(online)",
134         "RLDRAM test\t(offline)",
135         "BIST Test\t(offline)"
136 };
137
138 static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
139         {"tmac_frms"},
140         {"tmac_data_octets"},
141         {"tmac_drop_frms"},
142         {"tmac_mcst_frms"},
143         {"tmac_bcst_frms"},
144         {"tmac_pause_ctrl_frms"},
145         {"tmac_ttl_octets"},
146         {"tmac_ucst_frms"},
147         {"tmac_nucst_frms"},
148         {"tmac_any_err_frms"},
149         {"tmac_ttl_less_fb_octets"},
150         {"tmac_vld_ip_octets"},
151         {"tmac_vld_ip"},
152         {"tmac_drop_ip"},
153         {"tmac_icmp"},
154         {"tmac_rst_tcp"},
155         {"tmac_tcp"},
156         {"tmac_udp"},
157         {"rmac_vld_frms"},
158         {"rmac_data_octets"},
159         {"rmac_fcs_err_frms"},
160         {"rmac_drop_frms"},
161         {"rmac_vld_mcst_frms"},
162         {"rmac_vld_bcst_frms"},
163         {"rmac_in_rng_len_err_frms"},
164         {"rmac_out_rng_len_err_frms"},
165         {"rmac_long_frms"},
166         {"rmac_pause_ctrl_frms"},
167         {"rmac_unsup_ctrl_frms"},
168         {"rmac_ttl_octets"},
169         {"rmac_accepted_ucst_frms"},
170         {"rmac_accepted_nucst_frms"},
171         {"rmac_discarded_frms"},
172         {"rmac_drop_events"},
173         {"rmac_ttl_less_fb_octets"},
174         {"rmac_ttl_frms"},
175         {"rmac_usized_frms"},
176         {"rmac_osized_frms"},
177         {"rmac_frag_frms"},
178         {"rmac_jabber_frms"},
179         {"rmac_ttl_64_frms"},
180         {"rmac_ttl_65_127_frms"},
181         {"rmac_ttl_128_255_frms"},
182         {"rmac_ttl_256_511_frms"},
183         {"rmac_ttl_512_1023_frms"},
184         {"rmac_ttl_1024_1518_frms"},
185         {"rmac_ip"},
186         {"rmac_ip_octets"},
187         {"rmac_hdr_err_ip"},
188         {"rmac_drop_ip"},
189         {"rmac_icmp"},
190         {"rmac_tcp"},
191         {"rmac_udp"},
192         {"rmac_err_drp_udp"},
193         {"rmac_xgmii_err_sym"},
194         {"rmac_frms_q0"},
195         {"rmac_frms_q1"},
196         {"rmac_frms_q2"},
197         {"rmac_frms_q3"},
198         {"rmac_frms_q4"},
199         {"rmac_frms_q5"},
200         {"rmac_frms_q6"},
201         {"rmac_frms_q7"},
202         {"rmac_full_q0"},
203         {"rmac_full_q1"},
204         {"rmac_full_q2"},
205         {"rmac_full_q3"},
206         {"rmac_full_q4"},
207         {"rmac_full_q5"},
208         {"rmac_full_q6"},
209         {"rmac_full_q7"},
210         {"rmac_pause_cnt"},
211         {"rmac_xgmii_data_err_cnt"},
212         {"rmac_xgmii_ctrl_err_cnt"},
213         {"rmac_accepted_ip"},
214         {"rmac_err_tcp"},
215         {"rd_req_cnt"},
216         {"new_rd_req_cnt"},
217         {"new_rd_req_rtry_cnt"},
218         {"rd_rtry_cnt"},
219         {"wr_rtry_rd_ack_cnt"},
220         {"wr_req_cnt"},
221         {"new_wr_req_cnt"},
222         {"new_wr_req_rtry_cnt"},
223         {"wr_rtry_cnt"},
224         {"wr_disc_cnt"},
225         {"rd_rtry_wr_ack_cnt"},
226         {"txp_wr_cnt"},
227         {"txd_rd_cnt"},
228         {"txd_wr_cnt"},
229         {"rxd_rd_cnt"},
230         {"rxd_wr_cnt"},
231         {"txf_rd_cnt"},
232         {"rxf_wr_cnt"}
233 };
234
235 static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
236         {"rmac_ttl_1519_4095_frms"},
237         {"rmac_ttl_4096_8191_frms"},
238         {"rmac_ttl_8192_max_frms"},
239         {"rmac_ttl_gt_max_frms"},
240         {"rmac_osized_alt_frms"},
241         {"rmac_jabber_alt_frms"},
242         {"rmac_gt_max_alt_frms"},
243         {"rmac_vlan_frms"},
244         {"rmac_len_discard"},
245         {"rmac_fcs_discard"},
246         {"rmac_pf_discard"},
247         {"rmac_da_discard"},
248         {"rmac_red_discard"},
249         {"rmac_rts_discard"},
250         {"rmac_ingm_full_discard"},
251         {"link_fault_cnt"}
252 };
253
254 static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
255         {"\n DRIVER STATISTICS"},
256         {"single_bit_ecc_errs"},
257         {"double_bit_ecc_errs"},
258         {"parity_err_cnt"},
259         {"serious_err_cnt"},
260         {"soft_reset_cnt"},
261         {"fifo_full_cnt"},
262         {"ring_0_full_cnt"},
263         {"ring_1_full_cnt"},
264         {"ring_2_full_cnt"},
265         {"ring_3_full_cnt"},
266         {"ring_4_full_cnt"},
267         {"ring_5_full_cnt"},
268         {"ring_6_full_cnt"},
269         {"ring_7_full_cnt"},
270         {"alarm_transceiver_temp_high"},
271         {"alarm_transceiver_temp_low"},
272         {"alarm_laser_bias_current_high"},
273         {"alarm_laser_bias_current_low"},
274         {"alarm_laser_output_power_high"},
275         {"alarm_laser_output_power_low"},
276         {"warn_transceiver_temp_high"},
277         {"warn_transceiver_temp_low"},
278         {"warn_laser_bias_current_high"},
279         {"warn_laser_bias_current_low"},
280         {"warn_laser_output_power_high"},
281         {"warn_laser_output_power_low"},
282         {"lro_aggregated_pkts"},
283         {"lro_flush_both_count"},
284         {"lro_out_of_sequence_pkts"},
285         {"lro_flush_due_to_max_pkts"},
286         {"lro_avg_aggr_pkts"},
287         {"mem_alloc_fail_cnt"},
288         {"pci_map_fail_cnt"},
289         {"watchdog_timer_cnt"},
290         {"mem_allocated"},
291         {"mem_freed"},
292         {"link_up_cnt"},
293         {"link_down_cnt"},
294         {"link_up_time"},
295         {"link_down_time"},
296         {"tx_tcode_buf_abort_cnt"},
297         {"tx_tcode_desc_abort_cnt"},
298         {"tx_tcode_parity_err_cnt"},
299         {"tx_tcode_link_loss_cnt"},
300         {"tx_tcode_list_proc_err_cnt"},
301         {"rx_tcode_parity_err_cnt"},
302         {"rx_tcode_abort_cnt"},
303         {"rx_tcode_parity_abort_cnt"},
304         {"rx_tcode_rda_fail_cnt"},
305         {"rx_tcode_unkn_prot_cnt"},
306         {"rx_tcode_fcs_err_cnt"},
307         {"rx_tcode_buf_size_err_cnt"},
308         {"rx_tcode_rxd_corrupt_cnt"},
309         {"rx_tcode_unkn_err_cnt"},
310         {"tda_err_cnt"},
311         {"pfc_err_cnt"},
312         {"pcc_err_cnt"},
313         {"tti_err_cnt"},
314         {"tpa_err_cnt"},
315         {"sm_err_cnt"},
316         {"lso_err_cnt"},
317         {"mac_tmac_err_cnt"},
318         {"mac_rmac_err_cnt"},
319         {"xgxs_txgxs_err_cnt"},
320         {"xgxs_rxgxs_err_cnt"},
321         {"rc_err_cnt"},
322         {"prc_pcix_err_cnt"},
323         {"rpa_err_cnt"},
324         {"rda_err_cnt"},
325         {"rti_err_cnt"},
326         {"mc_err_cnt"}
327 };
328
329 #define S2IO_XENA_STAT_LEN      ARRAY_SIZE(ethtool_xena_stats_keys)
330 #define S2IO_ENHANCED_STAT_LEN  ARRAY_SIZE(ethtool_enhanced_stats_keys)
331 #define S2IO_DRIVER_STAT_LEN    ARRAY_SIZE(ethtool_driver_stats_keys)
332
333 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
334 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
335
336 #define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
337 #define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
338
339 #define S2IO_TEST_LEN   ARRAY_SIZE(s2io_gstrings)
340 #define S2IO_STRINGS_LEN        (S2IO_TEST_LEN * ETH_GSTRING_LEN)
341
342 #define S2IO_TIMER_CONF(timer, handle, arg, exp)        \
343         init_timer(&timer);                             \
344         timer.function = handle;                        \
345         timer.data = (unsigned long)arg;                \
346         mod_timer(&timer, (jiffies + exp))              \
347
348 /* copy mac addr to def_mac_addr array */
349 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
350 {
351         sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
352         sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
353         sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
354         sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
355         sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
356         sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
357 }
358
359 /* Add the vlan */
360 static void s2io_vlan_rx_register(struct net_device *dev,
361                                   struct vlan_group *grp)
362 {
363         int i;
364         struct s2io_nic *nic = netdev_priv(dev);
365         unsigned long flags[MAX_TX_FIFOS];
366         struct config_param *config = &nic->config;
367         struct mac_info *mac_control = &nic->mac_control;
368
369         for (i = 0; i < config->tx_fifo_num; i++) {
370                 struct fifo_info *fifo = &mac_control->fifos[i];
371
372                 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
373         }
374
375         nic->vlgrp = grp;
376
377         for (i = config->tx_fifo_num - 1; i >= 0; i--) {
378                 struct fifo_info *fifo = &mac_control->fifos[i];
379
380                 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
381         }
382 }
383
384 /* Unregister the vlan */
385 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
386 {
387         int i;
388         struct s2io_nic *nic = netdev_priv(dev);
389         unsigned long flags[MAX_TX_FIFOS];
390         struct config_param *config = &nic->config;
391         struct mac_info *mac_control = &nic->mac_control;
392
393         for (i = 0; i < config->tx_fifo_num; i++) {
394                 struct fifo_info *fifo = &mac_control->fifos[i];
395
396                 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
397         }
398
399         if (nic->vlgrp)
400                 vlan_group_set_device(nic->vlgrp, vid, NULL);
401
402         for (i = config->tx_fifo_num - 1; i >= 0; i--) {
403                 struct fifo_info *fifo = &mac_control->fifos[i];
404
405                 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
406         }
407 }
408
409 /*
410  * Constants to be programmed into the Xena's registers, to configure
411  * the XAUI.
412  */
413
414 #define END_SIGN        0x0
415 static const u64 herc_act_dtx_cfg[] = {
416         /* Set address */
417         0x8000051536750000ULL, 0x80000515367500E0ULL,
418         /* Write data */
419         0x8000051536750004ULL, 0x80000515367500E4ULL,
420         /* Set address */
421         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
422         /* Write data */
423         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
424         /* Set address */
425         0x801205150D440000ULL, 0x801205150D4400E0ULL,
426         /* Write data */
427         0x801205150D440004ULL, 0x801205150D4400E4ULL,
428         /* Set address */
429         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
430         /* Write data */
431         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
432         /* Done */
433         END_SIGN
434 };
435
436 static const u64 xena_dtx_cfg[] = {
437         /* Set address */
438         0x8000051500000000ULL, 0x80000515000000E0ULL,
439         /* Write data */
440         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
441         /* Set address */
442         0x8001051500000000ULL, 0x80010515000000E0ULL,
443         /* Write data */
444         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
445         /* Set address */
446         0x8002051500000000ULL, 0x80020515000000E0ULL,
447         /* Write data */
448         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
449         END_SIGN
450 };
451
452 /*
453  * Constants for Fixing the MacAddress problem seen mostly on
454  * Alpha machines.
455  */
456 static const u64 fix_mac[] = {
457         0x0060000000000000ULL, 0x0060600000000000ULL,
458         0x0040600000000000ULL, 0x0000600000000000ULL,
459         0x0020600000000000ULL, 0x0060600000000000ULL,
460         0x0020600000000000ULL, 0x0060600000000000ULL,
461         0x0020600000000000ULL, 0x0060600000000000ULL,
462         0x0020600000000000ULL, 0x0060600000000000ULL,
463         0x0020600000000000ULL, 0x0060600000000000ULL,
464         0x0020600000000000ULL, 0x0060600000000000ULL,
465         0x0020600000000000ULL, 0x0060600000000000ULL,
466         0x0020600000000000ULL, 0x0060600000000000ULL,
467         0x0020600000000000ULL, 0x0060600000000000ULL,
468         0x0020600000000000ULL, 0x0060600000000000ULL,
469         0x0020600000000000ULL, 0x0000600000000000ULL,
470         0x0040600000000000ULL, 0x0060600000000000ULL,
471         END_SIGN
472 };
473
474 MODULE_LICENSE("GPL");
475 MODULE_VERSION(DRV_VERSION);
476
477
478 /* Module Loadable parameters. */
479 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
480 S2IO_PARM_INT(rx_ring_num, 1);
481 S2IO_PARM_INT(multiq, 0);
482 S2IO_PARM_INT(rx_ring_mode, 1);
483 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
484 S2IO_PARM_INT(rmac_pause_time, 0x100);
485 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
486 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
487 S2IO_PARM_INT(shared_splits, 0);
488 S2IO_PARM_INT(tmac_util_period, 5);
489 S2IO_PARM_INT(rmac_util_period, 5);
490 S2IO_PARM_INT(l3l4hdr_size, 128);
491 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
492 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
493 /* Frequency of Rx desc syncs expressed as power of 2 */
494 S2IO_PARM_INT(rxsync_frequency, 3);
495 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
496 S2IO_PARM_INT(intr_type, 2);
497 /* Large receive offload feature */
498 static unsigned int lro_enable;
499 module_param_named(lro, lro_enable, uint, 0);
500
501 /* Max pkts to be aggregated by LRO at one time. If not specified,
502  * aggregation happens until we hit max IP pkt size(64K)
503  */
504 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
505 S2IO_PARM_INT(indicate_max_pkts, 0);
506
507 S2IO_PARM_INT(napi, 1);
508 S2IO_PARM_INT(ufo, 0);
509 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
510
511 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
512 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
513 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
514 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
515 static unsigned int rts_frm_len[MAX_RX_RINGS] =
516 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
517
518 module_param_array(tx_fifo_len, uint, NULL, 0);
519 module_param_array(rx_ring_sz, uint, NULL, 0);
520 module_param_array(rts_frm_len, uint, NULL, 0);
521
522 /*
523  * S2IO device table.
524  * This table lists all the devices that this driver supports.
525  */
526 static struct pci_device_id s2io_tbl[] __devinitdata = {
527         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
528          PCI_ANY_ID, PCI_ANY_ID},
529         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
530          PCI_ANY_ID, PCI_ANY_ID},
531         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
532          PCI_ANY_ID, PCI_ANY_ID},
533         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
534          PCI_ANY_ID, PCI_ANY_ID},
535         {0,}
536 };
537
538 MODULE_DEVICE_TABLE(pci, s2io_tbl);
539
540 static struct pci_error_handlers s2io_err_handler = {
541         .error_detected = s2io_io_error_detected,
542         .slot_reset = s2io_io_slot_reset,
543         .resume = s2io_io_resume,
544 };
545
546 static struct pci_driver s2io_driver = {
547         .name = "S2IO",
548         .id_table = s2io_tbl,
549         .probe = s2io_init_nic,
550         .remove = __devexit_p(s2io_rem_nic),
551         .err_handler = &s2io_err_handler,
552 };
553
554 /* A simplifier macro used both by init and free shared_mem Fns(). */
555 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
556
557 /* netqueue manipulation helper functions */
558 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
559 {
560         if (!sp->config.multiq) {
561                 int i;
562
563                 for (i = 0; i < sp->config.tx_fifo_num; i++)
564                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
565         }
566         netif_tx_stop_all_queues(sp->dev);
567 }
568
569 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
570 {
571         if (!sp->config.multiq)
572                 sp->mac_control.fifos[fifo_no].queue_state =
573                         FIFO_QUEUE_STOP;
574
575         netif_tx_stop_all_queues(sp->dev);
576 }
577
578 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
579 {
580         if (!sp->config.multiq) {
581                 int i;
582
583                 for (i = 0; i < sp->config.tx_fifo_num; i++)
584                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
585         }
586         netif_tx_start_all_queues(sp->dev);
587 }
588
589 static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
590 {
591         if (!sp->config.multiq)
592                 sp->mac_control.fifos[fifo_no].queue_state =
593                         FIFO_QUEUE_START;
594
595         netif_tx_start_all_queues(sp->dev);
596 }
597
598 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
599 {
600         if (!sp->config.multiq) {
601                 int i;
602
603                 for (i = 0; i < sp->config.tx_fifo_num; i++)
604                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
605         }
606         netif_tx_wake_all_queues(sp->dev);
607 }
608
609 static inline void s2io_wake_tx_queue(
610         struct fifo_info *fifo, int cnt, u8 multiq)
611 {
612
613         if (multiq) {
614                 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
615                         netif_wake_subqueue(fifo->dev, fifo->fifo_no);
616         } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
617                 if (netif_queue_stopped(fifo->dev)) {
618                         fifo->queue_state = FIFO_QUEUE_START;
619                         netif_wake_queue(fifo->dev);
620                 }
621         }
622 }
623
624 /**
625  * init_shared_mem - Allocation and Initialization of Memory
626  * @nic: Device private variable.
627  * Description: The function allocates all the memory areas shared
628  * between the NIC and the driver. This includes Tx descriptors,
629  * Rx descriptors and the statistics block.
630  */
631
632 static int init_shared_mem(struct s2io_nic *nic)
633 {
634         u32 size;
635         void *tmp_v_addr, *tmp_v_addr_next;
636         dma_addr_t tmp_p_addr, tmp_p_addr_next;
637         struct RxD_block *pre_rxd_blk = NULL;
638         int i, j, blk_cnt;
639         int lst_size, lst_per_page;
640         struct net_device *dev = nic->dev;
641         unsigned long tmp;
642         struct buffAdd *ba;
643         struct config_param *config = &nic->config;
644         struct mac_info *mac_control = &nic->mac_control;
645         unsigned long long mem_allocated = 0;
646
647         /* Allocation and initialization of TXDLs in FIFOs */
648         size = 0;
649         for (i = 0; i < config->tx_fifo_num; i++) {
650                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
651
652                 size += tx_cfg->fifo_len;
653         }
654         if (size > MAX_AVAILABLE_TXDS) {
655                 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
656                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n",
657                           size);
658                 return -EINVAL;
659         }
660
661         size = 0;
662         for (i = 0; i < config->tx_fifo_num; i++) {
663                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
664
665                 size = tx_cfg->fifo_len;
666                 /*
667                  * Legal values are from 2 to 8192
668                  */
669                 if (size < 2) {
670                         DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size);
671                         DBG_PRINT(ERR_DBG, "for fifo %d\n", i);
672                         DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len"
673                                   "are 2 to 8192\n");
674                         return -EINVAL;
675                 }
676         }
677
678         lst_size = (sizeof(struct TxD) * config->max_txds);
679         lst_per_page = PAGE_SIZE / lst_size;
680
681         for (i = 0; i < config->tx_fifo_num; i++) {
682                 struct fifo_info *fifo = &mac_control->fifos[i];
683                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
684                 int fifo_len = tx_cfg->fifo_len;
685                 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
686
687                 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
688                 if (!fifo->list_info) {
689                         DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
690                         return -ENOMEM;
691                 }
692                 mem_allocated += list_holder_size;
693         }
694         for (i = 0; i < config->tx_fifo_num; i++) {
695                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
696                                                 lst_per_page);
697                 struct fifo_info *fifo = &mac_control->fifos[i];
698                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
699
700                 fifo->tx_curr_put_info.offset = 0;
701                 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
702                 fifo->tx_curr_get_info.offset = 0;
703                 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
704                 fifo->fifo_no = i;
705                 fifo->nic = nic;
706                 fifo->max_txds = MAX_SKB_FRAGS + 2;
707                 fifo->dev = dev;
708
709                 for (j = 0; j < page_num; j++) {
710                         int k = 0;
711                         dma_addr_t tmp_p;
712                         void *tmp_v;
713                         tmp_v = pci_alloc_consistent(nic->pdev,
714                                                      PAGE_SIZE, &tmp_p);
715                         if (!tmp_v) {
716                                 DBG_PRINT(INFO_DBG, "pci_alloc_consistent ");
717                                 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
718                                 return -ENOMEM;
719                         }
720                         /* If we got a zero DMA address(can happen on
721                          * certain platforms like PPC), reallocate.
722                          * Store virtual address of page we don't want,
723                          * to be freed later.
724                          */
725                         if (!tmp_p) {
726                                 mac_control->zerodma_virt_addr = tmp_v;
727                                 DBG_PRINT(INIT_DBG,
728                                           "%s: Zero DMA address for TxDL. ",
729                                           dev->name);
730                                 DBG_PRINT(INIT_DBG,
731                                           "Virtual address %p\n", tmp_v);
732                                 tmp_v = pci_alloc_consistent(nic->pdev,
733                                                              PAGE_SIZE, &tmp_p);
734                                 if (!tmp_v) {
735                                         DBG_PRINT(INFO_DBG,
736                                                   "pci_alloc_consistent ");
737                                         DBG_PRINT(INFO_DBG,
738                                                   "failed for TxDL\n");
739                                         return -ENOMEM;
740                                 }
741                                 mem_allocated += PAGE_SIZE;
742                         }
743                         while (k < lst_per_page) {
744                                 int l = (j * lst_per_page) + k;
745                                 if (l == tx_cfg->fifo_len)
746                                         break;
747                                 fifo->list_info[l].list_virt_addr =
748                                         tmp_v + (k * lst_size);
749                                 fifo->list_info[l].list_phy_addr =
750                                         tmp_p + (k * lst_size);
751                                 k++;
752                         }
753                 }
754         }
755
756         for (i = 0; i < config->tx_fifo_num; i++) {
757                 struct fifo_info *fifo = &mac_control->fifos[i];
758                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
759
760                 size = tx_cfg->fifo_len;
761                 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
762                 if (!fifo->ufo_in_band_v)
763                         return -ENOMEM;
764                 mem_allocated += (size * sizeof(u64));
765         }
766
767         /* Allocation and initialization of RXDs in Rings */
768         size = 0;
769         for (i = 0; i < config->rx_ring_num; i++) {
770                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
771                 struct ring_info *ring = &mac_control->rings[i];
772
773                 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
774                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
775                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ", i);
776                         DBG_PRINT(ERR_DBG, "RxDs per Block");
777                         return FAILURE;
778                 }
779                 size += rx_cfg->num_rxd;
780                 ring->block_count = rx_cfg->num_rxd /
781                         (rxd_count[nic->rxd_mode] + 1);
782                 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
783         }
784         if (nic->rxd_mode == RXD_MODE_1)
785                 size = (size * (sizeof(struct RxD1)));
786         else
787                 size = (size * (sizeof(struct RxD3)));
788
789         for (i = 0; i < config->rx_ring_num; i++) {
790                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
791                 struct ring_info *ring = &mac_control->rings[i];
792
793                 ring->rx_curr_get_info.block_index = 0;
794                 ring->rx_curr_get_info.offset = 0;
795                 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
796                 ring->rx_curr_put_info.block_index = 0;
797                 ring->rx_curr_put_info.offset = 0;
798                 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
799                 ring->nic = nic;
800                 ring->ring_no = i;
801                 ring->lro = lro_enable;
802
803                 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
804                 /*  Allocating all the Rx blocks */
805                 for (j = 0; j < blk_cnt; j++) {
806                         struct rx_block_info *rx_blocks;
807                         int l;
808
809                         rx_blocks = &ring->rx_blocks[j];
810                         size = SIZE_OF_BLOCK;   /* size is always page size */
811                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
812                                                           &tmp_p_addr);
813                         if (tmp_v_addr == NULL) {
814                                 /*
815                                  * In case of failure, free_shared_mem()
816                                  * is called, which should free any
817                                  * memory that was alloced till the
818                                  * failure happened.
819                                  */
820                                 rx_blocks->block_virt_addr = tmp_v_addr;
821                                 return -ENOMEM;
822                         }
823                         mem_allocated += size;
824                         memset(tmp_v_addr, 0, size);
825
826                         size = sizeof(struct rxd_info) *
827                                 rxd_count[nic->rxd_mode];
828                         rx_blocks->block_virt_addr = tmp_v_addr;
829                         rx_blocks->block_dma_addr = tmp_p_addr;
830                         rx_blocks->rxds = kmalloc(size,  GFP_KERNEL);
831                         if (!rx_blocks->rxds)
832                                 return -ENOMEM;
833                         mem_allocated += size;
834                         for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
835                                 rx_blocks->rxds[l].virt_addr =
836                                         rx_blocks->block_virt_addr +
837                                         (rxd_size[nic->rxd_mode] * l);
838                                 rx_blocks->rxds[l].dma_addr =
839                                         rx_blocks->block_dma_addr +
840                                         (rxd_size[nic->rxd_mode] * l);
841                         }
842                 }
843                 /* Interlinking all Rx Blocks */
844                 for (j = 0; j < blk_cnt; j++) {
845                         int next = (j + 1) % blk_cnt;
846                         tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
847                         tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
848                         tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
849                         tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
850
851                         pre_rxd_blk = (struct RxD_block *)tmp_v_addr;
852                         pre_rxd_blk->reserved_2_pNext_RxD_block =
853                                 (unsigned long)tmp_v_addr_next;
854                         pre_rxd_blk->pNext_RxD_Blk_physical =
855                                 (u64)tmp_p_addr_next;
856                 }
857         }
858         if (nic->rxd_mode == RXD_MODE_3B) {
859                 /*
860                  * Allocation of Storages for buffer addresses in 2BUFF mode
861                  * and the buffers as well.
862                  */
863                 for (i = 0; i < config->rx_ring_num; i++) {
864                         struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
865                         struct ring_info *ring = &mac_control->rings[i];
866
867                         blk_cnt = rx_cfg->num_rxd /
868                                 (rxd_count[nic->rxd_mode] + 1);
869                         size = sizeof(struct buffAdd *) * blk_cnt;
870                         ring->ba = kmalloc(size, GFP_KERNEL);
871                         if (!ring->ba)
872                                 return -ENOMEM;
873                         mem_allocated += size;
874                         for (j = 0; j < blk_cnt; j++) {
875                                 int k = 0;
876
877                                 size = sizeof(struct buffAdd) *
878                                         (rxd_count[nic->rxd_mode] + 1);
879                                 ring->ba[j] = kmalloc(size, GFP_KERNEL);
880                                 if (!ring->ba[j])
881                                         return -ENOMEM;
882                                 mem_allocated += size;
883                                 while (k != rxd_count[nic->rxd_mode]) {
884                                         ba = &ring->ba[j][k];
885                                         size = BUF0_LEN + ALIGN_SIZE;
886                                         ba->ba_0_org = kmalloc(size, GFP_KERNEL);
887                                         if (!ba->ba_0_org)
888                                                 return -ENOMEM;
889                                         mem_allocated += size;
890                                         tmp = (unsigned long)ba->ba_0_org;
891                                         tmp += ALIGN_SIZE;
892                                         tmp &= ~((unsigned long)ALIGN_SIZE);
893                                         ba->ba_0 = (void *)tmp;
894
895                                         size = BUF1_LEN + ALIGN_SIZE;
896                                         ba->ba_1_org = kmalloc(size, GFP_KERNEL);
897                                         if (!ba->ba_1_org)
898                                                 return -ENOMEM;
899                                         mem_allocated += size;
900                                         tmp = (unsigned long)ba->ba_1_org;
901                                         tmp += ALIGN_SIZE;
902                                         tmp &= ~((unsigned long)ALIGN_SIZE);
903                                         ba->ba_1 = (void *)tmp;
904                                         k++;
905                                 }
906                         }
907                 }
908         }
909
910         /* Allocation and initialization of Statistics block */
911         size = sizeof(struct stat_block);
912         mac_control->stats_mem =
913                 pci_alloc_consistent(nic->pdev, size,
914                                      &mac_control->stats_mem_phy);
915
916         if (!mac_control->stats_mem) {
917                 /*
918                  * In case of failure, free_shared_mem() is called, which
919                  * should free any memory that was alloced till the
920                  * failure happened.
921                  */
922                 return -ENOMEM;
923         }
924         mem_allocated += size;
925         mac_control->stats_mem_sz = size;
926
927         tmp_v_addr = mac_control->stats_mem;
928         mac_control->stats_info = (struct stat_block *)tmp_v_addr;
929         memset(tmp_v_addr, 0, size);
930         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
931                   (unsigned long long)tmp_p_addr);
932         mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
933         return SUCCESS;
934 }
935
936 /**
937  * free_shared_mem - Free the allocated Memory
938  * @nic:  Device private variable.
939  * Description: This function is to free all memory locations allocated by
940  * the init_shared_mem() function and return it to the kernel.
941  */
942
943 static void free_shared_mem(struct s2io_nic *nic)
944 {
945         int i, j, blk_cnt, size;
946         void *tmp_v_addr;
947         dma_addr_t tmp_p_addr;
948         int lst_size, lst_per_page;
949         struct net_device *dev;
950         int page_num = 0;
951         struct config_param *config;
952         struct mac_info *mac_control;
953         struct stat_block *stats;
954         struct swStat *swstats;
955
956         if (!nic)
957                 return;
958
959         dev = nic->dev;
960
961         config = &nic->config;
962         mac_control = &nic->mac_control;
963         stats = mac_control->stats_info;
964         swstats = &stats->sw_stat;
965
966         lst_size = sizeof(struct TxD) * config->max_txds;
967         lst_per_page = PAGE_SIZE / lst_size;
968
969         for (i = 0; i < config->tx_fifo_num; i++) {
970                 struct fifo_info *fifo = &mac_control->fifos[i];
971                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
972
973                 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
974                 for (j = 0; j < page_num; j++) {
975                         int mem_blks = (j * lst_per_page);
976                         struct list_info_hold *fli;
977
978                         if (!fifo->list_info)
979                                 return;
980
981                         fli = &fifo->list_info[mem_blks];
982                         if (!fli->list_virt_addr)
983                                 break;
984                         pci_free_consistent(nic->pdev, PAGE_SIZE,
985                                             fli->list_virt_addr,
986                                             fli->list_phy_addr);
987                         swstats->mem_freed += PAGE_SIZE;
988                 }
989                 /* If we got a zero DMA address during allocation,
990                  * free the page now
991                  */
992                 if (mac_control->zerodma_virt_addr) {
993                         pci_free_consistent(nic->pdev, PAGE_SIZE,
994                                             mac_control->zerodma_virt_addr,
995                                             (dma_addr_t)0);
996                         DBG_PRINT(INIT_DBG,
997                                   "%s: Freeing TxDL with zero DMA addr. ",
998                                   dev->name);
999                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
1000                                   mac_control->zerodma_virt_addr);
1001                         swstats->mem_freed += PAGE_SIZE;
1002                 }
1003                 kfree(fifo->list_info);
1004                 swstats->mem_freed += nic->config.tx_cfg[i].fifo_len *
1005                         sizeof(struct list_info_hold);
1006         }
1007
1008         size = SIZE_OF_BLOCK;
1009         for (i = 0; i < config->rx_ring_num; i++) {
1010                 struct ring_info *ring = &mac_control->rings[i];
1011
1012                 blk_cnt = ring->block_count;
1013                 for (j = 0; j < blk_cnt; j++) {
1014                         tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1015                         tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1016                         if (tmp_v_addr == NULL)
1017                                 break;
1018                         pci_free_consistent(nic->pdev, size,
1019                                             tmp_v_addr, tmp_p_addr);
1020                         swstats->mem_freed += size;
1021                         kfree(ring->rx_blocks[j].rxds);
1022                         swstats->mem_freed += sizeof(struct rxd_info) *
1023                                 rxd_count[nic->rxd_mode];
1024                 }
1025         }
1026
1027         if (nic->rxd_mode == RXD_MODE_3B) {
1028                 /* Freeing buffer storage addresses in 2BUFF mode. */
1029                 for (i = 0; i < config->rx_ring_num; i++) {
1030                         struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1031                         struct ring_info *ring = &mac_control->rings[i];
1032
1033                         blk_cnt = rx_cfg->num_rxd /
1034                                 (rxd_count[nic->rxd_mode] + 1);
1035                         for (j = 0; j < blk_cnt; j++) {
1036                                 int k = 0;
1037                                 if (!ring->ba[j])
1038                                         continue;
1039                                 while (k != rxd_count[nic->rxd_mode]) {
1040                                         struct buffAdd *ba = &ring->ba[j][k];
1041                                         kfree(ba->ba_0_org);
1042                                         swstats->mem_freed +=
1043                                                 BUF0_LEN + ALIGN_SIZE;
1044                                         kfree(ba->ba_1_org);
1045                                         swstats->mem_freed +=
1046                                                 BUF1_LEN + ALIGN_SIZE;
1047                                         k++;
1048                                 }
1049                                 kfree(ring->ba[j]);
1050                                 swstats->mem_freed += sizeof(struct buffAdd) *
1051                                         (rxd_count[nic->rxd_mode] + 1);
1052                         }
1053                         kfree(ring->ba);
1054                         swstats->mem_freed += sizeof(struct buffAdd *) *
1055                                 blk_cnt;
1056                 }
1057         }
1058
1059         for (i = 0; i < nic->config.tx_fifo_num; i++) {
1060                 struct fifo_info *fifo = &mac_control->fifos[i];
1061                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1062
1063                 if (fifo->ufo_in_band_v) {
1064                         swstats->mem_freed += tx_cfg->fifo_len *
1065                                 sizeof(u64);
1066                         kfree(fifo->ufo_in_band_v);
1067                 }
1068         }
1069
1070         if (mac_control->stats_mem) {
1071                 swstats->mem_freed += mac_control->stats_mem_sz;
1072                 pci_free_consistent(nic->pdev,
1073                                     mac_control->stats_mem_sz,
1074                                     mac_control->stats_mem,
1075                                     mac_control->stats_mem_phy);
1076         }
1077 }
1078
1079 /**
1080  * s2io_verify_pci_mode -
1081  */
1082
1083 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1084 {
1085         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1086         register u64 val64 = 0;
1087         int     mode;
1088
1089         val64 = readq(&bar0->pci_mode);
1090         mode = (u8)GET_PCI_MODE(val64);
1091
1092         if (val64 & PCI_MODE_UNKNOWN_MODE)
1093                 return -1;      /* Unknown PCI mode */
1094         return mode;
1095 }
1096
1097 #define NEC_VENID   0x1033
1098 #define NEC_DEVID   0x0125
1099 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1100 {
1101         struct pci_dev *tdev = NULL;
1102         while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1103                 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1104                         if (tdev->bus == s2io_pdev->bus->parent) {
1105                                 pci_dev_put(tdev);
1106                                 return 1;
1107                         }
1108                 }
1109         }
1110         return 0;
1111 }
1112
1113 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1114 /**
1115  * s2io_print_pci_mode -
1116  */
1117 static int s2io_print_pci_mode(struct s2io_nic *nic)
1118 {
1119         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1120         register u64 val64 = 0;
1121         int     mode;
1122         struct config_param *config = &nic->config;
1123
1124         val64 = readq(&bar0->pci_mode);
1125         mode = (u8)GET_PCI_MODE(val64);
1126
1127         if (val64 & PCI_MODE_UNKNOWN_MODE)
1128                 return -1;      /* Unknown PCI mode */
1129
1130         config->bus_speed = bus_speed[mode];
1131
1132         if (s2io_on_nec_bridge(nic->pdev)) {
1133                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1134                           nic->dev->name);
1135                 return mode;
1136         }
1137
1138         DBG_PRINT(ERR_DBG, "%s: Device is on %d bit ",
1139                   nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64);
1140
1141         switch (mode) {
1142         case PCI_MODE_PCI_33:
1143                 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
1144                 break;
1145         case PCI_MODE_PCI_66:
1146                 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
1147                 break;
1148         case PCI_MODE_PCIX_M1_66:
1149                 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
1150                 break;
1151         case PCI_MODE_PCIX_M1_100:
1152                 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
1153                 break;
1154         case PCI_MODE_PCIX_M1_133:
1155                 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
1156                 break;
1157         case PCI_MODE_PCIX_M2_66:
1158                 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
1159                 break;
1160         case PCI_MODE_PCIX_M2_100:
1161                 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
1162                 break;
1163         case PCI_MODE_PCIX_M2_133:
1164                 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
1165                 break;
1166         default:
1167                 return -1;      /* Unsupported bus speed */
1168         }
1169
1170         return mode;
1171 }
1172
1173 /**
1174  *  init_tti - Initialization transmit traffic interrupt scheme
1175  *  @nic: device private variable
1176  *  @link: link status (UP/DOWN) used to enable/disable continuous
1177  *  transmit interrupts
1178  *  Description: The function configures transmit traffic interrupts
1179  *  Return Value:  SUCCESS on success and
1180  *  '-1' on failure
1181  */
1182
1183 static int init_tti(struct s2io_nic *nic, int link)
1184 {
1185         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1186         register u64 val64 = 0;
1187         int i;
1188         struct config_param *config = &nic->config;
1189
1190         for (i = 0; i < config->tx_fifo_num; i++) {
1191                 /*
1192                  * TTI Initialization. Default Tx timer gets us about
1193                  * 250 interrupts per sec. Continuous interrupts are enabled
1194                  * by default.
1195                  */
1196                 if (nic->device_type == XFRAME_II_DEVICE) {
1197                         int count = (nic->config.bus_speed * 125)/2;
1198                         val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1199                 } else
1200                         val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1201
1202                 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1203                         TTI_DATA1_MEM_TX_URNG_B(0x10) |
1204                         TTI_DATA1_MEM_TX_URNG_C(0x30) |
1205                         TTI_DATA1_MEM_TX_TIMER_AC_EN;
1206                 if (i == 0)
1207                         if (use_continuous_tx_intrs && (link == LINK_UP))
1208                                 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1209                 writeq(val64, &bar0->tti_data1_mem);
1210
1211                 if (nic->config.intr_type == MSI_X) {
1212                         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1213                                 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1214                                 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1215                                 TTI_DATA2_MEM_TX_UFC_D(0x300);
1216                 } else {
1217                         if ((nic->config.tx_steering_type ==
1218                              TX_DEFAULT_STEERING) &&
1219                             (config->tx_fifo_num > 1) &&
1220                             (i >= nic->udp_fifo_idx) &&
1221                             (i < (nic->udp_fifo_idx +
1222                                   nic->total_udp_fifos)))
1223                                 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1224                                         TTI_DATA2_MEM_TX_UFC_B(0x80) |
1225                                         TTI_DATA2_MEM_TX_UFC_C(0x100) |
1226                                         TTI_DATA2_MEM_TX_UFC_D(0x120);
1227                         else
1228                                 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1229                                         TTI_DATA2_MEM_TX_UFC_B(0x20) |
1230                                         TTI_DATA2_MEM_TX_UFC_C(0x40) |
1231                                         TTI_DATA2_MEM_TX_UFC_D(0x80);
1232                 }
1233
1234                 writeq(val64, &bar0->tti_data2_mem);
1235
1236                 val64 = TTI_CMD_MEM_WE |
1237                         TTI_CMD_MEM_STROBE_NEW_CMD |
1238                         TTI_CMD_MEM_OFFSET(i);
1239                 writeq(val64, &bar0->tti_command_mem);
1240
1241                 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1242                                           TTI_CMD_MEM_STROBE_NEW_CMD,
1243                                           S2IO_BIT_RESET) != SUCCESS)
1244                         return FAILURE;
1245         }
1246
1247         return SUCCESS;
1248 }
1249
1250 /**
1251  *  init_nic - Initialization of hardware
1252  *  @nic: device private variable
1253  *  Description: The function sequentially configures every block
1254  *  of the H/W from their reset values.
1255  *  Return Value:  SUCCESS on success and
1256  *  '-1' on failure (endian settings incorrect).
1257  */
1258
1259 static int init_nic(struct s2io_nic *nic)
1260 {
1261         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1262         struct net_device *dev = nic->dev;
1263         register u64 val64 = 0;
1264         void __iomem *add;
1265         u32 time;
1266         int i, j;
1267         int dtx_cnt = 0;
1268         unsigned long long mem_share;
1269         int mem_size;
1270         struct config_param *config = &nic->config;
1271         struct mac_info *mac_control = &nic->mac_control;
1272
1273         /* to set the swapper controle on the card */
1274         if (s2io_set_swapper(nic)) {
1275                 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
1276                 return -EIO;
1277         }
1278
1279         /*
1280          * Herc requires EOI to be removed from reset before XGXS, so..
1281          */
1282         if (nic->device_type & XFRAME_II_DEVICE) {
1283                 val64 = 0xA500000000ULL;
1284                 writeq(val64, &bar0->sw_reset);
1285                 msleep(500);
1286                 val64 = readq(&bar0->sw_reset);
1287         }
1288
1289         /* Remove XGXS from reset state */
1290         val64 = 0;
1291         writeq(val64, &bar0->sw_reset);
1292         msleep(500);
1293         val64 = readq(&bar0->sw_reset);
1294
1295         /* Ensure that it's safe to access registers by checking
1296          * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1297          */
1298         if (nic->device_type == XFRAME_II_DEVICE) {
1299                 for (i = 0; i < 50; i++) {
1300                         val64 = readq(&bar0->adapter_status);
1301                         if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1302                                 break;
1303                         msleep(10);
1304                 }
1305                 if (i == 50)
1306                         return -ENODEV;
1307         }
1308
1309         /*  Enable Receiving broadcasts */
1310         add = &bar0->mac_cfg;
1311         val64 = readq(&bar0->mac_cfg);
1312         val64 |= MAC_RMAC_BCAST_ENABLE;
1313         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1314         writel((u32)val64, add);
1315         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1316         writel((u32) (val64 >> 32), (add + 4));
1317
1318         /* Read registers in all blocks */
1319         val64 = readq(&bar0->mac_int_mask);
1320         val64 = readq(&bar0->mc_int_mask);
1321         val64 = readq(&bar0->xgxs_int_mask);
1322
1323         /*  Set MTU */
1324         val64 = dev->mtu;
1325         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1326
1327         if (nic->device_type & XFRAME_II_DEVICE) {
1328                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1329                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1330                                           &bar0->dtx_control, UF);
1331                         if (dtx_cnt & 0x1)
1332                                 msleep(1); /* Necessary!! */
1333                         dtx_cnt++;
1334                 }
1335         } else {
1336                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1337                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1338                                           &bar0->dtx_control, UF);
1339                         val64 = readq(&bar0->dtx_control);
1340                         dtx_cnt++;
1341                 }
1342         }
1343
1344         /*  Tx DMA Initialization */
1345         val64 = 0;
1346         writeq(val64, &bar0->tx_fifo_partition_0);
1347         writeq(val64, &bar0->tx_fifo_partition_1);
1348         writeq(val64, &bar0->tx_fifo_partition_2);
1349         writeq(val64, &bar0->tx_fifo_partition_3);
1350
1351         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1352                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1353
1354                 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1355                         vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1356
1357                 if (i == (config->tx_fifo_num - 1)) {
1358                         if (i % 2 == 0)
1359                                 i++;
1360                 }
1361
1362                 switch (i) {
1363                 case 1:
1364                         writeq(val64, &bar0->tx_fifo_partition_0);
1365                         val64 = 0;
1366                         j = 0;
1367                         break;
1368                 case 3:
1369                         writeq(val64, &bar0->tx_fifo_partition_1);
1370                         val64 = 0;
1371                         j = 0;
1372                         break;
1373                 case 5:
1374                         writeq(val64, &bar0->tx_fifo_partition_2);
1375                         val64 = 0;
1376                         j = 0;
1377                         break;
1378                 case 7:
1379                         writeq(val64, &bar0->tx_fifo_partition_3);
1380                         val64 = 0;
1381                         j = 0;
1382                         break;
1383                 default:
1384                         j++;
1385                         break;
1386                 }
1387         }
1388
1389         /*
1390          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1391          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1392          */
1393         if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
1394                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1395
1396         val64 = readq(&bar0->tx_fifo_partition_0);
1397         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1398                   &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1399
1400         /*
1401          * Initialization of Tx_PA_CONFIG register to ignore packet
1402          * integrity checking.
1403          */
1404         val64 = readq(&bar0->tx_pa_cfg);
1405         val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1406                 TX_PA_CFG_IGNORE_SNAP_OUI |
1407                 TX_PA_CFG_IGNORE_LLC_CTRL |
1408                 TX_PA_CFG_IGNORE_L2_ERR;
1409         writeq(val64, &bar0->tx_pa_cfg);
1410
1411         /* Rx DMA intialization. */
1412         val64 = 0;
1413         for (i = 0; i < config->rx_ring_num; i++) {
1414                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1415
1416                 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1417         }
1418         writeq(val64, &bar0->rx_queue_priority);
1419
1420         /*
1421          * Allocating equal share of memory to all the
1422          * configured Rings.
1423          */
1424         val64 = 0;
1425         if (nic->device_type & XFRAME_II_DEVICE)
1426                 mem_size = 32;
1427         else
1428                 mem_size = 64;
1429
1430         for (i = 0; i < config->rx_ring_num; i++) {
1431                 switch (i) {
1432                 case 0:
1433                         mem_share = (mem_size / config->rx_ring_num +
1434                                      mem_size % config->rx_ring_num);
1435                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1436                         continue;
1437                 case 1:
1438                         mem_share = (mem_size / config->rx_ring_num);
1439                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1440                         continue;
1441                 case 2:
1442                         mem_share = (mem_size / config->rx_ring_num);
1443                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1444                         continue;
1445                 case 3:
1446                         mem_share = (mem_size / config->rx_ring_num);
1447                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1448                         continue;
1449                 case 4:
1450                         mem_share = (mem_size / config->rx_ring_num);
1451                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1452                         continue;
1453                 case 5:
1454                         mem_share = (mem_size / config->rx_ring_num);
1455                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1456                         continue;
1457                 case 6:
1458                         mem_share = (mem_size / config->rx_ring_num);
1459                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1460                         continue;
1461                 case 7:
1462                         mem_share = (mem_size / config->rx_ring_num);
1463                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1464                         continue;
1465                 }
1466         }
1467         writeq(val64, &bar0->rx_queue_cfg);
1468
1469         /*
1470          * Filling Tx round robin registers
1471          * as per the number of FIFOs for equal scheduling priority
1472          */
1473         switch (config->tx_fifo_num) {
1474         case 1:
1475                 val64 = 0x0;
1476                 writeq(val64, &bar0->tx_w_round_robin_0);
1477                 writeq(val64, &bar0->tx_w_round_robin_1);
1478                 writeq(val64, &bar0->tx_w_round_robin_2);
1479                 writeq(val64, &bar0->tx_w_round_robin_3);
1480                 writeq(val64, &bar0->tx_w_round_robin_4);
1481                 break;
1482         case 2:
1483                 val64 = 0x0001000100010001ULL;
1484                 writeq(val64, &bar0->tx_w_round_robin_0);
1485                 writeq(val64, &bar0->tx_w_round_robin_1);
1486                 writeq(val64, &bar0->tx_w_round_robin_2);
1487                 writeq(val64, &bar0->tx_w_round_robin_3);
1488                 val64 = 0x0001000100000000ULL;
1489                 writeq(val64, &bar0->tx_w_round_robin_4);
1490                 break;
1491         case 3:
1492                 val64 = 0x0001020001020001ULL;
1493                 writeq(val64, &bar0->tx_w_round_robin_0);
1494                 val64 = 0x0200010200010200ULL;
1495                 writeq(val64, &bar0->tx_w_round_robin_1);
1496                 val64 = 0x0102000102000102ULL;
1497                 writeq(val64, &bar0->tx_w_round_robin_2);
1498                 val64 = 0x0001020001020001ULL;
1499                 writeq(val64, &bar0->tx_w_round_robin_3);
1500                 val64 = 0x0200010200000000ULL;
1501                 writeq(val64, &bar0->tx_w_round_robin_4);
1502                 break;
1503         case 4:
1504                 val64 = 0x0001020300010203ULL;
1505                 writeq(val64, &bar0->tx_w_round_robin_0);
1506                 writeq(val64, &bar0->tx_w_round_robin_1);
1507                 writeq(val64, &bar0->tx_w_round_robin_2);
1508                 writeq(val64, &bar0->tx_w_round_robin_3);
1509                 val64 = 0x0001020300000000ULL;
1510                 writeq(val64, &bar0->tx_w_round_robin_4);
1511                 break;
1512         case 5:
1513                 val64 = 0x0001020304000102ULL;
1514                 writeq(val64, &bar0->tx_w_round_robin_0);
1515                 val64 = 0x0304000102030400ULL;
1516                 writeq(val64, &bar0->tx_w_round_robin_1);
1517                 val64 = 0x0102030400010203ULL;
1518                 writeq(val64, &bar0->tx_w_round_robin_2);
1519                 val64 = 0x0400010203040001ULL;
1520                 writeq(val64, &bar0->tx_w_round_robin_3);
1521                 val64 = 0x0203040000000000ULL;
1522                 writeq(val64, &bar0->tx_w_round_robin_4);
1523                 break;
1524         case 6:
1525                 val64 = 0x0001020304050001ULL;
1526                 writeq(val64, &bar0->tx_w_round_robin_0);
1527                 val64 = 0x0203040500010203ULL;
1528                 writeq(val64, &bar0->tx_w_round_robin_1);
1529                 val64 = 0x0405000102030405ULL;
1530                 writeq(val64, &bar0->tx_w_round_robin_2);
1531                 val64 = 0x0001020304050001ULL;
1532                 writeq(val64, &bar0->tx_w_round_robin_3);
1533                 val64 = 0x0203040500000000ULL;
1534                 writeq(val64, &bar0->tx_w_round_robin_4);
1535                 break;
1536         case 7:
1537                 val64 = 0x0001020304050600ULL;
1538                 writeq(val64, &bar0->tx_w_round_robin_0);
1539                 val64 = 0x0102030405060001ULL;
1540                 writeq(val64, &bar0->tx_w_round_robin_1);
1541                 val64 = 0x0203040506000102ULL;
1542                 writeq(val64, &bar0->tx_w_round_robin_2);
1543                 val64 = 0x0304050600010203ULL;
1544                 writeq(val64, &bar0->tx_w_round_robin_3);
1545                 val64 = 0x0405060000000000ULL;
1546                 writeq(val64, &bar0->tx_w_round_robin_4);
1547                 break;
1548         case 8:
1549                 val64 = 0x0001020304050607ULL;
1550                 writeq(val64, &bar0->tx_w_round_robin_0);
1551                 writeq(val64, &bar0->tx_w_round_robin_1);
1552                 writeq(val64, &bar0->tx_w_round_robin_2);
1553                 writeq(val64, &bar0->tx_w_round_robin_3);
1554                 val64 = 0x0001020300000000ULL;
1555                 writeq(val64, &bar0->tx_w_round_robin_4);
1556                 break;
1557         }
1558
1559         /* Enable all configured Tx FIFO partitions */
1560         val64 = readq(&bar0->tx_fifo_partition_0);
1561         val64 |= (TX_FIFO_PARTITION_EN);
1562         writeq(val64, &bar0->tx_fifo_partition_0);
1563
1564         /* Filling the Rx round robin registers as per the
1565          * number of Rings and steering based on QoS with
1566          * equal priority.
1567          */
1568         switch (config->rx_ring_num) {
1569         case 1:
1570                 val64 = 0x0;
1571                 writeq(val64, &bar0->rx_w_round_robin_0);
1572                 writeq(val64, &bar0->rx_w_round_robin_1);
1573                 writeq(val64, &bar0->rx_w_round_robin_2);
1574                 writeq(val64, &bar0->rx_w_round_robin_3);
1575                 writeq(val64, &bar0->rx_w_round_robin_4);
1576
1577                 val64 = 0x8080808080808080ULL;
1578                 writeq(val64, &bar0->rts_qos_steering);
1579                 break;
1580         case 2:
1581                 val64 = 0x0001000100010001ULL;
1582                 writeq(val64, &bar0->rx_w_round_robin_0);
1583                 writeq(val64, &bar0->rx_w_round_robin_1);
1584                 writeq(val64, &bar0->rx_w_round_robin_2);
1585                 writeq(val64, &bar0->rx_w_round_robin_3);
1586                 val64 = 0x0001000100000000ULL;
1587                 writeq(val64, &bar0->rx_w_round_robin_4);
1588
1589                 val64 = 0x8080808040404040ULL;
1590                 writeq(val64, &bar0->rts_qos_steering);
1591                 break;
1592         case 3:
1593                 val64 = 0x0001020001020001ULL;
1594                 writeq(val64, &bar0->rx_w_round_robin_0);
1595                 val64 = 0x0200010200010200ULL;
1596                 writeq(val64, &bar0->rx_w_round_robin_1);
1597                 val64 = 0x0102000102000102ULL;
1598                 writeq(val64, &bar0->rx_w_round_robin_2);
1599                 val64 = 0x0001020001020001ULL;
1600                 writeq(val64, &bar0->rx_w_round_robin_3);
1601                 val64 = 0x0200010200000000ULL;
1602                 writeq(val64, &bar0->rx_w_round_robin_4);
1603
1604                 val64 = 0x8080804040402020ULL;
1605                 writeq(val64, &bar0->rts_qos_steering);
1606                 break;
1607         case 4:
1608                 val64 = 0x0001020300010203ULL;
1609                 writeq(val64, &bar0->rx_w_round_robin_0);
1610                 writeq(val64, &bar0->rx_w_round_robin_1);
1611                 writeq(val64, &bar0->rx_w_round_robin_2);
1612                 writeq(val64, &bar0->rx_w_round_robin_3);
1613                 val64 = 0x0001020300000000ULL;
1614                 writeq(val64, &bar0->rx_w_round_robin_4);
1615
1616                 val64 = 0x8080404020201010ULL;
1617                 writeq(val64, &bar0->rts_qos_steering);
1618                 break;
1619         case 5:
1620                 val64 = 0x0001020304000102ULL;
1621                 writeq(val64, &bar0->rx_w_round_robin_0);
1622                 val64 = 0x0304000102030400ULL;
1623                 writeq(val64, &bar0->rx_w_round_robin_1);
1624                 val64 = 0x0102030400010203ULL;
1625                 writeq(val64, &bar0->rx_w_round_robin_2);
1626                 val64 = 0x0400010203040001ULL;
1627                 writeq(val64, &bar0->rx_w_round_robin_3);
1628                 val64 = 0x0203040000000000ULL;
1629                 writeq(val64, &bar0->rx_w_round_robin_4);
1630
1631                 val64 = 0x8080404020201008ULL;
1632                 writeq(val64, &bar0->rts_qos_steering);
1633                 break;
1634         case 6:
1635                 val64 = 0x0001020304050001ULL;
1636                 writeq(val64, &bar0->rx_w_round_robin_0);
1637                 val64 = 0x0203040500010203ULL;
1638                 writeq(val64, &bar0->rx_w_round_robin_1);
1639                 val64 = 0x0405000102030405ULL;
1640                 writeq(val64, &bar0->rx_w_round_robin_2);
1641                 val64 = 0x0001020304050001ULL;
1642                 writeq(val64, &bar0->rx_w_round_robin_3);
1643                 val64 = 0x0203040500000000ULL;
1644                 writeq(val64, &bar0->rx_w_round_robin_4);
1645
1646                 val64 = 0x8080404020100804ULL;
1647                 writeq(val64, &bar0->rts_qos_steering);
1648                 break;
1649         case 7:
1650                 val64 = 0x0001020304050600ULL;
1651                 writeq(val64, &bar0->rx_w_round_robin_0);
1652                 val64 = 0x0102030405060001ULL;
1653                 writeq(val64, &bar0->rx_w_round_robin_1);
1654                 val64 = 0x0203040506000102ULL;
1655                 writeq(val64, &bar0->rx_w_round_robin_2);
1656                 val64 = 0x0304050600010203ULL;
1657                 writeq(val64, &bar0->rx_w_round_robin_3);
1658                 val64 = 0x0405060000000000ULL;
1659                 writeq(val64, &bar0->rx_w_round_robin_4);
1660
1661                 val64 = 0x8080402010080402ULL;
1662                 writeq(val64, &bar0->rts_qos_steering);
1663                 break;
1664         case 8:
1665                 val64 = 0x0001020304050607ULL;
1666                 writeq(val64, &bar0->rx_w_round_robin_0);
1667                 writeq(val64, &bar0->rx_w_round_robin_1);
1668                 writeq(val64, &bar0->rx_w_round_robin_2);
1669                 writeq(val64, &bar0->rx_w_round_robin_3);
1670                 val64 = 0x0001020300000000ULL;
1671                 writeq(val64, &bar0->rx_w_round_robin_4);
1672
1673                 val64 = 0x8040201008040201ULL;
1674                 writeq(val64, &bar0->rts_qos_steering);
1675                 break;
1676         }
1677
1678         /* UDP Fix */
1679         val64 = 0;
1680         for (i = 0; i < 8; i++)
1681                 writeq(val64, &bar0->rts_frm_len_n[i]);
1682
1683         /* Set the default rts frame length for the rings configured */
1684         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1685         for (i = 0 ; i < config->rx_ring_num ; i++)
1686                 writeq(val64, &bar0->rts_frm_len_n[i]);
1687
1688         /* Set the frame length for the configured rings
1689          * desired by the user
1690          */
1691         for (i = 0; i < config->rx_ring_num; i++) {
1692                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1693                  * specified frame length steering.
1694                  * If the user provides the frame length then program
1695                  * the rts_frm_len register for those values or else
1696                  * leave it as it is.
1697                  */
1698                 if (rts_frm_len[i] != 0) {
1699                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1700                                &bar0->rts_frm_len_n[i]);
1701                 }
1702         }
1703
1704         /* Disable differentiated services steering logic */
1705         for (i = 0; i < 64; i++) {
1706                 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1707                         DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1708                                   dev->name);
1709                         DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1710                         return -ENODEV;
1711                 }
1712         }
1713
1714         /* Program statistics memory */
1715         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1716
1717         if (nic->device_type == XFRAME_II_DEVICE) {
1718                 val64 = STAT_BC(0x320);
1719                 writeq(val64, &bar0->stat_byte_cnt);
1720         }
1721
1722         /*
1723          * Initializing the sampling rate for the device to calculate the
1724          * bandwidth utilization.
1725          */
1726         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1727                 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1728         writeq(val64, &bar0->mac_link_util);
1729
1730         /*
1731          * Initializing the Transmit and Receive Traffic Interrupt
1732          * Scheme.
1733          */
1734
1735         /* Initialize TTI */
1736         if (SUCCESS != init_tti(nic, nic->last_link_state))
1737                 return -ENODEV;
1738
1739         /* RTI Initialization */
1740         if (nic->device_type == XFRAME_II_DEVICE) {
1741                 /*
1742                  * Programmed to generate Apprx 500 Intrs per
1743                  * second
1744                  */
1745                 int count = (nic->config.bus_speed * 125)/4;
1746                 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1747         } else
1748                 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1749         val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1750                 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1751                 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1752                 RTI_DATA1_MEM_RX_TIMER_AC_EN;
1753
1754         writeq(val64, &bar0->rti_data1_mem);
1755
1756         val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1757                 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1758         if (nic->config.intr_type == MSI_X)
1759                 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1760                           RTI_DATA2_MEM_RX_UFC_D(0x40));
1761         else
1762                 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1763                           RTI_DATA2_MEM_RX_UFC_D(0x80));
1764         writeq(val64, &bar0->rti_data2_mem);
1765
1766         for (i = 0; i < config->rx_ring_num; i++) {
1767                 val64 = RTI_CMD_MEM_WE |
1768                         RTI_CMD_MEM_STROBE_NEW_CMD |
1769                         RTI_CMD_MEM_OFFSET(i);
1770                 writeq(val64, &bar0->rti_command_mem);
1771
1772                 /*
1773                  * Once the operation completes, the Strobe bit of the
1774                  * command register will be reset. We poll for this
1775                  * particular condition. We wait for a maximum of 500ms
1776                  * for the operation to complete, if it's not complete
1777                  * by then we return error.
1778                  */
1779                 time = 0;
1780                 while (true) {
1781                         val64 = readq(&bar0->rti_command_mem);
1782                         if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1783                                 break;
1784
1785                         if (time > 10) {
1786                                 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1787                                           dev->name);
1788                                 return -ENODEV;
1789                         }
1790                         time++;
1791                         msleep(50);
1792                 }
1793         }
1794
1795         /*
1796          * Initializing proper values as Pause threshold into all
1797          * the 8 Queues on Rx side.
1798          */
1799         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1800         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1801
1802         /* Disable RMAC PAD STRIPPING */
1803         add = &bar0->mac_cfg;
1804         val64 = readq(&bar0->mac_cfg);
1805         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1806         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1807         writel((u32) (val64), add);
1808         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1809         writel((u32) (val64 >> 32), (add + 4));
1810         val64 = readq(&bar0->mac_cfg);
1811
1812         /* Enable FCS stripping by adapter */
1813         add = &bar0->mac_cfg;
1814         val64 = readq(&bar0->mac_cfg);
1815         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1816         if (nic->device_type == XFRAME_II_DEVICE)
1817                 writeq(val64, &bar0->mac_cfg);
1818         else {
1819                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1820                 writel((u32) (val64), add);
1821                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1822                 writel((u32) (val64 >> 32), (add + 4));
1823         }
1824
1825         /*
1826          * Set the time value to be inserted in the pause frame
1827          * generated by xena.
1828          */
1829         val64 = readq(&bar0->rmac_pause_cfg);
1830         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1831         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1832         writeq(val64, &bar0->rmac_pause_cfg);
1833
1834         /*
1835          * Set the Threshold Limit for Generating the pause frame
1836          * If the amount of data in any Queue exceeds ratio of
1837          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1838          * pause frame is generated
1839          */
1840         val64 = 0;
1841         for (i = 0; i < 4; i++) {
1842                 val64 |= (((u64)0xFF00 |
1843                            nic->mac_control.mc_pause_threshold_q0q3)
1844                           << (i * 2 * 8));
1845         }
1846         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1847
1848         val64 = 0;
1849         for (i = 0; i < 4; i++) {
1850                 val64 |= (((u64)0xFF00 |
1851                            nic->mac_control.mc_pause_threshold_q4q7)
1852                           << (i * 2 * 8));
1853         }
1854         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1855
1856         /*
1857          * TxDMA will stop Read request if the number of read split has
1858          * exceeded the limit pointed by shared_splits
1859          */
1860         val64 = readq(&bar0->pic_control);
1861         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1862         writeq(val64, &bar0->pic_control);
1863
1864         if (nic->config.bus_speed == 266) {
1865                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1866                 writeq(0x0, &bar0->read_retry_delay);
1867                 writeq(0x0, &bar0->write_retry_delay);
1868         }
1869
1870         /*
1871          * Programming the Herc to split every write transaction
1872          * that does not start on an ADB to reduce disconnects.
1873          */
1874         if (nic->device_type == XFRAME_II_DEVICE) {
1875                 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1876                         MISC_LINK_STABILITY_PRD(3);
1877                 writeq(val64, &bar0->misc_control);
1878                 val64 = readq(&bar0->pic_control2);
1879                 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1880                 writeq(val64, &bar0->pic_control2);
1881         }
1882         if (strstr(nic->product_name, "CX4")) {
1883                 val64 = TMAC_AVG_IPG(0x17);
1884                 writeq(val64, &bar0->tmac_avg_ipg);
1885         }
1886
1887         return SUCCESS;
1888 }
1889 #define LINK_UP_DOWN_INTERRUPT          1
1890 #define MAC_RMAC_ERR_TIMER              2
1891
1892 static int s2io_link_fault_indication(struct s2io_nic *nic)
1893 {
1894         if (nic->device_type == XFRAME_II_DEVICE)
1895                 return LINK_UP_DOWN_INTERRUPT;
1896         else
1897                 return MAC_RMAC_ERR_TIMER;
1898 }
1899
1900 /**
1901  *  do_s2io_write_bits -  update alarm bits in alarm register
1902  *  @value: alarm bits
1903  *  @flag: interrupt status
1904  *  @addr: address value
1905  *  Description: update alarm bits in alarm register
1906  *  Return Value:
1907  *  NONE.
1908  */
1909 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1910 {
1911         u64 temp64;
1912
1913         temp64 = readq(addr);
1914
1915         if (flag == ENABLE_INTRS)
1916                 temp64 &= ~((u64)value);
1917         else
1918                 temp64 |= ((u64)value);
1919         writeq(temp64, addr);
1920 }
1921
1922 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1923 {
1924         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1925         register u64 gen_int_mask = 0;
1926         u64 interruptible;
1927
1928         writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1929         if (mask & TX_DMA_INTR) {
1930                 gen_int_mask |= TXDMA_INT_M;
1931
1932                 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1933                                    TXDMA_PCC_INT | TXDMA_TTI_INT |
1934                                    TXDMA_LSO_INT | TXDMA_TPA_INT |
1935                                    TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1936
1937                 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1938                                    PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1939                                    PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1940                                    &bar0->pfc_err_mask);
1941
1942                 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1943                                    TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1944                                    TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1945
1946                 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1947                                    PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1948                                    PCC_N_SERR | PCC_6_COF_OV_ERR |
1949                                    PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1950                                    PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1951                                    PCC_TXB_ECC_SG_ERR,
1952                                    flag, &bar0->pcc_err_mask);
1953
1954                 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1955                                    TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1956
1957                 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1958                                    LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1959                                    LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1960                                    flag, &bar0->lso_err_mask);
1961
1962                 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1963                                    flag, &bar0->tpa_err_mask);
1964
1965                 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1966         }
1967
1968         if (mask & TX_MAC_INTR) {
1969                 gen_int_mask |= TXMAC_INT_M;
1970                 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1971                                    &bar0->mac_int_mask);
1972                 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1973                                    TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1974                                    TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1975                                    flag, &bar0->mac_tmac_err_mask);
1976         }
1977
1978         if (mask & TX_XGXS_INTR) {
1979                 gen_int_mask |= TXXGXS_INT_M;
1980                 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1981                                    &bar0->xgxs_int_mask);
1982                 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1983                                    TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1984                                    flag, &bar0->xgxs_txgxs_err_mask);
1985         }
1986
1987         if (mask & RX_DMA_INTR) {
1988                 gen_int_mask |= RXDMA_INT_M;
1989                 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1990                                    RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1991                                    flag, &bar0->rxdma_int_mask);
1992                 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1993                                    RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1994                                    RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1995                                    RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1996                 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1997                                    PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1998                                    PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1999                                    &bar0->prc_pcix_err_mask);
2000                 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
2001                                    RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
2002                                    &bar0->rpa_err_mask);
2003                 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
2004                                    RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2005                                    RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2006                                    RDA_FRM_ECC_SG_ERR |
2007                                    RDA_MISC_ERR|RDA_PCIX_ERR,
2008                                    flag, &bar0->rda_err_mask);
2009                 do_s2io_write_bits(RTI_SM_ERR_ALARM |
2010                                    RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2011                                    flag, &bar0->rti_err_mask);
2012         }
2013
2014         if (mask & RX_MAC_INTR) {
2015                 gen_int_mask |= RXMAC_INT_M;
2016                 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2017                                    &bar0->mac_int_mask);
2018                 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2019                                  RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2020                                  RMAC_DOUBLE_ECC_ERR);
2021                 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2022                         interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2023                 do_s2io_write_bits(interruptible,
2024                                    flag, &bar0->mac_rmac_err_mask);
2025         }
2026
2027         if (mask & RX_XGXS_INTR) {
2028                 gen_int_mask |= RXXGXS_INT_M;
2029                 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2030                                    &bar0->xgxs_int_mask);
2031                 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2032                                    &bar0->xgxs_rxgxs_err_mask);
2033         }
2034
2035         if (mask & MC_INTR) {
2036                 gen_int_mask |= MC_INT_M;
2037                 do_s2io_write_bits(MC_INT_MASK_MC_INT,
2038                                    flag, &bar0->mc_int_mask);
2039                 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2040                                    MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2041                                    &bar0->mc_err_mask);
2042         }
2043         nic->general_int_mask = gen_int_mask;
2044
2045         /* Remove this line when alarm interrupts are enabled */
2046         nic->general_int_mask = 0;
2047 }
2048
2049 /**
2050  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
2051  *  @nic: device private variable,
2052  *  @mask: A mask indicating which Intr block must be modified and,
2053  *  @flag: A flag indicating whether to enable or disable the Intrs.
2054  *  Description: This function will either disable or enable the interrupts
2055  *  depending on the flag argument. The mask argument can be used to
2056  *  enable/disable any Intr block.
2057  *  Return Value: NONE.
2058  */
2059
2060 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2061 {
2062         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2063         register u64 temp64 = 0, intr_mask = 0;
2064
2065         intr_mask = nic->general_int_mask;
2066
2067         /*  Top level interrupt classification */
2068         /*  PIC Interrupts */
2069         if (mask & TX_PIC_INTR) {
2070                 /*  Enable PIC Intrs in the general intr mask register */
2071                 intr_mask |= TXPIC_INT_M;
2072                 if (flag == ENABLE_INTRS) {
2073                         /*
2074                          * If Hercules adapter enable GPIO otherwise
2075                          * disable all PCIX, Flash, MDIO, IIC and GPIO
2076                          * interrupts for now.
2077                          * TODO
2078                          */
2079                         if (s2io_link_fault_indication(nic) ==
2080                             LINK_UP_DOWN_INTERRUPT) {
2081                                 do_s2io_write_bits(PIC_INT_GPIO, flag,
2082                                                    &bar0->pic_int_mask);
2083                                 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2084                                                    &bar0->gpio_int_mask);
2085                         } else
2086                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2087                 } else if (flag == DISABLE_INTRS) {
2088                         /*
2089                          * Disable PIC Intrs in the general
2090                          * intr mask register
2091                          */
2092                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2093                 }
2094         }
2095
2096         /*  Tx traffic interrupts */
2097         if (mask & TX_TRAFFIC_INTR) {
2098                 intr_mask |= TXTRAFFIC_INT_M;
2099                 if (flag == ENABLE_INTRS) {
2100                         /*
2101                          * Enable all the Tx side interrupts
2102                          * writing 0 Enables all 64 TX interrupt levels
2103                          */
2104                         writeq(0x0, &bar0->tx_traffic_mask);
2105                 } else if (flag == DISABLE_INTRS) {
2106                         /*
2107                          * Disable Tx Traffic Intrs in the general intr mask
2108                          * register.
2109                          */
2110                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2111                 }
2112         }
2113
2114         /*  Rx traffic interrupts */
2115         if (mask & RX_TRAFFIC_INTR) {
2116                 intr_mask |= RXTRAFFIC_INT_M;
2117                 if (flag == ENABLE_INTRS) {
2118                         /* writing 0 Enables all 8 RX interrupt levels */
2119                         writeq(0x0, &bar0->rx_traffic_mask);
2120                 } else if (flag == DISABLE_INTRS) {
2121                         /*
2122                          * Disable Rx Traffic Intrs in the general intr mask
2123                          * register.
2124                          */
2125                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2126                 }
2127         }
2128
2129         temp64 = readq(&bar0->general_int_mask);
2130         if (flag == ENABLE_INTRS)
2131                 temp64 &= ~((u64)intr_mask);
2132         else
2133                 temp64 = DISABLE_ALL_INTRS;
2134         writeq(temp64, &bar0->general_int_mask);
2135
2136         nic->general_int_mask = readq(&bar0->general_int_mask);
2137 }
2138
2139 /**
2140  *  verify_pcc_quiescent- Checks for PCC quiescent state
2141  *  Return: 1 If PCC is quiescence
2142  *          0 If PCC is not quiescence
2143  */
2144 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2145 {
2146         int ret = 0, herc;
2147         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2148         u64 val64 = readq(&bar0->adapter_status);
2149
2150         herc = (sp->device_type == XFRAME_II_DEVICE);
2151
2152         if (flag == false) {
2153                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2154                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2155                                 ret = 1;
2156                 } else {
2157                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2158                                 ret = 1;
2159                 }
2160         } else {
2161                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2162                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2163                              ADAPTER_STATUS_RMAC_PCC_IDLE))
2164                                 ret = 1;
2165                 } else {
2166                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2167                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2168                                 ret = 1;
2169                 }
2170         }
2171
2172         return ret;
2173 }
2174 /**
2175  *  verify_xena_quiescence - Checks whether the H/W is ready
2176  *  Description: Returns whether the H/W is ready to go or not. Depending
2177  *  on whether adapter enable bit was written or not the comparison
2178  *  differs and the calling function passes the input argument flag to
2179  *  indicate this.
2180  *  Return: 1 If xena is quiescence
2181  *          0 If Xena is not quiescence
2182  */
2183
2184 static int verify_xena_quiescence(struct s2io_nic *sp)
2185 {
2186         int  mode;
2187         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2188         u64 val64 = readq(&bar0->adapter_status);
2189         mode = s2io_verify_pci_mode(sp);
2190
2191         if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2192                 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2193                 return 0;
2194         }
2195         if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2196                 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2197                 return 0;
2198         }
2199         if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2200                 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2201                 return 0;
2202         }
2203         if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2204                 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2205                 return 0;
2206         }
2207         if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2208                 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2209                 return 0;
2210         }
2211         if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2212                 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2213                 return 0;
2214         }
2215         if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2216                 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2217                 return 0;
2218         }
2219         if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2220                 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2221                 return 0;
2222         }
2223
2224         /*
2225          * In PCI 33 mode, the P_PLL is not used, and therefore,
2226          * the the P_PLL_LOCK bit in the adapter_status register will
2227          * not be asserted.
2228          */
2229         if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2230             sp->device_type == XFRAME_II_DEVICE &&
2231             mode != PCI_MODE_PCI_33) {
2232                 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2233                 return 0;
2234         }
2235         if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2236               ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2237                 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2238                 return 0;
2239         }
2240         return 1;
2241 }
2242
2243 /**
2244  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
2245  * @sp: Pointer to device specifc structure
2246  * Description :
2247  * New procedure to clear mac address reading  problems on Alpha platforms
2248  *
2249  */
2250
2251 static void fix_mac_address(struct s2io_nic *sp)
2252 {
2253         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2254         u64 val64;
2255         int i = 0;
2256
2257         while (fix_mac[i] != END_SIGN) {
2258                 writeq(fix_mac[i++], &bar0->gpio_control);
2259                 udelay(10);
2260                 val64 = readq(&bar0->gpio_control);
2261         }
2262 }
2263
2264 /**
2265  *  start_nic - Turns the device on
2266  *  @nic : device private variable.
2267  *  Description:
2268  *  This function actually turns the device on. Before this  function is
2269  *  called,all Registers are configured from their reset states
2270  *  and shared memory is allocated but the NIC is still quiescent. On
2271  *  calling this function, the device interrupts are cleared and the NIC is
2272  *  literally switched on by writing into the adapter control register.
2273  *  Return Value:
2274  *  SUCCESS on success and -1 on failure.
2275  */
2276
2277 static int start_nic(struct s2io_nic *nic)
2278 {
2279         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2280         struct net_device *dev = nic->dev;
2281         register u64 val64 = 0;
2282         u16 subid, i;
2283         struct config_param *config = &nic->config;
2284         struct mac_info *mac_control = &nic->mac_control;
2285
2286         /*  PRC Initialization and configuration */
2287         for (i = 0; i < config->rx_ring_num; i++) {
2288                 struct ring_info *ring = &mac_control->rings[i];
2289
2290                 writeq((u64)ring->rx_blocks[0].block_dma_addr,
2291                        &bar0->prc_rxd0_n[i]);
2292
2293                 val64 = readq(&bar0->prc_ctrl_n[i]);
2294                 if (nic->rxd_mode == RXD_MODE_1)
2295                         val64 |= PRC_CTRL_RC_ENABLED;
2296                 else
2297                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2298                 if (nic->device_type == XFRAME_II_DEVICE)
2299                         val64 |= PRC_CTRL_GROUP_READS;
2300                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2301                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2302                 writeq(val64, &bar0->prc_ctrl_n[i]);
2303         }
2304
2305         if (nic->rxd_mode == RXD_MODE_3B) {
2306                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2307                 val64 = readq(&bar0->rx_pa_cfg);
2308                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2309                 writeq(val64, &bar0->rx_pa_cfg);
2310         }
2311
2312         if (vlan_tag_strip == 0) {
2313                 val64 = readq(&bar0->rx_pa_cfg);
2314                 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2315                 writeq(val64, &bar0->rx_pa_cfg);
2316                 nic->vlan_strip_flag = 0;
2317         }
2318
2319         /*
2320          * Enabling MC-RLDRAM. After enabling the device, we timeout
2321          * for around 100ms, which is approximately the time required
2322          * for the device to be ready for operation.
2323          */
2324         val64 = readq(&bar0->mc_rldram_mrs);
2325         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2326         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2327         val64 = readq(&bar0->mc_rldram_mrs);
2328
2329         msleep(100);    /* Delay by around 100 ms. */
2330
2331         /* Enabling ECC Protection. */
2332         val64 = readq(&bar0->adapter_control);
2333         val64 &= ~ADAPTER_ECC_EN;
2334         writeq(val64, &bar0->adapter_control);
2335
2336         /*
2337          * Verify if the device is ready to be enabled, if so enable
2338          * it.
2339          */
2340         val64 = readq(&bar0->adapter_status);
2341         if (!verify_xena_quiescence(nic)) {
2342                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2343                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2344                           (unsigned long long)val64);
2345                 return FAILURE;
2346         }
2347
2348         /*
2349          * With some switches, link might be already up at this point.
2350          * Because of this weird behavior, when we enable laser,
2351          * we may not get link. We need to handle this. We cannot
2352          * figure out which switch is misbehaving. So we are forced to
2353          * make a global change.
2354          */
2355
2356         /* Enabling Laser. */
2357         val64 = readq(&bar0->adapter_control);
2358         val64 |= ADAPTER_EOI_TX_ON;
2359         writeq(val64, &bar0->adapter_control);
2360
2361         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2362                 /*
2363                  * Dont see link state interrupts initally on some switches,
2364                  * so directly scheduling the link state task here.
2365                  */
2366                 schedule_work(&nic->set_link_task);
2367         }
2368         /* SXE-002: Initialize link and activity LED */
2369         subid = nic->pdev->subsystem_device;
2370         if (((subid & 0xFF) >= 0x07) &&
2371             (nic->device_type == XFRAME_I_DEVICE)) {
2372                 val64 = readq(&bar0->gpio_control);
2373                 val64 |= 0x0000800000000000ULL;
2374                 writeq(val64, &bar0->gpio_control);
2375                 val64 = 0x0411040400000000ULL;
2376                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2377         }
2378
2379         return SUCCESS;
2380 }
2381 /**
2382  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2383  */
2384 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2385                                         struct TxD *txdlp, int get_off)
2386 {
2387         struct s2io_nic *nic = fifo_data->nic;
2388         struct sk_buff *skb;
2389         struct TxD *txds;
2390         u16 j, frg_cnt;
2391
2392         txds = txdlp;
2393         if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2394                 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2395                                  sizeof(u64), PCI_DMA_TODEVICE);
2396                 txds++;
2397         }
2398
2399         skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
2400         if (!skb) {
2401                 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2402                 return NULL;
2403         }
2404         pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2405                          skb->len - skb->data_len, PCI_DMA_TODEVICE);
2406         frg_cnt = skb_shinfo(skb)->nr_frags;
2407         if (frg_cnt) {
2408                 txds++;
2409                 for (j = 0; j < frg_cnt; j++, txds++) {
2410                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2411                         if (!txds->Buffer_Pointer)
2412                                 break;
2413                         pci_unmap_page(nic->pdev,
2414                                        (dma_addr_t)txds->Buffer_Pointer,
2415                                        frag->size, PCI_DMA_TODEVICE);
2416                 }
2417         }
2418         memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2419         return skb;
2420 }
2421
2422 /**
2423  *  free_tx_buffers - Free all queued Tx buffers
2424  *  @nic : device private variable.
2425  *  Description:
2426  *  Free all queued Tx buffers.
2427  *  Return Value: void
2428  */
2429
2430 static void free_tx_buffers(struct s2io_nic *nic)
2431 {
2432         struct net_device *dev = nic->dev;
2433         struct sk_buff *skb;
2434         struct TxD *txdp;
2435         int i, j;
2436         int cnt = 0;
2437         struct config_param *config = &nic->config;
2438         struct mac_info *mac_control = &nic->mac_control;
2439         struct stat_block *stats = mac_control->stats_info;
2440         struct swStat *swstats = &stats->sw_stat;
2441
2442         for (i = 0; i < config->tx_fifo_num; i++) {
2443                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2444                 struct fifo_info *fifo = &mac_control->fifos[i];
2445                 unsigned long flags;
2446
2447                 spin_lock_irqsave(&fifo->tx_lock, flags);
2448                 for (j = 0; j < tx_cfg->fifo_len; j++) {
2449                         txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
2450                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2451                         if (skb) {
2452                                 swstats->mem_freed += skb->truesize;
2453                                 dev_kfree_skb(skb);
2454                                 cnt++;
2455                         }
2456                 }
2457                 DBG_PRINT(INTR_DBG,
2458                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2459                           dev->name, cnt, i);
2460                 fifo->tx_curr_get_info.offset = 0;
2461                 fifo->tx_curr_put_info.offset = 0;
2462                 spin_unlock_irqrestore(&fifo->tx_lock, flags);
2463         }
2464 }
2465
2466 /**
2467  *   stop_nic -  To stop the nic
2468  *   @nic ; device private variable.
2469  *   Description:
2470  *   This function does exactly the opposite of what the start_nic()
2471  *   function does. This function is called to stop the device.
2472  *   Return Value:
2473  *   void.
2474  */
2475
2476 static void stop_nic(struct s2io_nic *nic)
2477 {
2478         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2479         register u64 val64 = 0;
2480         u16 interruptible;
2481
2482         /*  Disable all interrupts */
2483         en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2484         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2485         interruptible |= TX_PIC_INTR;
2486         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2487
2488         /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2489         val64 = readq(&bar0->adapter_control);
2490         val64 &= ~(ADAPTER_CNTL_EN);
2491         writeq(val64, &bar0->adapter_control);
2492 }
2493
2494 /**
2495  *  fill_rx_buffers - Allocates the Rx side skbs
2496  *  @ring_info: per ring structure
2497  *  @from_card_up: If this is true, we will map the buffer to get
2498  *     the dma address for buf0 and buf1 to give it to the card.
2499  *     Else we will sync the already mapped buffer to give it to the card.
2500  *  Description:
2501  *  The function allocates Rx side skbs and puts the physical
2502  *  address of these buffers into the RxD buffer pointers, so that the NIC
2503  *  can DMA the received frame into these locations.
2504  *  The NIC supports 3 receive modes, viz
2505  *  1. single buffer,
2506  *  2. three buffer and
2507  *  3. Five buffer modes.
2508  *  Each mode defines how many fragments the received frame will be split
2509  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2510  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2511  *  is split into 3 fragments. As of now only single buffer mode is
2512  *  supported.
2513  *   Return Value:
2514  *  SUCCESS on success or an appropriate -ve value on failure.
2515  */
2516 static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2517                            int from_card_up)
2518 {
2519         struct sk_buff *skb;
2520         struct RxD_t *rxdp;
2521         int off, size, block_no, block_no1;
2522         u32 alloc_tab = 0;
2523         u32 alloc_cnt;
2524         u64 tmp;
2525         struct buffAdd *ba;
2526         struct RxD_t *first_rxdp = NULL;
2527         u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2528         int rxd_index = 0;
2529         struct RxD1 *rxdp1;
2530         struct RxD3 *rxdp3;
2531         struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
2532
2533         alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2534
2535         block_no1 = ring->rx_curr_get_info.block_index;
2536         while (alloc_tab < alloc_cnt) {
2537                 block_no = ring->rx_curr_put_info.block_index;
2538
2539                 off = ring->rx_curr_put_info.offset;
2540
2541                 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2542
2543                 rxd_index = off + 1;
2544                 if (block_no)
2545                         rxd_index += (block_no * ring->rxd_count);
2546
2547                 if ((block_no == block_no1) &&
2548                     (off == ring->rx_curr_get_info.offset) &&
2549                     (rxdp->Host_Control)) {
2550                         DBG_PRINT(INTR_DBG, "%s: Get and Put", ring->dev->name);
2551                         DBG_PRINT(INTR_DBG, " info equated\n");
2552                         goto end;
2553                 }
2554                 if (off && (off == ring->rxd_count)) {
2555                         ring->rx_curr_put_info.block_index++;
2556                         if (ring->rx_curr_put_info.block_index ==
2557                             ring->block_count)
2558                                 ring->rx_curr_put_info.block_index = 0;
2559                         block_no = ring->rx_curr_put_info.block_index;
2560                         off = 0;
2561                         ring->rx_curr_put_info.offset = off;
2562                         rxdp = ring->rx_blocks[block_no].block_virt_addr;
2563                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2564                                   ring->dev->name, rxdp);
2565
2566                 }
2567
2568                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2569                     ((ring->rxd_mode == RXD_MODE_3B) &&
2570                      (rxdp->Control_2 & s2BIT(0)))) {
2571                         ring->rx_curr_put_info.offset = off;
2572                         goto end;
2573                 }
2574                 /* calculate size of skb based on ring mode */
2575                 size = ring->mtu +
2576                         HEADER_ETHERNET_II_802_3_SIZE +
2577                         HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2578                 if (ring->rxd_mode == RXD_MODE_1)
2579                         size += NET_IP_ALIGN;
2580                 else
2581                         size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2582
2583                 /* allocate skb */
2584                 skb = dev_alloc_skb(size);
2585                 if (!skb) {
2586                         DBG_PRINT(INFO_DBG, "%s: Out of ", ring->dev->name);
2587                         DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
2588                         if (first_rxdp) {
2589                                 wmb();
2590                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2591                         }
2592                         swstats->mem_alloc_fail_cnt++;
2593
2594                         return -ENOMEM ;
2595                 }
2596                 swstats->mem_allocated += skb->truesize;
2597
2598                 if (ring->rxd_mode == RXD_MODE_1) {
2599                         /* 1 buffer mode - normal operation mode */
2600                         rxdp1 = (struct RxD1 *)rxdp;
2601                         memset(rxdp, 0, sizeof(struct RxD1));
2602                         skb_reserve(skb, NET_IP_ALIGN);
2603                         rxdp1->Buffer0_ptr =
2604                                 pci_map_single(ring->pdev, skb->data,
2605                                                size - NET_IP_ALIGN,
2606                                                PCI_DMA_FROMDEVICE);
2607                         if (pci_dma_mapping_error(nic->pdev,
2608                                                   rxdp1->Buffer0_ptr))
2609                                 goto pci_map_failed;
2610
2611                         rxdp->Control_2 =
2612                                 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2613                         rxdp->Host_Control = (unsigned long)skb;
2614                 } else if (ring->rxd_mode == RXD_MODE_3B) {
2615                         /*
2616                          * 2 buffer mode -
2617                          * 2 buffer mode provides 128
2618                          * byte aligned receive buffers.
2619                          */
2620
2621                         rxdp3 = (struct RxD3 *)rxdp;
2622                         /* save buffer pointers to avoid frequent dma mapping */
2623                         Buffer0_ptr = rxdp3->Buffer0_ptr;
2624                         Buffer1_ptr = rxdp3->Buffer1_ptr;
2625                         memset(rxdp, 0, sizeof(struct RxD3));
2626                         /* restore the buffer pointers for dma sync*/
2627                         rxdp3->Buffer0_ptr = Buffer0_ptr;
2628                         rxdp3->Buffer1_ptr = Buffer1_ptr;
2629
2630                         ba = &ring->ba[block_no][off];
2631                         skb_reserve(skb, BUF0_LEN);
2632                         tmp = (u64)(unsigned long)skb->data;
2633                         tmp += ALIGN_SIZE;
2634                         tmp &= ~ALIGN_SIZE;
2635                         skb->data = (void *) (unsigned long)tmp;
2636                         skb_reset_tail_pointer(skb);
2637
2638                         if (from_card_up) {
2639                                 rxdp3->Buffer0_ptr =
2640                                         pci_map_single(ring->pdev, ba->ba_0,
2641                                                        BUF0_LEN,
2642                                                        PCI_DMA_FROMDEVICE);
2643                                 if (pci_dma_mapping_error(nic->pdev,
2644                                                           rxdp3->Buffer0_ptr))
2645                                         goto pci_map_failed;
2646                         } else
2647                                 pci_dma_sync_single_for_device(ring->pdev,
2648                                                                (dma_addr_t)rxdp3->Buffer0_ptr,
2649                                                                BUF0_LEN,
2650                                                                PCI_DMA_FROMDEVICE);
2651
2652                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2653                         if (ring->rxd_mode == RXD_MODE_3B) {
2654                                 /* Two buffer mode */
2655
2656                                 /*
2657                                  * Buffer2 will have L3/L4 header plus
2658                                  * L4 payload
2659                                  */
2660                                 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2661                                                                     skb->data,
2662                                                                     ring->mtu + 4,
2663                                                                     PCI_DMA_FROMDEVICE);
2664
2665                                 if (pci_dma_mapping_error(nic->pdev,
2666                                                           rxdp3->Buffer2_ptr))
2667                                         goto pci_map_failed;
2668
2669                                 if (from_card_up) {
2670                                         rxdp3->Buffer1_ptr =
2671                                                 pci_map_single(ring->pdev,
2672                                                                ba->ba_1,
2673                                                                BUF1_LEN,
2674                                                                PCI_DMA_FROMDEVICE);
2675
2676                                         if (pci_dma_mapping_error(nic->pdev,
2677                                                                   rxdp3->Buffer1_ptr)) {
2678                                                 pci_unmap_single(ring->pdev,
2679                                                                  (dma_addr_t)(unsigned long)
2680                                                                  skb->data,
2681                                                                  ring->mtu + 4,
2682                                                                  PCI_DMA_FROMDEVICE);
2683                                                 goto pci_map_failed;
2684                                         }
2685                                 }
2686                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2687                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2688                                         (ring->mtu + 4);
2689                         }
2690                         rxdp->Control_2 |= s2BIT(0);
2691                         rxdp->Host_Control = (unsigned long) (skb);
2692                 }
2693                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2694                         rxdp->Control_1 |= RXD_OWN_XENA;
2695                 off++;
2696                 if (off == (ring->rxd_count + 1))
2697                         off = 0;
2698                 ring->rx_curr_put_info.offset = off;
2699
2700                 rxdp->Control_2 |= SET_RXD_MARKER;
2701                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2702                         if (first_rxdp) {
2703                                 wmb();
2704                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2705                         }
2706                         first_rxdp = rxdp;
2707                 }
2708                 ring->rx_bufs_left += 1;
2709                 alloc_tab++;
2710         }
2711
2712 end:
2713         /* Transfer ownership of first descriptor to adapter just before
2714          * exiting. Before that, use memory barrier so that ownership
2715          * and other fields are seen by adapter correctly.
2716          */
2717         if (first_rxdp) {
2718                 wmb();
2719                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2720         }
2721
2722         return SUCCESS;
2723
2724 pci_map_failed:
2725         swstats->pci_map_fail_cnt++;
2726         swstats->mem_freed += skb->truesize;
2727         dev_kfree_skb_irq(skb);
2728         return -ENOMEM;
2729 }
2730
2731 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2732 {
2733         struct net_device *dev = sp->dev;
2734         int j;
2735         struct sk_buff *skb;
2736         struct RxD_t *rxdp;
2737         struct buffAdd *ba;
2738         struct RxD1 *rxdp1;
2739         struct RxD3 *rxdp3;
2740         struct mac_info *mac_control = &sp->mac_control;
2741         struct stat_block *stats = mac_control->stats_info;
2742         struct swStat *swstats = &stats->sw_stat;
2743
2744         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2745                 rxdp = mac_control->rings[ring_no].
2746                         rx_blocks[blk].rxds[j].virt_addr;
2747                 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2748                 if (!skb)
2749                         continue;
2750                 if (sp->rxd_mode == RXD_MODE_1) {
2751                         rxdp1 = (struct RxD1 *)rxdp;
2752                         pci_unmap_single(sp->pdev,
2753                                          (dma_addr_t)rxdp1->Buffer0_ptr,
2754                                          dev->mtu +
2755                                          HEADER_ETHERNET_II_802_3_SIZE +
2756                                          HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2757                                          PCI_DMA_FROMDEVICE);
2758                         memset(rxdp, 0, sizeof(struct RxD1));
2759                 } else if (sp->rxd_mode == RXD_MODE_3B) {
2760                         rxdp3 = (struct RxD3 *)rxdp;
2761                         ba = &mac_control->rings[ring_no].ba[blk][j];
2762                         pci_unmap_single(sp->pdev,
2763                                          (dma_addr_t)rxdp3->Buffer0_ptr,
2764                                          BUF0_LEN,
2765                                          PCI_DMA_FROMDEVICE);
2766                         pci_unmap_single(sp->pdev,
2767                                          (dma_addr_t)rxdp3->Buffer1_ptr,
2768                                          BUF1_LEN,
2769                                          PCI_DMA_FROMDEVICE);
2770                         pci_unmap_single(sp->pdev,
2771                                          (dma_addr_t)rxdp3->Buffer2_ptr,
2772                                          dev->mtu + 4,
2773                                          PCI_DMA_FROMDEVICE);
2774                         memset(rxdp, 0, sizeof(struct RxD3));
2775                 }
2776                 swstats->mem_freed += skb->truesize;
2777                 dev_kfree_skb(skb);
2778                 mac_control->rings[ring_no].rx_bufs_left -= 1;
2779         }
2780 }
2781
2782 /**
2783  *  free_rx_buffers - Frees all Rx buffers
2784  *  @sp: device private variable.
2785  *  Description:
2786  *  This function will free all Rx buffers allocated by host.
2787  *  Return Value:
2788  *  NONE.
2789  */
2790
2791 static void free_rx_buffers(struct s2io_nic *sp)
2792 {
2793         struct net_device *dev = sp->dev;
2794         int i, blk = 0, buf_cnt = 0;
2795         struct config_param *config = &sp->config;
2796         struct mac_info *mac_control = &sp->mac_control;
2797
2798         for (i = 0; i < config->rx_ring_num; i++) {
2799                 struct ring_info *ring = &mac_control->rings[i];
2800
2801                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2802                         free_rxd_blk(sp, i, blk);
2803
2804                 ring->rx_curr_put_info.block_index = 0;
2805                 ring->rx_curr_get_info.block_index = 0;
2806                 ring->rx_curr_put_info.offset = 0;
2807                 ring->rx_curr_get_info.offset = 0;
2808                 ring->rx_bufs_left = 0;
2809                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2810                           dev->name, buf_cnt, i);
2811         }
2812 }
2813
2814 static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2815 {
2816         if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2817                 DBG_PRINT(INFO_DBG, "%s:Out of memory", ring->dev->name);
2818                 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
2819         }
2820         return 0;
2821 }
2822
2823 /**
2824  * s2io_poll - Rx interrupt handler for NAPI support
2825  * @napi : pointer to the napi structure.
2826  * @budget : The number of packets that were budgeted to be processed
2827  * during  one pass through the 'Poll" function.
2828  * Description:
2829  * Comes into picture only if NAPI support has been incorporated. It does
2830  * the same thing that rx_intr_handler does, but not in a interrupt context
2831  * also It will process only a given number of packets.
2832  * Return value:
2833  * 0 on success and 1 if there are No Rx packets to be processed.
2834  */
2835
2836 static int s2io_poll_msix(struct napi_struct *napi, int budget)
2837 {
2838         struct ring_info *ring = container_of(napi, struct ring_info, napi);
2839         struct net_device *dev = ring->dev;
2840         int pkts_processed = 0;
2841         u8 __iomem *addr = NULL;
2842         u8 val8 = 0;
2843         struct s2io_nic *nic = netdev_priv(dev);
2844         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2845         int budget_org = budget;
2846
2847         if (unlikely(!is_s2io_card_up(nic)))
2848                 return 0;
2849
2850         pkts_processed = rx_intr_handler(ring, budget);
2851         s2io_chk_rx_buffers(nic, ring);
2852
2853         if (pkts_processed < budget_org) {
2854                 napi_complete(napi);
2855                 /*Re Enable MSI-Rx Vector*/
2856                 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2857                 addr += 7 - ring->ring_no;
2858                 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2859                 writeb(val8, addr);
2860                 val8 = readb(addr);
2861         }
2862         return pkts_processed;
2863 }
2864
2865 static int s2io_poll_inta(struct napi_struct *napi, int budget)
2866 {
2867         struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2868         int pkts_processed = 0;
2869         int ring_pkts_processed, i;
2870         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2871         int budget_org = budget;
2872         struct config_param *config = &nic->config;
2873         struct mac_info *mac_control = &nic->mac_control;
2874
2875         if (unlikely(!is_s2io_card_up(nic)))
2876                 return 0;
2877
2878         for (i = 0; i < config->rx_ring_num; i++) {
2879                 struct ring_info *ring = &mac_control->rings[i];
2880                 ring_pkts_processed = rx_intr_handler(ring, budget);
2881                 s2io_chk_rx_buffers(nic, ring);
2882                 pkts_processed += ring_pkts_processed;
2883                 budget -= ring_pkts_processed;
2884                 if (budget <= 0)
2885                         break;
2886         }
2887         if (pkts_processed < budget_org) {
2888                 napi_complete(napi);
2889                 /* Re enable the Rx interrupts for the ring */
2890                 writeq(0, &bar0->rx_traffic_mask);
2891                 readl(&bar0->rx_traffic_mask);
2892         }
2893         return pkts_processed;
2894 }
2895
2896 #ifdef CONFIG_NET_POLL_CONTROLLER
2897 /**
2898  * s2io_netpoll - netpoll event handler entry point
2899  * @dev : pointer to the device structure.
2900  * Description:
2901  *      This function will be called by upper layer to check for events on the
2902  * interface in situations where interrupts are disabled. It is used for
2903  * specific in-kernel networking tasks, such as remote consoles and kernel
2904  * debugging over the network (example netdump in RedHat).
2905  */
2906 static void s2io_netpoll(struct net_device *dev)
2907 {
2908         struct s2io_nic *nic = netdev_priv(dev);
2909         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2910         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2911         int i;
2912         struct config_param *config = &nic->config;
2913         struct mac_info *mac_control = &nic->mac_control;
2914
2915         if (pci_channel_offline(nic->pdev))
2916                 return;
2917
2918         disable_irq(dev->irq);
2919
2920         writeq(val64, &bar0->rx_traffic_int);
2921         writeq(val64, &bar0->tx_traffic_int);
2922
2923         /* we need to free up the transmitted skbufs or else netpoll will
2924          * run out of skbs and will fail and eventually netpoll application such
2925          * as netdump will fail.
2926          */
2927         for (i = 0; i < config->tx_fifo_num; i++)
2928                 tx_intr_handler(&mac_control->fifos[i]);
2929
2930         /* check for received packet and indicate up to network */
2931         for (i = 0; i < config->rx_ring_num; i++) {
2932                 struct ring_info *ring = &mac_control->rings[i];
2933
2934                 rx_intr_handler(ring, 0);
2935         }
2936
2937         for (i = 0; i < config->rx_ring_num; i++) {
2938                 struct ring_info *ring = &mac_control->rings[i];
2939
2940                 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2941                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2942                         DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
2943                         break;
2944                 }
2945         }
2946         enable_irq(dev->irq);
2947         return;
2948 }
2949 #endif
2950
2951 /**
2952  *  rx_intr_handler - Rx interrupt handler
2953  *  @ring_info: per ring structure.
2954  *  @budget: budget for napi processing.
2955  *  Description:
2956  *  If the interrupt is because of a received frame or if the
2957  *  receive ring contains fresh as yet un-processed frames,this function is
2958  *  called. It picks out the RxD at which place the last Rx processing had
2959  *  stopped and sends the skb to the OSM's Rx handler and then increments
2960  *  the offset.
2961  *  Return Value:
2962  *  No. of napi packets processed.
2963  */
2964 static int rx_intr_handler(struct ring_info *ring_data, int budget)
2965 {
2966         int get_block, put_block;
2967         struct rx_curr_get_info get_info, put_info;
2968         struct RxD_t *rxdp;
2969         struct sk_buff *skb;
2970         int pkt_cnt = 0, napi_pkts = 0;
2971         int i;
2972         struct RxD1 *rxdp1;
2973         struct RxD3 *rxdp3;
2974
2975         get_info = ring_data->rx_curr_get_info;
2976         get_block = get_info.block_index;
2977         memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2978         put_block = put_info.block_index;
2979         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2980
2981         while (RXD_IS_UP2DT(rxdp)) {
2982                 /*
2983                  * If your are next to put index then it's
2984                  * FIFO full condition
2985                  */
2986                 if ((get_block == put_block) &&
2987                     (get_info.offset + 1) == put_info.offset) {
2988                         DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2989                                   ring_data->dev->name);
2990                         break;
2991                 }
2992                 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2993                 if (skb == NULL) {
2994                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
2995                                   ring_data->dev->name);
2996                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2997                         return 0;
2998                 }
2999                 if (ring_data->rxd_mode == RXD_MODE_1) {
3000                         rxdp1 = (struct RxD1 *)rxdp;
3001                         pci_unmap_single(ring_data->pdev, (dma_addr_t)
3002                                          rxdp1->Buffer0_ptr,
3003                                          ring_data->mtu +
3004                                          HEADER_ETHERNET_II_802_3_SIZE +
3005                                          HEADER_802_2_SIZE +
3006                                          HEADER_SNAP_SIZE,
3007                                          PCI_DMA_FROMDEVICE);
3008                 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
3009                         rxdp3 = (struct RxD3 *)rxdp;
3010                         pci_dma_sync_single_for_cpu(ring_data->pdev,
3011                                                     (dma_addr_t)rxdp3->Buffer0_ptr,
3012                                                     BUF0_LEN,
3013                                                     PCI_DMA_FROMDEVICE);
3014                         pci_unmap_single(ring_data->pdev,
3015                                          (dma_addr_t)rxdp3->Buffer2_ptr,
3016                                          ring_data->mtu + 4,
3017                                          PCI_DMA_FROMDEVICE);
3018                 }
3019                 prefetch(skb->data);
3020                 rx_osm_handler(ring_data, rxdp);
3021                 get_info.offset++;
3022                 ring_data->rx_curr_get_info.offset = get_info.offset;
3023                 rxdp = ring_data->rx_blocks[get_block].
3024                         rxds[get_info.offset].virt_addr;
3025                 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
3026                         get_info.offset = 0;
3027                         ring_data->rx_curr_get_info.offset = get_info.offset;
3028                         get_block++;
3029                         if (get_block == ring_data->block_count)
3030                                 get_block = 0;
3031                         ring_data->rx_curr_get_info.block_index = get_block;
3032                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3033                 }
3034
3035                 if (ring_data->nic->config.napi) {
3036                         budget--;
3037                         napi_pkts++;
3038                         if (!budget)
3039                                 break;
3040                 }
3041                 pkt_cnt++;
3042                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3043                         break;
3044         }
3045         if (ring_data->lro) {
3046                 /* Clear all LRO sessions before exiting */
3047                 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
3048                         struct lro *lro = &ring_data->lro0_n[i];
3049                         if (lro->in_use) {
3050                                 update_L3L4_header(ring_data->nic, lro);
3051                                 queue_rx_frame(lro->parent, lro->vlan_tag);
3052                                 clear_lro_session(lro);
3053                         }
3054                 }
3055         }
3056         return napi_pkts;
3057 }
3058
3059 /**
3060  *  tx_intr_handler - Transmit interrupt handler
3061  *  @nic : device private variable
3062  *  Description:
3063  *  If an interrupt was raised to indicate DMA complete of the
3064  *  Tx packet, this function is called. It identifies the last TxD
3065  *  whose buffer was freed and frees all skbs whose data have already
3066  *  DMA'ed into the NICs internal memory.
3067  *  Return Value:
3068  *  NONE
3069  */
3070
3071 static void tx_intr_handler(struct fifo_info *fifo_data)
3072 {
3073         struct s2io_nic *nic = fifo_data->nic;
3074         struct tx_curr_get_info get_info, put_info;
3075         struct sk_buff *skb = NULL;
3076         struct TxD *txdlp;
3077         int pkt_cnt = 0;
3078         unsigned long flags = 0;
3079         u8 err_mask;
3080         struct stat_block *stats = nic->mac_control.stats_info;
3081         struct swStat *swstats = &stats->sw_stat;
3082
3083         if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3084                 return;
3085
3086         get_info = fifo_data->tx_curr_get_info;
3087         memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3088         txdlp = (struct TxD *)
3089                 fifo_data->list_info[get_info.offset].list_virt_addr;
3090         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3091                (get_info.offset != put_info.offset) &&
3092                (txdlp->Host_Control)) {
3093                 /* Check for TxD errors */
3094                 if (txdlp->Control_1 & TXD_T_CODE) {
3095                         unsigned long long err;
3096                         err = txdlp->Control_1 & TXD_T_CODE;
3097                         if (err & 0x1) {
3098                                 swstats->parity_err_cnt++;
3099                         }
3100
3101                         /* update t_code statistics */
3102                         err_mask = err >> 48;
3103                         switch (err_mask) {
3104                         case 2:
3105                                 swstats->tx_buf_abort_cnt++;
3106                                 break;
3107
3108                         case 3:
3109                                 swstats->tx_desc_abort_cnt++;
3110                                 break;
3111
3112                         case 7:
3113                                 swstats->tx_parity_err_cnt++;
3114                                 break;
3115
3116                         case 10:
3117                                 swstats->tx_link_loss_cnt++;
3118                                 break;
3119
3120                         case 15:
3121                                 swstats->tx_list_proc_err_cnt++;
3122                                 break;
3123                         }
3124                 }
3125
3126                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3127                 if (skb == NULL) {
3128                         spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3129                         DBG_PRINT(ERR_DBG, "%s: Null skb ", __func__);
3130                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
3131                         return;
3132                 }
3133                 pkt_cnt++;
3134
3135                 /* Updating the statistics block */
3136                 nic->dev->stats.tx_bytes += skb->len;
3137                 swstats->mem_freed += skb->truesize;
3138                 dev_kfree_skb_irq(skb);
3139
3140                 get_info.offset++;
3141                 if (get_info.offset == get_info.fifo_len + 1)
3142                         get_info.offset = 0;
3143                 txdlp = (struct TxD *)
3144                         fifo_data->list_info[get_info.offset].list_virt_addr;
3145                 fifo_data->tx_curr_get_info.offset = get_info.offset;
3146         }
3147
3148         s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3149
3150         spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3151 }
3152
3153 /**
3154  *  s2io_mdio_write - Function to write in to MDIO registers
3155  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3156  *  @addr     : address value
3157  *  @value    : data value
3158  *  @dev      : pointer to net_device structure
3159  *  Description:
3160  *  This function is used to write values to the MDIO registers
3161  *  NONE
3162  */
3163 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3164                             struct net_device *dev)
3165 {
3166         u64 val64;
3167         struct s2io_nic *sp = netdev_priv(dev);
3168         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3169
3170         /* address transaction */
3171         val64 = MDIO_MMD_INDX_ADDR(addr) |
3172                 MDIO_MMD_DEV_ADDR(mmd_type) |
3173                 MDIO_MMS_PRT_ADDR(0x0);
3174         writeq(val64, &bar0->mdio_control);
3175         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3176         writeq(val64, &bar0->mdio_control);
3177         udelay(100);
3178
3179         /* Data transaction */
3180         val64 = MDIO_MMD_INDX_ADDR(addr) |
3181                 MDIO_MMD_DEV_ADDR(mmd_type) |
3182                 MDIO_MMS_PRT_ADDR(0x0) |
3183                 MDIO_MDIO_DATA(value) |
3184                 MDIO_OP(MDIO_OP_WRITE_TRANS);
3185         writeq(val64, &bar0->mdio_control);
3186         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3187         writeq(val64, &bar0->mdio_control);
3188         udelay(100);
3189
3190         val64 = MDIO_MMD_INDX_ADDR(addr) |
3191                 MDIO_MMD_DEV_ADDR(mmd_type) |
3192                 MDIO_MMS_PRT_ADDR(0x0) |
3193                 MDIO_OP(MDIO_OP_READ_TRANS);
3194         writeq(val64, &bar0->mdio_control);
3195         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3196         writeq(val64, &bar0->mdio_control);
3197         udelay(100);
3198 }
3199
3200 /**
3201  *  s2io_mdio_read - Function to write in to MDIO registers
3202  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3203  *  @addr     : address value
3204  *  @dev      : pointer to net_device structure
3205  *  Description:
3206  *  This function is used to read values to the MDIO registers
3207  *  NONE
3208  */
3209 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3210 {
3211         u64 val64 = 0x0;
3212         u64 rval64 = 0x0;
3213         struct s2io_nic *sp = netdev_priv(dev);
3214         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3215
3216         /* address transaction */
3217         val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3218                          | MDIO_MMD_DEV_ADDR(mmd_type)
3219                          | MDIO_MMS_PRT_ADDR(0x0));
3220         writeq(val64, &bar0->mdio_control);
3221         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3222         writeq(val64, &bar0->mdio_control);
3223         udelay(100);
3224
3225         /* Data transaction */
3226         val64 = MDIO_MMD_INDX_ADDR(addr) |
3227                 MDIO_MMD_DEV_ADDR(mmd_type) |
3228                 MDIO_MMS_PRT_ADDR(0x0) |
3229                 MDIO_OP(MDIO_OP_READ_TRANS);
3230         writeq(val64, &bar0->mdio_control);
3231         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3232         writeq(val64, &bar0->mdio_control);
3233         udelay(100);
3234
3235         /* Read the value from regs */
3236         rval64 = readq(&bar0->mdio_control);
3237         rval64 = rval64 & 0xFFFF0000;
3238         rval64 = rval64 >> 16;
3239         return rval64;
3240 }
3241
3242 /**
3243  *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
3244  *  @counter      : couter value to be updated
3245  *  @flag         : flag to indicate the status
3246  *  @type         : counter type
3247  *  Description:
3248  *  This function is to check the status of the xpak counters value
3249  *  NONE
3250  */
3251
3252 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3253                                   u16 flag, u16 type)
3254 {
3255         u64 mask = 0x3;
3256         u64 val64;
3257         int i;
3258         for (i = 0; i < index; i++)
3259                 mask = mask << 0x2;
3260
3261         if (flag > 0) {
3262                 *counter = *counter + 1;
3263                 val64 = *regs_stat & mask;
3264                 val64 = val64 >> (index * 0x2);
3265                 val64 = val64 + 1;
3266                 if (val64 == 3) {
3267                         switch (type) {
3268                         case 1:
3269                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3270                                           "service. Excessive temperatures may "
3271                                           "result in premature transceiver "
3272                                           "failure \n");
3273                                 break;
3274                         case 2:
3275                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3276                                           "service Excessive bias currents may "
3277                                           "indicate imminent laser diode "
3278                                           "failure \n");
3279                                 break;
3280                         case 3:
3281                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3282                                           "service Excessive laser output "
3283                                           "power may saturate far-end "
3284                                           "receiver\n");
3285                                 break;
3286                         default:
3287                                 DBG_PRINT(ERR_DBG,
3288                                           "Incorrect XPAK Alarm type\n");
3289                         }
3290                         val64 = 0x0;
3291                 }
3292                 val64 = val64 << (index * 0x2);
3293                 *regs_stat = (*regs_stat & (~mask)) | (val64);
3294
3295         } else {
3296                 *regs_stat = *regs_stat & (~mask);
3297         }
3298 }
3299
3300 /**
3301  *  s2io_updt_xpak_counter - Function to update the xpak counters
3302  *  @dev         : pointer to net_device struct
3303  *  Description:
3304  *  This function is to upate the status of the xpak counters value
3305  *  NONE
3306  */
3307 static void s2io_updt_xpak_counter(struct net_device *dev)
3308 {
3309         u16 flag  = 0x0;
3310         u16 type  = 0x0;
3311         u16 val16 = 0x0;
3312         u64 val64 = 0x0;
3313         u64 addr  = 0x0;
3314
3315         struct s2io_nic *sp = netdev_priv(dev);
3316         struct stat_block *stats = sp->mac_control.stats_info;
3317         struct xpakStat *xstats = &stats->xpak_stat;
3318
3319         /* Check the communication with the MDIO slave */
3320         addr = MDIO_CTRL1;
3321         val64 = 0x0;
3322         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3323         if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
3324                 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3325                           "Returned %llx\n", (unsigned long long)val64);
3326                 return;
3327         }
3328
3329         /* Check for the expected value of control reg 1 */
3330         if (val64 != MDIO_CTRL1_SPEED10G) {
3331                 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3332                 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x%x\n",
3333                           (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
3334                 return;
3335         }
3336
3337         /* Loading the DOM register to MDIO register */
3338         addr = 0xA100;
3339         s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3340         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3341
3342         /* Reading the Alarm flags */
3343         addr = 0xA070;
3344         val64 = 0x0;
3345         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3346
3347         flag = CHECKBIT(val64, 0x7);
3348         type = 1;
3349         s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3350                               &xstats->xpak_regs_stat,
3351                               0x0, flag, type);
3352
3353         if (CHECKBIT(val64, 0x6))
3354                 xstats->alarm_transceiver_temp_low++;
3355
3356         flag = CHECKBIT(val64, 0x3);
3357         type = 2;
3358         s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3359                               &xstats->xpak_regs_stat,
3360                               0x2, flag, type);
3361
3362         if (CHECKBIT(val64, 0x2))
3363                 xstats->alarm_laser_bias_current_low++;
3364
3365         flag = CHECKBIT(val64, 0x1);
3366         type = 3;
3367         s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3368                               &xstats->xpak_regs_stat,
3369                               0x4, flag, type);
3370
3371         if (CHECKBIT(val64, 0x0))
3372                 xstats->alarm_laser_output_power_low++;
3373
3374         /* Reading the Warning flags */
3375         addr = 0xA074;
3376         val64 = 0x0;
3377         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3378
3379         if (CHECKBIT(val64, 0x7))
3380                 xstats->warn_transceiver_temp_high++;
3381
3382         if (CHECKBIT(val64, 0x6))
3383                 xstats->warn_transceiver_temp_low++;
3384
3385         if (CHECKBIT(val64, 0x3))
3386                 xstats->warn_laser_bias_current_high++;
3387
3388         if (CHECKBIT(val64, 0x2))
3389                 xstats->warn_laser_bias_current_low++;
3390
3391         if (CHECKBIT(val64, 0x1))
3392                 xstats->warn_laser_output_power_high++;
3393
3394         if (CHECKBIT(val64, 0x0))
3395                 xstats->warn_laser_output_power_low++;
3396 }
3397
3398 /**
3399  *  wait_for_cmd_complete - waits for a command to complete.
3400  *  @sp : private member of the device structure, which is a pointer to the
3401  *  s2io_nic structure.
3402  *  Description: Function that waits for a command to Write into RMAC
3403  *  ADDR DATA registers to be completed and returns either success or
3404  *  error depending on whether the command was complete or not.
3405  *  Return value:
3406  *   SUCCESS on success and FAILURE on failure.
3407  */
3408
3409 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3410                                  int bit_state)
3411 {
3412         int ret = FAILURE, cnt = 0, delay = 1;
3413         u64 val64;
3414
3415         if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3416                 return FAILURE;
3417
3418         do {
3419                 val64 = readq(addr);
3420                 if (bit_state == S2IO_BIT_RESET) {
3421                         if (!(val64 & busy_bit)) {
3422                                 ret = SUCCESS;
3423                                 break;
3424                         }
3425                 } else {
3426                         if (!(val64 & busy_bit)) {
3427                                 ret = SUCCESS;
3428                                 break;
3429                         }
3430                 }
3431
3432                 if (in_interrupt())
3433                         mdelay(delay);
3434                 else
3435                         msleep(delay);
3436
3437                 if (++cnt >= 10)
3438                         delay = 50;
3439         } while (cnt < 20);
3440         return ret;
3441 }
3442 /*
3443  * check_pci_device_id - Checks if the device id is supported
3444  * @id : device id
3445  * Description: Function to check if the pci device id is supported by driver.
3446  * Return value: Actual device id if supported else PCI_ANY_ID
3447  */
3448 static u16 check_pci_device_id(u16 id)
3449 {
3450         switch (id) {
3451         case PCI_DEVICE_ID_HERC_WIN:
3452         case PCI_DEVICE_ID_HERC_UNI:
3453                 return XFRAME_II_DEVICE;
3454         case PCI_DEVICE_ID_S2IO_UNI:
3455         case PCI_DEVICE_ID_S2IO_WIN:
3456                 return XFRAME_I_DEVICE;
3457         default:
3458                 return PCI_ANY_ID;
3459         }
3460 }
3461
3462 /**
3463  *  s2io_reset - Resets the card.
3464  *  @sp : private member of the device structure.
3465  *  Description: Function to Reset the card. This function then also
3466  *  restores the previously saved PCI configuration space registers as
3467  *  the card reset also resets the configuration space.
3468  *  Return value:
3469  *  void.
3470  */
3471
3472 static void s2io_reset(struct s2io_nic *sp)
3473 {
3474         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3475         u64 val64;
3476         u16 subid, pci_cmd;
3477         int i;
3478         u16 val16;
3479         unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3480         unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3481         struct stat_block *stats;
3482         struct swStat *swstats;
3483
3484         DBG_PRINT(INIT_DBG, "%s - Resetting XFrame card %s\n",
3485                   __func__, sp->dev->name);
3486
3487         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3488         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3489
3490         val64 = SW_RESET_ALL;
3491         writeq(val64, &bar0->sw_reset);
3492         if (strstr(sp->product_name, "CX4"))
3493                 msleep(750);
3494         msleep(250);
3495         for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3496
3497                 /* Restore the PCI state saved during initialization. */
3498                 pci_restore_state(sp->pdev);
3499                 pci_read_config_word(sp->pdev, 0x2, &val16);
3500                 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3501                         break;
3502                 msleep(200);
3503         }
3504
3505         if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3506                 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
3507
3508         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3509
3510         s2io_init_pci(sp);
3511
3512         /* Set swapper to enable I/O register access */
3513         s2io_set_swapper(sp);
3514
3515         /* restore mac_addr entries */
3516         do_s2io_restore_unicast_mc(sp);
3517
3518         /* Restore the MSIX table entries from local variables */
3519         restore_xmsi_data(sp);
3520
3521         /* Clear certain PCI/PCI-X fields after reset */
3522         if (sp->device_type == XFRAME_II_DEVICE) {
3523                 /* Clear "detected parity error" bit */
3524                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3525
3526                 /* Clearing PCIX Ecc status register */
3527                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3528
3529                 /* Clearing PCI_STATUS error reflected here */
3530                 writeq(s2BIT(62), &bar0->txpic_int_reg);
3531         }
3532
3533         /* Reset device statistics maintained by OS */
3534         memset(&sp->stats, 0, sizeof(struct net_device_stats));
3535
3536         stats = sp->mac_control.stats_info;
3537         swstats = &stats->sw_stat;
3538
3539         /* save link up/down time/cnt, reset/memory/watchdog cnt */
3540         up_cnt = swstats->link_up_cnt;
3541         down_cnt = swstats->link_down_cnt;
3542         up_time = swstats->link_up_time;
3543         down_time = swstats->link_down_time;
3544         reset_cnt = swstats->soft_reset_cnt;
3545         mem_alloc_cnt = swstats->mem_allocated;
3546         mem_free_cnt = swstats->mem_freed;
3547         watchdog_cnt = swstats->watchdog_timer_cnt;
3548
3549         memset(stats, 0, sizeof(struct stat_block));
3550
3551         /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3552         swstats->link_up_cnt = up_cnt;
3553         swstats->link_down_cnt = down_cnt;
3554         swstats->link_up_time = up_time;
3555         swstats->link_down_time = down_time;
3556         swstats->soft_reset_cnt = reset_cnt;
3557         swstats->mem_allocated = mem_alloc_cnt;
3558         swstats->mem_freed = mem_free_cnt;
3559         swstats->watchdog_timer_cnt = watchdog_cnt;
3560
3561         /* SXE-002: Configure link and activity LED to turn it off */
3562         subid = sp->pdev->subsystem_device;
3563         if (((subid & 0xFF) >= 0x07) &&
3564             (sp->device_type == XFRAME_I_DEVICE)) {
3565                 val64 = readq(&bar0->gpio_control);
3566                 val64 |= 0x0000800000000000ULL;
3567                 writeq(val64, &bar0->gpio_control);
3568                 val64 = 0x0411040400000000ULL;
3569                 writeq(val64, (void __iomem *)bar0 + 0x2700);
3570         }
3571
3572         /*
3573          * Clear spurious ECC interrupts that would have occured on
3574          * XFRAME II cards after reset.
3575          */
3576         if (sp->device_type == XFRAME_II_DEVICE) {
3577                 val64 = readq(&bar0->pcc_err_reg);
3578                 writeq(val64, &bar0->pcc_err_reg);
3579         }
3580
3581         sp->device_enabled_once = false;
3582 }
3583
3584 /**
3585  *  s2io_set_swapper - to set the swapper controle on the card
3586  *  @sp : private member of the device structure,
3587  *  pointer to the s2io_nic structure.
3588  *  Description: Function to set the swapper control on the card
3589  *  correctly depending on the 'endianness' of the system.
3590  *  Return value:
3591  *  SUCCESS on success and FAILURE on failure.
3592  */
3593
3594 static int s2io_set_swapper(struct s2io_nic *sp)
3595 {
3596         struct net_device *dev = sp->dev;
3597         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3598         u64 val64, valt, valr;
3599
3600         /*
3601          * Set proper endian settings and verify the same by reading
3602          * the PIF Feed-back register.
3603          */
3604
3605         val64 = readq(&bar0->pif_rd_swapper_fb);
3606         if (val64 != 0x0123456789ABCDEFULL) {
3607                 int i = 0;
3608                 u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
3609                                 0x8100008181000081ULL,  /* FE=1, SE=0 */
3610                                 0x4200004242000042ULL,  /* FE=0, SE=1 */
3611                                 0};                     /* FE=0, SE=0 */
3612
3613                 while (i < 4) {
3614                         writeq(value[i], &bar0->swapper_ctrl);
3615                         val64 = readq(&bar0->pif_rd_swapper_fb);
3616                         if (val64 == 0x0123456789ABCDEFULL)
3617                                 break;
3618                         i++;
3619                 }
3620                 if (i == 4) {
3621                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3622                                   dev->name);
3623                         DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3624                                   (unsigned long long)val64);
3625                         return FAILURE;
3626                 }
3627                 valr = value[i];
3628         } else {
3629                 valr = readq(&bar0->swapper_ctrl);
3630         }
3631
3632         valt = 0x0123456789ABCDEFULL;
3633         writeq(valt, &bar0->xmsi_address);
3634         val64 = readq(&bar0->xmsi_address);
3635
3636         if (val64 != valt) {
3637                 int i = 0;
3638                 u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
3639                                 0x0081810000818100ULL,  /* FE=1, SE=0 */
3640                                 0x0042420000424200ULL,  /* FE=0, SE=1 */
3641                                 0};                     /* FE=0, SE=0 */
3642
3643                 while (i < 4) {
3644                         writeq((value[i] | valr), &bar0->swapper_ctrl);
3645                         writeq(valt, &bar0->xmsi_address);
3646                         val64 = readq(&bar0->xmsi_address);
3647                         if (val64 == valt)
3648                                 break;
3649                         i++;
3650                 }
3651                 if (i == 4) {
3652                         unsigned long long x = val64;
3653                         DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3654                         DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3655                         return FAILURE;
3656                 }
3657         }
3658         val64 = readq(&bar0->swapper_ctrl);
3659         val64 &= 0xFFFF000000000000ULL;
3660
3661 #ifdef __BIG_ENDIAN
3662         /*
3663          * The device by default set to a big endian format, so a
3664          * big endian driver need not set anything.
3665          */
3666         val64 |= (SWAPPER_CTRL_TXP_FE |
3667                   SWAPPER_CTRL_TXP_SE |
3668                   SWAPPER_CTRL_TXD_R_FE |
3669                   SWAPPER_CTRL_TXD_W_FE |
3670                   SWAPPER_CTRL_TXF_R_FE |
3671                   SWAPPER_CTRL_RXD_R_FE |
3672                   SWAPPER_CTRL_RXD_W_FE |
3673                   SWAPPER_CTRL_RXF_W_FE |
3674                   SWAPPER_CTRL_XMSI_FE |
3675                   SWAPPER_CTRL_STATS_FE |
3676                   SWAPPER_CTRL_STATS_SE);
3677         if (sp->config.intr_type == INTA)
3678                 val64 |= SWAPPER_CTRL_XMSI_SE;
3679         writeq(val64, &bar0->swapper_ctrl);
3680 #else
3681         /*
3682          * Initially we enable all bits to make it accessible by the
3683          * driver, then we selectively enable only those bits that
3684          * we want to set.
3685          */
3686         val64 |= (SWAPPER_CTRL_TXP_FE |
3687                   SWAPPER_CTRL_TXP_SE |
3688                   SWAPPER_CTRL_TXD_R_FE |
3689                   SWAPPER_CTRL_TXD_R_SE |
3690                   SWAPPER_CTRL_TXD_W_FE |
3691                   SWAPPER_CTRL_TXD_W_SE |
3692                   SWAPPER_CTRL_TXF_R_FE |
3693                   SWAPPER_CTRL_RXD_R_FE |
3694                   SWAPPER_CTRL_RXD_R_SE |
3695                   SWAPPER_CTRL_RXD_W_FE |
3696                   SWAPPER_CTRL_RXD_W_SE |
3697                   SWAPPER_CTRL_RXF_W_FE |
3698                   SWAPPER_CTRL_XMSI_FE |
3699                   SWAPPER_CTRL_STATS_FE |
3700                   SWAPPER_CTRL_STATS_SE);
3701         if (sp->config.intr_type == INTA)
3702                 val64 |= SWAPPER_CTRL_XMSI_SE;
3703         writeq(val64, &bar0->swapper_ctrl);
3704 #endif
3705         val64 = readq(&bar0->swapper_ctrl);
3706
3707         /*
3708          * Verifying if endian settings are accurate by reading a
3709          * feedback register.
3710          */
3711         val64 = readq(&bar0->pif_rd_swapper_fb);
3712         if (val64 != 0x0123456789ABCDEFULL) {
3713                 /* Endian settings are incorrect, calls for another dekko. */
3714                 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3715                           dev->name);
3716                 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3717                           (unsigned long long)val64);
3718                 return FAILURE;
3719         }
3720
3721         return SUCCESS;
3722 }
3723
3724 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3725 {
3726         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3727         u64 val64;
3728         int ret = 0, cnt = 0;
3729
3730         do {
3731                 val64 = readq(&bar0->xmsi_access);
3732                 if (!(val64 & s2BIT(15)))
3733                         break;
3734                 mdelay(1);
3735                 cnt++;
3736         } while (cnt < 5);
3737         if (cnt == 5) {
3738                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3739                 ret = 1;
3740         }
3741
3742         return ret;
3743 }
3744
3745 static void restore_xmsi_data(struct s2io_nic *nic)
3746 {
3747         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3748         u64 val64;
3749         int i, msix_index;
3750
3751         if (nic->device_type == XFRAME_I_DEVICE)
3752                 return;
3753
3754         for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3755                 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3756                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3757                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3758                 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3759                 writeq(val64, &bar0->xmsi_access);
3760                 if (wait_for_msix_trans(nic, msix_index)) {
3761                         DBG_PRINT(ERR_DBG, "failed in %s\n", __func__);
3762                         continue;
3763                 }
3764         }
3765 }
3766
3767 static void store_xmsi_data(struct s2io_nic *nic)
3768 {
3769         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3770         u64 val64, addr, data;
3771         int i, msix_index;
3772
3773         if (nic->device_type == XFRAME_I_DEVICE)
3774                 return;
3775
3776         /* Store and display */
3777         for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3778                 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3779                 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3780                 writeq(val64, &bar0->xmsi_access);
3781                 if (wait_for_msix_trans(nic, msix_index)) {
3782                         DBG_PRINT(ERR_DBG, "failed in %s\n", __func__);
3783                         continue;
3784                 }
3785                 addr = readq(&bar0->xmsi_address);
3786                 data = readq(&bar0->xmsi_data);
3787                 if (addr && data) {
3788                         nic->msix_info[i].addr = addr;
3789                         nic->msix_info[i].data = data;
3790                 }
3791         }
3792 }
3793
3794 static int s2io_enable_msi_x(struct s2io_nic *nic)
3795 {
3796         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3797         u64 rx_mat;
3798         u16 msi_control; /* Temp variable */
3799         int ret, i, j, msix_indx = 1;
3800         int size;
3801         struct stat_block *stats = nic->mac_control.stats_info;
3802         struct swStat *swstats = &stats->sw_stat;
3803
3804         size = nic->num_entries * sizeof(struct msix_entry);
3805         nic->entries = kzalloc(size, GFP_KERNEL);
3806         if (!nic->entries) {
3807                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3808                           __func__);
3809                 swstats->mem_alloc_fail_cnt++;
3810                 return -ENOMEM;
3811         }
3812         swstats->mem_allocated += size;
3813
3814         size = nic->num_entries * sizeof(struct s2io_msix_entry);
3815         nic->s2io_entries = kzalloc(size, GFP_KERNEL);
3816         if (!nic->s2io_entries) {
3817                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3818                           __func__);
3819                 swstats->mem_alloc_fail_cnt++;
3820                 kfree(nic->entries);
3821                 swstats->mem_freed
3822                         += (nic->num_entries * sizeof(struct msix_entry));
3823                 return -ENOMEM;
3824         }
3825         swstats->mem_allocated += size;
3826
3827         nic->entries[0].entry = 0;
3828         nic->s2io_entries[0].entry = 0;
3829         nic->s2io_entries[0].in_use = MSIX_FLG;
3830         nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3831         nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3832
3833         for (i = 1; i < nic->num_entries; i++) {
3834                 nic->entries[i].entry = ((i - 1) * 8) + 1;
3835                 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3836                 nic->s2io_entries[i].arg = NULL;
3837                 nic->s2io_entries[i].in_use = 0;
3838         }
3839
3840         rx_mat = readq(&bar0->rx_mat);
3841         for (j = 0; j < nic->config.rx_ring_num; j++) {
3842                 rx_mat |= RX_MAT_SET(j, msix_indx);
3843                 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3844                 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3845                 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3846                 msix_indx += 8;
3847         }
3848         writeq(rx_mat, &bar0->rx_mat);
3849         readq(&bar0->rx_mat);
3850
3851         ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
3852         /* We fail init if error or we get less vectors than min required */
3853         if (ret) {
3854                 DBG_PRINT(ERR_DBG, "s2io: Enabling MSI-X failed\n");
3855                 kfree(nic->entries);
3856                 swstats->mem_freed += nic->num_entries *
3857                         sizeof(struct msix_entry);
3858                 kfree(nic->s2io_entries);
3859                 swstats->mem_freed += nic->num_entries *
3860                         sizeof(struct s2io_msix_entry);
3861                 nic->entries = NULL;
3862                 nic->s2io_entries = NULL;
3863                 return -ENOMEM;
3864         }
3865
3866         /*
3867          * To enable MSI-X, MSI also needs to be enabled, due to a bug
3868          * in the herc NIC. (Temp change, needs to be removed later)
3869          */
3870         pci_read_config_word(nic->pdev, 0x42, &msi_control);
3871         msi_control |= 0x1; /* Enable MSI */
3872         pci_write_config_word(nic->pdev, 0x42, msi_control);
3873
3874         return 0;
3875 }
3876
3877 /* Handle software interrupt used during MSI(X) test */
3878 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3879 {
3880         struct s2io_nic *sp = dev_id;
3881
3882         sp->msi_detected = 1;
3883         wake_up(&sp->msi_wait);
3884
3885         return IRQ_HANDLED;
3886 }
3887
3888 /* Test interrupt path by forcing a a software IRQ */
3889 static int s2io_test_msi(struct s2io_nic *sp)
3890 {
3891         struct pci_dev *pdev = sp->pdev;
3892         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3893         int err;
3894         u64 val64, saved64;
3895
3896         err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3897                           sp->name, sp);
3898         if (err) {
3899                 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3900                           sp->dev->name, pci_name(pdev), pdev->irq);
3901                 return err;
3902         }
3903
3904         init_waitqueue_head(&sp->msi_wait);
3905         sp->msi_detected = 0;
3906
3907         saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3908         val64 |= SCHED_INT_CTRL_ONE_SHOT;
3909         val64 |= SCHED_INT_CTRL_TIMER_EN;
3910         val64 |= SCHED_INT_CTRL_INT2MSI(1);
3911         writeq(val64, &bar0->scheduled_int_ctrl);
3912
3913         wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3914
3915         if (!sp->msi_detected) {
3916                 /* MSI(X) test failed, go back to INTx mode */
3917                 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3918                           "using MSI(X) during test\n", sp->dev->name,
3919                           pci_name(pdev));
3920
3921                 err = -EOPNOTSUPP;
3922         }
3923
3924         free_irq(sp->entries[1].vector, sp);
3925
3926         writeq(saved64, &bar0->scheduled_int_ctrl);
3927
3928         return err;
3929 }
3930
3931 static void remove_msix_isr(struct s2io_nic *sp)
3932 {
3933         int i;
3934         u16 msi_control;
3935
3936         for (i = 0; i < sp->num_entries; i++) {
3937                 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
3938                         int vector = sp->entries[i].vector;
3939                         void *arg = sp->s2io_entries[i].arg;
3940                         free_irq(vector, arg);
3941                 }
3942         }
3943
3944         kfree(sp->entries);
3945         kfree(sp->s2io_entries);
3946         sp->entries = NULL;
3947         sp->s2io_entries = NULL;
3948
3949         pci_read_config_word(sp->pdev, 0x42, &msi_control);
3950         msi_control &= 0xFFFE; /* Disable MSI */
3951         pci_write_config_word(sp->pdev, 0x42, msi_control);
3952
3953         pci_disable_msix(sp->pdev);
3954 }
3955
3956 static void remove_inta_isr(struct s2io_nic *sp)
3957 {
3958         struct net_device *dev = sp->dev;
3959
3960         free_irq(sp->pdev->irq, dev);
3961 }
3962
3963 /* ********************************************************* *
3964  * Functions defined below concern the OS part of the driver *
3965  * ********************************************************* */
3966
3967 /**
3968  *  s2io_open - open entry point of the driver
3969  *  @dev : pointer to the device structure.
3970  *  Description:
3971  *  This function is the open entry point of the driver. It mainly calls a
3972  *  function to allocate Rx buffers and inserts them into the buffer
3973  *  descriptors and then enables the Rx part of the NIC.
3974  *  Return value:
3975  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3976  *   file on failure.
3977  */
3978
3979 static int s2io_open(struct net_device *dev)
3980 {
3981         struct s2io_nic *sp = netdev_priv(dev);
3982         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
3983         int err = 0;
3984
3985         /*
3986          * Make sure you have link off by default every time
3987          * Nic is initialized
3988          */
3989         netif_carrier_off(dev);
3990         sp->last_link_state = 0;
3991
3992         /* Initialize H/W and enable interrupts */
3993         err = s2io_card_up(sp);
3994         if (err) {
3995                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3996                           dev->name);
3997                 goto hw_init_failed;
3998         }
3999
4000         if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
4001                 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
4002                 s2io_card_down(sp);
4003                 err = -ENODEV;
4004                 goto hw_init_failed;
4005         }
4006         s2io_start_all_tx_queue(sp);
4007         return 0;
4008
4009 hw_init_failed:
4010         if (sp->config.intr_type == MSI_X) {
4011                 if (sp->entries) {
4012                         kfree(sp->entries);
4013                         swstats->mem_freed += sp->num_entries *
4014                                 sizeof(struct msix_entry);
4015                 }
4016                 if (sp->s2io_entries) {
4017                         kfree(sp->s2io_entries);
4018                         swstats->mem_freed += sp->num_entries *
4019                                 sizeof(struct s2io_msix_entry);
4020                 }
4021         }
4022         return err;
4023 }
4024
4025 /**
4026  *  s2io_close -close entry point of the driver
4027  *  @dev : device pointer.
4028  *  Description:
4029  *  This is the stop entry point of the driver. It needs to undo exactly
4030  *  whatever was done by the open entry point,thus it's usually referred to
4031  *  as the close function.Among other things this function mainly stops the
4032  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4033  *  Return value:
4034  *  0 on success and an appropriate (-)ve integer as defined in errno.h
4035  *  file on failure.
4036  */
4037
4038 static int s2io_close(struct net_device *dev)
4039 {
4040         struct s2io_nic *sp = netdev_priv(dev);
4041         struct config_param *config = &sp->config;
4042         u64 tmp64;
4043         int offset;
4044
4045         /* Return if the device is already closed               *
4046          *  Can happen when s2io_card_up failed in change_mtu    *
4047          */
4048         if (!is_s2io_card_up(sp))
4049                 return 0;
4050
4051         s2io_stop_all_tx_queue(sp);
4052         /* delete all populated mac entries */
4053         for (offset = 1; offset < config->max_mc_addr; offset++) {
4054                 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4055                 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4056                         do_s2io_delete_unicast_mc(sp, tmp64);
4057         }
4058
4059         s2io_card_down(sp);
4060
4061         return 0;
4062 }
4063
4064 /**
4065  *  s2io_xmit - Tx entry point of te driver
4066  *  @skb : the socket buffer containing the Tx data.
4067  *  @dev : device pointer.
4068  *  Description :
4069  *  This function is the Tx entry point of the driver. S2IO NIC supports
4070  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
4071  *  NOTE: when device cant queue the pkt,just the trans_start variable will
4072  *  not be upadted.
4073  *  Return value:
4074  *  0 on success & 1 on failure.
4075  */
4076
4077 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4078 {
4079         struct s2io_nic *sp = netdev_priv(dev);
4080         u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4081         register u64 val64;
4082         struct TxD *txdp;
4083         struct TxFIFO_element __iomem *tx_fifo;
4084         unsigned long flags = 0;
4085         u16 vlan_tag = 0;
4086         struct fifo_info *fifo = NULL;
4087         int do_spin_lock = 1;
4088         int offload_type;
4089         int enable_per_list_interrupt = 0;
4090         struct config_param *config = &sp->config;
4091         struct mac_info *mac_control = &sp->mac_control;
4092         struct stat_block *stats = mac_control->stats_info;
4093         struct swStat *swstats = &stats->sw_stat;
4094
4095         DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4096
4097         if (unlikely(skb->len <= 0)) {
4098                 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
4099                 dev_kfree_skb_any(skb);
4100                 return NETDEV_TX_OK;
4101         }
4102
4103         if (!is_s2io_card_up(sp)) {
4104                 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4105                           dev->name);
4106                 dev_kfree_skb(skb);
4107                 return NETDEV_TX_OK;
4108         }
4109
4110         queue = 0;
4111         if (sp->vlgrp && vlan_tx_tag_present(skb))
4112                 vlan_tag = vlan_tx_tag_get(skb);
4113         if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4114                 if (skb->protocol == htons(ETH_P_IP)) {
4115                         struct iphdr *ip;
4116                         struct tcphdr *th;
4117                         ip = ip_hdr(skb);
4118
4119                         if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4120                                 th = (struct tcphdr *)(((unsigned char *)ip) +
4121                                                        ip->ihl*4);
4122
4123                                 if (ip->protocol == IPPROTO_TCP) {
4124                                         queue_len = sp->total_tcp_fifos;
4125                                         queue = (ntohs(th->source) +
4126                                                  ntohs(th->dest)) &
4127                                                 sp->fifo_selector[queue_len - 1];
4128                                         if (queue >= queue_len)
4129                                                 queue = queue_len - 1;
4130                                 } else if (ip->protocol == IPPROTO_UDP) {
4131                                         queue_len = sp->total_udp_fifos;
4132                                         queue = (ntohs(th->source) +
4133                                                  ntohs(th->dest)) &
4134                                                 sp->fifo_selector[queue_len - 1];
4135                                         if (queue >= queue_len)
4136                                                 queue = queue_len - 1;
4137                                         queue += sp->udp_fifo_idx;
4138                                         if (skb->len > 1024)
4139                                                 enable_per_list_interrupt = 1;
4140                                         do_spin_lock = 0;
4141                                 }
4142                         }
4143                 }
4144         } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4145                 /* get fifo number based on skb->priority value */
4146                 queue = config->fifo_mapping
4147                         [skb->priority & (MAX_TX_FIFOS - 1)];
4148         fifo = &mac_control->fifos[queue];
4149
4150         if (do_spin_lock)
4151                 spin_lock_irqsave(&fifo->tx_lock, flags);
4152         else {
4153                 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4154                         return NETDEV_TX_LOCKED;
4155         }
4156
4157         if (sp->config.multiq) {
4158                 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4159                         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4160                         return NETDEV_TX_BUSY;
4161                 }
4162         } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4163                 if (netif_queue_stopped(dev)) {
4164                         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4165                         return NETDEV_TX_BUSY;
4166                 }
4167         }
4168
4169         put_off = (u16)fifo->tx_curr_put_info.offset;
4170         get_off = (u16)fifo->tx_curr_get_info.offset;
4171         txdp = (struct TxD *)fifo->list_info[put_off].list_virt_addr;
4172
4173         queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4174         /* Avoid "put" pointer going beyond "get" pointer */
4175         if (txdp->Host_Control ||
4176             ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4177                 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4178                 s2io_stop_tx_queue(sp, fifo->fifo_no);
4179                 dev_kfree_skb(skb);
4180                 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4181                 return NETDEV_TX_OK;
4182         }
4183
4184         offload_type = s2io_offload_type(skb);
4185         if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4186                 txdp->Control_1 |= TXD_TCP_LSO_EN;
4187                 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4188         }
4189         if (skb->ip_summed == CHECKSUM_PARTIAL) {
4190                 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4191                                     TXD_TX_CKO_TCP_EN |
4192                                     TXD_TX_CKO_UDP_EN);
4193         }
4194         txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4195         txdp->Control_1 |= TXD_LIST_OWN_XENA;
4196         txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4197         if (enable_per_list_interrupt)
4198                 if (put_off & (queue_len >> 5))
4199                         txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4200         if (vlan_tag) {
4201                 txdp->Control_2 |= TXD_VLAN_ENABLE;
4202                 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4203         }
4204
4205         frg_len = skb->len - skb->data_len;
4206         if (offload_type == SKB_GSO_UDP) {
4207                 int ufo_size;
4208
4209                 ufo_size = s2io_udp_mss(skb);
4210                 ufo_size &= ~7;
4211                 txdp->Control_1 |= TXD_UFO_EN;
4212                 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4213                 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4214 #ifdef __BIG_ENDIAN
4215                 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4216                 fifo->ufo_in_band_v[put_off] =
4217                         (__force u64)skb_shinfo(skb)->ip6_frag_id;
4218 #else
4219                 fifo->ufo_in_band_v[put_off] =
4220                         (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
4221 #endif
4222                 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4223                 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4224                                                       fifo->ufo_in_band_v,
4225                                                       sizeof(u64),
4226                                                       PCI_DMA_TODEVICE);
4227                 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4228                         goto pci_map_failed;
4229                 txdp++;
4230         }
4231
4232         txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4233                                               frg_len, PCI_DMA_TODEVICE);
4234         if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4235                 goto pci_map_failed;
4236
4237         txdp->Host_Control = (unsigned long)skb;
4238         txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4239         if (offload_type == SKB_GSO_UDP)
4240                 txdp->Control_1 |= TXD_UFO_EN;
4241
4242         frg_cnt = skb_shinfo(skb)->nr_frags;
4243         /* For fragmented SKB. */
4244         for (i = 0; i < frg_cnt; i++) {
4245                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4246                 /* A '0' length fragment will be ignored */
4247                 if (!frag->size)
4248                         continue;
4249                 txdp++;
4250                 txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4251                                                          frag->page_offset,
4252                                                          frag->size,
4253                                                          PCI_DMA_TODEVICE);
4254                 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4255                 if (offload_type == SKB_GSO_UDP)
4256                         txdp->Control_1 |= TXD_UFO_EN;
4257         }
4258         txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4259
4260         if (offload_type == SKB_GSO_UDP)
4261                 frg_cnt++; /* as Txd0 was used for inband header */
4262
4263         tx_fifo = mac_control->tx_FIFO_start[queue];
4264         val64 = fifo->list_info[put_off].list_phy_addr;
4265         writeq(val64, &tx_fifo->TxDL_Pointer);
4266
4267         val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4268                  TX_FIFO_LAST_LIST);
4269         if (offload_type)
4270                 val64 |= TX_FIFO_SPECIAL_FUNC;
4271
4272         writeq(val64, &tx_fifo->List_Control);
4273
4274         mmiowb();
4275
4276         put_off++;
4277         if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4278                 put_off = 0;
4279         fifo->tx_curr_put_info.offset = put_off;
4280
4281         /* Avoid "put" pointer going beyond "get" pointer */
4282         if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4283                 swstats->fifo_full_cnt++;
4284                 DBG_PRINT(TX_DBG,
4285                           "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4286                           put_off, get_off);
4287                 s2io_stop_tx_queue(sp, fifo->fifo_no);
4288         }
4289         swstats->mem_allocated += skb->truesize;
4290         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4291
4292         if (sp->config.intr_type == MSI_X)
4293                 tx_intr_handler(fifo);
4294
4295         return NETDEV_TX_OK;
4296
4297 pci_map_failed:
4298         swstats->pci_map_fail_cnt++;
4299         s2io_stop_tx_queue(sp, fifo->fifo_no);
4300         swstats->mem_freed += skb->truesize;
4301         dev_kfree_skb(skb);
4302         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4303         return NETDEV_TX_OK;
4304 }
4305
4306 static void
4307 s2io_alarm_handle(unsigned long data)
4308 {
4309         struct s2io_nic *sp = (struct s2io_nic *)data;
4310         struct net_device *dev = sp->dev;
4311
4312         s2io_handle_errors(dev);
4313         mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4314 }
4315
4316 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4317 {
4318         struct ring_info *ring = (struct ring_info *)dev_id;
4319         struct s2io_nic *sp = ring->nic;
4320         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4321
4322         if (unlikely(!is_s2io_card_up(sp)))
4323                 return IRQ_HANDLED;
4324
4325         if (sp->config.napi) {
4326                 u8 __iomem *addr = NULL;
4327                 u8 val8 = 0;
4328
4329                 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4330                 addr += (7 - ring->ring_no);
4331                 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4332                 writeb(val8, addr);
4333                 val8 = readb(addr);
4334                 napi_schedule(&ring->napi);
4335         } else {
4336                 rx_intr_handler(ring, 0);
4337                 s2io_chk_rx_buffers(sp, ring);
4338         }
4339
4340         return IRQ_HANDLED;
4341 }
4342
4343 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4344 {
4345         int i;
4346         struct fifo_info *fifos = (struct fifo_info *)dev_id;
4347         struct s2io_nic *sp = fifos->nic;
4348         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4349         struct config_param *config  = &sp->config;
4350         u64 reason;
4351
4352         if (unlikely(!is_s2io_card_up(sp)))
4353                 return IRQ_NONE;
4354
4355         reason = readq(&bar0->general_int_status);
4356         if (unlikely(reason == S2IO_MINUS_ONE))
4357                 /* Nothing much can be done. Get out */
4358                 return IRQ_HANDLED;
4359
4360         if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4361                 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4362
4363                 if (reason & GEN_INTR_TXPIC)
4364                         s2io_txpic_intr_handle(sp);
4365
4366                 if (reason & GEN_INTR_TXTRAFFIC)
4367                         writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4368
4369                 for (i = 0; i < config->tx_fifo_num; i++)
4370                         tx_intr_handler(&fifos[i]);
4371
4372                 writeq(sp->general_int_mask, &bar0->general_int_mask);
4373                 readl(&bar0->general_int_status);
4374                 return IRQ_HANDLED;
4375         }
4376         /* The interrupt was not raised by us */
4377         return IRQ_NONE;
4378 }
4379
4380 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4381 {
4382         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4383         u64 val64;
4384
4385         val64 = readq(&bar0->pic_int_status);
4386         if (val64 & PIC_INT_GPIO) {
4387                 val64 = readq(&bar0->gpio_int_reg);
4388                 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4389                     (val64 & GPIO_INT_REG_LINK_UP)) {
4390                         /*
4391                          * This is unstable state so clear both up/down
4392                          * interrupt and adapter to re-evaluate the link state.
4393                          */
4394                         val64 |= GPIO_INT_REG_LINK_DOWN;
4395                         val64 |= GPIO_INT_REG_LINK_UP;
4396                         writeq(val64, &bar0->gpio_int_reg);
4397                         val64 = readq(&bar0->gpio_int_mask);
4398                         val64 &= ~(GPIO_INT_MASK_LINK_UP |
4399                                    GPIO_INT_MASK_LINK_DOWN);
4400                         writeq(val64, &bar0->gpio_int_mask);
4401                 } else if (val64 & GPIO_INT_REG_LINK_UP) {
4402                         val64 = readq(&bar0->adapter_status);
4403                         /* Enable Adapter */
4404                         val64 = readq(&bar0->adapter_control);
4405                         val64 |= ADAPTER_CNTL_EN;
4406                         writeq(val64, &bar0->adapter_control);
4407                         val64 |= ADAPTER_LED_ON;
4408                         writeq(val64, &bar0->adapter_control);
4409                         if (!sp->device_enabled_once)
4410                                 sp->device_enabled_once = 1;
4411
4412                         s2io_link(sp, LINK_UP);
4413                         /*
4414                          * unmask link down interrupt and mask link-up
4415                          * intr
4416                          */
4417                         val64 = readq(&bar0->gpio_int_mask);
4418                         val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4419                         val64 |= GPIO_INT_MASK_LINK_UP;
4420                         writeq(val64, &bar0->gpio_int_mask);
4421
4422                 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4423                         val64 = readq(&bar0->adapter_status);
4424                         s2io_link(sp, LINK_DOWN);
4425                         /* Link is down so unmaks link up interrupt */
4426                         val64 = readq(&bar0->gpio_int_mask);
4427                         val64 &= ~GPIO_INT_MASK_LINK_UP;
4428                         val64 |= GPIO_INT_MASK_LINK_DOWN;
4429                         writeq(val64, &bar0->gpio_int_mask);
4430
4431                         /* turn off LED */
4432                         val64 = readq(&bar0->adapter_control);
4433                         val64 = val64 & (~ADAPTER_LED_ON);
4434                         writeq(val64, &bar0->adapter_control);
4435                 }
4436         }
4437         val64 = readq(&bar0->gpio_int_mask);
4438 }
4439
4440 /**
4441  *  do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4442  *  @value: alarm bits
4443  *  @addr: address value
4444  *  @cnt: counter variable
4445  *  Description: Check for alarm and increment the counter
4446  *  Return Value:
4447  *  1 - if alarm bit set
4448  *  0 - if alarm bit is not set
4449  */
4450 static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4451                                  unsigned long long *cnt)
4452 {
4453         u64 val64;
4454         val64 = readq(addr);
4455         if (val64 & value) {
4456                 writeq(val64, addr);
4457                 (*cnt)++;
4458                 return 1;
4459         }
4460         return 0;
4461
4462 }
4463
4464 /**
4465  *  s2io_handle_errors - Xframe error indication handler
4466  *  @nic: device private variable
4467  *  Description: Handle alarms such as loss of link, single or
4468  *  double ECC errors, critical and serious errors.
4469  *  Return Value:
4470  *  NONE
4471  */
4472 static void s2io_handle_errors(void *dev_id)
4473 {
4474         struct net_device *dev = (struct net_device *)dev_id;
4475         struct s2io_nic *sp = netdev_priv(dev);
4476         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4477         u64 temp64 = 0, val64 = 0;
4478         int i = 0;
4479
4480         struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4481         struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4482
4483         if (!is_s2io_card_up(sp))
4484                 return;
4485
4486         if (pci_channel_offline(sp->pdev))
4487                 return;
4488
4489         memset(&sw_stat->ring_full_cnt, 0,
4490                sizeof(sw_stat->ring_full_cnt));
4491
4492         /* Handling the XPAK counters update */
4493         if (stats->xpak_timer_count < 72000) {
4494                 /* waiting for an hour */
4495                 stats->xpak_timer_count++;
4496         } else {
4497                 s2io_updt_xpak_counter(dev);
4498                 /* reset the count to zero */
4499                 stats->xpak_timer_count = 0;
4500         }
4501
4502         /* Handling link status change error Intr */
4503         if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4504                 val64 = readq(&bar0->mac_rmac_err_reg);
4505                 writeq(val64, &bar0->mac_rmac_err_reg);
4506                 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4507                         schedule_work(&sp->set_link_task);
4508         }
4509
4510         /* In case of a serious error, the device will be Reset. */
4511         if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4512                                   &sw_stat->serious_err_cnt))
4513                 goto reset;
4514
4515         /* Check for data parity error */
4516         if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4517                                   &sw_stat->parity_err_cnt))
4518                 goto reset;
4519
4520         /* Check for ring full counter */
4521         if (sp->device_type == XFRAME_II_DEVICE) {
4522                 val64 = readq(&bar0->ring_bump_counter1);
4523                 for (i = 0; i < 4; i++) {
4524                         temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4525                         temp64 >>= 64 - ((i+1)*16);
4526                         sw_stat->ring_full_cnt[i] += temp64;
4527                 }
4528
4529                 val64 = readq(&bar0->ring_bump_counter2);
4530                 for (i = 0; i < 4; i++) {
4531                         temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4532                         temp64 >>= 64 - ((i+1)*16);
4533                         sw_stat->ring_full_cnt[i+4] += temp64;
4534                 }
4535         }
4536
4537         val64 = readq(&bar0->txdma_int_status);
4538         /*check for pfc_err*/
4539         if (val64 & TXDMA_PFC_INT) {
4540                 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4541                                           PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4542                                           PFC_PCIX_ERR,
4543                                           &bar0->pfc_err_reg,
4544                                           &sw_stat->pfc_err_cnt))
4545                         goto reset;
4546                 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4547                                       &bar0->pfc_err_reg,
4548                                       &sw_stat->pfc_err_cnt);
4549         }
4550
4551         /*check for tda_err*/
4552         if (val64 & TXDMA_TDA_INT) {
4553                 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4554                                           TDA_SM0_ERR_ALARM |
4555                                           TDA_SM1_ERR_ALARM,
4556                                           &bar0->tda_err_reg,
4557                                           &sw_stat->tda_err_cnt))
4558                         goto reset;
4559                 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4560                                       &bar0->tda_err_reg,
4561                                       &sw_stat->tda_err_cnt);
4562         }
4563         /*check for pcc_err*/
4564         if (val64 & TXDMA_PCC_INT) {
4565                 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4566                                           PCC_N_SERR | PCC_6_COF_OV_ERR |
4567                                           PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4568                                           PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4569                                           PCC_TXB_ECC_DB_ERR,
4570                                           &bar0->pcc_err_reg,
4571                                           &sw_stat->pcc_err_cnt))
4572                         goto reset;
4573                 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4574                                       &bar0->pcc_err_reg,
4575                                       &sw_stat->pcc_err_cnt);
4576         }
4577
4578         /*check for tti_err*/
4579         if (val64 & TXDMA_TTI_INT) {
4580                 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4581                                           &bar0->tti_err_reg,
4582                                           &sw_stat->tti_err_cnt))
4583                         goto reset;
4584                 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4585                                       &bar0->tti_err_reg,
4586                                       &sw_stat->tti_err_cnt);
4587         }
4588
4589         /*check for lso_err*/
4590         if (val64 & TXDMA_LSO_INT) {
4591                 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4592                                           LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4593                                           &bar0->lso_err_reg,
4594                                           &sw_stat->lso_err_cnt))
4595                         goto reset;
4596                 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4597                                       &bar0->lso_err_reg,
4598                                       &sw_stat->lso_err_cnt);
4599         }
4600
4601         /*check for tpa_err*/
4602         if (val64 & TXDMA_TPA_INT) {
4603                 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4604                                           &bar0->tpa_err_reg,
4605                                           &sw_stat->tpa_err_cnt))
4606                         goto reset;
4607                 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4608                                       &bar0->tpa_err_reg,
4609                                       &sw_stat->tpa_err_cnt);
4610         }
4611
4612         /*check for sm_err*/
4613         if (val64 & TXDMA_SM_INT) {
4614                 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4615                                           &bar0->sm_err_reg,
4616                                           &sw_stat->sm_err_cnt))
4617                         goto reset;
4618         }
4619
4620         val64 = readq(&bar0->mac_int_status);
4621         if (val64 & MAC_INT_STATUS_TMAC_INT) {
4622                 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4623                                           &bar0->mac_tmac_err_reg,
4624                                           &sw_stat->mac_tmac_err_cnt))
4625                         goto reset;
4626                 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4627                                       TMAC_DESC_ECC_SG_ERR |
4628                                       TMAC_DESC_ECC_DB_ERR,
4629                                       &bar0->mac_tmac_err_reg,
4630                                       &sw_stat->mac_tmac_err_cnt);
4631         }
4632
4633         val64 = readq(&bar0->xgxs_int_status);
4634         if (val64 & XGXS_INT_STATUS_TXGXS) {
4635                 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4636                                           &bar0->xgxs_txgxs_err_reg,
4637                                           &sw_stat->xgxs_txgxs_err_cnt))
4638                         goto reset;
4639                 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4640                                       &bar0->xgxs_txgxs_err_reg,
4641                                       &sw_stat->xgxs_txgxs_err_cnt);
4642         }
4643
4644         val64 = readq(&bar0->rxdma_int_status);
4645         if (val64 & RXDMA_INT_RC_INT_M) {
4646                 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4647                                           RC_FTC_ECC_DB_ERR |
4648                                           RC_PRCn_SM_ERR_ALARM |
4649                                           RC_FTC_SM_ERR_ALARM,
4650                                           &bar0->rc_err_reg,
4651                                           &sw_stat->rc_err_cnt))
4652                         goto reset;
4653                 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4654                                       RC_FTC_ECC_SG_ERR |
4655                                       RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4656                                       &sw_stat->rc_err_cnt);
4657                 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4658                                           PRC_PCI_AB_WR_Rn |
4659                                           PRC_PCI_AB_F_WR_Rn,
4660                                           &bar0->prc_pcix_err_reg,
4661                                           &sw_stat->prc_pcix_err_cnt))
4662                         goto reset;
4663                 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4664                                       PRC_PCI_DP_WR_Rn |
4665                                       PRC_PCI_DP_F_WR_Rn,
4666                                       &bar0->prc_pcix_err_reg,
4667                                       &sw_stat->prc_pcix_err_cnt);
4668         }
4669
4670         if (val64 & RXDMA_INT_RPA_INT_M) {
4671                 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4672                                           &bar0->rpa_err_reg,
4673                                           &sw_stat->rpa_err_cnt))
4674                         goto reset;
4675                 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4676                                       &bar0->rpa_err_reg,
4677                                       &sw_stat->rpa_err_cnt);
4678         }
4679
4680         if (val64 & RXDMA_INT_RDA_INT_M) {
4681                 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4682                                           RDA_FRM_ECC_DB_N_AERR |
4683                                           RDA_SM1_ERR_ALARM |
4684                                           RDA_SM0_ERR_ALARM |
4685                                           RDA_RXD_ECC_DB_SERR,
4686                                           &bar0->rda_err_reg,
4687                                           &sw_stat->rda_err_cnt))
4688                         goto reset;
4689                 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4690                                       RDA_FRM_ECC_SG_ERR |
4691                                       RDA_MISC_ERR |
4692                                       RDA_PCIX_ERR,
4693                                       &bar0->rda_err_reg,
4694                                       &sw_stat->rda_err_cnt);
4695         }
4696
4697         if (val64 & RXDMA_INT_RTI_INT_M) {
4698                 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4699                                           &bar0->rti_err_reg,
4700                                           &sw_stat->rti_err_cnt))
4701                         goto reset;
4702                 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4703                                       &bar0->rti_err_reg,
4704                                       &sw_stat->rti_err_cnt);
4705         }
4706
4707         val64 = readq(&bar0->mac_int_status);
4708         if (val64 & MAC_INT_STATUS_RMAC_INT) {
4709                 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4710                                           &bar0->mac_rmac_err_reg,
4711                                           &sw_stat->mac_rmac_err_cnt))
4712                         goto reset;
4713                 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4714                                       RMAC_SINGLE_ECC_ERR |
4715                                       RMAC_DOUBLE_ECC_ERR,
4716                                       &bar0->mac_rmac_err_reg,
4717                                       &sw_stat->mac_rmac_err_cnt);
4718         }
4719
4720         val64 = readq(&bar0->xgxs_int_status);
4721         if (val64 & XGXS_INT_STATUS_RXGXS) {
4722                 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4723                                           &bar0->xgxs_rxgxs_err_reg,
4724                                           &sw_stat->xgxs_rxgxs_err_cnt))
4725                         goto reset;
4726         }
4727
4728         val64 = readq(&bar0->mc_int_status);
4729         if (val64 & MC_INT_STATUS_MC_INT) {
4730                 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4731                                           &bar0->mc_err_reg,
4732                                           &sw_stat->mc_err_cnt))
4733                         goto reset;
4734
4735                 /* Handling Ecc errors */
4736                 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4737                         writeq(val64, &bar0->mc_err_reg);
4738                         if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4739                                 sw_stat->double_ecc_errs++;
4740                                 if (sp->device_type != XFRAME_II_DEVICE) {
4741                                         /*
4742                                          * Reset XframeI only if critical error
4743                                          */
4744                                         if (val64 &
4745                                             (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4746                                              MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4747                                                 goto reset;
4748                                 }
4749                         } else
4750                                 sw_stat->single_ecc_errs++;
4751                 }
4752         }
4753         return;
4754
4755 reset:
4756         s2io_stop_all_tx_queue(sp);
4757         schedule_work(&sp->rst_timer_task);
4758         sw_stat->soft_reset_cnt++;
4759         return;
4760 }
4761
4762 /**
4763  *  s2io_isr - ISR handler of the device .
4764  *  @irq: the irq of the device.
4765  *  @dev_id: a void pointer to the dev structure of the NIC.
4766  *  Description:  This function is the ISR handler of the device. It
4767  *  identifies the reason for the interrupt and calls the relevant
4768  *  service routines. As a contongency measure, this ISR allocates the
4769  *  recv buffers, if their numbers are below the panic value which is
4770  *  presently set to 25% of the original number of rcv buffers allocated.
4771  *  Return value:
4772  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
4773  *   IRQ_NONE: will be returned if interrupt is not from our device
4774  */
4775 static irqreturn_t s2io_isr(int irq, void *dev_id)
4776 {
4777         struct net_device *dev = (struct net_device *)dev_id;
4778         struct s2io_nic *sp = netdev_priv(dev);
4779         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4780         int i;
4781         u64 reason = 0;
4782         struct mac_info *mac_control;
4783         struct config_param *config;
4784
4785         /* Pretend we handled any irq's from a disconnected card */
4786         if (pci_channel_offline(sp->pdev))
4787                 return IRQ_NONE;
4788
4789         if (!is_s2io_card_up(sp))
4790                 return IRQ_NONE;
4791
4792         config = &sp->config;
4793         mac_control = &sp->mac_control;
4794
4795         /*
4796          * Identify the cause for interrupt and call the appropriate
4797          * interrupt handler. Causes for the interrupt could be;
4798          * 1. Rx of packet.
4799          * 2. Tx complete.
4800          * 3. Link down.
4801          */
4802         reason = readq(&bar0->general_int_status);
4803
4804         if (unlikely(reason == S2IO_MINUS_ONE))
4805                 return IRQ_HANDLED;     /* Nothing much can be done. Get out */
4806
4807         if (reason &
4808             (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
4809                 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4810
4811                 if (config->napi) {
4812                         if (reason & GEN_INTR_RXTRAFFIC) {
4813                                 napi_schedule(&sp->napi);
4814                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4815                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4816                                 readl(&bar0->rx_traffic_int);
4817                         }
4818                 } else {
4819                         /*
4820                          * rx_traffic_int reg is an R1 register, writing all 1's
4821                          * will ensure that the actual interrupt causing bit
4822                          * get's cleared and hence a read can be avoided.
4823                          */
4824                         if (reason & GEN_INTR_RXTRAFFIC)
4825                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4826
4827                         for (i = 0; i < config->rx_ring_num; i++) {
4828                                 struct ring_info *ring = &mac_control->rings[i];
4829
4830                                 rx_intr_handler(ring, 0);
4831                         }
4832                 }
4833
4834                 /*
4835                  * tx_traffic_int reg is an R1 register, writing all 1's
4836                  * will ensure that the actual interrupt causing bit get's
4837                  * cleared and hence a read can be avoided.
4838                  */
4839                 if (reason & GEN_INTR_TXTRAFFIC)
4840                         writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4841
4842                 for (i = 0; i < config->tx_fifo_num; i++)
4843                         tx_intr_handler(&mac_control->fifos[i]);
4844
4845                 if (reason & GEN_INTR_TXPIC)
4846                         s2io_txpic_intr_handle(sp);
4847
4848                 /*
4849                  * Reallocate the buffers from the interrupt handler itself.
4850                  */
4851                 if (!config->napi) {
4852                         for (i = 0; i < config->rx_ring_num; i++) {
4853                                 struct ring_info *ring = &mac_control->rings[i];
4854
4855                                 s2io_chk_rx_buffers(sp, ring);
4856                         }
4857                 }
4858                 writeq(sp->general_int_mask, &bar0->general_int_mask);
4859                 readl(&bar0->general_int_status);
4860
4861                 return IRQ_HANDLED;
4862
4863         } else if (!reason) {
4864                 /* The interrupt was not raised by us */
4865                 return IRQ_NONE;
4866         }
4867
4868         return IRQ_HANDLED;
4869 }
4870
4871 /**
4872  * s2io_updt_stats -
4873  */
4874 static void s2io_updt_stats(struct s2io_nic *sp)
4875 {
4876         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4877         u64 val64;
4878         int cnt = 0;
4879
4880         if (is_s2io_card_up(sp)) {
4881                 /* Apprx 30us on a 133 MHz bus */
4882                 val64 = SET_UPDT_CLICKS(10) |
4883                         STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4884                 writeq(val64, &bar0->stat_cfg);
4885                 do {
4886                         udelay(100);
4887                         val64 = readq(&bar0->stat_cfg);
4888                         if (!(val64 & s2BIT(0)))
4889                                 break;
4890                         cnt++;
4891                         if (cnt == 5)
4892                                 break; /* Updt failed */
4893                 } while (1);
4894         }
4895 }
4896
4897 /**
4898  *  s2io_get_stats - Updates the device statistics structure.
4899  *  @dev : pointer to the device structure.
4900  *  Description:
4901  *  This function updates the device statistics structure in the s2io_nic
4902  *  structure and returns a pointer to the same.
4903  *  Return value:
4904  *  pointer to the updated net_device_stats structure.
4905  */
4906
4907 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4908 {
4909         struct s2io_nic *sp = netdev_priv(dev);
4910         struct config_param *config = &sp->config;
4911         struct mac_info *mac_control = &sp->mac_control;
4912         struct stat_block *stats = mac_control->stats_info;
4913         int i;
4914
4915         /* Configure Stats for immediate updt */
4916         s2io_updt_stats(sp);
4917
4918         /* Using sp->stats as a staging area, because reset (due to mtu
4919            change, for example) will clear some hardware counters */
4920         dev->stats.tx_packets += le32_to_cpu(stats->tmac_frms) -
4921                 sp->stats.tx_packets;
4922         sp->stats.tx_packets = le32_to_cpu(stats->tmac_frms);
4923
4924         dev->stats.tx_errors += le32_to_cpu(stats->tmac_any_err_frms) -
4925                 sp->stats.tx_errors;
4926         sp->stats.tx_errors = le32_to_cpu(stats->tmac_any_err_frms);
4927
4928         dev->stats.rx_errors += le64_to_cpu(stats->rmac_drop_frms) -
4929                 sp->stats.rx_errors;
4930         sp->stats.rx_errors = le64_to_cpu(stats->rmac_drop_frms);
4931
4932         dev->stats.multicast = le32_to_cpu(stats->rmac_vld_mcst_frms) -
4933                 sp->stats.multicast;
4934         sp->stats.multicast = le32_to_cpu(stats->rmac_vld_mcst_frms);
4935
4936         dev->stats.rx_length_errors = le64_to_cpu(stats->rmac_long_frms) -
4937                 sp->stats.rx_length_errors;
4938         sp->stats.rx_length_errors = le64_to_cpu(stats->rmac_long_frms);
4939
4940         /* collect per-ring rx_packets and rx_bytes */
4941         dev->stats.rx_packets = dev->stats.rx_bytes = 0;
4942         for (i = 0; i < config->rx_ring_num; i++) {
4943                 struct ring_info *ring = &mac_control->rings[i];
4944
4945                 dev->stats.rx_packets += ring->rx_packets;
4946                 dev->stats.rx_bytes += ring->rx_bytes;
4947         }
4948
4949         return &dev->stats;
4950 }
4951
4952 /**
4953  *  s2io_set_multicast - entry point for multicast address enable/disable.
4954  *  @dev : pointer to the device structure
4955  *  Description:
4956  *  This function is a driver entry point which gets called by the kernel
4957  *  whenever multicast addresses must be enabled/disabled. This also gets
4958  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
4959  *  determine, if multicast address must be enabled or if promiscuous mode
4960  *  is to be disabled etc.
4961  *  Return value:
4962  *  void.
4963  */
4964
4965 static void s2io_set_multicast(struct net_device *dev)
4966 {
4967         int i, j, prev_cnt;
4968         struct dev_mc_list *mclist;
4969         struct s2io_nic *sp = netdev_priv(dev);
4970         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4971         u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4972                 0xfeffffffffffULL;
4973         u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
4974         void __iomem *add;
4975         struct config_param *config = &sp->config;
4976
4977         if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4978                 /*  Enable all Multicast addresses */
4979                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4980                        &bar0->rmac_addr_data0_mem);
4981                 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4982                        &bar0->rmac_addr_data1_mem);
4983                 val64 = RMAC_ADDR_CMD_MEM_WE |
4984                         RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4985                         RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
4986                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4987                 /* Wait till command completes */
4988                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4989                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4990                                       S2IO_BIT_RESET);
4991
4992                 sp->m_cast_flg = 1;
4993                 sp->all_multi_pos = config->max_mc_addr - 1;
4994         } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4995                 /*  Disable all Multicast addresses */
4996                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4997                        &bar0->rmac_addr_data0_mem);
4998                 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4999                        &bar0->rmac_addr_data1_mem);
5000                 val64 = RMAC_ADDR_CMD_MEM_WE |
5001                         RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5002                         RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
5003                 writeq(val64, &bar0->rmac_addr_cmd_mem);
5004                 /* Wait till command completes */
5005                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5006                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5007                                       S2IO_BIT_RESET);
5008
5009                 sp->m_cast_flg = 0;
5010                 sp->all_multi_pos = 0;
5011         }
5012
5013         if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5014                 /*  Put the NIC into promiscuous mode */
5015                 add = &bar0->mac_cfg;
5016                 val64 = readq(&bar0->mac_cfg);
5017                 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5018
5019                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5020                 writel((u32)val64, add);
5021                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5022                 writel((u32) (val64 >> 32), (add + 4));
5023
5024                 if (vlan_tag_strip != 1) {
5025                         val64 = readq(&bar0->rx_pa_cfg);
5026                         val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5027                         writeq(val64, &bar0->rx_pa_cfg);
5028                         sp->vlan_strip_flag = 0;
5029                 }
5030
5031                 val64 = readq(&bar0->mac_cfg);
5032                 sp->promisc_flg = 1;
5033                 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
5034                           dev->name);
5035         } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5036                 /*  Remove the NIC from promiscuous mode */
5037                 add = &bar0->mac_cfg;
5038                 val64 = readq(&bar0->mac_cfg);
5039                 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5040
5041                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5042                 writel((u32)val64, add);
5043                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5044                 writel((u32) (val64 >> 32), (add + 4));
5045
5046                 if (vlan_tag_strip != 0) {
5047                         val64 = readq(&bar0->rx_pa_cfg);
5048                         val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5049                         writeq(val64, &bar0->rx_pa_cfg);
5050                         sp->vlan_strip_flag = 1;
5051                 }
5052
5053                 val64 = readq(&bar0->mac_cfg);
5054                 sp->promisc_flg = 0;
5055                 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
5056                           dev->name);
5057         }
5058
5059         /*  Update individual M_CAST address list */
5060         if ((!sp->m_cast_flg) && dev->mc_count) {
5061                 if (dev->mc_count >
5062                     (config->max_mc_addr - config->max_mac_addr)) {
5063                         DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
5064                                   dev->name);
5065                         DBG_PRINT(ERR_DBG, "can be added, please enable ");
5066                         DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
5067                         return;
5068                 }
5069
5070                 prev_cnt = sp->mc_addr_count;
5071                 sp->mc_addr_count = dev->mc_count;
5072
5073                 /* Clear out the previous list of Mc in the H/W. */
5074                 for (i = 0; i < prev_cnt; i++) {
5075                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5076                                &bar0->rmac_addr_data0_mem);
5077                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5078                                &bar0->rmac_addr_data1_mem);
5079                         val64 = RMAC_ADDR_CMD_MEM_WE |
5080                                 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5081                                 RMAC_ADDR_CMD_MEM_OFFSET
5082                                 (config->mc_start_offset + i);
5083                         writeq(val64, &bar0->rmac_addr_cmd_mem);
5084
5085                         /* Wait for command completes */
5086                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5087                                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5088                                                   S2IO_BIT_RESET)) {
5089                                 DBG_PRINT(ERR_DBG, "%s: Adding ", dev->name);
5090                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5091                                 return;
5092                         }
5093                 }
5094
5095                 /* Create the new Rx filter list and update the same in H/W. */
5096                 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
5097                      i++, mclist = mclist->next) {
5098                         memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
5099                                ETH_ALEN);
5100                         mac_addr = 0;
5101                         for (j = 0; j < ETH_ALEN; j++) {
5102                                 mac_addr |= mclist->dmi_addr[j];
5103                                 mac_addr <<= 8;
5104                         }
5105                         mac_addr >>= 8;
5106                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5107                                &bar0->rmac_addr_data0_mem);
5108                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5109                                &bar0->rmac_addr_data1_mem);
5110                         val64 = RMAC_ADDR_CMD_MEM_WE |
5111                                 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5112                                 RMAC_ADDR_CMD_MEM_OFFSET
5113                                 (i + config->mc_start_offset);
5114                         writeq(val64, &bar0->rmac_addr_cmd_mem);
5115
5116                         /* Wait for command completes */
5117                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5118                                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5119                                                   S2IO_BIT_RESET)) {
5120                                 DBG_PRINT(ERR_DBG, "%s: Adding ", dev->name);
5121                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5122                                 return;
5123                         }
5124                 }
5125         }
5126 }
5127
5128 /* read from CAM unicast & multicast addresses and store it in
5129  * def_mac_addr structure
5130  */
5131 static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5132 {
5133         int offset;
5134         u64 mac_addr = 0x0;
5135         struct config_param *config = &sp->config;
5136
5137         /* store unicast & multicast mac addresses */
5138         for (offset = 0; offset < config->max_mc_addr; offset++) {
5139                 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5140                 /* if read fails disable the entry */
5141                 if (mac_addr == FAILURE)
5142                         mac_addr = S2IO_DISABLE_MAC_ENTRY;
5143                 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5144         }
5145 }
5146
5147 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5148 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5149 {
5150         int offset;
5151         struct config_param *config = &sp->config;
5152         /* restore unicast mac address */
5153         for (offset = 0; offset < config->max_mac_addr; offset++)
5154                 do_s2io_prog_unicast(sp->dev,
5155                                      sp->def_mac_addr[offset].mac_addr);
5156
5157         /* restore multicast mac address */
5158         for (offset = config->mc_start_offset;
5159              offset < config->max_mc_addr; offset++)
5160                 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5161 }
5162
5163 /* add a multicast MAC address to CAM */
5164 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5165 {
5166         int i;
5167         u64 mac_addr = 0;
5168         struct config_param *config = &sp->config;
5169
5170         for (i = 0; i < ETH_ALEN; i++) {
5171                 mac_addr <<= 8;
5172                 mac_addr |= addr[i];
5173         }
5174         if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5175                 return SUCCESS;
5176
5177         /* check if the multicast mac already preset in CAM */
5178         for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5179                 u64 tmp64;
5180                 tmp64 = do_s2io_read_unicast_mc(sp, i);
5181                 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5182                         break;
5183
5184                 if (tmp64 == mac_addr)
5185                         return SUCCESS;
5186         }
5187         if (i == config->max_mc_addr) {
5188                 DBG_PRINT(ERR_DBG,
5189                           "CAM full no space left for multicast MAC\n");
5190                 return FAILURE;
5191         }
5192         /* Update the internal structure with this new mac address */
5193         do_s2io_copy_mac_addr(sp, i, mac_addr);
5194
5195         return do_s2io_add_mac(sp, mac_addr, i);
5196 }
5197
5198 /* add MAC address to CAM */
5199 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5200 {
5201         u64 val64;
5202         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5203
5204         writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5205                &bar0->rmac_addr_data0_mem);
5206
5207         val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5208                 RMAC_ADDR_CMD_MEM_OFFSET(off);
5209         writeq(val64, &bar0->rmac_addr_cmd_mem);
5210
5211         /* Wait till command completes */
5212         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5213                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5214                                   S2IO_BIT_RESET)) {
5215                 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5216                 return FAILURE;
5217         }
5218         return SUCCESS;
5219 }
5220 /* deletes a specified unicast/multicast mac entry from CAM */
5221 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5222 {
5223         int offset;
5224         u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5225         struct config_param *config = &sp->config;
5226
5227         for (offset = 1;
5228              offset < config->max_mc_addr; offset++) {
5229                 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5230                 if (tmp64 == addr) {
5231                         /* disable the entry by writing  0xffffffffffffULL */
5232                         if (do_s2io_add_mac(sp, dis_addr, offset) ==  FAILURE)
5233                                 return FAILURE;
5234                         /* store the new mac list from CAM */
5235                         do_s2io_store_unicast_mc(sp);
5236                         return SUCCESS;
5237                 }
5238         }
5239         DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5240                   (unsigned long long)addr);
5241         return FAILURE;
5242 }
5243
5244 /* read mac entries from CAM */
5245 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5246 {
5247         u64 tmp64 = 0xffffffffffff0000ULL, val64;
5248         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5249
5250         /* read mac addr */
5251         val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5252                 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5253         writeq(val64, &bar0->rmac_addr_cmd_mem);
5254
5255         /* Wait till command completes */
5256         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5257                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5258                                   S2IO_BIT_RESET)) {
5259                 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5260                 return FAILURE;
5261         }
5262         tmp64 = readq(&bar0->rmac_addr_data0_mem);
5263
5264         return tmp64 >> 16;
5265 }
5266
5267 /**
5268  * s2io_set_mac_addr driver entry point
5269  */
5270
5271 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5272 {
5273         struct sockaddr *addr = p;
5274
5275         if (!is_valid_ether_addr(addr->sa_data))
5276                 return -EINVAL;
5277
5278         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5279
5280         /* store the MAC address in CAM */
5281         return do_s2io_prog_unicast(dev, dev->dev_addr);
5282 }
5283 /**
5284  *  do_s2io_prog_unicast - Programs the Xframe mac address
5285  *  @dev : pointer to the device structure.
5286  *  @addr: a uchar pointer to the new mac address which is to be set.
5287  *  Description : This procedure will program the Xframe to receive
5288  *  frames with new Mac Address
5289  *  Return value: SUCCESS on success and an appropriate (-)ve integer
5290  *  as defined in errno.h file on failure.
5291  */
5292
5293 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5294 {
5295         struct s2io_nic *sp = netdev_priv(dev);
5296         register u64 mac_addr = 0, perm_addr = 0;
5297         int i;
5298         u64 tmp64;
5299         struct config_param *config = &sp->config;
5300
5301         /*
5302          * Set the new MAC address as the new unicast filter and reflect this
5303          * change on the device address registered with the OS. It will be
5304          * at offset 0.
5305          */
5306         for (i = 0; i < ETH_ALEN; i++) {
5307                 mac_addr <<= 8;
5308                 mac_addr |= addr[i];
5309                 perm_addr <<= 8;
5310                 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5311         }
5312
5313         /* check if the dev_addr is different than perm_addr */
5314         if (mac_addr == perm_addr)
5315                 return SUCCESS;
5316
5317         /* check if the mac already preset in CAM */
5318         for (i = 1; i < config->max_mac_addr; i++) {
5319                 tmp64 = do_s2io_read_unicast_mc(sp, i);
5320                 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5321                         break;
5322
5323                 if (tmp64 == mac_addr) {
5324                         DBG_PRINT(INFO_DBG,
5325                                   "MAC addr:0x%llx already present in CAM\n",
5326                                   (unsigned long long)mac_addr);
5327                         return SUCCESS;
5328                 }
5329         }
5330         if (i == config->max_mac_addr) {
5331                 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5332                 return FAILURE;
5333         }
5334         /* Update the internal structure with this new mac address */
5335         do_s2io_copy_mac_addr(sp, i, mac_addr);
5336
5337         return do_s2io_add_mac(sp, mac_addr, i);
5338 }
5339
5340 /**
5341  * s2io_ethtool_sset - Sets different link parameters.
5342  * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
5343  * @info: pointer to the structure with parameters given by ethtool to set
5344  * link information.
5345  * Description:
5346  * The function sets different link parameters provided by the user onto
5347  * the NIC.
5348  * Return value:
5349  * 0 on success.
5350  */
5351
5352 static int s2io_ethtool_sset(struct net_device *dev,
5353                              struct ethtool_cmd *info)
5354 {
5355         struct s2io_nic *sp = netdev_priv(dev);
5356         if ((info->autoneg == AUTONEG_ENABLE) ||
5357             (info->speed != SPEED_10000) ||
5358             (info->duplex != DUPLEX_FULL))
5359                 return -EINVAL;
5360         else {
5361                 s2io_close(sp->dev);
5362                 s2io_open(sp->dev);
5363         }
5364
5365         return 0;
5366 }
5367
5368 /**
5369  * s2io_ethtol_gset - Return link specific information.
5370  * @sp : private member of the device structure, pointer to the
5371  *      s2io_nic structure.
5372  * @info : pointer to the structure with parameters given by ethtool
5373  * to return link information.
5374  * Description:
5375  * Returns link specific information like speed, duplex etc.. to ethtool.
5376  * Return value :
5377  * return 0 on success.
5378  */
5379
5380 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5381 {
5382         struct s2io_nic *sp = netdev_priv(dev);
5383         info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5384         info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5385         info->port = PORT_FIBRE;
5386
5387         /* info->transceiver */
5388         info->transceiver = XCVR_EXTERNAL;
5389
5390         if (netif_carrier_ok(sp->dev)) {
5391                 info->speed = 10000;
5392                 info->duplex = DUPLEX_FULL;
5393         } else {
5394                 info->speed = -1;
5395                 info->duplex = -1;
5396         }
5397
5398         info->autoneg = AUTONEG_DISABLE;
5399         return 0;
5400 }
5401
5402 /**
5403  * s2io_ethtool_gdrvinfo - Returns driver specific information.
5404  * @sp : private member of the device structure, which is a pointer to the
5405  * s2io_nic structure.
5406  * @info : pointer to the structure with parameters given by ethtool to
5407  * return driver information.
5408  * Description:
5409  * Returns driver specefic information like name, version etc.. to ethtool.
5410  * Return value:
5411  *  void
5412  */
5413
5414 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5415                                   struct ethtool_drvinfo *info)
5416 {
5417         struct s2io_nic *sp = netdev_priv(dev);
5418
5419         strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5420         strncpy(info->version, s2io_driver_version, sizeof(info->version));
5421         strncpy(info->fw_version, "", sizeof(info->fw_version));
5422         strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5423         info->regdump_len = XENA_REG_SPACE;
5424         info->eedump_len = XENA_EEPROM_SPACE;
5425 }
5426
5427 /**
5428  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5429  *  @sp: private member of the device structure, which is a pointer to the
5430  *  s2io_nic structure.
5431  *  @regs : pointer to the structure with parameters given by ethtool for
5432  *  dumping the registers.
5433  *  @reg_space: The input argumnet into which all the registers are dumped.
5434  *  Description:
5435  *  Dumps the entire register space of xFrame NIC into the user given
5436  *  buffer area.
5437  * Return value :
5438  * void .
5439  */
5440
5441 static void s2io_ethtool_gregs(struct net_device *dev,
5442                                struct ethtool_regs *regs, void *space)
5443 {
5444         int i;
5445         u64 reg;
5446         u8 *reg_space = (u8 *)space;
5447         struct s2io_nic *sp = netdev_priv(dev);
5448
5449         regs->len = XENA_REG_SPACE;
5450         regs->version = sp->pdev->subsystem_device;
5451
5452         for (i = 0; i < regs->len; i += 8) {
5453                 reg = readq(sp->bar0 + i);
5454                 memcpy((reg_space + i), &reg, 8);
5455         }
5456 }
5457
5458 /**
5459  *  s2io_phy_id  - timer function that alternates adapter LED.
5460  *  @data : address of the private member of the device structure, which
5461  *  is a pointer to the s2io_nic structure, provided as an u32.
5462  * Description: This is actually the timer function that alternates the
5463  * adapter LED bit of the adapter control bit to set/reset every time on
5464  * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
5465  *  once every second.
5466  */
5467 static void s2io_phy_id(unsigned long data)
5468 {
5469         struct s2io_nic *sp = (struct s2io_nic *)data;
5470         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5471         u64 val64 = 0;
5472         u16 subid;
5473
5474         subid = sp->pdev->subsystem_device;
5475         if ((sp->device_type == XFRAME_II_DEVICE) ||
5476             ((subid & 0xFF) >= 0x07)) {
5477                 val64 = readq(&bar0->gpio_control);
5478                 val64 ^= GPIO_CTRL_GPIO_0;
5479                 writeq(val64, &bar0->gpio_control);
5480         } else {
5481                 val64 = readq(&bar0->adapter_control);
5482                 val64 ^= ADAPTER_LED_ON;
5483                 writeq(val64, &bar0->adapter_control);
5484         }
5485
5486         mod_timer(&sp->id_timer, jiffies + HZ / 2);
5487 }
5488
5489 /**
5490  * s2io_ethtool_idnic - To physically identify the nic on the system.
5491  * @sp : private member of the device structure, which is a pointer to the
5492  * s2io_nic structure.
5493  * @id : pointer to the structure with identification parameters given by
5494  * ethtool.
5495  * Description: Used to physically identify the NIC on the system.
5496  * The Link LED will blink for a time specified by the user for
<