r8169: adjust the RxConfig settings.
[linux-2.6.git] / drivers / net / r8169.c
1 /*
2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3  *
4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6  * Copyright (c) a lot of people too. Please respect their work.
7  *
8  * See MAINTAINERS file for support contact information.
9  */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
31
32 #include <asm/system.h>
33 #include <asm/io.h>
34 #include <asm/irq.h>
35
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
39
40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
46
47 #ifdef RTL8169_DEBUG
48 #define assert(expr) \
49         if (!(expr)) {                                  \
50                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
51                 #expr,__FILE__,__func__,__LINE__);              \
52         }
53 #define dprintk(fmt, args...) \
54         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
55 #else
56 #define assert(expr) do {} while (0)
57 #define dprintk(fmt, args...)   do {} while (0)
58 #endif /* RTL8169_DEBUG */
59
60 #define R8169_MSG_DEFAULT \
61         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
62
63 #define TX_BUFFS_AVAIL(tp) \
64         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
65
66 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
67    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
68 static const int multicast_filter_limit = 32;
69
70 /* MAC address length */
71 #define MAC_ADDR_LEN    6
72
73 #define MAX_READ_REQUEST_SHIFT  12
74 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
75 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
76 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
77
78 #define R8169_REGS_SIZE         256
79 #define R8169_NAPI_WEIGHT       64
80 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
81 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
82 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
83 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
84 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
85
86 #define RTL8169_TX_TIMEOUT      (6*HZ)
87 #define RTL8169_PHY_TIMEOUT     (10*HZ)
88
89 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
90 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
91 #define RTL_EEPROM_SIG_ADDR     0x0000
92
93 /* write/read MMIO register */
94 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
95 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
96 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
97 #define RTL_R8(reg)             readb (ioaddr + (reg))
98 #define RTL_R16(reg)            readw (ioaddr + (reg))
99 #define RTL_R32(reg)            readl (ioaddr + (reg))
100
101 enum mac_version {
102         RTL_GIGA_MAC_VER_01 = 0,
103         RTL_GIGA_MAC_VER_02,
104         RTL_GIGA_MAC_VER_03,
105         RTL_GIGA_MAC_VER_04,
106         RTL_GIGA_MAC_VER_05,
107         RTL_GIGA_MAC_VER_06,
108         RTL_GIGA_MAC_VER_07,
109         RTL_GIGA_MAC_VER_08,
110         RTL_GIGA_MAC_VER_09,
111         RTL_GIGA_MAC_VER_10,
112         RTL_GIGA_MAC_VER_11,
113         RTL_GIGA_MAC_VER_12,
114         RTL_GIGA_MAC_VER_13,
115         RTL_GIGA_MAC_VER_14,
116         RTL_GIGA_MAC_VER_15,
117         RTL_GIGA_MAC_VER_16,
118         RTL_GIGA_MAC_VER_17,
119         RTL_GIGA_MAC_VER_18,
120         RTL_GIGA_MAC_VER_19,
121         RTL_GIGA_MAC_VER_20,
122         RTL_GIGA_MAC_VER_21,
123         RTL_GIGA_MAC_VER_22,
124         RTL_GIGA_MAC_VER_23,
125         RTL_GIGA_MAC_VER_24,
126         RTL_GIGA_MAC_VER_25,
127         RTL_GIGA_MAC_VER_26,
128         RTL_GIGA_MAC_VER_27,
129         RTL_GIGA_MAC_VER_28,
130         RTL_GIGA_MAC_VER_29,
131         RTL_GIGA_MAC_VER_30,
132         RTL_GIGA_MAC_VER_31,
133         RTL_GIGA_MAC_VER_32,
134         RTL_GIGA_MAC_VER_33,
135         RTL_GIGA_MAC_VER_34,
136         RTL_GIGA_MAC_NONE   = 0xff,
137 };
138
139 enum rtl_tx_desc_version {
140         RTL_TD_0        = 0,
141         RTL_TD_1        = 1,
142 };
143
144 #define _R(NAME,TD,FW) \
145         { .name = NAME, .txd_version = TD, .fw_name = FW }
146
147 static const struct {
148         const char *name;
149         enum rtl_tx_desc_version txd_version;
150         const char *fw_name;
151 } rtl_chip_infos[] = {
152         /* PCI devices. */
153         [RTL_GIGA_MAC_VER_01] =
154                 _R("RTL8169",           RTL_TD_0, NULL),
155         [RTL_GIGA_MAC_VER_02] =
156                 _R("RTL8169s",          RTL_TD_0, NULL),
157         [RTL_GIGA_MAC_VER_03] =
158                 _R("RTL8110s",          RTL_TD_0, NULL),
159         [RTL_GIGA_MAC_VER_04] =
160                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL),
161         [RTL_GIGA_MAC_VER_05] =
162                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
163         [RTL_GIGA_MAC_VER_06] =
164                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
165         /* PCI-E devices. */
166         [RTL_GIGA_MAC_VER_07] =
167                 _R("RTL8102e",          RTL_TD_1, NULL),
168         [RTL_GIGA_MAC_VER_08] =
169                 _R("RTL8102e",          RTL_TD_1, NULL),
170         [RTL_GIGA_MAC_VER_09] =
171                 _R("RTL8102e",          RTL_TD_1, NULL),
172         [RTL_GIGA_MAC_VER_10] =
173                 _R("RTL8101e",          RTL_TD_0, NULL),
174         [RTL_GIGA_MAC_VER_11] =
175                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
176         [RTL_GIGA_MAC_VER_12] =
177                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
178         [RTL_GIGA_MAC_VER_13] =
179                 _R("RTL8101e",          RTL_TD_0, NULL),
180         [RTL_GIGA_MAC_VER_14] =
181                 _R("RTL8100e",          RTL_TD_0, NULL),
182         [RTL_GIGA_MAC_VER_15] =
183                 _R("RTL8100e",          RTL_TD_0, NULL),
184         [RTL_GIGA_MAC_VER_16] =
185                 _R("RTL8101e",          RTL_TD_0, NULL),
186         [RTL_GIGA_MAC_VER_17] =
187                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
188         [RTL_GIGA_MAC_VER_18] =
189                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
190         [RTL_GIGA_MAC_VER_19] =
191                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
192         [RTL_GIGA_MAC_VER_20] =
193                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
194         [RTL_GIGA_MAC_VER_21] =
195                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
196         [RTL_GIGA_MAC_VER_22] =
197                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
198         [RTL_GIGA_MAC_VER_23] =
199                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
200         [RTL_GIGA_MAC_VER_24] =
201                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
202         [RTL_GIGA_MAC_VER_25] =
203                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1),
204         [RTL_GIGA_MAC_VER_26] =
205                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2),
206         [RTL_GIGA_MAC_VER_27] =
207                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
208         [RTL_GIGA_MAC_VER_28] =
209                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
210         [RTL_GIGA_MAC_VER_29] =
211                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
212         [RTL_GIGA_MAC_VER_30] =
213                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
214         [RTL_GIGA_MAC_VER_31] =
215                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
216         [RTL_GIGA_MAC_VER_32] =
217                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1),
218         [RTL_GIGA_MAC_VER_33] =
219                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2),
220         [RTL_GIGA_MAC_VER_34] =
221                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3)
222 };
223 #undef _R
224
225 enum cfg_version {
226         RTL_CFG_0 = 0x00,
227         RTL_CFG_1,
228         RTL_CFG_2
229 };
230
231 static void rtl_hw_start_8169(struct net_device *);
232 static void rtl_hw_start_8168(struct net_device *);
233 static void rtl_hw_start_8101(struct net_device *);
234
235 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
236         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
237         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
238         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
239         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
240         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
241         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
242         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
243         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
244         { PCI_VENDOR_ID_LINKSYS,                0x1032,
245                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
246         { 0x0001,                               0x8168,
247                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
248         {0,},
249 };
250
251 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
252
253 static int rx_buf_sz = 16383;
254 static int use_dac;
255 static struct {
256         u32 msg_enable;
257 } debug = { -1 };
258
259 enum rtl_registers {
260         MAC0            = 0,    /* Ethernet hardware address. */
261         MAC4            = 4,
262         MAR0            = 8,    /* Multicast filter. */
263         CounterAddrLow          = 0x10,
264         CounterAddrHigh         = 0x14,
265         TxDescStartAddrLow      = 0x20,
266         TxDescStartAddrHigh     = 0x24,
267         TxHDescStartAddrLow     = 0x28,
268         TxHDescStartAddrHigh    = 0x2c,
269         FLASH           = 0x30,
270         ERSR            = 0x36,
271         ChipCmd         = 0x37,
272         TxPoll          = 0x38,
273         IntrMask        = 0x3c,
274         IntrStatus      = 0x3e,
275
276         TxConfig        = 0x40,
277 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
278 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
279
280         RxConfig        = 0x44,
281 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
282 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
283 #define RXCFG_FIFO_SHIFT                13
284                                         /* No threshold before first PCI xfer */
285 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
286 #define RXCFG_DMA_SHIFT                 8
287                                         /* Unlimited maximum PCI burst. */
288 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
289
290         RxMissed        = 0x4c,
291         Cfg9346         = 0x50,
292         Config0         = 0x51,
293         Config1         = 0x52,
294         Config2         = 0x53,
295         Config3         = 0x54,
296         Config4         = 0x55,
297         Config5         = 0x56,
298         MultiIntr       = 0x5c,
299         PHYAR           = 0x60,
300         PHYstatus       = 0x6c,
301         RxMaxSize       = 0xda,
302         CPlusCmd        = 0xe0,
303         IntrMitigate    = 0xe2,
304         RxDescAddrLow   = 0xe4,
305         RxDescAddrHigh  = 0xe8,
306         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
307
308 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
309
310         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
311
312 #define TxPacketMax     (8064 >> 7)
313
314         FuncEvent       = 0xf0,
315         FuncEventMask   = 0xf4,
316         FuncPresetState = 0xf8,
317         FuncForceEvent  = 0xfc,
318 };
319
320 enum rtl8110_registers {
321         TBICSR                  = 0x64,
322         TBI_ANAR                = 0x68,
323         TBI_LPAR                = 0x6a,
324 };
325
326 enum rtl8168_8101_registers {
327         CSIDR                   = 0x64,
328         CSIAR                   = 0x68,
329 #define CSIAR_FLAG                      0x80000000
330 #define CSIAR_WRITE_CMD                 0x80000000
331 #define CSIAR_BYTE_ENABLE               0x0f
332 #define CSIAR_BYTE_ENABLE_SHIFT         12
333 #define CSIAR_ADDR_MASK                 0x0fff
334         PMCH                    = 0x6f,
335         EPHYAR                  = 0x80,
336 #define EPHYAR_FLAG                     0x80000000
337 #define EPHYAR_WRITE_CMD                0x80000000
338 #define EPHYAR_REG_MASK                 0x1f
339 #define EPHYAR_REG_SHIFT                16
340 #define EPHYAR_DATA_MASK                0xffff
341         DLLPR                   = 0xd0,
342 #define PFM_EN                          (1 << 6)
343         DBG_REG                 = 0xd1,
344 #define FIX_NAK_1                       (1 << 4)
345 #define FIX_NAK_2                       (1 << 3)
346         TWSI                    = 0xd2,
347         MCU                     = 0xd3,
348 #define NOW_IS_OOB                      (1 << 7)
349 #define EN_NDP                          (1 << 3)
350 #define EN_OOB_RESET                    (1 << 2)
351         EFUSEAR                 = 0xdc,
352 #define EFUSEAR_FLAG                    0x80000000
353 #define EFUSEAR_WRITE_CMD               0x80000000
354 #define EFUSEAR_READ_CMD                0x00000000
355 #define EFUSEAR_REG_MASK                0x03ff
356 #define EFUSEAR_REG_SHIFT               8
357 #define EFUSEAR_DATA_MASK               0xff
358 };
359
360 enum rtl8168_registers {
361         LED_FREQ                = 0x1a,
362         EEE_LED                 = 0x1b,
363         ERIDR                   = 0x70,
364         ERIAR                   = 0x74,
365 #define ERIAR_FLAG                      0x80000000
366 #define ERIAR_WRITE_CMD                 0x80000000
367 #define ERIAR_READ_CMD                  0x00000000
368 #define ERIAR_ADDR_BYTE_ALIGN           4
369 #define ERIAR_TYPE_SHIFT                16
370 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
371 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
372 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
373 #define ERIAR_MASK_SHIFT                12
374 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
375 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
376 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
377         EPHY_RXER_NUM           = 0x7c,
378         OCPDR                   = 0xb0, /* OCP GPHY access */
379 #define OCPDR_WRITE_CMD                 0x80000000
380 #define OCPDR_READ_CMD                  0x00000000
381 #define OCPDR_REG_MASK                  0x7f
382 #define OCPDR_GPHY_REG_SHIFT            16
383 #define OCPDR_DATA_MASK                 0xffff
384         OCPAR                   = 0xb4,
385 #define OCPAR_FLAG                      0x80000000
386 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
387 #define OCPAR_GPHY_READ_CMD             0x0000f060
388         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
389         MISC                    = 0xf0, /* 8168e only. */
390 #define TXPLA_RST                       (1 << 29)
391 #define PWM_EN                          (1 << 22)
392 };
393
394 enum rtl_register_content {
395         /* InterruptStatusBits */
396         SYSErr          = 0x8000,
397         PCSTimeout      = 0x4000,
398         SWInt           = 0x0100,
399         TxDescUnavail   = 0x0080,
400         RxFIFOOver      = 0x0040,
401         LinkChg         = 0x0020,
402         RxOverflow      = 0x0010,
403         TxErr           = 0x0008,
404         TxOK            = 0x0004,
405         RxErr           = 0x0002,
406         RxOK            = 0x0001,
407
408         /* RxStatusDesc */
409         RxFOVF  = (1 << 23),
410         RxRWT   = (1 << 22),
411         RxRES   = (1 << 21),
412         RxRUNT  = (1 << 20),
413         RxCRC   = (1 << 19),
414
415         /* ChipCmdBits */
416         StopReq         = 0x80,
417         CmdReset        = 0x10,
418         CmdRxEnb        = 0x08,
419         CmdTxEnb        = 0x04,
420         RxBufEmpty      = 0x01,
421
422         /* TXPoll register p.5 */
423         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
424         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
425         FSWInt          = 0x01,         /* Forced software interrupt */
426
427         /* Cfg9346Bits */
428         Cfg9346_Lock    = 0x00,
429         Cfg9346_Unlock  = 0xc0,
430
431         /* rx_mode_bits */
432         AcceptErr       = 0x20,
433         AcceptRunt      = 0x10,
434         AcceptBroadcast = 0x08,
435         AcceptMulticast = 0x04,
436         AcceptMyPhys    = 0x02,
437         AcceptAllPhys   = 0x01,
438
439         /* TxConfigBits */
440         TxInterFrameGapShift = 24,
441         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
442
443         /* Config1 register p.24 */
444         LEDS1           = (1 << 7),
445         LEDS0           = (1 << 6),
446         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
447         Speed_down      = (1 << 4),
448         MEMMAP          = (1 << 3),
449         IOMAP           = (1 << 2),
450         VPD             = (1 << 1),
451         PMEnable        = (1 << 0),     /* Power Management Enable */
452
453         /* Config2 register p. 25 */
454         PCI_Clock_66MHz = 0x01,
455         PCI_Clock_33MHz = 0x00,
456
457         /* Config3 register p.25 */
458         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
459         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
460         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
461
462         /* Config5 register p.27 */
463         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
464         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
465         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
466         Spi_en          = (1 << 3),
467         LanWake         = (1 << 1),     /* LanWake enable/disable */
468         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
469
470         /* TBICSR p.28 */
471         TBIReset        = 0x80000000,
472         TBILoopback     = 0x40000000,
473         TBINwEnable     = 0x20000000,
474         TBINwRestart    = 0x10000000,
475         TBILinkOk       = 0x02000000,
476         TBINwComplete   = 0x01000000,
477
478         /* CPlusCmd p.31 */
479         EnableBist      = (1 << 15),    // 8168 8101
480         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
481         Normal_mode     = (1 << 13),    // unused
482         Force_half_dup  = (1 << 12),    // 8168 8101
483         Force_rxflow_en = (1 << 11),    // 8168 8101
484         Force_txflow_en = (1 << 10),    // 8168 8101
485         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
486         ASF             = (1 << 8),     // 8168 8101
487         PktCntrDisable  = (1 << 7),     // 8168 8101
488         Mac_dbgo_sel    = 0x001c,       // 8168
489         RxVlan          = (1 << 6),
490         RxChkSum        = (1 << 5),
491         PCIDAC          = (1 << 4),
492         PCIMulRW        = (1 << 3),
493         INTT_0          = 0x0000,       // 8168
494         INTT_1          = 0x0001,       // 8168
495         INTT_2          = 0x0002,       // 8168
496         INTT_3          = 0x0003,       // 8168
497
498         /* rtl8169_PHYstatus */
499         TBI_Enable      = 0x80,
500         TxFlowCtrl      = 0x40,
501         RxFlowCtrl      = 0x20,
502         _1000bpsF       = 0x10,
503         _100bps         = 0x08,
504         _10bps          = 0x04,
505         LinkStatus      = 0x02,
506         FullDup         = 0x01,
507
508         /* _TBICSRBit */
509         TBILinkOK       = 0x02000000,
510
511         /* DumpCounterCommand */
512         CounterDump     = 0x8,
513 };
514
515 enum rtl_desc_bit {
516         /* First doubleword. */
517         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
518         RingEnd         = (1 << 30), /* End of descriptor ring */
519         FirstFrag       = (1 << 29), /* First segment of a packet */
520         LastFrag        = (1 << 28), /* Final segment of a packet */
521 };
522
523 /* Generic case. */
524 enum rtl_tx_desc_bit {
525         /* First doubleword. */
526         TD_LSO          = (1 << 27),            /* Large Send Offload */
527 #define TD_MSS_MAX                      0x07ffu /* MSS value */
528
529         /* Second doubleword. */
530         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
531 };
532
533 /* 8169, 8168b and 810x except 8102e. */
534 enum rtl_tx_desc_bit_0 {
535         /* First doubleword. */
536 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
537         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
538         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
539         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
540 };
541
542 /* 8102e, 8168c and beyond. */
543 enum rtl_tx_desc_bit_1 {
544         /* Second doubleword. */
545 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
546         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
547         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
548         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
549 };
550
551 static const struct rtl_tx_desc_info {
552         struct {
553                 u32 udp;
554                 u32 tcp;
555         } checksum;
556         u16 mss_shift;
557         u16 opts_offset;
558 } tx_desc_info [] = {
559         [RTL_TD_0] = {
560                 .checksum = {
561                         .udp    = TD0_IP_CS | TD0_UDP_CS,
562                         .tcp    = TD0_IP_CS | TD0_TCP_CS
563                 },
564                 .mss_shift      = TD0_MSS_SHIFT,
565                 .opts_offset    = 0
566         },
567         [RTL_TD_1] = {
568                 .checksum = {
569                         .udp    = TD1_IP_CS | TD1_UDP_CS,
570                         .tcp    = TD1_IP_CS | TD1_TCP_CS
571                 },
572                 .mss_shift      = TD1_MSS_SHIFT,
573                 .opts_offset    = 1
574         }
575 };
576
577 enum rtl_rx_desc_bit {
578         /* Rx private */
579         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
580         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
581
582 #define RxProtoUDP      (PID1)
583 #define RxProtoTCP      (PID0)
584 #define RxProtoIP       (PID1 | PID0)
585 #define RxProtoMask     RxProtoIP
586
587         IPFail          = (1 << 16), /* IP checksum failed */
588         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
589         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
590         RxVlanTag       = (1 << 16), /* VLAN tag available */
591 };
592
593 #define RsvdMask        0x3fffc000
594
595 struct TxDesc {
596         __le32 opts1;
597         __le32 opts2;
598         __le64 addr;
599 };
600
601 struct RxDesc {
602         __le32 opts1;
603         __le32 opts2;
604         __le64 addr;
605 };
606
607 struct ring_info {
608         struct sk_buff  *skb;
609         u32             len;
610         u8              __pad[sizeof(void *) - sizeof(u32)];
611 };
612
613 enum features {
614         RTL_FEATURE_WOL         = (1 << 0),
615         RTL_FEATURE_MSI         = (1 << 1),
616         RTL_FEATURE_GMII        = (1 << 2),
617 };
618
619 struct rtl8169_counters {
620         __le64  tx_packets;
621         __le64  rx_packets;
622         __le64  tx_errors;
623         __le32  rx_errors;
624         __le16  rx_missed;
625         __le16  align_errors;
626         __le32  tx_one_collision;
627         __le32  tx_multi_collision;
628         __le64  rx_unicast;
629         __le64  rx_broadcast;
630         __le32  rx_multicast;
631         __le16  tx_aborted;
632         __le16  tx_underun;
633 };
634
635 struct rtl8169_private {
636         void __iomem *mmio_addr;        /* memory map physical address */
637         struct pci_dev *pci_dev;
638         struct net_device *dev;
639         struct napi_struct napi;
640         spinlock_t lock;
641         u32 msg_enable;
642         u16 txd_version;
643         u16 mac_version;
644         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
645         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
646         u32 dirty_rx;
647         u32 dirty_tx;
648         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
649         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
650         dma_addr_t TxPhyAddr;
651         dma_addr_t RxPhyAddr;
652         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
653         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
654         struct timer_list timer;
655         u16 cp_cmd;
656         u16 intr_event;
657         u16 napi_event;
658         u16 intr_mask;
659
660         struct mdio_ops {
661                 void (*write)(void __iomem *, int, int);
662                 int (*read)(void __iomem *, int);
663         } mdio_ops;
664
665         struct pll_power_ops {
666                 void (*down)(struct rtl8169_private *);
667                 void (*up)(struct rtl8169_private *);
668         } pll_power_ops;
669
670         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
671         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
672         void (*phy_reset_enable)(struct rtl8169_private *tp);
673         void (*hw_start)(struct net_device *);
674         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
675         unsigned int (*link_ok)(void __iomem *);
676         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
677         struct delayed_work task;
678         unsigned features;
679
680         struct mii_if_info mii;
681         struct rtl8169_counters counters;
682         u32 saved_wolopts;
683
684         struct rtl_fw {
685                 const struct firmware *fw;
686
687 #define RTL_VER_SIZE            32
688
689                 char version[RTL_VER_SIZE];
690
691                 struct rtl_fw_phy_action {
692                         __le32 *code;
693                         size_t size;
694                 } phy_action;
695         } *rtl_fw;
696 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN);
697 };
698
699 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
700 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
701 module_param(use_dac, int, 0);
702 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
703 module_param_named(debug, debug.msg_enable, int, 0);
704 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
705 MODULE_LICENSE("GPL");
706 MODULE_VERSION(RTL8169_VERSION);
707 MODULE_FIRMWARE(FIRMWARE_8168D_1);
708 MODULE_FIRMWARE(FIRMWARE_8168D_2);
709 MODULE_FIRMWARE(FIRMWARE_8168E_1);
710 MODULE_FIRMWARE(FIRMWARE_8168E_2);
711 MODULE_FIRMWARE(FIRMWARE_8105E_1);
712
713 static int rtl8169_open(struct net_device *dev);
714 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
715                                       struct net_device *dev);
716 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
717 static int rtl8169_init_ring(struct net_device *dev);
718 static void rtl_hw_start(struct net_device *dev);
719 static int rtl8169_close(struct net_device *dev);
720 static void rtl_set_rx_mode(struct net_device *dev);
721 static void rtl8169_tx_timeout(struct net_device *dev);
722 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
723 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
724                                 void __iomem *, u32 budget);
725 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
726 static void rtl8169_down(struct net_device *dev);
727 static void rtl8169_rx_clear(struct rtl8169_private *tp);
728 static int rtl8169_poll(struct napi_struct *napi, int budget);
729
730 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
731 {
732         void __iomem *ioaddr = tp->mmio_addr;
733         int i;
734
735         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
736         for (i = 0; i < 20; i++) {
737                 udelay(100);
738                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
739                         break;
740         }
741         return RTL_R32(OCPDR);
742 }
743
744 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
745 {
746         void __iomem *ioaddr = tp->mmio_addr;
747         int i;
748
749         RTL_W32(OCPDR, data);
750         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
751         for (i = 0; i < 20; i++) {
752                 udelay(100);
753                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
754                         break;
755         }
756 }
757
758 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
759 {
760         void __iomem *ioaddr = tp->mmio_addr;
761         int i;
762
763         RTL_W8(ERIDR, cmd);
764         RTL_W32(ERIAR, 0x800010e8);
765         msleep(2);
766         for (i = 0; i < 5; i++) {
767                 udelay(100);
768                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
769                         break;
770         }
771
772         ocp_write(tp, 0x1, 0x30, 0x00000001);
773 }
774
775 #define OOB_CMD_RESET           0x00
776 #define OOB_CMD_DRIVER_START    0x05
777 #define OOB_CMD_DRIVER_STOP     0x06
778
779 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
780 {
781         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
782 }
783
784 static void rtl8168_driver_start(struct rtl8169_private *tp)
785 {
786         u16 reg;
787         int i;
788
789         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
790
791         reg = rtl8168_get_ocp_reg(tp);
792
793         for (i = 0; i < 10; i++) {
794                 msleep(10);
795                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
796                         break;
797         }
798 }
799
800 static void rtl8168_driver_stop(struct rtl8169_private *tp)
801 {
802         u16 reg;
803         int i;
804
805         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
806
807         reg = rtl8168_get_ocp_reg(tp);
808
809         for (i = 0; i < 10; i++) {
810                 msleep(10);
811                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
812                         break;
813         }
814 }
815
816 static int r8168dp_check_dash(struct rtl8169_private *tp)
817 {
818         u16 reg = rtl8168_get_ocp_reg(tp);
819
820         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
821 }
822
823 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
824 {
825         int i;
826
827         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
828
829         for (i = 20; i > 0; i--) {
830                 /*
831                  * Check if the RTL8169 has completed writing to the specified
832                  * MII register.
833                  */
834                 if (!(RTL_R32(PHYAR) & 0x80000000))
835                         break;
836                 udelay(25);
837         }
838         /*
839          * According to hardware specs a 20us delay is required after write
840          * complete indication, but before sending next command.
841          */
842         udelay(20);
843 }
844
845 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
846 {
847         int i, value = -1;
848
849         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
850
851         for (i = 20; i > 0; i--) {
852                 /*
853                  * Check if the RTL8169 has completed retrieving data from
854                  * the specified MII register.
855                  */
856                 if (RTL_R32(PHYAR) & 0x80000000) {
857                         value = RTL_R32(PHYAR) & 0xffff;
858                         break;
859                 }
860                 udelay(25);
861         }
862         /*
863          * According to hardware specs a 20us delay is required after read
864          * complete indication, but before sending next command.
865          */
866         udelay(20);
867
868         return value;
869 }
870
871 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
872 {
873         int i;
874
875         RTL_W32(OCPDR, data |
876                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
877         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
878         RTL_W32(EPHY_RXER_NUM, 0);
879
880         for (i = 0; i < 100; i++) {
881                 mdelay(1);
882                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
883                         break;
884         }
885 }
886
887 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
888 {
889         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
890                 (value & OCPDR_DATA_MASK));
891 }
892
893 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
894 {
895         int i;
896
897         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
898
899         mdelay(1);
900         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
901         RTL_W32(EPHY_RXER_NUM, 0);
902
903         for (i = 0; i < 100; i++) {
904                 mdelay(1);
905                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
906                         break;
907         }
908
909         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
910 }
911
912 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
913
914 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
915 {
916         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
917 }
918
919 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
920 {
921         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
922 }
923
924 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
925 {
926         r8168dp_2_mdio_start(ioaddr);
927
928         r8169_mdio_write(ioaddr, reg_addr, value);
929
930         r8168dp_2_mdio_stop(ioaddr);
931 }
932
933 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
934 {
935         int value;
936
937         r8168dp_2_mdio_start(ioaddr);
938
939         value = r8169_mdio_read(ioaddr, reg_addr);
940
941         r8168dp_2_mdio_stop(ioaddr);
942
943         return value;
944 }
945
946 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
947 {
948         tp->mdio_ops.write(tp->mmio_addr, location, val);
949 }
950
951 static int rtl_readphy(struct rtl8169_private *tp, int location)
952 {
953         return tp->mdio_ops.read(tp->mmio_addr, location);
954 }
955
956 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
957 {
958         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
959 }
960
961 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
962 {
963         int val;
964
965         val = rtl_readphy(tp, reg_addr);
966         rtl_writephy(tp, reg_addr, (val | p) & ~m);
967 }
968
969 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
970                            int val)
971 {
972         struct rtl8169_private *tp = netdev_priv(dev);
973
974         rtl_writephy(tp, location, val);
975 }
976
977 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
978 {
979         struct rtl8169_private *tp = netdev_priv(dev);
980
981         return rtl_readphy(tp, location);
982 }
983
984 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
985 {
986         unsigned int i;
987
988         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
989                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
990
991         for (i = 0; i < 100; i++) {
992                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
993                         break;
994                 udelay(10);
995         }
996 }
997
998 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
999 {
1000         u16 value = 0xffff;
1001         unsigned int i;
1002
1003         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1004
1005         for (i = 0; i < 100; i++) {
1006                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1007                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1008                         break;
1009                 }
1010                 udelay(10);
1011         }
1012
1013         return value;
1014 }
1015
1016 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1017 {
1018         unsigned int i;
1019
1020         RTL_W32(CSIDR, value);
1021         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1022                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1023
1024         for (i = 0; i < 100; i++) {
1025                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1026                         break;
1027                 udelay(10);
1028         }
1029 }
1030
1031 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1032 {
1033         u32 value = ~0x00;
1034         unsigned int i;
1035
1036         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1037                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1038
1039         for (i = 0; i < 100; i++) {
1040                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1041                         value = RTL_R32(CSIDR);
1042                         break;
1043                 }
1044                 udelay(10);
1045         }
1046
1047         return value;
1048 }
1049
1050 static
1051 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1052 {
1053         unsigned int i;
1054
1055         BUG_ON((addr & 3) || (mask == 0));
1056         RTL_W32(ERIDR, val);
1057         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1058
1059         for (i = 0; i < 100; i++) {
1060                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1061                         break;
1062                 udelay(100);
1063         }
1064 }
1065
1066 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1067 {
1068         u32 value = ~0x00;
1069         unsigned int i;
1070
1071         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1072
1073         for (i = 0; i < 100; i++) {
1074                 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1075                         value = RTL_R32(ERIDR);
1076                         break;
1077                 }
1078                 udelay(100);
1079         }
1080
1081         return value;
1082 }
1083
1084 static void
1085 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1086 {
1087         u32 val;
1088
1089         val = rtl_eri_read(ioaddr, addr, type);
1090         rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1091 }
1092
1093 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1094 {
1095         u8 value = 0xff;
1096         unsigned int i;
1097
1098         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1099
1100         for (i = 0; i < 300; i++) {
1101                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1102                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1103                         break;
1104                 }
1105                 udelay(100);
1106         }
1107
1108         return value;
1109 }
1110
1111 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1112 {
1113         RTL_W16(IntrMask, 0x0000);
1114
1115         RTL_W16(IntrStatus, 0xffff);
1116 }
1117
1118 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1119 {
1120         void __iomem *ioaddr = tp->mmio_addr;
1121
1122         return RTL_R32(TBICSR) & TBIReset;
1123 }
1124
1125 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1126 {
1127         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1128 }
1129
1130 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1131 {
1132         return RTL_R32(TBICSR) & TBILinkOk;
1133 }
1134
1135 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1136 {
1137         return RTL_R8(PHYstatus) & LinkStatus;
1138 }
1139
1140 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1141 {
1142         void __iomem *ioaddr = tp->mmio_addr;
1143
1144         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1145 }
1146
1147 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1148 {
1149         unsigned int val;
1150
1151         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1152         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1153 }
1154
1155 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1156 {
1157         void __iomem *ioaddr = tp->mmio_addr;
1158         struct net_device *dev = tp->dev;
1159
1160         if (!netif_running(dev))
1161                 return;
1162
1163         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1164                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1165                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1166                                       0x00000011, ERIAR_EXGMAC);
1167                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1168                                       0x00000005, ERIAR_EXGMAC);
1169                 } else if (RTL_R8(PHYstatus) & _100bps) {
1170                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1171                                       0x0000001f, ERIAR_EXGMAC);
1172                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1173                                       0x00000005, ERIAR_EXGMAC);
1174                 } else {
1175                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1176                                       0x0000001f, ERIAR_EXGMAC);
1177                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1178                                       0x0000003f, ERIAR_EXGMAC);
1179                 }
1180                 /* Reset packet filter */
1181                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1182                              ERIAR_EXGMAC);
1183                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1184                              ERIAR_EXGMAC);
1185         }
1186 }
1187
1188 static void __rtl8169_check_link_status(struct net_device *dev,
1189                                         struct rtl8169_private *tp,
1190                                         void __iomem *ioaddr, bool pm)
1191 {
1192         unsigned long flags;
1193
1194         spin_lock_irqsave(&tp->lock, flags);
1195         if (tp->link_ok(ioaddr)) {
1196                 rtl_link_chg_patch(tp);
1197                 /* This is to cancel a scheduled suspend if there's one. */
1198                 if (pm)
1199                         pm_request_resume(&tp->pci_dev->dev);
1200                 netif_carrier_on(dev);
1201                 if (net_ratelimit())
1202                         netif_info(tp, ifup, dev, "link up\n");
1203         } else {
1204                 netif_carrier_off(dev);
1205                 netif_info(tp, ifdown, dev, "link down\n");
1206                 if (pm)
1207                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
1208         }
1209         spin_unlock_irqrestore(&tp->lock, flags);
1210 }
1211
1212 static void rtl8169_check_link_status(struct net_device *dev,
1213                                       struct rtl8169_private *tp,
1214                                       void __iomem *ioaddr)
1215 {
1216         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1217 }
1218
1219 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1220
1221 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1222 {
1223         void __iomem *ioaddr = tp->mmio_addr;
1224         u8 options;
1225         u32 wolopts = 0;
1226
1227         options = RTL_R8(Config1);
1228         if (!(options & PMEnable))
1229                 return 0;
1230
1231         options = RTL_R8(Config3);
1232         if (options & LinkUp)
1233                 wolopts |= WAKE_PHY;
1234         if (options & MagicPacket)
1235                 wolopts |= WAKE_MAGIC;
1236
1237         options = RTL_R8(Config5);
1238         if (options & UWF)
1239                 wolopts |= WAKE_UCAST;
1240         if (options & BWF)
1241                 wolopts |= WAKE_BCAST;
1242         if (options & MWF)
1243                 wolopts |= WAKE_MCAST;
1244
1245         return wolopts;
1246 }
1247
1248 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1249 {
1250         struct rtl8169_private *tp = netdev_priv(dev);
1251
1252         spin_lock_irq(&tp->lock);
1253
1254         wol->supported = WAKE_ANY;
1255         wol->wolopts = __rtl8169_get_wol(tp);
1256
1257         spin_unlock_irq(&tp->lock);
1258 }
1259
1260 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1261 {
1262         void __iomem *ioaddr = tp->mmio_addr;
1263         unsigned int i;
1264         static const struct {
1265                 u32 opt;
1266                 u16 reg;
1267                 u8  mask;
1268         } cfg[] = {
1269                 { WAKE_ANY,   Config1, PMEnable },
1270                 { WAKE_PHY,   Config3, LinkUp },
1271                 { WAKE_MAGIC, Config3, MagicPacket },
1272                 { WAKE_UCAST, Config5, UWF },
1273                 { WAKE_BCAST, Config5, BWF },
1274                 { WAKE_MCAST, Config5, MWF },
1275                 { WAKE_ANY,   Config5, LanWake }
1276         };
1277
1278         RTL_W8(Cfg9346, Cfg9346_Unlock);
1279
1280         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1281                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1282                 if (wolopts & cfg[i].opt)
1283                         options |= cfg[i].mask;
1284                 RTL_W8(cfg[i].reg, options);
1285         }
1286
1287         RTL_W8(Cfg9346, Cfg9346_Lock);
1288 }
1289
1290 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1291 {
1292         struct rtl8169_private *tp = netdev_priv(dev);
1293
1294         spin_lock_irq(&tp->lock);
1295
1296         if (wol->wolopts)
1297                 tp->features |= RTL_FEATURE_WOL;
1298         else
1299                 tp->features &= ~RTL_FEATURE_WOL;
1300         __rtl8169_set_wol(tp, wol->wolopts);
1301         spin_unlock_irq(&tp->lock);
1302
1303         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1304
1305         return 0;
1306 }
1307
1308 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1309 {
1310         return rtl_chip_infos[tp->mac_version].fw_name;
1311 }
1312
1313 static void rtl8169_get_drvinfo(struct net_device *dev,
1314                                 struct ethtool_drvinfo *info)
1315 {
1316         struct rtl8169_private *tp = netdev_priv(dev);
1317         struct rtl_fw *rtl_fw = tp->rtl_fw;
1318
1319         strcpy(info->driver, MODULENAME);
1320         strcpy(info->version, RTL8169_VERSION);
1321         strcpy(info->bus_info, pci_name(tp->pci_dev));
1322         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1323         strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1324                rtl_fw->version);
1325 }
1326
1327 static int rtl8169_get_regs_len(struct net_device *dev)
1328 {
1329         return R8169_REGS_SIZE;
1330 }
1331
1332 static int rtl8169_set_speed_tbi(struct net_device *dev,
1333                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1334 {
1335         struct rtl8169_private *tp = netdev_priv(dev);
1336         void __iomem *ioaddr = tp->mmio_addr;
1337         int ret = 0;
1338         u32 reg;
1339
1340         reg = RTL_R32(TBICSR);
1341         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1342             (duplex == DUPLEX_FULL)) {
1343                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1344         } else if (autoneg == AUTONEG_ENABLE)
1345                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1346         else {
1347                 netif_warn(tp, link, dev,
1348                            "incorrect speed setting refused in TBI mode\n");
1349                 ret = -EOPNOTSUPP;
1350         }
1351
1352         return ret;
1353 }
1354
1355 static int rtl8169_set_speed_xmii(struct net_device *dev,
1356                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1357 {
1358         struct rtl8169_private *tp = netdev_priv(dev);
1359         int giga_ctrl, bmcr;
1360         int rc = -EINVAL;
1361
1362         rtl_writephy(tp, 0x1f, 0x0000);
1363
1364         if (autoneg == AUTONEG_ENABLE) {
1365                 int auto_nego;
1366
1367                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1368                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1369                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1370
1371                 if (adv & ADVERTISED_10baseT_Half)
1372                         auto_nego |= ADVERTISE_10HALF;
1373                 if (adv & ADVERTISED_10baseT_Full)
1374                         auto_nego |= ADVERTISE_10FULL;
1375                 if (adv & ADVERTISED_100baseT_Half)
1376                         auto_nego |= ADVERTISE_100HALF;
1377                 if (adv & ADVERTISED_100baseT_Full)
1378                         auto_nego |= ADVERTISE_100FULL;
1379
1380                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1381
1382                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1383                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1384
1385                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1386                 if (tp->mii.supports_gmii) {
1387                         if (adv & ADVERTISED_1000baseT_Half)
1388                                 giga_ctrl |= ADVERTISE_1000HALF;
1389                         if (adv & ADVERTISED_1000baseT_Full)
1390                                 giga_ctrl |= ADVERTISE_1000FULL;
1391                 } else if (adv & (ADVERTISED_1000baseT_Half |
1392                                   ADVERTISED_1000baseT_Full)) {
1393                         netif_info(tp, link, dev,
1394                                    "PHY does not support 1000Mbps\n");
1395                         goto out;
1396                 }
1397
1398                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1399
1400                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1401                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1402         } else {
1403                 giga_ctrl = 0;
1404
1405                 if (speed == SPEED_10)
1406                         bmcr = 0;
1407                 else if (speed == SPEED_100)
1408                         bmcr = BMCR_SPEED100;
1409                 else
1410                         goto out;
1411
1412                 if (duplex == DUPLEX_FULL)
1413                         bmcr |= BMCR_FULLDPLX;
1414         }
1415
1416         rtl_writephy(tp, MII_BMCR, bmcr);
1417
1418         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1419             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1420                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1421                         rtl_writephy(tp, 0x17, 0x2138);
1422                         rtl_writephy(tp, 0x0e, 0x0260);
1423                 } else {
1424                         rtl_writephy(tp, 0x17, 0x2108);
1425                         rtl_writephy(tp, 0x0e, 0x0000);
1426                 }
1427         }
1428
1429         rc = 0;
1430 out:
1431         return rc;
1432 }
1433
1434 static int rtl8169_set_speed(struct net_device *dev,
1435                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1436 {
1437         struct rtl8169_private *tp = netdev_priv(dev);
1438         int ret;
1439
1440         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1441         if (ret < 0)
1442                 goto out;
1443
1444         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1445             (advertising & ADVERTISED_1000baseT_Full)) {
1446                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1447         }
1448 out:
1449         return ret;
1450 }
1451
1452 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1453 {
1454         struct rtl8169_private *tp = netdev_priv(dev);
1455         unsigned long flags;
1456         int ret;
1457
1458         del_timer_sync(&tp->timer);
1459
1460         spin_lock_irqsave(&tp->lock, flags);
1461         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1462                                 cmd->duplex, cmd->advertising);
1463         spin_unlock_irqrestore(&tp->lock, flags);
1464
1465         return ret;
1466 }
1467
1468 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1469 {
1470         if (dev->mtu > TD_MSS_MAX)
1471                 features &= ~NETIF_F_ALL_TSO;
1472
1473         return features;
1474 }
1475
1476 static int rtl8169_set_features(struct net_device *dev, u32 features)
1477 {
1478         struct rtl8169_private *tp = netdev_priv(dev);
1479         void __iomem *ioaddr = tp->mmio_addr;
1480         unsigned long flags;
1481
1482         spin_lock_irqsave(&tp->lock, flags);
1483
1484         if (features & NETIF_F_RXCSUM)
1485                 tp->cp_cmd |= RxChkSum;
1486         else
1487                 tp->cp_cmd &= ~RxChkSum;
1488
1489         if (dev->features & NETIF_F_HW_VLAN_RX)
1490                 tp->cp_cmd |= RxVlan;
1491         else
1492                 tp->cp_cmd &= ~RxVlan;
1493
1494         RTL_W16(CPlusCmd, tp->cp_cmd);
1495         RTL_R16(CPlusCmd);
1496
1497         spin_unlock_irqrestore(&tp->lock, flags);
1498
1499         return 0;
1500 }
1501
1502 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1503                                       struct sk_buff *skb)
1504 {
1505         return (vlan_tx_tag_present(skb)) ?
1506                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1507 }
1508
1509 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1510 {
1511         u32 opts2 = le32_to_cpu(desc->opts2);
1512
1513         if (opts2 & RxVlanTag)
1514                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1515
1516         desc->opts2 = 0;
1517 }
1518
1519 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1520 {
1521         struct rtl8169_private *tp = netdev_priv(dev);
1522         void __iomem *ioaddr = tp->mmio_addr;
1523         u32 status;
1524
1525         cmd->supported =
1526                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1527         cmd->port = PORT_FIBRE;
1528         cmd->transceiver = XCVR_INTERNAL;
1529
1530         status = RTL_R32(TBICSR);
1531         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1532         cmd->autoneg = !!(status & TBINwEnable);
1533
1534         ethtool_cmd_speed_set(cmd, SPEED_1000);
1535         cmd->duplex = DUPLEX_FULL; /* Always set */
1536
1537         return 0;
1538 }
1539
1540 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1541 {
1542         struct rtl8169_private *tp = netdev_priv(dev);
1543
1544         return mii_ethtool_gset(&tp->mii, cmd);
1545 }
1546
1547 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1548 {
1549         struct rtl8169_private *tp = netdev_priv(dev);
1550         unsigned long flags;
1551         int rc;
1552
1553         spin_lock_irqsave(&tp->lock, flags);
1554
1555         rc = tp->get_settings(dev, cmd);
1556
1557         spin_unlock_irqrestore(&tp->lock, flags);
1558         return rc;
1559 }
1560
1561 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1562                              void *p)
1563 {
1564         struct rtl8169_private *tp = netdev_priv(dev);
1565         unsigned long flags;
1566
1567         if (regs->len > R8169_REGS_SIZE)
1568                 regs->len = R8169_REGS_SIZE;
1569
1570         spin_lock_irqsave(&tp->lock, flags);
1571         memcpy_fromio(p, tp->mmio_addr, regs->len);
1572         spin_unlock_irqrestore(&tp->lock, flags);
1573 }
1574
1575 static u32 rtl8169_get_msglevel(struct net_device *dev)
1576 {
1577         struct rtl8169_private *tp = netdev_priv(dev);
1578
1579         return tp->msg_enable;
1580 }
1581
1582 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1583 {
1584         struct rtl8169_private *tp = netdev_priv(dev);
1585
1586         tp->msg_enable = value;
1587 }
1588
1589 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1590         "tx_packets",
1591         "rx_packets",
1592         "tx_errors",
1593         "rx_errors",
1594         "rx_missed",
1595         "align_errors",
1596         "tx_single_collisions",
1597         "tx_multi_collisions",
1598         "unicast",
1599         "broadcast",
1600         "multicast",
1601         "tx_aborted",
1602         "tx_underrun",
1603 };
1604
1605 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1606 {
1607         switch (sset) {
1608         case ETH_SS_STATS:
1609                 return ARRAY_SIZE(rtl8169_gstrings);
1610         default:
1611                 return -EOPNOTSUPP;
1612         }
1613 }
1614
1615 static void rtl8169_update_counters(struct net_device *dev)
1616 {
1617         struct rtl8169_private *tp = netdev_priv(dev);
1618         void __iomem *ioaddr = tp->mmio_addr;
1619         struct device *d = &tp->pci_dev->dev;
1620         struct rtl8169_counters *counters;
1621         dma_addr_t paddr;
1622         u32 cmd;
1623         int wait = 1000;
1624
1625         /*
1626          * Some chips are unable to dump tally counters when the receiver
1627          * is disabled.
1628          */
1629         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1630                 return;
1631
1632         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1633         if (!counters)
1634                 return;
1635
1636         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1637         cmd = (u64)paddr & DMA_BIT_MASK(32);
1638         RTL_W32(CounterAddrLow, cmd);
1639         RTL_W32(CounterAddrLow, cmd | CounterDump);
1640
1641         while (wait--) {
1642                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1643                         memcpy(&tp->counters, counters, sizeof(*counters));
1644                         break;
1645                 }
1646                 udelay(10);
1647         }
1648
1649         RTL_W32(CounterAddrLow, 0);
1650         RTL_W32(CounterAddrHigh, 0);
1651
1652         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1653 }
1654
1655 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1656                                       struct ethtool_stats *stats, u64 *data)
1657 {
1658         struct rtl8169_private *tp = netdev_priv(dev);
1659
1660         ASSERT_RTNL();
1661
1662         rtl8169_update_counters(dev);
1663
1664         data[0] = le64_to_cpu(tp->counters.tx_packets);
1665         data[1] = le64_to_cpu(tp->counters.rx_packets);
1666         data[2] = le64_to_cpu(tp->counters.tx_errors);
1667         data[3] = le32_to_cpu(tp->counters.rx_errors);
1668         data[4] = le16_to_cpu(tp->counters.rx_missed);
1669         data[5] = le16_to_cpu(tp->counters.align_errors);
1670         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1671         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1672         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1673         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1674         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1675         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1676         data[12] = le16_to_cpu(tp->counters.tx_underun);
1677 }
1678
1679 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1680 {
1681         switch(stringset) {
1682         case ETH_SS_STATS:
1683                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1684                 break;
1685         }
1686 }
1687
1688 static const struct ethtool_ops rtl8169_ethtool_ops = {
1689         .get_drvinfo            = rtl8169_get_drvinfo,
1690         .get_regs_len           = rtl8169_get_regs_len,
1691         .get_link               = ethtool_op_get_link,
1692         .get_settings           = rtl8169_get_settings,
1693         .set_settings           = rtl8169_set_settings,
1694         .get_msglevel           = rtl8169_get_msglevel,
1695         .set_msglevel           = rtl8169_set_msglevel,
1696         .get_regs               = rtl8169_get_regs,
1697         .get_wol                = rtl8169_get_wol,
1698         .set_wol                = rtl8169_set_wol,
1699         .get_strings            = rtl8169_get_strings,
1700         .get_sset_count         = rtl8169_get_sset_count,
1701         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1702 };
1703
1704 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1705                                     struct net_device *dev, u8 default_version)
1706 {
1707         void __iomem *ioaddr = tp->mmio_addr;
1708         /*
1709          * The driver currently handles the 8168Bf and the 8168Be identically
1710          * but they can be identified more specifically through the test below
1711          * if needed:
1712          *
1713          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1714          *
1715          * Same thing for the 8101Eb and the 8101Ec:
1716          *
1717          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1718          */
1719         static const struct rtl_mac_info {
1720                 u32 mask;
1721                 u32 val;
1722                 int mac_version;
1723         } mac_info[] = {
1724                 /* 8168E family. */
1725                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
1726                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1727                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1728                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1729
1730                 /* 8168D family. */
1731                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1732                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1733                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1734
1735                 /* 8168DP family. */
1736                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1737                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1738                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1739
1740                 /* 8168C family. */
1741                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1742                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1743                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1744                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1745                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1746                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1747                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1748                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1749                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1750
1751                 /* 8168B family. */
1752                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1753                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1754                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1755                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1756
1757                 /* 8101 family. */
1758                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1759                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1760                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1761                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1762                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1763                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1764                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1765                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1766                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1767                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1768                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1769                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1770                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1771                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1772                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1773                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1774                 /* FIXME: where did these entries come from ? -- FR */
1775                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1776                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1777
1778                 /* 8110 family. */
1779                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1780                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1781                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1782                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1783                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1784                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1785
1786                 /* Catch-all */
1787                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1788         };
1789         const struct rtl_mac_info *p = mac_info;
1790         u32 reg;
1791
1792         reg = RTL_R32(TxConfig);
1793         while ((reg & p->mask) != p->val)
1794                 p++;
1795         tp->mac_version = p->mac_version;
1796
1797         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1798                 netif_notice(tp, probe, dev,
1799                              "unknown MAC, using family default\n");
1800                 tp->mac_version = default_version;
1801         }
1802 }
1803
1804 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1805 {
1806         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1807 }
1808
1809 struct phy_reg {
1810         u16 reg;
1811         u16 val;
1812 };
1813
1814 static void rtl_writephy_batch(struct rtl8169_private *tp,
1815                                const struct phy_reg *regs, int len)
1816 {
1817         while (len-- > 0) {
1818                 rtl_writephy(tp, regs->reg, regs->val);
1819                 regs++;
1820         }
1821 }
1822
1823 #define PHY_READ                0x00000000
1824 #define PHY_DATA_OR             0x10000000
1825 #define PHY_DATA_AND            0x20000000
1826 #define PHY_BJMPN               0x30000000
1827 #define PHY_READ_EFUSE          0x40000000
1828 #define PHY_READ_MAC_BYTE       0x50000000
1829 #define PHY_WRITE_MAC_BYTE      0x60000000
1830 #define PHY_CLEAR_READCOUNT     0x70000000
1831 #define PHY_WRITE               0x80000000
1832 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1833 #define PHY_COMP_EQ_SKIPN       0xa0000000
1834 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1835 #define PHY_WRITE_PREVIOUS      0xc0000000
1836 #define PHY_SKIPN               0xd0000000
1837 #define PHY_DELAY_MS            0xe0000000
1838 #define PHY_WRITE_ERI_WORD      0xf0000000
1839
1840 struct fw_info {
1841         u32     magic;
1842         char    version[RTL_VER_SIZE];
1843         __le32  fw_start;
1844         __le32  fw_len;
1845         u8      chksum;
1846 } __packed;
1847
1848 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1849
1850 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1851 {
1852         const struct firmware *fw = rtl_fw->fw;
1853         struct fw_info *fw_info = (struct fw_info *)fw->data;
1854         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1855         char *version = rtl_fw->version;
1856         bool rc = false;
1857
1858         if (fw->size < FW_OPCODE_SIZE)
1859                 goto out;
1860
1861         if (!fw_info->magic) {
1862                 size_t i, size, start;
1863                 u8 checksum = 0;
1864
1865                 if (fw->size < sizeof(*fw_info))
1866                         goto out;
1867
1868                 for (i = 0; i < fw->size; i++)
1869                         checksum += fw->data[i];
1870                 if (checksum != 0)
1871                         goto out;
1872
1873                 start = le32_to_cpu(fw_info->fw_start);
1874                 if (start > fw->size)
1875                         goto out;
1876
1877                 size = le32_to_cpu(fw_info->fw_len);
1878                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1879                         goto out;
1880
1881                 memcpy(version, fw_info->version, RTL_VER_SIZE);
1882
1883                 pa->code = (__le32 *)(fw->data + start);
1884                 pa->size = size;
1885         } else {
1886                 if (fw->size % FW_OPCODE_SIZE)
1887                         goto out;
1888
1889                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1890
1891                 pa->code = (__le32 *)fw->data;
1892                 pa->size = fw->size / FW_OPCODE_SIZE;
1893         }
1894         version[RTL_VER_SIZE - 1] = 0;
1895
1896         rc = true;
1897 out:
1898         return rc;
1899 }
1900
1901 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
1902                            struct rtl_fw_phy_action *pa)
1903 {
1904         bool rc = false;
1905         size_t index;
1906
1907         for (index = 0; index < pa->size; index++) {
1908                 u32 action = le32_to_cpu(pa->code[index]);
1909                 u32 regno = (action & 0x0fff0000) >> 16;
1910
1911                 switch(action & 0xf0000000) {
1912                 case PHY_READ:
1913                 case PHY_DATA_OR:
1914                 case PHY_DATA_AND:
1915                 case PHY_READ_EFUSE:
1916                 case PHY_CLEAR_READCOUNT:
1917                 case PHY_WRITE:
1918                 case PHY_WRITE_PREVIOUS:
1919                 case PHY_DELAY_MS:
1920                         break;
1921
1922                 case PHY_BJMPN:
1923                         if (regno > index) {
1924                                 netif_err(tp, ifup, tp->dev,
1925                                           "Out of range of firmware\n");
1926                                 goto out;
1927                         }
1928                         break;
1929                 case PHY_READCOUNT_EQ_SKIP:
1930                         if (index + 2 >= pa->size) {
1931                                 netif_err(tp, ifup, tp->dev,
1932                                           "Out of range of firmware\n");
1933                                 goto out;
1934                         }
1935                         break;
1936                 case PHY_COMP_EQ_SKIPN:
1937                 case PHY_COMP_NEQ_SKIPN:
1938                 case PHY_SKIPN:
1939                         if (index + 1 + regno >= pa->size) {
1940                                 netif_err(tp, ifup, tp->dev,
1941                                           "Out of range of firmware\n");
1942                                 goto out;
1943                         }
1944                         break;
1945
1946                 case PHY_READ_MAC_BYTE:
1947                 case PHY_WRITE_MAC_BYTE:
1948                 case PHY_WRITE_ERI_WORD:
1949                 default:
1950                         netif_err(tp, ifup, tp->dev,
1951                                   "Invalid action 0x%08x\n", action);
1952                         goto out;
1953                 }
1954         }
1955         rc = true;
1956 out:
1957         return rc;
1958 }
1959
1960 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1961 {
1962         struct net_device *dev = tp->dev;
1963         int rc = -EINVAL;
1964
1965         if (!rtl_fw_format_ok(tp, rtl_fw)) {
1966                 netif_err(tp, ifup, dev, "invalid firwmare\n");
1967                 goto out;
1968         }
1969
1970         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
1971                 rc = 0;
1972 out:
1973         return rc;
1974 }
1975
1976 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1977 {
1978         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1979         u32 predata, count;
1980         size_t index;
1981
1982         predata = count = 0;
1983
1984         for (index = 0; index < pa->size; ) {
1985                 u32 action = le32_to_cpu(pa->code[index]);
1986                 u32 data = action & 0x0000ffff;
1987                 u32 regno = (action & 0x0fff0000) >> 16;
1988
1989                 if (!action)
1990                         break;
1991
1992                 switch(action & 0xf0000000) {
1993                 case PHY_READ:
1994                         predata = rtl_readphy(tp, regno);
1995                         count++;
1996                         index++;
1997                         break;
1998                 case PHY_DATA_OR:
1999                         predata |= data;
2000                         index++;
2001                         break;
2002                 case PHY_DATA_AND:
2003                         predata &= data;
2004                         index++;
2005                         break;
2006                 case PHY_BJMPN:
2007                         index -= regno;
2008                         break;
2009                 case PHY_READ_EFUSE:
2010                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2011                         index++;
2012                         break;
2013                 case PHY_CLEAR_READCOUNT:
2014                         count = 0;
2015                         index++;
2016                         break;
2017                 case PHY_WRITE:
2018                         rtl_writephy(tp, regno, data);
2019                         index++;
2020                         break;
2021                 case PHY_READCOUNT_EQ_SKIP:
2022                         index += (count == data) ? 2 : 1;
2023                         break;
2024                 case PHY_COMP_EQ_SKIPN:
2025                         if (predata == data)
2026                                 index += regno;
2027                         index++;
2028                         break;
2029                 case PHY_COMP_NEQ_SKIPN:
2030                         if (predata != data)
2031                                 index += regno;
2032                         index++;
2033                         break;
2034                 case PHY_WRITE_PREVIOUS:
2035                         rtl_writephy(tp, regno, predata);
2036                         index++;
2037                         break;
2038                 case PHY_SKIPN:
2039                         index += regno + 1;
2040                         break;
2041                 case PHY_DELAY_MS:
2042                         mdelay(data);
2043                         index++;
2044                         break;
2045
2046                 case PHY_READ_MAC_BYTE:
2047                 case PHY_WRITE_MAC_BYTE:
2048                 case PHY_WRITE_ERI_WORD:
2049                 default:
2050                         BUG();
2051                 }
2052         }
2053 }
2054
2055 static void rtl_release_firmware(struct rtl8169_private *tp)
2056 {
2057         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2058                 release_firmware(tp->rtl_fw->fw);
2059                 kfree(tp->rtl_fw);
2060         }
2061         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2062 }
2063
2064 static void rtl_apply_firmware(struct rtl8169_private *tp)
2065 {
2066         struct rtl_fw *rtl_fw = tp->rtl_fw;
2067
2068         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2069         if (!IS_ERR_OR_NULL(rtl_fw))
2070                 rtl_phy_write_fw(tp, rtl_fw);
2071 }
2072
2073 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2074 {
2075         if (rtl_readphy(tp, reg) != val)
2076                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2077         else
2078                 rtl_apply_firmware(tp);
2079 }
2080
2081 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2082 {
2083         static const struct phy_reg phy_reg_init[] = {
2084                 { 0x1f, 0x0001 },
2085                 { 0x06, 0x006e },
2086                 { 0x08, 0x0708 },
2087                 { 0x15, 0x4000 },
2088                 { 0x18, 0x65c7 },
2089
2090                 { 0x1f, 0x0001 },
2091                 { 0x03, 0x00a1 },
2092                 { 0x02, 0x0008 },
2093                 { 0x01, 0x0120 },
2094                 { 0x00, 0x1000 },
2095                 { 0x04, 0x0800 },
2096                 { 0x04, 0x0000 },
2097
2098                 { 0x03, 0xff41 },
2099                 { 0x02, 0xdf60 },
2100                 { 0x01, 0x0140 },
2101                 { 0x00, 0x0077 },
2102                 { 0x04, 0x7800 },
2103                 { 0x04, 0x7000 },
2104
2105                 { 0x03, 0x802f },
2106                 { 0x02, 0x4f02 },
2107                 { 0x01, 0x0409 },
2108                 { 0x00, 0xf0f9 },
2109                 { 0x04, 0x9800 },
2110                 { 0x04, 0x9000 },
2111
2112                 { 0x03, 0xdf01 },
2113                 { 0x02, 0xdf20 },
2114                 { 0x01, 0xff95 },
2115                 { 0x00, 0xba00 },
2116                 { 0x04, 0xa800 },
2117                 { 0x04, 0xa000 },
2118
2119                 { 0x03, 0xff41 },
2120                 { 0x02, 0xdf20 },
2121                 { 0x01, 0x0140 },
2122                 { 0x00, 0x00bb },
2123                 { 0x04, 0xb800 },
2124                 { 0x04, 0xb000 },
2125
2126                 { 0x03, 0xdf41 },
2127                 { 0x02, 0xdc60 },
2128                 { 0x01, 0x6340 },
2129                 { 0x00, 0x007d },
2130                 { 0x04, 0xd800 },
2131                 { 0x04, 0xd000 },
2132
2133                 { 0x03, 0xdf01 },
2134                 { 0x02, 0xdf20 },
2135                 { 0x01, 0x100a },
2136                 { 0x00, 0xa0ff },
2137                 { 0x04, 0xf800 },
2138                 { 0x04, 0xf000 },
2139
2140                 { 0x1f, 0x0000 },
2141                 { 0x0b, 0x0000 },
2142                 { 0x00, 0x9200 }
2143         };
2144
2145         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2146 }
2147
2148 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2149 {
2150         static const struct phy_reg phy_reg_init[] = {
2151                 { 0x1f, 0x0002 },
2152                 { 0x01, 0x90d0 },
2153                 { 0x1f, 0x0000 }
2154         };
2155
2156         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2157 }
2158
2159 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2160 {
2161         struct pci_dev *pdev = tp->pci_dev;
2162         u16 vendor_id, device_id;
2163
2164         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
2165         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
2166
2167         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
2168                 return;
2169
2170         rtl_writephy(tp, 0x1f, 0x0001);
2171         rtl_writephy(tp, 0x10, 0xf01b);
2172         rtl_writephy(tp, 0x1f, 0x0000);
2173 }
2174
2175 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2176 {
2177         static const struct phy_reg phy_reg_init[] = {
2178                 { 0x1f, 0x0001 },
2179                 { 0x04, 0x0000 },
2180                 { 0x03, 0x00a1 },
2181                 { 0x02, 0x0008 },
2182                 { 0x01, 0x0120 },
2183                 { 0x00, 0x1000 },
2184                 { 0x04, 0x0800 },
2185                 { 0x04, 0x9000 },
2186                 { 0x03, 0x802f },
2187                 { 0x02, 0x4f02 },
2188                 { 0x01, 0x0409 },
2189                 { 0x00, 0xf099 },
2190                 { 0x04, 0x9800 },
2191                 { 0x04, 0xa000 },
2192                 { 0x03, 0xdf01 },
2193                 { 0x02, 0xdf20 },
2194                 { 0x01, 0xff95 },
2195                 { 0x00, 0xba00 },
2196                 { 0x04, 0xa800 },
2197                 { 0x04, 0xf000 },
2198                 { 0x03, 0xdf01 },
2199                 { 0x02, 0xdf20 },
2200                 { 0x01, 0x101a },
2201                 { 0x00, 0xa0ff },
2202                 { 0x04, 0xf800 },
2203                 { 0x04, 0x0000 },
2204                 { 0x1f, 0x0000 },
2205
2206                 { 0x1f, 0x0001 },
2207                 { 0x10, 0xf41b },
2208                 { 0x14, 0xfb54 },
2209                 { 0x18, 0xf5c7 },
2210                 { 0x1f, 0x0000 },
2211
2212                 { 0x1f, 0x0001 },
2213                 { 0x17, 0x0cc0 },
2214                 { 0x1f, 0x0000 }
2215         };
2216
2217         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2218
2219         rtl8169scd_hw_phy_config_quirk(tp);
2220 }
2221
2222 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2223 {
2224         static const struct phy_reg phy_reg_init[] = {
2225                 { 0x1f, 0x0001 },
2226                 { 0x04, 0x0000 },
2227                 { 0x03, 0x00a1 },
2228                 { 0x02, 0x0008 },
2229                 { 0x01, 0x0120 },
2230                 { 0x00, 0x1000 },
2231                 { 0x04, 0x0800 },
2232                 { 0x04, 0x9000 },
2233                 { 0x03, 0x802f },
2234                 { 0x02, 0x4f02 },
2235                 { 0x01, 0x0409 },
2236                 { 0x00, 0xf099 },
2237                 { 0x04, 0x9800 },
2238                 { 0x04, 0xa000 },
2239                 { 0x03, 0xdf01 },
2240                 { 0x02, 0xdf20 },
2241                 { 0x01, 0xff95 },
2242                 { 0x00, 0xba00 },
2243                 { 0x04, 0xa800 },
2244                 { 0x04, 0xf000 },
2245                 { 0x03, 0xdf01 },
2246                 { 0x02, 0xdf20 },
2247                 { 0x01, 0x101a },
2248                 { 0x00, 0xa0ff },
2249                 { 0x04, 0xf800 },
2250                 { 0x04, 0x0000 },
2251                 { 0x1f, 0x0000 },
2252
2253                 { 0x1f, 0x0001 },
2254                 { 0x0b, 0x8480 },
2255                 { 0x1f, 0x0000 },
2256
2257                 { 0x1f, 0x0001 },
2258                 { 0x18, 0x67c7 },
2259                 { 0x04, 0x2000 },
2260                 { 0x03, 0x002f },
2261                 { 0x02, 0x4360 },
2262                 { 0x01, 0x0109 },
2263                 { 0x00, 0x3022 },
2264                 { 0x04, 0x2800 },
2265                 { 0x1f, 0x0000 },
2266
2267                 { 0x1f, 0x0001 },
2268                 { 0x17, 0x0cc0 },
2269                 { 0x1f, 0x0000 }
2270         };
2271
2272         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2273 }
2274
2275 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2276 {
2277         static const struct phy_reg phy_reg_init[] = {
2278                 { 0x10, 0xf41b },
2279                 { 0x1f, 0x0000 }
2280         };
2281
2282         rtl_writephy(tp, 0x1f, 0x0001);
2283         rtl_patchphy(tp, 0x16, 1 << 0);
2284
2285         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2286 }
2287
2288 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2289 {
2290         static const struct phy_reg phy_reg_init[] = {
2291                 { 0x1f, 0x0001 },
2292                 { 0x10, 0xf41b },
2293                 { 0x1f, 0x0000 }
2294         };
2295
2296         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2297 }
2298
2299 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2300 {
2301         static const struct phy_reg phy_reg_init[] = {
2302                 { 0x1f, 0x0000 },
2303                 { 0x1d, 0x0f00 },
2304                 { 0x1f, 0x0002 },
2305                 { 0x0c, 0x1ec8 },
2306                 { 0x1f, 0x0000 }
2307         };
2308
2309         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2310 }
2311
2312 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2313 {
2314         static const struct phy_reg phy_reg_init[] = {
2315                 { 0x1f, 0x0001 },
2316                 { 0x1d, 0x3d98 },
2317                 { 0x1f, 0x0000 }
2318         };
2319
2320         rtl_writephy(tp, 0x1f, 0x0000);
2321         rtl_patchphy(tp, 0x14, 1 << 5);
2322         rtl_patchphy(tp, 0x0d, 1 << 5);
2323
2324         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2325 }
2326
2327 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2328 {
2329         static const struct phy_reg phy_reg_init[] = {
2330                 { 0x1f, 0x0001 },
2331                 { 0x12, 0x2300 },
2332                 { 0x1f, 0x0002 },
2333                 { 0x00, 0x88d4 },
2334                 { 0x01, 0x82b1 },
2335                 { 0x03, 0x7002 },
2336                 { 0x08, 0x9e30 },
2337                 { 0x09, 0x01f0 },
2338                 { 0x0a, 0x5500 },
2339                 { 0x0c, 0x00c8 },
2340                 { 0x1f, 0x0003 },
2341                 { 0x12, 0xc096 },
2342                 { 0x16, 0x000a },
2343                 { 0x1f, 0x0000 },
2344                 { 0x1f, 0x0000 },
2345                 { 0x09, 0x2000 },
2346                 { 0x09, 0x0000 }
2347         };
2348
2349         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2350
2351         rtl_patchphy(tp, 0x14, 1 << 5);
2352         rtl_patchphy(tp, 0x0d, 1 << 5);
2353         rtl_writephy(tp, 0x1f, 0x0000);
2354 }
2355
2356 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2357 {
2358         static const struct phy_reg phy_reg_init[] = {
2359                 { 0x1f, 0x0001 },
2360                 { 0x12, 0x2300 },
2361                 { 0x03, 0x802f },
2362                 { 0x02, 0x4f02 },
2363                 { 0x01, 0x0409 },
2364                 { 0x00, 0xf099 },
2365                 { 0x04, 0x9800 },
2366                 { 0x04, 0x9000 },
2367                 { 0x1d, 0x3d98 },
2368                 { 0x1f, 0x0002 },
2369                 { 0x0c, 0x7eb8 },
2370                 { 0x06, 0x0761 },
2371                 { 0x1f, 0x0003 },
2372                 { 0x16, 0x0f0a },
2373                 { 0x1f, 0x0000 }
2374         };
2375
2376         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2377
2378         rtl_patchphy(tp, 0x16, 1 << 0);
2379         rtl_patchphy(tp, 0x14, 1 << 5);
2380         rtl_patchphy(tp, 0x0d, 1 << 5);
2381         rtl_writephy(tp, 0x1f, 0x0000);
2382 }
2383
2384 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2385 {
2386         static const struct phy_reg phy_reg_init[] = {
2387                 { 0x1f, 0x0001 },
2388                 { 0x12, 0x2300 },
2389                 { 0x1d, 0x3d98 },
2390                 { 0x1f, 0x0002 },
2391                 { 0x0c, 0x7eb8 },
2392                 { 0x06, 0x5461 },
2393                 { 0x1f, 0x0003 },
2394                 { 0x16, 0x0f0a },
2395                 { 0x1f, 0x0000 }
2396         };
2397
2398         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2399
2400         rtl_patchphy(tp, 0x16, 1 << 0);
2401         rtl_patchphy(tp, 0x14, 1 << 5);
2402         rtl_patchphy(tp, 0x0d, 1 << 5);
2403         rtl_writephy(tp, 0x1f, 0x0000);
2404 }
2405
2406 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2407 {
2408         rtl8168c_3_hw_phy_config(tp);
2409 }
2410
2411 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2412 {
2413         static const struct phy_reg phy_reg_init_0[] = {
2414                 /* Channel Estimation */
2415                 { 0x1f, 0x0001 },
2416                 { 0x06, 0x4064 },
2417                 { 0x07, 0x2863 },
2418                 { 0x08, 0x059c },
2419                 { 0x09, 0x26b4 },
2420                 { 0x0a, 0x6a19 },
2421                 { 0x0b, 0xdcc8 },
2422                 { 0x10, 0xf06d },
2423                 { 0x14, 0x7f68 },
2424                 { 0x18, 0x7fd9 },
2425                 { 0x1c, 0xf0ff },
2426                 { 0x1d, 0x3d9c },
2427                 { 0x1f, 0x0003 },
2428                 { 0x12, 0xf49f },
2429                 { 0x13, 0x070b },
2430                 { 0x1a, 0x05ad },
2431                 { 0x14, 0x94c0 },
2432
2433                 /*
2434                  * Tx Error Issue
2435                  * Enhance line driver power
2436                  */
2437                 { 0x1f, 0x0002 },
2438                 { 0x06, 0x5561 },
2439                 { 0x1f, 0x0005 },
2440                 { 0x05, 0x8332 },
2441                 { 0x06, 0x5561 },
2442
2443                 /*
2444                  * Can not link to 1Gbps with bad cable
2445                  * Decrease SNR threshold form 21.07dB to 19.04dB
2446                  */
2447                 { 0x1f, 0x0001 },
2448                 { 0x17, 0x0cc0 },
2449
2450                 { 0x1f, 0x0000 },
2451                 { 0x0d, 0xf880 }
2452         };
2453         void __iomem *ioaddr = tp->mmio_addr;
2454
2455         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2456
2457         /*
2458          * Rx Error Issue
2459          * Fine Tune Switching regulator parameter
2460          */
2461         rtl_writephy(tp, 0x1f, 0x0002);
2462         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2463         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2464
2465         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2466                 static const struct phy_reg phy_reg_init[] = {
2467                         { 0x1f, 0x0002 },
2468                         { 0x05, 0x669a },
2469                         { 0x1f, 0x0005 },
2470                         { 0x05, 0x8330 },
2471                         { 0x06, 0x669a },
2472                         { 0x1f, 0x0002 }
2473                 };
2474                 int val;
2475
2476                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2477
2478                 val = rtl_readphy(tp, 0x0d);
2479
2480                 if ((val & 0x00ff) != 0x006c) {
2481                         static const u32 set[] = {
2482                                 0x0065, 0x0066, 0x0067, 0x0068,
2483                                 0x0069, 0x006a, 0x006b, 0x006c
2484                         };
2485                         int i;
2486
2487                         rtl_writephy(tp, 0x1f, 0x0002);
2488
2489                         val &= 0xff00;
2490                         for (i = 0; i < ARRAY_SIZE(set); i++)
2491                                 rtl_writephy(tp, 0x0d, val | set[i]);
2492                 }
2493         } else {
2494                 static const struct phy_reg phy_reg_init[] = {
2495                         { 0x1f, 0x0002 },
2496                         { 0x05, 0x6662 },
2497                         { 0x1f, 0x0005 },
2498                         { 0x05, 0x8330 },
2499                         { 0x06, 0x6662 }
2500                 };
2501
2502                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2503         }
2504
2505         /* RSET couple improve */
2506         rtl_writephy(tp, 0x1f, 0x0002);
2507         rtl_patchphy(tp, 0x0d, 0x0300);
2508         rtl_patchphy(tp, 0x0f, 0x0010);
2509
2510         /* Fine tune PLL performance */
2511         rtl_writephy(tp, 0x1f, 0x0002);
2512         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2513         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2514
2515         rtl_writephy(tp, 0x1f, 0x0005);
2516         rtl_writephy(tp, 0x05, 0x001b);
2517
2518         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2519
2520         rtl_writephy(tp, 0x1f, 0x0000);
2521 }
2522
2523 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2524 {
2525         static const struct phy_reg phy_reg_init_0[] = {
2526                 /* Channel Estimation */
2527                 { 0x1f, 0x0001 },
2528                 { 0x06, 0x4064 },
2529                 { 0x07, 0x2863 },
2530                 { 0x08, 0x059c },
2531                 { 0x09, 0x26b4 },
2532                 { 0x0a, 0x6a19 },
2533                 { 0x0b, 0xdcc8 },
2534                 { 0x10, 0xf06d },
2535                 { 0x14, 0x7f68 },
2536                 { 0x18, 0x7fd9 },
2537                 { 0x1c, 0xf0ff },
2538                 { 0x1d, 0x3d9c },
2539                 { 0x1f, 0x0003 },
2540                 { 0x12, 0xf49f },
2541                 { 0x13, 0x070b },
2542                 { 0x1a, 0x05ad },
2543                 { 0x14, 0x94c0 },
2544
2545                 /*
2546                  * Tx Error Issue
2547                  * Enhance line driver power
2548                  */
2549                 { 0x1f, 0x0002 },
2550                 { 0x06, 0x5561 },
2551                 { 0x1f, 0x0005 },
2552                 { 0x05, 0x8332 },
2553                 { 0x06, 0x5561 },
2554
2555                 /*
2556                  * Can not link to 1Gbps with bad cable
2557                  * Decrease SNR threshold form 21.07dB to 19.04dB
2558                  */
2559                 { 0x1f, 0x0001 },
2560                 { 0x17, 0x0cc0 },
2561
2562                 { 0x1f, 0x0000 },
2563                 { 0x0d, 0xf880 }
2564         };
2565         void __iomem *ioaddr = tp->mmio_addr;
2566
2567         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2568
2569         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2570                 static const struct phy_reg phy_reg_init[] = {
2571                         { 0x1f, 0x0002 },
2572                         { 0x05, 0x669a },
2573                         { 0x1f, 0x0005 },
2574                         { 0x05, 0x8330 },
2575                         { 0x06, 0x669a },
2576
2577                         { 0x1f, 0x0002 }
2578                 };
2579                 int val;
2580
2581                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2582
2583                 val = rtl_readphy(tp, 0x0d);
2584                 if ((val & 0x00ff) != 0x006c) {
2585                         static const u32 set[] = {
2586                                 0x0065, 0x0066, 0x0067, 0x0068,
2587                                 0x0069, 0x006a, 0x006b, 0x006c
2588                         };
2589                         int i;
2590
2591                         rtl_writephy(tp, 0x1f, 0x0002);
2592
2593                         val &= 0xff00;
2594                         for (i = 0; i < ARRAY_SIZE(set); i++)
2595                                 rtl_writephy(tp, 0x0d, val | set[i]);
2596                 }
2597         } else {
2598                 static const struct phy_reg phy_reg_init[] = {
2599                         { 0x1f, 0x0002 },
2600                         { 0x05, 0x2642 },
2601                         { 0x1f, 0x0005 },
2602                         { 0x05, 0x8330 },
2603                         { 0x06, 0x2642 }
2604                 };
2605
2606                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2607         }
2608
2609         /* Fine tune PLL performance */
2610         rtl_writephy(tp, 0x1f, 0x0002);
2611         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2612         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2613
2614         /* Switching regulator Slew rate */
2615         rtl_writephy(tp, 0x1f, 0x0002);
2616         rtl_patchphy(tp, 0x0f, 0x0017);
2617
2618         rtl_writephy(tp, 0x1f, 0x0005);
2619         rtl_writephy(tp, 0x05, 0x001b);
2620
2621         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2622
2623         rtl_writephy(tp, 0x1f, 0x0000);
2624 }
2625
2626 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2627 {
2628         static const struct phy_reg phy_reg_init[] = {
2629                 { 0x1f, 0x0002 },
2630                 { 0x10, 0x0008 },
2631                 { 0x0d, 0x006c },
2632
2633                 { 0x1f, 0x0000 },
2634                 { 0x0d, 0xf880 },
2635
2636                 { 0x1f, 0x0001 },
2637                 { 0x17, 0x0cc0 },
2638
2639                 { 0x1f, 0x0001 },
2640                 { 0x0b, 0xa4d8 },
2641                 { 0x09, 0x281c },
2642                 { 0x07, 0x2883 },
2643                 { 0x0a, 0x6b35 },
2644                 { 0x1d, 0x3da4 },
2645                 { 0x1c, 0xeffd },
2646                 { 0x14, 0x7f52 },
2647                 { 0x18, 0x7fc6 },
2648                 { 0x08, 0x0601 },
2649                 { 0x06, 0x4063 },
2650                 { 0x10, 0xf074 },
2651                 { 0x1f, 0x0003 },
2652                 { 0x13, 0x0789 },
2653                 { 0x12, 0xf4bd },
2654                 { 0x1a, 0x04fd },
2655                 { 0x14, 0x84b0 },
2656                 { 0x1f, 0x0000 },
2657                 { 0x00, 0x9200 },
2658
2659                 { 0x1f, 0x0005 },
2660                 { 0x01, 0x0340 },
2661                 { 0x1f, 0x0001 },
2662                 { 0x04, 0x4000 },
2663                 { 0x03, 0x1d21 },
2664                 { 0x02, 0x0c32 },
2665                 { 0x01, 0x0200 },
2666                 { 0x00, 0x5554 },
2667                 { 0x04, 0x4800 },
2668                 { 0x04, 0x4000 },
2669                 { 0x04, 0xf000 },
2670                 { 0x03, 0xdf01 },
2671                 { 0x02, 0xdf20 },
2672                 { 0x01, 0x101a },
2673                 { 0x00, 0xa0ff },
2674                 { 0x04, 0xf800 },
2675                 { 0x04, 0xf000 },
2676                 { 0x1f, 0x0000 },
2677
2678                 { 0x1f, 0x0007 },
2679                 { 0x1e, 0x0023 },
2680                 { 0x16, 0x0000 },
2681                 { 0x1f, 0x0000 }
2682         };
2683
2684         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2685 }
2686
2687 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2688 {
2689         static const struct phy_reg phy_reg_init[] = {
2690                 { 0x1f, 0x0001 },
2691                 { 0x17, 0x0cc0 },
2692
2693                 { 0x1f, 0x0007 },
2694                 { 0x1e, 0x002d },
2695                 { 0x18, 0x0040 },
2696                 { 0x1f, 0x0000 }
2697         };
2698
2699         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2700         rtl_patchphy(tp, 0x0d, 1 << 5);
2701 }
2702
2703 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2704 {
2705         static const struct phy_reg phy_reg_init[] = {
2706                 /* Enable Delay cap */
2707                 { 0x1f, 0x0005 },
2708                 { 0x05, 0x8b80 },
2709                 { 0x06, 0xc896 },
2710                 { 0x1f, 0x0000 },
2711
2712                 /* Channel estimation fine tune */
2713                 { 0x1f, 0x0001 },
2714                 { 0x0b, 0x6c20 },
2715                 { 0x07, 0x2872 },
2716                 { 0x1c, 0xefff },
2717                 { 0x1f, 0x0003 },
2718                 { 0x14, 0x6420 },
2719                 { 0x1f, 0x0000 },
2720
2721                 /* Update PFM & 10M TX idle timer */
2722                 { 0x1f, 0x0007 },
2723                 { 0x1e, 0x002f },
2724                 { 0x15, 0x1919 },
2725                 { 0x1f, 0x0000 },
2726
2727                 { 0x1f, 0x0007 },
2728                 { 0x1e, 0x00ac },
2729                 { 0x18, 0x0006 },
2730                 { 0x1f, 0x0000 }
2731         };
2732
2733         rtl_apply_firmware(tp);
2734
2735         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2736
2737         /* DCO enable for 10M IDLE Power */
2738         rtl_writephy(tp, 0x1f, 0x0007);
2739         rtl_writephy(tp, 0x1e, 0x0023);
2740         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2741         rtl_writephy(tp, 0x1f, 0x0000);
2742
2743         /* For impedance matching */
2744         rtl_writephy(tp, 0x1f, 0x0002);
2745         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2746         rtl_writephy(tp, 0x1f, 0x0000);
2747
2748         /* PHY auto speed down */
2749         rtl_writephy(tp, 0x1f, 0x0007);
2750         rtl_writephy(tp, 0x1e, 0x002d);
2751         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2752         rtl_writephy(tp, 0x1f, 0x0000);
2753         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2754
2755         rtl_writephy(tp, 0x1f, 0x0005);
2756         rtl_writephy(tp, 0x05, 0x8b86);
2757         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2758         rtl_writephy(tp, 0x1f, 0x0000);
2759
2760         rtl_writephy(tp, 0x1f, 0x0005);
2761         rtl_writephy(tp, 0x05, 0x8b85);
2762         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2763         rtl_writephy(tp, 0x1f, 0x0007);
2764         rtl_writephy(tp, 0x1e, 0x0020);
2765         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2766         rtl_writephy(tp, 0x1f, 0x0006);
2767         rtl_writephy(tp, 0x00, 0x5a00);
2768         rtl_writephy(tp, 0x1f, 0x0000);
2769         rtl_writephy(tp, 0x0d, 0x0007);
2770         rtl_writephy(tp, 0x0e, 0x003c);
2771         rtl_writephy(tp, 0x0d, 0x4007);
2772         rtl_writephy(tp, 0x0e, 0x0000);
2773         rtl_writephy(tp, 0x0d, 0x0000);
2774 }
2775
2776 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2777 {
2778         static const struct phy_reg phy_reg_init[] = {
2779                 /* Enable Delay cap */
2780                 { 0x1f, 0x0004 },
2781                 { 0x1f, 0x0007 },
2782                 { 0x1e, 0x00ac },
2783                 { 0x18, 0x0006 },
2784                 { 0x1f, 0x0002 },
2785                 { 0x1f, 0x0000 },
2786                 { 0x1f, 0x0000 },
2787
2788                 /* Channel estimation fine tune */
2789                 { 0x1f, 0x0003 },
2790                 { 0x09, 0xa20f },
2791                 { 0x1f, 0x0000 },
2792                 { 0x1f, 0x0000 },
2793
2794                 /* Green Setting */
2795                 { 0x1f, 0x0005 },
2796                 { 0x05, 0x8b5b },
2797                 { 0x06, 0x9222 },
2798                 { 0x05, 0x8b6d },
2799                 { 0x06, 0x8000 },
2800                 { 0x05, 0x8b76 },
2801                 { 0x06, 0x8000 },
2802                 { 0x1f, 0x0000 }
2803         };
2804
2805         rtl_apply_firmware(tp);
2806
2807         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2808
2809         /* For 4-corner performance improve */
2810         rtl_writephy(tp, 0x1f, 0x0005);
2811         rtl_writephy(tp, 0x05, 0x8b80);
2812         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2813         rtl_writephy(tp, 0x1f, 0x0000);
2814
2815         /* PHY auto speed down */
2816         rtl_writephy(tp, 0x1f, 0x0004);
2817         rtl_writephy(tp, 0x1f, 0x0007);
2818         rtl_writephy(tp, 0x1e, 0x002d);
2819         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2820         rtl_writephy(tp, 0x1f, 0x0002);
2821         rtl_writephy(tp, 0x1f, 0x0000);
2822         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2823
2824         /* improve 10M EEE waveform */
2825         rtl_writephy(tp, 0x1f, 0x0005);
2826         rtl_writephy(tp, 0x05, 0x8b86);
2827         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2828         rtl_writephy(tp, 0x1f, 0x0000);
2829
2830         /* Improve 2-pair detection performance */
2831         rtl_writephy(tp, 0x1f, 0x0005);
2832         rtl_writephy(tp, 0x05, 0x8b85);
2833         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2834         rtl_writephy(tp, 0x1f, 0x0000);
2835
2836         /* EEE setting */
2837         rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2838                      ERIAR_EXGMAC);
2839         rtl_writephy(tp, 0x1f, 0x0005);
2840         rtl_writephy(tp, 0x05, 0x8b85);
2841         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2842         rtl_writephy(tp, 0x1f, 0x0004);
2843         rtl_writephy(tp, 0x1f, 0x0007);
2844         rtl_writephy(tp, 0x1e, 0x0020);
2845         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
2846         rtl_writephy(tp, 0x1f, 0x0002);
2847         rtl_writephy(tp, 0x1f, 0x0000);
2848         rtl_writephy(tp, 0x0d, 0x0007);
2849         rtl_writephy(tp, 0x0e, 0x003c);
2850         rtl_writephy(tp, 0x0d, 0x4007);
2851         rtl_writephy(tp, 0x0e, 0x0000);
2852         rtl_writephy(tp, 0x0d, 0x0000);
2853
2854         /* Green feature */
2855         rtl_writephy(tp, 0x1f, 0x0003);
2856         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
2857         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
2858         rtl_writephy(tp, 0x1f, 0x0000);
2859 }
2860
2861 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2862 {
2863         static const struct phy_reg phy_reg_init[] = {
2864                 { 0x1f, 0x0003 },
2865                 { 0x08, 0x441d },
2866                 { 0x01, 0x9100 },
2867                 { 0x1f, 0x0000 }
2868         };
2869
2870         rtl_writephy(tp, 0x1f, 0x0000);
2871         rtl_patchphy(tp, 0x11, 1 << 12);
2872         rtl_patchphy(tp, 0x19, 1 << 13);
2873         rtl_patchphy(tp, 0x10, 1 << 15);
2874
2875         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2876 }
2877
2878 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2879 {
2880         static const struct phy_reg phy_reg_init[] = {
2881                 { 0x1f, 0x0005 },
2882                 { 0x1a, 0x0000 },
2883                 { 0x1f, 0x0000 },
2884
2885                 { 0x1f, 0x0004 },
2886                 { 0x1c, 0x0000 },
2887                 { 0x1f, 0x0000 },
2888
2889                 { 0x1f, 0x0001 },
2890                 { 0x15, 0x7701 },
2891                 { 0x1f, 0x0000 }
2892         };
2893
2894         /* Disable ALDPS before ram code */
2895         rtl_writephy(tp, 0x1f, 0x0000);
2896         rtl_writephy(tp, 0x18, 0x0310);
2897         msleep(100);
2898
2899         rtl_apply_firmware(tp);
2900
2901         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2902 }
2903
2904 static void rtl_hw_phy_config(struct net_device *dev)
2905 {
2906         struct rtl8169_private *tp = netdev_priv(dev);
2907
2908         rtl8169_print_mac_version(tp);
2909
2910         switch (tp->mac_version) {
2911         case RTL_GIGA_MAC_VER_01:
2912                 break;
2913         case RTL_GIGA_MAC_VER_02:
2914         case RTL_GIGA_MAC_VER_03:
2915                 rtl8169s_hw_phy_config(tp);
2916                 break;
2917         case RTL_GIGA_MAC_VER_04:
2918                 rtl8169sb_hw_phy_config(tp);
2919                 break;
2920         case RTL_GIGA_MAC_VER_05:
2921                 rtl8169scd_hw_phy_config(tp);
2922                 break;
2923         case RTL_GIGA_MAC_VER_06:
2924                 rtl8169sce_hw_phy_config(tp);
2925                 break;
2926         case RTL_GIGA_MAC_VER_07:
2927         case RTL_GIGA_MAC_VER_08:
2928         case RTL_GIGA_MAC_VER_09:
2929                 rtl8102e_hw_phy_config(tp);
2930                 break;
2931         case RTL_GIGA_MAC_VER_11:
2932                 rtl8168bb_hw_phy_config(tp);
2933                 break;
2934         case RTL_GIGA_MAC_VER_12:
2935                 rtl8168bef_hw_phy_config(tp);
2936                 break;
2937         case RTL_GIGA_MAC_VER_17:
2938                 rtl8168bef_hw_phy_config(tp);
2939                 break;
2940         case RTL_GIGA_MAC_VER_18:
2941                 rtl8168cp_1_hw_phy_config(tp);
2942                 break;
2943         case RTL_GIGA_MAC_VER_19:
2944                 rtl8168c_1_hw_phy_config(tp);
2945                 break;
2946         case RTL_GIGA_MAC_VER_20:
2947                 rtl8168c_2_hw_phy_config(tp);
2948                 break;
2949         case RTL_GIGA_MAC_VER_21:
2950                 rtl8168c_3_hw_phy_config(tp);
2951                 break;
2952         case RTL_GIGA_MAC_VER_22:
2953                 rtl8168c_4_hw_phy_config(tp);
2954                 break;
2955         case RTL_GIGA_MAC_VER_23:
2956         case RTL_GIGA_MAC_VER_24:
2957                 rtl8168cp_2_hw_phy_config(tp);
2958                 break;
2959         case RTL_GIGA_MAC_VER_25:
2960                 rtl8168d_1_hw_phy_config(tp);
2961                 break;
2962         case RTL_GIGA_MAC_VER_26:
2963                 rtl8168d_2_hw_phy_config(tp);
2964                 break;
2965         case RTL_GIGA_MAC_VER_27:
2966                 rtl8168d_3_hw_phy_config(tp);
2967                 break;
2968         case RTL_GIGA_MAC_VER_28:
2969                 rtl8168d_4_hw_phy_config(tp);
2970                 break;
2971         case RTL_GIGA_MAC_VER_29:
2972         case RTL_GIGA_MAC_VER_30:
2973                 rtl8105e_hw_phy_config(tp);
2974                 break;
2975         case RTL_GIGA_MAC_VER_31:
2976                 /* None. */
2977                 break;
2978         case RTL_GIGA_MAC_VER_32:
2979         case RTL_GIGA_MAC_VER_33:
2980                 rtl8168e_1_hw_phy_config(tp);
2981                 break;
2982         case RTL_GIGA_MAC_VER_34:
2983                 rtl8168e_2_hw_phy_config(tp);
2984                 break;
2985
2986         default:
2987                 break;
2988         }
2989 }
2990
2991 static void rtl8169_phy_timer(unsigned long __opaque)
2992 {
2993         struct net_device *dev = (struct net_device *)__opaque;
2994         struct rtl8169_private *tp = netdev_priv(dev);
2995         struct timer_list *timer = &tp->timer;
2996         void __iomem *ioaddr = tp->mmio_addr;
2997         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2998
2999         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3000
3001         spin_lock_irq(&tp->lock);
3002
3003         if (tp->phy_reset_pending(tp)) {
3004                 /*
3005                  * A busy loop could burn quite a few cycles on nowadays CPU.
3006                  * Let's delay the execution of the timer for a few ticks.
3007                  */
3008                 timeout = HZ/10;
3009                 goto out_mod_timer;
3010         }
3011
3012         if (tp->link_ok(ioaddr))
3013                 goto out_unlock;
3014
3015         netif_warn(tp, link, dev, "PHY reset until link up\n");
3016
3017         tp->phy_reset_enable(tp);
3018
3019 out_mod_timer:
3020         mod_timer(timer, jiffies + timeout);
3021 out_unlock:
3022         spin_unlock_irq(&tp->lock);
3023 }
3024
3025 #ifdef CONFIG_NET_POLL_CONTROLLER
3026 /*
3027  * Polling 'interrupt' - used by things like netconsole to send skbs
3028  * without having to re-enable interrupts. It's not called while
3029  * the interrupt routine is executing.
3030  */
3031 static void rtl8169_netpoll(struct net_device *dev)
3032 {
3033         struct rtl8169_private *tp = netdev_priv(dev);
3034         struct pci_dev *pdev = tp->pci_dev;
3035
3036         disable_irq(pdev->irq);
3037         rtl8169_interrupt(pdev->irq, dev);
3038         enable_irq(pdev->irq);
3039 }
3040 #endif
3041
3042 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3043                                   void __iomem *ioaddr)
3044 {
3045         iounmap(ioaddr);
3046         pci_release_regions(pdev);
3047         pci_clear_mwi(pdev);
3048         pci_disable_device(pdev);
3049         free_netdev(dev);
3050 }
3051
3052 static void rtl8169_phy_reset(struct net_device *dev,
3053                               struct rtl8169_private *tp)
3054 {
3055         unsigned int i;
3056
3057         tp->phy_reset_enable(tp);
3058         for (i = 0; i < 100; i++) {
3059                 if (!tp->phy_reset_pending(tp))
3060                         return;
3061                 msleep(1);
3062         }
3063         netif_err(tp, link, dev, "PHY reset failed\n");
3064 }
3065
3066 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3067 {
3068         void __iomem *ioaddr = tp->mmio_addr;
3069
3070         rtl_hw_phy_config(dev);
3071
3072         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3073                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3074                 RTL_W8(0x82, 0x01);
3075         }
3076
3077         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3078
3079         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3080                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3081
3082         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3083                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3084                 RTL_W8(0x82, 0x01);
3085                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3086                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3087         }
3088
3089         rtl8169_phy_reset(dev, tp);
3090
3091         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3092                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3093                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3094                           (tp->mii.supports_gmii ?
3095                            ADVERTISED_1000baseT_Half |
3096                            ADVERTISED_1000baseT_Full : 0));
3097
3098         if (RTL_R8(PHYstatus) & TBI_Enable)
3099                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3100 }
3101
3102 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3103 {
3104         void __iomem *ioaddr = tp->mmio_addr;
3105         u32 high;
3106         u32 low;
3107
3108         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3109         high = addr[4] | (addr[5] << 8);
3110
3111         spin_lock_irq(&tp->lock);
3112
3113         RTL_W8(Cfg9346, Cfg9346_Unlock);
3114
3115         RTL_W32(MAC4, high);
3116         RTL_R32(MAC4);
3117
3118         RTL_W32(MAC0, low);
3119         RTL_R32(MAC0);
3120
3121         RTL_W8(Cfg9346, Cfg9346_Lock);
3122
3123         spin_unlock_irq(&tp->lock);
3124 }
3125
3126 static int rtl_set_mac_address(struct net_device *dev, void *p)
3127 {
3128         struct rtl8169_private *tp = netdev_priv(dev);
3129         struct sockaddr *addr = p;
3130
3131         if (!is_valid_ether_addr(addr->sa_data))
3132                 return -EADDRNOTAVAIL;
3133
3134         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3135
3136         rtl_rar_set(tp, dev->dev_addr);
3137
3138         return 0;
3139 }
3140
3141 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3142 {
3143         struct rtl8169_private *tp = netdev_priv(dev);
3144         struct mii_ioctl_data *data = if_mii(ifr);
3145
3146         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3147 }
3148
3149 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3150                           struct mii_ioctl_data *data, int cmd)
3151 {
3152         switch (cmd) {
3153         case SIOCGMIIPHY:
3154                 data->phy_id = 32; /* Internal PHY */
3155                 return 0;
3156
3157         case SIOCGMIIREG:
3158                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3159                 return 0;
3160
3161         case SIOCSMIIREG:
3162                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3163                 return 0;
3164         }
3165         return -EOPNOTSUPP;
3166 }
3167
3168 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3169 {
3170         return -EOPNOTSUPP;
3171 }
3172
3173 static const struct rtl_cfg_info {
3174         void (*hw_start)(struct net_device *);
3175         unsigned int region;
3176         unsigned int align;
3177         u16 intr_event;
3178         u16 napi_event;
3179         unsigned features;
3180         u8 default_ver;
3181 } rtl_cfg_infos [] = {
3182         [RTL_CFG_0] = {
3183                 .hw_start       = rtl_hw_start_8169,
3184                 .region         = 1,
3185                 .align          = 0,
3186                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3187                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3188                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3189                 .features       = RTL_FEATURE_GMII,
3190                 .default_ver    = RTL_GIGA_MAC_VER_01,
3191         },
3192         [RTL_CFG_1] = {
3193                 .hw_start       = rtl_hw_start_8168,
3194                 .region         = 2,
3195                 .align          = 8,
3196                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3197                                   TxErr | TxOK | RxOK | RxErr,
3198                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
3199                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3200                 .default_ver    = RTL_GIGA_MAC_VER_11,
3201         },
3202         [RTL_CFG_2] = {
3203                 .hw_start       = rtl_hw_start_8101,
3204                 .region         = 2,
3205                 .align          = 8,
3206                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3207                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3208                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3209                 .features       = RTL_FEATURE_MSI,
3210                 .default_ver    = RTL_GIGA_MAC_VER_13,
3211         }
3212 };
3213
3214 /* Cfg9346_Unlock assumed. */
3215 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
3216                             const struct rtl_cfg_info *cfg)
3217 {
3218         unsigned msi = 0;
3219         u8 cfg2;
3220
3221         cfg2 = RTL_R8(Config2) & ~MSIEnable;
3222         if (cfg->features & RTL_FEATURE_MSI) {
3223                 if (pci_enable_msi(pdev)) {
3224                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3225                 } else {
3226                         cfg2 |= MSIEnable;
3227                         msi = RTL_FEATURE_MSI;
3228                 }
3229         }
3230         RTL_W8(Config2, cfg2);
3231         return msi;
3232 }
3233
3234 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3235 {
3236         if (tp->features & RTL_FEATURE_MSI) {
3237                 pci_disable_msi(pdev);
3238                 tp->features &= ~RTL_FEATURE_MSI;
3239         }
3240 }
3241
3242 static const struct net_device_ops rtl8169_netdev_ops = {
3243         .ndo_open               = rtl8169_open,
3244         .ndo_stop               = rtl8169_close,
3245         .ndo_get_stats          = rtl8169_get_stats,
3246         .ndo_start_xmit         = rtl8169_start_xmit,
3247         .ndo_tx_timeout         = rtl8169_tx_timeout,
3248         .ndo_validate_addr      = eth_validate_addr,
3249         .ndo_change_mtu         = rtl8169_change_mtu,
3250         .ndo_fix_features       = rtl8169_fix_features,
3251         .ndo_set_features       = rtl8169_set_features,
3252         .ndo_set_mac_address    = rtl_set_mac_address,
3253         .ndo_do_ioctl           = rtl8169_ioctl,
3254         .ndo_set_multicast_list = rtl_set_rx_mode,
3255 #ifdef CONFIG_NET_POLL_CONTROLLER
3256         .ndo_poll_controller    = rtl8169_netpoll,
3257 #endif
3258
3259 };
3260
3261 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3262 {
3263         struct mdio_ops *ops = &tp->mdio_ops;
3264
3265         switch (tp->mac_version) {
3266         case RTL_GIGA_MAC_VER_27:
3267                 ops->write      = r8168dp_1_mdio_write;
3268                 ops->read       = r8168dp_1_mdio_read;
3269                 break;
3270         case RTL_GIGA_MAC_VER_28:
3271         case RTL_GIGA_MAC_VER_31:
3272                 ops->write      = r8168dp_2_mdio_write;
3273                 ops->read       = r8168dp_2_mdio_read;
3274                 break;
3275         default:
3276                 ops->write      = r8169_mdio_write;
3277                 ops->read       = r8169_mdio_read;
3278                 break;
3279         }
3280 }
3281
3282 static void r810x_phy_power_down(struct rtl8169_private *tp)
3283 {
3284         rtl_writephy(tp, 0x1f, 0x0000);
3285         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3286 }
3287
3288 static void r810x_phy_power_up(struct rtl8169_private *tp)
3289 {
3290         rtl_writephy(tp, 0x1f, 0x0000);
3291         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3292 }
3293
3294 static void r810x_pll_power_down(struct rtl8169_private *tp)
3295 {
3296         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3297                 rtl_writephy(tp, 0x1f, 0x0000);
3298                 rtl_writephy(tp, MII_BMCR, 0x0000);
3299                 return;
3300         }
3301
3302         r810x_phy_power_down(tp);
3303 }
3304
3305 static void r810x_pll_power_up(struct rtl8169_private *tp)
3306 {
3307         r810x_phy_power_up(tp);
3308 }
3309
3310 static void r8168_phy_power_up(struct rtl8169_private *tp)
3311 {
3312         rtl_writephy(tp, 0x1f, 0x0000);
3313         switch (tp->mac_version) {
3314         case RTL_GIGA_MAC_VER_11:
3315         case RTL_GIGA_MAC_VER_12:
3316         case RTL_GIGA_MAC_VER_17:
3317         case RTL_GIGA_MAC_VER_18:
3318         case RTL_GIGA_MAC_VER_19:
3319         case RTL_GIGA_MAC_VER_20:
3320         case RTL_GIGA_MAC_VER_21:
3321         case RTL_GIGA_MAC_VER_22:
3322         case RTL_GIGA_MAC_VER_23:
3323         case RTL_GIGA_MAC_VER_24:
3324         case RTL_GIGA_MAC_VER_25:
3325         case RTL_GIGA_MAC_VER_26:
3326         case RTL_GIGA_MAC_VER_27:
3327         case RTL_GIGA_MAC_VER_28:
3328         case RTL_GIGA_MAC_VER_31:
3329                 rtl_writephy(tp, 0x0e, 0x0000);
3330                 break;
3331         default:
3332                 break;
3333         }
3334         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3335 }
3336
3337 static void r8168_phy_power_down(struct rtl8169_private *tp)
3338 {
3339         rtl_writephy(tp, 0x1f, 0x0000);
3340         switch (tp->mac_version) {
3341         case RTL_GIGA_MAC_VER_32:
3342         case RTL_GIGA_MAC_VER_33:
3343                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3344                 break;
3345
3346         case RTL_GIGA_MAC_VER_11:
3347         case RTL_GIGA_MAC_VER_12:
3348         case RTL_GIGA_MAC_VER_17:
3349         case RTL_GIGA_MAC_VER_18:
3350         case RTL_GIGA_MAC_VER_19:
3351         case RTL_GIGA_MAC_VER_20:
3352         case RTL_GIGA_MAC_VER_21:
3353         case RTL_GIGA_MAC_VER_22:
3354         case RTL_GIGA_MAC_VER_23:
3355         case RTL_GIGA_MAC_VER_24:
3356         case RTL_GIGA_MAC_VER_25:
3357         case RTL_GIGA_MAC_VER_26:
3358         case RTL_GIGA_MAC_VER_27:
3359         case RTL_GIGA_MAC_VER_28:
3360         case RTL_GIGA_MAC_VER_31:
3361                 rtl_writephy(tp, 0x0e, 0x0200);
3362         default:
3363                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3364                 break;
3365         }
3366 }
3367
3368 static void r8168_pll_power_down(struct rtl8169_private *tp)
3369 {
3370         void __iomem *ioaddr = tp->mmio_addr;
3371
3372         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3373              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3374              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3375             r8168dp_check_dash(tp)) {
3376                 return;
3377         }
3378
3379         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3380              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3381             (RTL_R16(CPlusCmd) & ASF)) {
3382                 return;
3383         }
3384
3385         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3386             tp->mac_version == RTL_GIGA_MAC_VER_33)
3387                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3388
3389         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3390                 rtl_writephy(tp, 0x1f, 0x0000);
3391                 rtl_writephy(tp, MII_BMCR, 0x0000);
3392
3393                 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3394                     tp->mac_version == RTL_GIGA_MAC_VER_33)
3395                         RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3396                                 AcceptMulticast | AcceptMyPhys);
3397                 return;
3398         }
3399
3400         r8168_phy_power_down(tp);
3401
3402         switch (tp->mac_version) {
3403         case RTL_GIGA_MAC_VER_25:
3404         case RTL_GIGA_MAC_VER_26:
3405         case RTL_GIGA_MAC_VER_27:
3406         case RTL_GIGA_MAC_VER_28:
3407         case RTL_GIGA_MAC_VER_31:
3408         case RTL_GIGA_MAC_VER_32:
3409         case RTL_GIGA_MAC_VER_33:
3410                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3411                 break;
3412         }
3413 }
3414
3415 static void r8168_pll_power_up(struct rtl8169_private *tp)
3416 {
3417         void __iomem *ioaddr = tp->mmio_addr;
3418
3419         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3420              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3421              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3422             r8168dp_check_dash(tp)) {
3423                 return;
3424         }
3425
3426         switch (tp->mac_version) {
3427         case RTL_GIGA_MAC_VER_25:
3428         case RTL_GIGA_MAC_VER_26:
3429         case RTL_GIGA_MAC_VER_27:
3430         case RTL_GIGA_MAC_VER_28:
3431         case RTL_GIGA_MAC_VER_31:
3432         case RTL_GIGA_MAC_VER_32:
3433         case RTL_GIGA_MAC_VER_33:
3434                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3435                 break;
3436         }
3437
3438         r8168_phy_power_up(tp);
3439 }
3440
3441 static void rtl_pll_power_op(struct rtl8169_private *tp,
3442                              void (*op)(struct rtl8169_private *))
3443 {
3444         if (op)
3445                 op(tp);
3446 }
3447
3448 static void rtl_pll_power_down(struct rtl8169_private *tp)
3449 {
3450         rtl_pll_power_op(tp, tp->pll_power_ops.down);
3451 }
3452
3453 static void rtl_pll_power_up(struct rtl8169_private *tp)
3454 {
3455         rtl_pll_power_op(tp, tp->pll_power_ops.up);
3456 }
3457
3458 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3459 {
3460         struct pll_power_ops *ops = &tp->pll_power_ops;
3461
3462         switch (tp->mac_version) {
3463         case RTL_GIGA_MAC_VER_07:
3464         case RTL_GIGA_MAC_VER_08:
3465         case RTL_GIGA_MAC_VER_09:
3466         case RTL_GIGA_MAC_VER_10:
3467         case RTL_GIGA_MAC_VER_16:
3468         case RTL_GIGA_MAC_VER_29:
3469         case RTL_GIGA_MAC_VER_30:
3470                 ops->down       = r810x_pll_power_down;
3471                 ops->up         = r810x_pll_power_up;
3472                 break;
3473
3474         case RTL_GIGA_MAC_VER_11:
3475         case RTL_GIGA_MAC_VER_12:
3476         case RTL_GIGA_MAC_VER_17:
3477         case RTL_GIGA_MAC_VER_18:
3478         case RTL_GIGA_MAC_VER_19:
3479         case RTL_GIGA_MAC_VER_20:
3480         case RTL_GIGA_MAC_VER_21:
3481         case RTL_GIGA_MAC_VER_22:
3482         case RTL_GIGA_MAC_VER_23:
3483         case RTL_GIGA_MAC_VER_24:
3484         case RTL_GIGA_MAC_VER_25:
3485         case RTL_GIGA_MAC_VER_26:
3486         case RTL_GIGA_MAC_VER_27:
3487         case RTL_GIGA_MAC_VER_28:
3488         case RTL_GIGA_MAC_VER_31:
3489         case RTL_GIGA_MAC_VER_32:
3490         case RTL_GIGA_MAC_VER_33:
3491         case RTL_GIGA_MAC_VER_34:
3492                 ops->down       = r8168_pll_power_down;
3493                 ops->up         = r8168_pll_power_up;
3494                 break;
3495
3496         default:
3497                 ops->down       = NULL;
3498                 ops->up         = NULL;
3499                 break;
3500         }
3501 }
3502
3503 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3504 {
3505         void __iomem *ioaddr = tp->mmio_addr;
3506
3507         switch (tp->mac_version) {
3508         case RTL_GIGA_MAC_VER_01:
3509         case RTL_GIGA_MAC_VER_02:
3510         case RTL_GIGA_MAC_VER_03:
3511         case RTL_GIGA_MAC_VER_04:
3512         case RTL_GIGA_MAC_VER_05:
3513         case RTL_GIGA_MAC_VER_06:
3514         case RTL_GIGA_MAC_VER_10:
3515         case RTL_GIGA_MAC_VER_11:
3516         case RTL_GIGA_MAC_VER_12:
3517         case RTL_GIGA_MAC_VER_13:
3518         case RTL_GIGA_MAC_VER_14:
3519         case RTL_GIGA_MAC_VER_15:
3520         case RTL_GIGA_MAC_VER_16:
3521         case RTL_GIGA_MAC_VER_17:
3522                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3523                 break;
3524         case RTL_GIGA_MAC_VER_18:
3525         case RTL_GIGA_MAC_VER_19:
3526         case RTL_GIGA_MAC_VER_20:
3527         case RTL_GIGA_MAC_VER_21:
3528         case RTL_GIGA_MAC_VER_22:
3529         case RTL_GIGA_MAC_VER_23:
3530         case RTL_GIGA_MAC_VER_24:
3531                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3532                 break;
3533         default:
3534                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3535                 break;
3536         }
3537 }
3538
3539 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3540 {
3541         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3542 }
3543
3544 static void rtl_hw_reset(struct rtl8169_private *tp)
3545 {
3546         void __iomem *ioaddr = tp->mmio_addr;
3547         int i;
3548
3549         /* Soft reset the chip. */
3550         RTL_W8(ChipCmd, CmdReset);
3551
3552         /* Check that the chip has finished the reset. */
3553         for (i = 0; i < 100; i++) {
3554                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3555                         break;
3556                 udelay(100);
3557         }
3558
3559         rtl8169_init_ring_indexes(tp);
3560 }
3561
3562 static int __devinit
3563 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3564 {
3565         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3566         const unsigned int region = cfg->region;
3567         struct rtl8169_private *tp;
3568         struct mii_if_info *mii;
3569         struct net_device *dev;
3570         void __iomem *ioaddr;
3571         int chipset, i;
3572         int rc;
3573
3574         if (netif_msg_drv(&debug)) {
3575                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3576                        MODULENAME, RTL8169_VERSION);
3577         }
3578
3579         dev = alloc_etherdev(sizeof (*tp));
3580         if (!dev) {
3581                 if (netif_msg_drv(&debug))
3582                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3583                 rc = -ENOMEM;
3584                 goto out;
3585         }
3586
3587         SET_NETDEV_DEV(dev, &pdev->dev);
3588         dev->netdev_ops = &rtl8169_netdev_ops;
3589         tp = netdev_priv(dev);
3590         tp->dev = dev;
3591         tp->pci_dev = pdev;
3592         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3593
3594         mii = &tp->mii;
3595         mii->dev = dev;
3596         mii->mdio_read = rtl_mdio_read;
3597         mii->mdio_write = rtl_mdio_write;
3598         mii->phy_id_mask = 0x1f;
3599         mii->reg_num_mask = 0x1f;
3600         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3601
3602         /* disable ASPM completely as that cause random device stop working
3603          * problems as well as full system hangs for some PCIe devices users */
3604         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3605                                      PCIE_LINK_STATE_CLKPM);
3606
3607         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3608         rc = pci_enable_device(pdev);
3609         if (rc < 0) {
3610                 netif_err(tp, probe, dev, "enable failure\n");
3611                 goto err_out_free_dev_1;
3612         }
3613
3614         if (pci_set_mwi(pdev) < 0)
3615                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3616
3617         /* make sure PCI base addr 1 is MMIO */
3618         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3619                 netif_err(tp, probe, dev,
3620                           "region #%d not an MMIO resource, aborting\n",
3621                           region);
3622                 rc = -ENODEV;
3623                 goto err_out_mwi_2;
3624         }
3625
3626         /* check for weird/broken PCI region reporting */
3627         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3628                 netif_err(tp, probe, dev,
3629                           "Invalid PCI region size(s), aborting\n");
3630                 rc = -ENODEV;
3631                 goto err_out_mwi_2;
3632         }
3633
3634         rc = pci_request_regions(pdev, MODULENAME);
3635         if (rc < 0) {
3636                 netif_err(tp, probe, dev, "could not request regions\n");
3637                 goto err_out_mwi_2;
3638         }
3639
3640         tp->cp_cmd = RxChkSum;
3641
3642         if ((sizeof(dma_addr_t) > 4) &&
3643             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3644                 tp->cp_cmd |= PCIDAC;
3645                 dev->features |= NETIF_F_HIGHDMA;
3646         } else {
3647                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3648                 if (rc < 0) {
3649                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3650                         goto err_out_free_res_3;
3651                 }
3652         }
3653
3654         /* ioremap MMIO region */
3655         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3656         if (!ioaddr) {
3657                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3658                 rc = -EIO;
3659                 goto err_out_free_res_3;
3660         }
3661         tp->mmio_addr = ioaddr;
3662
3663         if (!pci_is_pcie(pdev))
3664                 netif_info(tp, probe, dev, "not PCI Express\n");
3665
3666         /* Identify chip attached to board */
3667         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3668
3669         rtl_init_rxcfg(tp);
3670
3671         RTL_W16(IntrMask, 0x0000);
3672
3673         rtl_hw_reset(tp);
3674
3675         RTL_W16(IntrStatus, 0xffff);
3676
3677         pci_set_master(pdev);
3678
3679         /*
3680          * Pretend we are using VLANs; This bypasses a nasty bug where
3681          * Interrupts stop flowing on high load on 8110SCd controllers.
3682          */
3683         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3684                 tp->cp_cmd |= RxVlan;
3685
3686         rtl_init_mdio_ops(tp);
3687         rtl_init_pll_power_ops(tp);
3688
3689         rtl8169_print_mac_version(tp);
3690
3691         chipset = tp->mac_version;
3692         tp->txd_version = rtl_chip_infos[chipset].txd_version;
3693
3694         RTL_W8(Cfg9346, Cfg9346_Unlock);
3695         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3696         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3697         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3698                 tp->features |= RTL_FEATURE_WOL;
3699         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3700                 tp->features |= RTL_FEATURE_WOL;
3701         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3702         RTL_W8(Cfg9346, Cfg9346_Lock);
3703
3704         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3705             (RTL_R8(PHYstatus) & TBI_Enable)) {
3706                 tp->set_speed = rtl8169_set_speed_tbi;
3707                 tp->get_settings = rtl8169_gset_tbi;
3708                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3709                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3710                 tp->link_ok = rtl8169_tbi_link_ok;
3711                 tp->do_ioctl = rtl_tbi_ioctl;
3712         } else {
3713                 tp->set_speed = rtl8169_set_speed_xmii;
3714                 tp->get_settings = rtl8169_gset_xmii;
3715                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3716                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3717                 tp->link_ok = rtl8169_xmii_link_ok;
3718                 tp->do_ioctl = rtl_xmii_ioctl;
3719         }
3720
3721         spin_lock_init(&tp->lock);
3722
3723         /* Get MAC address */
3724         for (i = 0; i < MAC_ADDR_LEN; i++)
3725                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3726         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3727
3728         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3729         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3730         dev->irq = pdev->irq;
3731         dev->base_addr = (unsigned long) ioaddr;
3732
3733         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3734
3735         /* don't enable SG, IP_CSUM and TSO by default - it might not work
3736          * properly for all devices */
3737         dev->features |= NETIF_F_RXCSUM |
3738                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3739
3740         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3741                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3742         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3743                 NETIF_F_HIGHDMA;
3744
3745         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3746                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3747                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3748
3749         tp->intr_mask = 0xffff;
3750         tp->hw_start = cfg->hw_start;
3751         tp->intr_event = cfg->intr_event;
3752         tp->napi_event = cfg->napi_event;
3753
3754         init_timer(&tp->timer);
3755         tp->timer.data = (unsigned long) dev;
3756         tp->timer.function = rtl8169_phy_timer;
3757
3758         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
3759
3760         rc = register_netdev(dev);
3761         if (rc < 0)
3762                 goto err_out_msi_4;
3763
3764         pci_set_drvdata(pdev, dev);
3765
3766         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3767                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3768                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3769
3770         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3771             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3772             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3773                 rtl8168_driver_start(tp);
3774         }
3775
3776         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3777
3778         if (pci_dev_run_wake(pdev))
3779                 pm_runtime_put_noidle(&pdev->dev);
3780
3781         netif_carrier_off(dev);
3782
3783 out:
3784         return rc;
3785
3786 err_out_msi_4:
3787         rtl_disable_msi(pdev, tp);
3788         iounmap(ioaddr);
3789 err_out_free_res_3:
3790         pci_release_regions(pdev);
3791 err_out_mwi_2:
3792         pci_clear_mwi(pdev);
3793         pci_disable_device(pdev);
3794 err_out_free_dev_1:
3795         free_netdev(dev);
3796         goto out;
3797 }
3798
3799 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3800 {
3801         struct net_device *dev = pci_get_drvdata(pdev);
3802         struct rtl8169_private *tp = netdev_priv(dev);
3803
3804         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3805             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3806             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3807                 rtl8168_driver_stop(tp);
3808         }
3809
3810         cancel_delayed_work_sync(&tp->task);
3811
3812         unregister_netdev(dev);
3813
3814         rtl_release_firmware(tp);
3815
3816         if (pci_dev_run_wake(pdev))
3817                 pm_runtime_get_noresume(&pdev->dev);
3818
3819         /* restore original MAC address */
3820         rtl_rar_set(tp, dev->perm_addr);
3821
3822         rtl_disable_msi(pdev, tp);
3823         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3824         pci_set_drvdata(pdev, NULL);
3825 }
3826
3827 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3828 {
3829         struct rtl_fw *rtl_fw;
3830         const char *name;
3831         int rc = -ENOMEM;
3832
3833         name = rtl_lookup_firmware_name(tp);
3834         if (!name)
3835                 goto out_no_firmware;
3836
3837         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3838         if (!rtl_fw)
3839                 goto err_warn;
3840
3841         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3842         if (rc < 0)
3843                 goto err_free;
3844
3845         rc = rtl_check_firmware(tp, rtl_fw);
3846         if (rc < 0)
3847                 goto err_release_firmware;
3848
3849         tp->rtl_fw = rtl_fw;
3850 out:
3851         return;
3852
3853 err_release_firmware:
3854         release_firmware(rtl_fw->fw);
3855 err_free:
3856         kfree(rtl_fw);
3857 err_warn:
3858         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3859                    name, rc);
3860 out_no_firmware:
3861         tp->rtl_fw = NULL;
3862         goto out;
3863 }
3864
3865 static void rtl_request_firmware(struct rtl8169_private *tp)
3866 {
3867         if (IS_ERR(tp->rtl_fw))
3868                 rtl_request_uncached_firmware(tp);
3869 }
3870
3871 static int rtl8169_open(struct net_device *dev)
3872 {
3873         struct rtl8169_private *tp = netdev_priv(dev);
3874         void __iomem *ioaddr = tp->mmio_addr;
3875         struct pci_dev *pdev = tp->pci_dev;
3876         int retval = -ENOMEM;
3877
3878         pm_runtime_get_sync(&pdev->dev);
3879
3880         /*
3881          * Rx and Tx desscriptors needs 256 bytes alignment.
3882          * dma_alloc_coherent provides more.
3883          */
3884         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3885                                              &tp->TxPhyAddr, GFP_KERNEL);
3886         if (!tp->TxDescArray)
3887                 goto err_pm_runtime_put;
3888
3889         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3890                                              &tp->RxPhyAddr, GFP_KERNEL);
3891         if (!tp->RxDescArray)
3892                 goto err_free_tx_0;
3893
3894         retval = rtl8169_init_ring(dev);
3895         if (retval < 0)
3896                 goto err_free_rx_1;
3897
3898         INIT_DELAYED_WORK(&tp->task, NULL);
3899
3900         smp_mb();
3901
3902         rtl_request_firmware(tp);
3903
3904         retval = request_irq(dev->irq, rtl8169_interrupt,
3905                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3906                              dev->name, dev);
3907         if (retval < 0)
3908                 goto err_release_fw_2;
3909
3910         napi_enable(&tp->napi);
3911
3912         rtl8169_init_phy(dev, tp);
3913
3914         rtl8169_set_features(dev, dev->features);
3915
3916         rtl_pll_power_up(tp);
3917
3918         rtl_hw_start(dev);
3919
3920         tp->saved_wolopts = 0;
3921         pm_runtime_put_noidle(&pdev->dev);
3922
3923         rtl8169_check_link_status(dev, tp, ioaddr);
3924 out:
3925         return retval;
3926
3927 err_release_fw_2:
3928         rtl_release_firmware(tp);
3929         rtl8169_rx_clear(tp);
3930 err_free_rx_1:
3931         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3932                           tp->RxPhyAddr);
3933         tp->RxDescArray = NULL;
3934 err_free_tx_0:
3935         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3936                           tp->TxPhyAddr);
3937         tp->TxDescArray = NULL;
3938 err_pm_runtime_put:
3939         pm_runtime_put_noidle(&pdev->dev);
3940         goto out;
3941 }
3942
3943 static void rtl_rx_close(struct rtl8169_private *tp)
3944 {
3945         void __iomem *ioaddr = tp->mmio_addr;
3946         u32 rxcfg = RTL_R32(RxConfig);
3947
3948         rxcfg &= ~(AcceptErr | AcceptRunt | AcceptBroadcast | AcceptMulticast |
3949                    AcceptMyPhys | AcceptAllPhys);
3950         RTL_W32(RxConfig, rxcfg);
3951 }
3952
3953 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3954 {
3955         void __iomem *ioaddr = tp->mmio_addr;
3956
3957         /* Disable interrupts */
3958         rtl8169_irq_mask_and_ack(ioaddr);
3959
3960         rtl_rx_close(tp);
3961
3962         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3963             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3964             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3965                 while (RTL_R8(TxPoll) & NPQ)
3966                         udelay(20);
3967         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3968                 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
3969                         udelay(100);
3970         } else {
3971                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3972                 udelay(100);
3973         }
3974
3975         rtl_hw_reset(tp);
3976 }
3977
3978 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3979 {
3980         void __iomem *ioaddr = tp->mmio_addr;
3981
3982         /* Set DMA burst size and Interframe Gap Time */
3983         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3984                 (InterFrameGap << TxInterFrameGapShift));
3985 }
3986
3987 static void rtl_hw_start(struct net_device *dev)
3988 {
3989         struct rtl8169_private *tp = netdev_priv(dev);
3990
3991         tp->hw_start(dev);
3992
3993         netif_start_queue(dev);
3994 }
3995
3996 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3997                                          void __iomem *ioaddr)
3998 {
3999         /*
4000          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4001          * register to be written before TxDescAddrLow to work.
4002          * Switching from MMIO to I/O access fixes the issue as well.
4003          */
4004         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4005         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4006         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4007         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4008 }
4009
4010 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4011 {
4012         u16 cmd;
4013
4014         cmd = RTL_R16(CPlusCmd);
4015         RTL_W16(CPlusCmd, cmd);
4016         return cmd;
4017 }
4018
4019 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4020 {
4021         /* Low hurts. Let's disable the filtering. */
4022         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4023 }
4024
4025 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4026 {
4027         static const struct rtl_cfg2_info {
4028                 u32 mac_version;
4029                 u32 clk;
4030                 u32 val;
4031         } cfg2_info [] = {
4032                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4033                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4034                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4035                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4036         };
4037         const struct rtl_cfg2_info *p = cfg2_info;
4038         unsigned int i;
4039         u32 clk;
4040
4041         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4042         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4043                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4044                         RTL_W32(0x7c, p->val);
4045                         break;
4046                 }
4047         }
4048 }
4049
4050 static void rtl_hw_start_8169(struct net_device *dev)
4051 {
4052         struct rtl8169_private *tp = netdev_priv(dev);
4053         void __iomem *ioaddr = tp->mmio_addr;
4054         struct pci_dev *pdev = tp->pci_dev;
4055
4056         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4057                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4058                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4059         }
4060
4061         RTL_W8(Cfg9346, Cfg9346_Unlock);
4062         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4063             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4064             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4065             tp->mac_version == RTL_GIGA_MAC_VER_04)
4066                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4067
4068         rtl_init_rxcfg(tp);
4069
4070         RTL_W8(EarlyTxThres, NoEarlyTx);
4071
4072         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4073
4074         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4075             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4076             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4077             tp->mac_version == RTL_GIGA_MAC_VER_04)
4078                 rtl_set_rx_tx_config_registers(tp);
4079
4080         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4081
4082         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4083             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4084                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4085                         "Bit-3 and bit-14 MUST be 1\n");
4086                 tp->cp_cmd |= (1 << 14);
4087         }
4088
4089         RTL_W16(CPlusCmd, tp->cp_cmd);
4090
4091         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4092
4093         /*
4094          * Undocumented corner. Supposedly:
4095          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4096          */
4097         RTL_W16(IntrMitigate, 0x0000);
4098
4099         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4100
4101         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4102             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4103             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4104             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4105                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4106                 rtl_set_rx_tx_config_registers(tp);
4107         }
4108
4109         RTL_W8(Cfg9346, Cfg9346_Lock);
4110
4111         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4112         RTL_R8(IntrMask);
4113
4114         RTL_W32(RxMissed, 0);
4115
4116         rtl_set_rx_mode(dev);
4117
4118         /* no early-rx interrupts */
4119         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4120
4121         /* Enable all known interrupts by setting the interrupt mask. */
4122         RTL_W16(IntrMask, tp->intr_event);
4123 }
4124
4125 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
4126 {
4127         int cap = pci_pcie_cap(pdev);
4128
4129         if (cap) {
4130                 u16 ctl;
4131
4132                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
4133                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
4134                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
4135         }
4136 }
4137
4138 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4139 {
4140         u32 csi;
4141
4142         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4143         rtl_csi_write(ioaddr, 0x070c, csi | bits);
4144 }
4145
4146 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4147 {
4148         rtl_csi_access_enable(ioaddr, 0x17000000);
4149 }
4150
4151 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4152 {
4153         rtl_csi_access_enable(ioaddr, 0x27000000);
4154 }
4155
4156 struct ephy_info {
4157         unsigned int offset;
4158         u16 mask;
4159         u16 bits;
4160 };
4161
4162 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4163 {
4164         u16 w;
4165
4166         while (len-- > 0) {
4167                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4168                 rtl_ephy_write(ioaddr, e->offset, w);
4169                 e++;
4170         }
4171 }
4172
4173 static void rtl_disable_clock_request(struct pci_dev *pdev)
4174 {
4175         int cap = pci_pcie_cap(pdev);
4176
4177         if (cap) {
4178                 u16 ctl;
4179
4180                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4181                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4182                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4183         }
4184 }
4185
4186 static void rtl_enable_clock_request(struct pci_dev *pdev)
4187 {
4188         int cap = pci_pcie_cap(pdev);
4189
4190         if (cap) {
4191                 u16 ctl;
4192
4193                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4194                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4195                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4196         }
4197 }
4198
4199 #define R8168_CPCMD_QUIRK_MASK (\
4200         EnableBist | \
4201         Mac_dbgo_oe | \
4202         Force_half_dup | \
4203         Force_rxflow_en | \
4204         Force_txflow_en | \
4205         Cxpl_dbg_sel | \
4206         ASF | \
4207         PktCntrDisable | \
4208         Mac_dbgo_sel)
4209
4210 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4211 {
4212         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4213
4214         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4215
4216         rtl_tx_performance_tweak(pdev,
4217                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4218 }
4219
4220 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4221 {
4222         rtl_hw_start_8168bb(ioaddr, pdev);
4223
4224         RTL_W8(MaxTxPacketSize, TxPacketMax);
4225
4226         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4227 }
4228
4229 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4230 {
4231         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4232
4233         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4234
4235         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4236
4237         rtl_disable_clock_request(pdev);
4238
4239         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4240 }
4241
4242 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4243 {
4244         static const struct ephy_info e_info_8168cp[] = {
4245                 { 0x01, 0,      0x0001 },
4246                 { 0x02, 0x0800, 0x1000 },
4247                 { 0x03, 0,      0x0042 },
4248                 { 0x06, 0x0080, 0x0000 },
4249                 { 0x07, 0,      0x2000 }
4250         };
4251
4252         rtl_csi_access_enable_2(ioaddr);
4253
4254         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4255
4256         __rtl_hw_start_8168cp(ioaddr, pdev);
4257 }
4258
4259 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4260 {
4261         rtl_csi_access_enable_2(ioaddr);
4262
4263         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4264
4265         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4266
4267         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4268 }
4269
4270 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4271 {
4272         rtl_csi_access_enable_2(ioaddr);
4273
4274         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4275
4276         /* Magic. */
4277         RTL_W8(DBG_REG, 0x20);
4278
4279         RTL_W8(MaxTxPacketSize, TxPacketMax);
4280
4281         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4282
4283         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4284 }
4285
4286 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4287 {
4288         static const struct ephy_info e_info_8168c_1[] = {
4289                 { 0x02, 0x0800, 0x1000 },
4290                 { 0x03, 0,      0x0002 },
4291                 { 0x06, 0x0080, 0x0000 }
4292         };
4293
4294         rtl_csi_access_enable_2(ioaddr);
4295
4296         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4297
4298         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4299
4300         __rtl_hw_start_8168cp(ioaddr, pdev);
4301 }
4302
4303 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4304 {
4305         static const struct ephy_info e_info_8168c_2[] = {
4306                 { 0x01, 0,      0x0001 },
4307                 { 0x03, 0x0400, 0x0220 }
4308         };
4309
4310         rtl_csi_access_enable_2(ioaddr);
4311
4312         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4313
4314         __rtl_hw_start_8168cp(ioaddr, pdev);
4315 }
4316
4317 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4318 {
4319         rtl_hw_start_8168c_2(ioaddr, pdev);
4320 }
4321
4322 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4323 {
4324         rtl_csi_access_enable_2(ioaddr);
4325
4326         __rtl_hw_start_8168cp(ioaddr, pdev);
4327 }
4328
4329 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4330 {
4331         rtl_csi_access_enable_2(ioaddr);
4332
4333         rtl_disable_clock_request(pdev);
4334
4335         RTL_W8(MaxTxPacketSize, TxPacketMax);
4336
4337         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4338
4339         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4340 }
4341
4342 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4343 {
4344         rtl_csi_access_enable_1(ioaddr);
4345
4346         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4347
4348         RTL_W8(MaxTxPacketSize, TxPacketMax);
4349
4350         rtl_disable_clock_request(pdev);
4351 }
4352
4353 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4354 {
4355         static const struct ephy_info e_info_8168d_4[] = {
4356                 { 0x0b, ~0,     0x48 },
4357                 { 0x19, 0x20,   0x50 },
4358                 { 0x0c, ~0,     0x20 }
4359         };
4360         int i;
4361
4362         rtl_csi_access_enable_1(ioaddr);
4363
4364         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4365
4366         RTL_W8(MaxTxPacketSize, TxPacketMax);
4367
4368         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4369                 const struct ephy_info *e = e_info_8168d_4 + i;
4370                 u16 w;
4371
4372                 w = rtl_ephy_read(ioaddr, e->offset);
4373                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4374         }
4375
4376         rtl_enable_clock_request(pdev);
4377 }
4378
4379 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4380 {
4381         static const struct ephy_info e_info_8168e_1[] = {
4382                 { 0x00, 0x0200, 0x0100 },
4383                 { 0x00, 0x0000, 0x0004 },
4384                 { 0x06, 0x0002, 0x0001 },
4385                 { 0x06, 0x0000, 0x0030 },
4386                 { 0x07, 0x0000, 0x2000 },
4387                 { 0x00, 0x0000, 0x0020 },
4388                 { 0x03, 0x5800, 0x2000 },
4389                 { 0x03, 0x0000, 0x0001 },
4390                 { 0x01, 0x0800, 0x1000 },
4391                 { 0x07, 0x0000, 0x4000 },
4392                 { 0x1e, 0x0000, 0x2000 },
4393                 { 0x19, 0xffff, 0xfe6c },
4394                 { 0x0a, 0x0000, 0x0040 }
4395         };
4396
4397         rtl_csi_access_enable_2(ioaddr);
4398
4399         rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4400
4401         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4402
4403         RTL_W8(MaxTxPacketSize, TxPacketMax);
4404
4405         rtl_disable_clock_request(pdev);
4406
4407         /* Reset tx FIFO pointer */
4408         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4409         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4410
4411         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4412 }
4413
4414 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4415 {
4416         static const struct ephy_info e_info_8168e_2[] = {
4417                 { 0x09, 0x0000, 0x0080 },
4418                 { 0x19, 0x0000, 0x0224 }
4419         };
4420
4421         rtl_csi_access_enable_1(ioaddr);
4422
4423         rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4424
4425         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4426
4427         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4428         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4429         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4430         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4431         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4432         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4433         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4434         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4435                      ERIAR_EXGMAC);
4436
4437         RTL_W8(MaxTxPacketSize, 0x27);
4438
4439         rtl_disable_clock_request(pdev);
4440
4441         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4442         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4443
4444         /* Adjust EEE LED frequency */
4445         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4446
4447         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4448         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4449         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4450 }
4451
4452 static void rtl_hw_start_8168(struct net_device *dev)
4453 {
4454         struct rtl8169_private *tp = netdev_priv(dev);
4455         void __iomem *ioaddr = tp->mmio_addr;
4456         struct pci_dev *pdev = tp->pci_dev;
4457
4458         RTL_W8(Cfg9346, Cfg9346_Unlock);
4459
4460         RTL_W8(MaxTxPacketSize, TxPacketMax);
4461
4462         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4463
4464         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4465
4466         RTL_W16(CPlusCmd, tp->cp_cmd);
4467
4468         RTL_W16(IntrMitigate, 0x5151);
4469
4470         /* Work around for RxFIFO overflow. */
4471         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4472             tp->mac_version == RTL_GIGA_MAC_VER_22) {
4473                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4474                 tp->intr_event &= ~RxOverflow;
4475         }
4476
4477         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4478
4479         rtl_set_rx_mode(dev);
4480
4481         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4482                 (InterFrameGap << TxInterFrameGapShift));
4483
4484         RTL_R8(IntrMask);
4485
4486         switch (tp->mac_version) {
4487         case RTL_GIGA_MAC_VER_11:
4488                 rtl_hw_start_8168bb(ioaddr, pdev);
4489                 break;
4490
4491         case RTL_GIGA_MAC_VER_12:
4492         case RTL_GIGA_MAC_VER_17:
4493                 rtl_hw_start_8168bef(ioaddr, pdev);
4494                 break;
4495
4496         case RTL_GIGA_MAC_VER_18:
4497                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4498                 break;
4499
4500         case RTL_GIGA_MAC_VER_19:
4501                 rtl_hw_start_8168c_1(ioaddr, pdev);
4502                 break;
4503
4504         case RTL_GIGA_MAC_VER_20:
4505                 rtl_hw_start_8168c_2(ioaddr, pdev);
4506                 break;
4507
4508         case RTL_GIGA_MAC_VER_21:
4509                 rtl_hw_start_8168c_3(ioaddr, pdev);
4510                 break;
4511
4512         case RTL_GIGA_MAC_VER_22:
4513                 rtl_hw_start_8168c_4(ioaddr, pdev);
4514                 break;
4515
4516         case RTL_GIGA_MAC_VER_23:
4517                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4518                 break;
4519
4520         case RTL_GIGA_MAC_VER_24:
4521                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4522                 break;
4523
4524         case RTL_GIGA_MAC_VER_25:
4525         case RTL_GIGA_MAC_VER_26:
4526         case RTL_GIGA_MAC_VER_27:
4527                 rtl_hw_start_8168d(ioaddr, pdev);
4528                 break;
4529
4530         case RTL_GIGA_MAC_VER_28:
4531                 rtl_hw_start_8168d_4(ioaddr, pdev);
4532                 break;
4533
4534         case RTL_GIGA_MAC_VER_31:
4535                 rtl_hw_start_8168dp(ioaddr, pdev);
4536                 break;
4537
4538         case RTL_GIGA_MAC_VER_32:
4539         case RTL_GIGA_MAC_VER_33:
4540                 rtl_hw_start_8168e_1(ioaddr, pdev);
4541                 break;
4542         case RTL_GIGA_MAC_VER_34:
4543                 rtl_hw_start_8168e_2(ioaddr, pdev);
4544                 break;
4545
4546         default:
4547                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4548                         dev->name, tp->mac_version);
4549                 break;
4550         }
4551
4552         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4553
4554         RTL_W8(Cfg9346, Cfg9346_Lock);
4555
4556         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4557
4558         RTL_W16(IntrMask, tp->intr_event);
4559 }
4560
4561 #define R810X_CPCMD_QUIRK_MASK (\
4562         EnableBist | \
4563         Mac_dbgo_oe | \
4564         Force_half_dup | \
4565         Force_rxflow_en | \
4566         Force_txflow_en | \
4567         Cxpl_dbg_sel | \
4568         ASF | \
4569         PktCntrDisable | \
4570         Mac_dbgo_sel)
4571
4572 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4573 {
4574         static const struct ephy_info e_info_8102e_1[] = {
4575                 { 0x01, 0, 0x6e65 },
4576                 { 0x02, 0, 0x091f },
4577                 { 0x03, 0, 0xc2f9 },
4578                 { 0x06, 0, 0xafb5 },
4579                 { 0x07, 0, 0x0e00 },
4580                 { 0x19, 0, 0xec80 },
4581                 { 0x01, 0, 0x2e65 },
4582                 { 0x01, 0, 0x6e65 }
4583         };
4584         u8 cfg1;
4585
4586         rtl_csi_access_enable_2(ioaddr);
4587
4588         RTL_W8(DBG_REG, FIX_NAK_1);
4589
4590         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4591
4592         RTL_W8(Config1,
4593                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4594         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4595
4596         cfg1 = RTL_R8(Config1);
4597         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4598                 RTL_W8(Config1, cfg1 & ~LEDS0);
4599
4600         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4601 }
4602
4603 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4604 {
4605         rtl_csi_access_enable_2(ioaddr);
4606
4607         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4608
4609         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4610         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4611 }
4612
4613 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4614 {
4615         rtl_hw_start_8102e_2(ioaddr, pdev);
4616
4617         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4618 }
4619
4620 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4621 {
4622         static const struct ephy_info e_info_8105e_1[] = {
4623                 { 0x07, 0, 0x4000 },
4624                 { 0x19, 0, 0x0200 },
4625                 { 0x19, 0, 0x0020 },
4626                 { 0x1e, 0, 0x2000 },
4627                 { 0x03, 0, 0x0001 },
4628                 { 0x19, 0, 0x0100 },
4629                 { 0x19, 0, 0x0004 },
4630                 { 0x0a, 0, 0x0020 }
4631         };
4632
4633         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4634         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4635
4636         /* Disable Early Tally Counter */
4637         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4638
4639         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4640         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4641
4642         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4643 }
4644
4645 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4646 {
4647         rtl_hw_start_8105e_1(ioaddr, pdev);
4648         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4649 }
4650
4651 static void rtl_hw_start_8101(struct net_device *dev)
4652 {
4653         struct rtl8169_private *tp = netdev_priv(dev);
4654         void __iomem *ioaddr = tp->mmio_addr;
4655         struct pci_dev *pdev = tp->pci_dev;
4656
4657         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4658             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4659                 int cap = pci_pcie_cap(pdev);
4660
4661                 if (cap) {
4662                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4663                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4664                 }
4665         }
4666
4667         RTL_W8(Cfg9346, Cfg9346_Unlock);
4668
4669         switch (tp->mac_version) {
4670         case RTL_GIGA_MAC_VER_07:
4671                 rtl_hw_start_8102e_1(ioaddr, pdev);
4672                 break;
4673
4674         case RTL_GIGA_MAC_VER_08:
4675                 rtl_hw_start_8102e_3(ioaddr, pdev);
4676                 break;
4677
4678         case RTL_GIGA_MAC_VER_09:
4679                 rtl_hw_start_8102e_2(ioaddr, pdev);
4680                 break;
4681
4682         case RTL_GIGA_MAC_VER_29:
4683                 rtl_hw_start_8105e_1(ioaddr, pdev);
4684                 break;
4685         case RTL_GIGA_MAC_VER_30:
4686                 rtl_hw_start_8105e_2(ioaddr, pdev);
4687                 break;
4688         }
4689
4690         RTL_W8(Cfg9346, Cfg9346_Lock);
4691
4692         RTL_W8(MaxTxPacketSize, TxPacketMax);
4693
4694         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4695
4696         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4697         RTL_W16(CPlusCmd, tp->cp_cmd);
4698
4699         RTL_W16(IntrMitigate, 0x0000);
4700
4701         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4702
4703         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4704         rtl_set_rx_tx_config_registers(tp);
4705
4706         RTL_R8(IntrMask);
4707
4708         rtl_set_rx_mode(dev);
4709
4710         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4711
4712         RTL_W16(IntrMask, tp->intr_event);
4713 }
4714
4715 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4716 {
4717         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4718                 return -EINVAL;
4719
4720         dev->mtu = new_mtu;
4721         netdev_update_features(dev);
4722
4723         return 0;
4724 }
4725
4726 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4727 {
4728         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4729         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4730 }
4731
4732 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4733                                      void **data_buff, struct RxDesc *desc)
4734 {
4735         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4736                          DMA_FROM_DEVICE);
4737
4738         kfree(*data_buff);
4739         *data_buff = NULL;
4740         rtl8169_make_unusable_by_asic(desc);
4741 }
4742
4743 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4744 {
4745         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4746
4747         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4748 }
4749
4750 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4751                                        u32 rx_buf_sz)
4752 {
4753         desc->addr = cpu_to_le64(mapping);
4754         wmb();
4755         rtl8169_mark_to_asic(desc, rx_buf_sz);
4756 }
4757
4758 static inline void *rtl8169_align(void *data)
4759 {
4760         return (void *)ALIGN((long)data, 16);
4761 }
4762
4763 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4764                                              struct RxDesc *desc)
4765 {
4766         void *data;
4767         dma_addr_t mapping;
4768         struct device *d = &tp->pci_dev->dev;
4769         struct net_device *dev = tp->dev;
4770         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4771
4772         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4773         if (!data)
4774                 return NULL;
4775
4776         if (rtl8169_align(data) != data) {
4777                 kfree(data);
4778                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4779                 if (!data)
4780                         return NULL;
4781         }
4782
4783         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4784                                  DMA_FROM_DEVICE);
4785         if (unlikely(dma_mapping_error(d, mapping))) {
4786                 if (net_ratelimit())
4787                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4788                 goto err_out;
4789         }
4790
4791         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4792         return data;
4793
4794 err_out:
4795         kfree(data);
4796         return NULL;
4797 }
4798
4799 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4800 {
4801         unsigned int i;
4802
4803         for (i = 0; i < NUM_RX_DESC; i++) {
4804                 if (tp->Rx_databuff[i]) {
4805                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4806                                             tp->RxDescArray + i);
4807                 }
4808         }
4809 }
4810
4811 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4812 {
4813         desc->opts1 |= cpu_to_le32(RingEnd);
4814 }
4815
4816 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4817 {
4818         unsigned int i;
4819
4820         for (i = 0; i < NUM_RX_DESC; i++) {
4821                 void *data;
4822
4823                 if (tp->Rx_databuff[i])
4824                         continue;
4825
4826                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4827                 if (!data) {
4828                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4829                         goto err_out;
4830                 }
4831                 tp->Rx_databuff[i] = data;
4832         }
4833
4834         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4835         return 0;
4836
4837 err_out:
4838         rtl8169_rx_clear(tp);
4839         return -ENOMEM;
4840 }
4841
4842 static int rtl8169_init_ring(struct net_device *dev)
4843 {
4844         struct rtl8169_private *tp = netdev_priv(dev);
4845
4846         rtl8169_init_ring_indexes(tp);
4847
4848         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4849         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4850
4851         return rtl8169_rx_fill(tp);
4852 }
4853
4854 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4855                                  struct TxDesc *desc)
4856 {
4857         unsigned int len = tx_skb->len;
4858
4859         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4860
4861         desc->opts1 = 0x00;
4862         desc->opts2 = 0x00;
4863         desc->addr = 0x00;
4864         tx_skb->len = 0;
4865 }
4866
4867 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4868                                    unsigned int n)
4869 {
4870         unsigned int i;
4871
4872         for (i = 0; i < n; i++) {
4873                 unsigned int entry = (start + i) % NUM_TX_DESC;
4874                 struct ring_info *tx_skb = tp->tx_skb + entry;
4875                 unsigned int len = tx_skb->len;
4876
4877                 if (len) {
4878                         struct sk_buff *skb = tx_skb->skb;
4879
4880                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4881                                              tp->TxDescArray + entry);
4882                         if (skb) {
4883                                 tp->dev->stats.tx_dropped++;
4884                                 dev_kfree_skb(skb);
4885                                 tx_skb->skb = NULL;
4886                         }
4887                 }
4888         }
4889 }
4890
4891 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4892 {
4893         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4894         tp->cur_tx = tp->dirty_tx = 0;
4895 }
4896
4897 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4898 {
4899         struct rtl8169_private *tp = netdev_priv(dev);
4900
4901         PREPARE_DELAYED_WORK(&tp->task, task);
4902         schedule_delayed_work(&tp->task, 4);
4903 }
4904
4905 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4906 {
4907         struct rtl8169_private *tp = netdev_priv(dev);
4908         void __iomem *ioaddr = tp->mmio_addr;
4909
4910         synchronize_irq(dev->irq);
4911
4912         /* Wait for any pending NAPI task to complete */
4913         napi_disable(&tp->napi);
4914
4915         rtl8169_irq_mask_and_ack(ioaddr);
4916
4917         tp->intr_mask = 0xffff;
4918         RTL_W16(IntrMask, tp->intr_event);
4919         napi_enable(&tp->napi);
4920 }
4921
4922 static void rtl8169_reinit_task(struct work_struct *work)
4923 {
4924         struct rtl8169_private *tp =
4925                 container_of(work, struct rtl8169_private, task.work);
4926         struct net_device *dev = tp->dev;
4927         int ret;
4928
4929         rtnl_lock();
4930
4931         if (!netif_running(dev))
4932                 goto out_unlock;
4933
4934         rtl8169_wait_for_quiescence(dev);
4935         rtl8169_close(dev);
4936
4937         ret = rtl8169_open(dev);
4938         if (unlikely(ret < 0)) {
4939                 if (net_ratelimit())
4940                         netif_err(tp, drv, dev,
4941                                   "reinit failure (status = %d). Rescheduling\n",
4942                                   ret);
4943                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4944         }
4945
4946 out_unlock:
4947         rtnl_unlock();
4948 }
4949
4950 static void rtl8169_reset_task(struct work_struct *work)
4951 {
4952         struct rtl8169_private *tp =
4953                 container_of(work, struct rtl8169_private, task.work);
4954         struct net_device *dev = tp->dev;
4955         int i;
4956
4957         rtnl_lock();
4958
4959         if (!netif_running(dev))
4960                 goto out_unlock;
4961
4962         rtl8169_wait_for_quiescence(dev);
4963
4964         for (i = 0; i < NUM_RX_DESC; i++)
4965                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4966
4967         rtl8169_tx_clear(tp);
4968
4969         rtl8169_hw_reset(tp);
4970         rtl_hw_start(dev);
4971         netif_wake_queue(dev);
4972         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4973
4974 out_unlock:
4975         rtnl_unlock();
4976 }
4977
4978 static void rtl8169_tx_timeout(struct net_device *dev)
4979 {
4980         struct rtl8169_private *tp = netdev_priv(dev);
4981
4982         rtl8169_hw_reset(tp);
4983
4984         /* Let's wait a bit while any (async) irq lands on */
4985         rtl8169_schedule_work(dev, rtl8169_reset_task);
4986 }
4987
4988 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4989                               u32 *opts)
4990 {
4991         struct skb_shared_info *info = skb_shinfo(skb);
4992         unsigned int cur_frag, entry;
4993         struct TxDesc * uninitialized_var(txd);
4994         struct device *d = &tp->pci_dev->dev;
4995
4996         entry = tp->cur_tx;
4997         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4998                 skb_frag_t *frag = info->frags + cur_frag;
4999                 dma_addr_t mapping;
5000                 u32 status, len;
5001                 void *addr;
5002
5003                 entry = (entry + 1) % NUM_TX_DESC;
5004
5005                 txd = tp->TxDescArray + entry;
5006                 len = frag->size;
5007                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
5008                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5009                 if (unlikely(dma_mapping_error(d, mapping))) {
5010                         if (net_ratelimit())
5011                                 netif_err(tp, drv, tp->dev,
5012                                           "Failed to map TX fragments DMA!\n");
5013                         goto err_out;
5014                 }
5015
5016                 /* Anti gcc 2.95.3 bugware (sic) */
5017                 status = opts[0] | len |
5018                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5019
5020                 txd->opts1 = cpu_to_le32(status);
5021                 txd->opts2 = cpu_to_le32(opts[1]);
5022                 txd->addr = cpu_to_le64(mapping);
5023
5024                 tp->tx_skb[entry].len = len;
5025         }
5026
5027         if (cur_frag) {
5028                 tp->tx_skb[entry].skb = skb;
5029                 txd->opts1 |= cpu_to_le32(LastFrag);
5030         }
5031
5032         return cur_frag;
5033
5034 err_out:
5035         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5036         return -EIO;
5037 }
5038
5039 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5040                                     struct sk_buff *skb, u32 *opts)
5041 {
5042         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5043         u32 mss = skb_shinfo(skb)->gso_size;
5044         int offset = info->opts_offset;
5045
5046         if (mss) {
5047                 opts[0] |= TD_LSO;
5048                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5049         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5050                 const struct iphdr *ip = ip_hdr(skb);
5051
5052                 if (ip->protocol == IPPROTO_TCP)
5053                         opts[offset] |= info->checksum.tcp;
5054                 else if (ip->protocol == IPPROTO_UDP)
5055                         opts[offset] |= info->checksum.udp;
5056                 else
5057                         WARN_ON_ONCE(1);
5058         }
5059 }
5060
5061 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5062                                       struct net_device *dev)
5063 {
5064         struct rtl8169_private *tp = netdev_priv(dev);
5065         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5066         struct TxDesc *txd = tp->TxDescArray + entry;
5067         void __iomem *ioaddr = tp->mmio_addr;
5068         struct device *d = &tp->pci_dev->dev;
5069         dma_addr_t mapping;
5070         u32 status, len;
5071         u32 opts[2];
5072         int frags;
5073
5074         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
5075                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5076                 goto err_stop_0;
5077         }
5078
5079         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5080                 goto err_stop_0;
5081
5082         len = skb_headlen(skb);
5083         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5084         if (unlikely(dma_mapping_error(d, mapping))) {
5085                 if (net_ratelimit())
5086                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5087                 goto err_dma_0;
5088         }
5089
5090         tp->tx_skb[entry].len = len;
5091         txd->addr = cpu_to_le64(mapping);
5092
5093         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5094         opts[0] = DescOwn;
5095
5096         rtl8169_tso_csum(tp, skb, opts);
5097
5098         frags = rtl8169_xmit_frags(tp, skb, opts);
5099         if (frags < 0)
5100                 goto err_dma_1;
5101         else if (frags)
5102                 opts[0] |= FirstFrag;
5103         else {
5104                 opts[0] |= FirstFrag | LastFrag;
5105                 tp->tx_skb[entry].skb = skb;
5106         }
5107
5108         txd->opts2 = cpu_to_le32(opts[1]);
5109
5110         wmb();
5111
5112         /* Anti gcc 2.95.3 bugware (sic) */
5113         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5114         txd->opts1 = cpu_to_le32(status);
5115
5116         tp->cur_tx += frags + 1;
5117
5118         wmb();
5119
5120         RTL_W8(TxPoll, NPQ);
5121
5122         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5123                 netif_stop_queue(dev);
5124                 smp_rmb();
5125                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5126                         netif_wake_queue(dev);
5127         }
5128
5129         return NETDEV_TX_OK;
5130
5131 err_dma_1:
5132         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5133 err_dma_0:
5134         dev_kfree_skb(skb);
5135         dev->stats.tx_dropped++;
5136         return NETDEV_TX_OK;
5137
5138 err_stop_0:
5139         netif_stop_queue(dev);
5140         dev->stats.tx_dropped++;
5141         return NETDEV_TX_BUSY;
5142 }
5143
5144 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5145 {
5146         struct rtl8169_private *tp = netdev_priv(dev);
5147         struct pci_dev *pdev = tp->pci_dev;
5148         u16 pci_status, pci_cmd;
5149
5150         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5151         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5152
5153         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5154                   pci_cmd, pci_status);
5155
5156         /*
5157          * The recovery sequence below admits a very elaborated explanation:
5158          * - it seems to work;
5159          * - I did not see what else could be done;
5160          * - it makes iop3xx happy.
5161          *
5162          * Feel free to adjust to your needs.
5163          */
5164         if (pdev->broken_parity_status)
5165                 pci_cmd &= ~PCI_COMMAND_PARITY;
5166         else
5167                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5168
5169         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5170
5171         pci_write_config_word(pdev, PCI_STATUS,
5172                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5173                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5174                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5175
5176         /* The infamous DAC f*ckup only happens at boot time */
5177         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5178                 void __iomem *ioaddr = tp->mmio_addr;
5179
5180                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5181                 tp->cp_cmd &= ~PCIDAC;
5182                 RTL_W16(CPlusCmd, tp->cp_cmd);
5183                 dev->features &= ~NETIF_F_HIGHDMA;
5184         }
5185
5186         rtl8169_hw_reset(tp);
5187
5188         rtl8169_schedule_work(dev, rtl8169_reinit_task);
5189 }
5190
5191 static void rtl8169_tx_interrupt(struct net_device *dev,
5192                                  struct rtl8169_private *tp,
5193                                  void __iomem *ioaddr)
5194 {
5195         unsigned int dirty_tx, tx_left;
5196
5197         dirty_tx = tp->dirty_tx;
5198         smp_rmb();
5199         tx_left = tp->cur_tx - dirty_tx;
5200
5201         while (tx_left > 0) {
5202                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5203                 struct ring_info *tx_skb = tp->tx_skb + entry;
5204                 u32 status;
5205
5206                 rmb();
5207                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5208                 if (status & DescOwn)
5209                         break;
5210
5211                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5212                                      tp->TxDescArray + entry);
5213                 if (status & LastFrag) {
5214                         dev->stats.tx_packets++;
5215                         dev->stats.tx_bytes += tx_skb->skb->len;
5216                         dev_kfree_skb(tx_skb->skb);
5217                         tx_skb->skb = NULL;
5218                 }
5219                 dirty_tx++;
5220                 tx_left--;
5221         }
5222
5223         if (tp->dirty_tx != dirty_tx) {
5224                 tp->dirty_tx = dirty_tx;
5225                 smp_wmb();
5226                 if (netif_queue_stopped(dev) &&
5227                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5228                         netif_wake_queue(dev);
5229                 }
5230                 /*
5231                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5232                  * too close. Let's kick an extra TxPoll request when a burst
5233                  * of start_xmit activity is detected (if it is not detected,
5234                  * it is slow enough). -- FR
5235                  */
5236                 smp_rmb();
5237                 if (tp->cur_tx != dirty_tx)
5238                         RTL_W8(TxPoll, NPQ);
5239         }
5240 }
5241
5242 static inline int rtl8169_fragmented_frame(u32 status)
5243 {
5244         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5245 }
5246
5247 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5248 {
5249         u32 status = opts1 & RxProtoMask;
5250
5251         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5252             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5253                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5254         else
5255                 skb_checksum_none_assert(skb);
5256 }
5257
5258 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5259                                            struct rtl8169_private *tp,
5260                                            int pkt_size,
5261                                            dma_addr_t addr)
5262 {
5263         struct sk_buff *skb;
5264         struct device *d = &tp->pci_dev->dev;
5265
5266         data = rtl8169_align(data);
5267         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5268         prefetch(data);
5269         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5270         if (skb)
5271                 memcpy(skb->data, data, pkt_size);
5272         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5273
5274         return skb;
5275 }
5276
5277 static int rtl8169_rx_interrupt(struct net_device *dev,
5278                                 struct rtl8169_private *tp,
5279                                 void __iomem *ioaddr, u32 budget)
5280 {
5281         unsigned int cur_rx, rx_left;
5282         unsigned int count;
5283
5284         cur_rx = tp->cur_rx;
5285         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5286         rx_left = min(rx_left, budget);
5287
5288         for (; rx_left > 0; rx_left--, cur_rx++) {
5289                 unsigned int entry = cur_rx % NUM_RX_DESC;
5290                 struct RxDesc *desc = tp->RxDescArray + entry;
5291                 u32 status;
5292
5293                 rmb();
5294                 status = le32_to_cpu(desc->opts1);
5295
5296                 if (status & DescOwn)
5297                         break;
5298                 if (unlikely(status & RxRES)) {
5299                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5300                                    status);
5301                         dev->stats.rx_errors++;
5302                         if (status & (RxRWT | RxRUNT))
5303                                 dev->stats.rx_length_errors++;
5304                         if (status & RxCRC)
5305                                 dev->stats.rx_crc_errors++;
5306                         if (status & RxFOVF) {
5307                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
5308                                 dev->stats.rx_fifo_errors++;
5309                         }
5310                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5311                 } else {
5312                         struct sk_buff *skb;
5313                         dma_addr_t addr = le64_to_cpu(desc->addr);
5314                         int pkt_size = (status & 0x00001FFF) - 4;
5315
5316                         /*
5317                          * The driver does not support incoming fragmented
5318                          * frames. They are seen as a symptom of over-mtu
5319                          * sized frames.
5320                          */
5321                         if (unlikely(rtl8169_fragmented_frame(status))) {
5322                                 dev->stats.rx_dropped++;
5323                                 dev->stats.rx_length_errors++;
5324                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5325                                 continue;
5326                         }
5327
5328                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5329                                                   tp, pkt_size, addr);
5330                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5331                         if (!skb) {
5332                                 dev->stats.rx_dropped++;
5333                                 continue;
5334                         }
5335
5336                         rtl8169_rx_csum(skb, status);
5337                         skb_put(skb, pkt_size);
5338                         skb->protocol = eth_type_trans(skb, dev);
5339
5340                         rtl8169_rx_vlan_tag(desc, skb);
5341
5342                         napi_gro_receive(&tp->napi, skb);
5343
5344                         dev->stats.rx_bytes += pkt_size;
5345                         dev->stats.rx_packets++;
5346                 }
5347
5348                 /* Work around for AMD plateform. */
5349                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5350                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5351                         desc->opts2 = 0;
5352                         cur_rx++;
5353                 }
5354         }
5355
5356         count = cur_rx - tp->cur_rx;
5357         tp->cur_rx = cur_rx;
5358
5359         tp->dirty_rx += count;
5360
5361         return count;
5362 }
5363
5364 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5365 {
5366         struct net_device *dev = dev_instance;
5367         struct rtl8169_private *tp = netdev_priv(dev);
5368         void __iomem *ioaddr = tp->mmio_addr;
5369         int handled = 0;
5370         int status;
5371
5372         /* loop handling interrupts until we have no new ones or
5373          * we hit a invalid/hotplug case.
5374          */
5375         status = RTL_R16(IntrStatus);
5376         while (status && status != 0xffff) {
5377                 handled = 1;
5378
5379                 /* Handle all of the error cases first. These will reset
5380                  * the chip, so just exit the loop.
5381                  */
5382                 if (unlikely(!netif_running(dev))) {
5383                         rtl8169_hw_reset(tp);
5384                         break;
5385                 }
5386
5387                 if (unlikely(status & RxFIFOOver)) {
5388                         switch (tp->mac_version) {
5389                         /* Work around for rx fifo overflow */
5390                         case RTL_GIGA_MAC_VER_11:
5391                         case RTL_GIGA_MAC_VER_22:
5392                         case RTL_GIGA_MAC_VER_26:
5393                                 netif_stop_queue(dev);
5394                                 rtl8169_tx_timeout(dev);
5395                                 goto done;
5396                         /* Testers needed. */
5397                         case RTL_GIGA_MAC_VER_17:
5398                         case RTL_GIGA_MAC_VER_19:
5399                         case RTL_GIGA_MAC_VER_20:
5400                         case RTL_GIGA_MAC_VER_21:
5401                         case RTL_GIGA_MAC_VER_23:
5402                         case RTL_GIGA_MAC_VER_24:
5403                         case RTL_GIGA_MAC_VER_27:
5404                         case RTL_GIGA_MAC_VER_28:
5405                         case RTL_GIGA_MAC_VER_31:
5406                         /* Experimental science. Pktgen proof. */
5407                         case RTL_GIGA_MAC_VER_12:
5408                         case RTL_GIGA_MAC_VER_25:
5409                                 if (status == RxFIFOOver)
5410                                         goto done;
5411                                 break;
5412                         default:
5413                                 break;
5414                         }
5415                 }
5416
5417                 if (unlikely(status & SYSErr)) {
5418                         rtl8169_pcierr_interrupt(dev);
5419                         break;
5420                 }
5421
5422                 if (status & LinkChg)
5423                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5424
5425                 /* We need to see the lastest version of tp->intr_mask to
5426                  * avoid ignoring an MSI interrupt and having to wait for
5427                  * another event which may never come.
5428                  */
5429                 smp_rmb();
5430                 if (status & tp->intr_mask & tp->napi_event) {
5431                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5432                         tp->intr_mask = ~tp->napi_event;
5433
5434                         if (likely(napi_schedule_prep(&tp->napi)))
5435                                 __napi_schedule(&tp->napi);
5436                         else
5437                                 netif_info(tp, intr, dev,
5438                                            "interrupt %04x in poll\n", status);
5439                 }
5440
5441                 /* We only get a new MSI interrupt when all active irq
5442                  * sources on the chip have been acknowledged. So, ack
5443                  * everything we've seen and check if new sources have become
5444                  * active to avoid blocking all interrupts from the chip.
5445                  */
5446                 RTL_W16(IntrStatus,
5447                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5448                 status = RTL_R16(IntrStatus);
5449         }
5450 done:
5451         return IRQ_RETVAL(handled);
5452 }
5453
5454 static int rtl8169_poll(struct napi_struct *napi, int budget)
5455 {
5456         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5457         struct net_device *dev = tp->dev;
5458         void __iomem *ioaddr = tp->mmio_addr;
5459         int work_done;
5460
5461         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5462         rtl8169_tx_interrupt(dev, tp, ioaddr);
5463
5464         if (work_done < budget) {
5465                 napi_complete(napi);
5466
5467                 /* We need for force the visibility of tp->intr_mask
5468                  * for other CPUs, as we can loose an MSI interrupt
5469                  * and potentially wait for a retransmit timeout if we don't.
5470                  * The posted write to IntrMask is safe, as it will
5471                  * eventually make it to the chip and we won't loose anything
5472                  * until it does.
5473                  */
5474                 tp->intr_mask = 0xffff;
5475                 wmb();
5476                 RTL_W16(IntrMask, tp->intr_event);
5477         }
5478
5479         return work_done;
5480 }
5481
5482 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5483 {
5484         struct rtl8169_private *tp = netdev_priv(dev);
5485
5486         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5487                 return;
5488
5489         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5490         RTL_W32(RxMissed, 0);
5491 }
5492
5493 static void rtl8169_down(struct net_device *dev)
5494 {
5495         struct rtl8169_private *tp = netdev_priv(dev);
5496         void __iomem *ioaddr = tp->mmio_addr;
5497
5498         del_timer_sync(&tp->timer);
5499
5500         netif_stop_queue(dev);
5501
5502         napi_disable(&tp->napi);
5503
5504         spin_lock_irq(&tp->lock);
5505
5506         rtl8169_hw_reset(tp);
5507         /*
5508          * At this point device interrupts can not be enabled in any function,
5509          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5510          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5511          */
5512         rtl8169_rx_missed(dev, ioaddr);
5513
5514         spin_unlock_irq(&tp->lock);
5515
5516         synchronize_irq(dev->irq);
5517
5518         /* Give a racing hard_start_xmit a few cycles to complete. */
5519         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5520
5521         rtl8169_tx_clear(tp);
5522
5523         rtl8169_rx_clear(tp);
5524
5525         rtl_pll_power_down(tp);
5526 }
5527
5528 static int rtl8169_close(struct net_device *dev)
5529 {
5530         struct rtl8169_private *tp = netdev_priv(dev);
5531         struct pci_dev *pdev = tp->pci_dev;
5532
5533         pm_runtime_get_sync(&pdev->dev);
5534
5535         /* Update counters before going down */
5536         rtl8169_update_counters(dev);
5537
5538         rtl8169_down(dev);
5539
5540         free_irq(dev->irq, dev);
5541
5542         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5543                           tp->RxPhyAddr);
5544         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5545                           tp->TxPhyAddr);
5546         tp->TxDescArray = NULL;
5547         tp->RxDescArray = NULL;
5548
5549         pm_runtime_put_sync(&pdev->dev);
5550
5551         return 0;
5552 }
5553
5554 static void rtl_set_rx_mode(struct net_device *dev)
5555 {
5556         struct rtl8169_private *tp = netdev_priv(dev);
5557         void __iomem *ioaddr = tp->mmio_addr;
5558         unsigned long flags;
5559         u32 mc_filter[2];       /* Multicast hash filter */
5560         int rx_mode;
5561         u32 tmp = 0;
5562
5563         if (dev->flags & IFF_PROMISC) {
5564                 /* Unconditionally log net taps. */
5565                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5566                 rx_mode =
5567                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5568                     AcceptAllPhys;
5569                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5570         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5571                    (dev->flags & IFF_ALLMULTI)) {
5572                 /* Too many to filter perfectly -- accept all multicasts. */
5573                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5574                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5575         } else {
5576                 struct netdev_hw_addr *ha;
5577
5578                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5579                 mc_filter[1] = mc_filter[0] = 0;
5580                 netdev_for_each_mc_addr(ha, dev) {
5581                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5582                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5583                         rx_mode |= AcceptMulticast;
5584                 }
5585         }
5586
5587         spin_lock_irqsave(&tp->lock, flags);
5588
5589         tmp = RTL_R32(RxConfig) | rx_mode;
5590
5591         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5592                 u32 data = mc_filter[0];
5593
5594                 mc_filter[0] = swab32(mc_filter[1]);
5595                 mc_filter[1] = swab32(data);
5596         }
5597
5598         RTL_W32(MAR0 + 4, mc_filter[1]);
5599         RTL_W32(MAR0 + 0, mc_filter[0]);
5600
5601         RTL_W32(RxConfig, tmp);
5602
5603         spin_unlock_irqrestore(&tp->lock, flags);
5604 }
5605
5606 /**
5607  *  rtl8169_get_stats - Get rtl8169 read/write statistics
5608  *  @dev: The Ethernet Device to get statistics for
5609  *
5610  *  Get TX/RX statistics for rtl8169
5611  */
5612 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5613 {
5614         struct rtl8169_private *tp = netdev_priv(dev);
5615         void __iomem *ioaddr = tp->mmio_addr;
5616         unsigned long flags;
5617
5618         if (netif_running(dev)) {
5619                 spin_lock_irqsave(&tp->lock, flags);
5620                 rtl8169_rx_missed(dev, ioaddr);
5621                 spin_unlock_irqrestore(&tp->lock, flags);
5622         }
5623
5624         return &dev->stats;
5625 }
5626
5627 static void rtl8169_net_suspend(struct net_device *dev)
5628 {
5629         struct rtl8169_private *tp = netdev_priv(dev);
5630
5631         if (!netif_running(dev))
5632                 return;
5633
5634         rtl_pll_power_down(tp);
5635
5636         netif_device_detach(dev);
5637         netif_stop_queue(dev);
5638 }
5639
5640 #ifdef CONFIG_PM
5641
5642 static int rtl8169_suspend(struct device *device)
5643 {
5644         struct pci_dev *pdev = to_pci_dev(device);
5645         struct net_device *dev = pci_get_drvdata(pdev);
5646
5647         rtl8169_net_suspend(dev);
5648
5649         return 0;
5650 }
5651
5652 static void __rtl8169_resume(struct net_device *dev)
5653 {
5654         struct rtl8169_private *tp = netdev_priv(dev);
5655
5656         netif_device_attach(dev);
5657
5658         rtl_pll_power_up(tp);
5659
5660         rtl8169_schedule_work(dev, rtl8169_reset_task);
5661 }
5662
5663 static int rtl8169_resume(struct device *device)
5664 {
5665         struct pci_dev *pdev = to_pci_dev(device);
5666         struct net_device *dev = pci_get_drvdata(pdev);
5667         struct rtl8169_private *tp = netdev_priv(dev);
5668
5669         rtl8169_init_phy(dev, tp);
5670
5671         if (netif_running(dev))
5672                 __rtl8169_resume(dev);
5673
5674         return 0;
5675 }
5676
5677 static int rtl8169_runtime_suspend(struct device *device)
5678 {
5679         struct pci_dev *pdev = to_pci_dev(device);
5680         struct net_device *dev = pci_get_drvdata(pdev);
5681         struct rtl8169_private *tp = netdev_priv(dev);
5682
5683         if (!tp->TxDescArray)
5684                 return 0;
5685
5686         spin_lock_irq(&tp->lock);
5687         tp->saved_wolopts = __rtl8169_get_wol(tp);
5688         __rtl8169_set_wol(tp, WAKE_ANY);
5689         spin_unlock_irq(&tp->lock);
5690
5691         rtl8169_net_suspend(dev);
5692
5693         return 0;
5694 }
5695
5696 static int rtl8169_runtime_resume(struct device *device)
5697 {
5698         struct pci_dev *pdev = to_pci_dev(device);
5699         struct net_device *dev = pci_get_drvdata(pdev);
5700         struct rtl8169_private *tp = netdev_priv(dev);
5701
5702         if (!tp->TxDescArray)
5703                 return 0;
5704
5705         spin_lock_irq(&tp->lock);
5706         __rtl8169_set_wol(tp, tp->saved_wolopts);
5707         tp->saved_wolopts = 0;
5708         spin_unlock_irq(&tp->lock);
5709
5710         rtl8169_init_phy(dev, tp);
5711
5712         __rtl8169_resume(dev);
5713
5714         return 0;
5715 }
5716
5717 static int rtl8169_runtime_idle(struct device *device)
5718 {
5719         struct pci_dev *pdev = to_pci_dev(device);
5720         struct net_device *dev = pci_get_drvdata(pdev);
5721         struct rtl8169_private *tp = netdev_priv(dev);
5722
5723         return tp->TxDescArray ? -EBUSY : 0;
5724 }
5725
5726 static const struct dev_pm_ops rtl8169_pm_ops = {
5727         .suspend                = rtl8169_suspend,
5728         .resume                 = rtl8169_resume,
5729         .freeze                 = rtl8169_suspend,
5730         .thaw                   = rtl8169_resume,
5731         .poweroff               = rtl8169_suspend,
5732         .restore                = rtl8169_resume,
5733         .runtime_suspend        = rtl8169_runtime_suspend,
5734         .runtime_resume         = rtl8169_runtime_resume,
5735         .runtime_idle           = rtl8169_runtime_idle,
5736 };
5737
5738 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5739
5740 #else /* !CONFIG_PM */
5741
5742 #define RTL8169_PM_OPS  NULL
5743
5744 #endif /* !CONFIG_PM */
5745
5746 static void rtl_shutdown(struct pci_dev *pdev)
5747 {
5748         struct net_device *dev = pci_get_drvdata(pdev);
5749         struct rtl8169_private *tp = netdev_priv(dev);
5750         void __iomem *ioaddr = tp->mmio_addr;
5751
5752         rtl8169_net_suspend(dev);
5753
5754         /* Restore original MAC address */
5755         rtl_rar_set(tp, dev->perm_addr);
5756
5757         spin_lock_irq(&tp->lock);
5758
5759         rtl8169_hw_reset(tp);
5760
5761         spin_unlock_irq(&tp->lock);
5762
5763         if (system_state == SYSTEM_POWER_OFF) {
5764                 /* WoL fails with 8168b when the receiver is disabled. */
5765                 if ((tp->mac_version == RTL_GIGA_MAC_VER_11 ||
5766                      tp->mac_version == RTL_GIGA_MAC_VER_12 ||
5767                      tp->mac_version == RTL_GIGA_MAC_VER_17) &&
5768                     (tp->features & RTL_FEATURE_WOL)) {
5769                         pci_clear_master(pdev);
5770
5771                         RTL_W8(ChipCmd, CmdRxEnb);
5772                         /* PCI commit */
5773                         RTL_R8(ChipCmd);
5774                 }
5775
5776                 pci_wake_from_d3(pdev, true);
5777                 pci_set_power_state(pdev, PCI_D3hot);
5778         }
5779 }
5780
5781 static struct pci_driver rtl8169_pci_driver = {
5782         .name           = MODULENAME,
5783         .id_table       = rtl8169_pci_tbl,
5784         .probe          = rtl8169_init_one,
5785         .remove         = __devexit_p(rtl8169_remove_one),
5786         .shutdown       = rtl_shutdown,
5787         .driver.pm      = RTL8169_PM_OPS,
5788 };
5789
5790 static int __init rtl8169_init_module(void)
5791 {
5792         return pci_register_driver(&rtl8169_pci_driver);
5793 }
5794
5795 static void __exit rtl8169_cleanup_module(void)
5796 {
5797         pci_unregister_driver(&rtl8169_pci_driver);
5798 }
5799
5800 module_init(rtl8169_init_module);
5801 module_exit(rtl8169_cleanup_module);