Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6.git] / drivers / net / r8169.c
1 /*
2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3  *
4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6  * Copyright (c) a lot of people too. Please respect their work.
7  *
8  * See MAINTAINERS file for support contact information.
9  */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
31
32 #include <asm/system.h>
33 #include <asm/io.h>
34 #include <asm/irq.h>
35
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
39
40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
45
46 #ifdef RTL8169_DEBUG
47 #define assert(expr) \
48         if (!(expr)) {                                  \
49                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
50                 #expr,__FILE__,__func__,__LINE__);              \
51         }
52 #define dprintk(fmt, args...) \
53         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
54 #else
55 #define assert(expr) do {} while (0)
56 #define dprintk(fmt, args...)   do {} while (0)
57 #endif /* RTL8169_DEBUG */
58
59 #define R8169_MSG_DEFAULT \
60         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
61
62 #define TX_BUFFS_AVAIL(tp) \
63         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
64
65 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
66    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
67 static const int multicast_filter_limit = 32;
68
69 /* MAC address length */
70 #define MAC_ADDR_LEN    6
71
72 #define MAX_READ_REQUEST_SHIFT  12
73 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
74 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
75 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
76 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
77 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
78
79 #define R8169_REGS_SIZE         256
80 #define R8169_NAPI_WEIGHT       64
81 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
82 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
83 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
84 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
85 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
86
87 #define RTL8169_TX_TIMEOUT      (6*HZ)
88 #define RTL8169_PHY_TIMEOUT     (10*HZ)
89
90 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
91 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
92 #define RTL_EEPROM_SIG_ADDR     0x0000
93
94 /* write/read MMIO register */
95 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
96 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
97 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
98 #define RTL_R8(reg)             readb (ioaddr + (reg))
99 #define RTL_R16(reg)            readw (ioaddr + (reg))
100 #define RTL_R32(reg)            readl (ioaddr + (reg))
101
102 enum mac_version {
103         RTL_GIGA_MAC_VER_01 = 0,
104         RTL_GIGA_MAC_VER_02,
105         RTL_GIGA_MAC_VER_03,
106         RTL_GIGA_MAC_VER_04,
107         RTL_GIGA_MAC_VER_05,
108         RTL_GIGA_MAC_VER_06,
109         RTL_GIGA_MAC_VER_07,
110         RTL_GIGA_MAC_VER_08,
111         RTL_GIGA_MAC_VER_09,
112         RTL_GIGA_MAC_VER_10,
113         RTL_GIGA_MAC_VER_11,
114         RTL_GIGA_MAC_VER_12,
115         RTL_GIGA_MAC_VER_13,
116         RTL_GIGA_MAC_VER_14,
117         RTL_GIGA_MAC_VER_15,
118         RTL_GIGA_MAC_VER_16,
119         RTL_GIGA_MAC_VER_17,
120         RTL_GIGA_MAC_VER_18,
121         RTL_GIGA_MAC_VER_19,
122         RTL_GIGA_MAC_VER_20,
123         RTL_GIGA_MAC_VER_21,
124         RTL_GIGA_MAC_VER_22,
125         RTL_GIGA_MAC_VER_23,
126         RTL_GIGA_MAC_VER_24,
127         RTL_GIGA_MAC_VER_25,
128         RTL_GIGA_MAC_VER_26,
129         RTL_GIGA_MAC_VER_27,
130         RTL_GIGA_MAC_VER_28,
131         RTL_GIGA_MAC_VER_29,
132         RTL_GIGA_MAC_VER_30,
133         RTL_GIGA_MAC_VER_31,
134         RTL_GIGA_MAC_VER_32,
135         RTL_GIGA_MAC_VER_33,
136         RTL_GIGA_MAC_NONE   = 0xff,
137 };
138
139 enum rtl_tx_desc_version {
140         RTL_TD_0        = 0,
141         RTL_TD_1        = 1,
142 };
143
144 #define _R(NAME,TD,FW) \
145         { .name = NAME, .txd_version = TD, .fw_name = FW }
146
147 static const struct {
148         const char *name;
149         enum rtl_tx_desc_version txd_version;
150         const char *fw_name;
151 } rtl_chip_infos[] = {
152         /* PCI devices. */
153         [RTL_GIGA_MAC_VER_01] =
154                 _R("RTL8169",           RTL_TD_0, NULL),
155         [RTL_GIGA_MAC_VER_02] =
156                 _R("RTL8169s",          RTL_TD_0, NULL),
157         [RTL_GIGA_MAC_VER_03] =
158                 _R("RTL8110s",          RTL_TD_0, NULL),
159         [RTL_GIGA_MAC_VER_04] =
160                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL),
161         [RTL_GIGA_MAC_VER_05] =
162                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
163         [RTL_GIGA_MAC_VER_06] =
164                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
165         /* PCI-E devices. */
166         [RTL_GIGA_MAC_VER_07] =
167                 _R("RTL8102e",          RTL_TD_1, NULL),
168         [RTL_GIGA_MAC_VER_08] =
169                 _R("RTL8102e",          RTL_TD_1, NULL),
170         [RTL_GIGA_MAC_VER_09] =
171                 _R("RTL8102e",          RTL_TD_1, NULL),
172         [RTL_GIGA_MAC_VER_10] =
173                 _R("RTL8101e",          RTL_TD_0, NULL),
174         [RTL_GIGA_MAC_VER_11] =
175                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
176         [RTL_GIGA_MAC_VER_12] =
177                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
178         [RTL_GIGA_MAC_VER_13] =
179                 _R("RTL8101e",          RTL_TD_0, NULL),
180         [RTL_GIGA_MAC_VER_14] =
181                 _R("RTL8100e",          RTL_TD_0, NULL),
182         [RTL_GIGA_MAC_VER_15] =
183                 _R("RTL8100e",          RTL_TD_0, NULL),
184         [RTL_GIGA_MAC_VER_16] =
185                 _R("RTL8101e",          RTL_TD_0, NULL),
186         [RTL_GIGA_MAC_VER_17] =
187                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
188         [RTL_GIGA_MAC_VER_18] =
189                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
190         [RTL_GIGA_MAC_VER_19] =
191                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
192         [RTL_GIGA_MAC_VER_20] =
193                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
194         [RTL_GIGA_MAC_VER_21] =
195                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
196         [RTL_GIGA_MAC_VER_22] =
197                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
198         [RTL_GIGA_MAC_VER_23] =
199                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
200         [RTL_GIGA_MAC_VER_24] =
201                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
202         [RTL_GIGA_MAC_VER_25] =
203                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1),
204         [RTL_GIGA_MAC_VER_26] =
205                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2),
206         [RTL_GIGA_MAC_VER_27] =
207                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
208         [RTL_GIGA_MAC_VER_28] =
209                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
210         [RTL_GIGA_MAC_VER_29] =
211                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
212         [RTL_GIGA_MAC_VER_30] =
213                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
214         [RTL_GIGA_MAC_VER_31] =
215                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
216         [RTL_GIGA_MAC_VER_32] =
217                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1),
218         [RTL_GIGA_MAC_VER_33] =
219                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2)
220 };
221 #undef _R
222
223 enum cfg_version {
224         RTL_CFG_0 = 0x00,
225         RTL_CFG_1,
226         RTL_CFG_2
227 };
228
229 static void rtl_hw_start_8169(struct net_device *);
230 static void rtl_hw_start_8168(struct net_device *);
231 static void rtl_hw_start_8101(struct net_device *);
232
233 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
234         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
235         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
236         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
237         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
238         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
239         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
240         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
241         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
242         { PCI_VENDOR_ID_LINKSYS,                0x1032,
243                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
244         { 0x0001,                               0x8168,
245                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
246         {0,},
247 };
248
249 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
250
251 static int rx_buf_sz = 16383;
252 static int use_dac;
253 static struct {
254         u32 msg_enable;
255 } debug = { -1 };
256
257 enum rtl_registers {
258         MAC0            = 0,    /* Ethernet hardware address. */
259         MAC4            = 4,
260         MAR0            = 8,    /* Multicast filter. */
261         CounterAddrLow          = 0x10,
262         CounterAddrHigh         = 0x14,
263         TxDescStartAddrLow      = 0x20,
264         TxDescStartAddrHigh     = 0x24,
265         TxHDescStartAddrLow     = 0x28,
266         TxHDescStartAddrHigh    = 0x2c,
267         FLASH           = 0x30,
268         ERSR            = 0x36,
269         ChipCmd         = 0x37,
270         TxPoll          = 0x38,
271         IntrMask        = 0x3c,
272         IntrStatus      = 0x3e,
273         TxConfig        = 0x40,
274         RxConfig        = 0x44,
275
276 #define RTL_RX_CONFIG_MASK              0xff7e1880u
277
278         RxMissed        = 0x4c,
279         Cfg9346         = 0x50,
280         Config0         = 0x51,
281         Config1         = 0x52,
282         Config2         = 0x53,
283         Config3         = 0x54,
284         Config4         = 0x55,
285         Config5         = 0x56,
286         MultiIntr       = 0x5c,
287         PHYAR           = 0x60,
288         PHYstatus       = 0x6c,
289         RxMaxSize       = 0xda,
290         CPlusCmd        = 0xe0,
291         IntrMitigate    = 0xe2,
292         RxDescAddrLow   = 0xe4,
293         RxDescAddrHigh  = 0xe8,
294         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
295
296 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
297
298         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
299
300 #define TxPacketMax     (8064 >> 7)
301
302         FuncEvent       = 0xf0,
303         FuncEventMask   = 0xf4,
304         FuncPresetState = 0xf8,
305         FuncForceEvent  = 0xfc,
306 };
307
308 enum rtl8110_registers {
309         TBICSR                  = 0x64,
310         TBI_ANAR                = 0x68,
311         TBI_LPAR                = 0x6a,
312 };
313
314 enum rtl8168_8101_registers {
315         CSIDR                   = 0x64,
316         CSIAR                   = 0x68,
317 #define CSIAR_FLAG                      0x80000000
318 #define CSIAR_WRITE_CMD                 0x80000000
319 #define CSIAR_BYTE_ENABLE               0x0f
320 #define CSIAR_BYTE_ENABLE_SHIFT         12
321 #define CSIAR_ADDR_MASK                 0x0fff
322         PMCH                    = 0x6f,
323         EPHYAR                  = 0x80,
324 #define EPHYAR_FLAG                     0x80000000
325 #define EPHYAR_WRITE_CMD                0x80000000
326 #define EPHYAR_REG_MASK                 0x1f
327 #define EPHYAR_REG_SHIFT                16
328 #define EPHYAR_DATA_MASK                0xffff
329         DLLPR                   = 0xd0,
330 #define PM_SWITCH                       (1 << 6)
331         DBG_REG                 = 0xd1,
332 #define FIX_NAK_1                       (1 << 4)
333 #define FIX_NAK_2                       (1 << 3)
334         TWSI                    = 0xd2,
335         MCU                     = 0xd3,
336 #define EN_NDP                          (1 << 3)
337 #define EN_OOB_RESET                    (1 << 2)
338         EFUSEAR                 = 0xdc,
339 #define EFUSEAR_FLAG                    0x80000000
340 #define EFUSEAR_WRITE_CMD               0x80000000
341 #define EFUSEAR_READ_CMD                0x00000000
342 #define EFUSEAR_REG_MASK                0x03ff
343 #define EFUSEAR_REG_SHIFT               8
344 #define EFUSEAR_DATA_MASK               0xff
345 };
346
347 enum rtl8168_registers {
348         ERIDR                   = 0x70,
349         ERIAR                   = 0x74,
350 #define ERIAR_FLAG                      0x80000000
351 #define ERIAR_WRITE_CMD                 0x80000000
352 #define ERIAR_READ_CMD                  0x00000000
353 #define ERIAR_ADDR_BYTE_ALIGN           4
354 #define ERIAR_EXGMAC                    0
355 #define ERIAR_MSIX                      1
356 #define ERIAR_ASF                       2
357 #define ERIAR_TYPE_SHIFT                16
358 #define ERIAR_BYTEEN                    0x0f
359 #define ERIAR_BYTEEN_SHIFT              12
360         EPHY_RXER_NUM           = 0x7c,
361         OCPDR                   = 0xb0, /* OCP GPHY access */
362 #define OCPDR_WRITE_CMD                 0x80000000
363 #define OCPDR_READ_CMD                  0x00000000
364 #define OCPDR_REG_MASK                  0x7f
365 #define OCPDR_GPHY_REG_SHIFT            16
366 #define OCPDR_DATA_MASK                 0xffff
367         OCPAR                   = 0xb4,
368 #define OCPAR_FLAG                      0x80000000
369 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
370 #define OCPAR_GPHY_READ_CMD             0x0000f060
371         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
372         MISC                    = 0xf0, /* 8168e only. */
373 #define TXPLA_RST                       (1 << 29)
374 };
375
376 enum rtl_register_content {
377         /* InterruptStatusBits */
378         SYSErr          = 0x8000,
379         PCSTimeout      = 0x4000,
380         SWInt           = 0x0100,
381         TxDescUnavail   = 0x0080,
382         RxFIFOOver      = 0x0040,
383         LinkChg         = 0x0020,
384         RxOverflow      = 0x0010,
385         TxErr           = 0x0008,
386         TxOK            = 0x0004,
387         RxErr           = 0x0002,
388         RxOK            = 0x0001,
389
390         /* RxStatusDesc */
391         RxFOVF  = (1 << 23),
392         RxRWT   = (1 << 22),
393         RxRES   = (1 << 21),
394         RxRUNT  = (1 << 20),
395         RxCRC   = (1 << 19),
396
397         /* ChipCmdBits */
398         CmdReset        = 0x10,
399         CmdRxEnb        = 0x08,
400         CmdTxEnb        = 0x04,
401         RxBufEmpty      = 0x01,
402
403         /* TXPoll register p.5 */
404         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
405         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
406         FSWInt          = 0x01,         /* Forced software interrupt */
407
408         /* Cfg9346Bits */
409         Cfg9346_Lock    = 0x00,
410         Cfg9346_Unlock  = 0xc0,
411
412         /* rx_mode_bits */
413         AcceptErr       = 0x20,
414         AcceptRunt      = 0x10,
415         AcceptBroadcast = 0x08,
416         AcceptMulticast = 0x04,
417         AcceptMyPhys    = 0x02,
418         AcceptAllPhys   = 0x01,
419
420         /* RxConfigBits */
421         RxCfgFIFOShift  = 13,
422         RxCfgDMAShift   =  8,
423
424         /* TxConfigBits */
425         TxInterFrameGapShift = 24,
426         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
427
428         /* Config1 register p.24 */
429         LEDS1           = (1 << 7),
430         LEDS0           = (1 << 6),
431         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
432         Speed_down      = (1 << 4),
433         MEMMAP          = (1 << 3),
434         IOMAP           = (1 << 2),
435         VPD             = (1 << 1),
436         PMEnable        = (1 << 0),     /* Power Management Enable */
437
438         /* Config2 register p. 25 */
439         PCI_Clock_66MHz = 0x01,
440         PCI_Clock_33MHz = 0x00,
441
442         /* Config3 register p.25 */
443         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
444         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
445         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
446
447         /* Config5 register p.27 */
448         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
449         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
450         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
451         Spi_en          = (1 << 3),
452         LanWake         = (1 << 1),     /* LanWake enable/disable */
453         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
454
455         /* TBICSR p.28 */
456         TBIReset        = 0x80000000,
457         TBILoopback     = 0x40000000,
458         TBINwEnable     = 0x20000000,
459         TBINwRestart    = 0x10000000,
460         TBILinkOk       = 0x02000000,
461         TBINwComplete   = 0x01000000,
462
463         /* CPlusCmd p.31 */
464         EnableBist      = (1 << 15),    // 8168 8101
465         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
466         Normal_mode     = (1 << 13),    // unused
467         Force_half_dup  = (1 << 12),    // 8168 8101
468         Force_rxflow_en = (1 << 11),    // 8168 8101
469         Force_txflow_en = (1 << 10),    // 8168 8101
470         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
471         ASF             = (1 << 8),     // 8168 8101
472         PktCntrDisable  = (1 << 7),     // 8168 8101
473         Mac_dbgo_sel    = 0x001c,       // 8168
474         RxVlan          = (1 << 6),
475         RxChkSum        = (1 << 5),
476         PCIDAC          = (1 << 4),
477         PCIMulRW        = (1 << 3),
478         INTT_0          = 0x0000,       // 8168
479         INTT_1          = 0x0001,       // 8168
480         INTT_2          = 0x0002,       // 8168
481         INTT_3          = 0x0003,       // 8168
482
483         /* rtl8169_PHYstatus */
484         TBI_Enable      = 0x80,
485         TxFlowCtrl      = 0x40,
486         RxFlowCtrl      = 0x20,
487         _1000bpsF       = 0x10,
488         _100bps         = 0x08,
489         _10bps          = 0x04,
490         LinkStatus      = 0x02,
491         FullDup         = 0x01,
492
493         /* _TBICSRBit */
494         TBILinkOK       = 0x02000000,
495
496         /* DumpCounterCommand */
497         CounterDump     = 0x8,
498 };
499
500 enum rtl_desc_bit {
501         /* First doubleword. */
502         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
503         RingEnd         = (1 << 30), /* End of descriptor ring */
504         FirstFrag       = (1 << 29), /* First segment of a packet */
505         LastFrag        = (1 << 28), /* Final segment of a packet */
506 };
507
508 /* Generic case. */
509 enum rtl_tx_desc_bit {
510         /* First doubleword. */
511         TD_LSO          = (1 << 27),            /* Large Send Offload */
512 #define TD_MSS_MAX                      0x07ffu /* MSS value */
513
514         /* Second doubleword. */
515         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
516 };
517
518 /* 8169, 8168b and 810x except 8102e. */
519 enum rtl_tx_desc_bit_0 {
520         /* First doubleword. */
521 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
522         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
523         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
524         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
525 };
526
527 /* 8102e, 8168c and beyond. */
528 enum rtl_tx_desc_bit_1 {
529         /* Second doubleword. */
530 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
531         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
532         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
533         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
534 };
535
536 static const struct rtl_tx_desc_info {
537         struct {
538                 u32 udp;
539                 u32 tcp;
540         } checksum;
541         u16 mss_shift;
542         u16 opts_offset;
543 } tx_desc_info [] = {
544         [RTL_TD_0] = {
545                 .checksum = {
546                         .udp    = TD0_IP_CS | TD0_UDP_CS,
547                         .tcp    = TD0_IP_CS | TD0_TCP_CS
548                 },
549                 .mss_shift      = TD0_MSS_SHIFT,
550                 .opts_offset    = 0
551         },
552         [RTL_TD_1] = {
553                 .checksum = {
554                         .udp    = TD1_IP_CS | TD1_UDP_CS,
555                         .tcp    = TD1_IP_CS | TD1_TCP_CS
556                 },
557                 .mss_shift      = TD1_MSS_SHIFT,
558                 .opts_offset    = 1
559         }
560 };
561
562 enum rtl_rx_desc_bit {
563         /* Rx private */
564         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
565         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
566
567 #define RxProtoUDP      (PID1)
568 #define RxProtoTCP      (PID0)
569 #define RxProtoIP       (PID1 | PID0)
570 #define RxProtoMask     RxProtoIP
571
572         IPFail          = (1 << 16), /* IP checksum failed */
573         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
574         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
575         RxVlanTag       = (1 << 16), /* VLAN tag available */
576 };
577
578 #define RsvdMask        0x3fffc000
579
580 struct TxDesc {
581         __le32 opts1;
582         __le32 opts2;
583         __le64 addr;
584 };
585
586 struct RxDesc {
587         __le32 opts1;
588         __le32 opts2;
589         __le64 addr;
590 };
591
592 struct ring_info {
593         struct sk_buff  *skb;
594         u32             len;
595         u8              __pad[sizeof(void *) - sizeof(u32)];
596 };
597
598 enum features {
599         RTL_FEATURE_WOL         = (1 << 0),
600         RTL_FEATURE_MSI         = (1 << 1),
601         RTL_FEATURE_GMII        = (1 << 2),
602 };
603
604 struct rtl8169_counters {
605         __le64  tx_packets;
606         __le64  rx_packets;
607         __le64  tx_errors;
608         __le32  rx_errors;
609         __le16  rx_missed;
610         __le16  align_errors;
611         __le32  tx_one_collision;
612         __le32  tx_multi_collision;
613         __le64  rx_unicast;
614         __le64  rx_broadcast;
615         __le32  rx_multicast;
616         __le16  tx_aborted;
617         __le16  tx_underun;
618 };
619
620 struct rtl8169_private {
621         void __iomem *mmio_addr;        /* memory map physical address */
622         struct pci_dev *pci_dev;
623         struct net_device *dev;
624         struct napi_struct napi;
625         spinlock_t lock;
626         u32 msg_enable;
627         u16 txd_version;
628         u16 mac_version;
629         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
630         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
631         u32 dirty_rx;
632         u32 dirty_tx;
633         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
634         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
635         dma_addr_t TxPhyAddr;
636         dma_addr_t RxPhyAddr;
637         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
638         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
639         struct timer_list timer;
640         u16 cp_cmd;
641         u16 intr_event;
642         u16 napi_event;
643         u16 intr_mask;
644
645         struct mdio_ops {
646                 void (*write)(void __iomem *, int, int);
647                 int (*read)(void __iomem *, int);
648         } mdio_ops;
649
650         struct pll_power_ops {
651                 void (*down)(struct rtl8169_private *);
652                 void (*up)(struct rtl8169_private *);
653         } pll_power_ops;
654
655         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
656         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
657         void (*phy_reset_enable)(struct rtl8169_private *tp);
658         void (*hw_start)(struct net_device *);
659         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
660         unsigned int (*link_ok)(void __iomem *);
661         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
662         struct delayed_work task;
663         unsigned features;
664
665         struct mii_if_info mii;
666         struct rtl8169_counters counters;
667         u32 saved_wolopts;
668
669         struct rtl_fw {
670                 const struct firmware *fw;
671
672 #define RTL_VER_SIZE            32
673
674                 char version[RTL_VER_SIZE];
675
676                 struct rtl_fw_phy_action {
677                         __le32 *code;
678                         size_t size;
679                 } phy_action;
680         } *rtl_fw;
681 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN);
682 };
683
684 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
685 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
686 module_param(use_dac, int, 0);
687 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
688 module_param_named(debug, debug.msg_enable, int, 0);
689 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
690 MODULE_LICENSE("GPL");
691 MODULE_VERSION(RTL8169_VERSION);
692 MODULE_FIRMWARE(FIRMWARE_8168D_1);
693 MODULE_FIRMWARE(FIRMWARE_8168D_2);
694 MODULE_FIRMWARE(FIRMWARE_8168E_1);
695 MODULE_FIRMWARE(FIRMWARE_8168E_2);
696 MODULE_FIRMWARE(FIRMWARE_8105E_1);
697
698 static int rtl8169_open(struct net_device *dev);
699 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
700                                       struct net_device *dev);
701 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
702 static int rtl8169_init_ring(struct net_device *dev);
703 static void rtl_hw_start(struct net_device *dev);
704 static int rtl8169_close(struct net_device *dev);
705 static void rtl_set_rx_mode(struct net_device *dev);
706 static void rtl8169_tx_timeout(struct net_device *dev);
707 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
708 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
709                                 void __iomem *, u32 budget);
710 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
711 static void rtl8169_down(struct net_device *dev);
712 static void rtl8169_rx_clear(struct rtl8169_private *tp);
713 static int rtl8169_poll(struct napi_struct *napi, int budget);
714
715 static const unsigned int rtl8169_rx_config =
716         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
717
718 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
719 {
720         void __iomem *ioaddr = tp->mmio_addr;
721         int i;
722
723         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
724         for (i = 0; i < 20; i++) {
725                 udelay(100);
726                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
727                         break;
728         }
729         return RTL_R32(OCPDR);
730 }
731
732 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
733 {
734         void __iomem *ioaddr = tp->mmio_addr;
735         int i;
736
737         RTL_W32(OCPDR, data);
738         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
739         for (i = 0; i < 20; i++) {
740                 udelay(100);
741                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
742                         break;
743         }
744 }
745
746 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
747 {
748         void __iomem *ioaddr = tp->mmio_addr;
749         int i;
750
751         RTL_W8(ERIDR, cmd);
752         RTL_W32(ERIAR, 0x800010e8);
753         msleep(2);
754         for (i = 0; i < 5; i++) {
755                 udelay(100);
756                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
757                         break;
758         }
759
760         ocp_write(tp, 0x1, 0x30, 0x00000001);
761 }
762
763 #define OOB_CMD_RESET           0x00
764 #define OOB_CMD_DRIVER_START    0x05
765 #define OOB_CMD_DRIVER_STOP     0x06
766
767 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
768 {
769         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
770 }
771
772 static void rtl8168_driver_start(struct rtl8169_private *tp)
773 {
774         u16 reg;
775         int i;
776
777         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
778
779         reg = rtl8168_get_ocp_reg(tp);
780
781         for (i = 0; i < 10; i++) {
782                 msleep(10);
783                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
784                         break;
785         }
786 }
787
788 static void rtl8168_driver_stop(struct rtl8169_private *tp)
789 {
790         u16 reg;
791         int i;
792
793         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
794
795         reg = rtl8168_get_ocp_reg(tp);
796
797         for (i = 0; i < 10; i++) {
798                 msleep(10);
799                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
800                         break;
801         }
802 }
803
804 static int r8168dp_check_dash(struct rtl8169_private *tp)
805 {
806         u16 reg = rtl8168_get_ocp_reg(tp);
807
808         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
809 }
810
811 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
812 {
813         int i;
814
815         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
816
817         for (i = 20; i > 0; i--) {
818                 /*
819                  * Check if the RTL8169 has completed writing to the specified
820                  * MII register.
821                  */
822                 if (!(RTL_R32(PHYAR) & 0x80000000))
823                         break;
824                 udelay(25);
825         }
826         /*
827          * According to hardware specs a 20us delay is required after write
828          * complete indication, but before sending next command.
829          */
830         udelay(20);
831 }
832
833 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
834 {
835         int i, value = -1;
836
837         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
838
839         for (i = 20; i > 0; i--) {
840                 /*
841                  * Check if the RTL8169 has completed retrieving data from
842                  * the specified MII register.
843                  */
844                 if (RTL_R32(PHYAR) & 0x80000000) {
845                         value = RTL_R32(PHYAR) & 0xffff;
846                         break;
847                 }
848                 udelay(25);
849         }
850         /*
851          * According to hardware specs a 20us delay is required after read
852          * complete indication, but before sending next command.
853          */
854         udelay(20);
855
856         return value;
857 }
858
859 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
860 {
861         int i;
862
863         RTL_W32(OCPDR, data |
864                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
865         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
866         RTL_W32(EPHY_RXER_NUM, 0);
867
868         for (i = 0; i < 100; i++) {
869                 mdelay(1);
870                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
871                         break;
872         }
873 }
874
875 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
876 {
877         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
878                 (value & OCPDR_DATA_MASK));
879 }
880
881 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
882 {
883         int i;
884
885         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
886
887         mdelay(1);
888         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
889         RTL_W32(EPHY_RXER_NUM, 0);
890
891         for (i = 0; i < 100; i++) {
892                 mdelay(1);
893                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
894                         break;
895         }
896
897         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
898 }
899
900 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
901
902 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
903 {
904         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
905 }
906
907 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
908 {
909         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
910 }
911
912 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
913 {
914         r8168dp_2_mdio_start(ioaddr);
915
916         r8169_mdio_write(ioaddr, reg_addr, value);
917
918         r8168dp_2_mdio_stop(ioaddr);
919 }
920
921 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
922 {
923         int value;
924
925         r8168dp_2_mdio_start(ioaddr);
926
927         value = r8169_mdio_read(ioaddr, reg_addr);
928
929         r8168dp_2_mdio_stop(ioaddr);
930
931         return value;
932 }
933
934 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
935 {
936         tp->mdio_ops.write(tp->mmio_addr, location, val);
937 }
938
939 static int rtl_readphy(struct rtl8169_private *tp, int location)
940 {
941         return tp->mdio_ops.read(tp->mmio_addr, location);
942 }
943
944 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
945 {
946         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
947 }
948
949 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
950 {
951         int val;
952
953         val = rtl_readphy(tp, reg_addr);
954         rtl_writephy(tp, reg_addr, (val | p) & ~m);
955 }
956
957 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
958                            int val)
959 {
960         struct rtl8169_private *tp = netdev_priv(dev);
961
962         rtl_writephy(tp, location, val);
963 }
964
965 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
966 {
967         struct rtl8169_private *tp = netdev_priv(dev);
968
969         return rtl_readphy(tp, location);
970 }
971
972 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
973 {
974         unsigned int i;
975
976         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
977                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
978
979         for (i = 0; i < 100; i++) {
980                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
981                         break;
982                 udelay(10);
983         }
984 }
985
986 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
987 {
988         u16 value = 0xffff;
989         unsigned int i;
990
991         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
992
993         for (i = 0; i < 100; i++) {
994                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
995                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
996                         break;
997                 }
998                 udelay(10);
999         }
1000
1001         return value;
1002 }
1003
1004 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1005 {
1006         unsigned int i;
1007
1008         RTL_W32(CSIDR, value);
1009         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1010                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1011
1012         for (i = 0; i < 100; i++) {
1013                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1014                         break;
1015                 udelay(10);
1016         }
1017 }
1018
1019 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1020 {
1021         u32 value = ~0x00;
1022         unsigned int i;
1023
1024         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1025                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1026
1027         for (i = 0; i < 100; i++) {
1028                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1029                         value = RTL_R32(CSIDR);
1030                         break;
1031                 }
1032                 udelay(10);
1033         }
1034
1035         return value;
1036 }
1037
1038 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1039 {
1040         u8 value = 0xff;
1041         unsigned int i;
1042
1043         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1044
1045         for (i = 0; i < 300; i++) {
1046                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1047                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1048                         break;
1049                 }
1050                 udelay(100);
1051         }
1052
1053         return value;
1054 }
1055
1056 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1057 {
1058         RTL_W16(IntrMask, 0x0000);
1059
1060         RTL_W16(IntrStatus, 0xffff);
1061 }
1062
1063 static void rtl8169_asic_down(void __iomem *ioaddr)
1064 {
1065         RTL_W8(ChipCmd, 0x00);
1066         rtl8169_irq_mask_and_ack(ioaddr);
1067         RTL_R16(CPlusCmd);
1068 }
1069
1070 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1071 {
1072         void __iomem *ioaddr = tp->mmio_addr;
1073
1074         return RTL_R32(TBICSR) & TBIReset;
1075 }
1076
1077 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1078 {
1079         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1080 }
1081
1082 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1083 {
1084         return RTL_R32(TBICSR) & TBILinkOk;
1085 }
1086
1087 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1088 {
1089         return RTL_R8(PHYstatus) & LinkStatus;
1090 }
1091
1092 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1093 {
1094         void __iomem *ioaddr = tp->mmio_addr;
1095
1096         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1097 }
1098
1099 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1100 {
1101         unsigned int val;
1102
1103         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1104         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1105 }
1106
1107 static void __rtl8169_check_link_status(struct net_device *dev,
1108                                         struct rtl8169_private *tp,
1109                                         void __iomem *ioaddr, bool pm)
1110 {
1111         unsigned long flags;
1112
1113         spin_lock_irqsave(&tp->lock, flags);
1114         if (tp->link_ok(ioaddr)) {
1115                 /* This is to cancel a scheduled suspend if there's one. */
1116                 if (pm)
1117                         pm_request_resume(&tp->pci_dev->dev);
1118                 netif_carrier_on(dev);
1119                 if (net_ratelimit())
1120                         netif_info(tp, ifup, dev, "link up\n");
1121         } else {
1122                 netif_carrier_off(dev);
1123                 netif_info(tp, ifdown, dev, "link down\n");
1124                 if (pm)
1125                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
1126         }
1127         spin_unlock_irqrestore(&tp->lock, flags);
1128 }
1129
1130 static void rtl8169_check_link_status(struct net_device *dev,
1131                                       struct rtl8169_private *tp,
1132                                       void __iomem *ioaddr)
1133 {
1134         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1135 }
1136
1137 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1138
1139 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1140 {
1141         void __iomem *ioaddr = tp->mmio_addr;
1142         u8 options;
1143         u32 wolopts = 0;
1144
1145         options = RTL_R8(Config1);
1146         if (!(options & PMEnable))
1147                 return 0;
1148
1149         options = RTL_R8(Config3);
1150         if (options & LinkUp)
1151                 wolopts |= WAKE_PHY;
1152         if (options & MagicPacket)
1153                 wolopts |= WAKE_MAGIC;
1154
1155         options = RTL_R8(Config5);
1156         if (options & UWF)
1157                 wolopts |= WAKE_UCAST;
1158         if (options & BWF)
1159                 wolopts |= WAKE_BCAST;
1160         if (options & MWF)
1161                 wolopts |= WAKE_MCAST;
1162
1163         return wolopts;
1164 }
1165
1166 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1167 {
1168         struct rtl8169_private *tp = netdev_priv(dev);
1169
1170         spin_lock_irq(&tp->lock);
1171
1172         wol->supported = WAKE_ANY;
1173         wol->wolopts = __rtl8169_get_wol(tp);
1174
1175         spin_unlock_irq(&tp->lock);
1176 }
1177
1178 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1179 {
1180         void __iomem *ioaddr = tp->mmio_addr;
1181         unsigned int i;
1182         static const struct {
1183                 u32 opt;
1184                 u16 reg;
1185                 u8  mask;
1186         } cfg[] = {
1187                 { WAKE_ANY,   Config1, PMEnable },
1188                 { WAKE_PHY,   Config3, LinkUp },
1189                 { WAKE_MAGIC, Config3, MagicPacket },
1190                 { WAKE_UCAST, Config5, UWF },
1191                 { WAKE_BCAST, Config5, BWF },
1192                 { WAKE_MCAST, Config5, MWF },
1193                 { WAKE_ANY,   Config5, LanWake }
1194         };
1195
1196         RTL_W8(Cfg9346, Cfg9346_Unlock);
1197
1198         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1199                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1200                 if (wolopts & cfg[i].opt)
1201                         options |= cfg[i].mask;
1202                 RTL_W8(cfg[i].reg, options);
1203         }
1204
1205         RTL_W8(Cfg9346, Cfg9346_Lock);
1206 }
1207
1208 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1209 {
1210         struct rtl8169_private *tp = netdev_priv(dev);
1211
1212         spin_lock_irq(&tp->lock);
1213
1214         if (wol->wolopts)
1215                 tp->features |= RTL_FEATURE_WOL;
1216         else
1217                 tp->features &= ~RTL_FEATURE_WOL;
1218         __rtl8169_set_wol(tp, wol->wolopts);
1219         spin_unlock_irq(&tp->lock);
1220
1221         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1222
1223         return 0;
1224 }
1225
1226 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1227 {
1228         return rtl_chip_infos[tp->mac_version].fw_name;
1229 }
1230
1231 static void rtl8169_get_drvinfo(struct net_device *dev,
1232                                 struct ethtool_drvinfo *info)
1233 {
1234         struct rtl8169_private *tp = netdev_priv(dev);
1235         struct rtl_fw *rtl_fw = tp->rtl_fw;
1236
1237         strcpy(info->driver, MODULENAME);
1238         strcpy(info->version, RTL8169_VERSION);
1239         strcpy(info->bus_info, pci_name(tp->pci_dev));
1240         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1241         strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1242                rtl_fw->version);
1243 }
1244
1245 static int rtl8169_get_regs_len(struct net_device *dev)
1246 {
1247         return R8169_REGS_SIZE;
1248 }
1249
1250 static int rtl8169_set_speed_tbi(struct net_device *dev,
1251                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1252 {
1253         struct rtl8169_private *tp = netdev_priv(dev);
1254         void __iomem *ioaddr = tp->mmio_addr;
1255         int ret = 0;
1256         u32 reg;
1257
1258         reg = RTL_R32(TBICSR);
1259         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1260             (duplex == DUPLEX_FULL)) {
1261                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1262         } else if (autoneg == AUTONEG_ENABLE)
1263                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1264         else {
1265                 netif_warn(tp, link, dev,
1266                            "incorrect speed setting refused in TBI mode\n");
1267                 ret = -EOPNOTSUPP;
1268         }
1269
1270         return ret;
1271 }
1272
1273 static int rtl8169_set_speed_xmii(struct net_device *dev,
1274                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1275 {
1276         struct rtl8169_private *tp = netdev_priv(dev);
1277         int giga_ctrl, bmcr;
1278         int rc = -EINVAL;
1279
1280         rtl_writephy(tp, 0x1f, 0x0000);
1281
1282         if (autoneg == AUTONEG_ENABLE) {
1283                 int auto_nego;
1284
1285                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1286                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1287                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1288
1289                 if (adv & ADVERTISED_10baseT_Half)
1290                         auto_nego |= ADVERTISE_10HALF;
1291                 if (adv & ADVERTISED_10baseT_Full)
1292                         auto_nego |= ADVERTISE_10FULL;
1293                 if (adv & ADVERTISED_100baseT_Half)
1294                         auto_nego |= ADVERTISE_100HALF;
1295                 if (adv & ADVERTISED_100baseT_Full)
1296                         auto_nego |= ADVERTISE_100FULL;
1297
1298                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1299
1300                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1301                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1302
1303                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1304                 if (tp->mii.supports_gmii) {
1305                         if (adv & ADVERTISED_1000baseT_Half)
1306                                 giga_ctrl |= ADVERTISE_1000HALF;
1307                         if (adv & ADVERTISED_1000baseT_Full)
1308                                 giga_ctrl |= ADVERTISE_1000FULL;
1309                 } else if (adv & (ADVERTISED_1000baseT_Half |
1310                                   ADVERTISED_1000baseT_Full)) {
1311                         netif_info(tp, link, dev,
1312                                    "PHY does not support 1000Mbps\n");
1313                         goto out;
1314                 }
1315
1316                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1317
1318                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1319                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1320         } else {
1321                 giga_ctrl = 0;
1322
1323                 if (speed == SPEED_10)
1324                         bmcr = 0;
1325                 else if (speed == SPEED_100)
1326                         bmcr = BMCR_SPEED100;
1327                 else
1328                         goto out;
1329
1330                 if (duplex == DUPLEX_FULL)
1331                         bmcr |= BMCR_FULLDPLX;
1332         }
1333
1334         rtl_writephy(tp, MII_BMCR, bmcr);
1335
1336         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1337             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1338                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1339                         rtl_writephy(tp, 0x17, 0x2138);
1340                         rtl_writephy(tp, 0x0e, 0x0260);
1341                 } else {
1342                         rtl_writephy(tp, 0x17, 0x2108);
1343                         rtl_writephy(tp, 0x0e, 0x0000);
1344                 }
1345         }
1346
1347         rc = 0;
1348 out:
1349         return rc;
1350 }
1351
1352 static int rtl8169_set_speed(struct net_device *dev,
1353                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1354 {
1355         struct rtl8169_private *tp = netdev_priv(dev);
1356         int ret;
1357
1358         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1359         if (ret < 0)
1360                 goto out;
1361
1362         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1363             (advertising & ADVERTISED_1000baseT_Full)) {
1364                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1365         }
1366 out:
1367         return ret;
1368 }
1369
1370 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1371 {
1372         struct rtl8169_private *tp = netdev_priv(dev);
1373         unsigned long flags;
1374         int ret;
1375
1376         del_timer_sync(&tp->timer);
1377
1378         spin_lock_irqsave(&tp->lock, flags);
1379         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1380                                 cmd->duplex, cmd->advertising);
1381         spin_unlock_irqrestore(&tp->lock, flags);
1382
1383         return ret;
1384 }
1385
1386 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1387 {
1388         if (dev->mtu > TD_MSS_MAX)
1389                 features &= ~NETIF_F_ALL_TSO;
1390
1391         return features;
1392 }
1393
1394 static int rtl8169_set_features(struct net_device *dev, u32 features)
1395 {
1396         struct rtl8169_private *tp = netdev_priv(dev);
1397         void __iomem *ioaddr = tp->mmio_addr;
1398         unsigned long flags;
1399
1400         spin_lock_irqsave(&tp->lock, flags);
1401
1402         if (features & NETIF_F_RXCSUM)
1403                 tp->cp_cmd |= RxChkSum;
1404         else
1405                 tp->cp_cmd &= ~RxChkSum;
1406
1407         if (dev->features & NETIF_F_HW_VLAN_RX)
1408                 tp->cp_cmd |= RxVlan;
1409         else
1410                 tp->cp_cmd &= ~RxVlan;
1411
1412         RTL_W16(CPlusCmd, tp->cp_cmd);
1413         RTL_R16(CPlusCmd);
1414
1415         spin_unlock_irqrestore(&tp->lock, flags);
1416
1417         return 0;
1418 }
1419
1420 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1421                                       struct sk_buff *skb)
1422 {
1423         return (vlan_tx_tag_present(skb)) ?
1424                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1425 }
1426
1427 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1428 {
1429         u32 opts2 = le32_to_cpu(desc->opts2);
1430
1431         if (opts2 & RxVlanTag)
1432                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1433
1434         desc->opts2 = 0;
1435 }
1436
1437 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1438 {
1439         struct rtl8169_private *tp = netdev_priv(dev);
1440         void __iomem *ioaddr = tp->mmio_addr;
1441         u32 status;
1442
1443         cmd->supported =
1444                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1445         cmd->port = PORT_FIBRE;
1446         cmd->transceiver = XCVR_INTERNAL;
1447
1448         status = RTL_R32(TBICSR);
1449         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1450         cmd->autoneg = !!(status & TBINwEnable);
1451
1452         ethtool_cmd_speed_set(cmd, SPEED_1000);
1453         cmd->duplex = DUPLEX_FULL; /* Always set */
1454
1455         return 0;
1456 }
1457
1458 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1459 {
1460         struct rtl8169_private *tp = netdev_priv(dev);
1461
1462         return mii_ethtool_gset(&tp->mii, cmd);
1463 }
1464
1465 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1466 {
1467         struct rtl8169_private *tp = netdev_priv(dev);
1468         unsigned long flags;
1469         int rc;
1470
1471         spin_lock_irqsave(&tp->lock, flags);
1472
1473         rc = tp->get_settings(dev, cmd);
1474
1475         spin_unlock_irqrestore(&tp->lock, flags);
1476         return rc;
1477 }
1478
1479 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1480                              void *p)
1481 {
1482         struct rtl8169_private *tp = netdev_priv(dev);
1483         unsigned long flags;
1484
1485         if (regs->len > R8169_REGS_SIZE)
1486                 regs->len = R8169_REGS_SIZE;
1487
1488         spin_lock_irqsave(&tp->lock, flags);
1489         memcpy_fromio(p, tp->mmio_addr, regs->len);
1490         spin_unlock_irqrestore(&tp->lock, flags);
1491 }
1492
1493 static u32 rtl8169_get_msglevel(struct net_device *dev)
1494 {
1495         struct rtl8169_private *tp = netdev_priv(dev);
1496
1497         return tp->msg_enable;
1498 }
1499
1500 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1501 {
1502         struct rtl8169_private *tp = netdev_priv(dev);
1503
1504         tp->msg_enable = value;
1505 }
1506
1507 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1508         "tx_packets",
1509         "rx_packets",
1510         "tx_errors",
1511         "rx_errors",
1512         "rx_missed",
1513         "align_errors",
1514         "tx_single_collisions",
1515         "tx_multi_collisions",
1516         "unicast",
1517         "broadcast",
1518         "multicast",
1519         "tx_aborted",
1520         "tx_underrun",
1521 };
1522
1523 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1524 {
1525         switch (sset) {
1526         case ETH_SS_STATS:
1527                 return ARRAY_SIZE(rtl8169_gstrings);
1528         default:
1529                 return -EOPNOTSUPP;
1530         }
1531 }
1532
1533 static void rtl8169_update_counters(struct net_device *dev)
1534 {
1535         struct rtl8169_private *tp = netdev_priv(dev);
1536         void __iomem *ioaddr = tp->mmio_addr;
1537         struct device *d = &tp->pci_dev->dev;
1538         struct rtl8169_counters *counters;
1539         dma_addr_t paddr;
1540         u32 cmd;
1541         int wait = 1000;
1542
1543         /*
1544          * Some chips are unable to dump tally counters when the receiver
1545          * is disabled.
1546          */
1547         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1548                 return;
1549
1550         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1551         if (!counters)
1552                 return;
1553
1554         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1555         cmd = (u64)paddr & DMA_BIT_MASK(32);
1556         RTL_W32(CounterAddrLow, cmd);
1557         RTL_W32(CounterAddrLow, cmd | CounterDump);
1558
1559         while (wait--) {
1560                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1561                         memcpy(&tp->counters, counters, sizeof(*counters));
1562                         break;
1563                 }
1564                 udelay(10);
1565         }
1566
1567         RTL_W32(CounterAddrLow, 0);
1568         RTL_W32(CounterAddrHigh, 0);
1569
1570         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1571 }
1572
1573 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1574                                       struct ethtool_stats *stats, u64 *data)
1575 {
1576         struct rtl8169_private *tp = netdev_priv(dev);
1577
1578         ASSERT_RTNL();
1579
1580         rtl8169_update_counters(dev);
1581
1582         data[0] = le64_to_cpu(tp->counters.tx_packets);
1583         data[1] = le64_to_cpu(tp->counters.rx_packets);
1584         data[2] = le64_to_cpu(tp->counters.tx_errors);
1585         data[3] = le32_to_cpu(tp->counters.rx_errors);
1586         data[4] = le16_to_cpu(tp->counters.rx_missed);
1587         data[5] = le16_to_cpu(tp->counters.align_errors);
1588         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1589         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1590         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1591         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1592         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1593         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1594         data[12] = le16_to_cpu(tp->counters.tx_underun);
1595 }
1596
1597 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1598 {
1599         switch(stringset) {
1600         case ETH_SS_STATS:
1601                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1602                 break;
1603         }
1604 }
1605
1606 static const struct ethtool_ops rtl8169_ethtool_ops = {
1607         .get_drvinfo            = rtl8169_get_drvinfo,
1608         .get_regs_len           = rtl8169_get_regs_len,
1609         .get_link               = ethtool_op_get_link,
1610         .get_settings           = rtl8169_get_settings,
1611         .set_settings           = rtl8169_set_settings,
1612         .get_msglevel           = rtl8169_get_msglevel,
1613         .set_msglevel           = rtl8169_set_msglevel,
1614         .get_regs               = rtl8169_get_regs,
1615         .get_wol                = rtl8169_get_wol,
1616         .set_wol                = rtl8169_set_wol,
1617         .get_strings            = rtl8169_get_strings,
1618         .get_sset_count         = rtl8169_get_sset_count,
1619         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1620 };
1621
1622 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1623                                     struct net_device *dev, u8 default_version)
1624 {
1625         void __iomem *ioaddr = tp->mmio_addr;
1626         /*
1627          * The driver currently handles the 8168Bf and the 8168Be identically
1628          * but they can be identified more specifically through the test below
1629          * if needed:
1630          *
1631          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1632          *
1633          * Same thing for the 8101Eb and the 8101Ec:
1634          *
1635          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1636          */
1637         static const struct rtl_mac_info {
1638                 u32 mask;
1639                 u32 val;
1640                 int mac_version;
1641         } mac_info[] = {
1642                 /* 8168E family. */
1643                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1644                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1645                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1646
1647                 /* 8168D family. */
1648                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1649                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1650                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1651
1652                 /* 8168DP family. */
1653                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1654                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1655                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1656
1657                 /* 8168C family. */
1658                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1659                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1660                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1661                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1662                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1663                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1664                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1665                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1666                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1667
1668                 /* 8168B family. */
1669                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1670                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1671                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1672                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1673
1674                 /* 8101 family. */
1675                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1676                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1677                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1678                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1679                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1680                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1681                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1682                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1683                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1684                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1685                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1686                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1687                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1688                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1689                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1690                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1691                 /* FIXME: where did these entries come from ? -- FR */
1692                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1693                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1694
1695                 /* 8110 family. */
1696                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1697                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1698                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1699                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1700                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1701                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1702
1703                 /* Catch-all */
1704                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1705         };
1706         const struct rtl_mac_info *p = mac_info;
1707         u32 reg;
1708
1709         reg = RTL_R32(TxConfig);
1710         while ((reg & p->mask) != p->val)
1711                 p++;
1712         tp->mac_version = p->mac_version;
1713
1714         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1715                 netif_notice(tp, probe, dev,
1716                              "unknown MAC, using family default\n");
1717                 tp->mac_version = default_version;
1718         }
1719 }
1720
1721 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1722 {
1723         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1724 }
1725
1726 struct phy_reg {
1727         u16 reg;
1728         u16 val;
1729 };
1730
1731 static void rtl_writephy_batch(struct rtl8169_private *tp,
1732                                const struct phy_reg *regs, int len)
1733 {
1734         while (len-- > 0) {
1735                 rtl_writephy(tp, regs->reg, regs->val);
1736                 regs++;
1737         }
1738 }
1739
1740 #define PHY_READ                0x00000000
1741 #define PHY_DATA_OR             0x10000000
1742 #define PHY_DATA_AND            0x20000000
1743 #define PHY_BJMPN               0x30000000
1744 #define PHY_READ_EFUSE          0x40000000
1745 #define PHY_READ_MAC_BYTE       0x50000000
1746 #define PHY_WRITE_MAC_BYTE      0x60000000
1747 #define PHY_CLEAR_READCOUNT     0x70000000
1748 #define PHY_WRITE               0x80000000
1749 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1750 #define PHY_COMP_EQ_SKIPN       0xa0000000
1751 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1752 #define PHY_WRITE_PREVIOUS      0xc0000000
1753 #define PHY_SKIPN               0xd0000000
1754 #define PHY_DELAY_MS            0xe0000000
1755 #define PHY_WRITE_ERI_WORD      0xf0000000
1756
1757 struct fw_info {
1758         u32     magic;
1759         char    version[RTL_VER_SIZE];
1760         __le32  fw_start;
1761         __le32  fw_len;
1762         u8      chksum;
1763 } __packed;
1764
1765 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1766
1767 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1768 {
1769         const struct firmware *fw = rtl_fw->fw;
1770         struct fw_info *fw_info = (struct fw_info *)fw->data;
1771         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1772         char *version = rtl_fw->version;
1773         bool rc = false;
1774
1775         if (fw->size < FW_OPCODE_SIZE)
1776                 goto out;
1777
1778         if (!fw_info->magic) {
1779                 size_t i, size, start;
1780                 u8 checksum = 0;
1781
1782                 if (fw->size < sizeof(*fw_info))
1783                         goto out;
1784
1785                 for (i = 0; i < fw->size; i++)
1786                         checksum += fw->data[i];
1787                 if (checksum != 0)
1788                         goto out;
1789
1790                 start = le32_to_cpu(fw_info->fw_start);
1791                 if (start > fw->size)
1792                         goto out;
1793
1794                 size = le32_to_cpu(fw_info->fw_len);
1795                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1796                         goto out;
1797
1798                 memcpy(version, fw_info->version, RTL_VER_SIZE);
1799
1800                 pa->code = (__le32 *)(fw->data + start);
1801                 pa->size = size;
1802         } else {
1803                 if (fw->size % FW_OPCODE_SIZE)
1804                         goto out;
1805
1806                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1807
1808                 pa->code = (__le32 *)fw->data;
1809                 pa->size = fw->size / FW_OPCODE_SIZE;
1810         }
1811         version[RTL_VER_SIZE - 1] = 0;
1812
1813         rc = true;
1814 out:
1815         return rc;
1816 }
1817
1818 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
1819                            struct rtl_fw_phy_action *pa)
1820 {
1821         bool rc = false;
1822         size_t index;
1823
1824         for (index = 0; index < pa->size; index++) {
1825                 u32 action = le32_to_cpu(pa->code[index]);
1826                 u32 regno = (action & 0x0fff0000) >> 16;
1827
1828                 switch(action & 0xf0000000) {
1829                 case PHY_READ:
1830                 case PHY_DATA_OR:
1831                 case PHY_DATA_AND:
1832                 case PHY_READ_EFUSE:
1833                 case PHY_CLEAR_READCOUNT:
1834                 case PHY_WRITE:
1835                 case PHY_WRITE_PREVIOUS:
1836                 case PHY_DELAY_MS:
1837                         break;
1838
1839                 case PHY_BJMPN:
1840                         if (regno > index) {
1841                                 netif_err(tp, ifup, tp->dev,
1842                                           "Out of range of firmware\n");
1843                                 goto out;
1844                         }
1845                         break;
1846                 case PHY_READCOUNT_EQ_SKIP:
1847                         if (index + 2 >= pa->size) {
1848                                 netif_err(tp, ifup, tp->dev,
1849                                           "Out of range of firmware\n");
1850                                 goto out;
1851                         }
1852                         break;
1853                 case PHY_COMP_EQ_SKIPN:
1854                 case PHY_COMP_NEQ_SKIPN:
1855                 case PHY_SKIPN:
1856                         if (index + 1 + regno >= pa->size) {
1857                                 netif_err(tp, ifup, tp->dev,
1858                                           "Out of range of firmware\n");
1859                                 goto out;
1860                         }
1861                         break;
1862
1863                 case PHY_READ_MAC_BYTE:
1864                 case PHY_WRITE_MAC_BYTE:
1865                 case PHY_WRITE_ERI_WORD:
1866                 default:
1867                         netif_err(tp, ifup, tp->dev,
1868                                   "Invalid action 0x%08x\n", action);
1869                         goto out;
1870                 }
1871         }
1872         rc = true;
1873 out:
1874         return rc;
1875 }
1876
1877 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1878 {
1879         struct net_device *dev = tp->dev;
1880         int rc = -EINVAL;
1881
1882         if (!rtl_fw_format_ok(tp, rtl_fw)) {
1883                 netif_err(tp, ifup, dev, "invalid firwmare\n");
1884                 goto out;
1885         }
1886
1887         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
1888                 rc = 0;
1889 out:
1890         return rc;
1891 }
1892
1893 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1894 {
1895         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1896         u32 predata, count;
1897         size_t index;
1898
1899         predata = count = 0;
1900
1901         for (index = 0; index < pa->size; ) {
1902                 u32 action = le32_to_cpu(pa->code[index]);
1903                 u32 data = action & 0x0000ffff;
1904                 u32 regno = (action & 0x0fff0000) >> 16;
1905
1906                 if (!action)
1907                         break;
1908
1909                 switch(action & 0xf0000000) {
1910                 case PHY_READ:
1911                         predata = rtl_readphy(tp, regno);
1912                         count++;
1913                         index++;
1914                         break;
1915                 case PHY_DATA_OR:
1916                         predata |= data;
1917                         index++;
1918                         break;
1919                 case PHY_DATA_AND:
1920                         predata &= data;
1921                         index++;
1922                         break;
1923                 case PHY_BJMPN:
1924                         index -= regno;
1925                         break;
1926                 case PHY_READ_EFUSE:
1927                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1928                         index++;
1929                         break;
1930                 case PHY_CLEAR_READCOUNT:
1931                         count = 0;
1932                         index++;
1933                         break;
1934                 case PHY_WRITE:
1935                         rtl_writephy(tp, regno, data);
1936                         index++;
1937                         break;
1938                 case PHY_READCOUNT_EQ_SKIP:
1939                         index += (count == data) ? 2 : 1;
1940                         break;
1941                 case PHY_COMP_EQ_SKIPN:
1942                         if (predata == data)
1943                                 index += regno;
1944                         index++;
1945                         break;
1946                 case PHY_COMP_NEQ_SKIPN:
1947                         if (predata != data)
1948                                 index += regno;
1949                         index++;
1950                         break;
1951                 case PHY_WRITE_PREVIOUS:
1952                         rtl_writephy(tp, regno, predata);
1953                         index++;
1954                         break;
1955                 case PHY_SKIPN:
1956                         index += regno + 1;
1957                         break;
1958                 case PHY_DELAY_MS:
1959                         mdelay(data);
1960                         index++;
1961                         break;
1962
1963                 case PHY_READ_MAC_BYTE:
1964                 case PHY_WRITE_MAC_BYTE:
1965                 case PHY_WRITE_ERI_WORD:
1966                 default:
1967                         BUG();
1968                 }
1969         }
1970 }
1971
1972 static void rtl_release_firmware(struct rtl8169_private *tp)
1973 {
1974         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
1975                 release_firmware(tp->rtl_fw->fw);
1976                 kfree(tp->rtl_fw);
1977         }
1978         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
1979 }
1980
1981 static void rtl_apply_firmware(struct rtl8169_private *tp)
1982 {
1983         struct rtl_fw *rtl_fw = tp->rtl_fw;
1984
1985         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1986         if (!IS_ERR_OR_NULL(rtl_fw))
1987                 rtl_phy_write_fw(tp, rtl_fw);
1988 }
1989
1990 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1991 {
1992         if (rtl_readphy(tp, reg) != val)
1993                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1994         else
1995                 rtl_apply_firmware(tp);
1996 }
1997
1998 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1999 {
2000         static const struct phy_reg phy_reg_init[] = {
2001                 { 0x1f, 0x0001 },
2002                 { 0x06, 0x006e },
2003                 { 0x08, 0x0708 },
2004                 { 0x15, 0x4000 },
2005                 { 0x18, 0x65c7 },
2006
2007                 { 0x1f, 0x0001 },
2008                 { 0x03, 0x00a1 },
2009                 { 0x02, 0x0008 },
2010                 { 0x01, 0x0120 },
2011                 { 0x00, 0x1000 },
2012                 { 0x04, 0x0800 },
2013                 { 0x04, 0x0000 },
2014
2015                 { 0x03, 0xff41 },
2016                 { 0x02, 0xdf60 },
2017                 { 0x01, 0x0140 },
2018                 { 0x00, 0x0077 },
2019                 { 0x04, 0x7800 },
2020                 { 0x04, 0x7000 },
2021
2022                 { 0x03, 0x802f },
2023                 { 0x02, 0x4f02 },
2024                 { 0x01, 0x0409 },
2025                 { 0x00, 0xf0f9 },
2026                 { 0x04, 0x9800 },
2027                 { 0x04, 0x9000 },
2028
2029                 { 0x03, 0xdf01 },
2030                 { 0x02, 0xdf20 },
2031                 { 0x01, 0xff95 },
2032                 { 0x00, 0xba00 },
2033                 { 0x04, 0xa800 },
2034                 { 0x04, 0xa000 },
2035
2036                 { 0x03, 0xff41 },
2037                 { 0x02, 0xdf20 },
2038                 { 0x01, 0x0140 },
2039                 { 0x00, 0x00bb },
2040                 { 0x04, 0xb800 },
2041                 { 0x04, 0xb000 },
2042
2043                 { 0x03, 0xdf41 },
2044                 { 0x02, 0xdc60 },
2045                 { 0x01, 0x6340 },
2046                 { 0x00, 0x007d },
2047                 { 0x04, 0xd800 },
2048                 { 0x04, 0xd000 },
2049
2050                 { 0x03, 0xdf01 },
2051                 { 0x02, 0xdf20 },
2052                 { 0x01, 0x100a },
2053                 { 0x00, 0xa0ff },
2054                 { 0x04, 0xf800 },
2055                 { 0x04, 0xf000 },
2056
2057                 { 0x1f, 0x0000 },
2058                 { 0x0b, 0x0000 },
2059                 { 0x00, 0x9200 }
2060         };
2061
2062         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2063 }
2064
2065 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2066 {
2067         static const struct phy_reg phy_reg_init[] = {
2068                 { 0x1f, 0x0002 },
2069                 { 0x01, 0x90d0 },
2070                 { 0x1f, 0x0000 }
2071         };
2072
2073         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2074 }
2075
2076 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2077 {
2078         struct pci_dev *pdev = tp->pci_dev;
2079         u16 vendor_id, device_id;
2080
2081         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
2082         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
2083
2084         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
2085                 return;
2086
2087         rtl_writephy(tp, 0x1f, 0x0001);
2088         rtl_writephy(tp, 0x10, 0xf01b);
2089         rtl_writephy(tp, 0x1f, 0x0000);
2090 }
2091
2092 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2093 {
2094         static const struct phy_reg phy_reg_init[] = {
2095                 { 0x1f, 0x0001 },
2096                 { 0x04, 0x0000 },
2097                 { 0x03, 0x00a1 },
2098                 { 0x02, 0x0008 },
2099                 { 0x01, 0x0120 },
2100                 { 0x00, 0x1000 },
2101                 { 0x04, 0x0800 },
2102                 { 0x04, 0x9000 },
2103                 { 0x03, 0x802f },
2104                 { 0x02, 0x4f02 },
2105                 { 0x01, 0x0409 },
2106                 { 0x00, 0xf099 },
2107                 { 0x04, 0x9800 },
2108                 { 0x04, 0xa000 },
2109                 { 0x03, 0xdf01 },
2110                 { 0x02, 0xdf20 },
2111                 { 0x01, 0xff95 },
2112                 { 0x00, 0xba00 },
2113                 { 0x04, 0xa800 },
2114                 { 0x04, 0xf000 },
2115                 { 0x03, 0xdf01 },
2116                 { 0x02, 0xdf20 },
2117                 { 0x01, 0x101a },
2118                 { 0x00, 0xa0ff },
2119                 { 0x04, 0xf800 },
2120                 { 0x04, 0x0000 },
2121                 { 0x1f, 0x0000 },
2122
2123                 { 0x1f, 0x0001 },
2124                 { 0x10, 0xf41b },
2125                 { 0x14, 0xfb54 },
2126                 { 0x18, 0xf5c7 },
2127                 { 0x1f, 0x0000 },
2128
2129                 { 0x1f, 0x0001 },
2130                 { 0x17, 0x0cc0 },
2131                 { 0x1f, 0x0000 }
2132         };
2133
2134         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2135
2136         rtl8169scd_hw_phy_config_quirk(tp);
2137 }
2138
2139 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2140 {
2141         static const struct phy_reg phy_reg_init[] = {
2142                 { 0x1f, 0x0001 },
2143                 { 0x04, 0x0000 },
2144                 { 0x03, 0x00a1 },
2145                 { 0x02, 0x0008 },
2146                 { 0x01, 0x0120 },
2147                 { 0x00, 0x1000 },
2148                 { 0x04, 0x0800 },
2149                 { 0x04, 0x9000 },
2150                 { 0x03, 0x802f },
2151                 { 0x02, 0x4f02 },
2152                 { 0x01, 0x0409 },
2153                 { 0x00, 0xf099 },
2154                 { 0x04, 0x9800 },
2155                 { 0x04, 0xa000 },
2156                 { 0x03, 0xdf01 },
2157                 { 0x02, 0xdf20 },
2158                 { 0x01, 0xff95 },
2159                 { 0x00, 0xba00 },
2160                 { 0x04, 0xa800 },
2161                 { 0x04, 0xf000 },
2162                 { 0x03, 0xdf01 },
2163                 { 0x02, 0xdf20 },
2164                 { 0x01, 0x101a },
2165                 { 0x00, 0xa0ff },
2166                 { 0x04, 0xf800 },
2167                 { 0x04, 0x0000 },
2168                 { 0x1f, 0x0000 },
2169
2170                 { 0x1f, 0x0001 },
2171                 { 0x0b, 0x8480 },
2172                 { 0x1f, 0x0000 },
2173
2174                 { 0x1f, 0x0001 },
2175                 { 0x18, 0x67c7 },
2176                 { 0x04, 0x2000 },
2177                 { 0x03, 0x002f },
2178                 { 0x02, 0x4360 },
2179                 { 0x01, 0x0109 },
2180                 { 0x00, 0x3022 },
2181                 { 0x04, 0x2800 },
2182                 { 0x1f, 0x0000 },
2183
2184                 { 0x1f, 0x0001 },
2185                 { 0x17, 0x0cc0 },
2186                 { 0x1f, 0x0000 }
2187         };
2188
2189         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2190 }
2191
2192 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2193 {
2194         static const struct phy_reg phy_reg_init[] = {
2195                 { 0x10, 0xf41b },
2196                 { 0x1f, 0x0000 }
2197         };
2198
2199         rtl_writephy(tp, 0x1f, 0x0001);
2200         rtl_patchphy(tp, 0x16, 1 << 0);
2201
2202         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2203 }
2204
2205 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2206 {
2207         static const struct phy_reg phy_reg_init[] = {
2208                 { 0x1f, 0x0001 },
2209                 { 0x10, 0xf41b },
2210                 { 0x1f, 0x0000 }
2211         };
2212
2213         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2214 }
2215
2216 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2217 {
2218         static const struct phy_reg phy_reg_init[] = {
2219                 { 0x1f, 0x0000 },
2220                 { 0x1d, 0x0f00 },
2221                 { 0x1f, 0x0002 },
2222                 { 0x0c, 0x1ec8 },
2223                 { 0x1f, 0x0000 }
2224         };
2225
2226         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2227 }
2228
2229 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2230 {
2231         static const struct phy_reg phy_reg_init[] = {
2232                 { 0x1f, 0x0001 },
2233                 { 0x1d, 0x3d98 },
2234                 { 0x1f, 0x0000 }
2235         };
2236
2237         rtl_writephy(tp, 0x1f, 0x0000);
2238         rtl_patchphy(tp, 0x14, 1 << 5);
2239         rtl_patchphy(tp, 0x0d, 1 << 5);
2240
2241         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2242 }
2243
2244 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2245 {
2246         static const struct phy_reg phy_reg_init[] = {
2247                 { 0x1f, 0x0001 },
2248                 { 0x12, 0x2300 },
2249                 { 0x1f, 0x0002 },
2250                 { 0x00, 0x88d4 },
2251                 { 0x01, 0x82b1 },
2252                 { 0x03, 0x7002 },
2253                 { 0x08, 0x9e30 },
2254                 { 0x09, 0x01f0 },
2255                 { 0x0a, 0x5500 },
2256                 { 0x0c, 0x00c8 },
2257                 { 0x1f, 0x0003 },
2258                 { 0x12, 0xc096 },
2259                 { 0x16, 0x000a },
2260                 { 0x1f, 0x0000 },
2261                 { 0x1f, 0x0000 },
2262                 { 0x09, 0x2000 },
2263                 { 0x09, 0x0000 }
2264         };
2265
2266         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2267
2268         rtl_patchphy(tp, 0x14, 1 << 5);
2269         rtl_patchphy(tp, 0x0d, 1 << 5);
2270         rtl_writephy(tp, 0x1f, 0x0000);
2271 }
2272
2273 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2274 {
2275         static const struct phy_reg phy_reg_init[] = {
2276                 { 0x1f, 0x0001 },
2277                 { 0x12, 0x2300 },
2278                 { 0x03, 0x802f },
2279                 { 0x02, 0x4f02 },
2280                 { 0x01, 0x0409 },
2281                 { 0x00, 0xf099 },
2282                 { 0x04, 0x9800 },
2283                 { 0x04, 0x9000 },
2284                 { 0x1d, 0x3d98 },
2285                 { 0x1f, 0x0002 },
2286                 { 0x0c, 0x7eb8 },
2287                 { 0x06, 0x0761 },
2288                 { 0x1f, 0x0003 },
2289                 { 0x16, 0x0f0a },
2290                 { 0x1f, 0x0000 }
2291         };
2292
2293         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2294
2295         rtl_patchphy(tp, 0x16, 1 << 0);
2296         rtl_patchphy(tp, 0x14, 1 << 5);
2297         rtl_patchphy(tp, 0x0d, 1 << 5);
2298         rtl_writephy(tp, 0x1f, 0x0000);
2299 }
2300
2301 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2302 {
2303         static const struct phy_reg phy_reg_init[] = {
2304                 { 0x1f, 0x0001 },
2305                 { 0x12, 0x2300 },
2306                 { 0x1d, 0x3d98 },
2307                 { 0x1f, 0x0002 },
2308                 { 0x0c, 0x7eb8 },
2309                 { 0x06, 0x5461 },
2310                 { 0x1f, 0x0003 },
2311                 { 0x16, 0x0f0a },
2312                 { 0x1f, 0x0000 }
2313         };
2314
2315         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2316
2317         rtl_patchphy(tp, 0x16, 1 << 0);
2318         rtl_patchphy(tp, 0x14, 1 << 5);
2319         rtl_patchphy(tp, 0x0d, 1 << 5);
2320         rtl_writephy(tp, 0x1f, 0x0000);
2321 }
2322
2323 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2324 {
2325         rtl8168c_3_hw_phy_config(tp);
2326 }
2327
2328 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2329 {
2330         static const struct phy_reg phy_reg_init_0[] = {
2331                 /* Channel Estimation */
2332                 { 0x1f, 0x0001 },
2333                 { 0x06, 0x4064 },
2334                 { 0x07, 0x2863 },
2335                 { 0x08, 0x059c },
2336                 { 0x09, 0x26b4 },
2337                 { 0x0a, 0x6a19 },
2338                 { 0x0b, 0xdcc8 },
2339                 { 0x10, 0xf06d },
2340                 { 0x14, 0x7f68 },
2341                 { 0x18, 0x7fd9 },
2342                 { 0x1c, 0xf0ff },
2343                 { 0x1d, 0x3d9c },
2344                 { 0x1f, 0x0003 },
2345                 { 0x12, 0xf49f },
2346                 { 0x13, 0x070b },
2347                 { 0x1a, 0x05ad },
2348                 { 0x14, 0x94c0 },
2349
2350                 /*
2351                  * Tx Error Issue
2352                  * Enhance line driver power
2353                  */
2354                 { 0x1f, 0x0002 },
2355                 { 0x06, 0x5561 },
2356                 { 0x1f, 0x0005 },
2357                 { 0x05, 0x8332 },
2358                 { 0x06, 0x5561 },
2359
2360                 /*
2361                  * Can not link to 1Gbps with bad cable
2362                  * Decrease SNR threshold form 21.07dB to 19.04dB
2363                  */
2364                 { 0x1f, 0x0001 },
2365                 { 0x17, 0x0cc0 },
2366
2367                 { 0x1f, 0x0000 },
2368                 { 0x0d, 0xf880 }
2369         };
2370         void __iomem *ioaddr = tp->mmio_addr;
2371
2372         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2373
2374         /*
2375          * Rx Error Issue
2376          * Fine Tune Switching regulator parameter
2377          */
2378         rtl_writephy(tp, 0x1f, 0x0002);
2379         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2380         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2381
2382         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2383                 static const struct phy_reg phy_reg_init[] = {
2384                         { 0x1f, 0x0002 },
2385                         { 0x05, 0x669a },
2386                         { 0x1f, 0x0005 },
2387                         { 0x05, 0x8330 },
2388                         { 0x06, 0x669a },
2389                         { 0x1f, 0x0002 }
2390                 };
2391                 int val;
2392
2393                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2394
2395                 val = rtl_readphy(tp, 0x0d);
2396
2397                 if ((val & 0x00ff) != 0x006c) {
2398                         static const u32 set[] = {
2399                                 0x0065, 0x0066, 0x0067, 0x0068,
2400                                 0x0069, 0x006a, 0x006b, 0x006c
2401                         };
2402                         int i;
2403
2404                         rtl_writephy(tp, 0x1f, 0x0002);
2405
2406                         val &= 0xff00;
2407                         for (i = 0; i < ARRAY_SIZE(set); i++)
2408                                 rtl_writephy(tp, 0x0d, val | set[i]);
2409                 }
2410         } else {
2411                 static const struct phy_reg phy_reg_init[] = {
2412                         { 0x1f, 0x0002 },
2413                         { 0x05, 0x6662 },
2414                         { 0x1f, 0x0005 },
2415                         { 0x05, 0x8330 },
2416                         { 0x06, 0x6662 }
2417                 };
2418
2419                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2420         }
2421
2422         /* RSET couple improve */
2423         rtl_writephy(tp, 0x1f, 0x0002);
2424         rtl_patchphy(tp, 0x0d, 0x0300);
2425         rtl_patchphy(tp, 0x0f, 0x0010);
2426
2427         /* Fine tune PLL performance */
2428         rtl_writephy(tp, 0x1f, 0x0002);
2429         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2430         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2431
2432         rtl_writephy(tp, 0x1f, 0x0005);
2433         rtl_writephy(tp, 0x05, 0x001b);
2434
2435         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2436
2437         rtl_writephy(tp, 0x1f, 0x0000);
2438 }
2439
2440 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2441 {
2442         static const struct phy_reg phy_reg_init_0[] = {
2443                 /* Channel Estimation */
2444                 { 0x1f, 0x0001 },
2445                 { 0x06, 0x4064 },
2446                 { 0x07, 0x2863 },
2447                 { 0x08, 0x059c },
2448                 { 0x09, 0x26b4 },
2449                 { 0x0a, 0x6a19 },
2450                 { 0x0b, 0xdcc8 },
2451                 { 0x10, 0xf06d },
2452                 { 0x14, 0x7f68 },
2453                 { 0x18, 0x7fd9 },
2454                 { 0x1c, 0xf0ff },
2455                 { 0x1d, 0x3d9c },
2456                 { 0x1f, 0x0003 },
2457                 { 0x12, 0xf49f },
2458                 { 0x13, 0x070b },
2459                 { 0x1a, 0x05ad },
2460                 { 0x14, 0x94c0 },
2461
2462                 /*
2463                  * Tx Error Issue
2464                  * Enhance line driver power
2465                  */
2466                 { 0x1f, 0x0002 },
2467                 { 0x06, 0x5561 },
2468                 { 0x1f, 0x0005 },
2469                 { 0x05, 0x8332 },
2470                 { 0x06, 0x5561 },
2471
2472                 /*
2473                  * Can not link to 1Gbps with bad cable
2474                  * Decrease SNR threshold form 21.07dB to 19.04dB
2475                  */
2476                 { 0x1f, 0x0001 },
2477                 { 0x17, 0x0cc0 },
2478
2479                 { 0x1f, 0x0000 },
2480                 { 0x0d, 0xf880 }
2481         };
2482         void __iomem *ioaddr = tp->mmio_addr;
2483
2484         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2485
2486         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2487                 static const struct phy_reg phy_reg_init[] = {
2488                         { 0x1f, 0x0002 },
2489                         { 0x05, 0x669a },
2490                         { 0x1f, 0x0005 },
2491                         { 0x05, 0x8330 },
2492                         { 0x06, 0x669a },
2493
2494                         { 0x1f, 0x0002 }
2495                 };
2496                 int val;
2497
2498                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2499
2500                 val = rtl_readphy(tp, 0x0d);
2501                 if ((val & 0x00ff) != 0x006c) {
2502                         static const u32 set[] = {
2503                                 0x0065, 0x0066, 0x0067, 0x0068,
2504                                 0x0069, 0x006a, 0x006b, 0x006c
2505                         };
2506                         int i;
2507
2508                         rtl_writephy(tp, 0x1f, 0x0002);
2509
2510                         val &= 0xff00;
2511                         for (i = 0; i < ARRAY_SIZE(set); i++)
2512                                 rtl_writephy(tp, 0x0d, val | set[i]);
2513                 }
2514         } else {
2515                 static const struct phy_reg phy_reg_init[] = {
2516                         { 0x1f, 0x0002 },
2517                         { 0x05, 0x2642 },
2518                         { 0x1f, 0x0005 },
2519                         { 0x05, 0x8330 },
2520                         { 0x06, 0x2642 }
2521                 };
2522
2523                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2524         }
2525
2526         /* Fine tune PLL performance */
2527         rtl_writephy(tp, 0x1f, 0x0002);
2528         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2529         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2530
2531         /* Switching regulator Slew rate */
2532         rtl_writephy(tp, 0x1f, 0x0002);
2533         rtl_patchphy(tp, 0x0f, 0x0017);
2534
2535         rtl_writephy(tp, 0x1f, 0x0005);
2536         rtl_writephy(tp, 0x05, 0x001b);
2537
2538         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2539
2540         rtl_writephy(tp, 0x1f, 0x0000);
2541 }
2542
2543 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2544 {
2545         static const struct phy_reg phy_reg_init[] = {
2546                 { 0x1f, 0x0002 },
2547                 { 0x10, 0x0008 },
2548                 { 0x0d, 0x006c },
2549
2550                 { 0x1f, 0x0000 },
2551                 { 0x0d, 0xf880 },
2552
2553                 { 0x1f, 0x0001 },
2554                 { 0x17, 0x0cc0 },
2555
2556                 { 0x1f, 0x0001 },
2557                 { 0x0b, 0xa4d8 },
2558                 { 0x09, 0x281c },
2559                 { 0x07, 0x2883 },
2560                 { 0x0a, 0x6b35 },
2561                 { 0x1d, 0x3da4 },
2562                 { 0x1c, 0xeffd },
2563                 { 0x14, 0x7f52 },
2564                 { 0x18, 0x7fc6 },
2565                 { 0x08, 0x0601 },
2566                 { 0x06, 0x4063 },
2567                 { 0x10, 0xf074 },
2568                 { 0x1f, 0x0003 },
2569                 { 0x13, 0x0789 },
2570                 { 0x12, 0xf4bd },
2571                 { 0x1a, 0x04fd },
2572                 { 0x14, 0x84b0 },
2573                 { 0x1f, 0x0000 },
2574                 { 0x00, 0x9200 },
2575
2576                 { 0x1f, 0x0005 },
2577                 { 0x01, 0x0340 },
2578                 { 0x1f, 0x0001 },
2579                 { 0x04, 0x4000 },
2580                 { 0x03, 0x1d21 },
2581                 { 0x02, 0x0c32 },
2582                 { 0x01, 0x0200 },
2583                 { 0x00, 0x5554 },
2584                 { 0x04, 0x4800 },
2585                 { 0x04, 0x4000 },
2586                 { 0x04, 0xf000 },
2587                 { 0x03, 0xdf01 },
2588                 { 0x02, 0xdf20 },
2589                 { 0x01, 0x101a },
2590                 { 0x00, 0xa0ff },
2591                 { 0x04, 0xf800 },
2592                 { 0x04, 0xf000 },
2593                 { 0x1f, 0x0000 },
2594
2595                 { 0x1f, 0x0007 },
2596                 { 0x1e, 0x0023 },
2597                 { 0x16, 0x0000 },
2598                 { 0x1f, 0x0000 }
2599         };
2600
2601         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2602 }
2603
2604 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2605 {
2606         static const struct phy_reg phy_reg_init[] = {
2607                 { 0x1f, 0x0001 },
2608                 { 0x17, 0x0cc0 },
2609
2610                 { 0x1f, 0x0007 },
2611                 { 0x1e, 0x002d },
2612                 { 0x18, 0x0040 },
2613                 { 0x1f, 0x0000 }
2614         };
2615
2616         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2617         rtl_patchphy(tp, 0x0d, 1 << 5);
2618 }
2619
2620 static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2621 {
2622         static const struct phy_reg phy_reg_init[] = {
2623                 /* Enable Delay cap */
2624                 { 0x1f, 0x0005 },
2625                 { 0x05, 0x8b80 },
2626                 { 0x06, 0xc896 },
2627                 { 0x1f, 0x0000 },
2628
2629                 /* Channel estimation fine tune */
2630                 { 0x1f, 0x0001 },
2631                 { 0x0b, 0x6c20 },
2632                 { 0x07, 0x2872 },
2633                 { 0x1c, 0xefff },
2634                 { 0x1f, 0x0003 },
2635                 { 0x14, 0x6420 },
2636                 { 0x1f, 0x0000 },
2637
2638                 /* Update PFM & 10M TX idle timer */
2639                 { 0x1f, 0x0007 },
2640                 { 0x1e, 0x002f },
2641                 { 0x15, 0x1919 },
2642                 { 0x1f, 0x0000 },
2643
2644                 { 0x1f, 0x0007 },
2645                 { 0x1e, 0x00ac },
2646                 { 0x18, 0x0006 },
2647                 { 0x1f, 0x0000 }
2648         };
2649
2650         rtl_apply_firmware(tp);
2651
2652         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2653
2654         /* DCO enable for 10M IDLE Power */
2655         rtl_writephy(tp, 0x1f, 0x0007);
2656         rtl_writephy(tp, 0x1e, 0x0023);
2657         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2658         rtl_writephy(tp, 0x1f, 0x0000);
2659
2660         /* For impedance matching */
2661         rtl_writephy(tp, 0x1f, 0x0002);
2662         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2663         rtl_writephy(tp, 0x1f, 0x0000);
2664
2665         /* PHY auto speed down */
2666         rtl_writephy(tp, 0x1f, 0x0007);
2667         rtl_writephy(tp, 0x1e, 0x002d);
2668         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2669         rtl_writephy(tp, 0x1f, 0x0000);
2670         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2671
2672         rtl_writephy(tp, 0x1f, 0x0005);
2673         rtl_writephy(tp, 0x05, 0x8b86);
2674         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2675         rtl_writephy(tp, 0x1f, 0x0000);
2676
2677         rtl_writephy(tp, 0x1f, 0x0005);
2678         rtl_writephy(tp, 0x05, 0x8b85);
2679         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2680         rtl_writephy(tp, 0x1f, 0x0007);
2681         rtl_writephy(tp, 0x1e, 0x0020);
2682         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2683         rtl_writephy(tp, 0x1f, 0x0006);
2684         rtl_writephy(tp, 0x00, 0x5a00);
2685         rtl_writephy(tp, 0x1f, 0x0000);
2686         rtl_writephy(tp, 0x0d, 0x0007);
2687         rtl_writephy(tp, 0x0e, 0x003c);
2688         rtl_writephy(tp, 0x0d, 0x4007);
2689         rtl_writephy(tp, 0x0e, 0x0000);
2690         rtl_writephy(tp, 0x0d, 0x0000);
2691 }
2692
2693 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2694 {
2695         static const struct phy_reg phy_reg_init[] = {
2696                 { 0x1f, 0x0003 },
2697                 { 0x08, 0x441d },
2698                 { 0x01, 0x9100 },
2699                 { 0x1f, 0x0000 }
2700         };
2701
2702         rtl_writephy(tp, 0x1f, 0x0000);
2703         rtl_patchphy(tp, 0x11, 1 << 12);
2704         rtl_patchphy(tp, 0x19, 1 << 13);
2705         rtl_patchphy(tp, 0x10, 1 << 15);
2706
2707         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2708 }
2709
2710 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2711 {
2712         static const struct phy_reg phy_reg_init[] = {
2713                 { 0x1f, 0x0005 },
2714                 { 0x1a, 0x0000 },
2715                 { 0x1f, 0x0000 },
2716
2717                 { 0x1f, 0x0004 },
2718                 { 0x1c, 0x0000 },
2719                 { 0x1f, 0x0000 },
2720
2721                 { 0x1f, 0x0001 },
2722                 { 0x15, 0x7701 },
2723                 { 0x1f, 0x0000 }
2724         };
2725
2726         /* Disable ALDPS before ram code */
2727         rtl_writephy(tp, 0x1f, 0x0000);
2728         rtl_writephy(tp, 0x18, 0x0310);
2729         msleep(100);
2730
2731         rtl_apply_firmware(tp);
2732
2733         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2734 }
2735
2736 static void rtl_hw_phy_config(struct net_device *dev)
2737 {
2738         struct rtl8169_private *tp = netdev_priv(dev);
2739
2740         rtl8169_print_mac_version(tp);
2741
2742         switch (tp->mac_version) {
2743         case RTL_GIGA_MAC_VER_01:
2744                 break;
2745         case RTL_GIGA_MAC_VER_02:
2746         case RTL_GIGA_MAC_VER_03:
2747                 rtl8169s_hw_phy_config(tp);
2748                 break;
2749         case RTL_GIGA_MAC_VER_04:
2750                 rtl8169sb_hw_phy_config(tp);
2751                 break;
2752         case RTL_GIGA_MAC_VER_05:
2753                 rtl8169scd_hw_phy_config(tp);
2754                 break;
2755         case RTL_GIGA_MAC_VER_06:
2756                 rtl8169sce_hw_phy_config(tp);
2757                 break;
2758         case RTL_GIGA_MAC_VER_07:
2759         case RTL_GIGA_MAC_VER_08:
2760         case RTL_GIGA_MAC_VER_09:
2761                 rtl8102e_hw_phy_config(tp);
2762                 break;
2763         case RTL_GIGA_MAC_VER_11:
2764                 rtl8168bb_hw_phy_config(tp);
2765                 break;
2766         case RTL_GIGA_MAC_VER_12:
2767                 rtl8168bef_hw_phy_config(tp);
2768                 break;
2769         case RTL_GIGA_MAC_VER_17:
2770                 rtl8168bef_hw_phy_config(tp);
2771                 break;
2772         case RTL_GIGA_MAC_VER_18:
2773                 rtl8168cp_1_hw_phy_config(tp);
2774                 break;
2775         case RTL_GIGA_MAC_VER_19:
2776                 rtl8168c_1_hw_phy_config(tp);
2777                 break;
2778         case RTL_GIGA_MAC_VER_20:
2779                 rtl8168c_2_hw_phy_config(tp);
2780                 break;
2781         case RTL_GIGA_MAC_VER_21:
2782                 rtl8168c_3_hw_phy_config(tp);
2783                 break;
2784         case RTL_GIGA_MAC_VER_22:
2785                 rtl8168c_4_hw_phy_config(tp);
2786                 break;
2787         case RTL_GIGA_MAC_VER_23:
2788         case RTL_GIGA_MAC_VER_24:
2789                 rtl8168cp_2_hw_phy_config(tp);
2790                 break;
2791         case RTL_GIGA_MAC_VER_25:
2792                 rtl8168d_1_hw_phy_config(tp);
2793                 break;
2794         case RTL_GIGA_MAC_VER_26:
2795                 rtl8168d_2_hw_phy_config(tp);
2796                 break;
2797         case RTL_GIGA_MAC_VER_27:
2798                 rtl8168d_3_hw_phy_config(tp);
2799                 break;
2800         case RTL_GIGA_MAC_VER_28:
2801                 rtl8168d_4_hw_phy_config(tp);
2802                 break;
2803         case RTL_GIGA_MAC_VER_29:
2804         case RTL_GIGA_MAC_VER_30:
2805                 rtl8105e_hw_phy_config(tp);
2806                 break;
2807         case RTL_GIGA_MAC_VER_31:
2808                 /* None. */
2809                 break;
2810         case RTL_GIGA_MAC_VER_32:
2811         case RTL_GIGA_MAC_VER_33:
2812                 rtl8168e_hw_phy_config(tp);
2813                 break;
2814
2815         default:
2816                 break;
2817         }
2818 }
2819
2820 static void rtl8169_phy_timer(unsigned long __opaque)
2821 {
2822         struct net_device *dev = (struct net_device *)__opaque;
2823         struct rtl8169_private *tp = netdev_priv(dev);
2824         struct timer_list *timer = &tp->timer;
2825         void __iomem *ioaddr = tp->mmio_addr;
2826         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2827
2828         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2829
2830         spin_lock_irq(&tp->lock);
2831
2832         if (tp->phy_reset_pending(tp)) {
2833                 /*
2834                  * A busy loop could burn quite a few cycles on nowadays CPU.
2835                  * Let's delay the execution of the timer for a few ticks.
2836                  */
2837                 timeout = HZ/10;
2838                 goto out_mod_timer;
2839         }
2840
2841         if (tp->link_ok(ioaddr))
2842                 goto out_unlock;
2843
2844         netif_warn(tp, link, dev, "PHY reset until link up\n");
2845
2846         tp->phy_reset_enable(tp);
2847
2848 out_mod_timer:
2849         mod_timer(timer, jiffies + timeout);
2850 out_unlock:
2851         spin_unlock_irq(&tp->lock);
2852 }
2853
2854 #ifdef CONFIG_NET_POLL_CONTROLLER
2855 /*
2856  * Polling 'interrupt' - used by things like netconsole to send skbs
2857  * without having to re-enable interrupts. It's not called while
2858  * the interrupt routine is executing.
2859  */
2860 static void rtl8169_netpoll(struct net_device *dev)
2861 {
2862         struct rtl8169_private *tp = netdev_priv(dev);
2863         struct pci_dev *pdev = tp->pci_dev;
2864
2865         disable_irq(pdev->irq);
2866         rtl8169_interrupt(pdev->irq, dev);
2867         enable_irq(pdev->irq);
2868 }
2869 #endif
2870
2871 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2872                                   void __iomem *ioaddr)
2873 {
2874         iounmap(ioaddr);
2875         pci_release_regions(pdev);
2876         pci_clear_mwi(pdev);
2877         pci_disable_device(pdev);
2878         free_netdev(dev);
2879 }
2880
2881 static void rtl8169_phy_reset(struct net_device *dev,
2882                               struct rtl8169_private *tp)
2883 {
2884         unsigned int i;
2885
2886         tp->phy_reset_enable(tp);
2887         for (i = 0; i < 100; i++) {
2888                 if (!tp->phy_reset_pending(tp))
2889                         return;
2890                 msleep(1);
2891         }
2892         netif_err(tp, link, dev, "PHY reset failed\n");
2893 }
2894
2895 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2896 {
2897         void __iomem *ioaddr = tp->mmio_addr;
2898
2899         rtl_hw_phy_config(dev);
2900
2901         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2902                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2903                 RTL_W8(0x82, 0x01);
2904         }
2905
2906         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2907
2908         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2909                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2910
2911         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2912                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2913                 RTL_W8(0x82, 0x01);
2914                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2915                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2916         }
2917
2918         rtl8169_phy_reset(dev, tp);
2919
2920         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2921                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2922                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2923                           (tp->mii.supports_gmii ?
2924                            ADVERTISED_1000baseT_Half |
2925                            ADVERTISED_1000baseT_Full : 0));
2926
2927         if (RTL_R8(PHYstatus) & TBI_Enable)
2928                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2929 }
2930
2931 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2932 {
2933         void __iomem *ioaddr = tp->mmio_addr;
2934         u32 high;
2935         u32 low;
2936
2937         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2938         high = addr[4] | (addr[5] << 8);
2939
2940         spin_lock_irq(&tp->lock);
2941
2942         RTL_W8(Cfg9346, Cfg9346_Unlock);
2943
2944         RTL_W32(MAC4, high);
2945         RTL_R32(MAC4);
2946
2947         RTL_W32(MAC0, low);
2948         RTL_R32(MAC0);
2949
2950         RTL_W8(Cfg9346, Cfg9346_Lock);
2951
2952         spin_unlock_irq(&tp->lock);
2953 }
2954
2955 static int rtl_set_mac_address(struct net_device *dev, void *p)
2956 {
2957         struct rtl8169_private *tp = netdev_priv(dev);
2958         struct sockaddr *addr = p;
2959
2960         if (!is_valid_ether_addr(addr->sa_data))
2961                 return -EADDRNOTAVAIL;
2962
2963         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2964
2965         rtl_rar_set(tp, dev->dev_addr);
2966
2967         return 0;
2968 }
2969
2970 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2971 {
2972         struct rtl8169_private *tp = netdev_priv(dev);
2973         struct mii_ioctl_data *data = if_mii(ifr);
2974
2975         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2976 }
2977
2978 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2979                           struct mii_ioctl_data *data, int cmd)
2980 {
2981         switch (cmd) {
2982         case SIOCGMIIPHY:
2983                 data->phy_id = 32; /* Internal PHY */
2984                 return 0;
2985
2986         case SIOCGMIIREG:
2987                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2988                 return 0;
2989
2990         case SIOCSMIIREG:
2991                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2992                 return 0;
2993         }
2994         return -EOPNOTSUPP;
2995 }
2996
2997 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2998 {
2999         return -EOPNOTSUPP;
3000 }
3001
3002 static const struct rtl_cfg_info {
3003         void (*hw_start)(struct net_device *);
3004         unsigned int region;
3005         unsigned int align;
3006         u16 intr_event;
3007         u16 napi_event;
3008         unsigned features;
3009         u8 default_ver;
3010 } rtl_cfg_infos [] = {
3011         [RTL_CFG_0] = {
3012                 .hw_start       = rtl_hw_start_8169,
3013                 .region         = 1,
3014                 .align          = 0,
3015                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3016                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3017                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3018                 .features       = RTL_FEATURE_GMII,
3019                 .default_ver    = RTL_GIGA_MAC_VER_01,
3020         },
3021         [RTL_CFG_1] = {
3022                 .hw_start       = rtl_hw_start_8168,
3023                 .region         = 2,
3024                 .align          = 8,
3025                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3026                                   TxErr | TxOK | RxOK | RxErr,
3027                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
3028                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3029                 .default_ver    = RTL_GIGA_MAC_VER_11,
3030         },
3031         [RTL_CFG_2] = {
3032                 .hw_start       = rtl_hw_start_8101,
3033                 .region         = 2,
3034                 .align          = 8,
3035                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3036                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3037                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3038                 .features       = RTL_FEATURE_MSI,
3039                 .default_ver    = RTL_GIGA_MAC_VER_13,
3040         }
3041 };
3042
3043 /* Cfg9346_Unlock assumed. */
3044 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
3045                             const struct rtl_cfg_info *cfg)
3046 {
3047         unsigned msi = 0;
3048         u8 cfg2;
3049
3050         cfg2 = RTL_R8(Config2) & ~MSIEnable;
3051         if (cfg->features & RTL_FEATURE_MSI) {
3052                 if (pci_enable_msi(pdev)) {
3053                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3054                 } else {
3055                         cfg2 |= MSIEnable;
3056                         msi = RTL_FEATURE_MSI;
3057                 }
3058         }
3059         RTL_W8(Config2, cfg2);
3060         return msi;
3061 }
3062
3063 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3064 {
3065         if (tp->features & RTL_FEATURE_MSI) {
3066                 pci_disable_msi(pdev);
3067                 tp->features &= ~RTL_FEATURE_MSI;
3068         }
3069 }
3070
3071 static const struct net_device_ops rtl8169_netdev_ops = {
3072         .ndo_open               = rtl8169_open,
3073         .ndo_stop               = rtl8169_close,
3074         .ndo_get_stats          = rtl8169_get_stats,
3075         .ndo_start_xmit         = rtl8169_start_xmit,
3076         .ndo_tx_timeout         = rtl8169_tx_timeout,
3077         .ndo_validate_addr      = eth_validate_addr,
3078         .ndo_change_mtu         = rtl8169_change_mtu,
3079         .ndo_fix_features       = rtl8169_fix_features,
3080         .ndo_set_features       = rtl8169_set_features,
3081         .ndo_set_mac_address    = rtl_set_mac_address,
3082         .ndo_do_ioctl           = rtl8169_ioctl,
3083         .ndo_set_multicast_list = rtl_set_rx_mode,
3084 #ifdef CONFIG_NET_POLL_CONTROLLER
3085         .ndo_poll_controller    = rtl8169_netpoll,
3086 #endif
3087
3088 };
3089
3090 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3091 {
3092         struct mdio_ops *ops = &tp->mdio_ops;
3093
3094         switch (tp->mac_version) {
3095         case RTL_GIGA_MAC_VER_27:
3096                 ops->write      = r8168dp_1_mdio_write;
3097                 ops->read       = r8168dp_1_mdio_read;
3098                 break;
3099         case RTL_GIGA_MAC_VER_28:
3100         case RTL_GIGA_MAC_VER_31:
3101                 ops->write      = r8168dp_2_mdio_write;
3102                 ops->read       = r8168dp_2_mdio_read;
3103                 break;
3104         default:
3105                 ops->write      = r8169_mdio_write;
3106                 ops->read       = r8169_mdio_read;
3107                 break;
3108         }
3109 }
3110
3111 static void r810x_phy_power_down(struct rtl8169_private *tp)
3112 {
3113         rtl_writephy(tp, 0x1f, 0x0000);
3114         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3115 }
3116
3117 static void r810x_phy_power_up(struct rtl8169_private *tp)
3118 {
3119         rtl_writephy(tp, 0x1f, 0x0000);
3120         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3121 }
3122
3123 static void r810x_pll_power_down(struct rtl8169_private *tp)
3124 {
3125         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3126                 rtl_writephy(tp, 0x1f, 0x0000);
3127                 rtl_writephy(tp, MII_BMCR, 0x0000);
3128                 return;
3129         }
3130
3131         r810x_phy_power_down(tp);
3132 }
3133
3134 static void r810x_pll_power_up(struct rtl8169_private *tp)
3135 {
3136         r810x_phy_power_up(tp);
3137 }
3138
3139 static void r8168_phy_power_up(struct rtl8169_private *tp)
3140 {
3141         rtl_writephy(tp, 0x1f, 0x0000);
3142         switch (tp->mac_version) {
3143         case RTL_GIGA_MAC_VER_11:
3144         case RTL_GIGA_MAC_VER_12:
3145         case RTL_GIGA_MAC_VER_17:
3146         case RTL_GIGA_MAC_VER_18:
3147         case RTL_GIGA_MAC_VER_19:
3148         case RTL_GIGA_MAC_VER_20:
3149         case RTL_GIGA_MAC_VER_21:
3150         case RTL_GIGA_MAC_VER_22:
3151         case RTL_GIGA_MAC_VER_23:
3152         case RTL_GIGA_MAC_VER_24:
3153         case RTL_GIGA_MAC_VER_25:
3154         case RTL_GIGA_MAC_VER_26:
3155         case RTL_GIGA_MAC_VER_27:
3156         case RTL_GIGA_MAC_VER_28:
3157         case RTL_GIGA_MAC_VER_31:
3158                 rtl_writephy(tp, 0x0e, 0x0000);
3159                 break;
3160         default:
3161                 break;
3162         }
3163         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3164 }
3165
3166 static void r8168_phy_power_down(struct rtl8169_private *tp)
3167 {
3168         rtl_writephy(tp, 0x1f, 0x0000);
3169         switch (tp->mac_version) {
3170         case RTL_GIGA_MAC_VER_32:
3171         case RTL_GIGA_MAC_VER_33:
3172                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3173                 break;
3174
3175         case RTL_GIGA_MAC_VER_11:
3176         case RTL_GIGA_MAC_VER_12:
3177         case RTL_GIGA_MAC_VER_17:
3178         case RTL_GIGA_MAC_VER_18:
3179         case RTL_GIGA_MAC_VER_19:
3180         case RTL_GIGA_MAC_VER_20:
3181         case RTL_GIGA_MAC_VER_21:
3182         case RTL_GIGA_MAC_VER_22:
3183         case RTL_GIGA_MAC_VER_23:
3184         case RTL_GIGA_MAC_VER_24:
3185         case RTL_GIGA_MAC_VER_25:
3186         case RTL_GIGA_MAC_VER_26:
3187         case RTL_GIGA_MAC_VER_27:
3188         case RTL_GIGA_MAC_VER_28:
3189         case RTL_GIGA_MAC_VER_31:
3190                 rtl_writephy(tp, 0x0e, 0x0200);
3191         default:
3192                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3193                 break;
3194         }
3195 }
3196
3197 static void r8168_pll_power_down(struct rtl8169_private *tp)
3198 {
3199         void __iomem *ioaddr = tp->mmio_addr;
3200
3201         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3202              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3203              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3204             r8168dp_check_dash(tp)) {
3205                 return;
3206         }
3207
3208         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3209              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3210             (RTL_R16(CPlusCmd) & ASF)) {
3211                 return;
3212         }
3213
3214         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3215             tp->mac_version == RTL_GIGA_MAC_VER_33)
3216                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3217
3218         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3219                 rtl_writephy(tp, 0x1f, 0x0000);
3220                 rtl_writephy(tp, MII_BMCR, 0x0000);
3221
3222                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3223                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3224                 return;
3225         }
3226
3227         r8168_phy_power_down(tp);
3228
3229         switch (tp->mac_version) {
3230         case RTL_GIGA_MAC_VER_25:
3231         case RTL_GIGA_MAC_VER_26:
3232         case RTL_GIGA_MAC_VER_27:
3233         case RTL_GIGA_MAC_VER_28:
3234         case RTL_GIGA_MAC_VER_31:
3235         case RTL_GIGA_MAC_VER_32:
3236         case RTL_GIGA_MAC_VER_33:
3237                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3238                 break;
3239         }
3240 }
3241
3242 static void r8168_pll_power_up(struct rtl8169_private *tp)
3243 {
3244         void __iomem *ioaddr = tp->mmio_addr;
3245
3246         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3247              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3248              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3249             r8168dp_check_dash(tp)) {
3250                 return;
3251         }
3252
3253         switch (tp->mac_version) {
3254         case RTL_GIGA_MAC_VER_25:
3255         case RTL_GIGA_MAC_VER_26:
3256         case RTL_GIGA_MAC_VER_27:
3257         case RTL_GIGA_MAC_VER_28:
3258         case RTL_GIGA_MAC_VER_31:
3259         case RTL_GIGA_MAC_VER_32:
3260         case RTL_GIGA_MAC_VER_33:
3261                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3262                 break;
3263         }
3264
3265         r8168_phy_power_up(tp);
3266 }
3267
3268 static void rtl_pll_power_op(struct rtl8169_private *tp,
3269                              void (*op)(struct rtl8169_private *))
3270 {
3271         if (op)
3272                 op(tp);
3273 }
3274
3275 static void rtl_pll_power_down(struct rtl8169_private *tp)
3276 {
3277         rtl_pll_power_op(tp, tp->pll_power_ops.down);
3278 }
3279
3280 static void rtl_pll_power_up(struct rtl8169_private *tp)
3281 {
3282         rtl_pll_power_op(tp, tp->pll_power_ops.up);
3283 }
3284
3285 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3286 {
3287         struct pll_power_ops *ops = &tp->pll_power_ops;
3288
3289         switch (tp->mac_version) {
3290         case RTL_GIGA_MAC_VER_07:
3291         case RTL_GIGA_MAC_VER_08:
3292         case RTL_GIGA_MAC_VER_09:
3293         case RTL_GIGA_MAC_VER_10:
3294         case RTL_GIGA_MAC_VER_16:
3295         case RTL_GIGA_MAC_VER_29:
3296         case RTL_GIGA_MAC_VER_30:
3297                 ops->down       = r810x_pll_power_down;
3298                 ops->up         = r810x_pll_power_up;
3299                 break;
3300
3301         case RTL_GIGA_MAC_VER_11:
3302         case RTL_GIGA_MAC_VER_12:
3303         case RTL_GIGA_MAC_VER_17:
3304         case RTL_GIGA_MAC_VER_18:
3305         case RTL_GIGA_MAC_VER_19:
3306         case RTL_GIGA_MAC_VER_20:
3307         case RTL_GIGA_MAC_VER_21:
3308         case RTL_GIGA_MAC_VER_22:
3309         case RTL_GIGA_MAC_VER_23:
3310         case RTL_GIGA_MAC_VER_24:
3311         case RTL_GIGA_MAC_VER_25:
3312         case RTL_GIGA_MAC_VER_26:
3313         case RTL_GIGA_MAC_VER_27:
3314         case RTL_GIGA_MAC_VER_28:
3315         case RTL_GIGA_MAC_VER_31:
3316         case RTL_GIGA_MAC_VER_32:
3317         case RTL_GIGA_MAC_VER_33:
3318                 ops->down       = r8168_pll_power_down;
3319                 ops->up         = r8168_pll_power_up;
3320                 break;
3321
3322         default:
3323                 ops->down       = NULL;
3324                 ops->up         = NULL;
3325                 break;
3326         }
3327 }
3328
3329 static void rtl_hw_reset(struct rtl8169_private *tp)
3330 {
3331         void __iomem *ioaddr = tp->mmio_addr;
3332         int i;
3333
3334         /* Soft reset the chip. */
3335         RTL_W8(ChipCmd, CmdReset);
3336
3337         /* Check that the chip has finished the reset. */
3338         for (i = 0; i < 100; i++) {
3339                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3340                         break;
3341                 msleep_interruptible(1);
3342         }
3343 }
3344
3345 static int __devinit
3346 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3347 {
3348         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3349         const unsigned int region = cfg->region;
3350         struct rtl8169_private *tp;
3351         struct mii_if_info *mii;
3352         struct net_device *dev;
3353         void __iomem *ioaddr;
3354         int chipset, i;
3355         int rc;
3356
3357         if (netif_msg_drv(&debug)) {
3358                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3359                        MODULENAME, RTL8169_VERSION);
3360         }
3361
3362         dev = alloc_etherdev(sizeof (*tp));
3363         if (!dev) {
3364                 if (netif_msg_drv(&debug))
3365                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3366                 rc = -ENOMEM;
3367                 goto out;
3368         }
3369
3370         SET_NETDEV_DEV(dev, &pdev->dev);
3371         dev->netdev_ops = &rtl8169_netdev_ops;
3372         tp = netdev_priv(dev);
3373         tp->dev = dev;
3374         tp->pci_dev = pdev;
3375         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3376
3377         mii = &tp->mii;
3378         mii->dev = dev;
3379         mii->mdio_read = rtl_mdio_read;
3380         mii->mdio_write = rtl_mdio_write;
3381         mii->phy_id_mask = 0x1f;
3382         mii->reg_num_mask = 0x1f;
3383         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3384
3385         /* disable ASPM completely as that cause random device stop working
3386          * problems as well as full system hangs for some PCIe devices users */
3387         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3388                                      PCIE_LINK_STATE_CLKPM);
3389
3390         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3391         rc = pci_enable_device(pdev);
3392         if (rc < 0) {
3393                 netif_err(tp, probe, dev, "enable failure\n");
3394                 goto err_out_free_dev_1;
3395         }
3396
3397         if (pci_set_mwi(pdev) < 0)
3398                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3399
3400         /* make sure PCI base addr 1 is MMIO */
3401         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3402                 netif_err(tp, probe, dev,
3403                           "region #%d not an MMIO resource, aborting\n",
3404                           region);
3405                 rc = -ENODEV;
3406                 goto err_out_mwi_2;
3407         }
3408
3409         /* check for weird/broken PCI region reporting */
3410         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3411                 netif_err(tp, probe, dev,
3412                           "Invalid PCI region size(s), aborting\n");
3413                 rc = -ENODEV;
3414                 goto err_out_mwi_2;
3415         }
3416
3417         rc = pci_request_regions(pdev, MODULENAME);
3418         if (rc < 0) {
3419                 netif_err(tp, probe, dev, "could not request regions\n");
3420                 goto err_out_mwi_2;
3421         }
3422
3423         tp->cp_cmd = RxChkSum;
3424
3425         if ((sizeof(dma_addr_t) > 4) &&
3426             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3427                 tp->cp_cmd |= PCIDAC;
3428                 dev->features |= NETIF_F_HIGHDMA;
3429         } else {
3430                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3431                 if (rc < 0) {
3432                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3433                         goto err_out_free_res_3;
3434                 }
3435         }
3436
3437         /* ioremap MMIO region */
3438         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3439         if (!ioaddr) {
3440                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3441                 rc = -EIO;
3442                 goto err_out_free_res_3;
3443         }
3444         tp->mmio_addr = ioaddr;
3445
3446         if (!pci_is_pcie(pdev))
3447                 netif_info(tp, probe, dev, "not PCI Express\n");
3448
3449         RTL_W16(IntrMask, 0x0000);
3450
3451         rtl_hw_reset(tp);
3452
3453         RTL_W16(IntrStatus, 0xffff);
3454
3455         pci_set_master(pdev);
3456
3457         /* Identify chip attached to board */
3458         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3459
3460         /*
3461          * Pretend we are using VLANs; This bypasses a nasty bug where
3462          * Interrupts stop flowing on high load on 8110SCd controllers.
3463          */
3464         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3465                 tp->cp_cmd |= RxVlan;
3466
3467         rtl_init_mdio_ops(tp);
3468         rtl_init_pll_power_ops(tp);
3469
3470         rtl8169_print_mac_version(tp);
3471
3472         chipset = tp->mac_version;
3473         tp->txd_version = rtl_chip_infos[chipset].txd_version;
3474
3475         RTL_W8(Cfg9346, Cfg9346_Unlock);
3476         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3477         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3478         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3479                 tp->features |= RTL_FEATURE_WOL;
3480         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3481                 tp->features |= RTL_FEATURE_WOL;
3482         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3483         RTL_W8(Cfg9346, Cfg9346_Lock);
3484
3485         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3486             (RTL_R8(PHYstatus) & TBI_Enable)) {
3487                 tp->set_speed = rtl8169_set_speed_tbi;
3488                 tp->get_settings = rtl8169_gset_tbi;
3489                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3490                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3491                 tp->link_ok = rtl8169_tbi_link_ok;
3492                 tp->do_ioctl = rtl_tbi_ioctl;
3493         } else {
3494                 tp->set_speed = rtl8169_set_speed_xmii;
3495                 tp->get_settings = rtl8169_gset_xmii;
3496                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3497                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3498                 tp->link_ok = rtl8169_xmii_link_ok;
3499                 tp->do_ioctl = rtl_xmii_ioctl;
3500         }
3501
3502         spin_lock_init(&tp->lock);
3503
3504         /* Get MAC address */
3505         for (i = 0; i < MAC_ADDR_LEN; i++)
3506                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3507         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3508
3509         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3510         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3511         dev->irq = pdev->irq;
3512         dev->base_addr = (unsigned long) ioaddr;
3513
3514         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3515
3516         /* don't enable SG, IP_CSUM and TSO by default - it might not work
3517          * properly for all devices */
3518         dev->features |= NETIF_F_RXCSUM |
3519                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3520
3521         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3522                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3523         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3524                 NETIF_F_HIGHDMA;
3525
3526         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3527                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3528                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3529
3530         tp->intr_mask = 0xffff;
3531         tp->hw_start = cfg->hw_start;
3532         tp->intr_event = cfg->intr_event;
3533         tp->napi_event = cfg->napi_event;
3534
3535         init_timer(&tp->timer);
3536         tp->timer.data = (unsigned long) dev;
3537         tp->timer.function = rtl8169_phy_timer;
3538
3539         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
3540
3541         rc = register_netdev(dev);
3542         if (rc < 0)
3543                 goto err_out_msi_4;
3544
3545         pci_set_drvdata(pdev, dev);
3546
3547         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3548                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3549                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3550
3551         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3552             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3553             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3554                 rtl8168_driver_start(tp);
3555         }
3556
3557         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3558
3559         if (pci_dev_run_wake(pdev))
3560                 pm_runtime_put_noidle(&pdev->dev);
3561
3562         netif_carrier_off(dev);
3563
3564 out:
3565         return rc;
3566
3567 err_out_msi_4:
3568         rtl_disable_msi(pdev, tp);
3569         iounmap(ioaddr);
3570 err_out_free_res_3:
3571         pci_release_regions(pdev);
3572 err_out_mwi_2:
3573         pci_clear_mwi(pdev);
3574         pci_disable_device(pdev);
3575 err_out_free_dev_1:
3576         free_netdev(dev);
3577         goto out;
3578 }
3579
3580 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3581 {
3582         struct net_device *dev = pci_get_drvdata(pdev);
3583         struct rtl8169_private *tp = netdev_priv(dev);
3584
3585         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3586             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3587             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3588                 rtl8168_driver_stop(tp);
3589         }
3590
3591         cancel_delayed_work_sync(&tp->task);
3592
3593         unregister_netdev(dev);
3594
3595         rtl_release_firmware(tp);
3596
3597         if (pci_dev_run_wake(pdev))
3598                 pm_runtime_get_noresume(&pdev->dev);
3599
3600         /* restore original MAC address */
3601         rtl_rar_set(tp, dev->perm_addr);
3602
3603         rtl_disable_msi(pdev, tp);
3604         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3605         pci_set_drvdata(pdev, NULL);
3606 }
3607
3608 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3609 {
3610         struct rtl_fw *rtl_fw;
3611         const char *name;
3612         int rc = -ENOMEM;
3613
3614         name = rtl_lookup_firmware_name(tp);
3615         if (!name)
3616                 goto out_no_firmware;
3617
3618         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3619         if (!rtl_fw)
3620                 goto err_warn;
3621
3622         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3623         if (rc < 0)
3624                 goto err_free;
3625
3626         rc = rtl_check_firmware(tp, rtl_fw);
3627         if (rc < 0)
3628                 goto err_release_firmware;
3629
3630         tp->rtl_fw = rtl_fw;
3631 out:
3632         return;
3633
3634 err_release_firmware:
3635         release_firmware(rtl_fw->fw);
3636 err_free:
3637         kfree(rtl_fw);
3638 err_warn:
3639         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3640                    name, rc);
3641 out_no_firmware:
3642         tp->rtl_fw = NULL;
3643         goto out;
3644 }
3645
3646 static void rtl_request_firmware(struct rtl8169_private *tp)
3647 {
3648         if (IS_ERR(tp->rtl_fw))
3649                 rtl_request_uncached_firmware(tp);
3650 }
3651
3652 static int rtl8169_open(struct net_device *dev)
3653 {
3654         struct rtl8169_private *tp = netdev_priv(dev);
3655         void __iomem *ioaddr = tp->mmio_addr;
3656         struct pci_dev *pdev = tp->pci_dev;
3657         int retval = -ENOMEM;
3658
3659         pm_runtime_get_sync(&pdev->dev);
3660
3661         /*
3662          * Rx and Tx desscriptors needs 256 bytes alignment.
3663          * dma_alloc_coherent provides more.
3664          */
3665         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3666                                              &tp->TxPhyAddr, GFP_KERNEL);
3667         if (!tp->TxDescArray)
3668                 goto err_pm_runtime_put;
3669
3670         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3671                                              &tp->RxPhyAddr, GFP_KERNEL);
3672         if (!tp->RxDescArray)
3673                 goto err_free_tx_0;
3674
3675         retval = rtl8169_init_ring(dev);
3676         if (retval < 0)
3677                 goto err_free_rx_1;
3678
3679         INIT_DELAYED_WORK(&tp->task, NULL);
3680
3681         smp_mb();
3682
3683         rtl_request_firmware(tp);
3684
3685         retval = request_irq(dev->irq, rtl8169_interrupt,
3686                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3687                              dev->name, dev);
3688         if (retval < 0)
3689                 goto err_release_fw_2;
3690
3691         napi_enable(&tp->napi);
3692
3693         rtl8169_init_phy(dev, tp);
3694
3695         rtl8169_set_features(dev, dev->features);
3696
3697         rtl_pll_power_up(tp);
3698
3699         rtl_hw_start(dev);
3700
3701         tp->saved_wolopts = 0;
3702         pm_runtime_put_noidle(&pdev->dev);
3703
3704         rtl8169_check_link_status(dev, tp, ioaddr);
3705 out:
3706         return retval;
3707
3708 err_release_fw_2:
3709         rtl_release_firmware(tp);
3710         rtl8169_rx_clear(tp);
3711 err_free_rx_1:
3712         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3713                           tp->RxPhyAddr);
3714         tp->RxDescArray = NULL;
3715 err_free_tx_0:
3716         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3717                           tp->TxPhyAddr);
3718         tp->TxDescArray = NULL;
3719 err_pm_runtime_put:
3720         pm_runtime_put_noidle(&pdev->dev);
3721         goto out;
3722 }
3723
3724 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3725 {
3726         void __iomem *ioaddr = tp->mmio_addr;
3727
3728         /* Disable interrupts */
3729         rtl8169_irq_mask_and_ack(ioaddr);
3730
3731         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3732             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3733             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3734                 while (RTL_R8(TxPoll) & NPQ)
3735                         udelay(20);
3736
3737         }
3738
3739         /* Reset the chipset */
3740         RTL_W8(ChipCmd, CmdReset);
3741
3742         /* PCI commit */
3743         RTL_R8(ChipCmd);
3744 }
3745
3746 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3747 {
3748         void __iomem *ioaddr = tp->mmio_addr;
3749         u32 cfg = rtl8169_rx_config;
3750
3751         cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
3752         RTL_W32(RxConfig, cfg);
3753
3754         /* Set DMA burst size and Interframe Gap Time */
3755         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3756                 (InterFrameGap << TxInterFrameGapShift));
3757 }
3758
3759 static void rtl_hw_start(struct net_device *dev)
3760 {
3761         struct rtl8169_private *tp = netdev_priv(dev);
3762
3763         rtl_hw_reset(tp);
3764
3765         tp->hw_start(dev);
3766
3767         netif_start_queue(dev);
3768 }
3769
3770 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3771                                          void __iomem *ioaddr)
3772 {
3773         /*
3774          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3775          * register to be written before TxDescAddrLow to work.
3776          * Switching from MMIO to I/O access fixes the issue as well.
3777          */
3778         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3779         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3780         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3781         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3782 }
3783
3784 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3785 {
3786         u16 cmd;
3787
3788         cmd = RTL_R16(CPlusCmd);
3789         RTL_W16(CPlusCmd, cmd);
3790         return cmd;
3791 }
3792
3793 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3794 {
3795         /* Low hurts. Let's disable the filtering. */
3796         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3797 }
3798
3799 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3800 {
3801         static const struct rtl_cfg2_info {
3802                 u32 mac_version;
3803                 u32 clk;
3804                 u32 val;
3805         } cfg2_info [] = {
3806                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3807                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3808                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3809                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3810         };
3811         const struct rtl_cfg2_info *p = cfg2_info;
3812         unsigned int i;
3813         u32 clk;
3814
3815         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3816         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3817                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3818                         RTL_W32(0x7c, p->val);
3819                         break;
3820                 }
3821         }
3822 }
3823
3824 static void rtl_hw_start_8169(struct net_device *dev)
3825 {
3826         struct rtl8169_private *tp = netdev_priv(dev);
3827         void __iomem *ioaddr = tp->mmio_addr;
3828         struct pci_dev *pdev = tp->pci_dev;
3829
3830         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3831                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3832                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3833         }
3834
3835         RTL_W8(Cfg9346, Cfg9346_Unlock);
3836         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3837             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3838             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3839             tp->mac_version == RTL_GIGA_MAC_VER_04)
3840                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3841
3842         RTL_W8(EarlyTxThres, NoEarlyTx);
3843
3844         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3845
3846         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3847             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3848             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3849             tp->mac_version == RTL_GIGA_MAC_VER_04)
3850                 rtl_set_rx_tx_config_registers(tp);
3851
3852         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3853
3854         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3855             tp->mac_version == RTL_GIGA_MAC_VER_03) {
3856                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3857                         "Bit-3 and bit-14 MUST be 1\n");
3858                 tp->cp_cmd |= (1 << 14);
3859         }
3860
3861         RTL_W16(CPlusCmd, tp->cp_cmd);
3862
3863         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3864
3865         /*
3866          * Undocumented corner. Supposedly:
3867          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3868          */
3869         RTL_W16(IntrMitigate, 0x0000);
3870
3871         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3872
3873         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3874             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3875             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3876             tp->mac_version != RTL_GIGA_MAC_VER_04) {
3877                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3878                 rtl_set_rx_tx_config_registers(tp);
3879         }
3880
3881         RTL_W8(Cfg9346, Cfg9346_Lock);
3882
3883         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3884         RTL_R8(IntrMask);
3885
3886         RTL_W32(RxMissed, 0);
3887
3888         rtl_set_rx_mode(dev);
3889
3890         /* no early-rx interrupts */
3891         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3892
3893         /* Enable all known interrupts by setting the interrupt mask. */
3894         RTL_W16(IntrMask, tp->intr_event);
3895 }
3896
3897 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3898 {
3899         int cap = pci_pcie_cap(pdev);
3900
3901         if (cap) {
3902                 u16 ctl;
3903
3904                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3905                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3906                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3907         }
3908 }
3909
3910 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3911 {
3912         u32 csi;
3913
3914         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3915         rtl_csi_write(ioaddr, 0x070c, csi | bits);
3916 }
3917
3918 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3919 {
3920         rtl_csi_access_enable(ioaddr, 0x17000000);
3921 }
3922
3923 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3924 {
3925         rtl_csi_access_enable(ioaddr, 0x27000000);
3926 }
3927
3928 struct ephy_info {
3929         unsigned int offset;
3930         u16 mask;
3931         u16 bits;
3932 };
3933
3934 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3935 {
3936         u16 w;
3937
3938         while (len-- > 0) {
3939                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3940                 rtl_ephy_write(ioaddr, e->offset, w);
3941                 e++;
3942         }
3943 }
3944
3945 static void rtl_disable_clock_request(struct pci_dev *pdev)
3946 {
3947         int cap = pci_pcie_cap(pdev);
3948
3949         if (cap) {
3950                 u16 ctl;
3951
3952                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3953                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3954                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3955         }
3956 }
3957
3958 static void rtl_enable_clock_request(struct pci_dev *pdev)
3959 {
3960         int cap = pci_pcie_cap(pdev);
3961
3962         if (cap) {
3963                 u16 ctl;
3964
3965                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3966                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3967                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3968         }
3969 }
3970
3971 #define R8168_CPCMD_QUIRK_MASK (\
3972         EnableBist | \
3973         Mac_dbgo_oe | \
3974         Force_half_dup | \
3975         Force_rxflow_en | \
3976         Force_txflow_en | \
3977         Cxpl_dbg_sel | \
3978         ASF | \
3979         PktCntrDisable | \
3980         Mac_dbgo_sel)
3981
3982 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3983 {
3984         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3985
3986         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3987
3988         rtl_tx_performance_tweak(pdev,
3989                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3990 }
3991
3992 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3993 {
3994         rtl_hw_start_8168bb(ioaddr, pdev);
3995
3996         RTL_W8(MaxTxPacketSize, TxPacketMax);
3997
3998         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3999 }
4000
4001 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4002 {
4003         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4004
4005         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4006
4007         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4008
4009         rtl_disable_clock_request(pdev);
4010
4011         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4012 }
4013
4014 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4015 {
4016         static const struct ephy_info e_info_8168cp[] = {
4017                 { 0x01, 0,      0x0001 },
4018                 { 0x02, 0x0800, 0x1000 },
4019                 { 0x03, 0,      0x0042 },
4020                 { 0x06, 0x0080, 0x0000 },
4021                 { 0x07, 0,      0x2000 }
4022         };
4023
4024         rtl_csi_access_enable_2(ioaddr);
4025
4026         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4027
4028         __rtl_hw_start_8168cp(ioaddr, pdev);
4029 }
4030
4031 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4032 {
4033         rtl_csi_access_enable_2(ioaddr);
4034
4035         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4036
4037         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4038
4039         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4040 }
4041
4042 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4043 {
4044         rtl_csi_access_enable_2(ioaddr);
4045
4046         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4047
4048         /* Magic. */
4049         RTL_W8(DBG_REG, 0x20);
4050
4051         RTL_W8(MaxTxPacketSize, TxPacketMax);
4052
4053         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4054
4055         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4056 }
4057
4058 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4059 {
4060         static const struct ephy_info e_info_8168c_1[] = {
4061                 { 0x02, 0x0800, 0x1000 },
4062                 { 0x03, 0,      0x0002 },
4063                 { 0x06, 0x0080, 0x0000 }
4064         };
4065
4066         rtl_csi_access_enable_2(ioaddr);
4067
4068         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4069
4070         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4071
4072         __rtl_hw_start_8168cp(ioaddr, pdev);
4073 }
4074
4075 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4076 {
4077         static const struct ephy_info e_info_8168c_2[] = {
4078                 { 0x01, 0,      0x0001 },
4079                 { 0x03, 0x0400, 0x0220 }
4080         };
4081
4082         rtl_csi_access_enable_2(ioaddr);
4083
4084         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4085
4086         __rtl_hw_start_8168cp(ioaddr, pdev);
4087 }
4088
4089 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4090 {
4091         rtl_hw_start_8168c_2(ioaddr, pdev);
4092 }
4093
4094 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4095 {
4096         rtl_csi_access_enable_2(ioaddr);
4097
4098         __rtl_hw_start_8168cp(ioaddr, pdev);
4099 }
4100
4101 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4102 {
4103         rtl_csi_access_enable_2(ioaddr);
4104
4105         rtl_disable_clock_request(pdev);
4106
4107         RTL_W8(MaxTxPacketSize, TxPacketMax);
4108
4109         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4110
4111         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4112 }
4113
4114 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4115 {
4116         rtl_csi_access_enable_1(ioaddr);
4117
4118         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4119
4120         RTL_W8(MaxTxPacketSize, TxPacketMax);
4121
4122         rtl_disable_clock_request(pdev);
4123 }
4124
4125 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4126 {
4127         static const struct ephy_info e_info_8168d_4[] = {
4128                 { 0x0b, ~0,     0x48 },
4129                 { 0x19, 0x20,   0x50 },
4130                 { 0x0c, ~0,     0x20 }
4131         };
4132         int i;
4133
4134         rtl_csi_access_enable_1(ioaddr);
4135
4136         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4137
4138         RTL_W8(MaxTxPacketSize, TxPacketMax);
4139
4140         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4141                 const struct ephy_info *e = e_info_8168d_4 + i;
4142                 u16 w;
4143
4144                 w = rtl_ephy_read(ioaddr, e->offset);
4145                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4146         }
4147
4148         rtl_enable_clock_request(pdev);
4149 }
4150
4151 static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4152 {
4153         static const struct ephy_info e_info_8168e[] = {
4154                 { 0x00, 0x0200, 0x0100 },
4155                 { 0x00, 0x0000, 0x0004 },
4156                 { 0x06, 0x0002, 0x0001 },
4157                 { 0x06, 0x0000, 0x0030 },
4158                 { 0x07, 0x0000, 0x2000 },
4159                 { 0x00, 0x0000, 0x0020 },
4160                 { 0x03, 0x5800, 0x2000 },
4161                 { 0x03, 0x0000, 0x0001 },
4162                 { 0x01, 0x0800, 0x1000 },
4163                 { 0x07, 0x0000, 0x4000 },
4164                 { 0x1e, 0x0000, 0x2000 },
4165                 { 0x19, 0xffff, 0xfe6c },
4166                 { 0x0a, 0x0000, 0x0040 }
4167         };
4168
4169         rtl_csi_access_enable_2(ioaddr);
4170
4171         rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4172
4173         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4174
4175         RTL_W8(MaxTxPacketSize, TxPacketMax);
4176
4177         rtl_disable_clock_request(pdev);
4178
4179         /* Reset tx FIFO pointer */
4180         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4181         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4182
4183         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4184 }
4185
4186 static void rtl_hw_start_8168(struct net_device *dev)
4187 {
4188         struct rtl8169_private *tp = netdev_priv(dev);
4189         void __iomem *ioaddr = tp->mmio_addr;
4190         struct pci_dev *pdev = tp->pci_dev;
4191
4192         RTL_W8(Cfg9346, Cfg9346_Unlock);
4193
4194         RTL_W8(MaxTxPacketSize, TxPacketMax);
4195
4196         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4197
4198         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4199
4200         RTL_W16(CPlusCmd, tp->cp_cmd);
4201
4202         RTL_W16(IntrMitigate, 0x5151);
4203
4204         /* Work around for RxFIFO overflow. */
4205         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4206             tp->mac_version == RTL_GIGA_MAC_VER_22) {
4207                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4208                 tp->intr_event &= ~RxOverflow;
4209         }
4210
4211         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4212
4213         rtl_set_rx_mode(dev);
4214
4215         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4216                 (InterFrameGap << TxInterFrameGapShift));
4217
4218         RTL_R8(IntrMask);
4219
4220         switch (tp->mac_version) {
4221         case RTL_GIGA_MAC_VER_11:
4222                 rtl_hw_start_8168bb(ioaddr, pdev);
4223                 break;
4224
4225         case RTL_GIGA_MAC_VER_12:
4226         case RTL_GIGA_MAC_VER_17:
4227                 rtl_hw_start_8168bef(ioaddr, pdev);
4228                 break;
4229
4230         case RTL_GIGA_MAC_VER_18:
4231                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4232                 break;
4233
4234         case RTL_GIGA_MAC_VER_19:
4235                 rtl_hw_start_8168c_1(ioaddr, pdev);
4236                 break;
4237
4238         case RTL_GIGA_MAC_VER_20:
4239                 rtl_hw_start_8168c_2(ioaddr, pdev);
4240                 break;
4241
4242         case RTL_GIGA_MAC_VER_21:
4243                 rtl_hw_start_8168c_3(ioaddr, pdev);
4244                 break;
4245
4246         case RTL_GIGA_MAC_VER_22:
4247                 rtl_hw_start_8168c_4(ioaddr, pdev);
4248                 break;
4249
4250         case RTL_GIGA_MAC_VER_23:
4251                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4252                 break;
4253
4254         case RTL_GIGA_MAC_VER_24:
4255                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4256                 break;
4257
4258         case RTL_GIGA_MAC_VER_25:
4259         case RTL_GIGA_MAC_VER_26:
4260         case RTL_GIGA_MAC_VER_27:
4261                 rtl_hw_start_8168d(ioaddr, pdev);
4262                 break;
4263
4264         case RTL_GIGA_MAC_VER_28:
4265                 rtl_hw_start_8168d_4(ioaddr, pdev);
4266                 break;
4267
4268         case RTL_GIGA_MAC_VER_31:
4269                 rtl_hw_start_8168dp(ioaddr, pdev);
4270                 break;
4271
4272         case RTL_GIGA_MAC_VER_32:
4273         case RTL_GIGA_MAC_VER_33:
4274                 rtl_hw_start_8168e(ioaddr, pdev);
4275                 break;
4276
4277         default:
4278                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4279                         dev->name, tp->mac_version);
4280                 break;
4281         }
4282
4283         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4284
4285         RTL_W8(Cfg9346, Cfg9346_Lock);
4286
4287         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4288
4289         RTL_W16(IntrMask, tp->intr_event);
4290 }
4291
4292 #define R810X_CPCMD_QUIRK_MASK (\
4293         EnableBist | \
4294         Mac_dbgo_oe | \
4295         Force_half_dup | \
4296         Force_rxflow_en | \
4297         Force_txflow_en | \
4298         Cxpl_dbg_sel | \
4299         ASF | \
4300         PktCntrDisable | \
4301         Mac_dbgo_sel)
4302
4303 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4304 {
4305         static const struct ephy_info e_info_8102e_1[] = {
4306                 { 0x01, 0, 0x6e65 },
4307                 { 0x02, 0, 0x091f },
4308                 { 0x03, 0, 0xc2f9 },
4309                 { 0x06, 0, 0xafb5 },
4310                 { 0x07, 0, 0x0e00 },
4311                 { 0x19, 0, 0xec80 },
4312                 { 0x01, 0, 0x2e65 },
4313                 { 0x01, 0, 0x6e65 }
4314         };
4315         u8 cfg1;
4316
4317         rtl_csi_access_enable_2(ioaddr);
4318
4319         RTL_W8(DBG_REG, FIX_NAK_1);
4320
4321         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4322
4323         RTL_W8(Config1,
4324                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4325         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4326
4327         cfg1 = RTL_R8(Config1);
4328         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4329                 RTL_W8(Config1, cfg1 & ~LEDS0);
4330
4331         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4332 }
4333
4334 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4335 {
4336         rtl_csi_access_enable_2(ioaddr);
4337
4338         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4339
4340         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4341         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4342 }
4343
4344 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4345 {
4346         rtl_hw_start_8102e_2(ioaddr, pdev);
4347
4348         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4349 }
4350
4351 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4352 {
4353         static const struct ephy_info e_info_8105e_1[] = {
4354                 { 0x07, 0, 0x4000 },
4355                 { 0x19, 0, 0x0200 },
4356                 { 0x19, 0, 0x0020 },
4357                 { 0x1e, 0, 0x2000 },
4358                 { 0x03, 0, 0x0001 },
4359                 { 0x19, 0, 0x0100 },
4360                 { 0x19, 0, 0x0004 },
4361                 { 0x0a, 0, 0x0020 }
4362         };
4363
4364         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4365         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4366
4367         /* Disable Early Tally Counter */
4368         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4369
4370         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4371         RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4372
4373         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4374 }
4375
4376 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4377 {
4378         rtl_hw_start_8105e_1(ioaddr, pdev);
4379         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4380 }
4381
4382 static void rtl_hw_start_8101(struct net_device *dev)
4383 {
4384         struct rtl8169_private *tp = netdev_priv(dev);
4385         void __iomem *ioaddr = tp->mmio_addr;
4386         struct pci_dev *pdev = tp->pci_dev;
4387
4388         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4389             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4390                 int cap = pci_pcie_cap(pdev);
4391
4392                 if (cap) {
4393                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4394                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4395                 }
4396         }
4397
4398         RTL_W8(Cfg9346, Cfg9346_Unlock);
4399
4400         switch (tp->mac_version) {
4401         case RTL_GIGA_MAC_VER_07:
4402                 rtl_hw_start_8102e_1(ioaddr, pdev);
4403                 break;
4404
4405         case RTL_GIGA_MAC_VER_08:
4406                 rtl_hw_start_8102e_3(ioaddr, pdev);
4407                 break;
4408
4409         case RTL_GIGA_MAC_VER_09:
4410                 rtl_hw_start_8102e_2(ioaddr, pdev);
4411                 break;
4412
4413         case RTL_GIGA_MAC_VER_29:
4414                 rtl_hw_start_8105e_1(ioaddr, pdev);
4415                 break;
4416         case RTL_GIGA_MAC_VER_30:
4417                 rtl_hw_start_8105e_2(ioaddr, pdev);
4418                 break;
4419         }
4420
4421         RTL_W8(Cfg9346, Cfg9346_Lock);
4422
4423         RTL_W8(MaxTxPacketSize, TxPacketMax);
4424
4425         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4426
4427         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4428         RTL_W16(CPlusCmd, tp->cp_cmd);
4429
4430         RTL_W16(IntrMitigate, 0x0000);
4431
4432         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4433
4434         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4435         rtl_set_rx_tx_config_registers(tp);
4436
4437         RTL_R8(IntrMask);
4438
4439         rtl_set_rx_mode(dev);
4440
4441         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4442
4443         RTL_W16(IntrMask, tp->intr_event);
4444 }
4445
4446 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4447 {
4448         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4449                 return -EINVAL;
4450
4451         dev->mtu = new_mtu;
4452         netdev_update_features(dev);
4453
4454         return 0;
4455 }
4456
4457 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4458 {
4459         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4460         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4461 }
4462
4463 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4464                                      void **data_buff, struct RxDesc *desc)
4465 {
4466         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4467                          DMA_FROM_DEVICE);
4468
4469         kfree(*data_buff);
4470         *data_buff = NULL;
4471         rtl8169_make_unusable_by_asic(desc);
4472 }
4473
4474 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4475 {
4476         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4477
4478         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4479 }
4480
4481 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4482                                        u32 rx_buf_sz)
4483 {
4484         desc->addr = cpu_to_le64(mapping);
4485         wmb();
4486         rtl8169_mark_to_asic(desc, rx_buf_sz);
4487 }
4488
4489 static inline void *rtl8169_align(void *data)
4490 {
4491         return (void *)ALIGN((long)data, 16);
4492 }
4493
4494 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4495                                              struct RxDesc *desc)
4496 {
4497         void *data;
4498         dma_addr_t mapping;
4499         struct device *d = &tp->pci_dev->dev;
4500         struct net_device *dev = tp->dev;
4501         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4502
4503         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4504         if (!data)
4505                 return NULL;
4506
4507         if (rtl8169_align(data) != data) {
4508                 kfree(data);
4509                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4510                 if (!data)
4511                         return NULL;
4512         }
4513
4514         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4515                                  DMA_FROM_DEVICE);
4516         if (unlikely(dma_mapping_error(d, mapping))) {
4517                 if (net_ratelimit())
4518                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4519                 goto err_out;
4520         }
4521
4522         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4523         return data;
4524
4525 err_out:
4526         kfree(data);
4527         return NULL;
4528 }
4529
4530 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4531 {
4532         unsigned int i;
4533
4534         for (i = 0; i < NUM_RX_DESC; i++) {
4535                 if (tp->Rx_databuff[i]) {
4536                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4537                                             tp->RxDescArray + i);
4538                 }
4539         }
4540 }
4541
4542 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4543 {
4544         desc->opts1 |= cpu_to_le32(RingEnd);
4545 }
4546
4547 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4548 {
4549         unsigned int i;
4550
4551         for (i = 0; i < NUM_RX_DESC; i++) {
4552                 void *data;
4553
4554                 if (tp->Rx_databuff[i])
4555                         continue;
4556
4557                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4558                 if (!data) {
4559                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4560                         goto err_out;
4561                 }
4562                 tp->Rx_databuff[i] = data;
4563         }
4564
4565         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4566         return 0;
4567
4568 err_out:
4569         rtl8169_rx_clear(tp);
4570         return -ENOMEM;
4571 }
4572
4573 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4574 {
4575         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4576 }
4577
4578 static int rtl8169_init_ring(struct net_device *dev)
4579 {
4580         struct rtl8169_private *tp = netdev_priv(dev);
4581
4582         rtl8169_init_ring_indexes(tp);
4583
4584         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4585         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4586
4587         return rtl8169_rx_fill(tp);
4588 }
4589
4590 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4591                                  struct TxDesc *desc)
4592 {
4593         unsigned int len = tx_skb->len;
4594
4595         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4596
4597         desc->opts1 = 0x00;
4598         desc->opts2 = 0x00;
4599         desc->addr = 0x00;
4600         tx_skb->len = 0;
4601 }
4602
4603 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4604                                    unsigned int n)
4605 {
4606         unsigned int i;
4607
4608         for (i = 0; i < n; i++) {
4609                 unsigned int entry = (start + i) % NUM_TX_DESC;
4610                 struct ring_info *tx_skb = tp->tx_skb + entry;
4611                 unsigned int len = tx_skb->len;
4612
4613                 if (len) {
4614                         struct sk_buff *skb = tx_skb->skb;
4615
4616                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4617                                              tp->TxDescArray + entry);
4618                         if (skb) {
4619                                 tp->dev->stats.tx_dropped++;
4620                                 dev_kfree_skb(skb);
4621                                 tx_skb->skb = NULL;
4622                         }
4623                 }
4624         }
4625 }
4626
4627 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4628 {
4629         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4630         tp->cur_tx = tp->dirty_tx = 0;
4631 }
4632
4633 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4634 {
4635         struct rtl8169_private *tp = netdev_priv(dev);
4636
4637         PREPARE_DELAYED_WORK(&tp->task, task);
4638         schedule_delayed_work(&tp->task, 4);
4639 }
4640
4641 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4642 {
4643         struct rtl8169_private *tp = netdev_priv(dev);
4644         void __iomem *ioaddr = tp->mmio_addr;
4645
4646         synchronize_irq(dev->irq);
4647
4648         /* Wait for any pending NAPI task to complete */
4649         napi_disable(&tp->napi);
4650
4651         rtl8169_irq_mask_and_ack(ioaddr);
4652
4653         tp->intr_mask = 0xffff;
4654         RTL_W16(IntrMask, tp->intr_event);
4655         napi_enable(&tp->napi);
4656 }
4657
4658 static void rtl8169_reinit_task(struct work_struct *work)
4659 {
4660         struct rtl8169_private *tp =
4661                 container_of(work, struct rtl8169_private, task.work);
4662         struct net_device *dev = tp->dev;
4663         int ret;
4664
4665         rtnl_lock();
4666
4667         if (!netif_running(dev))
4668                 goto out_unlock;
4669
4670         rtl8169_wait_for_quiescence(dev);
4671         rtl8169_close(dev);
4672
4673         ret = rtl8169_open(dev);
4674         if (unlikely(ret < 0)) {
4675                 if (net_ratelimit())
4676                         netif_err(tp, drv, dev,
4677                                   "reinit failure (status = %d). Rescheduling\n",
4678                                   ret);
4679                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4680         }
4681
4682 out_unlock:
4683         rtnl_unlock();
4684 }
4685
4686 static void rtl8169_reset_task(struct work_struct *work)
4687 {
4688         struct rtl8169_private *tp =
4689                 container_of(work, struct rtl8169_private, task.work);
4690         struct net_device *dev = tp->dev;
4691         int i;
4692
4693         rtnl_lock();
4694
4695         if (!netif_running(dev))
4696                 goto out_unlock;
4697
4698         rtl8169_wait_for_quiescence(dev);
4699
4700         for (i = 0; i < NUM_RX_DESC; i++)
4701                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4702
4703         rtl8169_tx_clear(tp);
4704
4705         rtl8169_init_ring_indexes(tp);
4706         rtl_hw_start(dev);
4707         netif_wake_queue(dev);
4708         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4709
4710 out_unlock:
4711         rtnl_unlock();
4712 }
4713
4714 static void rtl8169_tx_timeout(struct net_device *dev)
4715 {
4716         struct rtl8169_private *tp = netdev_priv(dev);
4717
4718         rtl8169_hw_reset(tp);
4719
4720         /* Let's wait a bit while any (async) irq lands on */
4721         rtl8169_schedule_work(dev, rtl8169_reset_task);
4722 }
4723
4724 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4725                               u32 *opts)
4726 {
4727         struct skb_shared_info *info = skb_shinfo(skb);
4728         unsigned int cur_frag, entry;
4729         struct TxDesc * uninitialized_var(txd);
4730         struct device *d = &tp->pci_dev->dev;
4731
4732         entry = tp->cur_tx;
4733         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4734                 skb_frag_t *frag = info->frags + cur_frag;
4735                 dma_addr_t mapping;
4736                 u32 status, len;
4737                 void *addr;
4738
4739                 entry = (entry + 1) % NUM_TX_DESC;
4740
4741                 txd = tp->TxDescArray + entry;
4742                 len = frag->size;
4743                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4744                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4745                 if (unlikely(dma_mapping_error(d, mapping))) {
4746                         if (net_ratelimit())
4747                                 netif_err(tp, drv, tp->dev,
4748                                           "Failed to map TX fragments DMA!\n");
4749                         goto err_out;
4750                 }
4751
4752                 /* Anti gcc 2.95.3 bugware (sic) */
4753                 status = opts[0] | len |
4754                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
4755
4756                 txd->opts1 = cpu_to_le32(status);
4757                 txd->opts2 = cpu_to_le32(opts[1]);
4758                 txd->addr = cpu_to_le64(mapping);
4759
4760                 tp->tx_skb[entry].len = len;
4761         }
4762
4763         if (cur_frag) {
4764                 tp->tx_skb[entry].skb = skb;
4765                 txd->opts1 |= cpu_to_le32(LastFrag);
4766         }
4767
4768         return cur_frag;
4769
4770 err_out:
4771         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4772         return -EIO;
4773 }
4774
4775 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4776                                     struct sk_buff *skb, u32 *opts)
4777 {
4778         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
4779         u32 mss = skb_shinfo(skb)->gso_size;
4780         int offset = info->opts_offset;
4781
4782         if (mss) {
4783                 opts[0] |= TD_LSO;
4784                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4785         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4786                 const struct iphdr *ip = ip_hdr(skb);
4787
4788                 if (ip->protocol == IPPROTO_TCP)
4789                         opts[offset] |= info->checksum.tcp;
4790                 else if (ip->protocol == IPPROTO_UDP)
4791                         opts[offset] |= info->checksum.udp;
4792                 else
4793                         WARN_ON_ONCE(1);
4794         }
4795 }
4796
4797 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4798                                       struct net_device *dev)
4799 {
4800         struct rtl8169_private *tp = netdev_priv(dev);
4801         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4802         struct TxDesc *txd = tp->TxDescArray + entry;
4803         void __iomem *ioaddr = tp->mmio_addr;
4804         struct device *d = &tp->pci_dev->dev;
4805         dma_addr_t mapping;
4806         u32 status, len;
4807         u32 opts[2];
4808         int frags;
4809
4810         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4811                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4812                 goto err_stop_0;
4813         }
4814
4815         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4816                 goto err_stop_0;
4817
4818         len = skb_headlen(skb);
4819         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4820         if (unlikely(dma_mapping_error(d, mapping))) {
4821                 if (net_ratelimit())
4822                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4823                 goto err_dma_0;
4824         }
4825
4826         tp->tx_skb[entry].len = len;
4827         txd->addr = cpu_to_le64(mapping);
4828
4829         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4830         opts[0] = DescOwn;
4831
4832         rtl8169_tso_csum(tp, skb, opts);
4833
4834         frags = rtl8169_xmit_frags(tp, skb, opts);
4835         if (frags < 0)
4836                 goto err_dma_1;
4837         else if (frags)
4838                 opts[0] |= FirstFrag;
4839         else {
4840                 opts[0] |= FirstFrag | LastFrag;
4841                 tp->tx_skb[entry].skb = skb;
4842         }
4843
4844         txd->opts2 = cpu_to_le32(opts[1]);
4845
4846         wmb();
4847
4848         /* Anti gcc 2.95.3 bugware (sic) */
4849         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4850         txd->opts1 = cpu_to_le32(status);
4851
4852         tp->cur_tx += frags + 1;
4853
4854         wmb();
4855
4856         RTL_W8(TxPoll, NPQ);
4857
4858         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4859                 netif_stop_queue(dev);
4860                 smp_rmb();
4861                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4862                         netif_wake_queue(dev);
4863         }
4864
4865         return NETDEV_TX_OK;
4866
4867 err_dma_1:
4868         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4869 err_dma_0:
4870         dev_kfree_skb(skb);
4871         dev->stats.tx_dropped++;
4872         return NETDEV_TX_OK;
4873
4874 err_stop_0:
4875         netif_stop_queue(dev);
4876         dev->stats.tx_dropped++;
4877         return NETDEV_TX_BUSY;
4878 }
4879
4880 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4881 {
4882         struct rtl8169_private *tp = netdev_priv(dev);
4883         struct pci_dev *pdev = tp->pci_dev;
4884         u16 pci_status, pci_cmd;
4885
4886         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4887         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4888
4889         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4890                   pci_cmd, pci_status);
4891
4892         /*
4893          * The recovery sequence below admits a very elaborated explanation:
4894          * - it seems to work;
4895          * - I did not see what else could be done;
4896          * - it makes iop3xx happy.
4897          *
4898          * Feel free to adjust to your needs.
4899          */
4900         if (pdev->broken_parity_status)
4901                 pci_cmd &= ~PCI_COMMAND_PARITY;
4902         else
4903                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4904
4905         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4906
4907         pci_write_config_word(pdev, PCI_STATUS,
4908                 pci_status & (PCI_STATUS_DETECTED_PARITY |
4909                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4910                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4911
4912         /* The infamous DAC f*ckup only happens at boot time */
4913         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4914                 void __iomem *ioaddr = tp->mmio_addr;
4915
4916                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4917                 tp->cp_cmd &= ~PCIDAC;
4918                 RTL_W16(CPlusCmd, tp->cp_cmd);
4919                 dev->features &= ~NETIF_F_HIGHDMA;
4920         }
4921
4922         rtl8169_hw_reset(tp);
4923
4924         rtl8169_schedule_work(dev, rtl8169_reinit_task);
4925 }
4926
4927 static void rtl8169_tx_interrupt(struct net_device *dev,
4928                                  struct rtl8169_private *tp,
4929                                  void __iomem *ioaddr)
4930 {
4931         unsigned int dirty_tx, tx_left;
4932
4933         dirty_tx = tp->dirty_tx;
4934         smp_rmb();
4935         tx_left = tp->cur_tx - dirty_tx;
4936
4937         while (tx_left > 0) {
4938                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4939                 struct ring_info *tx_skb = tp->tx_skb + entry;
4940                 u32 status;
4941
4942                 rmb();
4943                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4944                 if (status & DescOwn)
4945                         break;
4946
4947                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4948                                      tp->TxDescArray + entry);
4949                 if (status & LastFrag) {
4950                         dev->stats.tx_packets++;
4951                         dev->stats.tx_bytes += tx_skb->skb->len;
4952                         dev_kfree_skb(tx_skb->skb);
4953                         tx_skb->skb = NULL;
4954                 }
4955                 dirty_tx++;
4956                 tx_left--;
4957         }
4958
4959         if (tp->dirty_tx != dirty_tx) {
4960                 tp->dirty_tx = dirty_tx;
4961                 smp_wmb();
4962                 if (netif_queue_stopped(dev) &&
4963                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4964                         netif_wake_queue(dev);
4965                 }
4966                 /*
4967                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4968                  * too close. Let's kick an extra TxPoll request when a burst
4969                  * of start_xmit activity is detected (if it is not detected,
4970                  * it is slow enough). -- FR
4971                  */
4972                 smp_rmb();
4973                 if (tp->cur_tx != dirty_tx)
4974                         RTL_W8(TxPoll, NPQ);
4975         }
4976 }
4977
4978 static inline int rtl8169_fragmented_frame(u32 status)
4979 {
4980         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4981 }
4982
4983 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4984 {
4985         u32 status = opts1 & RxProtoMask;
4986
4987         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4988             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4989                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4990         else
4991                 skb_checksum_none_assert(skb);
4992 }
4993
4994 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4995                                            struct rtl8169_private *tp,
4996                                            int pkt_size,
4997                                            dma_addr_t addr)
4998 {
4999         struct sk_buff *skb;
5000         struct device *d = &tp->pci_dev->dev;
5001
5002         data = rtl8169_align(data);
5003         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5004         prefetch(data);
5005         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5006         if (skb)
5007                 memcpy(skb->data, data, pkt_size);
5008         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5009
5010         return skb;
5011 }
5012
5013 static int rtl8169_rx_interrupt(struct net_device *dev,
5014                                 struct rtl8169_private *tp,
5015                                 void __iomem *ioaddr, u32 budget)
5016 {
5017         unsigned int cur_rx, rx_left;
5018         unsigned int count;
5019
5020         cur_rx = tp->cur_rx;
5021         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5022         rx_left = min(rx_left, budget);
5023
5024         for (; rx_left > 0; rx_left--, cur_rx++) {
5025                 unsigned int entry = cur_rx % NUM_RX_DESC;
5026                 struct RxDesc *desc = tp->RxDescArray + entry;
5027                 u32 status;
5028
5029                 rmb();
5030                 status = le32_to_cpu(desc->opts1);
5031
5032                 if (status & DescOwn)
5033                         break;
5034                 if (unlikely(status & RxRES)) {
5035                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5036                                    status);
5037                         dev->stats.rx_errors++;
5038                         if (status & (RxRWT | RxRUNT))
5039                                 dev->stats.rx_length_errors++;
5040                         if (status & RxCRC)
5041                                 dev->stats.rx_crc_errors++;
5042                         if (status & RxFOVF) {
5043                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
5044                                 dev->stats.rx_fifo_errors++;
5045                         }
5046                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5047                 } else {
5048                         struct sk_buff *skb;
5049                         dma_addr_t addr = le64_to_cpu(desc->addr);
5050                         int pkt_size = (status & 0x00001FFF) - 4;
5051
5052                         /*
5053                          * The driver does not support incoming fragmented
5054                          * frames. They are seen as a symptom of over-mtu
5055                          * sized frames.
5056                          */
5057                         if (unlikely(rtl8169_fragmented_frame(status))) {
5058                                 dev->stats.rx_dropped++;
5059                                 dev->stats.rx_length_errors++;
5060                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5061                                 continue;
5062                         }
5063
5064                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5065                                                   tp, pkt_size, addr);
5066                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5067                         if (!skb) {
5068                                 dev->stats.rx_dropped++;
5069                                 continue;
5070                         }
5071
5072                         rtl8169_rx_csum(skb, status);
5073                         skb_put(skb, pkt_size);
5074                         skb->protocol = eth_type_trans(skb, dev);
5075
5076                         rtl8169_rx_vlan_tag(desc, skb);
5077
5078                         napi_gro_receive(&tp->napi, skb);
5079
5080                         dev->stats.rx_bytes += pkt_size;
5081                         dev->stats.rx_packets++;
5082                 }
5083
5084                 /* Work around for AMD plateform. */
5085                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5086                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5087                         desc->opts2 = 0;
5088                         cur_rx++;
5089                 }
5090         }
5091
5092         count = cur_rx - tp->cur_rx;
5093         tp->cur_rx = cur_rx;
5094
5095         tp->dirty_rx += count;
5096
5097         return count;
5098 }
5099
5100 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5101 {
5102         struct net_device *dev = dev_instance;
5103         struct rtl8169_private *tp = netdev_priv(dev);
5104         void __iomem *ioaddr = tp->mmio_addr;
5105         int handled = 0;
5106         int status;
5107
5108         /* loop handling interrupts until we have no new ones or
5109          * we hit a invalid/hotplug case.
5110          */
5111         status = RTL_R16(IntrStatus);
5112         while (status && status != 0xffff) {
5113                 handled = 1;
5114
5115                 /* Handle all of the error cases first. These will reset
5116                  * the chip, so just exit the loop.
5117                  */
5118                 if (unlikely(!netif_running(dev))) {
5119                         rtl8169_asic_down(ioaddr);
5120                         break;
5121                 }
5122
5123                 if (unlikely(status & RxFIFOOver)) {
5124                         switch (tp->mac_version) {
5125                         /* Work around for rx fifo overflow */
5126                         case RTL_GIGA_MAC_VER_11:
5127                         case RTL_GIGA_MAC_VER_22:
5128                         case RTL_GIGA_MAC_VER_26:
5129                                 netif_stop_queue(dev);
5130                                 rtl8169_tx_timeout(dev);
5131                                 goto done;
5132                         /* Testers needed. */
5133                         case RTL_GIGA_MAC_VER_17:
5134                         case RTL_GIGA_MAC_VER_19:
5135                         case RTL_GIGA_MAC_VER_20:
5136                         case RTL_GIGA_MAC_VER_21:
5137                         case RTL_GIGA_MAC_VER_23:
5138                         case RTL_GIGA_MAC_VER_24:
5139                         case RTL_GIGA_MAC_VER_27:
5140                         case RTL_GIGA_MAC_VER_28:
5141                         case RTL_GIGA_MAC_VER_31:
5142                         /* Experimental science. Pktgen proof. */
5143                         case RTL_GIGA_MAC_VER_12:
5144                         case RTL_GIGA_MAC_VER_25:
5145                                 if (status == RxFIFOOver)
5146                                         goto done;
5147                                 break;
5148                         default:
5149                                 break;
5150                         }
5151                 }
5152
5153                 if (unlikely(status & SYSErr)) {
5154                         rtl8169_pcierr_interrupt(dev);
5155                         break;
5156                 }
5157
5158                 if (status & LinkChg)
5159                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5160
5161                 /* We need to see the lastest version of tp->intr_mask to
5162                  * avoid ignoring an MSI interrupt and having to wait for
5163                  * another event which may never come.
5164                  */
5165                 smp_rmb();
5166                 if (status & tp->intr_mask & tp->napi_event) {
5167                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5168                         tp->intr_mask = ~tp->napi_event;
5169
5170                         if (likely(napi_schedule_prep(&tp->napi)))
5171                                 __napi_schedule(&tp->napi);
5172                         else
5173                                 netif_info(tp, intr, dev,
5174                                            "interrupt %04x in poll\n", status);
5175                 }
5176
5177                 /* We only get a new MSI interrupt when all active irq
5178                  * sources on the chip have been acknowledged. So, ack
5179                  * everything we've seen and check if new sources have become
5180                  * active to avoid blocking all interrupts from the chip.
5181                  */
5182                 RTL_W16(IntrStatus,
5183                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5184                 status = RTL_R16(IntrStatus);
5185         }
5186 done:
5187         return IRQ_RETVAL(handled);
5188 }
5189
5190 static int rtl8169_poll(struct napi_struct *napi, int budget)
5191 {
5192         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5193         struct net_device *dev = tp->dev;
5194         void __iomem *ioaddr = tp->mmio_addr;
5195         int work_done;
5196
5197         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5198         rtl8169_tx_interrupt(dev, tp, ioaddr);
5199
5200         if (work_done < budget) {
5201                 napi_complete(napi);
5202
5203                 /* We need for force the visibility of tp->intr_mask
5204                  * for other CPUs, as we can loose an MSI interrupt
5205                  * and potentially wait for a retransmit timeout if we don't.
5206                  * The posted write to IntrMask is safe, as it will
5207                  * eventually make it to the chip and we won't loose anything
5208                  * until it does.
5209                  */
5210                 tp->intr_mask = 0xffff;
5211                 wmb();
5212                 RTL_W16(IntrMask, tp->intr_event);
5213         }
5214
5215         return work_done;
5216 }
5217
5218 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5219 {
5220         struct rtl8169_private *tp = netdev_priv(dev);
5221
5222         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5223                 return;
5224
5225         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5226         RTL_W32(RxMissed, 0);
5227 }
5228
5229 static void rtl8169_down(struct net_device *dev)
5230 {
5231         struct rtl8169_private *tp = netdev_priv(dev);
5232         void __iomem *ioaddr = tp->mmio_addr;
5233
5234         del_timer_sync(&tp->timer);
5235
5236         netif_stop_queue(dev);
5237
5238         napi_disable(&tp->napi);
5239
5240         spin_lock_irq(&tp->lock);
5241
5242         rtl8169_asic_down(ioaddr);
5243         /*
5244          * At this point device interrupts can not be enabled in any function,
5245          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5246          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5247          */
5248         rtl8169_rx_missed(dev, ioaddr);
5249
5250         spin_unlock_irq(&tp->lock);
5251
5252         synchronize_irq(dev->irq);
5253
5254         /* Give a racing hard_start_xmit a few cycles to complete. */
5255         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5256
5257         rtl8169_tx_clear(tp);
5258
5259         rtl8169_rx_clear(tp);
5260
5261         rtl_pll_power_down(tp);
5262 }
5263
5264 static int rtl8169_close(struct net_device *dev)
5265 {
5266         struct rtl8169_private *tp = netdev_priv(dev);
5267         struct pci_dev *pdev = tp->pci_dev;
5268
5269         pm_runtime_get_sync(&pdev->dev);
5270
5271         /* Update counters before going down */
5272         rtl8169_update_counters(dev);
5273
5274         rtl8169_down(dev);
5275
5276         free_irq(dev->irq, dev);
5277
5278         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5279                           tp->RxPhyAddr);
5280         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5281                           tp->TxPhyAddr);
5282         tp->TxDescArray = NULL;
5283         tp->RxDescArray = NULL;
5284
5285         pm_runtime_put_sync(&pdev->dev);
5286
5287         return 0;
5288 }
5289
5290 static void rtl_set_rx_mode(struct net_device *dev)
5291 {
5292         struct rtl8169_private *tp = netdev_priv(dev);
5293         void __iomem *ioaddr = tp->mmio_addr;
5294         unsigned long flags;
5295         u32 mc_filter[2];       /* Multicast hash filter */
5296         int rx_mode;
5297         u32 tmp = 0;
5298
5299         if (dev->flags & IFF_PROMISC) {
5300                 /* Unconditionally log net taps. */
5301                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5302                 rx_mode =
5303                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5304                     AcceptAllPhys;
5305                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5306         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5307                    (dev->flags & IFF_ALLMULTI)) {
5308                 /* Too many to filter perfectly -- accept all multicasts. */
5309                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5310                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5311         } else {
5312                 struct netdev_hw_addr *ha;
5313
5314                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5315                 mc_filter[1] = mc_filter[0] = 0;
5316                 netdev_for_each_mc_addr(ha, dev) {
5317                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5318                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5319                         rx_mode |= AcceptMulticast;
5320                 }
5321         }
5322
5323         spin_lock_irqsave(&tp->lock, flags);
5324
5325         tmp = rtl8169_rx_config | rx_mode |
5326               (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
5327
5328         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5329                 u32 data = mc_filter[0];
5330
5331                 mc_filter[0] = swab32(mc_filter[1]);
5332                 mc_filter[1] = swab32(data);
5333         }
5334
5335         RTL_W32(MAR0 + 4, mc_filter[1]);
5336         RTL_W32(MAR0 + 0, mc_filter[0]);
5337
5338         RTL_W32(RxConfig, tmp);
5339
5340         spin_unlock_irqrestore(&tp->lock, flags);
5341 }
5342
5343 /**
5344  *  rtl8169_get_stats - Get rtl8169 read/write statistics
5345  *  @dev: The Ethernet Device to get statistics for
5346  *
5347  *  Get TX/RX statistics for rtl8169
5348  */
5349 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5350 {
5351         struct rtl8169_private *tp = netdev_priv(dev);
5352         void __iomem *ioaddr = tp->mmio_addr;
5353         unsigned long flags;
5354
5355         if (netif_running(dev)) {
5356                 spin_lock_irqsave(&tp->lock, flags);
5357                 rtl8169_rx_missed(dev, ioaddr);
5358                 spin_unlock_irqrestore(&tp->lock, flags);
5359         }
5360
5361         return &dev->stats;
5362 }
5363
5364 static void rtl8169_net_suspend(struct net_device *dev)
5365 {
5366         struct rtl8169_private *tp = netdev_priv(dev);
5367
5368         if (!netif_running(dev))
5369                 return;
5370
5371         rtl_pll_power_down(tp);
5372
5373         netif_device_detach(dev);
5374         netif_stop_queue(dev);
5375 }
5376
5377 #ifdef CONFIG_PM
5378
5379 static int rtl8169_suspend(struct device *device)
5380 {
5381         struct pci_dev *pdev = to_pci_dev(device);
5382         struct net_device *dev = pci_get_drvdata(pdev);
5383
5384         rtl8169_net_suspend(dev);
5385
5386         return 0;
5387 }
5388
5389 static void __rtl8169_resume(struct net_device *dev)
5390 {
5391         struct rtl8169_private *tp = netdev_priv(dev);
5392
5393         netif_device_attach(dev);
5394
5395         rtl_pll_power_up(tp);
5396
5397         rtl8169_schedule_work(dev, rtl8169_reset_task);
5398 }
5399
5400 static int rtl8169_resume(struct device *device)
5401 {
5402         struct pci_dev *pdev = to_pci_dev(device);
5403         struct net_device *dev = pci_get_drvdata(pdev);
5404         struct rtl8169_private *tp = netdev_priv(dev);
5405
5406         rtl8169_init_phy(dev, tp);
5407
5408         if (netif_running(dev))
5409                 __rtl8169_resume(dev);
5410
5411         return 0;
5412 }
5413
5414 static int rtl8169_runtime_suspend(struct device *device)
5415 {
5416         struct pci_dev *pdev = to_pci_dev(device);
5417         struct net_device *dev = pci_get_drvdata(pdev);
5418         struct rtl8169_private *tp = netdev_priv(dev);
5419
5420         if (!tp->TxDescArray)
5421                 return 0;
5422
5423         spin_lock_irq(&tp->lock);
5424         tp->saved_wolopts = __rtl8169_get_wol(tp);
5425         __rtl8169_set_wol(tp, WAKE_ANY);
5426         spin_unlock_irq(&tp->lock);
5427
5428         rtl8169_net_suspend(dev);
5429
5430         return 0;
5431 }
5432
5433 static int rtl8169_runtime_resume(struct device *device)
5434 {
5435         struct pci_dev *pdev = to_pci_dev(device);
5436         struct net_device *dev = pci_get_drvdata(pdev);
5437         struct rtl8169_private *tp = netdev_priv(dev);
5438
5439         if (!tp->TxDescArray)
5440                 return 0;
5441
5442         spin_lock_irq(&tp->lock);
5443         __rtl8169_set_wol(tp, tp->saved_wolopts);
5444         tp->saved_wolopts = 0;
5445         spin_unlock_irq(&tp->lock);
5446
5447         rtl8169_init_phy(dev, tp);
5448
5449         __rtl8169_resume(dev);
5450
5451         return 0;
5452 }
5453
5454 static int rtl8169_runtime_idle(struct device *device)
5455 {
5456         struct pci_dev *pdev = to_pci_dev(device);
5457         struct net_device *dev = pci_get_drvdata(pdev);
5458         struct rtl8169_private *tp = netdev_priv(dev);
5459
5460         return tp->TxDescArray ? -EBUSY : 0;
5461 }
5462
5463 static const struct dev_pm_ops rtl8169_pm_ops = {
5464         .suspend                = rtl8169_suspend,
5465         .resume                 = rtl8169_resume,
5466         .freeze                 = rtl8169_suspend,
5467         .thaw                   = rtl8169_resume,
5468         .poweroff               = rtl8169_suspend,
5469         .restore                = rtl8169_resume,
5470         .runtime_suspend        = rtl8169_runtime_suspend,
5471         .runtime_resume         = rtl8169_runtime_resume,
5472         .runtime_idle           = rtl8169_runtime_idle,
5473 };
5474
5475 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5476
5477 #else /* !CONFIG_PM */
5478
5479 #define RTL8169_PM_OPS  NULL
5480
5481 #endif /* !CONFIG_PM */
5482
5483 static void rtl_shutdown(struct pci_dev *pdev)
5484 {
5485         struct net_device *dev = pci_get_drvdata(pdev);
5486         struct rtl8169_private *tp = netdev_priv(dev);
5487         void __iomem *ioaddr = tp->mmio_addr;
5488
5489         rtl8169_net_suspend(dev);
5490
5491         /* Restore original MAC address */
5492         rtl_rar_set(tp, dev->perm_addr);
5493
5494         spin_lock_irq(&tp->lock);
5495
5496         rtl8169_asic_down(ioaddr);
5497
5498         spin_unlock_irq(&tp->lock);
5499
5500         if (system_state == SYSTEM_POWER_OFF) {
5501                 /* WoL fails with some 8168 when the receiver is disabled. */
5502                 if (tp->features & RTL_FEATURE_WOL) {
5503                         pci_clear_master(pdev);
5504
5505                         RTL_W8(ChipCmd, CmdRxEnb);
5506                         /* PCI commit */
5507                         RTL_R8(ChipCmd);
5508                 }
5509
5510                 pci_wake_from_d3(pdev, true);
5511                 pci_set_power_state(pdev, PCI_D3hot);
5512         }
5513 }
5514
5515 static struct pci_driver rtl8169_pci_driver = {
5516         .name           = MODULENAME,
5517         .id_table       = rtl8169_pci_tbl,
5518         .probe          = rtl8169_init_one,
5519         .remove         = __devexit_p(rtl8169_remove_one),
5520         .shutdown       = rtl_shutdown,
5521         .driver.pm      = RTL8169_PM_OPS,
5522 };
5523
5524 static int __init rtl8169_init_module(void)
5525 {
5526         return pci_register_driver(&rtl8169_pci_driver);
5527 }
5528
5529 static void __exit rtl8169_cleanup_module(void)
5530 {
5531         pci_unregister_driver(&rtl8169_pci_driver);
5532 }
5533
5534 module_init(rtl8169_init_module);
5535 module_exit(rtl8169_cleanup_module);