r8169: support new firmware format.
[linux-2.6.git] / drivers / net / r8169.c
1 /*
2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3  *
4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6  * Copyright (c) a lot of people too. Please respect their work.
7  *
8  * See MAINTAINERS file for support contact information.
9  */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
31
32 #include <asm/system.h>
33 #include <asm/io.h>
34 #include <asm/irq.h>
35
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
39
40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
45
46 #ifdef RTL8169_DEBUG
47 #define assert(expr) \
48         if (!(expr)) {                                  \
49                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
50                 #expr,__FILE__,__func__,__LINE__);              \
51         }
52 #define dprintk(fmt, args...) \
53         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
54 #else
55 #define assert(expr) do {} while (0)
56 #define dprintk(fmt, args...)   do {} while (0)
57 #endif /* RTL8169_DEBUG */
58
59 #define R8169_MSG_DEFAULT \
60         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
61
62 #define TX_BUFFS_AVAIL(tp) \
63         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
64
65 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
66    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
67 static const int multicast_filter_limit = 32;
68
69 /* MAC address length */
70 #define MAC_ADDR_LEN    6
71
72 #define MAX_READ_REQUEST_SHIFT  12
73 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
74 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
75 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
76 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
77 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
78
79 #define R8169_REGS_SIZE         256
80 #define R8169_NAPI_WEIGHT       64
81 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
82 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
83 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
84 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
85 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
86
87 #define RTL8169_TX_TIMEOUT      (6*HZ)
88 #define RTL8169_PHY_TIMEOUT     (10*HZ)
89
90 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
91 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
92 #define RTL_EEPROM_SIG_ADDR     0x0000
93
94 /* write/read MMIO register */
95 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
96 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
97 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
98 #define RTL_R8(reg)             readb (ioaddr + (reg))
99 #define RTL_R16(reg)            readw (ioaddr + (reg))
100 #define RTL_R32(reg)            readl (ioaddr + (reg))
101
102 enum mac_version {
103         RTL_GIGA_MAC_VER_01 = 0,
104         RTL_GIGA_MAC_VER_02,
105         RTL_GIGA_MAC_VER_03,
106         RTL_GIGA_MAC_VER_04,
107         RTL_GIGA_MAC_VER_05,
108         RTL_GIGA_MAC_VER_06,
109         RTL_GIGA_MAC_VER_07,
110         RTL_GIGA_MAC_VER_08,
111         RTL_GIGA_MAC_VER_09,
112         RTL_GIGA_MAC_VER_10,
113         RTL_GIGA_MAC_VER_11,
114         RTL_GIGA_MAC_VER_12,
115         RTL_GIGA_MAC_VER_13,
116         RTL_GIGA_MAC_VER_14,
117         RTL_GIGA_MAC_VER_15,
118         RTL_GIGA_MAC_VER_16,
119         RTL_GIGA_MAC_VER_17,
120         RTL_GIGA_MAC_VER_18,
121         RTL_GIGA_MAC_VER_19,
122         RTL_GIGA_MAC_VER_20,
123         RTL_GIGA_MAC_VER_21,
124         RTL_GIGA_MAC_VER_22,
125         RTL_GIGA_MAC_VER_23,
126         RTL_GIGA_MAC_VER_24,
127         RTL_GIGA_MAC_VER_25,
128         RTL_GIGA_MAC_VER_26,
129         RTL_GIGA_MAC_VER_27,
130         RTL_GIGA_MAC_VER_28,
131         RTL_GIGA_MAC_VER_29,
132         RTL_GIGA_MAC_VER_30,
133         RTL_GIGA_MAC_VER_31,
134         RTL_GIGA_MAC_VER_32,
135         RTL_GIGA_MAC_VER_33,
136         RTL_GIGA_MAC_NONE   = 0xff,
137 };
138
139 enum rtl_tx_desc_version {
140         RTL_TD_0        = 0,
141         RTL_TD_1        = 1,
142 };
143
144 #define _R(NAME,TD,FW) \
145         { .name = NAME, .txd_version = TD, .fw_name = FW }
146
147 static const struct {
148         const char *name;
149         enum rtl_tx_desc_version txd_version;
150         const char *fw_name;
151 } rtl_chip_infos[] = {
152         /* PCI devices. */
153         [RTL_GIGA_MAC_VER_01] =
154                 _R("RTL8169",           RTL_TD_0, NULL),
155         [RTL_GIGA_MAC_VER_02] =
156                 _R("RTL8169s",          RTL_TD_0, NULL),
157         [RTL_GIGA_MAC_VER_03] =
158                 _R("RTL8110s",          RTL_TD_0, NULL),
159         [RTL_GIGA_MAC_VER_04] =
160                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL),
161         [RTL_GIGA_MAC_VER_05] =
162                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
163         [RTL_GIGA_MAC_VER_06] =
164                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
165         /* PCI-E devices. */
166         [RTL_GIGA_MAC_VER_07] =
167                 _R("RTL8102e",          RTL_TD_1, NULL),
168         [RTL_GIGA_MAC_VER_08] =
169                 _R("RTL8102e",          RTL_TD_1, NULL),
170         [RTL_GIGA_MAC_VER_09] =
171                 _R("RTL8102e",          RTL_TD_1, NULL),
172         [RTL_GIGA_MAC_VER_10] =
173                 _R("RTL8101e",          RTL_TD_0, NULL),
174         [RTL_GIGA_MAC_VER_11] =
175                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
176         [RTL_GIGA_MAC_VER_12] =
177                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
178         [RTL_GIGA_MAC_VER_13] =
179                 _R("RTL8101e",          RTL_TD_0, NULL),
180         [RTL_GIGA_MAC_VER_14] =
181                 _R("RTL8100e",          RTL_TD_0, NULL),
182         [RTL_GIGA_MAC_VER_15] =
183                 _R("RTL8100e",          RTL_TD_0, NULL),
184         [RTL_GIGA_MAC_VER_16] =
185                 _R("RTL8101e",          RTL_TD_0, NULL),
186         [RTL_GIGA_MAC_VER_17] =
187                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
188         [RTL_GIGA_MAC_VER_18] =
189                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
190         [RTL_GIGA_MAC_VER_19] =
191                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
192         [RTL_GIGA_MAC_VER_20] =
193                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
194         [RTL_GIGA_MAC_VER_21] =
195                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
196         [RTL_GIGA_MAC_VER_22] =
197                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
198         [RTL_GIGA_MAC_VER_23] =
199                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
200         [RTL_GIGA_MAC_VER_24] =
201                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
202         [RTL_GIGA_MAC_VER_25] =
203                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1),
204         [RTL_GIGA_MAC_VER_26] =
205                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2),
206         [RTL_GIGA_MAC_VER_27] =
207                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
208         [RTL_GIGA_MAC_VER_28] =
209                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
210         [RTL_GIGA_MAC_VER_29] =
211                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
212         [RTL_GIGA_MAC_VER_30] =
213                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
214         [RTL_GIGA_MAC_VER_31] =
215                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
216         [RTL_GIGA_MAC_VER_32] =
217                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1),
218         [RTL_GIGA_MAC_VER_33] =
219                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2)
220 };
221 #undef _R
222
223 enum cfg_version {
224         RTL_CFG_0 = 0x00,
225         RTL_CFG_1,
226         RTL_CFG_2
227 };
228
229 static void rtl_hw_start_8169(struct net_device *);
230 static void rtl_hw_start_8168(struct net_device *);
231 static void rtl_hw_start_8101(struct net_device *);
232
233 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
234         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
235         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
236         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
237         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
238         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
239         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
240         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
241         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
242         { PCI_VENDOR_ID_LINKSYS,                0x1032,
243                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
244         { 0x0001,                               0x8168,
245                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
246         {0,},
247 };
248
249 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
250
251 static int rx_buf_sz = 16383;
252 static int use_dac;
253 static struct {
254         u32 msg_enable;
255 } debug = { -1 };
256
257 enum rtl_registers {
258         MAC0            = 0,    /* Ethernet hardware address. */
259         MAC4            = 4,
260         MAR0            = 8,    /* Multicast filter. */
261         CounterAddrLow          = 0x10,
262         CounterAddrHigh         = 0x14,
263         TxDescStartAddrLow      = 0x20,
264         TxDescStartAddrHigh     = 0x24,
265         TxHDescStartAddrLow     = 0x28,
266         TxHDescStartAddrHigh    = 0x2c,
267         FLASH           = 0x30,
268         ERSR            = 0x36,
269         ChipCmd         = 0x37,
270         TxPoll          = 0x38,
271         IntrMask        = 0x3c,
272         IntrStatus      = 0x3e,
273         TxConfig        = 0x40,
274         RxConfig        = 0x44,
275
276 #define RTL_RX_CONFIG_MASK              0xff7e1880u
277
278         RxMissed        = 0x4c,
279         Cfg9346         = 0x50,
280         Config0         = 0x51,
281         Config1         = 0x52,
282         Config2         = 0x53,
283         Config3         = 0x54,
284         Config4         = 0x55,
285         Config5         = 0x56,
286         MultiIntr       = 0x5c,
287         PHYAR           = 0x60,
288         PHYstatus       = 0x6c,
289         RxMaxSize       = 0xda,
290         CPlusCmd        = 0xe0,
291         IntrMitigate    = 0xe2,
292         RxDescAddrLow   = 0xe4,
293         RxDescAddrHigh  = 0xe8,
294         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
295
296 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
297
298         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
299
300 #define TxPacketMax     (8064 >> 7)
301
302         FuncEvent       = 0xf0,
303         FuncEventMask   = 0xf4,
304         FuncPresetState = 0xf8,
305         FuncForceEvent  = 0xfc,
306 };
307
308 enum rtl8110_registers {
309         TBICSR                  = 0x64,
310         TBI_ANAR                = 0x68,
311         TBI_LPAR                = 0x6a,
312 };
313
314 enum rtl8168_8101_registers {
315         CSIDR                   = 0x64,
316         CSIAR                   = 0x68,
317 #define CSIAR_FLAG                      0x80000000
318 #define CSIAR_WRITE_CMD                 0x80000000
319 #define CSIAR_BYTE_ENABLE               0x0f
320 #define CSIAR_BYTE_ENABLE_SHIFT         12
321 #define CSIAR_ADDR_MASK                 0x0fff
322         PMCH                    = 0x6f,
323         EPHYAR                  = 0x80,
324 #define EPHYAR_FLAG                     0x80000000
325 #define EPHYAR_WRITE_CMD                0x80000000
326 #define EPHYAR_REG_MASK                 0x1f
327 #define EPHYAR_REG_SHIFT                16
328 #define EPHYAR_DATA_MASK                0xffff
329         DLLPR                   = 0xd0,
330 #define PM_SWITCH                       (1 << 6)
331         DBG_REG                 = 0xd1,
332 #define FIX_NAK_1                       (1 << 4)
333 #define FIX_NAK_2                       (1 << 3)
334         TWSI                    = 0xd2,
335         MCU                     = 0xd3,
336 #define EN_NDP                          (1 << 3)
337 #define EN_OOB_RESET                    (1 << 2)
338         EFUSEAR                 = 0xdc,
339 #define EFUSEAR_FLAG                    0x80000000
340 #define EFUSEAR_WRITE_CMD               0x80000000
341 #define EFUSEAR_READ_CMD                0x00000000
342 #define EFUSEAR_REG_MASK                0x03ff
343 #define EFUSEAR_REG_SHIFT               8
344 #define EFUSEAR_DATA_MASK               0xff
345 };
346
347 enum rtl8168_registers {
348         ERIDR                   = 0x70,
349         ERIAR                   = 0x74,
350 #define ERIAR_FLAG                      0x80000000
351 #define ERIAR_WRITE_CMD                 0x80000000
352 #define ERIAR_READ_CMD                  0x00000000
353 #define ERIAR_ADDR_BYTE_ALIGN           4
354 #define ERIAR_EXGMAC                    0
355 #define ERIAR_MSIX                      1
356 #define ERIAR_ASF                       2
357 #define ERIAR_TYPE_SHIFT                16
358 #define ERIAR_BYTEEN                    0x0f
359 #define ERIAR_BYTEEN_SHIFT              12
360         EPHY_RXER_NUM           = 0x7c,
361         OCPDR                   = 0xb0, /* OCP GPHY access */
362 #define OCPDR_WRITE_CMD                 0x80000000
363 #define OCPDR_READ_CMD                  0x00000000
364 #define OCPDR_REG_MASK                  0x7f
365 #define OCPDR_GPHY_REG_SHIFT            16
366 #define OCPDR_DATA_MASK                 0xffff
367         OCPAR                   = 0xb4,
368 #define OCPAR_FLAG                      0x80000000
369 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
370 #define OCPAR_GPHY_READ_CMD             0x0000f060
371         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
372         MISC                    = 0xf0, /* 8168e only. */
373 #define TXPLA_RST                       (1 << 29)
374 };
375
376 enum rtl_register_content {
377         /* InterruptStatusBits */
378         SYSErr          = 0x8000,
379         PCSTimeout      = 0x4000,
380         SWInt           = 0x0100,
381         TxDescUnavail   = 0x0080,
382         RxFIFOOver      = 0x0040,
383         LinkChg         = 0x0020,
384         RxOverflow      = 0x0010,
385         TxErr           = 0x0008,
386         TxOK            = 0x0004,
387         RxErr           = 0x0002,
388         RxOK            = 0x0001,
389
390         /* RxStatusDesc */
391         RxFOVF  = (1 << 23),
392         RxRWT   = (1 << 22),
393         RxRES   = (1 << 21),
394         RxRUNT  = (1 << 20),
395         RxCRC   = (1 << 19),
396
397         /* ChipCmdBits */
398         CmdReset        = 0x10,
399         CmdRxEnb        = 0x08,
400         CmdTxEnb        = 0x04,
401         RxBufEmpty      = 0x01,
402
403         /* TXPoll register p.5 */
404         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
405         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
406         FSWInt          = 0x01,         /* Forced software interrupt */
407
408         /* Cfg9346Bits */
409         Cfg9346_Lock    = 0x00,
410         Cfg9346_Unlock  = 0xc0,
411
412         /* rx_mode_bits */
413         AcceptErr       = 0x20,
414         AcceptRunt      = 0x10,
415         AcceptBroadcast = 0x08,
416         AcceptMulticast = 0x04,
417         AcceptMyPhys    = 0x02,
418         AcceptAllPhys   = 0x01,
419
420         /* RxConfigBits */
421         RxCfgFIFOShift  = 13,
422         RxCfgDMAShift   =  8,
423
424         /* TxConfigBits */
425         TxInterFrameGapShift = 24,
426         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
427
428         /* Config1 register p.24 */
429         LEDS1           = (1 << 7),
430         LEDS0           = (1 << 6),
431         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
432         Speed_down      = (1 << 4),
433         MEMMAP          = (1 << 3),
434         IOMAP           = (1 << 2),
435         VPD             = (1 << 1),
436         PMEnable        = (1 << 0),     /* Power Management Enable */
437
438         /* Config2 register p. 25 */
439         PCI_Clock_66MHz = 0x01,
440         PCI_Clock_33MHz = 0x00,
441
442         /* Config3 register p.25 */
443         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
444         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
445         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
446
447         /* Config5 register p.27 */
448         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
449         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
450         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
451         Spi_en          = (1 << 3),
452         LanWake         = (1 << 1),     /* LanWake enable/disable */
453         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
454
455         /* TBICSR p.28 */
456         TBIReset        = 0x80000000,
457         TBILoopback     = 0x40000000,
458         TBINwEnable     = 0x20000000,
459         TBINwRestart    = 0x10000000,
460         TBILinkOk       = 0x02000000,
461         TBINwComplete   = 0x01000000,
462
463         /* CPlusCmd p.31 */
464         EnableBist      = (1 << 15),    // 8168 8101
465         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
466         Normal_mode     = (1 << 13),    // unused
467         Force_half_dup  = (1 << 12),    // 8168 8101
468         Force_rxflow_en = (1 << 11),    // 8168 8101
469         Force_txflow_en = (1 << 10),    // 8168 8101
470         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
471         ASF             = (1 << 8),     // 8168 8101
472         PktCntrDisable  = (1 << 7),     // 8168 8101
473         Mac_dbgo_sel    = 0x001c,       // 8168
474         RxVlan          = (1 << 6),
475         RxChkSum        = (1 << 5),
476         PCIDAC          = (1 << 4),
477         PCIMulRW        = (1 << 3),
478         INTT_0          = 0x0000,       // 8168
479         INTT_1          = 0x0001,       // 8168
480         INTT_2          = 0x0002,       // 8168
481         INTT_3          = 0x0003,       // 8168
482
483         /* rtl8169_PHYstatus */
484         TBI_Enable      = 0x80,
485         TxFlowCtrl      = 0x40,
486         RxFlowCtrl      = 0x20,
487         _1000bpsF       = 0x10,
488         _100bps         = 0x08,
489         _10bps          = 0x04,
490         LinkStatus      = 0x02,
491         FullDup         = 0x01,
492
493         /* _TBICSRBit */
494         TBILinkOK       = 0x02000000,
495
496         /* DumpCounterCommand */
497         CounterDump     = 0x8,
498 };
499
500 enum rtl_desc_bit {
501         /* First doubleword. */
502         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
503         RingEnd         = (1 << 30), /* End of descriptor ring */
504         FirstFrag       = (1 << 29), /* First segment of a packet */
505         LastFrag        = (1 << 28), /* Final segment of a packet */
506 };
507
508 /* Generic case. */
509 enum rtl_tx_desc_bit {
510         /* First doubleword. */
511         TD_LSO          = (1 << 27),            /* Large Send Offload */
512 #define TD_MSS_MAX                      0x07ffu /* MSS value */
513
514         /* Second doubleword. */
515         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
516 };
517
518 /* 8169, 8168b and 810x except 8102e. */
519 enum rtl_tx_desc_bit_0 {
520         /* First doubleword. */
521 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
522         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
523         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
524         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
525 };
526
527 /* 8102e, 8168c and beyond. */
528 enum rtl_tx_desc_bit_1 {
529         /* Second doubleword. */
530 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
531         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
532         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
533         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
534 };
535
536 static const struct rtl_tx_desc_info {
537         struct {
538                 u32 udp;
539                 u32 tcp;
540         } checksum;
541         u16 mss_shift;
542         u16 opts_offset;
543 } tx_desc_info [] = {
544         [RTL_TD_0] = {
545                 .checksum = {
546                         .udp    = TD0_IP_CS | TD0_UDP_CS,
547                         .tcp    = TD0_IP_CS | TD0_TCP_CS
548                 },
549                 .mss_shift      = TD0_MSS_SHIFT,
550                 .opts_offset    = 0
551         },
552         [RTL_TD_1] = {
553                 .checksum = {
554                         .udp    = TD1_IP_CS | TD1_UDP_CS,
555                         .tcp    = TD1_IP_CS | TD1_TCP_CS
556                 },
557                 .mss_shift      = TD1_MSS_SHIFT,
558                 .opts_offset    = 1
559         }
560 };
561
562 enum rtl_rx_desc_bit {
563         /* Rx private */
564         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
565         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
566
567 #define RxProtoUDP      (PID1)
568 #define RxProtoTCP      (PID0)
569 #define RxProtoIP       (PID1 | PID0)
570 #define RxProtoMask     RxProtoIP
571
572         IPFail          = (1 << 16), /* IP checksum failed */
573         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
574         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
575         RxVlanTag       = (1 << 16), /* VLAN tag available */
576 };
577
578 #define RsvdMask        0x3fffc000
579
580 struct TxDesc {
581         __le32 opts1;
582         __le32 opts2;
583         __le64 addr;
584 };
585
586 struct RxDesc {
587         __le32 opts1;
588         __le32 opts2;
589         __le64 addr;
590 };
591
592 struct ring_info {
593         struct sk_buff  *skb;
594         u32             len;
595         u8              __pad[sizeof(void *) - sizeof(u32)];
596 };
597
598 enum features {
599         RTL_FEATURE_WOL         = (1 << 0),
600         RTL_FEATURE_MSI         = (1 << 1),
601         RTL_FEATURE_GMII        = (1 << 2),
602 };
603
604 struct rtl8169_counters {
605         __le64  tx_packets;
606         __le64  rx_packets;
607         __le64  tx_errors;
608         __le32  rx_errors;
609         __le16  rx_missed;
610         __le16  align_errors;
611         __le32  tx_one_collision;
612         __le32  tx_multi_collision;
613         __le64  rx_unicast;
614         __le64  rx_broadcast;
615         __le32  rx_multicast;
616         __le16  tx_aborted;
617         __le16  tx_underun;
618 };
619
620 struct rtl8169_private {
621         void __iomem *mmio_addr;        /* memory map physical address */
622         struct pci_dev *pci_dev;
623         struct net_device *dev;
624         struct napi_struct napi;
625         spinlock_t lock;
626         u32 msg_enable;
627         u16 txd_version;
628         u16 mac_version;
629         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
630         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
631         u32 dirty_rx;
632         u32 dirty_tx;
633         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
634         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
635         dma_addr_t TxPhyAddr;
636         dma_addr_t RxPhyAddr;
637         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
638         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
639         struct timer_list timer;
640         u16 cp_cmd;
641         u16 intr_event;
642         u16 napi_event;
643         u16 intr_mask;
644
645         struct mdio_ops {
646                 void (*write)(void __iomem *, int, int);
647                 int (*read)(void __iomem *, int);
648         } mdio_ops;
649
650         struct pll_power_ops {
651                 void (*down)(struct rtl8169_private *);
652                 void (*up)(struct rtl8169_private *);
653         } pll_power_ops;
654
655         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
656         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
657         void (*phy_reset_enable)(struct rtl8169_private *tp);
658         void (*hw_start)(struct net_device *);
659         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
660         unsigned int (*link_ok)(void __iomem *);
661         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
662         int pcie_cap;
663         struct delayed_work task;
664         unsigned features;
665
666         struct mii_if_info mii;
667         struct rtl8169_counters counters;
668         u32 saved_wolopts;
669
670         struct rtl_fw {
671                 const struct firmware *fw;
672
673 #define RTL_VER_SIZE            32
674
675                 char version[RTL_VER_SIZE];
676
677                 struct rtl_fw_phy_action {
678                         __le32 *code;
679                         size_t size;
680                 } phy_action;
681         } *rtl_fw;
682 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN);
683 };
684
685 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
686 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
687 module_param(use_dac, int, 0);
688 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
689 module_param_named(debug, debug.msg_enable, int, 0);
690 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
691 MODULE_LICENSE("GPL");
692 MODULE_VERSION(RTL8169_VERSION);
693 MODULE_FIRMWARE(FIRMWARE_8168D_1);
694 MODULE_FIRMWARE(FIRMWARE_8168D_2);
695 MODULE_FIRMWARE(FIRMWARE_8168E_1);
696 MODULE_FIRMWARE(FIRMWARE_8168E_2);
697 MODULE_FIRMWARE(FIRMWARE_8105E_1);
698
699 static int rtl8169_open(struct net_device *dev);
700 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
701                                       struct net_device *dev);
702 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
703 static int rtl8169_init_ring(struct net_device *dev);
704 static void rtl_hw_start(struct net_device *dev);
705 static int rtl8169_close(struct net_device *dev);
706 static void rtl_set_rx_mode(struct net_device *dev);
707 static void rtl8169_tx_timeout(struct net_device *dev);
708 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
709 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
710                                 void __iomem *, u32 budget);
711 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
712 static void rtl8169_down(struct net_device *dev);
713 static void rtl8169_rx_clear(struct rtl8169_private *tp);
714 static int rtl8169_poll(struct napi_struct *napi, int budget);
715
716 static const unsigned int rtl8169_rx_config =
717         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
718
719 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
720 {
721         void __iomem *ioaddr = tp->mmio_addr;
722         int i;
723
724         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
725         for (i = 0; i < 20; i++) {
726                 udelay(100);
727                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
728                         break;
729         }
730         return RTL_R32(OCPDR);
731 }
732
733 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
734 {
735         void __iomem *ioaddr = tp->mmio_addr;
736         int i;
737
738         RTL_W32(OCPDR, data);
739         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
740         for (i = 0; i < 20; i++) {
741                 udelay(100);
742                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
743                         break;
744         }
745 }
746
747 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
748 {
749         void __iomem *ioaddr = tp->mmio_addr;
750         int i;
751
752         RTL_W8(ERIDR, cmd);
753         RTL_W32(ERIAR, 0x800010e8);
754         msleep(2);
755         for (i = 0; i < 5; i++) {
756                 udelay(100);
757                 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
758                         break;
759         }
760
761         ocp_write(tp, 0x1, 0x30, 0x00000001);
762 }
763
764 #define OOB_CMD_RESET           0x00
765 #define OOB_CMD_DRIVER_START    0x05
766 #define OOB_CMD_DRIVER_STOP     0x06
767
768 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
769 {
770         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
771 }
772
773 static void rtl8168_driver_start(struct rtl8169_private *tp)
774 {
775         u16 reg;
776         int i;
777
778         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
779
780         reg = rtl8168_get_ocp_reg(tp);
781
782         for (i = 0; i < 10; i++) {
783                 msleep(10);
784                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
785                         break;
786         }
787 }
788
789 static void rtl8168_driver_stop(struct rtl8169_private *tp)
790 {
791         u16 reg;
792         int i;
793
794         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
795
796         reg = rtl8168_get_ocp_reg(tp);
797
798         for (i = 0; i < 10; i++) {
799                 msleep(10);
800                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
801                         break;
802         }
803 }
804
805 static int r8168dp_check_dash(struct rtl8169_private *tp)
806 {
807         u16 reg = rtl8168_get_ocp_reg(tp);
808
809         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
810 }
811
812 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
813 {
814         int i;
815
816         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
817
818         for (i = 20; i > 0; i--) {
819                 /*
820                  * Check if the RTL8169 has completed writing to the specified
821                  * MII register.
822                  */
823                 if (!(RTL_R32(PHYAR) & 0x80000000))
824                         break;
825                 udelay(25);
826         }
827         /*
828          * According to hardware specs a 20us delay is required after write
829          * complete indication, but before sending next command.
830          */
831         udelay(20);
832 }
833
834 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
835 {
836         int i, value = -1;
837
838         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
839
840         for (i = 20; i > 0; i--) {
841                 /*
842                  * Check if the RTL8169 has completed retrieving data from
843                  * the specified MII register.
844                  */
845                 if (RTL_R32(PHYAR) & 0x80000000) {
846                         value = RTL_R32(PHYAR) & 0xffff;
847                         break;
848                 }
849                 udelay(25);
850         }
851         /*
852          * According to hardware specs a 20us delay is required after read
853          * complete indication, but before sending next command.
854          */
855         udelay(20);
856
857         return value;
858 }
859
860 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
861 {
862         int i;
863
864         RTL_W32(OCPDR, data |
865                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
866         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
867         RTL_W32(EPHY_RXER_NUM, 0);
868
869         for (i = 0; i < 100; i++) {
870                 mdelay(1);
871                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
872                         break;
873         }
874 }
875
876 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
877 {
878         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
879                 (value & OCPDR_DATA_MASK));
880 }
881
882 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
883 {
884         int i;
885
886         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
887
888         mdelay(1);
889         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
890         RTL_W32(EPHY_RXER_NUM, 0);
891
892         for (i = 0; i < 100; i++) {
893                 mdelay(1);
894                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
895                         break;
896         }
897
898         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
899 }
900
901 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
902
903 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
904 {
905         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
906 }
907
908 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
909 {
910         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
911 }
912
913 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
914 {
915         r8168dp_2_mdio_start(ioaddr);
916
917         r8169_mdio_write(ioaddr, reg_addr, value);
918
919         r8168dp_2_mdio_stop(ioaddr);
920 }
921
922 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
923 {
924         int value;
925
926         r8168dp_2_mdio_start(ioaddr);
927
928         value = r8169_mdio_read(ioaddr, reg_addr);
929
930         r8168dp_2_mdio_stop(ioaddr);
931
932         return value;
933 }
934
935 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
936 {
937         tp->mdio_ops.write(tp->mmio_addr, location, val);
938 }
939
940 static int rtl_readphy(struct rtl8169_private *tp, int location)
941 {
942         return tp->mdio_ops.read(tp->mmio_addr, location);
943 }
944
945 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
946 {
947         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
948 }
949
950 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
951 {
952         int val;
953
954         val = rtl_readphy(tp, reg_addr);
955         rtl_writephy(tp, reg_addr, (val | p) & ~m);
956 }
957
958 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
959                            int val)
960 {
961         struct rtl8169_private *tp = netdev_priv(dev);
962
963         rtl_writephy(tp, location, val);
964 }
965
966 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
967 {
968         struct rtl8169_private *tp = netdev_priv(dev);
969
970         return rtl_readphy(tp, location);
971 }
972
973 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
974 {
975         unsigned int i;
976
977         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
978                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
979
980         for (i = 0; i < 100; i++) {
981                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
982                         break;
983                 udelay(10);
984         }
985 }
986
987 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
988 {
989         u16 value = 0xffff;
990         unsigned int i;
991
992         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
993
994         for (i = 0; i < 100; i++) {
995                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
996                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
997                         break;
998                 }
999                 udelay(10);
1000         }
1001
1002         return value;
1003 }
1004
1005 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1006 {
1007         unsigned int i;
1008
1009         RTL_W32(CSIDR, value);
1010         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1011                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1012
1013         for (i = 0; i < 100; i++) {
1014                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1015                         break;
1016                 udelay(10);
1017         }
1018 }
1019
1020 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1021 {
1022         u32 value = ~0x00;
1023         unsigned int i;
1024
1025         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1026                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1027
1028         for (i = 0; i < 100; i++) {
1029                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1030                         value = RTL_R32(CSIDR);
1031                         break;
1032                 }
1033                 udelay(10);
1034         }
1035
1036         return value;
1037 }
1038
1039 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1040 {
1041         u8 value = 0xff;
1042         unsigned int i;
1043
1044         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1045
1046         for (i = 0; i < 300; i++) {
1047                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1048                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1049                         break;
1050                 }
1051                 udelay(100);
1052         }
1053
1054         return value;
1055 }
1056
1057 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1058 {
1059         RTL_W16(IntrMask, 0x0000);
1060
1061         RTL_W16(IntrStatus, 0xffff);
1062 }
1063
1064 static void rtl8169_asic_down(void __iomem *ioaddr)
1065 {
1066         RTL_W8(ChipCmd, 0x00);
1067         rtl8169_irq_mask_and_ack(ioaddr);
1068         RTL_R16(CPlusCmd);
1069 }
1070
1071 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1072 {
1073         void __iomem *ioaddr = tp->mmio_addr;
1074
1075         return RTL_R32(TBICSR) & TBIReset;
1076 }
1077
1078 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1079 {
1080         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1081 }
1082
1083 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1084 {
1085         return RTL_R32(TBICSR) & TBILinkOk;
1086 }
1087
1088 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1089 {
1090         return RTL_R8(PHYstatus) & LinkStatus;
1091 }
1092
1093 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1094 {
1095         void __iomem *ioaddr = tp->mmio_addr;
1096
1097         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1098 }
1099
1100 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1101 {
1102         unsigned int val;
1103
1104         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1105         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1106 }
1107
1108 static void __rtl8169_check_link_status(struct net_device *dev,
1109                                         struct rtl8169_private *tp,
1110                                         void __iomem *ioaddr, bool pm)
1111 {
1112         unsigned long flags;
1113
1114         spin_lock_irqsave(&tp->lock, flags);
1115         if (tp->link_ok(ioaddr)) {
1116                 /* This is to cancel a scheduled suspend if there's one. */
1117                 if (pm)
1118                         pm_request_resume(&tp->pci_dev->dev);
1119                 netif_carrier_on(dev);
1120                 if (net_ratelimit())
1121                         netif_info(tp, ifup, dev, "link up\n");
1122         } else {
1123                 netif_carrier_off(dev);
1124                 netif_info(tp, ifdown, dev, "link down\n");
1125                 if (pm)
1126                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
1127         }
1128         spin_unlock_irqrestore(&tp->lock, flags);
1129 }
1130
1131 static void rtl8169_check_link_status(struct net_device *dev,
1132                                       struct rtl8169_private *tp,
1133                                       void __iomem *ioaddr)
1134 {
1135         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1136 }
1137
1138 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1139
1140 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1141 {
1142         void __iomem *ioaddr = tp->mmio_addr;
1143         u8 options;
1144         u32 wolopts = 0;
1145
1146         options = RTL_R8(Config1);
1147         if (!(options & PMEnable))
1148                 return 0;
1149
1150         options = RTL_R8(Config3);
1151         if (options & LinkUp)
1152                 wolopts |= WAKE_PHY;
1153         if (options & MagicPacket)
1154                 wolopts |= WAKE_MAGIC;
1155
1156         options = RTL_R8(Config5);
1157         if (options & UWF)
1158                 wolopts |= WAKE_UCAST;
1159         if (options & BWF)
1160                 wolopts |= WAKE_BCAST;
1161         if (options & MWF)
1162                 wolopts |= WAKE_MCAST;
1163
1164         return wolopts;
1165 }
1166
1167 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1168 {
1169         struct rtl8169_private *tp = netdev_priv(dev);
1170
1171         spin_lock_irq(&tp->lock);
1172
1173         wol->supported = WAKE_ANY;
1174         wol->wolopts = __rtl8169_get_wol(tp);
1175
1176         spin_unlock_irq(&tp->lock);
1177 }
1178
1179 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1180 {
1181         void __iomem *ioaddr = tp->mmio_addr;
1182         unsigned int i;
1183         static const struct {
1184                 u32 opt;
1185                 u16 reg;
1186                 u8  mask;
1187         } cfg[] = {
1188                 { WAKE_ANY,   Config1, PMEnable },
1189                 { WAKE_PHY,   Config3, LinkUp },
1190                 { WAKE_MAGIC, Config3, MagicPacket },
1191                 { WAKE_UCAST, Config5, UWF },
1192                 { WAKE_BCAST, Config5, BWF },
1193                 { WAKE_MCAST, Config5, MWF },
1194                 { WAKE_ANY,   Config5, LanWake }
1195         };
1196
1197         RTL_W8(Cfg9346, Cfg9346_Unlock);
1198
1199         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1200                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1201                 if (wolopts & cfg[i].opt)
1202                         options |= cfg[i].mask;
1203                 RTL_W8(cfg[i].reg, options);
1204         }
1205
1206         RTL_W8(Cfg9346, Cfg9346_Lock);
1207 }
1208
1209 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1210 {
1211         struct rtl8169_private *tp = netdev_priv(dev);
1212
1213         spin_lock_irq(&tp->lock);
1214
1215         if (wol->wolopts)
1216                 tp->features |= RTL_FEATURE_WOL;
1217         else
1218                 tp->features &= ~RTL_FEATURE_WOL;
1219         __rtl8169_set_wol(tp, wol->wolopts);
1220         spin_unlock_irq(&tp->lock);
1221
1222         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1223
1224         return 0;
1225 }
1226
1227 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1228 {
1229         return rtl_chip_infos[tp->mac_version].fw_name;
1230 }
1231
1232 static void rtl8169_get_drvinfo(struct net_device *dev,
1233                                 struct ethtool_drvinfo *info)
1234 {
1235         struct rtl8169_private *tp = netdev_priv(dev);
1236         struct rtl_fw *rtl_fw = tp->rtl_fw;
1237
1238         strcpy(info->driver, MODULENAME);
1239         strcpy(info->version, RTL8169_VERSION);
1240         strcpy(info->bus_info, pci_name(tp->pci_dev));
1241         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1242         strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1243                rtl_fw->version);
1244 }
1245
1246 static int rtl8169_get_regs_len(struct net_device *dev)
1247 {
1248         return R8169_REGS_SIZE;
1249 }
1250
1251 static int rtl8169_set_speed_tbi(struct net_device *dev,
1252                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1253 {
1254         struct rtl8169_private *tp = netdev_priv(dev);
1255         void __iomem *ioaddr = tp->mmio_addr;
1256         int ret = 0;
1257         u32 reg;
1258
1259         reg = RTL_R32(TBICSR);
1260         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1261             (duplex == DUPLEX_FULL)) {
1262                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1263         } else if (autoneg == AUTONEG_ENABLE)
1264                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1265         else {
1266                 netif_warn(tp, link, dev,
1267                            "incorrect speed setting refused in TBI mode\n");
1268                 ret = -EOPNOTSUPP;
1269         }
1270
1271         return ret;
1272 }
1273
1274 static int rtl8169_set_speed_xmii(struct net_device *dev,
1275                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1276 {
1277         struct rtl8169_private *tp = netdev_priv(dev);
1278         int giga_ctrl, bmcr;
1279         int rc = -EINVAL;
1280
1281         rtl_writephy(tp, 0x1f, 0x0000);
1282
1283         if (autoneg == AUTONEG_ENABLE) {
1284                 int auto_nego;
1285
1286                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1287                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1288                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1289
1290                 if (adv & ADVERTISED_10baseT_Half)
1291                         auto_nego |= ADVERTISE_10HALF;
1292                 if (adv & ADVERTISED_10baseT_Full)
1293                         auto_nego |= ADVERTISE_10FULL;
1294                 if (adv & ADVERTISED_100baseT_Half)
1295                         auto_nego |= ADVERTISE_100HALF;
1296                 if (adv & ADVERTISED_100baseT_Full)
1297                         auto_nego |= ADVERTISE_100FULL;
1298
1299                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1300
1301                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1302                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1303
1304                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1305                 if (tp->mii.supports_gmii) {
1306                         if (adv & ADVERTISED_1000baseT_Half)
1307                                 giga_ctrl |= ADVERTISE_1000HALF;
1308                         if (adv & ADVERTISED_1000baseT_Full)
1309                                 giga_ctrl |= ADVERTISE_1000FULL;
1310                 } else if (adv & (ADVERTISED_1000baseT_Half |
1311                                   ADVERTISED_1000baseT_Full)) {
1312                         netif_info(tp, link, dev,
1313                                    "PHY does not support 1000Mbps\n");
1314                         goto out;
1315                 }
1316
1317                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1318
1319                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1320                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1321         } else {
1322                 giga_ctrl = 0;
1323
1324                 if (speed == SPEED_10)
1325                         bmcr = 0;
1326                 else if (speed == SPEED_100)
1327                         bmcr = BMCR_SPEED100;
1328                 else
1329                         goto out;
1330
1331                 if (duplex == DUPLEX_FULL)
1332                         bmcr |= BMCR_FULLDPLX;
1333         }
1334
1335         rtl_writephy(tp, MII_BMCR, bmcr);
1336
1337         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1338             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1339                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1340                         rtl_writephy(tp, 0x17, 0x2138);
1341                         rtl_writephy(tp, 0x0e, 0x0260);
1342                 } else {
1343                         rtl_writephy(tp, 0x17, 0x2108);
1344                         rtl_writephy(tp, 0x0e, 0x0000);
1345                 }
1346         }
1347
1348         rc = 0;
1349 out:
1350         return rc;
1351 }
1352
1353 static int rtl8169_set_speed(struct net_device *dev,
1354                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1355 {
1356         struct rtl8169_private *tp = netdev_priv(dev);
1357         int ret;
1358
1359         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1360         if (ret < 0)
1361                 goto out;
1362
1363         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1364             (advertising & ADVERTISED_1000baseT_Full)) {
1365                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1366         }
1367 out:
1368         return ret;
1369 }
1370
1371 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1372 {
1373         struct rtl8169_private *tp = netdev_priv(dev);
1374         unsigned long flags;
1375         int ret;
1376
1377         del_timer_sync(&tp->timer);
1378
1379         spin_lock_irqsave(&tp->lock, flags);
1380         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1381                                 cmd->duplex, cmd->advertising);
1382         spin_unlock_irqrestore(&tp->lock, flags);
1383
1384         return ret;
1385 }
1386
1387 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1388 {
1389         if (dev->mtu > TD_MSS_MAX)
1390                 features &= ~NETIF_F_ALL_TSO;
1391
1392         return features;
1393 }
1394
1395 static int rtl8169_set_features(struct net_device *dev, u32 features)
1396 {
1397         struct rtl8169_private *tp = netdev_priv(dev);
1398         void __iomem *ioaddr = tp->mmio_addr;
1399         unsigned long flags;
1400
1401         spin_lock_irqsave(&tp->lock, flags);
1402
1403         if (features & NETIF_F_RXCSUM)
1404                 tp->cp_cmd |= RxChkSum;
1405         else
1406                 tp->cp_cmd &= ~RxChkSum;
1407
1408         if (dev->features & NETIF_F_HW_VLAN_RX)
1409                 tp->cp_cmd |= RxVlan;
1410         else
1411                 tp->cp_cmd &= ~RxVlan;
1412
1413         RTL_W16(CPlusCmd, tp->cp_cmd);
1414         RTL_R16(CPlusCmd);
1415
1416         spin_unlock_irqrestore(&tp->lock, flags);
1417
1418         return 0;
1419 }
1420
1421 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1422                                       struct sk_buff *skb)
1423 {
1424         return (vlan_tx_tag_present(skb)) ?
1425                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1426 }
1427
1428 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1429 {
1430         u32 opts2 = le32_to_cpu(desc->opts2);
1431
1432         if (opts2 & RxVlanTag)
1433                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1434
1435         desc->opts2 = 0;
1436 }
1437
1438 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1439 {
1440         struct rtl8169_private *tp = netdev_priv(dev);
1441         void __iomem *ioaddr = tp->mmio_addr;
1442         u32 status;
1443
1444         cmd->supported =
1445                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1446         cmd->port = PORT_FIBRE;
1447         cmd->transceiver = XCVR_INTERNAL;
1448
1449         status = RTL_R32(TBICSR);
1450         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1451         cmd->autoneg = !!(status & TBINwEnable);
1452
1453         ethtool_cmd_speed_set(cmd, SPEED_1000);
1454         cmd->duplex = DUPLEX_FULL; /* Always set */
1455
1456         return 0;
1457 }
1458
1459 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1460 {
1461         struct rtl8169_private *tp = netdev_priv(dev);
1462
1463         return mii_ethtool_gset(&tp->mii, cmd);
1464 }
1465
1466 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1467 {
1468         struct rtl8169_private *tp = netdev_priv(dev);
1469         unsigned long flags;
1470         int rc;
1471
1472         spin_lock_irqsave(&tp->lock, flags);
1473
1474         rc = tp->get_settings(dev, cmd);
1475
1476         spin_unlock_irqrestore(&tp->lock, flags);
1477         return rc;
1478 }
1479
1480 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1481                              void *p)
1482 {
1483         struct rtl8169_private *tp = netdev_priv(dev);
1484         unsigned long flags;
1485
1486         if (regs->len > R8169_REGS_SIZE)
1487                 regs->len = R8169_REGS_SIZE;
1488
1489         spin_lock_irqsave(&tp->lock, flags);
1490         memcpy_fromio(p, tp->mmio_addr, regs->len);
1491         spin_unlock_irqrestore(&tp->lock, flags);
1492 }
1493
1494 static u32 rtl8169_get_msglevel(struct net_device *dev)
1495 {
1496         struct rtl8169_private *tp = netdev_priv(dev);
1497
1498         return tp->msg_enable;
1499 }
1500
1501 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1502 {
1503         struct rtl8169_private *tp = netdev_priv(dev);
1504
1505         tp->msg_enable = value;
1506 }
1507
1508 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1509         "tx_packets",
1510         "rx_packets",
1511         "tx_errors",
1512         "rx_errors",
1513         "rx_missed",
1514         "align_errors",
1515         "tx_single_collisions",
1516         "tx_multi_collisions",
1517         "unicast",
1518         "broadcast",
1519         "multicast",
1520         "tx_aborted",
1521         "tx_underrun",
1522 };
1523
1524 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1525 {
1526         switch (sset) {
1527         case ETH_SS_STATS:
1528                 return ARRAY_SIZE(rtl8169_gstrings);
1529         default:
1530                 return -EOPNOTSUPP;
1531         }
1532 }
1533
1534 static void rtl8169_update_counters(struct net_device *dev)
1535 {
1536         struct rtl8169_private *tp = netdev_priv(dev);
1537         void __iomem *ioaddr = tp->mmio_addr;
1538         struct device *d = &tp->pci_dev->dev;
1539         struct rtl8169_counters *counters;
1540         dma_addr_t paddr;
1541         u32 cmd;
1542         int wait = 1000;
1543
1544         /*
1545          * Some chips are unable to dump tally counters when the receiver
1546          * is disabled.
1547          */
1548         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1549                 return;
1550
1551         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1552         if (!counters)
1553                 return;
1554
1555         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1556         cmd = (u64)paddr & DMA_BIT_MASK(32);
1557         RTL_W32(CounterAddrLow, cmd);
1558         RTL_W32(CounterAddrLow, cmd | CounterDump);
1559
1560         while (wait--) {
1561                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1562                         memcpy(&tp->counters, counters, sizeof(*counters));
1563                         break;
1564                 }
1565                 udelay(10);
1566         }
1567
1568         RTL_W32(CounterAddrLow, 0);
1569         RTL_W32(CounterAddrHigh, 0);
1570
1571         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1572 }
1573
1574 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1575                                       struct ethtool_stats *stats, u64 *data)
1576 {
1577         struct rtl8169_private *tp = netdev_priv(dev);
1578
1579         ASSERT_RTNL();
1580
1581         rtl8169_update_counters(dev);
1582
1583         data[0] = le64_to_cpu(tp->counters.tx_packets);
1584         data[1] = le64_to_cpu(tp->counters.rx_packets);
1585         data[2] = le64_to_cpu(tp->counters.tx_errors);
1586         data[3] = le32_to_cpu(tp->counters.rx_errors);
1587         data[4] = le16_to_cpu(tp->counters.rx_missed);
1588         data[5] = le16_to_cpu(tp->counters.align_errors);
1589         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1590         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1591         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1592         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1593         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1594         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1595         data[12] = le16_to_cpu(tp->counters.tx_underun);
1596 }
1597
1598 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1599 {
1600         switch(stringset) {
1601         case ETH_SS_STATS:
1602                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1603                 break;
1604         }
1605 }
1606
1607 static const struct ethtool_ops rtl8169_ethtool_ops = {
1608         .get_drvinfo            = rtl8169_get_drvinfo,
1609         .get_regs_len           = rtl8169_get_regs_len,
1610         .get_link               = ethtool_op_get_link,
1611         .get_settings           = rtl8169_get_settings,
1612         .set_settings           = rtl8169_set_settings,
1613         .get_msglevel           = rtl8169_get_msglevel,
1614         .set_msglevel           = rtl8169_set_msglevel,
1615         .get_regs               = rtl8169_get_regs,
1616         .get_wol                = rtl8169_get_wol,
1617         .set_wol                = rtl8169_set_wol,
1618         .get_strings            = rtl8169_get_strings,
1619         .get_sset_count         = rtl8169_get_sset_count,
1620         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1621 };
1622
1623 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1624                                     struct net_device *dev, u8 default_version)
1625 {
1626         void __iomem *ioaddr = tp->mmio_addr;
1627         /*
1628          * The driver currently handles the 8168Bf and the 8168Be identically
1629          * but they can be identified more specifically through the test below
1630          * if needed:
1631          *
1632          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1633          *
1634          * Same thing for the 8101Eb and the 8101Ec:
1635          *
1636          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1637          */
1638         static const struct {
1639                 u32 mask;
1640                 u32 val;
1641                 int mac_version;
1642         } mac_info[] = {
1643                 /* 8168E family. */
1644                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1645                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1646                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1647
1648                 /* 8168D family. */
1649                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1650                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1651                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1652
1653                 /* 8168DP family. */
1654                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1655                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1656                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1657
1658                 /* 8168C family. */
1659                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1660                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1661                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1662                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1663                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1664                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1665                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1666                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1667                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1668
1669                 /* 8168B family. */
1670                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1671                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1672                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1673                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1674
1675                 /* 8101 family. */
1676                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1677                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1678                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1679                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1680                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1681                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1682                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1683                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1684                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1685                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1686                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1687                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1688                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1689                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1690                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1691                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1692                 /* FIXME: where did these entries come from ? -- FR */
1693                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1694                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1695
1696                 /* 8110 family. */
1697                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1698                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1699                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1700                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1701                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1702                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1703
1704                 /* Catch-all */
1705                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1706         }, *p = mac_info;
1707         u32 reg;
1708
1709         reg = RTL_R32(TxConfig);
1710         while ((reg & p->mask) != p->val)
1711                 p++;
1712         tp->mac_version = p->mac_version;
1713
1714         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1715                 netif_notice(tp, probe, dev,
1716                              "unknown MAC, using family default\n");
1717                 tp->mac_version = default_version;
1718         }
1719 }
1720
1721 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1722 {
1723         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1724 }
1725
1726 struct phy_reg {
1727         u16 reg;
1728         u16 val;
1729 };
1730
1731 static void rtl_writephy_batch(struct rtl8169_private *tp,
1732                                const struct phy_reg *regs, int len)
1733 {
1734         while (len-- > 0) {
1735                 rtl_writephy(tp, regs->reg, regs->val);
1736                 regs++;
1737         }
1738 }
1739
1740 #define PHY_READ                0x00000000
1741 #define PHY_DATA_OR             0x10000000
1742 #define PHY_DATA_AND            0x20000000
1743 #define PHY_BJMPN               0x30000000
1744 #define PHY_READ_EFUSE          0x40000000
1745 #define PHY_READ_MAC_BYTE       0x50000000
1746 #define PHY_WRITE_MAC_BYTE      0x60000000
1747 #define PHY_CLEAR_READCOUNT     0x70000000
1748 #define PHY_WRITE               0x80000000
1749 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1750 #define PHY_COMP_EQ_SKIPN       0xa0000000
1751 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1752 #define PHY_WRITE_PREVIOUS      0xc0000000
1753 #define PHY_SKIPN               0xd0000000
1754 #define PHY_DELAY_MS            0xe0000000
1755 #define PHY_WRITE_ERI_WORD      0xf0000000
1756
1757 struct fw_info {
1758         u32     magic;
1759         char    version[RTL_VER_SIZE];
1760         __le32  fw_start;
1761         __le32  fw_len;
1762         u8      chksum;
1763 } __packed;
1764
1765 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1766
1767 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1768 {
1769         const struct firmware *fw = rtl_fw->fw;
1770         struct fw_info *fw_info = (struct fw_info *)fw->data;
1771         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1772         char *version = rtl_fw->version;
1773         bool rc = false;
1774
1775         if (fw->size < FW_OPCODE_SIZE)
1776                 goto out;
1777
1778         if (!fw_info->magic) {
1779                 size_t i, size, start;
1780                 u8 checksum = 0;
1781
1782                 if (fw->size < sizeof(*fw_info))
1783                         goto out;
1784
1785                 for (i = 0; i < fw->size; i++)
1786                         checksum += fw->data[i];
1787                 if (checksum != 0)
1788                         goto out;
1789
1790                 start = le32_to_cpu(fw_info->fw_start);
1791                 if (start > fw->size)
1792                         goto out;
1793
1794                 size = le32_to_cpu(fw_info->fw_len);
1795                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1796                         goto out;
1797
1798                 memcpy(version, fw_info->version, RTL_VER_SIZE);
1799
1800                 pa->code = (__le32 *)(fw->data + start);
1801                 pa->size = size;
1802         } else {
1803                 if (fw->size % FW_OPCODE_SIZE)
1804                         goto out;
1805
1806                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1807
1808                 pa->code = (__le32 *)fw->data;
1809                 pa->size = fw->size / FW_OPCODE_SIZE;
1810         }
1811         version[RTL_VER_SIZE - 1] = 0;
1812
1813         rc = true;
1814 out:
1815         return rc;
1816 }
1817
1818 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1819 {
1820         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1821         struct net_device *dev = tp->dev;
1822         u32 predata, count;
1823         size_t index;
1824
1825         if (!rtl_fw_format_ok(tp, rtl_fw)) {
1826                 netif_err(tp, probe, dev, "invalid firwmare\n");
1827                 return;
1828         }
1829
1830         for (index = 0; index < pa->size; index++) {
1831                 u32 action = le32_to_cpu(pa->code[index]);
1832                 u32 regno = (action & 0x0fff0000) >> 16;
1833
1834                 switch(action & 0xf0000000) {
1835                 case PHY_READ:
1836                 case PHY_DATA_OR:
1837                 case PHY_DATA_AND:
1838                 case PHY_READ_EFUSE:
1839                 case PHY_CLEAR_READCOUNT:
1840                 case PHY_WRITE:
1841                 case PHY_WRITE_PREVIOUS:
1842                 case PHY_DELAY_MS:
1843                         break;
1844
1845                 case PHY_BJMPN:
1846                         if (regno > index) {
1847                                 netif_err(tp, probe, tp->dev,
1848                                           "Out of range of firmware\n");
1849                                 return;
1850                         }
1851                         break;
1852                 case PHY_READCOUNT_EQ_SKIP:
1853                         if (index + 2 >= pa->size) {
1854                                 netif_err(tp, probe, tp->dev,
1855                                           "Out of range of firmware\n");
1856                                 return;
1857                         }
1858                         break;
1859                 case PHY_COMP_EQ_SKIPN:
1860                 case PHY_COMP_NEQ_SKIPN:
1861                 case PHY_SKIPN:
1862                         if (index + 1 + regno >= pa->size) {
1863                                 netif_err(tp, probe, tp->dev,
1864                                           "Out of range of firmware\n");
1865                                 return;
1866                         }
1867                         break;
1868
1869                 case PHY_READ_MAC_BYTE:
1870                 case PHY_WRITE_MAC_BYTE:
1871                 case PHY_WRITE_ERI_WORD:
1872                 default:
1873                         netif_err(tp, probe, tp->dev,
1874                                   "Invalid action 0x%08x\n", action);
1875                         return;
1876                 }
1877         }
1878
1879         predata = 0;
1880         count = 0;
1881
1882         for (index = 0; index < pa->size; ) {
1883                 u32 action = le32_to_cpu(pa->code[index]);
1884                 u32 data = action & 0x0000ffff;
1885                 u32 regno = (action & 0x0fff0000) >> 16;
1886
1887                 if (!action)
1888                         break;
1889
1890                 switch(action & 0xf0000000) {
1891                 case PHY_READ:
1892                         predata = rtl_readphy(tp, regno);
1893                         count++;
1894                         index++;
1895                         break;
1896                 case PHY_DATA_OR:
1897                         predata |= data;
1898                         index++;
1899                         break;
1900                 case PHY_DATA_AND:
1901                         predata &= data;
1902                         index++;
1903                         break;
1904                 case PHY_BJMPN:
1905                         index -= regno;
1906                         break;
1907                 case PHY_READ_EFUSE:
1908                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1909                         index++;
1910                         break;
1911                 case PHY_CLEAR_READCOUNT:
1912                         count = 0;
1913                         index++;
1914                         break;
1915                 case PHY_WRITE:
1916                         rtl_writephy(tp, regno, data);
1917                         index++;
1918                         break;
1919                 case PHY_READCOUNT_EQ_SKIP:
1920                         index += (count == data) ? 2 : 1;
1921                         break;
1922                 case PHY_COMP_EQ_SKIPN:
1923                         if (predata == data)
1924                                 index += regno;
1925                         index++;
1926                         break;
1927                 case PHY_COMP_NEQ_SKIPN:
1928                         if (predata != data)
1929                                 index += regno;
1930                         index++;
1931                         break;
1932                 case PHY_WRITE_PREVIOUS:
1933                         rtl_writephy(tp, regno, predata);
1934                         index++;
1935                         break;
1936                 case PHY_SKIPN:
1937                         index += regno + 1;
1938                         break;
1939                 case PHY_DELAY_MS:
1940                         mdelay(data);
1941                         index++;
1942                         break;
1943
1944                 case PHY_READ_MAC_BYTE:
1945                 case PHY_WRITE_MAC_BYTE:
1946                 case PHY_WRITE_ERI_WORD:
1947                 default:
1948                         BUG();
1949                 }
1950         }
1951 }
1952
1953 static void rtl_release_firmware(struct rtl8169_private *tp)
1954 {
1955         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
1956                 release_firmware(tp->rtl_fw->fw);
1957                 kfree(tp->rtl_fw);
1958         }
1959         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
1960 }
1961
1962 static void rtl_apply_firmware(struct rtl8169_private *tp)
1963 {
1964         struct rtl_fw *rtl_fw = tp->rtl_fw;
1965
1966         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1967         if (!IS_ERR_OR_NULL(rtl_fw))
1968                 rtl_phy_write_fw(tp, rtl_fw);
1969 }
1970
1971 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1972 {
1973         if (rtl_readphy(tp, reg) != val)
1974                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1975         else
1976                 rtl_apply_firmware(tp);
1977 }
1978
1979 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1980 {
1981         static const struct phy_reg phy_reg_init[] = {
1982                 { 0x1f, 0x0001 },
1983                 { 0x06, 0x006e },
1984                 { 0x08, 0x0708 },
1985                 { 0x15, 0x4000 },
1986                 { 0x18, 0x65c7 },
1987
1988                 { 0x1f, 0x0001 },
1989                 { 0x03, 0x00a1 },
1990                 { 0x02, 0x0008 },
1991                 { 0x01, 0x0120 },
1992                 { 0x00, 0x1000 },
1993                 { 0x04, 0x0800 },
1994                 { 0x04, 0x0000 },
1995
1996                 { 0x03, 0xff41 },
1997                 { 0x02, 0xdf60 },
1998                 { 0x01, 0x0140 },
1999                 { 0x00, 0x0077 },
2000                 { 0x04, 0x7800 },
2001                 { 0x04, 0x7000 },
2002
2003                 { 0x03, 0x802f },
2004                 { 0x02, 0x4f02 },
2005                 { 0x01, 0x0409 },
2006                 { 0x00, 0xf0f9 },
2007                 { 0x04, 0x9800 },
2008                 { 0x04, 0x9000 },
2009
2010                 { 0x03, 0xdf01 },
2011                 { 0x02, 0xdf20 },
2012                 { 0x01, 0xff95 },
2013                 { 0x00, 0xba00 },
2014                 { 0x04, 0xa800 },
2015                 { 0x04, 0xa000 },
2016
2017                 { 0x03, 0xff41 },
2018                 { 0x02, 0xdf20 },
2019                 { 0x01, 0x0140 },
2020                 { 0x00, 0x00bb },
2021                 { 0x04, 0xb800 },
2022                 { 0x04, 0xb000 },
2023
2024                 { 0x03, 0xdf41 },
2025                 { 0x02, 0xdc60 },
2026                 { 0x01, 0x6340 },
2027                 { 0x00, 0x007d },
2028                 { 0x04, 0xd800 },
2029                 { 0x04, 0xd000 },
2030
2031                 { 0x03, 0xdf01 },
2032                 { 0x02, 0xdf20 },
2033                 { 0x01, 0x100a },
2034                 { 0x00, 0xa0ff },
2035                 { 0x04, 0xf800 },
2036                 { 0x04, 0xf000 },
2037
2038                 { 0x1f, 0x0000 },
2039                 { 0x0b, 0x0000 },
2040                 { 0x00, 0x9200 }
2041         };
2042
2043         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2044 }
2045
2046 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2047 {
2048         static const struct phy_reg phy_reg_init[] = {
2049                 { 0x1f, 0x0002 },
2050                 { 0x01, 0x90d0 },
2051                 { 0x1f, 0x0000 }
2052         };
2053
2054         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2055 }
2056
2057 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2058 {
2059         struct pci_dev *pdev = tp->pci_dev;
2060         u16 vendor_id, device_id;
2061
2062         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
2063         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
2064
2065         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
2066                 return;
2067
2068         rtl_writephy(tp, 0x1f, 0x0001);
2069         rtl_writephy(tp, 0x10, 0xf01b);
2070         rtl_writephy(tp, 0x1f, 0x0000);
2071 }
2072
2073 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2074 {
2075         static const struct phy_reg phy_reg_init[] = {
2076                 { 0x1f, 0x0001 },
2077                 { 0x04, 0x0000 },
2078                 { 0x03, 0x00a1 },
2079                 { 0x02, 0x0008 },
2080                 { 0x01, 0x0120 },
2081                 { 0x00, 0x1000 },
2082                 { 0x04, 0x0800 },
2083                 { 0x04, 0x9000 },
2084                 { 0x03, 0x802f },
2085                 { 0x02, 0x4f02 },
2086                 { 0x01, 0x0409 },
2087                 { 0x00, 0xf099 },
2088                 { 0x04, 0x9800 },
2089                 { 0x04, 0xa000 },
2090                 { 0x03, 0xdf01 },
2091                 { 0x02, 0xdf20 },
2092                 { 0x01, 0xff95 },
2093                 { 0x00, 0xba00 },
2094                 { 0x04, 0xa800 },
2095                 { 0x04, 0xf000 },
2096                 { 0x03, 0xdf01 },
2097                 { 0x02, 0xdf20 },
2098                 { 0x01, 0x101a },
2099                 { 0x00, 0xa0ff },
2100                 { 0x04, 0xf800 },
2101                 { 0x04, 0x0000 },
2102                 { 0x1f, 0x0000 },
2103
2104                 { 0x1f, 0x0001 },
2105                 { 0x10, 0xf41b },
2106                 { 0x14, 0xfb54 },
2107                 { 0x18, 0xf5c7 },
2108                 { 0x1f, 0x0000 },
2109
2110                 { 0x1f, 0x0001 },
2111                 { 0x17, 0x0cc0 },
2112                 { 0x1f, 0x0000 }
2113         };
2114
2115         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2116
2117         rtl8169scd_hw_phy_config_quirk(tp);
2118 }
2119
2120 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2121 {
2122         static const struct phy_reg phy_reg_init[] = {
2123                 { 0x1f, 0x0001 },
2124                 { 0x04, 0x0000 },
2125                 { 0x03, 0x00a1 },
2126                 { 0x02, 0x0008 },
2127                 { 0x01, 0x0120 },
2128                 { 0x00, 0x1000 },
2129                 { 0x04, 0x0800 },
2130                 { 0x04, 0x9000 },
2131                 { 0x03, 0x802f },
2132                 { 0x02, 0x4f02 },
2133                 { 0x01, 0x0409 },
2134                 { 0x00, 0xf099 },
2135                 { 0x04, 0x9800 },
2136                 { 0x04, 0xa000 },
2137                 { 0x03, 0xdf01 },
2138                 { 0x02, 0xdf20 },
2139                 { 0x01, 0xff95 },
2140                 { 0x00, 0xba00 },
2141                 { 0x04, 0xa800 },
2142                 { 0x04, 0xf000 },
2143                 { 0x03, 0xdf01 },
2144                 { 0x02, 0xdf20 },
2145                 { 0x01, 0x101a },
2146                 { 0x00, 0xa0ff },
2147                 { 0x04, 0xf800 },
2148                 { 0x04, 0x0000 },
2149                 { 0x1f, 0x0000 },
2150
2151                 { 0x1f, 0x0001 },
2152                 { 0x0b, 0x8480 },
2153                 { 0x1f, 0x0000 },
2154
2155                 { 0x1f, 0x0001 },
2156                 { 0x18, 0x67c7 },
2157                 { 0x04, 0x2000 },
2158                 { 0x03, 0x002f },
2159                 { 0x02, 0x4360 },
2160                 { 0x01, 0x0109 },
2161                 { 0x00, 0x3022 },
2162                 { 0x04, 0x2800 },
2163                 { 0x1f, 0x0000 },
2164
2165                 { 0x1f, 0x0001 },
2166                 { 0x17, 0x0cc0 },
2167                 { 0x1f, 0x0000 }
2168         };
2169
2170         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2171 }
2172
2173 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2174 {
2175         static const struct phy_reg phy_reg_init[] = {
2176                 { 0x10, 0xf41b },
2177                 { 0x1f, 0x0000 }
2178         };
2179
2180         rtl_writephy(tp, 0x1f, 0x0001);
2181         rtl_patchphy(tp, 0x16, 1 << 0);
2182
2183         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2184 }
2185
2186 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2187 {
2188         static const struct phy_reg phy_reg_init[] = {
2189                 { 0x1f, 0x0001 },
2190                 { 0x10, 0xf41b },
2191                 { 0x1f, 0x0000 }
2192         };
2193
2194         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2195 }
2196
2197 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2198 {
2199         static const struct phy_reg phy_reg_init[] = {
2200                 { 0x1f, 0x0000 },
2201                 { 0x1d, 0x0f00 },
2202                 { 0x1f, 0x0002 },
2203                 { 0x0c, 0x1ec8 },
2204                 { 0x1f, 0x0000 }
2205         };
2206
2207         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2208 }
2209
2210 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2211 {
2212         static const struct phy_reg phy_reg_init[] = {
2213                 { 0x1f, 0x0001 },
2214                 { 0x1d, 0x3d98 },
2215                 { 0x1f, 0x0000 }
2216         };
2217
2218         rtl_writephy(tp, 0x1f, 0x0000);
2219         rtl_patchphy(tp, 0x14, 1 << 5);
2220         rtl_patchphy(tp, 0x0d, 1 << 5);
2221
2222         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2223 }
2224
2225 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2226 {
2227         static const struct phy_reg phy_reg_init[] = {
2228                 { 0x1f, 0x0001 },
2229                 { 0x12, 0x2300 },
2230                 { 0x1f, 0x0002 },
2231                 { 0x00, 0x88d4 },
2232                 { 0x01, 0x82b1 },
2233                 { 0x03, 0x7002 },
2234                 { 0x08, 0x9e30 },
2235                 { 0x09, 0x01f0 },
2236                 { 0x0a, 0x5500 },
2237                 { 0x0c, 0x00c8 },
2238                 { 0x1f, 0x0003 },
2239                 { 0x12, 0xc096 },
2240                 { 0x16, 0x000a },
2241                 { 0x1f, 0x0000 },
2242                 { 0x1f, 0x0000 },
2243                 { 0x09, 0x2000 },
2244                 { 0x09, 0x0000 }
2245         };
2246
2247         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2248
2249         rtl_patchphy(tp, 0x14, 1 << 5);
2250         rtl_patchphy(tp, 0x0d, 1 << 5);
2251         rtl_writephy(tp, 0x1f, 0x0000);
2252 }
2253
2254 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2255 {
2256         static const struct phy_reg phy_reg_init[] = {
2257                 { 0x1f, 0x0001 },
2258                 { 0x12, 0x2300 },
2259                 { 0x03, 0x802f },
2260                 { 0x02, 0x4f02 },
2261                 { 0x01, 0x0409 },
2262                 { 0x00, 0xf099 },
2263                 { 0x04, 0x9800 },
2264                 { 0x04, 0x9000 },
2265                 { 0x1d, 0x3d98 },
2266                 { 0x1f, 0x0002 },
2267                 { 0x0c, 0x7eb8 },
2268                 { 0x06, 0x0761 },
2269                 { 0x1f, 0x0003 },
2270                 { 0x16, 0x0f0a },
2271                 { 0x1f, 0x0000 }
2272         };
2273
2274         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2275
2276         rtl_patchphy(tp, 0x16, 1 << 0);
2277         rtl_patchphy(tp, 0x14, 1 << 5);
2278         rtl_patchphy(tp, 0x0d, 1 << 5);
2279         rtl_writephy(tp, 0x1f, 0x0000);
2280 }
2281
2282 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2283 {
2284         static const struct phy_reg phy_reg_init[] = {
2285                 { 0x1f, 0x0001 },
2286                 { 0x12, 0x2300 },
2287                 { 0x1d, 0x3d98 },
2288                 { 0x1f, 0x0002 },
2289                 { 0x0c, 0x7eb8 },
2290                 { 0x06, 0x5461 },
2291                 { 0x1f, 0x0003 },
2292                 { 0x16, 0x0f0a },
2293                 { 0x1f, 0x0000 }
2294         };
2295
2296         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2297
2298         rtl_patchphy(tp, 0x16, 1 << 0);
2299         rtl_patchphy(tp, 0x14, 1 << 5);
2300         rtl_patchphy(tp, 0x0d, 1 << 5);
2301         rtl_writephy(tp, 0x1f, 0x0000);
2302 }
2303
2304 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2305 {
2306         rtl8168c_3_hw_phy_config(tp);
2307 }
2308
2309 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2310 {
2311         static const struct phy_reg phy_reg_init_0[] = {
2312                 /* Channel Estimation */
2313                 { 0x1f, 0x0001 },
2314                 { 0x06, 0x4064 },
2315                 { 0x07, 0x2863 },
2316                 { 0x08, 0x059c },
2317                 { 0x09, 0x26b4 },
2318                 { 0x0a, 0x6a19 },
2319                 { 0x0b, 0xdcc8 },
2320                 { 0x10, 0xf06d },
2321                 { 0x14, 0x7f68 },
2322                 { 0x18, 0x7fd9 },
2323                 { 0x1c, 0xf0ff },
2324                 { 0x1d, 0x3d9c },
2325                 { 0x1f, 0x0003 },
2326                 { 0x12, 0xf49f },
2327                 { 0x13, 0x070b },
2328                 { 0x1a, 0x05ad },
2329                 { 0x14, 0x94c0 },
2330
2331                 /*
2332                  * Tx Error Issue
2333                  * Enhance line driver power
2334                  */
2335                 { 0x1f, 0x0002 },
2336                 { 0x06, 0x5561 },
2337                 { 0x1f, 0x0005 },
2338                 { 0x05, 0x8332 },
2339                 { 0x06, 0x5561 },
2340
2341                 /*
2342                  * Can not link to 1Gbps with bad cable
2343                  * Decrease SNR threshold form 21.07dB to 19.04dB
2344                  */
2345                 { 0x1f, 0x0001 },
2346                 { 0x17, 0x0cc0 },
2347
2348                 { 0x1f, 0x0000 },
2349                 { 0x0d, 0xf880 }
2350         };
2351         void __iomem *ioaddr = tp->mmio_addr;
2352
2353         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2354
2355         /*
2356          * Rx Error Issue
2357          * Fine Tune Switching regulator parameter
2358          */
2359         rtl_writephy(tp, 0x1f, 0x0002);
2360         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2361         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2362
2363         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2364                 static const struct phy_reg phy_reg_init[] = {
2365                         { 0x1f, 0x0002 },
2366                         { 0x05, 0x669a },
2367                         { 0x1f, 0x0005 },
2368                         { 0x05, 0x8330 },
2369                         { 0x06, 0x669a },
2370                         { 0x1f, 0x0002 }
2371                 };
2372                 int val;
2373
2374                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2375
2376                 val = rtl_readphy(tp, 0x0d);
2377
2378                 if ((val & 0x00ff) != 0x006c) {
2379                         static const u32 set[] = {
2380                                 0x0065, 0x0066, 0x0067, 0x0068,
2381                                 0x0069, 0x006a, 0x006b, 0x006c
2382                         };
2383                         int i;
2384
2385                         rtl_writephy(tp, 0x1f, 0x0002);
2386
2387                         val &= 0xff00;
2388                         for (i = 0; i < ARRAY_SIZE(set); i++)
2389                                 rtl_writephy(tp, 0x0d, val | set[i]);
2390                 }
2391         } else {
2392                 static const struct phy_reg phy_reg_init[] = {
2393                         { 0x1f, 0x0002 },
2394                         { 0x05, 0x6662 },
2395                         { 0x1f, 0x0005 },
2396                         { 0x05, 0x8330 },
2397                         { 0x06, 0x6662 }
2398                 };
2399
2400                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2401         }
2402
2403         /* RSET couple improve */
2404         rtl_writephy(tp, 0x1f, 0x0002);
2405         rtl_patchphy(tp, 0x0d, 0x0300);
2406         rtl_patchphy(tp, 0x0f, 0x0010);
2407
2408         /* Fine tune PLL performance */
2409         rtl_writephy(tp, 0x1f, 0x0002);
2410         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2411         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2412
2413         rtl_writephy(tp, 0x1f, 0x0005);
2414         rtl_writephy(tp, 0x05, 0x001b);
2415
2416         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2417
2418         rtl_writephy(tp, 0x1f, 0x0000);
2419 }
2420
2421 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2422 {
2423         static const struct phy_reg phy_reg_init_0[] = {
2424                 /* Channel Estimation */
2425                 { 0x1f, 0x0001 },
2426                 { 0x06, 0x4064 },
2427                 { 0x07, 0x2863 },
2428                 { 0x08, 0x059c },
2429                 { 0x09, 0x26b4 },
2430                 { 0x0a, 0x6a19 },
2431                 { 0x0b, 0xdcc8 },
2432                 { 0x10, 0xf06d },
2433                 { 0x14, 0x7f68 },
2434                 { 0x18, 0x7fd9 },
2435                 { 0x1c, 0xf0ff },
2436                 { 0x1d, 0x3d9c },
2437                 { 0x1f, 0x0003 },
2438                 { 0x12, 0xf49f },
2439                 { 0x13, 0x070b },
2440                 { 0x1a, 0x05ad },
2441                 { 0x14, 0x94c0 },
2442
2443                 /*
2444                  * Tx Error Issue
2445                  * Enhance line driver power
2446                  */
2447                 { 0x1f, 0x0002 },
2448                 { 0x06, 0x5561 },
2449                 { 0x1f, 0x0005 },
2450                 { 0x05, 0x8332 },
2451                 { 0x06, 0x5561 },
2452
2453                 /*
2454                  * Can not link to 1Gbps with bad cable
2455                  * Decrease SNR threshold form 21.07dB to 19.04dB
2456                  */
2457                 { 0x1f, 0x0001 },
2458                 { 0x17, 0x0cc0 },
2459
2460                 { 0x1f, 0x0000 },
2461                 { 0x0d, 0xf880 }
2462         };
2463         void __iomem *ioaddr = tp->mmio_addr;
2464
2465         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2466
2467         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2468                 static const struct phy_reg phy_reg_init[] = {
2469                         { 0x1f, 0x0002 },
2470                         { 0x05, 0x669a },
2471                         { 0x1f, 0x0005 },
2472                         { 0x05, 0x8330 },
2473                         { 0x06, 0x669a },
2474
2475                         { 0x1f, 0x0002 }
2476                 };
2477                 int val;
2478
2479                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2480
2481                 val = rtl_readphy(tp, 0x0d);
2482                 if ((val & 0x00ff) != 0x006c) {
2483                         static const u32 set[] = {
2484                                 0x0065, 0x0066, 0x0067, 0x0068,
2485                                 0x0069, 0x006a, 0x006b, 0x006c
2486                         };
2487                         int i;
2488
2489                         rtl_writephy(tp, 0x1f, 0x0002);
2490
2491                         val &= 0xff00;
2492                         for (i = 0; i < ARRAY_SIZE(set); i++)
2493                                 rtl_writephy(tp, 0x0d, val | set[i]);
2494                 }
2495         } else {
2496                 static const struct phy_reg phy_reg_init[] = {
2497                         { 0x1f, 0x0002 },
2498                         { 0x05, 0x2642 },
2499                         { 0x1f, 0x0005 },
2500                         { 0x05, 0x8330 },
2501                         { 0x06, 0x2642 }
2502                 };
2503
2504                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2505         }
2506
2507         /* Fine tune PLL performance */
2508         rtl_writephy(tp, 0x1f, 0x0002);
2509         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2510         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2511
2512         /* Switching regulator Slew rate */
2513         rtl_writephy(tp, 0x1f, 0x0002);
2514         rtl_patchphy(tp, 0x0f, 0x0017);
2515
2516         rtl_writephy(tp, 0x1f, 0x0005);
2517         rtl_writephy(tp, 0x05, 0x001b);
2518
2519         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2520
2521         rtl_writephy(tp, 0x1f, 0x0000);
2522 }
2523
2524 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2525 {
2526         static const struct phy_reg phy_reg_init[] = {
2527                 { 0x1f, 0x0002 },
2528                 { 0x10, 0x0008 },
2529                 { 0x0d, 0x006c },
2530
2531                 { 0x1f, 0x0000 },
2532                 { 0x0d, 0xf880 },
2533
2534                 { 0x1f, 0x0001 },
2535                 { 0x17, 0x0cc0 },
2536
2537                 { 0x1f, 0x0001 },
2538                 { 0x0b, 0xa4d8 },
2539                 { 0x09, 0x281c },
2540                 { 0x07, 0x2883 },
2541                 { 0x0a, 0x6b35 },
2542                 { 0x1d, 0x3da4 },
2543                 { 0x1c, 0xeffd },
2544                 { 0x14, 0x7f52 },
2545                 { 0x18, 0x7fc6 },
2546                 { 0x08, 0x0601 },
2547                 { 0x06, 0x4063 },
2548                 { 0x10, 0xf074 },
2549                 { 0x1f, 0x0003 },
2550                 { 0x13, 0x0789 },
2551                 { 0x12, 0xf4bd },
2552                 { 0x1a, 0x04fd },
2553                 { 0x14, 0x84b0 },
2554                 { 0x1f, 0x0000 },
2555                 { 0x00, 0x9200 },
2556
2557                 { 0x1f, 0x0005 },
2558                 { 0x01, 0x0340 },
2559                 { 0x1f, 0x0001 },
2560                 { 0x04, 0x4000 },
2561                 { 0x03, 0x1d21 },
2562                 { 0x02, 0x0c32 },
2563                 { 0x01, 0x0200 },
2564                 { 0x00, 0x5554 },
2565                 { 0x04, 0x4800 },
2566                 { 0x04, 0x4000 },
2567                 { 0x04, 0xf000 },
2568                 { 0x03, 0xdf01 },
2569                 { 0x02, 0xdf20 },
2570                 { 0x01, 0x101a },
2571                 { 0x00, 0xa0ff },
2572                 { 0x04, 0xf800 },
2573                 { 0x04, 0xf000 },
2574                 { 0x1f, 0x0000 },
2575
2576                 { 0x1f, 0x0007 },
2577                 { 0x1e, 0x0023 },
2578                 { 0x16, 0x0000 },
2579                 { 0x1f, 0x0000 }
2580         };
2581
2582         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2583 }
2584
2585 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2586 {
2587         static const struct phy_reg phy_reg_init[] = {
2588                 { 0x1f, 0x0001 },
2589                 { 0x17, 0x0cc0 },
2590
2591                 { 0x1f, 0x0007 },
2592                 { 0x1e, 0x002d },
2593                 { 0x18, 0x0040 },
2594                 { 0x1f, 0x0000 }
2595         };
2596
2597         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2598         rtl_patchphy(tp, 0x0d, 1 << 5);
2599 }
2600
2601 static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2602 {
2603         static const struct phy_reg phy_reg_init[] = {
2604                 /* Enable Delay cap */
2605                 { 0x1f, 0x0005 },
2606                 { 0x05, 0x8b80 },
2607                 { 0x06, 0xc896 },
2608                 { 0x1f, 0x0000 },
2609
2610                 /* Channel estimation fine tune */
2611                 { 0x1f, 0x0001 },
2612                 { 0x0b, 0x6c20 },
2613                 { 0x07, 0x2872 },
2614                 { 0x1c, 0xefff },
2615                 { 0x1f, 0x0003 },
2616                 { 0x14, 0x6420 },
2617                 { 0x1f, 0x0000 },
2618
2619                 /* Update PFM & 10M TX idle timer */
2620                 { 0x1f, 0x0007 },
2621                 { 0x1e, 0x002f },
2622                 { 0x15, 0x1919 },
2623                 { 0x1f, 0x0000 },
2624
2625                 { 0x1f, 0x0007 },
2626                 { 0x1e, 0x00ac },
2627                 { 0x18, 0x0006 },
2628                 { 0x1f, 0x0000 }
2629         };
2630
2631         rtl_apply_firmware(tp);
2632
2633         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2634
2635         /* DCO enable for 10M IDLE Power */
2636         rtl_writephy(tp, 0x1f, 0x0007);
2637         rtl_writephy(tp, 0x1e, 0x0023);
2638         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2639         rtl_writephy(tp, 0x1f, 0x0000);
2640
2641         /* For impedance matching */
2642         rtl_writephy(tp, 0x1f, 0x0002);
2643         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2644         rtl_writephy(tp, 0x1f, 0x0000);
2645
2646         /* PHY auto speed down */
2647         rtl_writephy(tp, 0x1f, 0x0007);
2648         rtl_writephy(tp, 0x1e, 0x002d);
2649         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2650         rtl_writephy(tp, 0x1f, 0x0000);
2651         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2652
2653         rtl_writephy(tp, 0x1f, 0x0005);
2654         rtl_writephy(tp, 0x05, 0x8b86);
2655         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2656         rtl_writephy(tp, 0x1f, 0x0000);
2657
2658         rtl_writephy(tp, 0x1f, 0x0005);
2659         rtl_writephy(tp, 0x05, 0x8b85);
2660         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2661         rtl_writephy(tp, 0x1f, 0x0007);
2662         rtl_writephy(tp, 0x1e, 0x0020);
2663         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2664         rtl_writephy(tp, 0x1f, 0x0006);
2665         rtl_writephy(tp, 0x00, 0x5a00);
2666         rtl_writephy(tp, 0x1f, 0x0000);
2667         rtl_writephy(tp, 0x0d, 0x0007);
2668         rtl_writephy(tp, 0x0e, 0x003c);
2669         rtl_writephy(tp, 0x0d, 0x4007);
2670         rtl_writephy(tp, 0x0e, 0x0000);
2671         rtl_writephy(tp, 0x0d, 0x0000);
2672 }
2673
2674 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2675 {
2676         static const struct phy_reg phy_reg_init[] = {
2677                 { 0x1f, 0x0003 },
2678                 { 0x08, 0x441d },
2679                 { 0x01, 0x9100 },
2680                 { 0x1f, 0x0000 }
2681         };
2682
2683         rtl_writephy(tp, 0x1f, 0x0000);
2684         rtl_patchphy(tp, 0x11, 1 << 12);
2685         rtl_patchphy(tp, 0x19, 1 << 13);
2686         rtl_patchphy(tp, 0x10, 1 << 15);
2687
2688         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2689 }
2690
2691 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2692 {
2693         static const struct phy_reg phy_reg_init[] = {
2694                 { 0x1f, 0x0005 },
2695                 { 0x1a, 0x0000 },
2696                 { 0x1f, 0x0000 },
2697
2698                 { 0x1f, 0x0004 },
2699                 { 0x1c, 0x0000 },
2700                 { 0x1f, 0x0000 },
2701
2702                 { 0x1f, 0x0001 },
2703                 { 0x15, 0x7701 },
2704                 { 0x1f, 0x0000 }
2705         };
2706
2707         /* Disable ALDPS before ram code */
2708         rtl_writephy(tp, 0x1f, 0x0000);
2709         rtl_writephy(tp, 0x18, 0x0310);
2710         msleep(100);
2711
2712         rtl_apply_firmware(tp);
2713
2714         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2715 }
2716
2717 static void rtl_hw_phy_config(struct net_device *dev)
2718 {
2719         struct rtl8169_private *tp = netdev_priv(dev);
2720
2721         rtl8169_print_mac_version(tp);
2722
2723         switch (tp->mac_version) {
2724         case RTL_GIGA_MAC_VER_01:
2725                 break;
2726         case RTL_GIGA_MAC_VER_02:
2727         case RTL_GIGA_MAC_VER_03:
2728                 rtl8169s_hw_phy_config(tp);
2729                 break;
2730         case RTL_GIGA_MAC_VER_04:
2731                 rtl8169sb_hw_phy_config(tp);
2732                 break;
2733         case RTL_GIGA_MAC_VER_05:
2734                 rtl8169scd_hw_phy_config(tp);
2735                 break;
2736         case RTL_GIGA_MAC_VER_06:
2737                 rtl8169sce_hw_phy_config(tp);
2738                 break;
2739         case RTL_GIGA_MAC_VER_07:
2740         case RTL_GIGA_MAC_VER_08:
2741         case RTL_GIGA_MAC_VER_09:
2742                 rtl8102e_hw_phy_config(tp);
2743                 break;
2744         case RTL_GIGA_MAC_VER_11:
2745                 rtl8168bb_hw_phy_config(tp);
2746                 break;
2747         case RTL_GIGA_MAC_VER_12:
2748                 rtl8168bef_hw_phy_config(tp);
2749                 break;
2750         case RTL_GIGA_MAC_VER_17:
2751                 rtl8168bef_hw_phy_config(tp);
2752                 break;
2753         case RTL_GIGA_MAC_VER_18:
2754                 rtl8168cp_1_hw_phy_config(tp);
2755                 break;
2756         case RTL_GIGA_MAC_VER_19:
2757                 rtl8168c_1_hw_phy_config(tp);
2758                 break;
2759         case RTL_GIGA_MAC_VER_20:
2760                 rtl8168c_2_hw_phy_config(tp);
2761                 break;
2762         case RTL_GIGA_MAC_VER_21:
2763                 rtl8168c_3_hw_phy_config(tp);
2764                 break;
2765         case RTL_GIGA_MAC_VER_22:
2766                 rtl8168c_4_hw_phy_config(tp);
2767                 break;
2768         case RTL_GIGA_MAC_VER_23:
2769         case RTL_GIGA_MAC_VER_24:
2770                 rtl8168cp_2_hw_phy_config(tp);
2771                 break;
2772         case RTL_GIGA_MAC_VER_25:
2773                 rtl8168d_1_hw_phy_config(tp);
2774                 break;
2775         case RTL_GIGA_MAC_VER_26:
2776                 rtl8168d_2_hw_phy_config(tp);
2777                 break;
2778         case RTL_GIGA_MAC_VER_27:
2779                 rtl8168d_3_hw_phy_config(tp);
2780                 break;
2781         case RTL_GIGA_MAC_VER_28:
2782                 rtl8168d_4_hw_phy_config(tp);
2783                 break;
2784         case RTL_GIGA_MAC_VER_29:
2785         case RTL_GIGA_MAC_VER_30:
2786                 rtl8105e_hw_phy_config(tp);
2787                 break;
2788         case RTL_GIGA_MAC_VER_31:
2789                 /* None. */
2790                 break;
2791         case RTL_GIGA_MAC_VER_32:
2792         case RTL_GIGA_MAC_VER_33:
2793                 rtl8168e_hw_phy_config(tp);
2794                 break;
2795
2796         default:
2797                 break;
2798         }
2799 }
2800
2801 static void rtl8169_phy_timer(unsigned long __opaque)
2802 {
2803         struct net_device *dev = (struct net_device *)__opaque;
2804         struct rtl8169_private *tp = netdev_priv(dev);
2805         struct timer_list *timer = &tp->timer;
2806         void __iomem *ioaddr = tp->mmio_addr;
2807         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2808
2809         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2810
2811         spin_lock_irq(&tp->lock);
2812
2813         if (tp->phy_reset_pending(tp)) {
2814                 /*
2815                  * A busy loop could burn quite a few cycles on nowadays CPU.
2816                  * Let's delay the execution of the timer for a few ticks.
2817                  */
2818                 timeout = HZ/10;
2819                 goto out_mod_timer;
2820         }
2821
2822         if (tp->link_ok(ioaddr))
2823                 goto out_unlock;
2824
2825         netif_warn(tp, link, dev, "PHY reset until link up\n");
2826
2827         tp->phy_reset_enable(tp);
2828
2829 out_mod_timer:
2830         mod_timer(timer, jiffies + timeout);
2831 out_unlock:
2832         spin_unlock_irq(&tp->lock);
2833 }
2834
2835 #ifdef CONFIG_NET_POLL_CONTROLLER
2836 /*
2837  * Polling 'interrupt' - used by things like netconsole to send skbs
2838  * without having to re-enable interrupts. It's not called while
2839  * the interrupt routine is executing.
2840  */
2841 static void rtl8169_netpoll(struct net_device *dev)
2842 {
2843         struct rtl8169_private *tp = netdev_priv(dev);
2844         struct pci_dev *pdev = tp->pci_dev;
2845
2846         disable_irq(pdev->irq);
2847         rtl8169_interrupt(pdev->irq, dev);
2848         enable_irq(pdev->irq);
2849 }
2850 #endif
2851
2852 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2853                                   void __iomem *ioaddr)
2854 {
2855         iounmap(ioaddr);
2856         pci_release_regions(pdev);
2857         pci_clear_mwi(pdev);
2858         pci_disable_device(pdev);
2859         free_netdev(dev);
2860 }
2861
2862 static void rtl8169_phy_reset(struct net_device *dev,
2863                               struct rtl8169_private *tp)
2864 {
2865         unsigned int i;
2866
2867         tp->phy_reset_enable(tp);
2868         for (i = 0; i < 100; i++) {
2869                 if (!tp->phy_reset_pending(tp))
2870                         return;
2871                 msleep(1);
2872         }
2873         netif_err(tp, link, dev, "PHY reset failed\n");
2874 }
2875
2876 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2877 {
2878         void __iomem *ioaddr = tp->mmio_addr;
2879
2880         rtl_hw_phy_config(dev);
2881
2882         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2883                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2884                 RTL_W8(0x82, 0x01);
2885         }
2886
2887         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2888
2889         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2890                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2891
2892         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2893                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2894                 RTL_W8(0x82, 0x01);
2895                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2896                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2897         }
2898
2899         rtl8169_phy_reset(dev, tp);
2900
2901         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2902                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2903                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2904                           (tp->mii.supports_gmii ?
2905                            ADVERTISED_1000baseT_Half |
2906                            ADVERTISED_1000baseT_Full : 0));
2907
2908         if (RTL_R8(PHYstatus) & TBI_Enable)
2909                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2910 }
2911
2912 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2913 {
2914         void __iomem *ioaddr = tp->mmio_addr;
2915         u32 high;
2916         u32 low;
2917
2918         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2919         high = addr[4] | (addr[5] << 8);
2920
2921         spin_lock_irq(&tp->lock);
2922
2923         RTL_W8(Cfg9346, Cfg9346_Unlock);
2924
2925         RTL_W32(MAC4, high);
2926         RTL_R32(MAC4);
2927
2928         RTL_W32(MAC0, low);
2929         RTL_R32(MAC0);
2930
2931         RTL_W8(Cfg9346, Cfg9346_Lock);
2932
2933         spin_unlock_irq(&tp->lock);
2934 }
2935
2936 static int rtl_set_mac_address(struct net_device *dev, void *p)
2937 {
2938         struct rtl8169_private *tp = netdev_priv(dev);
2939         struct sockaddr *addr = p;
2940
2941         if (!is_valid_ether_addr(addr->sa_data))
2942                 return -EADDRNOTAVAIL;
2943
2944         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2945
2946         rtl_rar_set(tp, dev->dev_addr);
2947
2948         return 0;
2949 }
2950
2951 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2952 {
2953         struct rtl8169_private *tp = netdev_priv(dev);
2954         struct mii_ioctl_data *data = if_mii(ifr);
2955
2956         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2957 }
2958
2959 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2960                           struct mii_ioctl_data *data, int cmd)
2961 {
2962         switch (cmd) {
2963         case SIOCGMIIPHY:
2964                 data->phy_id = 32; /* Internal PHY */
2965                 return 0;
2966
2967         case SIOCGMIIREG:
2968                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2969                 return 0;
2970
2971         case SIOCSMIIREG:
2972                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2973                 return 0;
2974         }
2975         return -EOPNOTSUPP;
2976 }
2977
2978 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2979 {
2980         return -EOPNOTSUPP;
2981 }
2982
2983 static const struct rtl_cfg_info {
2984         void (*hw_start)(struct net_device *);
2985         unsigned int region;
2986         unsigned int align;
2987         u16 intr_event;
2988         u16 napi_event;
2989         unsigned features;
2990         u8 default_ver;
2991 } rtl_cfg_infos [] = {
2992         [RTL_CFG_0] = {
2993                 .hw_start       = rtl_hw_start_8169,
2994                 .region         = 1,
2995                 .align          = 0,
2996                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2997                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2998                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2999                 .features       = RTL_FEATURE_GMII,
3000                 .default_ver    = RTL_GIGA_MAC_VER_01,
3001         },
3002         [RTL_CFG_1] = {
3003                 .hw_start       = rtl_hw_start_8168,
3004                 .region         = 2,
3005                 .align          = 8,
3006                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3007                                   TxErr | TxOK | RxOK | RxErr,
3008                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
3009                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3010                 .default_ver    = RTL_GIGA_MAC_VER_11,
3011         },
3012         [RTL_CFG_2] = {
3013                 .hw_start       = rtl_hw_start_8101,
3014                 .region         = 2,
3015                 .align          = 8,
3016                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3017                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3018                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3019                 .features       = RTL_FEATURE_MSI,
3020                 .default_ver    = RTL_GIGA_MAC_VER_13,
3021         }
3022 };
3023
3024 /* Cfg9346_Unlock assumed. */
3025 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
3026                             const struct rtl_cfg_info *cfg)
3027 {
3028         unsigned msi = 0;
3029         u8 cfg2;
3030
3031         cfg2 = RTL_R8(Config2) & ~MSIEnable;
3032         if (cfg->features & RTL_FEATURE_MSI) {
3033                 if (pci_enable_msi(pdev)) {
3034                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3035                 } else {
3036                         cfg2 |= MSIEnable;
3037                         msi = RTL_FEATURE_MSI;
3038                 }
3039         }
3040         RTL_W8(Config2, cfg2);
3041         return msi;
3042 }
3043
3044 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3045 {
3046         if (tp->features & RTL_FEATURE_MSI) {
3047                 pci_disable_msi(pdev);
3048                 tp->features &= ~RTL_FEATURE_MSI;
3049         }
3050 }
3051
3052 static const struct net_device_ops rtl8169_netdev_ops = {
3053         .ndo_open               = rtl8169_open,
3054         .ndo_stop               = rtl8169_close,
3055         .ndo_get_stats          = rtl8169_get_stats,
3056         .ndo_start_xmit         = rtl8169_start_xmit,
3057         .ndo_tx_timeout         = rtl8169_tx_timeout,
3058         .ndo_validate_addr      = eth_validate_addr,
3059         .ndo_change_mtu         = rtl8169_change_mtu,
3060         .ndo_fix_features       = rtl8169_fix_features,
3061         .ndo_set_features       = rtl8169_set_features,
3062         .ndo_set_mac_address    = rtl_set_mac_address,
3063         .ndo_do_ioctl           = rtl8169_ioctl,
3064         .ndo_set_multicast_list = rtl_set_rx_mode,
3065 #ifdef CONFIG_NET_POLL_CONTROLLER
3066         .ndo_poll_controller    = rtl8169_netpoll,
3067 #endif
3068
3069 };
3070
3071 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3072 {
3073         struct mdio_ops *ops = &tp->mdio_ops;
3074
3075         switch (tp->mac_version) {
3076         case RTL_GIGA_MAC_VER_27:
3077                 ops->write      = r8168dp_1_mdio_write;
3078                 ops->read       = r8168dp_1_mdio_read;
3079                 break;
3080         case RTL_GIGA_MAC_VER_28:
3081         case RTL_GIGA_MAC_VER_31:
3082                 ops->write      = r8168dp_2_mdio_write;
3083                 ops->read       = r8168dp_2_mdio_read;
3084                 break;
3085         default:
3086                 ops->write      = r8169_mdio_write;
3087                 ops->read       = r8169_mdio_read;
3088                 break;
3089         }
3090 }
3091
3092 static void r810x_phy_power_down(struct rtl8169_private *tp)
3093 {
3094         rtl_writephy(tp, 0x1f, 0x0000);
3095         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3096 }
3097
3098 static void r810x_phy_power_up(struct rtl8169_private *tp)
3099 {
3100         rtl_writephy(tp, 0x1f, 0x0000);
3101         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3102 }
3103
3104 static void r810x_pll_power_down(struct rtl8169_private *tp)
3105 {
3106         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3107                 rtl_writephy(tp, 0x1f, 0x0000);
3108                 rtl_writephy(tp, MII_BMCR, 0x0000);
3109                 return;
3110         }
3111
3112         r810x_phy_power_down(tp);
3113 }
3114
3115 static void r810x_pll_power_up(struct rtl8169_private *tp)
3116 {
3117         r810x_phy_power_up(tp);
3118 }
3119
3120 static void r8168_phy_power_up(struct rtl8169_private *tp)
3121 {
3122         rtl_writephy(tp, 0x1f, 0x0000);
3123         switch (tp->mac_version) {
3124         case RTL_GIGA_MAC_VER_11:
3125         case RTL_GIGA_MAC_VER_12:
3126         case RTL_GIGA_MAC_VER_17:
3127         case RTL_GIGA_MAC_VER_18:
3128         case RTL_GIGA_MAC_VER_19:
3129         case RTL_GIGA_MAC_VER_20:
3130         case RTL_GIGA_MAC_VER_21:
3131         case RTL_GIGA_MAC_VER_22:
3132         case RTL_GIGA_MAC_VER_23:
3133         case RTL_GIGA_MAC_VER_24:
3134         case RTL_GIGA_MAC_VER_25:
3135         case RTL_GIGA_MAC_VER_26:
3136         case RTL_GIGA_MAC_VER_27:
3137         case RTL_GIGA_MAC_VER_28:
3138         case RTL_GIGA_MAC_VER_31:
3139                 rtl_writephy(tp, 0x0e, 0x0000);
3140                 break;
3141         default:
3142                 break;
3143         }
3144         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3145 }
3146
3147 static void r8168_phy_power_down(struct rtl8169_private *tp)
3148 {
3149         rtl_writephy(tp, 0x1f, 0x0000);
3150         switch (tp->mac_version) {
3151         case RTL_GIGA_MAC_VER_32:
3152         case RTL_GIGA_MAC_VER_33:
3153                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3154                 break;
3155
3156         case RTL_GIGA_MAC_VER_11:
3157         case RTL_GIGA_MAC_VER_12:
3158         case RTL_GIGA_MAC_VER_17:
3159         case RTL_GIGA_MAC_VER_18:
3160         case RTL_GIGA_MAC_VER_19:
3161         case RTL_GIGA_MAC_VER_20:
3162         case RTL_GIGA_MAC_VER_21:
3163         case RTL_GIGA_MAC_VER_22:
3164         case RTL_GIGA_MAC_VER_23:
3165         case RTL_GIGA_MAC_VER_24:
3166         case RTL_GIGA_MAC_VER_25:
3167         case RTL_GIGA_MAC_VER_26:
3168         case RTL_GIGA_MAC_VER_27:
3169         case RTL_GIGA_MAC_VER_28:
3170         case RTL_GIGA_MAC_VER_31:
3171                 rtl_writephy(tp, 0x0e, 0x0200);
3172         default:
3173                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3174                 break;
3175         }
3176 }
3177
3178 static void r8168_pll_power_down(struct rtl8169_private *tp)
3179 {
3180         void __iomem *ioaddr = tp->mmio_addr;
3181
3182         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3183              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3184              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3185             r8168dp_check_dash(tp)) {
3186                 return;
3187         }
3188
3189         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3190              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3191             (RTL_R16(CPlusCmd) & ASF)) {
3192                 return;
3193         }
3194
3195         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3196             tp->mac_version == RTL_GIGA_MAC_VER_33)
3197                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3198
3199         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3200                 rtl_writephy(tp, 0x1f, 0x0000);
3201                 rtl_writephy(tp, MII_BMCR, 0x0000);
3202
3203                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3204                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3205                 return;
3206         }
3207
3208         r8168_phy_power_down(tp);
3209
3210         switch (tp->mac_version) {
3211         case RTL_GIGA_MAC_VER_25:
3212         case RTL_GIGA_MAC_VER_26:
3213         case RTL_GIGA_MAC_VER_27:
3214         case RTL_GIGA_MAC_VER_28:
3215         case RTL_GIGA_MAC_VER_31:
3216         case RTL_GIGA_MAC_VER_32:
3217         case RTL_GIGA_MAC_VER_33:
3218                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3219                 break;
3220         }
3221 }
3222
3223 static void r8168_pll_power_up(struct rtl8169_private *tp)
3224 {
3225         void __iomem *ioaddr = tp->mmio_addr;
3226
3227         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3228              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3229              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3230             r8168dp_check_dash(tp)) {
3231                 return;
3232         }
3233
3234         switch (tp->mac_version) {
3235         case RTL_GIGA_MAC_VER_25:
3236         case RTL_GIGA_MAC_VER_26:
3237         case RTL_GIGA_MAC_VER_27:
3238         case RTL_GIGA_MAC_VER_28:
3239         case RTL_GIGA_MAC_VER_31:
3240         case RTL_GIGA_MAC_VER_32:
3241         case RTL_GIGA_MAC_VER_33:
3242                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3243                 break;
3244         }
3245
3246         r8168_phy_power_up(tp);
3247 }
3248
3249 static void rtl_pll_power_op(struct rtl8169_private *tp,
3250                              void (*op)(struct rtl8169_private *))
3251 {
3252         if (op)
3253                 op(tp);
3254 }
3255
3256 static void rtl_pll_power_down(struct rtl8169_private *tp)
3257 {
3258         rtl_pll_power_op(tp, tp->pll_power_ops.down);
3259 }
3260
3261 static void rtl_pll_power_up(struct rtl8169_private *tp)
3262 {
3263         rtl_pll_power_op(tp, tp->pll_power_ops.up);
3264 }
3265
3266 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3267 {
3268         struct pll_power_ops *ops = &tp->pll_power_ops;
3269
3270         switch (tp->mac_version) {
3271         case RTL_GIGA_MAC_VER_07:
3272         case RTL_GIGA_MAC_VER_08:
3273         case RTL_GIGA_MAC_VER_09:
3274         case RTL_GIGA_MAC_VER_10:
3275         case RTL_GIGA_MAC_VER_16:
3276         case RTL_GIGA_MAC_VER_29:
3277         case RTL_GIGA_MAC_VER_30:
3278                 ops->down       = r810x_pll_power_down;
3279                 ops->up         = r810x_pll_power_up;
3280                 break;
3281
3282         case RTL_GIGA_MAC_VER_11:
3283         case RTL_GIGA_MAC_VER_12:
3284         case RTL_GIGA_MAC_VER_17:
3285         case RTL_GIGA_MAC_VER_18:
3286         case RTL_GIGA_MAC_VER_19:
3287         case RTL_GIGA_MAC_VER_20:
3288         case RTL_GIGA_MAC_VER_21:
3289         case RTL_GIGA_MAC_VER_22:
3290         case RTL_GIGA_MAC_VER_23:
3291         case RTL_GIGA_MAC_VER_24:
3292         case RTL_GIGA_MAC_VER_25:
3293         case RTL_GIGA_MAC_VER_26:
3294         case RTL_GIGA_MAC_VER_27:
3295         case RTL_GIGA_MAC_VER_28:
3296         case RTL_GIGA_MAC_VER_31:
3297         case RTL_GIGA_MAC_VER_32:
3298         case RTL_GIGA_MAC_VER_33:
3299                 ops->down       = r8168_pll_power_down;
3300                 ops->up         = r8168_pll_power_up;
3301                 break;
3302
3303         default:
3304                 ops->down       = NULL;
3305                 ops->up         = NULL;
3306                 break;
3307         }
3308 }
3309
3310 static void rtl_hw_reset(struct rtl8169_private *tp)
3311 {
3312         void __iomem *ioaddr = tp->mmio_addr;
3313         int i;
3314
3315         /* Soft reset the chip. */
3316         RTL_W8(ChipCmd, CmdReset);
3317
3318         /* Check that the chip has finished the reset. */
3319         for (i = 0; i < 100; i++) {
3320                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3321                         break;
3322                 msleep_interruptible(1);
3323         }
3324 }
3325
3326 static int __devinit
3327 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3328 {
3329         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3330         const unsigned int region = cfg->region;
3331         struct rtl8169_private *tp;
3332         struct mii_if_info *mii;
3333         struct net_device *dev;
3334         void __iomem *ioaddr;
3335         int chipset, i;
3336         int rc;
3337
3338         if (netif_msg_drv(&debug)) {
3339                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3340                        MODULENAME, RTL8169_VERSION);
3341         }
3342
3343         dev = alloc_etherdev(sizeof (*tp));
3344         if (!dev) {
3345                 if (netif_msg_drv(&debug))
3346                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3347                 rc = -ENOMEM;
3348                 goto out;
3349         }
3350
3351         SET_NETDEV_DEV(dev, &pdev->dev);
3352         dev->netdev_ops = &rtl8169_netdev_ops;
3353         tp = netdev_priv(dev);
3354         tp->dev = dev;
3355         tp->pci_dev = pdev;
3356         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3357
3358         mii = &tp->mii;
3359         mii->dev = dev;
3360         mii->mdio_read = rtl_mdio_read;
3361         mii->mdio_write = rtl_mdio_write;
3362         mii->phy_id_mask = 0x1f;
3363         mii->reg_num_mask = 0x1f;
3364         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3365
3366         /* disable ASPM completely as that cause random device stop working
3367          * problems as well as full system hangs for some PCIe devices users */
3368         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3369                                      PCIE_LINK_STATE_CLKPM);
3370
3371         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3372         rc = pci_enable_device(pdev);
3373         if (rc < 0) {
3374                 netif_err(tp, probe, dev, "enable failure\n");
3375                 goto err_out_free_dev_1;
3376         }
3377
3378         if (pci_set_mwi(pdev) < 0)
3379                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3380
3381         /* make sure PCI base addr 1 is MMIO */
3382         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3383                 netif_err(tp, probe, dev,
3384                           "region #%d not an MMIO resource, aborting\n",
3385                           region);
3386                 rc = -ENODEV;
3387                 goto err_out_mwi_2;
3388         }
3389
3390         /* check for weird/broken PCI region reporting */
3391         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3392                 netif_err(tp, probe, dev,
3393                           "Invalid PCI region size(s), aborting\n");
3394                 rc = -ENODEV;
3395                 goto err_out_mwi_2;
3396         }
3397
3398         rc = pci_request_regions(pdev, MODULENAME);
3399         if (rc < 0) {
3400                 netif_err(tp, probe, dev, "could not request regions\n");
3401                 goto err_out_mwi_2;
3402         }
3403
3404         tp->cp_cmd = RxChkSum;
3405
3406         if ((sizeof(dma_addr_t) > 4) &&
3407             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3408                 tp->cp_cmd |= PCIDAC;
3409                 dev->features |= NETIF_F_HIGHDMA;
3410         } else {
3411                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3412                 if (rc < 0) {
3413                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3414                         goto err_out_free_res_3;
3415                 }
3416         }
3417
3418         /* ioremap MMIO region */
3419         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3420         if (!ioaddr) {
3421                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3422                 rc = -EIO;
3423                 goto err_out_free_res_3;
3424         }
3425         tp->mmio_addr = ioaddr;
3426
3427         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3428         if (!tp->pcie_cap)
3429                 netif_info(tp, probe, dev, "no PCI Express capability\n");
3430
3431         RTL_W16(IntrMask, 0x0000);
3432
3433         rtl_hw_reset(tp);
3434
3435         RTL_W16(IntrStatus, 0xffff);
3436
3437         pci_set_master(pdev);
3438
3439         /* Identify chip attached to board */
3440         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3441
3442         /*
3443          * Pretend we are using VLANs; This bypasses a nasty bug where
3444          * Interrupts stop flowing on high load on 8110SCd controllers.
3445          */
3446         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3447                 tp->cp_cmd |= RxVlan;
3448
3449         rtl_init_mdio_ops(tp);
3450         rtl_init_pll_power_ops(tp);
3451
3452         rtl8169_print_mac_version(tp);
3453
3454         chipset = tp->mac_version;
3455         tp->txd_version = rtl_chip_infos[chipset].txd_version;
3456
3457         RTL_W8(Cfg9346, Cfg9346_Unlock);
3458         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3459         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3460         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3461                 tp->features |= RTL_FEATURE_WOL;
3462         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3463                 tp->features |= RTL_FEATURE_WOL;
3464         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3465         RTL_W8(Cfg9346, Cfg9346_Lock);
3466
3467         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3468             (RTL_R8(PHYstatus) & TBI_Enable)) {
3469                 tp->set_speed = rtl8169_set_speed_tbi;
3470                 tp->get_settings = rtl8169_gset_tbi;
3471                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3472                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3473                 tp->link_ok = rtl8169_tbi_link_ok;
3474                 tp->do_ioctl = rtl_tbi_ioctl;
3475         } else {
3476                 tp->set_speed = rtl8169_set_speed_xmii;
3477                 tp->get_settings = rtl8169_gset_xmii;
3478                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3479                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3480                 tp->link_ok = rtl8169_xmii_link_ok;
3481                 tp->do_ioctl = rtl_xmii_ioctl;
3482         }
3483
3484         spin_lock_init(&tp->lock);
3485
3486         /* Get MAC address */
3487         for (i = 0; i < MAC_ADDR_LEN; i++)
3488                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3489         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3490
3491         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3492         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3493         dev->irq = pdev->irq;
3494         dev->base_addr = (unsigned long) ioaddr;
3495
3496         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3497
3498         /* don't enable SG, IP_CSUM and TSO by default - it might not work
3499          * properly for all devices */
3500         dev->features |= NETIF_F_RXCSUM |
3501                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3502
3503         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3504                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3505         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3506                 NETIF_F_HIGHDMA;
3507
3508         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3509                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3510                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3511
3512         tp->intr_mask = 0xffff;
3513         tp->hw_start = cfg->hw_start;
3514         tp->intr_event = cfg->intr_event;
3515         tp->napi_event = cfg->napi_event;
3516
3517         init_timer(&tp->timer);
3518         tp->timer.data = (unsigned long) dev;
3519         tp->timer.function = rtl8169_phy_timer;
3520
3521         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
3522
3523         rc = register_netdev(dev);
3524         if (rc < 0)
3525                 goto err_out_msi_4;
3526
3527         pci_set_drvdata(pdev, dev);
3528
3529         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3530                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3531                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3532
3533         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3534             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3535             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3536                 rtl8168_driver_start(tp);
3537         }
3538
3539         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3540
3541         if (pci_dev_run_wake(pdev))
3542                 pm_runtime_put_noidle(&pdev->dev);
3543
3544         netif_carrier_off(dev);
3545
3546 out:
3547         return rc;
3548
3549 err_out_msi_4:
3550         rtl_disable_msi(pdev, tp);
3551         iounmap(ioaddr);
3552 err_out_free_res_3:
3553         pci_release_regions(pdev);
3554 err_out_mwi_2:
3555         pci_clear_mwi(pdev);
3556         pci_disable_device(pdev);
3557 err_out_free_dev_1:
3558         free_netdev(dev);
3559         goto out;
3560 }
3561
3562 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3563 {
3564         struct net_device *dev = pci_get_drvdata(pdev);
3565         struct rtl8169_private *tp = netdev_priv(dev);
3566
3567         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3568             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3569             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3570                 rtl8168_driver_stop(tp);
3571         }
3572
3573         cancel_delayed_work_sync(&tp->task);
3574
3575         unregister_netdev(dev);
3576
3577         rtl_release_firmware(tp);
3578
3579         if (pci_dev_run_wake(pdev))
3580                 pm_runtime_get_noresume(&pdev->dev);
3581
3582         /* restore original MAC address */
3583         rtl_rar_set(tp, dev->perm_addr);
3584
3585         rtl_disable_msi(pdev, tp);
3586         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3587         pci_set_drvdata(pdev, NULL);
3588 }
3589
3590 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3591 {
3592         struct rtl_fw *rtl_fw;
3593         const char *name;
3594         int rc = -ENOMEM;
3595
3596         name = rtl_lookup_firmware_name(tp);
3597         if (!name)
3598                 goto out_no_firmware;
3599
3600         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3601         if (!rtl_fw)
3602                 goto err_warn;
3603
3604         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3605         if (rc < 0)
3606                 goto err_free;
3607
3608         tp->rtl_fw = rtl_fw;
3609 out:
3610         return;
3611
3612 err_free:
3613         kfree(rtl_fw);
3614 err_warn:
3615         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3616                    name, rc);
3617 out_no_firmware:
3618         tp->rtl_fw = NULL;
3619         goto out;
3620 }
3621
3622 static void rtl_request_firmware(struct rtl8169_private *tp)
3623 {
3624         if (IS_ERR(tp->rtl_fw))
3625                 rtl_request_uncached_firmware(tp);
3626 }
3627
3628 static int rtl8169_open(struct net_device *dev)
3629 {
3630         struct rtl8169_private *tp = netdev_priv(dev);
3631         void __iomem *ioaddr = tp->mmio_addr;
3632         struct pci_dev *pdev = tp->pci_dev;
3633         int retval = -ENOMEM;
3634
3635         pm_runtime_get_sync(&pdev->dev);
3636
3637         /*
3638          * Rx and Tx desscriptors needs 256 bytes alignment.
3639          * dma_alloc_coherent provides more.
3640          */
3641         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3642                                              &tp->TxPhyAddr, GFP_KERNEL);
3643         if (!tp->TxDescArray)
3644                 goto err_pm_runtime_put;
3645
3646         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3647                                              &tp->RxPhyAddr, GFP_KERNEL);
3648         if (!tp->RxDescArray)
3649                 goto err_free_tx_0;
3650
3651         retval = rtl8169_init_ring(dev);
3652         if (retval < 0)
3653                 goto err_free_rx_1;
3654
3655         INIT_DELAYED_WORK(&tp->task, NULL);
3656
3657         smp_mb();
3658
3659         rtl_request_firmware(tp);
3660
3661         retval = request_irq(dev->irq, rtl8169_interrupt,
3662                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3663                              dev->name, dev);
3664         if (retval < 0)
3665                 goto err_release_fw_2;
3666
3667         napi_enable(&tp->napi);
3668
3669         rtl8169_init_phy(dev, tp);
3670
3671         rtl8169_set_features(dev, dev->features);
3672
3673         rtl_pll_power_up(tp);
3674
3675         rtl_hw_start(dev);
3676
3677         tp->saved_wolopts = 0;
3678         pm_runtime_put_noidle(&pdev->dev);
3679
3680         rtl8169_check_link_status(dev, tp, ioaddr);
3681 out:
3682         return retval;
3683
3684 err_release_fw_2:
3685         rtl_release_firmware(tp);
3686         rtl8169_rx_clear(tp);
3687 err_free_rx_1:
3688         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3689                           tp->RxPhyAddr);
3690         tp->RxDescArray = NULL;
3691 err_free_tx_0:
3692         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3693                           tp->TxPhyAddr);
3694         tp->TxDescArray = NULL;
3695 err_pm_runtime_put:
3696         pm_runtime_put_noidle(&pdev->dev);
3697         goto out;
3698 }
3699
3700 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3701 {
3702         void __iomem *ioaddr = tp->mmio_addr;
3703
3704         /* Disable interrupts */
3705         rtl8169_irq_mask_and_ack(ioaddr);
3706
3707         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3708             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3709             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3710                 while (RTL_R8(TxPoll) & NPQ)
3711                         udelay(20);
3712
3713         }
3714
3715         /* Reset the chipset */
3716         RTL_W8(ChipCmd, CmdReset);
3717
3718         /* PCI commit */
3719         RTL_R8(ChipCmd);
3720 }
3721
3722 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3723 {
3724         void __iomem *ioaddr = tp->mmio_addr;
3725         u32 cfg = rtl8169_rx_config;
3726
3727         cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
3728         RTL_W32(RxConfig, cfg);
3729
3730         /* Set DMA burst size and Interframe Gap Time */
3731         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3732                 (InterFrameGap << TxInterFrameGapShift));
3733 }
3734
3735 static void rtl_hw_start(struct net_device *dev)
3736 {
3737         struct rtl8169_private *tp = netdev_priv(dev);
3738
3739         rtl_hw_reset(tp);
3740
3741         tp->hw_start(dev);
3742
3743         netif_start_queue(dev);
3744 }
3745
3746 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3747                                          void __iomem *ioaddr)
3748 {
3749         /*
3750          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3751          * register to be written before TxDescAddrLow to work.
3752          * Switching from MMIO to I/O access fixes the issue as well.
3753          */
3754         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3755         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3756         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3757         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3758 }
3759
3760 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3761 {
3762         u16 cmd;
3763
3764         cmd = RTL_R16(CPlusCmd);
3765         RTL_W16(CPlusCmd, cmd);
3766         return cmd;
3767 }
3768
3769 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3770 {
3771         /* Low hurts. Let's disable the filtering. */
3772         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3773 }
3774
3775 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3776 {
3777         static const struct {
3778                 u32 mac_version;
3779                 u32 clk;
3780                 u32 val;
3781         } cfg2_info [] = {
3782                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3783                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3784                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3785                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3786         }, *p = cfg2_info;
3787         unsigned int i;
3788         u32 clk;
3789
3790         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3791         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3792                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3793                         RTL_W32(0x7c, p->val);
3794                         break;
3795                 }
3796         }
3797 }
3798
3799 static void rtl_hw_start_8169(struct net_device *dev)
3800 {
3801         struct rtl8169_private *tp = netdev_priv(dev);
3802         void __iomem *ioaddr = tp->mmio_addr;
3803         struct pci_dev *pdev = tp->pci_dev;
3804
3805         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3806                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3807                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3808         }
3809
3810         RTL_W8(Cfg9346, Cfg9346_Unlock);
3811         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3812             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3813             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3814             tp->mac_version == RTL_GIGA_MAC_VER_04)
3815                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3816
3817         RTL_W8(EarlyTxThres, NoEarlyTx);
3818
3819         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3820
3821         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3822             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3823             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3824             tp->mac_version == RTL_GIGA_MAC_VER_04)
3825                 rtl_set_rx_tx_config_registers(tp);
3826
3827         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3828
3829         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3830             tp->mac_version == RTL_GIGA_MAC_VER_03) {
3831                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3832                         "Bit-3 and bit-14 MUST be 1\n");
3833                 tp->cp_cmd |= (1 << 14);
3834         }
3835
3836         RTL_W16(CPlusCmd, tp->cp_cmd);
3837
3838         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3839
3840         /*
3841          * Undocumented corner. Supposedly:
3842          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3843          */
3844         RTL_W16(IntrMitigate, 0x0000);
3845
3846         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3847
3848         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3849             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3850             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3851             tp->mac_version != RTL_GIGA_MAC_VER_04) {
3852                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3853                 rtl_set_rx_tx_config_registers(tp);
3854         }
3855
3856         RTL_W8(Cfg9346, Cfg9346_Lock);
3857
3858         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3859         RTL_R8(IntrMask);
3860
3861         RTL_W32(RxMissed, 0);
3862
3863         rtl_set_rx_mode(dev);
3864
3865         /* no early-rx interrupts */
3866         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3867
3868         /* Enable all known interrupts by setting the interrupt mask. */
3869         RTL_W16(IntrMask, tp->intr_event);
3870 }
3871
3872 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3873 {
3874         struct net_device *dev = pci_get_drvdata(pdev);
3875         struct rtl8169_private *tp = netdev_priv(dev);
3876         int cap = tp->pcie_cap;
3877
3878         if (cap) {
3879                 u16 ctl;
3880
3881                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3882                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3883                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3884         }
3885 }
3886
3887 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3888 {
3889         u32 csi;
3890
3891         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3892         rtl_csi_write(ioaddr, 0x070c, csi | bits);
3893 }
3894
3895 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3896 {
3897         rtl_csi_access_enable(ioaddr, 0x17000000);
3898 }
3899
3900 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3901 {
3902         rtl_csi_access_enable(ioaddr, 0x27000000);
3903 }
3904
3905 struct ephy_info {
3906         unsigned int offset;
3907         u16 mask;
3908         u16 bits;
3909 };
3910
3911 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3912 {
3913         u16 w;
3914
3915         while (len-- > 0) {
3916                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3917                 rtl_ephy_write(ioaddr, e->offset, w);
3918                 e++;
3919         }
3920 }
3921
3922 static void rtl_disable_clock_request(struct pci_dev *pdev)
3923 {
3924         struct net_device *dev = pci_get_drvdata(pdev);
3925         struct rtl8169_private *tp = netdev_priv(dev);
3926         int cap = tp->pcie_cap;
3927
3928         if (cap) {
3929                 u16 ctl;
3930
3931                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3932                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3933                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3934         }
3935 }
3936
3937 static void rtl_enable_clock_request(struct pci_dev *pdev)
3938 {
3939         struct net_device *dev = pci_get_drvdata(pdev);
3940         struct rtl8169_private *tp = netdev_priv(dev);
3941         int cap = tp->pcie_cap;
3942
3943         if (cap) {
3944                 u16 ctl;
3945
3946                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3947                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3948                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3949         }
3950 }
3951
3952 #define R8168_CPCMD_QUIRK_MASK (\
3953         EnableBist | \
3954         Mac_dbgo_oe | \
3955         Force_half_dup | \
3956         Force_rxflow_en | \
3957         Force_txflow_en | \
3958         Cxpl_dbg_sel | \
3959         ASF | \
3960         PktCntrDisable | \
3961         Mac_dbgo_sel)
3962
3963 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3964 {
3965         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3966
3967         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3968
3969         rtl_tx_performance_tweak(pdev,
3970                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3971 }
3972
3973 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3974 {
3975         rtl_hw_start_8168bb(ioaddr, pdev);
3976
3977         RTL_W8(MaxTxPacketSize, TxPacketMax);
3978
3979         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3980 }
3981
3982 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3983 {
3984         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3985
3986         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3987
3988         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3989
3990         rtl_disable_clock_request(pdev);
3991
3992         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3993 }
3994
3995 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3996 {
3997         static const struct ephy_info e_info_8168cp[] = {
3998                 { 0x01, 0,      0x0001 },
3999                 { 0x02, 0x0800, 0x1000 },
4000                 { 0x03, 0,      0x0042 },
4001                 { 0x06, 0x0080, 0x0000 },
4002                 { 0x07, 0,      0x2000 }
4003         };
4004
4005         rtl_csi_access_enable_2(ioaddr);
4006
4007         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4008
4009         __rtl_hw_start_8168cp(ioaddr, pdev);
4010 }
4011
4012 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4013 {
4014         rtl_csi_access_enable_2(ioaddr);
4015
4016         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4017
4018         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4019
4020         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4021 }
4022
4023 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4024 {
4025         rtl_csi_access_enable_2(ioaddr);
4026
4027         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4028
4029         /* Magic. */
4030         RTL_W8(DBG_REG, 0x20);
4031
4032         RTL_W8(MaxTxPacketSize, TxPacketMax);
4033
4034         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4035
4036         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4037 }
4038
4039 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4040 {
4041         static const struct ephy_info e_info_8168c_1[] = {
4042                 { 0x02, 0x0800, 0x1000 },
4043                 { 0x03, 0,      0x0002 },
4044                 { 0x06, 0x0080, 0x0000 }
4045         };
4046
4047         rtl_csi_access_enable_2(ioaddr);
4048
4049         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4050
4051         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4052
4053         __rtl_hw_start_8168cp(ioaddr, pdev);
4054 }
4055
4056 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4057 {
4058         static const struct ephy_info e_info_8168c_2[] = {
4059                 { 0x01, 0,      0x0001 },
4060                 { 0x03, 0x0400, 0x0220 }
4061         };
4062
4063         rtl_csi_access_enable_2(ioaddr);
4064
4065         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4066
4067         __rtl_hw_start_8168cp(ioaddr, pdev);
4068 }
4069
4070 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4071 {
4072         rtl_hw_start_8168c_2(ioaddr, pdev);
4073 }
4074
4075 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4076 {
4077         rtl_csi_access_enable_2(ioaddr);
4078
4079         __rtl_hw_start_8168cp(ioaddr, pdev);
4080 }
4081
4082 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4083 {
4084         rtl_csi_access_enable_2(ioaddr);
4085
4086         rtl_disable_clock_request(pdev);
4087
4088         RTL_W8(MaxTxPacketSize, TxPacketMax);
4089
4090         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4091
4092         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4093 }
4094
4095 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4096 {
4097         rtl_csi_access_enable_1(ioaddr);
4098
4099         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4100
4101         RTL_W8(MaxTxPacketSize, TxPacketMax);
4102
4103         rtl_disable_clock_request(pdev);
4104 }
4105
4106 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4107 {
4108         static const struct ephy_info e_info_8168d_4[] = {
4109                 { 0x0b, ~0,     0x48 },
4110                 { 0x19, 0x20,   0x50 },
4111                 { 0x0c, ~0,     0x20 }
4112         };
4113         int i;
4114
4115         rtl_csi_access_enable_1(ioaddr);
4116
4117         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4118
4119         RTL_W8(MaxTxPacketSize, TxPacketMax);
4120
4121         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4122                 const struct ephy_info *e = e_info_8168d_4 + i;
4123                 u16 w;
4124
4125                 w = rtl_ephy_read(ioaddr, e->offset);
4126                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4127         }
4128
4129         rtl_enable_clock_request(pdev);
4130 }
4131
4132 static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4133 {
4134         static const struct ephy_info e_info_8168e[] = {
4135                 { 0x00, 0x0200, 0x0100 },
4136                 { 0x00, 0x0000, 0x0004 },
4137                 { 0x06, 0x0002, 0x0001 },
4138                 { 0x06, 0x0000, 0x0030 },
4139                 { 0x07, 0x0000, 0x2000 },
4140                 { 0x00, 0x0000, 0x0020 },
4141                 { 0x03, 0x5800, 0x2000 },
4142                 { 0x03, 0x0000, 0x0001 },
4143                 { 0x01, 0x0800, 0x1000 },
4144                 { 0x07, 0x0000, 0x4000 },
4145                 { 0x1e, 0x0000, 0x2000 },
4146                 { 0x19, 0xffff, 0xfe6c },
4147                 { 0x0a, 0x0000, 0x0040 }
4148         };
4149
4150         rtl_csi_access_enable_2(ioaddr);
4151
4152         rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4153
4154         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4155
4156         RTL_W8(MaxTxPacketSize, TxPacketMax);
4157
4158         rtl_disable_clock_request(pdev);
4159
4160         /* Reset tx FIFO pointer */
4161         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4162         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4163
4164         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4165 }
4166
4167 static void rtl_hw_start_8168(struct net_device *dev)
4168 {
4169         struct rtl8169_private *tp = netdev_priv(dev);
4170         void __iomem *ioaddr = tp->mmio_addr;
4171         struct pci_dev *pdev = tp->pci_dev;
4172
4173         RTL_W8(Cfg9346, Cfg9346_Unlock);
4174
4175         RTL_W8(MaxTxPacketSize, TxPacketMax);
4176
4177         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4178
4179         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4180
4181         RTL_W16(CPlusCmd, tp->cp_cmd);
4182
4183         RTL_W16(IntrMitigate, 0x5151);
4184
4185         /* Work around for RxFIFO overflow. */
4186         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4187             tp->mac_version == RTL_GIGA_MAC_VER_22) {
4188                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4189                 tp->intr_event &= ~RxOverflow;
4190         }
4191
4192         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4193
4194         rtl_set_rx_mode(dev);
4195
4196         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4197                 (InterFrameGap << TxInterFrameGapShift));
4198
4199         RTL_R8(IntrMask);
4200
4201         switch (tp->mac_version) {
4202         case RTL_GIGA_MAC_VER_11:
4203                 rtl_hw_start_8168bb(ioaddr, pdev);
4204                 break;
4205
4206         case RTL_GIGA_MAC_VER_12:
4207         case RTL_GIGA_MAC_VER_17:
4208                 rtl_hw_start_8168bef(ioaddr, pdev);
4209                 break;
4210
4211         case RTL_GIGA_MAC_VER_18:
4212                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4213                 break;
4214
4215         case RTL_GIGA_MAC_VER_19:
4216                 rtl_hw_start_8168c_1(ioaddr, pdev);
4217                 break;
4218
4219         case RTL_GIGA_MAC_VER_20:
4220                 rtl_hw_start_8168c_2(ioaddr, pdev);
4221                 break;
4222
4223         case RTL_GIGA_MAC_VER_21:
4224                 rtl_hw_start_8168c_3(ioaddr, pdev);
4225                 break;
4226
4227         case RTL_GIGA_MAC_VER_22:
4228                 rtl_hw_start_8168c_4(ioaddr, pdev);
4229                 break;
4230
4231         case RTL_GIGA_MAC_VER_23:
4232                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4233                 break;
4234
4235         case RTL_GIGA_MAC_VER_24:
4236                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4237                 break;
4238
4239         case RTL_GIGA_MAC_VER_25:
4240         case RTL_GIGA_MAC_VER_26:
4241         case RTL_GIGA_MAC_VER_27:
4242                 rtl_hw_start_8168d(ioaddr, pdev);
4243                 break;
4244
4245         case RTL_GIGA_MAC_VER_28:
4246                 rtl_hw_start_8168d_4(ioaddr, pdev);
4247                 break;
4248
4249         case RTL_GIGA_MAC_VER_31:
4250                 rtl_hw_start_8168dp(ioaddr, pdev);
4251                 break;
4252
4253         case RTL_GIGA_MAC_VER_32:
4254         case RTL_GIGA_MAC_VER_33:
4255                 rtl_hw_start_8168e(ioaddr, pdev);
4256                 break;
4257
4258         default:
4259                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4260                         dev->name, tp->mac_version);
4261                 break;
4262         }
4263
4264         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4265
4266         RTL_W8(Cfg9346, Cfg9346_Lock);
4267
4268         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4269
4270         RTL_W16(IntrMask, tp->intr_event);
4271 }
4272
4273 #define R810X_CPCMD_QUIRK_MASK (\
4274         EnableBist | \
4275         Mac_dbgo_oe | \
4276         Force_half_dup | \
4277         Force_rxflow_en | \
4278         Force_txflow_en | \
4279         Cxpl_dbg_sel | \
4280         ASF | \
4281         PktCntrDisable | \
4282         Mac_dbgo_sel)
4283
4284 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4285 {
4286         static const struct ephy_info e_info_8102e_1[] = {
4287                 { 0x01, 0, 0x6e65 },
4288                 { 0x02, 0, 0x091f },
4289                 { 0x03, 0, 0xc2f9 },
4290                 { 0x06, 0, 0xafb5 },
4291                 { 0x07, 0, 0x0e00 },
4292                 { 0x19, 0, 0xec80 },
4293                 { 0x01, 0, 0x2e65 },
4294                 { 0x01, 0, 0x6e65 }
4295         };
4296         u8 cfg1;
4297
4298         rtl_csi_access_enable_2(ioaddr);
4299
4300         RTL_W8(DBG_REG, FIX_NAK_1);
4301
4302         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4303
4304         RTL_W8(Config1,
4305                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4306         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4307
4308         cfg1 = RTL_R8(Config1);
4309         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4310                 RTL_W8(Config1, cfg1 & ~LEDS0);
4311
4312         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4313 }
4314
4315 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4316 {
4317         rtl_csi_access_enable_2(ioaddr);
4318
4319         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4320
4321         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4322         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4323 }
4324
4325 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4326 {
4327         rtl_hw_start_8102e_2(ioaddr, pdev);
4328
4329         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4330 }
4331
4332 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4333 {
4334         static const struct ephy_info e_info_8105e_1[] = {
4335                 { 0x07, 0, 0x4000 },
4336                 { 0x19, 0, 0x0200 },
4337                 { 0x19, 0, 0x0020 },
4338                 { 0x1e, 0, 0x2000 },
4339                 { 0x03, 0, 0x0001 },
4340                 { 0x19, 0, 0x0100 },
4341                 { 0x19, 0, 0x0004 },
4342                 { 0x0a, 0, 0x0020 }
4343         };
4344
4345         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4346         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4347
4348         /* Disable Early Tally Counter */
4349         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4350
4351         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4352         RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4353
4354         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4355 }
4356
4357 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4358 {
4359         rtl_hw_start_8105e_1(ioaddr, pdev);
4360         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4361 }
4362
4363 static void rtl_hw_start_8101(struct net_device *dev)
4364 {
4365         struct rtl8169_private *tp = netdev_priv(dev);
4366         void __iomem *ioaddr = tp->mmio_addr;
4367         struct pci_dev *pdev = tp->pci_dev;
4368
4369         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4370             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4371                 int cap = tp->pcie_cap;
4372
4373                 if (cap) {
4374                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4375                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4376                 }
4377         }
4378
4379         RTL_W8(Cfg9346, Cfg9346_Unlock);
4380
4381         switch (tp->mac_version) {
4382         case RTL_GIGA_MAC_VER_07:
4383                 rtl_hw_start_8102e_1(ioaddr, pdev);
4384                 break;
4385
4386         case RTL_GIGA_MAC_VER_08:
4387                 rtl_hw_start_8102e_3(ioaddr, pdev);
4388                 break;
4389
4390         case RTL_GIGA_MAC_VER_09:
4391                 rtl_hw_start_8102e_2(ioaddr, pdev);
4392                 break;
4393
4394         case RTL_GIGA_MAC_VER_29:
4395                 rtl_hw_start_8105e_1(ioaddr, pdev);
4396                 break;
4397         case RTL_GIGA_MAC_VER_30:
4398                 rtl_hw_start_8105e_2(ioaddr, pdev);
4399                 break;
4400         }
4401
4402         RTL_W8(Cfg9346, Cfg9346_Lock);
4403
4404         RTL_W8(MaxTxPacketSize, TxPacketMax);
4405
4406         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4407
4408         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4409         RTL_W16(CPlusCmd, tp->cp_cmd);
4410
4411         RTL_W16(IntrMitigate, 0x0000);
4412
4413         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4414
4415         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4416         rtl_set_rx_tx_config_registers(tp);
4417
4418         RTL_R8(IntrMask);
4419
4420         rtl_set_rx_mode(dev);
4421
4422         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4423
4424         RTL_W16(IntrMask, tp->intr_event);
4425 }
4426
4427 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4428 {
4429         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4430                 return -EINVAL;
4431
4432         dev->mtu = new_mtu;
4433         netdev_update_features(dev);
4434
4435         return 0;
4436 }
4437
4438 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4439 {
4440         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4441         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4442 }
4443
4444 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4445                                      void **data_buff, struct RxDesc *desc)
4446 {
4447         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4448                          DMA_FROM_DEVICE);
4449
4450         kfree(*data_buff);
4451         *data_buff = NULL;
4452         rtl8169_make_unusable_by_asic(desc);
4453 }
4454
4455 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4456 {
4457         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4458
4459         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4460 }
4461
4462 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4463                                        u32 rx_buf_sz)
4464 {
4465         desc->addr = cpu_to_le64(mapping);
4466         wmb();
4467         rtl8169_mark_to_asic(desc, rx_buf_sz);
4468 }
4469
4470 static inline void *rtl8169_align(void *data)
4471 {
4472         return (void *)ALIGN((long)data, 16);
4473 }
4474
4475 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4476                                              struct RxDesc *desc)
4477 {
4478         void *data;
4479         dma_addr_t mapping;
4480         struct device *d = &tp->pci_dev->dev;
4481         struct net_device *dev = tp->dev;
4482         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4483
4484         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4485         if (!data)
4486                 return NULL;
4487
4488         if (rtl8169_align(data) != data) {
4489                 kfree(data);
4490                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4491                 if (!data)
4492                         return NULL;
4493         }
4494
4495         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4496                                  DMA_FROM_DEVICE);
4497         if (unlikely(dma_mapping_error(d, mapping))) {
4498                 if (net_ratelimit())
4499                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4500                 goto err_out;
4501         }
4502
4503         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4504         return data;
4505
4506 err_out:
4507         kfree(data);
4508         return NULL;
4509 }
4510
4511 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4512 {
4513         unsigned int i;
4514
4515         for (i = 0; i < NUM_RX_DESC; i++) {
4516                 if (tp->Rx_databuff[i]) {
4517                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4518                                             tp->RxDescArray + i);
4519                 }
4520         }
4521 }
4522
4523 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4524 {
4525         desc->opts1 |= cpu_to_le32(RingEnd);
4526 }
4527
4528 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4529 {
4530         unsigned int i;
4531
4532         for (i = 0; i < NUM_RX_DESC; i++) {
4533                 void *data;
4534
4535                 if (tp->Rx_databuff[i])
4536                         continue;
4537
4538                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4539                 if (!data) {
4540                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4541                         goto err_out;
4542                 }
4543                 tp->Rx_databuff[i] = data;
4544         }
4545
4546         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4547         return 0;
4548
4549 err_out:
4550         rtl8169_rx_clear(tp);
4551         return -ENOMEM;
4552 }
4553
4554 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4555 {
4556         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4557 }
4558
4559 static int rtl8169_init_ring(struct net_device *dev)
4560 {
4561         struct rtl8169_private *tp = netdev_priv(dev);
4562
4563         rtl8169_init_ring_indexes(tp);
4564
4565         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4566         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4567
4568         return rtl8169_rx_fill(tp);
4569 }
4570
4571 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4572                                  struct TxDesc *desc)
4573 {
4574         unsigned int len = tx_skb->len;
4575
4576         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4577
4578         desc->opts1 = 0x00;
4579         desc->opts2 = 0x00;
4580         desc->addr = 0x00;
4581         tx_skb->len = 0;
4582 }
4583
4584 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4585                                    unsigned int n)
4586 {
4587         unsigned int i;
4588
4589         for (i = 0; i < n; i++) {
4590                 unsigned int entry = (start + i) % NUM_TX_DESC;
4591                 struct ring_info *tx_skb = tp->tx_skb + entry;
4592                 unsigned int len = tx_skb->len;
4593
4594                 if (len) {
4595                         struct sk_buff *skb = tx_skb->skb;
4596
4597                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4598                                              tp->TxDescArray + entry);
4599                         if (skb) {
4600                                 tp->dev->stats.tx_dropped++;
4601                                 dev_kfree_skb(skb);
4602                                 tx_skb->skb = NULL;
4603                         }
4604                 }
4605         }
4606 }
4607
4608 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4609 {
4610         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4611         tp->cur_tx = tp->dirty_tx = 0;
4612 }
4613
4614 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4615 {
4616         struct rtl8169_private *tp = netdev_priv(dev);
4617
4618         PREPARE_DELAYED_WORK(&tp->task, task);
4619         schedule_delayed_work(&tp->task, 4);
4620 }
4621
4622 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4623 {
4624         struct rtl8169_private *tp = netdev_priv(dev);
4625         void __iomem *ioaddr = tp->mmio_addr;
4626
4627         synchronize_irq(dev->irq);
4628
4629         /* Wait for any pending NAPI task to complete */
4630         napi_disable(&tp->napi);
4631
4632         rtl8169_irq_mask_and_ack(ioaddr);
4633
4634         tp->intr_mask = 0xffff;
4635         RTL_W16(IntrMask, tp->intr_event);
4636         napi_enable(&tp->napi);
4637 }
4638
4639 static void rtl8169_reinit_task(struct work_struct *work)
4640 {
4641         struct rtl8169_private *tp =
4642                 container_of(work, struct rtl8169_private, task.work);
4643         struct net_device *dev = tp->dev;
4644         int ret;
4645
4646         rtnl_lock();
4647
4648         if (!netif_running(dev))
4649                 goto out_unlock;
4650
4651         rtl8169_wait_for_quiescence(dev);
4652         rtl8169_close(dev);
4653
4654         ret = rtl8169_open(dev);
4655         if (unlikely(ret < 0)) {
4656                 if (net_ratelimit())
4657                         netif_err(tp, drv, dev,
4658                                   "reinit failure (status = %d). Rescheduling\n",
4659                                   ret);
4660                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4661         }
4662
4663 out_unlock:
4664         rtnl_unlock();
4665 }
4666
4667 static void rtl8169_reset_task(struct work_struct *work)
4668 {
4669         struct rtl8169_private *tp =
4670                 container_of(work, struct rtl8169_private, task.work);
4671         struct net_device *dev = tp->dev;
4672         int i;
4673
4674         rtnl_lock();
4675
4676         if (!netif_running(dev))
4677                 goto out_unlock;
4678
4679         rtl8169_wait_for_quiescence(dev);
4680
4681         for (i = 0; i < NUM_RX_DESC; i++)
4682                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4683
4684         rtl8169_tx_clear(tp);
4685
4686         rtl8169_init_ring_indexes(tp);
4687         rtl_hw_start(dev);
4688         netif_wake_queue(dev);
4689         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4690
4691 out_unlock:
4692         rtnl_unlock();
4693 }
4694
4695 static void rtl8169_tx_timeout(struct net_device *dev)
4696 {
4697         struct rtl8169_private *tp = netdev_priv(dev);
4698
4699         rtl8169_hw_reset(tp);
4700
4701         /* Let's wait a bit while any (async) irq lands on */
4702         rtl8169_schedule_work(dev, rtl8169_reset_task);
4703 }
4704
4705 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4706                               u32 *opts)
4707 {
4708         struct skb_shared_info *info = skb_shinfo(skb);
4709         unsigned int cur_frag, entry;
4710         struct TxDesc * uninitialized_var(txd);
4711         struct device *d = &tp->pci_dev->dev;
4712
4713         entry = tp->cur_tx;
4714         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4715                 skb_frag_t *frag = info->frags + cur_frag;
4716                 dma_addr_t mapping;
4717                 u32 status, len;
4718                 void *addr;
4719
4720                 entry = (entry + 1) % NUM_TX_DESC;
4721
4722                 txd = tp->TxDescArray + entry;
4723                 len = frag->size;
4724                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4725                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4726                 if (unlikely(dma_mapping_error(d, mapping))) {
4727                         if (net_ratelimit())
4728                                 netif_err(tp, drv, tp->dev,
4729                                           "Failed to map TX fragments DMA!\n");
4730                         goto err_out;
4731                 }
4732
4733                 /* Anti gcc 2.95.3 bugware (sic) */
4734                 status = opts[0] | len |
4735                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
4736
4737                 txd->opts1 = cpu_to_le32(status);
4738                 txd->opts2 = cpu_to_le32(opts[1]);
4739                 txd->addr = cpu_to_le64(mapping);
4740
4741                 tp->tx_skb[entry].len = len;
4742         }
4743
4744         if (cur_frag) {
4745                 tp->tx_skb[entry].skb = skb;
4746                 txd->opts1 |= cpu_to_le32(LastFrag);
4747         }
4748
4749         return cur_frag;
4750
4751 err_out:
4752         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4753         return -EIO;
4754 }
4755
4756 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4757                                     struct sk_buff *skb, u32 *opts)
4758 {
4759         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
4760         u32 mss = skb_shinfo(skb)->gso_size;
4761         int offset = info->opts_offset;
4762
4763         if (mss) {
4764                 opts[0] |= TD_LSO;
4765                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4766         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4767                 const struct iphdr *ip = ip_hdr(skb);
4768
4769                 if (ip->protocol == IPPROTO_TCP)
4770                         opts[offset] |= info->checksum.tcp;
4771                 else if (ip->protocol == IPPROTO_UDP)
4772                         opts[offset] |= info->checksum.udp;
4773                 else
4774                         WARN_ON_ONCE(1);
4775         }
4776 }
4777
4778 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4779                                       struct net_device *dev)
4780 {
4781         struct rtl8169_private *tp = netdev_priv(dev);
4782         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4783         struct TxDesc *txd = tp->TxDescArray + entry;
4784         void __iomem *ioaddr = tp->mmio_addr;
4785         struct device *d = &tp->pci_dev->dev;
4786         dma_addr_t mapping;
4787         u32 status, len;
4788         u32 opts[2];
4789         int frags;
4790
4791         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4792                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4793                 goto err_stop_0;
4794         }
4795
4796         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4797                 goto err_stop_0;
4798
4799         len = skb_headlen(skb);
4800         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4801         if (unlikely(dma_mapping_error(d, mapping))) {
4802                 if (net_ratelimit())
4803                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4804                 goto err_dma_0;
4805         }
4806
4807         tp->tx_skb[entry].len = len;
4808         txd->addr = cpu_to_le64(mapping);
4809
4810         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4811         opts[0] = DescOwn;
4812
4813         rtl8169_tso_csum(tp, skb, opts);
4814
4815         frags = rtl8169_xmit_frags(tp, skb, opts);
4816         if (frags < 0)
4817                 goto err_dma_1;
4818         else if (frags)
4819                 opts[0] |= FirstFrag;
4820         else {
4821                 opts[0] |= FirstFrag | LastFrag;
4822                 tp->tx_skb[entry].skb = skb;
4823         }
4824
4825         txd->opts2 = cpu_to_le32(opts[1]);
4826
4827         wmb();
4828
4829         /* Anti gcc 2.95.3 bugware (sic) */
4830         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4831         txd->opts1 = cpu_to_le32(status);
4832
4833         tp->cur_tx += frags + 1;
4834
4835         wmb();
4836
4837         RTL_W8(TxPoll, NPQ);
4838
4839         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4840                 netif_stop_queue(dev);
4841                 smp_rmb();
4842                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4843                         netif_wake_queue(dev);
4844         }
4845
4846         return NETDEV_TX_OK;
4847
4848 err_dma_1:
4849         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4850 err_dma_0:
4851         dev_kfree_skb(skb);
4852         dev->stats.tx_dropped++;
4853         return NETDEV_TX_OK;
4854
4855 err_stop_0:
4856         netif_stop_queue(dev);
4857         dev->stats.tx_dropped++;
4858         return NETDEV_TX_BUSY;
4859 }
4860
4861 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4862 {
4863         struct rtl8169_private *tp = netdev_priv(dev);
4864         struct pci_dev *pdev = tp->pci_dev;
4865         u16 pci_status, pci_cmd;
4866
4867         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4868         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4869
4870         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4871                   pci_cmd, pci_status);
4872
4873         /*
4874          * The recovery sequence below admits a very elaborated explanation:
4875          * - it seems to work;
4876          * - I did not see what else could be done;
4877          * - it makes iop3xx happy.
4878          *
4879          * Feel free to adjust to your needs.
4880          */
4881         if (pdev->broken_parity_status)
4882                 pci_cmd &= ~PCI_COMMAND_PARITY;
4883         else
4884                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4885
4886         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4887
4888         pci_write_config_word(pdev, PCI_STATUS,
4889                 pci_status & (PCI_STATUS_DETECTED_PARITY |
4890                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4891                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4892
4893         /* The infamous DAC f*ckup only happens at boot time */
4894         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4895                 void __iomem *ioaddr = tp->mmio_addr;
4896
4897                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4898                 tp->cp_cmd &= ~PCIDAC;
4899                 RTL_W16(CPlusCmd, tp->cp_cmd);
4900                 dev->features &= ~NETIF_F_HIGHDMA;
4901         }
4902
4903         rtl8169_hw_reset(tp);
4904
4905         rtl8169_schedule_work(dev, rtl8169_reinit_task);
4906 }
4907
4908 static void rtl8169_tx_interrupt(struct net_device *dev,
4909                                  struct rtl8169_private *tp,
4910                                  void __iomem *ioaddr)
4911 {
4912         unsigned int dirty_tx, tx_left;
4913
4914         dirty_tx = tp->dirty_tx;
4915         smp_rmb();
4916         tx_left = tp->cur_tx - dirty_tx;
4917
4918         while (tx_left > 0) {
4919                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4920                 struct ring_info *tx_skb = tp->tx_skb + entry;
4921                 u32 status;
4922
4923                 rmb();
4924                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4925                 if (status & DescOwn)
4926                         break;
4927
4928                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4929                                      tp->TxDescArray + entry);
4930                 if (status & LastFrag) {
4931                         dev->stats.tx_packets++;
4932                         dev->stats.tx_bytes += tx_skb->skb->len;
4933                         dev_kfree_skb(tx_skb->skb);
4934                         tx_skb->skb = NULL;
4935                 }
4936                 dirty_tx++;
4937                 tx_left--;
4938         }
4939
4940         if (tp->dirty_tx != dirty_tx) {
4941                 tp->dirty_tx = dirty_tx;
4942                 smp_wmb();
4943                 if (netif_queue_stopped(dev) &&
4944                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4945                         netif_wake_queue(dev);
4946                 }
4947                 /*
4948                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4949                  * too close. Let's kick an extra TxPoll request when a burst
4950                  * of start_xmit activity is detected (if it is not detected,
4951                  * it is slow enough). -- FR
4952                  */
4953                 smp_rmb();
4954                 if (tp->cur_tx != dirty_tx)
4955                         RTL_W8(TxPoll, NPQ);
4956         }
4957 }
4958
4959 static inline int rtl8169_fragmented_frame(u32 status)
4960 {
4961         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4962 }
4963
4964 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4965 {
4966         u32 status = opts1 & RxProtoMask;
4967
4968         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4969             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4970                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4971         else
4972                 skb_checksum_none_assert(skb);
4973 }
4974
4975 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4976                                            struct rtl8169_private *tp,
4977                                            int pkt_size,
4978                                            dma_addr_t addr)
4979 {
4980         struct sk_buff *skb;
4981         struct device *d = &tp->pci_dev->dev;
4982
4983         data = rtl8169_align(data);
4984         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4985         prefetch(data);
4986         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4987         if (skb)
4988                 memcpy(skb->data, data, pkt_size);
4989         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4990
4991         return skb;
4992 }
4993
4994 static int rtl8169_rx_interrupt(struct net_device *dev,
4995                                 struct rtl8169_private *tp,
4996                                 void __iomem *ioaddr, u32 budget)
4997 {
4998         unsigned int cur_rx, rx_left;
4999         unsigned int count;
5000
5001         cur_rx = tp->cur_rx;
5002         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5003         rx_left = min(rx_left, budget);
5004
5005         for (; rx_left > 0; rx_left--, cur_rx++) {
5006                 unsigned int entry = cur_rx % NUM_RX_DESC;
5007                 struct RxDesc *desc = tp->RxDescArray + entry;
5008                 u32 status;
5009
5010                 rmb();
5011                 status = le32_to_cpu(desc->opts1);
5012
5013                 if (status & DescOwn)
5014                         break;
5015                 if (unlikely(status & RxRES)) {
5016                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5017                                    status);
5018                         dev->stats.rx_errors++;
5019                         if (status & (RxRWT | RxRUNT))
5020                                 dev->stats.rx_length_errors++;
5021                         if (status & RxCRC)
5022                                 dev->stats.rx_crc_errors++;
5023                         if (status & RxFOVF) {
5024                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
5025                                 dev->stats.rx_fifo_errors++;
5026                         }
5027                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5028                 } else {
5029                         struct sk_buff *skb;
5030                         dma_addr_t addr = le64_to_cpu(desc->addr);
5031                         int pkt_size = (status & 0x00001FFF) - 4;
5032
5033                         /*
5034                          * The driver does not support incoming fragmented
5035                          * frames. They are seen as a symptom of over-mtu
5036                          * sized frames.
5037                          */
5038                         if (unlikely(rtl8169_fragmented_frame(status))) {
5039                                 dev->stats.rx_dropped++;
5040                                 dev->stats.rx_length_errors++;
5041                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5042                                 continue;
5043                         }
5044
5045                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5046                                                   tp, pkt_size, addr);
5047                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5048                         if (!skb) {
5049                                 dev->stats.rx_dropped++;
5050                                 continue;
5051                         }
5052
5053                         rtl8169_rx_csum(skb, status);
5054                         skb_put(skb, pkt_size);
5055                         skb->protocol = eth_type_trans(skb, dev);
5056
5057                         rtl8169_rx_vlan_tag(desc, skb);
5058
5059                         napi_gro_receive(&tp->napi, skb);
5060
5061                         dev->stats.rx_bytes += pkt_size;
5062                         dev->stats.rx_packets++;
5063                 }
5064
5065                 /* Work around for AMD plateform. */
5066                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5067                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5068                         desc->opts2 = 0;
5069                         cur_rx++;
5070                 }
5071         }
5072
5073         count = cur_rx - tp->cur_rx;
5074         tp->cur_rx = cur_rx;
5075
5076         tp->dirty_rx += count;
5077
5078         return count;
5079 }
5080
5081 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5082 {
5083         struct net_device *dev = dev_instance;
5084         struct rtl8169_private *tp = netdev_priv(dev);
5085         void __iomem *ioaddr = tp->mmio_addr;
5086         int handled = 0;
5087         int status;
5088
5089         /* loop handling interrupts until we have no new ones or
5090          * we hit a invalid/hotplug case.
5091          */
5092         status = RTL_R16(IntrStatus);
5093         while (status && status != 0xffff) {
5094                 handled = 1;
5095
5096                 /* Handle all of the error cases first. These will reset
5097                  * the chip, so just exit the loop.
5098                  */
5099                 if (unlikely(!netif_running(dev))) {
5100                         rtl8169_asic_down(ioaddr);
5101                         break;
5102                 }
5103
5104                 if (unlikely(status & RxFIFOOver)) {
5105                         switch (tp->mac_version) {
5106                         /* Work around for rx fifo overflow */
5107                         case RTL_GIGA_MAC_VER_11:
5108                         case RTL_GIGA_MAC_VER_22:
5109                         case RTL_GIGA_MAC_VER_26:
5110                                 netif_stop_queue(dev);
5111                                 rtl8169_tx_timeout(dev);
5112                                 goto done;
5113                         /* Testers needed. */
5114                         case RTL_GIGA_MAC_VER_17:
5115                         case RTL_GIGA_MAC_VER_19:
5116                         case RTL_GIGA_MAC_VER_20:
5117                         case RTL_GIGA_MAC_VER_21:
5118                         case RTL_GIGA_MAC_VER_23:
5119                         case RTL_GIGA_MAC_VER_24:
5120                         case RTL_GIGA_MAC_VER_27:
5121                         case RTL_GIGA_MAC_VER_28:
5122                         case RTL_GIGA_MAC_VER_31:
5123                         /* Experimental science. Pktgen proof. */
5124                         case RTL_GIGA_MAC_VER_12:
5125                         case RTL_GIGA_MAC_VER_25:
5126                                 if (status == RxFIFOOver)
5127                                         goto done;
5128                                 break;
5129                         default:
5130                                 break;
5131                         }
5132                 }
5133
5134                 if (unlikely(status & SYSErr)) {
5135                         rtl8169_pcierr_interrupt(dev);
5136                         break;
5137                 }
5138
5139                 if (status & LinkChg)
5140                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5141
5142                 /* We need to see the lastest version of tp->intr_mask to
5143                  * avoid ignoring an MSI interrupt and having to wait for
5144                  * another event which may never come.
5145                  */
5146                 smp_rmb();
5147                 if (status & tp->intr_mask & tp->napi_event) {
5148                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5149                         tp->intr_mask = ~tp->napi_event;
5150
5151                         if (likely(napi_schedule_prep(&tp->napi)))
5152                                 __napi_schedule(&tp->napi);
5153                         else
5154                                 netif_info(tp, intr, dev,
5155                                            "interrupt %04x in poll\n", status);
5156                 }
5157
5158                 /* We only get a new MSI interrupt when all active irq
5159                  * sources on the chip have been acknowledged. So, ack
5160                  * everything we've seen and check if new sources have become
5161                  * active to avoid blocking all interrupts from the chip.
5162                  */
5163                 RTL_W16(IntrStatus,
5164                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5165                 status = RTL_R16(IntrStatus);
5166         }
5167 done:
5168         return IRQ_RETVAL(handled);
5169 }
5170
5171 static int rtl8169_poll(struct napi_struct *napi, int budget)
5172 {
5173         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5174         struct net_device *dev = tp->dev;
5175         void __iomem *ioaddr = tp->mmio_addr;
5176         int work_done;
5177
5178         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5179         rtl8169_tx_interrupt(dev, tp, ioaddr);
5180
5181         if (work_done < budget) {
5182                 napi_complete(napi);
5183
5184                 /* We need for force the visibility of tp->intr_mask
5185                  * for other CPUs, as we can loose an MSI interrupt
5186                  * and potentially wait for a retransmit timeout if we don't.
5187                  * The posted write to IntrMask is safe, as it will
5188                  * eventually make it to the chip and we won't loose anything
5189                  * until it does.
5190                  */
5191                 tp->intr_mask = 0xffff;
5192                 wmb();
5193                 RTL_W16(IntrMask, tp->intr_event);
5194         }
5195
5196         return work_done;
5197 }
5198
5199 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5200 {
5201         struct rtl8169_private *tp = netdev_priv(dev);
5202
5203         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5204                 return;
5205
5206         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5207         RTL_W32(RxMissed, 0);
5208 }
5209
5210 static void rtl8169_down(struct net_device *dev)
5211 {
5212         struct rtl8169_private *tp = netdev_priv(dev);
5213         void __iomem *ioaddr = tp->mmio_addr;
5214
5215         del_timer_sync(&tp->timer);
5216
5217         netif_stop_queue(dev);
5218
5219         napi_disable(&tp->napi);
5220
5221         spin_lock_irq(&tp->lock);
5222
5223         rtl8169_asic_down(ioaddr);
5224         /*
5225          * At this point device interrupts can not be enabled in any function,
5226          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5227          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5228          */
5229         rtl8169_rx_missed(dev, ioaddr);
5230
5231         spin_unlock_irq(&tp->lock);
5232
5233         synchronize_irq(dev->irq);
5234
5235         /* Give a racing hard_start_xmit a few cycles to complete. */
5236         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5237
5238         rtl8169_tx_clear(tp);
5239
5240         rtl8169_rx_clear(tp);
5241
5242         rtl_pll_power_down(tp);
5243 }
5244
5245 static int rtl8169_close(struct net_device *dev)
5246 {
5247         struct rtl8169_private *tp = netdev_priv(dev);
5248         struct pci_dev *pdev = tp->pci_dev;
5249
5250         pm_runtime_get_sync(&pdev->dev);
5251
5252         /* Update counters before going down */
5253         rtl8169_update_counters(dev);
5254
5255         rtl8169_down(dev);
5256
5257         free_irq(dev->irq, dev);
5258
5259         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5260                           tp->RxPhyAddr);
5261         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5262                           tp->TxPhyAddr);
5263         tp->TxDescArray = NULL;
5264         tp->RxDescArray = NULL;
5265
5266         pm_runtime_put_sync(&pdev->dev);
5267
5268         return 0;
5269 }
5270
5271 static void rtl_set_rx_mode(struct net_device *dev)
5272 {
5273         struct rtl8169_private *tp = netdev_priv(dev);
5274         void __iomem *ioaddr = tp->mmio_addr;
5275         unsigned long flags;
5276         u32 mc_filter[2];       /* Multicast hash filter */
5277         int rx_mode;
5278         u32 tmp = 0;
5279
5280         if (dev->flags & IFF_PROMISC) {
5281                 /* Unconditionally log net taps. */
5282                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5283                 rx_mode =
5284                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5285                     AcceptAllPhys;
5286                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5287         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5288                    (dev->flags & IFF_ALLMULTI)) {
5289                 /* Too many to filter perfectly -- accept all multicasts. */
5290                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5291                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5292         } else {
5293                 struct netdev_hw_addr *ha;
5294
5295                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5296                 mc_filter[1] = mc_filter[0] = 0;
5297                 netdev_for_each_mc_addr(ha, dev) {
5298                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5299                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5300                         rx_mode |= AcceptMulticast;
5301                 }
5302         }
5303
5304         spin_lock_irqsave(&tp->lock, flags);
5305
5306         tmp = rtl8169_rx_config | rx_mode |
5307               (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
5308
5309         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5310                 u32 data = mc_filter[0];
5311
5312                 mc_filter[0] = swab32(mc_filter[1]);
5313                 mc_filter[1] = swab32(data);
5314         }
5315
5316         RTL_W32(MAR0 + 4, mc_filter[1]);
5317         RTL_W32(MAR0 + 0, mc_filter[0]);
5318
5319         RTL_W32(RxConfig, tmp);
5320
5321         spin_unlock_irqrestore(&tp->lock, flags);
5322 }
5323
5324 /**
5325  *  rtl8169_get_stats - Get rtl8169 read/write statistics
5326  *  @dev: The Ethernet Device to get statistics for
5327  *
5328  *  Get TX/RX statistics for rtl8169
5329  */
5330 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5331 {
5332         struct rtl8169_private *tp = netdev_priv(dev);
5333         void __iomem *ioaddr = tp->mmio_addr;
5334         unsigned long flags;
5335
5336         if (netif_running(dev)) {
5337                 spin_lock_irqsave(&tp->lock, flags);
5338                 rtl8169_rx_missed(dev, ioaddr);
5339                 spin_unlock_irqrestore(&tp->lock, flags);
5340         }
5341
5342         return &dev->stats;
5343 }
5344
5345 static void rtl8169_net_suspend(struct net_device *dev)
5346 {
5347         struct rtl8169_private *tp = netdev_priv(dev);
5348
5349         if (!netif_running(dev))
5350                 return;
5351
5352         rtl_pll_power_down(tp);
5353
5354         netif_device_detach(dev);
5355         netif_stop_queue(dev);
5356 }
5357
5358 #ifdef CONFIG_PM
5359
5360 static int rtl8169_suspend(struct device *device)
5361 {
5362         struct pci_dev *pdev = to_pci_dev(device);
5363         struct net_device *dev = pci_get_drvdata(pdev);
5364
5365         rtl8169_net_suspend(dev);
5366
5367         return 0;
5368 }
5369
5370 static void __rtl8169_resume(struct net_device *dev)
5371 {
5372         struct rtl8169_private *tp = netdev_priv(dev);
5373
5374         netif_device_attach(dev);
5375
5376         rtl_pll_power_up(tp);
5377
5378         rtl8169_schedule_work(dev, rtl8169_reset_task);
5379 }
5380
5381 static int rtl8169_resume(struct device *device)
5382 {
5383         struct pci_dev *pdev = to_pci_dev(device);
5384         struct net_device *dev = pci_get_drvdata(pdev);
5385         struct rtl8169_private *tp = netdev_priv(dev);
5386
5387         rtl8169_init_phy(dev, tp);
5388
5389         if (netif_running(dev))
5390                 __rtl8169_resume(dev);
5391
5392         return 0;
5393 }
5394
5395 static int rtl8169_runtime_suspend(struct device *device)
5396 {
5397         struct pci_dev *pdev = to_pci_dev(device);
5398         struct net_device *dev = pci_get_drvdata(pdev);
5399         struct rtl8169_private *tp = netdev_priv(dev);
5400
5401         if (!tp->TxDescArray)
5402                 return 0;
5403
5404         spin_lock_irq(&tp->lock);
5405         tp->saved_wolopts = __rtl8169_get_wol(tp);
5406         __rtl8169_set_wol(tp, WAKE_ANY);
5407         spin_unlock_irq(&tp->lock);
5408
5409         rtl8169_net_suspend(dev);
5410
5411         return 0;
5412 }
5413
5414 static int rtl8169_runtime_resume(struct device *device)
5415 {
5416         struct pci_dev *pdev = to_pci_dev(device);
5417         struct net_device *dev = pci_get_drvdata(pdev);
5418         struct rtl8169_private *tp = netdev_priv(dev);
5419
5420         if (!tp->TxDescArray)
5421                 return 0;
5422
5423         spin_lock_irq(&tp->lock);
5424         __rtl8169_set_wol(tp, tp->saved_wolopts);
5425         tp->saved_wolopts = 0;
5426         spin_unlock_irq(&tp->lock);
5427
5428         rtl8169_init_phy(dev, tp);
5429
5430         __rtl8169_resume(dev);
5431
5432         return 0;
5433 }
5434
5435 static int rtl8169_runtime_idle(struct device *device)
5436 {
5437         struct pci_dev *pdev = to_pci_dev(device);
5438         struct net_device *dev = pci_get_drvdata(pdev);
5439         struct rtl8169_private *tp = netdev_priv(dev);
5440
5441         return tp->TxDescArray ? -EBUSY : 0;
5442 }
5443
5444 static const struct dev_pm_ops rtl8169_pm_ops = {
5445         .suspend                = rtl8169_suspend,
5446         .resume                 = rtl8169_resume,
5447         .freeze                 = rtl8169_suspend,
5448         .thaw                   = rtl8169_resume,
5449         .poweroff               = rtl8169_suspend,
5450         .restore                = rtl8169_resume,
5451         .runtime_suspend        = rtl8169_runtime_suspend,
5452         .runtime_resume         = rtl8169_runtime_resume,
5453         .runtime_idle           = rtl8169_runtime_idle,
5454 };
5455
5456 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5457
5458 #else /* !CONFIG_PM */
5459
5460 #define RTL8169_PM_OPS  NULL
5461
5462 #endif /* !CONFIG_PM */
5463
5464 static void rtl_shutdown(struct pci_dev *pdev)
5465 {
5466         struct net_device *dev = pci_get_drvdata(pdev);
5467         struct rtl8169_private *tp = netdev_priv(dev);
5468         void __iomem *ioaddr = tp->mmio_addr;
5469
5470         rtl8169_net_suspend(dev);
5471
5472         /* Restore original MAC address */
5473         rtl_rar_set(tp, dev->perm_addr);
5474
5475         spin_lock_irq(&tp->lock);
5476
5477         rtl8169_asic_down(ioaddr);
5478
5479         spin_unlock_irq(&tp->lock);
5480
5481         if (system_state == SYSTEM_POWER_OFF) {
5482                 /* WoL fails with some 8168 when the receiver is disabled. */
5483                 if (tp->features & RTL_FEATURE_WOL) {
5484                         pci_clear_master(pdev);
5485
5486                         RTL_W8(ChipCmd, CmdRxEnb);
5487                         /* PCI commit */
5488                         RTL_R8(ChipCmd);
5489                 }
5490
5491                 pci_wake_from_d3(pdev, true);
5492                 pci_set_power_state(pdev, PCI_D3hot);
5493         }
5494 }
5495
5496 static struct pci_driver rtl8169_pci_driver = {
5497         .name           = MODULENAME,
5498         .id_table       = rtl8169_pci_tbl,
5499         .probe          = rtl8169_init_one,
5500         .remove         = __devexit_p(rtl8169_remove_one),
5501         .shutdown       = rtl_shutdown,
5502         .driver.pm      = RTL8169_PM_OPS,
5503 };
5504
5505 static int __init rtl8169_init_module(void)
5506 {
5507         return pci_register_driver(&rtl8169_pci_driver);
5508 }
5509
5510 static void __exit rtl8169_cleanup_module(void)
5511 {
5512         pci_unregister_driver(&rtl8169_pci_driver);
5513 }
5514
5515 module_init(rtl8169_init_module);
5516 module_exit(rtl8169_cleanup_module);