r8169: merge firmware information into the chipset description data.
[linux-2.6.git] / drivers / net / r8169.c
1 /*
2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3  *
4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6  * Copyright (c) a lot of people too. Please respect their work.
7  *
8  * See MAINTAINERS file for support contact information.
9  */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29
30 #include <asm/system.h>
31 #include <asm/io.h>
32 #include <asm/irq.h>
33
34 #define RTL8169_VERSION "2.3LK-NAPI"
35 #define MODULENAME "r8169"
36 #define PFX MODULENAME ": "
37
38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
43
44 #ifdef RTL8169_DEBUG
45 #define assert(expr) \
46         if (!(expr)) {                                  \
47                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
48                 #expr,__FILE__,__func__,__LINE__);              \
49         }
50 #define dprintk(fmt, args...) \
51         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
52 #else
53 #define assert(expr) do {} while (0)
54 #define dprintk(fmt, args...)   do {} while (0)
55 #endif /* RTL8169_DEBUG */
56
57 #define R8169_MSG_DEFAULT \
58         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
59
60 #define TX_BUFFS_AVAIL(tp) \
61         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
62
63 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
64    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
65 static const int multicast_filter_limit = 32;
66
67 /* MAC address length */
68 #define MAC_ADDR_LEN    6
69
70 #define MAX_READ_REQUEST_SHIFT  12
71 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
72 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
73 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
74 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
75 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
76
77 #define R8169_REGS_SIZE         256
78 #define R8169_NAPI_WEIGHT       64
79 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
80 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
81 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
82 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
83 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
84
85 #define RTL8169_TX_TIMEOUT      (6*HZ)
86 #define RTL8169_PHY_TIMEOUT     (10*HZ)
87
88 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
89 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
90 #define RTL_EEPROM_SIG_ADDR     0x0000
91
92 /* write/read MMIO register */
93 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
94 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
95 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
96 #define RTL_R8(reg)             readb (ioaddr + (reg))
97 #define RTL_R16(reg)            readw (ioaddr + (reg))
98 #define RTL_R32(reg)            readl (ioaddr + (reg))
99
100 enum mac_version {
101         RTL_GIGA_MAC_VER_01 = 0,
102         RTL_GIGA_MAC_VER_02,
103         RTL_GIGA_MAC_VER_03,
104         RTL_GIGA_MAC_VER_04,
105         RTL_GIGA_MAC_VER_05,
106         RTL_GIGA_MAC_VER_06,
107         RTL_GIGA_MAC_VER_07,
108         RTL_GIGA_MAC_VER_08,
109         RTL_GIGA_MAC_VER_09,
110         RTL_GIGA_MAC_VER_10,
111         RTL_GIGA_MAC_VER_11,
112         RTL_GIGA_MAC_VER_12,
113         RTL_GIGA_MAC_VER_13,
114         RTL_GIGA_MAC_VER_14,
115         RTL_GIGA_MAC_VER_15,
116         RTL_GIGA_MAC_VER_16,
117         RTL_GIGA_MAC_VER_17,
118         RTL_GIGA_MAC_VER_18,
119         RTL_GIGA_MAC_VER_19,
120         RTL_GIGA_MAC_VER_20,
121         RTL_GIGA_MAC_VER_21,
122         RTL_GIGA_MAC_VER_22,
123         RTL_GIGA_MAC_VER_23,
124         RTL_GIGA_MAC_VER_24,
125         RTL_GIGA_MAC_VER_25,
126         RTL_GIGA_MAC_VER_26,
127         RTL_GIGA_MAC_VER_27,
128         RTL_GIGA_MAC_VER_28,
129         RTL_GIGA_MAC_VER_29,
130         RTL_GIGA_MAC_VER_30,
131         RTL_GIGA_MAC_VER_31,
132         RTL_GIGA_MAC_VER_32,
133         RTL_GIGA_MAC_VER_33,
134         RTL_GIGA_MAC_NONE   = 0xff,
135 };
136
137 enum rtl_tx_desc_version {
138         RTL_TD_0        = 0,
139         RTL_TD_1        = 1,
140 };
141
142 #define _R(NAME,TD,FW) \
143         { .name = NAME, .txd_version = TD, .fw_name = FW }
144
145 static const struct {
146         const char *name;
147         enum rtl_tx_desc_version txd_version;
148         const char *fw_name;
149 } rtl_chip_infos[] = {
150         /* PCI devices. */
151         [RTL_GIGA_MAC_VER_01] =
152                 _R("RTL8169",           RTL_TD_0, NULL),
153         [RTL_GIGA_MAC_VER_02] =
154                 _R("RTL8169s",          RTL_TD_0, NULL),
155         [RTL_GIGA_MAC_VER_03] =
156                 _R("RTL8110s",          RTL_TD_0, NULL),
157         [RTL_GIGA_MAC_VER_04] =
158                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL),
159         [RTL_GIGA_MAC_VER_05] =
160                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
161         [RTL_GIGA_MAC_VER_06] =
162                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
163         /* PCI-E devices. */
164         [RTL_GIGA_MAC_VER_07] =
165                 _R("RTL8102e",          RTL_TD_1, NULL),
166         [RTL_GIGA_MAC_VER_08] =
167                 _R("RTL8102e",          RTL_TD_1, NULL),
168         [RTL_GIGA_MAC_VER_09] =
169                 _R("RTL8102e",          RTL_TD_1, NULL),
170         [RTL_GIGA_MAC_VER_10] =
171                 _R("RTL8101e",          RTL_TD_0, NULL),
172         [RTL_GIGA_MAC_VER_11] =
173                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
174         [RTL_GIGA_MAC_VER_12] =
175                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
176         [RTL_GIGA_MAC_VER_13] =
177                 _R("RTL8101e",          RTL_TD_0, NULL),
178         [RTL_GIGA_MAC_VER_14] =
179                 _R("RTL8100e",          RTL_TD_0, NULL),
180         [RTL_GIGA_MAC_VER_15] =
181                 _R("RTL8100e",          RTL_TD_0, NULL),
182         [RTL_GIGA_MAC_VER_16] =
183                 _R("RTL8101e",          RTL_TD_0, NULL),
184         [RTL_GIGA_MAC_VER_17] =
185                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
186         [RTL_GIGA_MAC_VER_18] =
187                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
188         [RTL_GIGA_MAC_VER_19] =
189                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
190         [RTL_GIGA_MAC_VER_20] =
191                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
192         [RTL_GIGA_MAC_VER_21] =
193                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
194         [RTL_GIGA_MAC_VER_22] =
195                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
196         [RTL_GIGA_MAC_VER_23] =
197                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
198         [RTL_GIGA_MAC_VER_24] =
199                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
200         [RTL_GIGA_MAC_VER_25] =
201                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1),
202         [RTL_GIGA_MAC_VER_26] =
203                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2),
204         [RTL_GIGA_MAC_VER_27] =
205                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
206         [RTL_GIGA_MAC_VER_28] =
207                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
208         [RTL_GIGA_MAC_VER_29] =
209                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
210         [RTL_GIGA_MAC_VER_30] =
211                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
212         [RTL_GIGA_MAC_VER_31] =
213                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
214         [RTL_GIGA_MAC_VER_32] =
215                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1),
216         [RTL_GIGA_MAC_VER_33] =
217                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2)
218 };
219 #undef _R
220
221 enum cfg_version {
222         RTL_CFG_0 = 0x00,
223         RTL_CFG_1,
224         RTL_CFG_2
225 };
226
227 static void rtl_hw_start_8169(struct net_device *);
228 static void rtl_hw_start_8168(struct net_device *);
229 static void rtl_hw_start_8101(struct net_device *);
230
231 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
232         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
233         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
234         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
235         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
236         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
237         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
238         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
239         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
240         { PCI_VENDOR_ID_LINKSYS,                0x1032,
241                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
242         { 0x0001,                               0x8168,
243                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
244         {0,},
245 };
246
247 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
248
249 static int rx_buf_sz = 16383;
250 static int use_dac;
251 static struct {
252         u32 msg_enable;
253 } debug = { -1 };
254
255 enum rtl_registers {
256         MAC0            = 0,    /* Ethernet hardware address. */
257         MAC4            = 4,
258         MAR0            = 8,    /* Multicast filter. */
259         CounterAddrLow          = 0x10,
260         CounterAddrHigh         = 0x14,
261         TxDescStartAddrLow      = 0x20,
262         TxDescStartAddrHigh     = 0x24,
263         TxHDescStartAddrLow     = 0x28,
264         TxHDescStartAddrHigh    = 0x2c,
265         FLASH           = 0x30,
266         ERSR            = 0x36,
267         ChipCmd         = 0x37,
268         TxPoll          = 0x38,
269         IntrMask        = 0x3c,
270         IntrStatus      = 0x3e,
271         TxConfig        = 0x40,
272         RxConfig        = 0x44,
273
274 #define RTL_RX_CONFIG_MASK              0xff7e1880u
275
276         RxMissed        = 0x4c,
277         Cfg9346         = 0x50,
278         Config0         = 0x51,
279         Config1         = 0x52,
280         Config2         = 0x53,
281         Config3         = 0x54,
282         Config4         = 0x55,
283         Config5         = 0x56,
284         MultiIntr       = 0x5c,
285         PHYAR           = 0x60,
286         PHYstatus       = 0x6c,
287         RxMaxSize       = 0xda,
288         CPlusCmd        = 0xe0,
289         IntrMitigate    = 0xe2,
290         RxDescAddrLow   = 0xe4,
291         RxDescAddrHigh  = 0xe8,
292         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
293
294 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
295
296         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
297
298 #define TxPacketMax     (8064 >> 7)
299
300         FuncEvent       = 0xf0,
301         FuncEventMask   = 0xf4,
302         FuncPresetState = 0xf8,
303         FuncForceEvent  = 0xfc,
304 };
305
306 enum rtl8110_registers {
307         TBICSR                  = 0x64,
308         TBI_ANAR                = 0x68,
309         TBI_LPAR                = 0x6a,
310 };
311
312 enum rtl8168_8101_registers {
313         CSIDR                   = 0x64,
314         CSIAR                   = 0x68,
315 #define CSIAR_FLAG                      0x80000000
316 #define CSIAR_WRITE_CMD                 0x80000000
317 #define CSIAR_BYTE_ENABLE               0x0f
318 #define CSIAR_BYTE_ENABLE_SHIFT         12
319 #define CSIAR_ADDR_MASK                 0x0fff
320         PMCH                    = 0x6f,
321         EPHYAR                  = 0x80,
322 #define EPHYAR_FLAG                     0x80000000
323 #define EPHYAR_WRITE_CMD                0x80000000
324 #define EPHYAR_REG_MASK                 0x1f
325 #define EPHYAR_REG_SHIFT                16
326 #define EPHYAR_DATA_MASK                0xffff
327         DLLPR                   = 0xd0,
328 #define PM_SWITCH                       (1 << 6)
329         DBG_REG                 = 0xd1,
330 #define FIX_NAK_1                       (1 << 4)
331 #define FIX_NAK_2                       (1 << 3)
332         TWSI                    = 0xd2,
333         MCU                     = 0xd3,
334 #define EN_NDP                          (1 << 3)
335 #define EN_OOB_RESET                    (1 << 2)
336         EFUSEAR                 = 0xdc,
337 #define EFUSEAR_FLAG                    0x80000000
338 #define EFUSEAR_WRITE_CMD               0x80000000
339 #define EFUSEAR_READ_CMD                0x00000000
340 #define EFUSEAR_REG_MASK                0x03ff
341 #define EFUSEAR_REG_SHIFT               8
342 #define EFUSEAR_DATA_MASK               0xff
343 };
344
345 enum rtl8168_registers {
346         ERIDR                   = 0x70,
347         ERIAR                   = 0x74,
348 #define ERIAR_FLAG                      0x80000000
349 #define ERIAR_WRITE_CMD                 0x80000000
350 #define ERIAR_READ_CMD                  0x00000000
351 #define ERIAR_ADDR_BYTE_ALIGN           4
352 #define ERIAR_EXGMAC                    0
353 #define ERIAR_MSIX                      1
354 #define ERIAR_ASF                       2
355 #define ERIAR_TYPE_SHIFT                16
356 #define ERIAR_BYTEEN                    0x0f
357 #define ERIAR_BYTEEN_SHIFT              12
358         EPHY_RXER_NUM           = 0x7c,
359         OCPDR                   = 0xb0, /* OCP GPHY access */
360 #define OCPDR_WRITE_CMD                 0x80000000
361 #define OCPDR_READ_CMD                  0x00000000
362 #define OCPDR_REG_MASK                  0x7f
363 #define OCPDR_GPHY_REG_SHIFT            16
364 #define OCPDR_DATA_MASK                 0xffff
365         OCPAR                   = 0xb4,
366 #define OCPAR_FLAG                      0x80000000
367 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
368 #define OCPAR_GPHY_READ_CMD             0x0000f060
369         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
370         MISC                    = 0xf0, /* 8168e only. */
371 #define TXPLA_RST                       (1 << 29)
372 };
373
374 enum rtl_register_content {
375         /* InterruptStatusBits */
376         SYSErr          = 0x8000,
377         PCSTimeout      = 0x4000,
378         SWInt           = 0x0100,
379         TxDescUnavail   = 0x0080,
380         RxFIFOOver      = 0x0040,
381         LinkChg         = 0x0020,
382         RxOverflow      = 0x0010,
383         TxErr           = 0x0008,
384         TxOK            = 0x0004,
385         RxErr           = 0x0002,
386         RxOK            = 0x0001,
387
388         /* RxStatusDesc */
389         RxFOVF  = (1 << 23),
390         RxRWT   = (1 << 22),
391         RxRES   = (1 << 21),
392         RxRUNT  = (1 << 20),
393         RxCRC   = (1 << 19),
394
395         /* ChipCmdBits */
396         CmdReset        = 0x10,
397         CmdRxEnb        = 0x08,
398         CmdTxEnb        = 0x04,
399         RxBufEmpty      = 0x01,
400
401         /* TXPoll register p.5 */
402         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
403         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
404         FSWInt          = 0x01,         /* Forced software interrupt */
405
406         /* Cfg9346Bits */
407         Cfg9346_Lock    = 0x00,
408         Cfg9346_Unlock  = 0xc0,
409
410         /* rx_mode_bits */
411         AcceptErr       = 0x20,
412         AcceptRunt      = 0x10,
413         AcceptBroadcast = 0x08,
414         AcceptMulticast = 0x04,
415         AcceptMyPhys    = 0x02,
416         AcceptAllPhys   = 0x01,
417
418         /* RxConfigBits */
419         RxCfgFIFOShift  = 13,
420         RxCfgDMAShift   =  8,
421
422         /* TxConfigBits */
423         TxInterFrameGapShift = 24,
424         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
425
426         /* Config1 register p.24 */
427         LEDS1           = (1 << 7),
428         LEDS0           = (1 << 6),
429         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
430         Speed_down      = (1 << 4),
431         MEMMAP          = (1 << 3),
432         IOMAP           = (1 << 2),
433         VPD             = (1 << 1),
434         PMEnable        = (1 << 0),     /* Power Management Enable */
435
436         /* Config2 register p. 25 */
437         PCI_Clock_66MHz = 0x01,
438         PCI_Clock_33MHz = 0x00,
439
440         /* Config3 register p.25 */
441         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
442         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
443         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
444
445         /* Config5 register p.27 */
446         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
447         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
448         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
449         Spi_en          = (1 << 3),
450         LanWake         = (1 << 1),     /* LanWake enable/disable */
451         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
452
453         /* TBICSR p.28 */
454         TBIReset        = 0x80000000,
455         TBILoopback     = 0x40000000,
456         TBINwEnable     = 0x20000000,
457         TBINwRestart    = 0x10000000,
458         TBILinkOk       = 0x02000000,
459         TBINwComplete   = 0x01000000,
460
461         /* CPlusCmd p.31 */
462         EnableBist      = (1 << 15),    // 8168 8101
463         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
464         Normal_mode     = (1 << 13),    // unused
465         Force_half_dup  = (1 << 12),    // 8168 8101
466         Force_rxflow_en = (1 << 11),    // 8168 8101
467         Force_txflow_en = (1 << 10),    // 8168 8101
468         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
469         ASF             = (1 << 8),     // 8168 8101
470         PktCntrDisable  = (1 << 7),     // 8168 8101
471         Mac_dbgo_sel    = 0x001c,       // 8168
472         RxVlan          = (1 << 6),
473         RxChkSum        = (1 << 5),
474         PCIDAC          = (1 << 4),
475         PCIMulRW        = (1 << 3),
476         INTT_0          = 0x0000,       // 8168
477         INTT_1          = 0x0001,       // 8168
478         INTT_2          = 0x0002,       // 8168
479         INTT_3          = 0x0003,       // 8168
480
481         /* rtl8169_PHYstatus */
482         TBI_Enable      = 0x80,
483         TxFlowCtrl      = 0x40,
484         RxFlowCtrl      = 0x20,
485         _1000bpsF       = 0x10,
486         _100bps         = 0x08,
487         _10bps          = 0x04,
488         LinkStatus      = 0x02,
489         FullDup         = 0x01,
490
491         /* _TBICSRBit */
492         TBILinkOK       = 0x02000000,
493
494         /* DumpCounterCommand */
495         CounterDump     = 0x8,
496 };
497
498 enum rtl_desc_bit {
499         /* First doubleword. */
500         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
501         RingEnd         = (1 << 30), /* End of descriptor ring */
502         FirstFrag       = (1 << 29), /* First segment of a packet */
503         LastFrag        = (1 << 28), /* Final segment of a packet */
504 };
505
506 /* Generic case. */
507 enum rtl_tx_desc_bit {
508         /* First doubleword. */
509         TD_LSO          = (1 << 27),            /* Large Send Offload */
510 #define TD_MSS_MAX                      0x07ffu /* MSS value */
511
512         /* Second doubleword. */
513         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
514 };
515
516 /* 8169, 8168b and 810x except 8102e. */
517 enum rtl_tx_desc_bit_0 {
518         /* First doubleword. */
519 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
520         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
521         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
522         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
523 };
524
525 /* 8102e, 8168c and beyond. */
526 enum rtl_tx_desc_bit_1 {
527         /* Second doubleword. */
528 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
529         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
530         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
531         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
532 };
533
534 static const struct rtl_tx_desc_info {
535         struct {
536                 u32 udp;
537                 u32 tcp;
538         } checksum;
539         u16 mss_shift;
540         u16 opts_offset;
541 } tx_desc_info [] = {
542         [RTL_TD_0] = {
543                 .checksum = {
544                         .udp    = TD0_IP_CS | TD0_UDP_CS,
545                         .tcp    = TD0_IP_CS | TD0_TCP_CS
546                 },
547                 .mss_shift      = TD0_MSS_SHIFT,
548                 .opts_offset    = 0
549         },
550         [RTL_TD_1] = {
551                 .checksum = {
552                         .udp    = TD1_IP_CS | TD1_UDP_CS,
553                         .tcp    = TD1_IP_CS | TD1_TCP_CS
554                 },
555                 .mss_shift      = TD1_MSS_SHIFT,
556                 .opts_offset    = 1
557         }
558 };
559
560 enum rtl_rx_desc_bit {
561         /* Rx private */
562         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
563         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
564
565 #define RxProtoUDP      (PID1)
566 #define RxProtoTCP      (PID0)
567 #define RxProtoIP       (PID1 | PID0)
568 #define RxProtoMask     RxProtoIP
569
570         IPFail          = (1 << 16), /* IP checksum failed */
571         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
572         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
573         RxVlanTag       = (1 << 16), /* VLAN tag available */
574 };
575
576 #define RsvdMask        0x3fffc000
577
578 struct TxDesc {
579         __le32 opts1;
580         __le32 opts2;
581         __le64 addr;
582 };
583
584 struct RxDesc {
585         __le32 opts1;
586         __le32 opts2;
587         __le64 addr;
588 };
589
590 struct ring_info {
591         struct sk_buff  *skb;
592         u32             len;
593         u8              __pad[sizeof(void *) - sizeof(u32)];
594 };
595
596 enum features {
597         RTL_FEATURE_WOL         = (1 << 0),
598         RTL_FEATURE_MSI         = (1 << 1),
599         RTL_FEATURE_GMII        = (1 << 2),
600 };
601
602 struct rtl8169_counters {
603         __le64  tx_packets;
604         __le64  rx_packets;
605         __le64  tx_errors;
606         __le32  rx_errors;
607         __le16  rx_missed;
608         __le16  align_errors;
609         __le32  tx_one_collision;
610         __le32  tx_multi_collision;
611         __le64  rx_unicast;
612         __le64  rx_broadcast;
613         __le32  rx_multicast;
614         __le16  tx_aborted;
615         __le16  tx_underun;
616 };
617
618 struct rtl8169_private {
619         void __iomem *mmio_addr;        /* memory map physical address */
620         struct pci_dev *pci_dev;
621         struct net_device *dev;
622         struct napi_struct napi;
623         spinlock_t lock;
624         u32 msg_enable;
625         u16 txd_version;
626         u16 mac_version;
627         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
628         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
629         u32 dirty_rx;
630         u32 dirty_tx;
631         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
632         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
633         dma_addr_t TxPhyAddr;
634         dma_addr_t RxPhyAddr;
635         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
636         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
637         struct timer_list timer;
638         u16 cp_cmd;
639         u16 intr_event;
640         u16 napi_event;
641         u16 intr_mask;
642
643         struct mdio_ops {
644                 void (*write)(void __iomem *, int, int);
645                 int (*read)(void __iomem *, int);
646         } mdio_ops;
647
648         struct pll_power_ops {
649                 void (*down)(struct rtl8169_private *);
650                 void (*up)(struct rtl8169_private *);
651         } pll_power_ops;
652
653         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
654         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
655         void (*phy_reset_enable)(struct rtl8169_private *tp);
656         void (*hw_start)(struct net_device *);
657         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
658         unsigned int (*link_ok)(void __iomem *);
659         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
660         int pcie_cap;
661         struct delayed_work task;
662         unsigned features;
663
664         struct mii_if_info mii;
665         struct rtl8169_counters counters;
666         u32 saved_wolopts;
667
668         const struct firmware *fw;
669 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN);
670 };
671
672 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
673 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
674 module_param(use_dac, int, 0);
675 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
676 module_param_named(debug, debug.msg_enable, int, 0);
677 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
678 MODULE_LICENSE("GPL");
679 MODULE_VERSION(RTL8169_VERSION);
680 MODULE_FIRMWARE(FIRMWARE_8168D_1);
681 MODULE_FIRMWARE(FIRMWARE_8168D_2);
682 MODULE_FIRMWARE(FIRMWARE_8168E_1);
683 MODULE_FIRMWARE(FIRMWARE_8168E_2);
684 MODULE_FIRMWARE(FIRMWARE_8105E_1);
685
686 static int rtl8169_open(struct net_device *dev);
687 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
688                                       struct net_device *dev);
689 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
690 static int rtl8169_init_ring(struct net_device *dev);
691 static void rtl_hw_start(struct net_device *dev);
692 static int rtl8169_close(struct net_device *dev);
693 static void rtl_set_rx_mode(struct net_device *dev);
694 static void rtl8169_tx_timeout(struct net_device *dev);
695 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
696 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
697                                 void __iomem *, u32 budget);
698 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
699 static void rtl8169_down(struct net_device *dev);
700 static void rtl8169_rx_clear(struct rtl8169_private *tp);
701 static int rtl8169_poll(struct napi_struct *napi, int budget);
702
703 static const unsigned int rtl8169_rx_config =
704         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
705
706 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
707 {
708         void __iomem *ioaddr = tp->mmio_addr;
709         int i;
710
711         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
712         for (i = 0; i < 20; i++) {
713                 udelay(100);
714                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
715                         break;
716         }
717         return RTL_R32(OCPDR);
718 }
719
720 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
721 {
722         void __iomem *ioaddr = tp->mmio_addr;
723         int i;
724
725         RTL_W32(OCPDR, data);
726         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
727         for (i = 0; i < 20; i++) {
728                 udelay(100);
729                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
730                         break;
731         }
732 }
733
734 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
735 {
736         void __iomem *ioaddr = tp->mmio_addr;
737         int i;
738
739         RTL_W8(ERIDR, cmd);
740         RTL_W32(ERIAR, 0x800010e8);
741         msleep(2);
742         for (i = 0; i < 5; i++) {
743                 udelay(100);
744                 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
745                         break;
746         }
747
748         ocp_write(tp, 0x1, 0x30, 0x00000001);
749 }
750
751 #define OOB_CMD_RESET           0x00
752 #define OOB_CMD_DRIVER_START    0x05
753 #define OOB_CMD_DRIVER_STOP     0x06
754
755 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
756 {
757         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
758 }
759
760 static void rtl8168_driver_start(struct rtl8169_private *tp)
761 {
762         u16 reg;
763         int i;
764
765         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
766
767         reg = rtl8168_get_ocp_reg(tp);
768
769         for (i = 0; i < 10; i++) {
770                 msleep(10);
771                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
772                         break;
773         }
774 }
775
776 static void rtl8168_driver_stop(struct rtl8169_private *tp)
777 {
778         u16 reg;
779         int i;
780
781         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
782
783         reg = rtl8168_get_ocp_reg(tp);
784
785         for (i = 0; i < 10; i++) {
786                 msleep(10);
787                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
788                         break;
789         }
790 }
791
792 static int r8168dp_check_dash(struct rtl8169_private *tp)
793 {
794         u16 reg = rtl8168_get_ocp_reg(tp);
795
796         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
797 }
798
799 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
800 {
801         int i;
802
803         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
804
805         for (i = 20; i > 0; i--) {
806                 /*
807                  * Check if the RTL8169 has completed writing to the specified
808                  * MII register.
809                  */
810                 if (!(RTL_R32(PHYAR) & 0x80000000))
811                         break;
812                 udelay(25);
813         }
814         /*
815          * According to hardware specs a 20us delay is required after write
816          * complete indication, but before sending next command.
817          */
818         udelay(20);
819 }
820
821 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
822 {
823         int i, value = -1;
824
825         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
826
827         for (i = 20; i > 0; i--) {
828                 /*
829                  * Check if the RTL8169 has completed retrieving data from
830                  * the specified MII register.
831                  */
832                 if (RTL_R32(PHYAR) & 0x80000000) {
833                         value = RTL_R32(PHYAR) & 0xffff;
834                         break;
835                 }
836                 udelay(25);
837         }
838         /*
839          * According to hardware specs a 20us delay is required after read
840          * complete indication, but before sending next command.
841          */
842         udelay(20);
843
844         return value;
845 }
846
847 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
848 {
849         int i;
850
851         RTL_W32(OCPDR, data |
852                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
853         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
854         RTL_W32(EPHY_RXER_NUM, 0);
855
856         for (i = 0; i < 100; i++) {
857                 mdelay(1);
858                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
859                         break;
860         }
861 }
862
863 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
864 {
865         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
866                 (value & OCPDR_DATA_MASK));
867 }
868
869 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
870 {
871         int i;
872
873         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
874
875         mdelay(1);
876         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
877         RTL_W32(EPHY_RXER_NUM, 0);
878
879         for (i = 0; i < 100; i++) {
880                 mdelay(1);
881                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
882                         break;
883         }
884
885         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
886 }
887
888 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
889
890 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
891 {
892         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
893 }
894
895 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
896 {
897         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
898 }
899
900 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
901 {
902         r8168dp_2_mdio_start(ioaddr);
903
904         r8169_mdio_write(ioaddr, reg_addr, value);
905
906         r8168dp_2_mdio_stop(ioaddr);
907 }
908
909 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
910 {
911         int value;
912
913         r8168dp_2_mdio_start(ioaddr);
914
915         value = r8169_mdio_read(ioaddr, reg_addr);
916
917         r8168dp_2_mdio_stop(ioaddr);
918
919         return value;
920 }
921
922 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
923 {
924         tp->mdio_ops.write(tp->mmio_addr, location, val);
925 }
926
927 static int rtl_readphy(struct rtl8169_private *tp, int location)
928 {
929         return tp->mdio_ops.read(tp->mmio_addr, location);
930 }
931
932 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
933 {
934         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
935 }
936
937 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
938 {
939         int val;
940
941         val = rtl_readphy(tp, reg_addr);
942         rtl_writephy(tp, reg_addr, (val | p) & ~m);
943 }
944
945 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
946                            int val)
947 {
948         struct rtl8169_private *tp = netdev_priv(dev);
949
950         rtl_writephy(tp, location, val);
951 }
952
953 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
954 {
955         struct rtl8169_private *tp = netdev_priv(dev);
956
957         return rtl_readphy(tp, location);
958 }
959
960 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
961 {
962         unsigned int i;
963
964         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
965                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
966
967         for (i = 0; i < 100; i++) {
968                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
969                         break;
970                 udelay(10);
971         }
972 }
973
974 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
975 {
976         u16 value = 0xffff;
977         unsigned int i;
978
979         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
980
981         for (i = 0; i < 100; i++) {
982                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
983                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
984                         break;
985                 }
986                 udelay(10);
987         }
988
989         return value;
990 }
991
992 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
993 {
994         unsigned int i;
995
996         RTL_W32(CSIDR, value);
997         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
998                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
999
1000         for (i = 0; i < 100; i++) {
1001                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1002                         break;
1003                 udelay(10);
1004         }
1005 }
1006
1007 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1008 {
1009         u32 value = ~0x00;
1010         unsigned int i;
1011
1012         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1013                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1014
1015         for (i = 0; i < 100; i++) {
1016                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1017                         value = RTL_R32(CSIDR);
1018                         break;
1019                 }
1020                 udelay(10);
1021         }
1022
1023         return value;
1024 }
1025
1026 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1027 {
1028         u8 value = 0xff;
1029         unsigned int i;
1030
1031         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1032
1033         for (i = 0; i < 300; i++) {
1034                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1035                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1036                         break;
1037                 }
1038                 udelay(100);
1039         }
1040
1041         return value;
1042 }
1043
1044 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1045 {
1046         RTL_W16(IntrMask, 0x0000);
1047
1048         RTL_W16(IntrStatus, 0xffff);
1049 }
1050
1051 static void rtl8169_asic_down(void __iomem *ioaddr)
1052 {
1053         RTL_W8(ChipCmd, 0x00);
1054         rtl8169_irq_mask_and_ack(ioaddr);
1055         RTL_R16(CPlusCmd);
1056 }
1057
1058 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1059 {
1060         void __iomem *ioaddr = tp->mmio_addr;
1061
1062         return RTL_R32(TBICSR) & TBIReset;
1063 }
1064
1065 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1066 {
1067         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1068 }
1069
1070 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1071 {
1072         return RTL_R32(TBICSR) & TBILinkOk;
1073 }
1074
1075 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1076 {
1077         return RTL_R8(PHYstatus) & LinkStatus;
1078 }
1079
1080 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1081 {
1082         void __iomem *ioaddr = tp->mmio_addr;
1083
1084         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1085 }
1086
1087 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1088 {
1089         unsigned int val;
1090
1091         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1092         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1093 }
1094
1095 static void __rtl8169_check_link_status(struct net_device *dev,
1096                                         struct rtl8169_private *tp,
1097                                         void __iomem *ioaddr, bool pm)
1098 {
1099         unsigned long flags;
1100
1101         spin_lock_irqsave(&tp->lock, flags);
1102         if (tp->link_ok(ioaddr)) {
1103                 /* This is to cancel a scheduled suspend if there's one. */
1104                 if (pm)
1105                         pm_request_resume(&tp->pci_dev->dev);
1106                 netif_carrier_on(dev);
1107                 if (net_ratelimit())
1108                         netif_info(tp, ifup, dev, "link up\n");
1109         } else {
1110                 netif_carrier_off(dev);
1111                 netif_info(tp, ifdown, dev, "link down\n");
1112                 if (pm)
1113                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
1114         }
1115         spin_unlock_irqrestore(&tp->lock, flags);
1116 }
1117
1118 static void rtl8169_check_link_status(struct net_device *dev,
1119                                       struct rtl8169_private *tp,
1120                                       void __iomem *ioaddr)
1121 {
1122         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1123 }
1124
1125 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1126
1127 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1128 {
1129         void __iomem *ioaddr = tp->mmio_addr;
1130         u8 options;
1131         u32 wolopts = 0;
1132
1133         options = RTL_R8(Config1);
1134         if (!(options & PMEnable))
1135                 return 0;
1136
1137         options = RTL_R8(Config3);
1138         if (options & LinkUp)
1139                 wolopts |= WAKE_PHY;
1140         if (options & MagicPacket)
1141                 wolopts |= WAKE_MAGIC;
1142
1143         options = RTL_R8(Config5);
1144         if (options & UWF)
1145                 wolopts |= WAKE_UCAST;
1146         if (options & BWF)
1147                 wolopts |= WAKE_BCAST;
1148         if (options & MWF)
1149                 wolopts |= WAKE_MCAST;
1150
1151         return wolopts;
1152 }
1153
1154 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1155 {
1156         struct rtl8169_private *tp = netdev_priv(dev);
1157
1158         spin_lock_irq(&tp->lock);
1159
1160         wol->supported = WAKE_ANY;
1161         wol->wolopts = __rtl8169_get_wol(tp);
1162
1163         spin_unlock_irq(&tp->lock);
1164 }
1165
1166 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1167 {
1168         void __iomem *ioaddr = tp->mmio_addr;
1169         unsigned int i;
1170         static const struct {
1171                 u32 opt;
1172                 u16 reg;
1173                 u8  mask;
1174         } cfg[] = {
1175                 { WAKE_ANY,   Config1, PMEnable },
1176                 { WAKE_PHY,   Config3, LinkUp },
1177                 { WAKE_MAGIC, Config3, MagicPacket },
1178                 { WAKE_UCAST, Config5, UWF },
1179                 { WAKE_BCAST, Config5, BWF },
1180                 { WAKE_MCAST, Config5, MWF },
1181                 { WAKE_ANY,   Config5, LanWake }
1182         };
1183
1184         RTL_W8(Cfg9346, Cfg9346_Unlock);
1185
1186         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1187                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1188                 if (wolopts & cfg[i].opt)
1189                         options |= cfg[i].mask;
1190                 RTL_W8(cfg[i].reg, options);
1191         }
1192
1193         RTL_W8(Cfg9346, Cfg9346_Lock);
1194 }
1195
1196 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1197 {
1198         struct rtl8169_private *tp = netdev_priv(dev);
1199
1200         spin_lock_irq(&tp->lock);
1201
1202         if (wol->wolopts)
1203                 tp->features |= RTL_FEATURE_WOL;
1204         else
1205                 tp->features &= ~RTL_FEATURE_WOL;
1206         __rtl8169_set_wol(tp, wol->wolopts);
1207         spin_unlock_irq(&tp->lock);
1208
1209         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1210
1211         return 0;
1212 }
1213
1214 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1215 {
1216         return rtl_chip_infos[tp->mac_version].fw_name;
1217 }
1218
1219 static void rtl8169_get_drvinfo(struct net_device *dev,
1220                                 struct ethtool_drvinfo *info)
1221 {
1222         struct rtl8169_private *tp = netdev_priv(dev);
1223
1224         strcpy(info->driver, MODULENAME);
1225         strcpy(info->version, RTL8169_VERSION);
1226         strcpy(info->bus_info, pci_name(tp->pci_dev));
1227         strncpy(info->fw_version, IS_ERR_OR_NULL(tp->fw) ? "N/A" :
1228                 rtl_lookup_firmware_name(tp), sizeof(info->fw_version) - 1);
1229 }
1230
1231 static int rtl8169_get_regs_len(struct net_device *dev)
1232 {
1233         return R8169_REGS_SIZE;
1234 }
1235
1236 static int rtl8169_set_speed_tbi(struct net_device *dev,
1237                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1238 {
1239         struct rtl8169_private *tp = netdev_priv(dev);
1240         void __iomem *ioaddr = tp->mmio_addr;
1241         int ret = 0;
1242         u32 reg;
1243
1244         reg = RTL_R32(TBICSR);
1245         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1246             (duplex == DUPLEX_FULL)) {
1247                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1248         } else if (autoneg == AUTONEG_ENABLE)
1249                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1250         else {
1251                 netif_warn(tp, link, dev,
1252                            "incorrect speed setting refused in TBI mode\n");
1253                 ret = -EOPNOTSUPP;
1254         }
1255
1256         return ret;
1257 }
1258
1259 static int rtl8169_set_speed_xmii(struct net_device *dev,
1260                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1261 {
1262         struct rtl8169_private *tp = netdev_priv(dev);
1263         int giga_ctrl, bmcr;
1264         int rc = -EINVAL;
1265
1266         rtl_writephy(tp, 0x1f, 0x0000);
1267
1268         if (autoneg == AUTONEG_ENABLE) {
1269                 int auto_nego;
1270
1271                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1272                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1273                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1274
1275                 if (adv & ADVERTISED_10baseT_Half)
1276                         auto_nego |= ADVERTISE_10HALF;
1277                 if (adv & ADVERTISED_10baseT_Full)
1278                         auto_nego |= ADVERTISE_10FULL;
1279                 if (adv & ADVERTISED_100baseT_Half)
1280                         auto_nego |= ADVERTISE_100HALF;
1281                 if (adv & ADVERTISED_100baseT_Full)
1282                         auto_nego |= ADVERTISE_100FULL;
1283
1284                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1285
1286                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1287                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1288
1289                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1290                 if (tp->mii.supports_gmii) {
1291                         if (adv & ADVERTISED_1000baseT_Half)
1292                                 giga_ctrl |= ADVERTISE_1000HALF;
1293                         if (adv & ADVERTISED_1000baseT_Full)
1294                                 giga_ctrl |= ADVERTISE_1000FULL;
1295                 } else if (adv & (ADVERTISED_1000baseT_Half |
1296                                   ADVERTISED_1000baseT_Full)) {
1297                         netif_info(tp, link, dev,
1298                                    "PHY does not support 1000Mbps\n");
1299                         goto out;
1300                 }
1301
1302                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1303
1304                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1305                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1306         } else {
1307                 giga_ctrl = 0;
1308
1309                 if (speed == SPEED_10)
1310                         bmcr = 0;
1311                 else if (speed == SPEED_100)
1312                         bmcr = BMCR_SPEED100;
1313                 else
1314                         goto out;
1315
1316                 if (duplex == DUPLEX_FULL)
1317                         bmcr |= BMCR_FULLDPLX;
1318         }
1319
1320         rtl_writephy(tp, MII_BMCR, bmcr);
1321
1322         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1323             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1324                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1325                         rtl_writephy(tp, 0x17, 0x2138);
1326                         rtl_writephy(tp, 0x0e, 0x0260);
1327                 } else {
1328                         rtl_writephy(tp, 0x17, 0x2108);
1329                         rtl_writephy(tp, 0x0e, 0x0000);
1330                 }
1331         }
1332
1333         rc = 0;
1334 out:
1335         return rc;
1336 }
1337
1338 static int rtl8169_set_speed(struct net_device *dev,
1339                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1340 {
1341         struct rtl8169_private *tp = netdev_priv(dev);
1342         int ret;
1343
1344         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1345         if (ret < 0)
1346                 goto out;
1347
1348         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1349             (advertising & ADVERTISED_1000baseT_Full)) {
1350                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1351         }
1352 out:
1353         return ret;
1354 }
1355
1356 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1357 {
1358         struct rtl8169_private *tp = netdev_priv(dev);
1359         unsigned long flags;
1360         int ret;
1361
1362         del_timer_sync(&tp->timer);
1363
1364         spin_lock_irqsave(&tp->lock, flags);
1365         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1366                                 cmd->duplex, cmd->advertising);
1367         spin_unlock_irqrestore(&tp->lock, flags);
1368
1369         return ret;
1370 }
1371
1372 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1373 {
1374         if (dev->mtu > TD_MSS_MAX)
1375                 features &= ~NETIF_F_ALL_TSO;
1376
1377         return features;
1378 }
1379
1380 static int rtl8169_set_features(struct net_device *dev, u32 features)
1381 {
1382         struct rtl8169_private *tp = netdev_priv(dev);
1383         void __iomem *ioaddr = tp->mmio_addr;
1384         unsigned long flags;
1385
1386         spin_lock_irqsave(&tp->lock, flags);
1387
1388         if (features & NETIF_F_RXCSUM)
1389                 tp->cp_cmd |= RxChkSum;
1390         else
1391                 tp->cp_cmd &= ~RxChkSum;
1392
1393         if (dev->features & NETIF_F_HW_VLAN_RX)
1394                 tp->cp_cmd |= RxVlan;
1395         else
1396                 tp->cp_cmd &= ~RxVlan;
1397
1398         RTL_W16(CPlusCmd, tp->cp_cmd);
1399         RTL_R16(CPlusCmd);
1400
1401         spin_unlock_irqrestore(&tp->lock, flags);
1402
1403         return 0;
1404 }
1405
1406 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1407                                       struct sk_buff *skb)
1408 {
1409         return (vlan_tx_tag_present(skb)) ?
1410                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1411 }
1412
1413 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1414 {
1415         u32 opts2 = le32_to_cpu(desc->opts2);
1416
1417         if (opts2 & RxVlanTag)
1418                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1419
1420         desc->opts2 = 0;
1421 }
1422
1423 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1424 {
1425         struct rtl8169_private *tp = netdev_priv(dev);
1426         void __iomem *ioaddr = tp->mmio_addr;
1427         u32 status;
1428
1429         cmd->supported =
1430                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1431         cmd->port = PORT_FIBRE;
1432         cmd->transceiver = XCVR_INTERNAL;
1433
1434         status = RTL_R32(TBICSR);
1435         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1436         cmd->autoneg = !!(status & TBINwEnable);
1437
1438         ethtool_cmd_speed_set(cmd, SPEED_1000);
1439         cmd->duplex = DUPLEX_FULL; /* Always set */
1440
1441         return 0;
1442 }
1443
1444 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1445 {
1446         struct rtl8169_private *tp = netdev_priv(dev);
1447
1448         return mii_ethtool_gset(&tp->mii, cmd);
1449 }
1450
1451 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1452 {
1453         struct rtl8169_private *tp = netdev_priv(dev);
1454         unsigned long flags;
1455         int rc;
1456
1457         spin_lock_irqsave(&tp->lock, flags);
1458
1459         rc = tp->get_settings(dev, cmd);
1460
1461         spin_unlock_irqrestore(&tp->lock, flags);
1462         return rc;
1463 }
1464
1465 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1466                              void *p)
1467 {
1468         struct rtl8169_private *tp = netdev_priv(dev);
1469         unsigned long flags;
1470
1471         if (regs->len > R8169_REGS_SIZE)
1472                 regs->len = R8169_REGS_SIZE;
1473
1474         spin_lock_irqsave(&tp->lock, flags);
1475         memcpy_fromio(p, tp->mmio_addr, regs->len);
1476         spin_unlock_irqrestore(&tp->lock, flags);
1477 }
1478
1479 static u32 rtl8169_get_msglevel(struct net_device *dev)
1480 {
1481         struct rtl8169_private *tp = netdev_priv(dev);
1482
1483         return tp->msg_enable;
1484 }
1485
1486 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1487 {
1488         struct rtl8169_private *tp = netdev_priv(dev);
1489
1490         tp->msg_enable = value;
1491 }
1492
1493 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1494         "tx_packets",
1495         "rx_packets",
1496         "tx_errors",
1497         "rx_errors",
1498         "rx_missed",
1499         "align_errors",
1500         "tx_single_collisions",
1501         "tx_multi_collisions",
1502         "unicast",
1503         "broadcast",
1504         "multicast",
1505         "tx_aborted",
1506         "tx_underrun",
1507 };
1508
1509 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1510 {
1511         switch (sset) {
1512         case ETH_SS_STATS:
1513                 return ARRAY_SIZE(rtl8169_gstrings);
1514         default:
1515                 return -EOPNOTSUPP;
1516         }
1517 }
1518
1519 static void rtl8169_update_counters(struct net_device *dev)
1520 {
1521         struct rtl8169_private *tp = netdev_priv(dev);
1522         void __iomem *ioaddr = tp->mmio_addr;
1523         struct device *d = &tp->pci_dev->dev;
1524         struct rtl8169_counters *counters;
1525         dma_addr_t paddr;
1526         u32 cmd;
1527         int wait = 1000;
1528
1529         /*
1530          * Some chips are unable to dump tally counters when the receiver
1531          * is disabled.
1532          */
1533         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1534                 return;
1535
1536         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1537         if (!counters)
1538                 return;
1539
1540         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1541         cmd = (u64)paddr & DMA_BIT_MASK(32);
1542         RTL_W32(CounterAddrLow, cmd);
1543         RTL_W32(CounterAddrLow, cmd | CounterDump);
1544
1545         while (wait--) {
1546                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1547                         memcpy(&tp->counters, counters, sizeof(*counters));
1548                         break;
1549                 }
1550                 udelay(10);
1551         }
1552
1553         RTL_W32(CounterAddrLow, 0);
1554         RTL_W32(CounterAddrHigh, 0);
1555
1556         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1557 }
1558
1559 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1560                                       struct ethtool_stats *stats, u64 *data)
1561 {
1562         struct rtl8169_private *tp = netdev_priv(dev);
1563
1564         ASSERT_RTNL();
1565
1566         rtl8169_update_counters(dev);
1567
1568         data[0] = le64_to_cpu(tp->counters.tx_packets);
1569         data[1] = le64_to_cpu(tp->counters.rx_packets);
1570         data[2] = le64_to_cpu(tp->counters.tx_errors);
1571         data[3] = le32_to_cpu(tp->counters.rx_errors);
1572         data[4] = le16_to_cpu(tp->counters.rx_missed);
1573         data[5] = le16_to_cpu(tp->counters.align_errors);
1574         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1575         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1576         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1577         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1578         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1579         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1580         data[12] = le16_to_cpu(tp->counters.tx_underun);
1581 }
1582
1583 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1584 {
1585         switch(stringset) {
1586         case ETH_SS_STATS:
1587                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1588                 break;
1589         }
1590 }
1591
1592 static const struct ethtool_ops rtl8169_ethtool_ops = {
1593         .get_drvinfo            = rtl8169_get_drvinfo,
1594         .get_regs_len           = rtl8169_get_regs_len,
1595         .get_link               = ethtool_op_get_link,
1596         .get_settings           = rtl8169_get_settings,
1597         .set_settings           = rtl8169_set_settings,
1598         .get_msglevel           = rtl8169_get_msglevel,
1599         .set_msglevel           = rtl8169_set_msglevel,
1600         .get_regs               = rtl8169_get_regs,
1601         .get_wol                = rtl8169_get_wol,
1602         .set_wol                = rtl8169_set_wol,
1603         .get_strings            = rtl8169_get_strings,
1604         .get_sset_count         = rtl8169_get_sset_count,
1605         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1606 };
1607
1608 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1609                                     void __iomem *ioaddr)
1610 {
1611         /*
1612          * The driver currently handles the 8168Bf and the 8168Be identically
1613          * but they can be identified more specifically through the test below
1614          * if needed:
1615          *
1616          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1617          *
1618          * Same thing for the 8101Eb and the 8101Ec:
1619          *
1620          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1621          */
1622         static const struct {
1623                 u32 mask;
1624                 u32 val;
1625                 int mac_version;
1626         } mac_info[] = {
1627                 /* 8168E family. */
1628                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1629                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1630                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1631
1632                 /* 8168D family. */
1633                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1634                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1635                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1636
1637                 /* 8168DP family. */
1638                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1639                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1640                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1641
1642                 /* 8168C family. */
1643                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1644                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1645                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1646                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1647                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1648                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1649                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1650                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1651                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1652
1653                 /* 8168B family. */
1654                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1655                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1656                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1657                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1658
1659                 /* 8101 family. */
1660                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1661                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1662                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1663                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1664                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1665                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1666                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1667                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1668                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1669                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1670                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1671                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1672                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1673                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1674                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1675                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1676                 /* FIXME: where did these entries come from ? -- FR */
1677                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1678                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1679
1680                 /* 8110 family. */
1681                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1682                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1683                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1684                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1685                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1686                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1687
1688                 /* Catch-all */
1689                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1690         }, *p = mac_info;
1691         u32 reg;
1692
1693         reg = RTL_R32(TxConfig);
1694         while ((reg & p->mask) != p->val)
1695                 p++;
1696         tp->mac_version = p->mac_version;
1697 }
1698
1699 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1700 {
1701         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1702 }
1703
1704 struct phy_reg {
1705         u16 reg;
1706         u16 val;
1707 };
1708
1709 static void rtl_writephy_batch(struct rtl8169_private *tp,
1710                                const struct phy_reg *regs, int len)
1711 {
1712         while (len-- > 0) {
1713                 rtl_writephy(tp, regs->reg, regs->val);
1714                 regs++;
1715         }
1716 }
1717
1718 #define PHY_READ                0x00000000
1719 #define PHY_DATA_OR             0x10000000
1720 #define PHY_DATA_AND            0x20000000
1721 #define PHY_BJMPN               0x30000000
1722 #define PHY_READ_EFUSE          0x40000000
1723 #define PHY_READ_MAC_BYTE       0x50000000
1724 #define PHY_WRITE_MAC_BYTE      0x60000000
1725 #define PHY_CLEAR_READCOUNT     0x70000000
1726 #define PHY_WRITE               0x80000000
1727 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1728 #define PHY_COMP_EQ_SKIPN       0xa0000000
1729 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1730 #define PHY_WRITE_PREVIOUS      0xc0000000
1731 #define PHY_SKIPN               0xd0000000
1732 #define PHY_DELAY_MS            0xe0000000
1733 #define PHY_WRITE_ERI_WORD      0xf0000000
1734
1735 static void
1736 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1737 {
1738         __le32 *phytable = (__le32 *)fw->data;
1739         struct net_device *dev = tp->dev;
1740         size_t index, fw_size = fw->size / sizeof(*phytable);
1741         u32 predata, count;
1742
1743         if (fw->size % sizeof(*phytable)) {
1744                 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1745                 return;
1746         }
1747
1748         for (index = 0; index < fw_size; index++) {
1749                 u32 action = le32_to_cpu(phytable[index]);
1750                 u32 regno = (action & 0x0fff0000) >> 16;
1751
1752                 switch(action & 0xf0000000) {
1753                 case PHY_READ:
1754                 case PHY_DATA_OR:
1755                 case PHY_DATA_AND:
1756                 case PHY_READ_EFUSE:
1757                 case PHY_CLEAR_READCOUNT:
1758                 case PHY_WRITE:
1759                 case PHY_WRITE_PREVIOUS:
1760                 case PHY_DELAY_MS:
1761                         break;
1762
1763                 case PHY_BJMPN:
1764                         if (regno > index) {
1765                                 netif_err(tp, probe, tp->dev,
1766                                           "Out of range of firmware\n");
1767                                 return;
1768                         }
1769                         break;
1770                 case PHY_READCOUNT_EQ_SKIP:
1771                         if (index + 2 >= fw_size) {
1772                                 netif_err(tp, probe, tp->dev,
1773                                           "Out of range of firmware\n");
1774                                 return;
1775                         }
1776                         break;
1777                 case PHY_COMP_EQ_SKIPN:
1778                 case PHY_COMP_NEQ_SKIPN:
1779                 case PHY_SKIPN:
1780                         if (index + 1 + regno >= fw_size) {
1781                                 netif_err(tp, probe, tp->dev,
1782                                           "Out of range of firmware\n");
1783                                 return;
1784                         }
1785                         break;
1786
1787                 case PHY_READ_MAC_BYTE:
1788                 case PHY_WRITE_MAC_BYTE:
1789                 case PHY_WRITE_ERI_WORD:
1790                 default:
1791                         netif_err(tp, probe, tp->dev,
1792                                   "Invalid action 0x%08x\n", action);
1793                         return;
1794                 }
1795         }
1796
1797         predata = 0;
1798         count = 0;
1799
1800         for (index = 0; index < fw_size; ) {
1801                 u32 action = le32_to_cpu(phytable[index]);
1802                 u32 data = action & 0x0000ffff;
1803                 u32 regno = (action & 0x0fff0000) >> 16;
1804
1805                 if (!action)
1806                         break;
1807
1808                 switch(action & 0xf0000000) {
1809                 case PHY_READ:
1810                         predata = rtl_readphy(tp, regno);
1811                         count++;
1812                         index++;
1813                         break;
1814                 case PHY_DATA_OR:
1815                         predata |= data;
1816                         index++;
1817                         break;
1818                 case PHY_DATA_AND:
1819                         predata &= data;
1820                         index++;
1821                         break;
1822                 case PHY_BJMPN:
1823                         index -= regno;
1824                         break;
1825                 case PHY_READ_EFUSE:
1826                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1827                         index++;
1828                         break;
1829                 case PHY_CLEAR_READCOUNT:
1830                         count = 0;
1831                         index++;
1832                         break;
1833                 case PHY_WRITE:
1834                         rtl_writephy(tp, regno, data);
1835                         index++;
1836                         break;
1837                 case PHY_READCOUNT_EQ_SKIP:
1838                         index += (count == data) ? 2 : 1;
1839                         break;
1840                 case PHY_COMP_EQ_SKIPN:
1841                         if (predata == data)
1842                                 index += regno;
1843                         index++;
1844                         break;
1845                 case PHY_COMP_NEQ_SKIPN:
1846                         if (predata != data)
1847                                 index += regno;
1848                         index++;
1849                         break;
1850                 case PHY_WRITE_PREVIOUS:
1851                         rtl_writephy(tp, regno, predata);
1852                         index++;
1853                         break;
1854                 case PHY_SKIPN:
1855                         index += regno + 1;
1856                         break;
1857                 case PHY_DELAY_MS:
1858                         mdelay(data);
1859                         index++;
1860                         break;
1861
1862                 case PHY_READ_MAC_BYTE:
1863                 case PHY_WRITE_MAC_BYTE:
1864                 case PHY_WRITE_ERI_WORD:
1865                 default:
1866                         BUG();
1867                 }
1868         }
1869 }
1870
1871 static void rtl_release_firmware(struct rtl8169_private *tp)
1872 {
1873         if (!IS_ERR_OR_NULL(tp->fw))
1874                 release_firmware(tp->fw);
1875         tp->fw = RTL_FIRMWARE_UNKNOWN;
1876 }
1877
1878 static void rtl_apply_firmware(struct rtl8169_private *tp)
1879 {
1880         const struct firmware *fw = tp->fw;
1881
1882         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1883         if (!IS_ERR_OR_NULL(fw))
1884                 rtl_phy_write_fw(tp, fw);
1885 }
1886
1887 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1888 {
1889         if (rtl_readphy(tp, reg) != val)
1890                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1891         else
1892                 rtl_apply_firmware(tp);
1893 }
1894
1895 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1896 {
1897         static const struct phy_reg phy_reg_init[] = {
1898                 { 0x1f, 0x0001 },
1899                 { 0x06, 0x006e },
1900                 { 0x08, 0x0708 },
1901                 { 0x15, 0x4000 },
1902                 { 0x18, 0x65c7 },
1903
1904                 { 0x1f, 0x0001 },
1905                 { 0x03, 0x00a1 },
1906                 { 0x02, 0x0008 },
1907                 { 0x01, 0x0120 },
1908                 { 0x00, 0x1000 },
1909                 { 0x04, 0x0800 },
1910                 { 0x04, 0x0000 },
1911
1912                 { 0x03, 0xff41 },
1913                 { 0x02, 0xdf60 },
1914                 { 0x01, 0x0140 },
1915                 { 0x00, 0x0077 },
1916                 { 0x04, 0x7800 },
1917                 { 0x04, 0x7000 },
1918
1919                 { 0x03, 0x802f },
1920                 { 0x02, 0x4f02 },
1921                 { 0x01, 0x0409 },
1922                 { 0x00, 0xf0f9 },
1923                 { 0x04, 0x9800 },
1924                 { 0x04, 0x9000 },
1925
1926                 { 0x03, 0xdf01 },
1927                 { 0x02, 0xdf20 },
1928                 { 0x01, 0xff95 },
1929                 { 0x00, 0xba00 },
1930                 { 0x04, 0xa800 },
1931                 { 0x04, 0xa000 },
1932
1933                 { 0x03, 0xff41 },
1934                 { 0x02, 0xdf20 },
1935                 { 0x01, 0x0140 },
1936                 { 0x00, 0x00bb },
1937                 { 0x04, 0xb800 },
1938                 { 0x04, 0xb000 },
1939
1940                 { 0x03, 0xdf41 },
1941                 { 0x02, 0xdc60 },
1942                 { 0x01, 0x6340 },
1943                 { 0x00, 0x007d },
1944                 { 0x04, 0xd800 },
1945                 { 0x04, 0xd000 },
1946
1947                 { 0x03, 0xdf01 },
1948                 { 0x02, 0xdf20 },
1949                 { 0x01, 0x100a },
1950                 { 0x00, 0xa0ff },
1951                 { 0x04, 0xf800 },
1952                 { 0x04, 0xf000 },
1953
1954                 { 0x1f, 0x0000 },
1955                 { 0x0b, 0x0000 },
1956                 { 0x00, 0x9200 }
1957         };
1958
1959         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1960 }
1961
1962 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1963 {
1964         static const struct phy_reg phy_reg_init[] = {
1965                 { 0x1f, 0x0002 },
1966                 { 0x01, 0x90d0 },
1967                 { 0x1f, 0x0000 }
1968         };
1969
1970         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1971 }
1972
1973 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1974 {
1975         struct pci_dev *pdev = tp->pci_dev;
1976         u16 vendor_id, device_id;
1977
1978         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1979         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1980
1981         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1982                 return;
1983
1984         rtl_writephy(tp, 0x1f, 0x0001);
1985         rtl_writephy(tp, 0x10, 0xf01b);
1986         rtl_writephy(tp, 0x1f, 0x0000);
1987 }
1988
1989 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
1990 {
1991         static const struct phy_reg phy_reg_init[] = {
1992                 { 0x1f, 0x0001 },
1993                 { 0x04, 0x0000 },
1994                 { 0x03, 0x00a1 },
1995                 { 0x02, 0x0008 },
1996                 { 0x01, 0x0120 },
1997                 { 0x00, 0x1000 },
1998                 { 0x04, 0x0800 },
1999                 { 0x04, 0x9000 },
2000                 { 0x03, 0x802f },
2001                 { 0x02, 0x4f02 },
2002                 { 0x01, 0x0409 },
2003                 { 0x00, 0xf099 },
2004                 { 0x04, 0x9800 },
2005                 { 0x04, 0xa000 },
2006                 { 0x03, 0xdf01 },
2007                 { 0x02, 0xdf20 },
2008                 { 0x01, 0xff95 },
2009                 { 0x00, 0xba00 },
2010                 { 0x04, 0xa800 },
2011                 { 0x04, 0xf000 },
2012                 { 0x03, 0xdf01 },
2013                 { 0x02, 0xdf20 },
2014                 { 0x01, 0x101a },
2015                 { 0x00, 0xa0ff },
2016                 { 0x04, 0xf800 },
2017                 { 0x04, 0x0000 },
2018                 { 0x1f, 0x0000 },
2019
2020                 { 0x1f, 0x0001 },
2021                 { 0x10, 0xf41b },
2022                 { 0x14, 0xfb54 },
2023                 { 0x18, 0xf5c7 },
2024                 { 0x1f, 0x0000 },
2025
2026                 { 0x1f, 0x0001 },
2027                 { 0x17, 0x0cc0 },
2028                 { 0x1f, 0x0000 }
2029         };
2030
2031         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2032
2033         rtl8169scd_hw_phy_config_quirk(tp);
2034 }
2035
2036 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2037 {
2038         static const struct phy_reg phy_reg_init[] = {
2039                 { 0x1f, 0x0001 },
2040                 { 0x04, 0x0000 },
2041                 { 0x03, 0x00a1 },
2042                 { 0x02, 0x0008 },
2043                 { 0x01, 0x0120 },
2044                 { 0x00, 0x1000 },
2045                 { 0x04, 0x0800 },
2046                 { 0x04, 0x9000 },
2047                 { 0x03, 0x802f },
2048                 { 0x02, 0x4f02 },
2049                 { 0x01, 0x0409 },
2050                 { 0x00, 0xf099 },
2051                 { 0x04, 0x9800 },
2052                 { 0x04, 0xa000 },
2053                 { 0x03, 0xdf01 },
2054                 { 0x02, 0xdf20 },
2055                 { 0x01, 0xff95 },
2056                 { 0x00, 0xba00 },
2057                 { 0x04, 0xa800 },
2058                 { 0x04, 0xf000 },
2059                 { 0x03, 0xdf01 },
2060                 { 0x02, 0xdf20 },
2061                 { 0x01, 0x101a },
2062                 { 0x00, 0xa0ff },
2063                 { 0x04, 0xf800 },
2064                 { 0x04, 0x0000 },
2065                 { 0x1f, 0x0000 },
2066
2067                 { 0x1f, 0x0001 },
2068                 { 0x0b, 0x8480 },
2069                 { 0x1f, 0x0000 },
2070
2071                 { 0x1f, 0x0001 },
2072                 { 0x18, 0x67c7 },
2073                 { 0x04, 0x2000 },
2074                 { 0x03, 0x002f },
2075                 { 0x02, 0x4360 },
2076                 { 0x01, 0x0109 },
2077                 { 0x00, 0x3022 },
2078                 { 0x04, 0x2800 },
2079                 { 0x1f, 0x0000 },
2080
2081                 { 0x1f, 0x0001 },
2082                 { 0x17, 0x0cc0 },
2083                 { 0x1f, 0x0000 }
2084         };
2085
2086         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2087 }
2088
2089 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2090 {
2091         static const struct phy_reg phy_reg_init[] = {
2092                 { 0x10, 0xf41b },
2093                 { 0x1f, 0x0000 }
2094         };
2095
2096         rtl_writephy(tp, 0x1f, 0x0001);
2097         rtl_patchphy(tp, 0x16, 1 << 0);
2098
2099         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2100 }
2101
2102 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2103 {
2104         static const struct phy_reg phy_reg_init[] = {
2105                 { 0x1f, 0x0001 },
2106                 { 0x10, 0xf41b },
2107                 { 0x1f, 0x0000 }
2108         };
2109
2110         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2111 }
2112
2113 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2114 {
2115         static const struct phy_reg phy_reg_init[] = {
2116                 { 0x1f, 0x0000 },
2117                 { 0x1d, 0x0f00 },
2118                 { 0x1f, 0x0002 },
2119                 { 0x0c, 0x1ec8 },
2120                 { 0x1f, 0x0000 }
2121         };
2122
2123         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2124 }
2125
2126 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2127 {
2128         static const struct phy_reg phy_reg_init[] = {
2129                 { 0x1f, 0x0001 },
2130                 { 0x1d, 0x3d98 },
2131                 { 0x1f, 0x0000 }
2132         };
2133
2134         rtl_writephy(tp, 0x1f, 0x0000);
2135         rtl_patchphy(tp, 0x14, 1 << 5);
2136         rtl_patchphy(tp, 0x0d, 1 << 5);
2137
2138         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2139 }
2140
2141 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2142 {
2143         static const struct phy_reg phy_reg_init[] = {
2144                 { 0x1f, 0x0001 },
2145                 { 0x12, 0x2300 },
2146                 { 0x1f, 0x0002 },
2147                 { 0x00, 0x88d4 },
2148                 { 0x01, 0x82b1 },
2149                 { 0x03, 0x7002 },
2150                 { 0x08, 0x9e30 },
2151                 { 0x09, 0x01f0 },
2152                 { 0x0a, 0x5500 },
2153                 { 0x0c, 0x00c8 },
2154                 { 0x1f, 0x0003 },
2155                 { 0x12, 0xc096 },
2156                 { 0x16, 0x000a },
2157                 { 0x1f, 0x0000 },
2158                 { 0x1f, 0x0000 },
2159                 { 0x09, 0x2000 },
2160                 { 0x09, 0x0000 }
2161         };
2162
2163         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2164
2165         rtl_patchphy(tp, 0x14, 1 << 5);
2166         rtl_patchphy(tp, 0x0d, 1 << 5);
2167         rtl_writephy(tp, 0x1f, 0x0000);
2168 }
2169
2170 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2171 {
2172         static const struct phy_reg phy_reg_init[] = {
2173                 { 0x1f, 0x0001 },
2174                 { 0x12, 0x2300 },
2175                 { 0x03, 0x802f },
2176                 { 0x02, 0x4f02 },
2177                 { 0x01, 0x0409 },
2178                 { 0x00, 0xf099 },
2179                 { 0x04, 0x9800 },
2180                 { 0x04, 0x9000 },
2181                 { 0x1d, 0x3d98 },
2182                 { 0x1f, 0x0002 },
2183                 { 0x0c, 0x7eb8 },
2184                 { 0x06, 0x0761 },
2185                 { 0x1f, 0x0003 },
2186                 { 0x16, 0x0f0a },
2187                 { 0x1f, 0x0000 }
2188         };
2189
2190         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2191
2192         rtl_patchphy(tp, 0x16, 1 << 0);
2193         rtl_patchphy(tp, 0x14, 1 << 5);
2194         rtl_patchphy(tp, 0x0d, 1 << 5);
2195         rtl_writephy(tp, 0x1f, 0x0000);
2196 }
2197
2198 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2199 {
2200         static const struct phy_reg phy_reg_init[] = {
2201                 { 0x1f, 0x0001 },
2202                 { 0x12, 0x2300 },
2203                 { 0x1d, 0x3d98 },
2204                 { 0x1f, 0x0002 },
2205                 { 0x0c, 0x7eb8 },
2206                 { 0x06, 0x5461 },
2207                 { 0x1f, 0x0003 },
2208                 { 0x16, 0x0f0a },
2209                 { 0x1f, 0x0000 }
2210         };
2211
2212         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2213
2214         rtl_patchphy(tp, 0x16, 1 << 0);
2215         rtl_patchphy(tp, 0x14, 1 << 5);
2216         rtl_patchphy(tp, 0x0d, 1 << 5);
2217         rtl_writephy(tp, 0x1f, 0x0000);
2218 }
2219
2220 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2221 {
2222         rtl8168c_3_hw_phy_config(tp);
2223 }
2224
2225 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2226 {
2227         static const struct phy_reg phy_reg_init_0[] = {
2228                 /* Channel Estimation */
2229                 { 0x1f, 0x0001 },
2230                 { 0x06, 0x4064 },
2231                 { 0x07, 0x2863 },
2232                 { 0x08, 0x059c },
2233                 { 0x09, 0x26b4 },
2234                 { 0x0a, 0x6a19 },
2235                 { 0x0b, 0xdcc8 },
2236                 { 0x10, 0xf06d },
2237                 { 0x14, 0x7f68 },
2238                 { 0x18, 0x7fd9 },
2239                 { 0x1c, 0xf0ff },
2240                 { 0x1d, 0x3d9c },
2241                 { 0x1f, 0x0003 },
2242                 { 0x12, 0xf49f },
2243                 { 0x13, 0x070b },
2244                 { 0x1a, 0x05ad },
2245                 { 0x14, 0x94c0 },
2246
2247                 /*
2248                  * Tx Error Issue
2249                  * Enhance line driver power
2250                  */
2251                 { 0x1f, 0x0002 },
2252                 { 0x06, 0x5561 },
2253                 { 0x1f, 0x0005 },
2254                 { 0x05, 0x8332 },
2255                 { 0x06, 0x5561 },
2256
2257                 /*
2258                  * Can not link to 1Gbps with bad cable
2259                  * Decrease SNR threshold form 21.07dB to 19.04dB
2260                  */
2261                 { 0x1f, 0x0001 },
2262                 { 0x17, 0x0cc0 },
2263
2264                 { 0x1f, 0x0000 },
2265                 { 0x0d, 0xf880 }
2266         };
2267         void __iomem *ioaddr = tp->mmio_addr;
2268
2269         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2270
2271         /*
2272          * Rx Error Issue
2273          * Fine Tune Switching regulator parameter
2274          */
2275         rtl_writephy(tp, 0x1f, 0x0002);
2276         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2277         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2278
2279         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2280                 static const struct phy_reg phy_reg_init[] = {
2281                         { 0x1f, 0x0002 },
2282                         { 0x05, 0x669a },
2283                         { 0x1f, 0x0005 },
2284                         { 0x05, 0x8330 },
2285                         { 0x06, 0x669a },
2286                         { 0x1f, 0x0002 }
2287                 };
2288                 int val;
2289
2290                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2291
2292                 val = rtl_readphy(tp, 0x0d);
2293
2294                 if ((val & 0x00ff) != 0x006c) {
2295                         static const u32 set[] = {
2296                                 0x0065, 0x0066, 0x0067, 0x0068,
2297                                 0x0069, 0x006a, 0x006b, 0x006c
2298                         };
2299                         int i;
2300
2301                         rtl_writephy(tp, 0x1f, 0x0002);
2302
2303                         val &= 0xff00;
2304                         for (i = 0; i < ARRAY_SIZE(set); i++)
2305                                 rtl_writephy(tp, 0x0d, val | set[i]);
2306                 }
2307         } else {
2308                 static const struct phy_reg phy_reg_init[] = {
2309                         { 0x1f, 0x0002 },
2310                         { 0x05, 0x6662 },
2311                         { 0x1f, 0x0005 },
2312                         { 0x05, 0x8330 },
2313                         { 0x06, 0x6662 }
2314                 };
2315
2316                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2317         }
2318
2319         /* RSET couple improve */
2320         rtl_writephy(tp, 0x1f, 0x0002);
2321         rtl_patchphy(tp, 0x0d, 0x0300);
2322         rtl_patchphy(tp, 0x0f, 0x0010);
2323
2324         /* Fine tune PLL performance */
2325         rtl_writephy(tp, 0x1f, 0x0002);
2326         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2327         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2328
2329         rtl_writephy(tp, 0x1f, 0x0005);
2330         rtl_writephy(tp, 0x05, 0x001b);
2331
2332         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2333
2334         rtl_writephy(tp, 0x1f, 0x0000);
2335 }
2336
2337 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2338 {
2339         static const struct phy_reg phy_reg_init_0[] = {
2340                 /* Channel Estimation */
2341                 { 0x1f, 0x0001 },
2342                 { 0x06, 0x4064 },
2343                 { 0x07, 0x2863 },
2344                 { 0x08, 0x059c },
2345                 { 0x09, 0x26b4 },
2346                 { 0x0a, 0x6a19 },
2347                 { 0x0b, 0xdcc8 },
2348                 { 0x10, 0xf06d },
2349                 { 0x14, 0x7f68 },
2350                 { 0x18, 0x7fd9 },
2351                 { 0x1c, 0xf0ff },
2352                 { 0x1d, 0x3d9c },
2353                 { 0x1f, 0x0003 },
2354                 { 0x12, 0xf49f },
2355                 { 0x13, 0x070b },
2356                 { 0x1a, 0x05ad },
2357                 { 0x14, 0x94c0 },
2358
2359                 /*
2360                  * Tx Error Issue
2361                  * Enhance line driver power
2362                  */
2363                 { 0x1f, 0x0002 },
2364                 { 0x06, 0x5561 },
2365                 { 0x1f, 0x0005 },
2366                 { 0x05, 0x8332 },
2367                 { 0x06, 0x5561 },
2368
2369                 /*
2370                  * Can not link to 1Gbps with bad cable
2371                  * Decrease SNR threshold form 21.07dB to 19.04dB
2372                  */
2373                 { 0x1f, 0x0001 },
2374                 { 0x17, 0x0cc0 },
2375
2376                 { 0x1f, 0x0000 },
2377                 { 0x0d, 0xf880 }
2378         };
2379         void __iomem *ioaddr = tp->mmio_addr;
2380
2381         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2382
2383         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2384                 static const struct phy_reg phy_reg_init[] = {
2385                         { 0x1f, 0x0002 },
2386                         { 0x05, 0x669a },
2387                         { 0x1f, 0x0005 },
2388                         { 0x05, 0x8330 },
2389                         { 0x06, 0x669a },
2390
2391                         { 0x1f, 0x0002 }
2392                 };
2393                 int val;
2394
2395                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2396
2397                 val = rtl_readphy(tp, 0x0d);
2398                 if ((val & 0x00ff) != 0x006c) {
2399                         static const u32 set[] = {
2400                                 0x0065, 0x0066, 0x0067, 0x0068,
2401                                 0x0069, 0x006a, 0x006b, 0x006c
2402                         };
2403                         int i;
2404
2405                         rtl_writephy(tp, 0x1f, 0x0002);
2406
2407                         val &= 0xff00;
2408                         for (i = 0; i < ARRAY_SIZE(set); i++)
2409                                 rtl_writephy(tp, 0x0d, val | set[i]);
2410                 }
2411         } else {
2412                 static const struct phy_reg phy_reg_init[] = {
2413                         { 0x1f, 0x0002 },
2414                         { 0x05, 0x2642 },
2415                         { 0x1f, 0x0005 },
2416                         { 0x05, 0x8330 },
2417                         { 0x06, 0x2642 }
2418                 };
2419
2420                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2421         }
2422
2423         /* Fine tune PLL performance */
2424         rtl_writephy(tp, 0x1f, 0x0002);
2425         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2426         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2427
2428         /* Switching regulator Slew rate */
2429         rtl_writephy(tp, 0x1f, 0x0002);
2430         rtl_patchphy(tp, 0x0f, 0x0017);
2431
2432         rtl_writephy(tp, 0x1f, 0x0005);
2433         rtl_writephy(tp, 0x05, 0x001b);
2434
2435         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2436
2437         rtl_writephy(tp, 0x1f, 0x0000);
2438 }
2439
2440 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2441 {
2442         static const struct phy_reg phy_reg_init[] = {
2443                 { 0x1f, 0x0002 },
2444                 { 0x10, 0x0008 },
2445                 { 0x0d, 0x006c },
2446
2447                 { 0x1f, 0x0000 },
2448                 { 0x0d, 0xf880 },
2449
2450                 { 0x1f, 0x0001 },
2451                 { 0x17, 0x0cc0 },
2452
2453                 { 0x1f, 0x0001 },
2454                 { 0x0b, 0xa4d8 },
2455                 { 0x09, 0x281c },
2456                 { 0x07, 0x2883 },
2457                 { 0x0a, 0x6b35 },
2458                 { 0x1d, 0x3da4 },
2459                 { 0x1c, 0xeffd },
2460                 { 0x14, 0x7f52 },
2461                 { 0x18, 0x7fc6 },
2462                 { 0x08, 0x0601 },
2463                 { 0x06, 0x4063 },
2464                 { 0x10, 0xf074 },
2465                 { 0x1f, 0x0003 },
2466                 { 0x13, 0x0789 },
2467                 { 0x12, 0xf4bd },
2468                 { 0x1a, 0x04fd },
2469                 { 0x14, 0x84b0 },
2470                 { 0x1f, 0x0000 },
2471                 { 0x00, 0x9200 },
2472
2473                 { 0x1f, 0x0005 },
2474                 { 0x01, 0x0340 },
2475                 { 0x1f, 0x0001 },
2476                 { 0x04, 0x4000 },
2477                 { 0x03, 0x1d21 },
2478                 { 0x02, 0x0c32 },
2479                 { 0x01, 0x0200 },
2480                 { 0x00, 0x5554 },
2481                 { 0x04, 0x4800 },
2482                 { 0x04, 0x4000 },
2483                 { 0x04, 0xf000 },
2484                 { 0x03, 0xdf01 },
2485                 { 0x02, 0xdf20 },
2486                 { 0x01, 0x101a },
2487                 { 0x00, 0xa0ff },
2488                 { 0x04, 0xf800 },
2489                 { 0x04, 0xf000 },
2490                 { 0x1f, 0x0000 },
2491
2492                 { 0x1f, 0x0007 },
2493                 { 0x1e, 0x0023 },
2494                 { 0x16, 0x0000 },
2495                 { 0x1f, 0x0000 }
2496         };
2497
2498         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2499 }
2500
2501 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2502 {
2503         static const struct phy_reg phy_reg_init[] = {
2504                 { 0x1f, 0x0001 },
2505                 { 0x17, 0x0cc0 },
2506
2507                 { 0x1f, 0x0007 },
2508                 { 0x1e, 0x002d },
2509                 { 0x18, 0x0040 },
2510                 { 0x1f, 0x0000 }
2511         };
2512
2513         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2514         rtl_patchphy(tp, 0x0d, 1 << 5);
2515 }
2516
2517 static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2518 {
2519         static const struct phy_reg phy_reg_init[] = {
2520                 /* Enable Delay cap */
2521                 { 0x1f, 0x0005 },
2522                 { 0x05, 0x8b80 },
2523                 { 0x06, 0xc896 },
2524                 { 0x1f, 0x0000 },
2525
2526                 /* Channel estimation fine tune */
2527                 { 0x1f, 0x0001 },
2528                 { 0x0b, 0x6c20 },
2529                 { 0x07, 0x2872 },
2530                 { 0x1c, 0xefff },
2531                 { 0x1f, 0x0003 },
2532                 { 0x14, 0x6420 },
2533                 { 0x1f, 0x0000 },
2534
2535                 /* Update PFM & 10M TX idle timer */
2536                 { 0x1f, 0x0007 },
2537                 { 0x1e, 0x002f },
2538                 { 0x15, 0x1919 },
2539                 { 0x1f, 0x0000 },
2540
2541                 { 0x1f, 0x0007 },
2542                 { 0x1e, 0x00ac },
2543                 { 0x18, 0x0006 },
2544                 { 0x1f, 0x0000 }
2545         };
2546
2547         rtl_apply_firmware(tp);
2548
2549         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2550
2551         /* DCO enable for 10M IDLE Power */
2552         rtl_writephy(tp, 0x1f, 0x0007);
2553         rtl_writephy(tp, 0x1e, 0x0023);
2554         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2555         rtl_writephy(tp, 0x1f, 0x0000);
2556
2557         /* For impedance matching */
2558         rtl_writephy(tp, 0x1f, 0x0002);
2559         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2560         rtl_writephy(tp, 0x1f, 0x0000);
2561
2562         /* PHY auto speed down */
2563         rtl_writephy(tp, 0x1f, 0x0007);
2564         rtl_writephy(tp, 0x1e, 0x002d);
2565         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2566         rtl_writephy(tp, 0x1f, 0x0000);
2567         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2568
2569         rtl_writephy(tp, 0x1f, 0x0005);
2570         rtl_writephy(tp, 0x05, 0x8b86);
2571         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2572         rtl_writephy(tp, 0x1f, 0x0000);
2573
2574         rtl_writephy(tp, 0x1f, 0x0005);
2575         rtl_writephy(tp, 0x05, 0x8b85);
2576         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2577         rtl_writephy(tp, 0x1f, 0x0007);
2578         rtl_writephy(tp, 0x1e, 0x0020);
2579         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2580         rtl_writephy(tp, 0x1f, 0x0006);
2581         rtl_writephy(tp, 0x00, 0x5a00);
2582         rtl_writephy(tp, 0x1f, 0x0000);
2583         rtl_writephy(tp, 0x0d, 0x0007);
2584         rtl_writephy(tp, 0x0e, 0x003c);
2585         rtl_writephy(tp, 0x0d, 0x4007);
2586         rtl_writephy(tp, 0x0e, 0x0000);
2587         rtl_writephy(tp, 0x0d, 0x0000);
2588 }
2589
2590 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2591 {
2592         static const struct phy_reg phy_reg_init[] = {
2593                 { 0x1f, 0x0003 },
2594                 { 0x08, 0x441d },
2595                 { 0x01, 0x9100 },
2596                 { 0x1f, 0x0000 }
2597         };
2598
2599         rtl_writephy(tp, 0x1f, 0x0000);
2600         rtl_patchphy(tp, 0x11, 1 << 12);
2601         rtl_patchphy(tp, 0x19, 1 << 13);
2602         rtl_patchphy(tp, 0x10, 1 << 15);
2603
2604         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2605 }
2606
2607 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2608 {
2609         static const struct phy_reg phy_reg_init[] = {
2610                 { 0x1f, 0x0005 },
2611                 { 0x1a, 0x0000 },
2612                 { 0x1f, 0x0000 },
2613
2614                 { 0x1f, 0x0004 },
2615                 { 0x1c, 0x0000 },
2616                 { 0x1f, 0x0000 },
2617
2618                 { 0x1f, 0x0001 },
2619                 { 0x15, 0x7701 },
2620                 { 0x1f, 0x0000 }
2621         };
2622
2623         /* Disable ALDPS before ram code */
2624         rtl_writephy(tp, 0x1f, 0x0000);
2625         rtl_writephy(tp, 0x18, 0x0310);
2626         msleep(100);
2627
2628         rtl_apply_firmware(tp);
2629
2630         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2631 }
2632
2633 static void rtl_hw_phy_config(struct net_device *dev)
2634 {
2635         struct rtl8169_private *tp = netdev_priv(dev);
2636
2637         rtl8169_print_mac_version(tp);
2638
2639         switch (tp->mac_version) {
2640         case RTL_GIGA_MAC_VER_01:
2641                 break;
2642         case RTL_GIGA_MAC_VER_02:
2643         case RTL_GIGA_MAC_VER_03:
2644                 rtl8169s_hw_phy_config(tp);
2645                 break;
2646         case RTL_GIGA_MAC_VER_04:
2647                 rtl8169sb_hw_phy_config(tp);
2648                 break;
2649         case RTL_GIGA_MAC_VER_05:
2650                 rtl8169scd_hw_phy_config(tp);
2651                 break;
2652         case RTL_GIGA_MAC_VER_06:
2653                 rtl8169sce_hw_phy_config(tp);
2654                 break;
2655         case RTL_GIGA_MAC_VER_07:
2656         case RTL_GIGA_MAC_VER_08:
2657         case RTL_GIGA_MAC_VER_09:
2658                 rtl8102e_hw_phy_config(tp);
2659                 break;
2660         case RTL_GIGA_MAC_VER_11:
2661                 rtl8168bb_hw_phy_config(tp);
2662                 break;
2663         case RTL_GIGA_MAC_VER_12:
2664                 rtl8168bef_hw_phy_config(tp);
2665                 break;
2666         case RTL_GIGA_MAC_VER_17:
2667                 rtl8168bef_hw_phy_config(tp);
2668                 break;
2669         case RTL_GIGA_MAC_VER_18:
2670                 rtl8168cp_1_hw_phy_config(tp);
2671                 break;
2672         case RTL_GIGA_MAC_VER_19:
2673                 rtl8168c_1_hw_phy_config(tp);
2674                 break;
2675         case RTL_GIGA_MAC_VER_20:
2676                 rtl8168c_2_hw_phy_config(tp);
2677                 break;
2678         case RTL_GIGA_MAC_VER_21:
2679                 rtl8168c_3_hw_phy_config(tp);
2680                 break;
2681         case RTL_GIGA_MAC_VER_22:
2682                 rtl8168c_4_hw_phy_config(tp);
2683                 break;
2684         case RTL_GIGA_MAC_VER_23:
2685         case RTL_GIGA_MAC_VER_24:
2686                 rtl8168cp_2_hw_phy_config(tp);
2687                 break;
2688         case RTL_GIGA_MAC_VER_25:
2689                 rtl8168d_1_hw_phy_config(tp);
2690                 break;
2691         case RTL_GIGA_MAC_VER_26:
2692                 rtl8168d_2_hw_phy_config(tp);
2693                 break;
2694         case RTL_GIGA_MAC_VER_27:
2695                 rtl8168d_3_hw_phy_config(tp);
2696                 break;
2697         case RTL_GIGA_MAC_VER_28:
2698                 rtl8168d_4_hw_phy_config(tp);
2699                 break;
2700         case RTL_GIGA_MAC_VER_29:
2701         case RTL_GIGA_MAC_VER_30:
2702                 rtl8105e_hw_phy_config(tp);
2703                 break;
2704         case RTL_GIGA_MAC_VER_31:
2705                 /* None. */
2706                 break;
2707         case RTL_GIGA_MAC_VER_32:
2708         case RTL_GIGA_MAC_VER_33:
2709                 rtl8168e_hw_phy_config(tp);
2710                 break;
2711
2712         default:
2713                 break;
2714         }
2715 }
2716
2717 static void rtl8169_phy_timer(unsigned long __opaque)
2718 {
2719         struct net_device *dev = (struct net_device *)__opaque;
2720         struct rtl8169_private *tp = netdev_priv(dev);
2721         struct timer_list *timer = &tp->timer;
2722         void __iomem *ioaddr = tp->mmio_addr;
2723         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2724
2725         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2726
2727         spin_lock_irq(&tp->lock);
2728
2729         if (tp->phy_reset_pending(tp)) {
2730                 /*
2731                  * A busy loop could burn quite a few cycles on nowadays CPU.
2732                  * Let's delay the execution of the timer for a few ticks.
2733                  */
2734                 timeout = HZ/10;
2735                 goto out_mod_timer;
2736         }
2737
2738         if (tp->link_ok(ioaddr))
2739                 goto out_unlock;
2740
2741         netif_warn(tp, link, dev, "PHY reset until link up\n");
2742
2743         tp->phy_reset_enable(tp);
2744
2745 out_mod_timer:
2746         mod_timer(timer, jiffies + timeout);
2747 out_unlock:
2748         spin_unlock_irq(&tp->lock);
2749 }
2750
2751 #ifdef CONFIG_NET_POLL_CONTROLLER
2752 /*
2753  * Polling 'interrupt' - used by things like netconsole to send skbs
2754  * without having to re-enable interrupts. It's not called while
2755  * the interrupt routine is executing.
2756  */
2757 static void rtl8169_netpoll(struct net_device *dev)
2758 {
2759         struct rtl8169_private *tp = netdev_priv(dev);
2760         struct pci_dev *pdev = tp->pci_dev;
2761
2762         disable_irq(pdev->irq);
2763         rtl8169_interrupt(pdev->irq, dev);
2764         enable_irq(pdev->irq);
2765 }
2766 #endif
2767
2768 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2769                                   void __iomem *ioaddr)
2770 {
2771         iounmap(ioaddr);
2772         pci_release_regions(pdev);
2773         pci_clear_mwi(pdev);
2774         pci_disable_device(pdev);
2775         free_netdev(dev);
2776 }
2777
2778 static void rtl8169_phy_reset(struct net_device *dev,
2779                               struct rtl8169_private *tp)
2780 {
2781         unsigned int i;
2782
2783         tp->phy_reset_enable(tp);
2784         for (i = 0; i < 100; i++) {
2785                 if (!tp->phy_reset_pending(tp))
2786                         return;
2787                 msleep(1);
2788         }
2789         netif_err(tp, link, dev, "PHY reset failed\n");
2790 }
2791
2792 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2793 {
2794         void __iomem *ioaddr = tp->mmio_addr;
2795
2796         rtl_hw_phy_config(dev);
2797
2798         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2799                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2800                 RTL_W8(0x82, 0x01);
2801         }
2802
2803         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2804
2805         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2806                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2807
2808         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2809                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2810                 RTL_W8(0x82, 0x01);
2811                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2812                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2813         }
2814
2815         rtl8169_phy_reset(dev, tp);
2816
2817         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2818                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2819                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2820                           (tp->mii.supports_gmii ?
2821                            ADVERTISED_1000baseT_Half |
2822                            ADVERTISED_1000baseT_Full : 0));
2823
2824         if (RTL_R8(PHYstatus) & TBI_Enable)
2825                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2826 }
2827
2828 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2829 {
2830         void __iomem *ioaddr = tp->mmio_addr;
2831         u32 high;
2832         u32 low;
2833
2834         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2835         high = addr[4] | (addr[5] << 8);
2836
2837         spin_lock_irq(&tp->lock);
2838
2839         RTL_W8(Cfg9346, Cfg9346_Unlock);
2840
2841         RTL_W32(MAC4, high);
2842         RTL_R32(MAC4);
2843
2844         RTL_W32(MAC0, low);
2845         RTL_R32(MAC0);
2846
2847         RTL_W8(Cfg9346, Cfg9346_Lock);
2848
2849         spin_unlock_irq(&tp->lock);
2850 }
2851
2852 static int rtl_set_mac_address(struct net_device *dev, void *p)
2853 {
2854         struct rtl8169_private *tp = netdev_priv(dev);
2855         struct sockaddr *addr = p;
2856
2857         if (!is_valid_ether_addr(addr->sa_data))
2858                 return -EADDRNOTAVAIL;
2859
2860         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2861
2862         rtl_rar_set(tp, dev->dev_addr);
2863
2864         return 0;
2865 }
2866
2867 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2868 {
2869         struct rtl8169_private *tp = netdev_priv(dev);
2870         struct mii_ioctl_data *data = if_mii(ifr);
2871
2872         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2873 }
2874
2875 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2876                           struct mii_ioctl_data *data, int cmd)
2877 {
2878         switch (cmd) {
2879         case SIOCGMIIPHY:
2880                 data->phy_id = 32; /* Internal PHY */
2881                 return 0;
2882
2883         case SIOCGMIIREG:
2884                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2885                 return 0;
2886
2887         case SIOCSMIIREG:
2888                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2889                 return 0;
2890         }
2891         return -EOPNOTSUPP;
2892 }
2893
2894 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2895 {
2896         return -EOPNOTSUPP;
2897 }
2898
2899 static const struct rtl_cfg_info {
2900         void (*hw_start)(struct net_device *);
2901         unsigned int region;
2902         unsigned int align;
2903         u16 intr_event;
2904         u16 napi_event;
2905         unsigned features;
2906         u8 default_ver;
2907 } rtl_cfg_infos [] = {
2908         [RTL_CFG_0] = {
2909                 .hw_start       = rtl_hw_start_8169,
2910                 .region         = 1,
2911                 .align          = 0,
2912                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2913                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2914                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2915                 .features       = RTL_FEATURE_GMII,
2916                 .default_ver    = RTL_GIGA_MAC_VER_01,
2917         },
2918         [RTL_CFG_1] = {
2919                 .hw_start       = rtl_hw_start_8168,
2920                 .region         = 2,
2921                 .align          = 8,
2922                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2923                                   TxErr | TxOK | RxOK | RxErr,
2924                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
2925                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2926                 .default_ver    = RTL_GIGA_MAC_VER_11,
2927         },
2928         [RTL_CFG_2] = {
2929                 .hw_start       = rtl_hw_start_8101,
2930                 .region         = 2,
2931                 .align          = 8,
2932                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2933                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2934                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2935                 .features       = RTL_FEATURE_MSI,
2936                 .default_ver    = RTL_GIGA_MAC_VER_13,
2937         }
2938 };
2939
2940 /* Cfg9346_Unlock assumed. */
2941 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2942                             const struct rtl_cfg_info *cfg)
2943 {
2944         unsigned msi = 0;
2945         u8 cfg2;
2946
2947         cfg2 = RTL_R8(Config2) & ~MSIEnable;
2948         if (cfg->features & RTL_FEATURE_MSI) {
2949                 if (pci_enable_msi(pdev)) {
2950                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2951                 } else {
2952                         cfg2 |= MSIEnable;
2953                         msi = RTL_FEATURE_MSI;
2954                 }
2955         }
2956         RTL_W8(Config2, cfg2);
2957         return msi;
2958 }
2959
2960 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2961 {
2962         if (tp->features & RTL_FEATURE_MSI) {
2963                 pci_disable_msi(pdev);
2964                 tp->features &= ~RTL_FEATURE_MSI;
2965         }
2966 }
2967
2968 static const struct net_device_ops rtl8169_netdev_ops = {
2969         .ndo_open               = rtl8169_open,
2970         .ndo_stop               = rtl8169_close,
2971         .ndo_get_stats          = rtl8169_get_stats,
2972         .ndo_start_xmit         = rtl8169_start_xmit,
2973         .ndo_tx_timeout         = rtl8169_tx_timeout,
2974         .ndo_validate_addr      = eth_validate_addr,
2975         .ndo_change_mtu         = rtl8169_change_mtu,
2976         .ndo_fix_features       = rtl8169_fix_features,
2977         .ndo_set_features       = rtl8169_set_features,
2978         .ndo_set_mac_address    = rtl_set_mac_address,
2979         .ndo_do_ioctl           = rtl8169_ioctl,
2980         .ndo_set_multicast_list = rtl_set_rx_mode,
2981 #ifdef CONFIG_NET_POLL_CONTROLLER
2982         .ndo_poll_controller    = rtl8169_netpoll,
2983 #endif
2984
2985 };
2986
2987 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2988 {
2989         struct mdio_ops *ops = &tp->mdio_ops;
2990
2991         switch (tp->mac_version) {
2992         case RTL_GIGA_MAC_VER_27:
2993                 ops->write      = r8168dp_1_mdio_write;
2994                 ops->read       = r8168dp_1_mdio_read;
2995                 break;
2996         case RTL_GIGA_MAC_VER_28:
2997         case RTL_GIGA_MAC_VER_31:
2998                 ops->write      = r8168dp_2_mdio_write;
2999                 ops->read       = r8168dp_2_mdio_read;
3000                 break;
3001         default:
3002                 ops->write      = r8169_mdio_write;
3003                 ops->read       = r8169_mdio_read;
3004                 break;
3005         }
3006 }
3007
3008 static void r810x_phy_power_down(struct rtl8169_private *tp)
3009 {
3010         rtl_writephy(tp, 0x1f, 0x0000);
3011         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3012 }
3013
3014 static void r810x_phy_power_up(struct rtl8169_private *tp)
3015 {
3016         rtl_writephy(tp, 0x1f, 0x0000);
3017         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3018 }
3019
3020 static void r810x_pll_power_down(struct rtl8169_private *tp)
3021 {
3022         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3023                 rtl_writephy(tp, 0x1f, 0x0000);
3024                 rtl_writephy(tp, MII_BMCR, 0x0000);
3025                 return;
3026         }
3027
3028         r810x_phy_power_down(tp);
3029 }
3030
3031 static void r810x_pll_power_up(struct rtl8169_private *tp)
3032 {
3033         r810x_phy_power_up(tp);
3034 }
3035
3036 static void r8168_phy_power_up(struct rtl8169_private *tp)
3037 {
3038         rtl_writephy(tp, 0x1f, 0x0000);
3039         switch (tp->mac_version) {
3040         case RTL_GIGA_MAC_VER_11:
3041         case RTL_GIGA_MAC_VER_12:
3042         case RTL_GIGA_MAC_VER_17:
3043         case RTL_GIGA_MAC_VER_18:
3044         case RTL_GIGA_MAC_VER_19:
3045         case RTL_GIGA_MAC_VER_20:
3046         case RTL_GIGA_MAC_VER_21:
3047         case RTL_GIGA_MAC_VER_22:
3048         case RTL_GIGA_MAC_VER_23:
3049         case RTL_GIGA_MAC_VER_24:
3050         case RTL_GIGA_MAC_VER_25:
3051         case RTL_GIGA_MAC_VER_26:
3052         case RTL_GIGA_MAC_VER_27:
3053         case RTL_GIGA_MAC_VER_28:
3054         case RTL_GIGA_MAC_VER_31:
3055                 rtl_writephy(tp, 0x0e, 0x0000);
3056                 break;
3057         default:
3058                 break;
3059         }
3060         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3061 }
3062
3063 static void r8168_phy_power_down(struct rtl8169_private *tp)
3064 {
3065         rtl_writephy(tp, 0x1f, 0x0000);
3066         switch (tp->mac_version) {
3067         case RTL_GIGA_MAC_VER_32:
3068         case RTL_GIGA_MAC_VER_33:
3069                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3070                 break;
3071
3072         case RTL_GIGA_MAC_VER_11:
3073         case RTL_GIGA_MAC_VER_12:
3074         case RTL_GIGA_MAC_VER_17:
3075         case RTL_GIGA_MAC_VER_18:
3076         case RTL_GIGA_MAC_VER_19:
3077         case RTL_GIGA_MAC_VER_20:
3078         case RTL_GIGA_MAC_VER_21:
3079         case RTL_GIGA_MAC_VER_22:
3080         case RTL_GIGA_MAC_VER_23:
3081         case RTL_GIGA_MAC_VER_24:
3082         case RTL_GIGA_MAC_VER_25:
3083         case RTL_GIGA_MAC_VER_26:
3084         case RTL_GIGA_MAC_VER_27:
3085         case RTL_GIGA_MAC_VER_28:
3086         case RTL_GIGA_MAC_VER_31:
3087                 rtl_writephy(tp, 0x0e, 0x0200);
3088         default:
3089                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3090                 break;
3091         }
3092 }
3093
3094 static void r8168_pll_power_down(struct rtl8169_private *tp)
3095 {
3096         void __iomem *ioaddr = tp->mmio_addr;
3097
3098         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3099              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3100              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3101             r8168dp_check_dash(tp)) {
3102                 return;
3103         }
3104
3105         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3106              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3107             (RTL_R16(CPlusCmd) & ASF)) {
3108                 return;
3109         }
3110
3111         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3112             tp->mac_version == RTL_GIGA_MAC_VER_33)
3113                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3114
3115         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3116                 rtl_writephy(tp, 0x1f, 0x0000);
3117                 rtl_writephy(tp, MII_BMCR, 0x0000);
3118
3119                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3120                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3121                 return;
3122         }
3123
3124         r8168_phy_power_down(tp);
3125
3126         switch (tp->mac_version) {
3127         case RTL_GIGA_MAC_VER_25:
3128         case RTL_GIGA_MAC_VER_26:
3129         case RTL_GIGA_MAC_VER_27:
3130         case RTL_GIGA_MAC_VER_28:
3131         case RTL_GIGA_MAC_VER_31:
3132         case RTL_GIGA_MAC_VER_32:
3133         case RTL_GIGA_MAC_VER_33:
3134                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3135                 break;
3136         }
3137 }
3138
3139 static void r8168_pll_power_up(struct rtl8169_private *tp)
3140 {
3141         void __iomem *ioaddr = tp->mmio_addr;
3142
3143         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3144              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3145              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3146             r8168dp_check_dash(tp)) {
3147                 return;
3148         }
3149
3150         switch (tp->mac_version) {
3151         case RTL_GIGA_MAC_VER_25:
3152         case RTL_GIGA_MAC_VER_26:
3153         case RTL_GIGA_MAC_VER_27:
3154         case RTL_GIGA_MAC_VER_28:
3155         case RTL_GIGA_MAC_VER_31:
3156         case RTL_GIGA_MAC_VER_32:
3157         case RTL_GIGA_MAC_VER_33:
3158                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3159                 break;
3160         }
3161
3162         r8168_phy_power_up(tp);
3163 }
3164
3165 static void rtl_pll_power_op(struct rtl8169_private *tp,
3166                              void (*op)(struct rtl8169_private *))
3167 {
3168         if (op)
3169                 op(tp);
3170 }
3171
3172 static void rtl_pll_power_down(struct rtl8169_private *tp)
3173 {
3174         rtl_pll_power_op(tp, tp->pll_power_ops.down);
3175 }
3176
3177 static void rtl_pll_power_up(struct rtl8169_private *tp)
3178 {
3179         rtl_pll_power_op(tp, tp->pll_power_ops.up);
3180 }
3181
3182 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3183 {
3184         struct pll_power_ops *ops = &tp->pll_power_ops;
3185
3186         switch (tp->mac_version) {
3187         case RTL_GIGA_MAC_VER_07:
3188         case RTL_GIGA_MAC_VER_08:
3189         case RTL_GIGA_MAC_VER_09:
3190         case RTL_GIGA_MAC_VER_10:
3191         case RTL_GIGA_MAC_VER_16:
3192         case RTL_GIGA_MAC_VER_29:
3193         case RTL_GIGA_MAC_VER_30:
3194                 ops->down       = r810x_pll_power_down;
3195                 ops->up         = r810x_pll_power_up;
3196                 break;
3197
3198         case RTL_GIGA_MAC_VER_11:
3199         case RTL_GIGA_MAC_VER_12:
3200         case RTL_GIGA_MAC_VER_17:
3201         case RTL_GIGA_MAC_VER_18:
3202         case RTL_GIGA_MAC_VER_19:
3203         case RTL_GIGA_MAC_VER_20:
3204         case RTL_GIGA_MAC_VER_21:
3205         case RTL_GIGA_MAC_VER_22:
3206         case RTL_GIGA_MAC_VER_23:
3207         case RTL_GIGA_MAC_VER_24:
3208         case RTL_GIGA_MAC_VER_25:
3209         case RTL_GIGA_MAC_VER_26:
3210         case RTL_GIGA_MAC_VER_27:
3211         case RTL_GIGA_MAC_VER_28:
3212         case RTL_GIGA_MAC_VER_31:
3213         case RTL_GIGA_MAC_VER_32:
3214         case RTL_GIGA_MAC_VER_33:
3215                 ops->down       = r8168_pll_power_down;
3216                 ops->up         = r8168_pll_power_up;
3217                 break;
3218
3219         default:
3220                 ops->down       = NULL;
3221                 ops->up         = NULL;
3222                 break;
3223         }
3224 }
3225
3226 static void rtl_hw_reset(struct rtl8169_private *tp)
3227 {
3228         void __iomem *ioaddr = tp->mmio_addr;
3229         int i;
3230
3231         /* Soft reset the chip. */
3232         RTL_W8(ChipCmd, CmdReset);
3233
3234         /* Check that the chip has finished the reset. */
3235         for (i = 0; i < 100; i++) {
3236                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3237                         break;
3238                 msleep_interruptible(1);
3239         }
3240 }
3241
3242 static int __devinit
3243 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3244 {
3245         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3246         const unsigned int region = cfg->region;
3247         struct rtl8169_private *tp;
3248         struct mii_if_info *mii;
3249         struct net_device *dev;
3250         void __iomem *ioaddr;
3251         int chipset, i;
3252         int rc;
3253
3254         if (netif_msg_drv(&debug)) {
3255                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3256                        MODULENAME, RTL8169_VERSION);
3257         }
3258
3259         dev = alloc_etherdev(sizeof (*tp));
3260         if (!dev) {
3261                 if (netif_msg_drv(&debug))
3262                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3263                 rc = -ENOMEM;
3264                 goto out;
3265         }
3266
3267         SET_NETDEV_DEV(dev, &pdev->dev);
3268         dev->netdev_ops = &rtl8169_netdev_ops;
3269         tp = netdev_priv(dev);
3270         tp->dev = dev;
3271         tp->pci_dev = pdev;
3272         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3273
3274         mii = &tp->mii;
3275         mii->dev = dev;
3276         mii->mdio_read = rtl_mdio_read;
3277         mii->mdio_write = rtl_mdio_write;
3278         mii->phy_id_mask = 0x1f;
3279         mii->reg_num_mask = 0x1f;
3280         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3281
3282         /* disable ASPM completely as that cause random device stop working
3283          * problems as well as full system hangs for some PCIe devices users */
3284         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3285                                      PCIE_LINK_STATE_CLKPM);
3286
3287         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3288         rc = pci_enable_device(pdev);
3289         if (rc < 0) {
3290                 netif_err(tp, probe, dev, "enable failure\n");
3291                 goto err_out_free_dev_1;
3292         }
3293
3294         if (pci_set_mwi(pdev) < 0)
3295                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3296
3297         /* make sure PCI base addr 1 is MMIO */
3298         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3299                 netif_err(tp, probe, dev,
3300                           "region #%d not an MMIO resource, aborting\n",
3301                           region);
3302                 rc = -ENODEV;
3303                 goto err_out_mwi_2;
3304         }
3305
3306         /* check for weird/broken PCI region reporting */
3307         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3308                 netif_err(tp, probe, dev,
3309                           "Invalid PCI region size(s), aborting\n");
3310                 rc = -ENODEV;
3311                 goto err_out_mwi_2;
3312         }
3313
3314         rc = pci_request_regions(pdev, MODULENAME);
3315         if (rc < 0) {
3316                 netif_err(tp, probe, dev, "could not request regions\n");
3317                 goto err_out_mwi_2;
3318         }
3319
3320         tp->cp_cmd = RxChkSum;
3321
3322         if ((sizeof(dma_addr_t) > 4) &&
3323             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3324                 tp->cp_cmd |= PCIDAC;
3325                 dev->features |= NETIF_F_HIGHDMA;
3326         } else {
3327                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3328                 if (rc < 0) {
3329                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3330                         goto err_out_free_res_3;
3331                 }
3332         }
3333
3334         /* ioremap MMIO region */
3335         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3336         if (!ioaddr) {
3337                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3338                 rc = -EIO;
3339                 goto err_out_free_res_3;
3340         }
3341         tp->mmio_addr = ioaddr;
3342
3343         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3344         if (!tp->pcie_cap)
3345                 netif_info(tp, probe, dev, "no PCI Express capability\n");
3346
3347         RTL_W16(IntrMask, 0x0000);
3348
3349         rtl_hw_reset(tp);
3350
3351         RTL_W16(IntrStatus, 0xffff);
3352
3353         pci_set_master(pdev);
3354
3355         /* Identify chip attached to board */
3356         rtl8169_get_mac_version(tp, ioaddr);
3357
3358         /*
3359          * Pretend we are using VLANs; This bypasses a nasty bug where
3360          * Interrupts stop flowing on high load on 8110SCd controllers.
3361          */
3362         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3363                 tp->cp_cmd |= RxVlan;
3364
3365         rtl_init_mdio_ops(tp);
3366         rtl_init_pll_power_ops(tp);
3367
3368         /* Use appropriate default if unknown */
3369         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3370                 netif_notice(tp, probe, dev,
3371                              "unknown MAC, using family default\n");
3372                 tp->mac_version = cfg->default_ver;
3373         }
3374
3375         rtl8169_print_mac_version(tp);
3376
3377         chipset = tp->mac_version;
3378         tp->txd_version = rtl_chip_infos[chipset].txd_version;
3379
3380         RTL_W8(Cfg9346, Cfg9346_Unlock);
3381         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3382         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3383         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3384                 tp->features |= RTL_FEATURE_WOL;
3385         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3386                 tp->features |= RTL_FEATURE_WOL;
3387         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3388         RTL_W8(Cfg9346, Cfg9346_Lock);
3389
3390         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3391             (RTL_R8(PHYstatus) & TBI_Enable)) {
3392                 tp->set_speed = rtl8169_set_speed_tbi;
3393                 tp->get_settings = rtl8169_gset_tbi;
3394                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3395                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3396                 tp->link_ok = rtl8169_tbi_link_ok;
3397                 tp->do_ioctl = rtl_tbi_ioctl;
3398         } else {
3399                 tp->set_speed = rtl8169_set_speed_xmii;
3400                 tp->get_settings = rtl8169_gset_xmii;
3401                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3402                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3403                 tp->link_ok = rtl8169_xmii_link_ok;
3404                 tp->do_ioctl = rtl_xmii_ioctl;
3405         }
3406
3407         spin_lock_init(&tp->lock);
3408
3409         /* Get MAC address */
3410         for (i = 0; i < MAC_ADDR_LEN; i++)
3411                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3412         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3413
3414         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3415         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3416         dev->irq = pdev->irq;
3417         dev->base_addr = (unsigned long) ioaddr;
3418
3419         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3420
3421         /* don't enable SG, IP_CSUM and TSO by default - it might not work
3422          * properly for all devices */
3423         dev->features |= NETIF_F_RXCSUM |
3424                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3425
3426         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3427                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3428         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3429                 NETIF_F_HIGHDMA;
3430
3431         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3432                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3433                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3434
3435         tp->intr_mask = 0xffff;
3436         tp->hw_start = cfg->hw_start;
3437         tp->intr_event = cfg->intr_event;
3438         tp->napi_event = cfg->napi_event;
3439
3440         init_timer(&tp->timer);
3441         tp->timer.data = (unsigned long) dev;
3442         tp->timer.function = rtl8169_phy_timer;
3443
3444         tp->fw = RTL_FIRMWARE_UNKNOWN;
3445
3446         rc = register_netdev(dev);
3447         if (rc < 0)
3448                 goto err_out_msi_4;
3449
3450         pci_set_drvdata(pdev, dev);
3451
3452         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3453                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3454                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3455
3456         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3457             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3458             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3459                 rtl8168_driver_start(tp);
3460         }
3461
3462         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3463
3464         if (pci_dev_run_wake(pdev))
3465                 pm_runtime_put_noidle(&pdev->dev);
3466
3467         netif_carrier_off(dev);
3468
3469 out:
3470         return rc;
3471
3472 err_out_msi_4:
3473         rtl_disable_msi(pdev, tp);
3474         iounmap(ioaddr);
3475 err_out_free_res_3:
3476         pci_release_regions(pdev);
3477 err_out_mwi_2:
3478         pci_clear_mwi(pdev);
3479         pci_disable_device(pdev);
3480 err_out_free_dev_1:
3481         free_netdev(dev);
3482         goto out;
3483 }
3484
3485 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3486 {
3487         struct net_device *dev = pci_get_drvdata(pdev);
3488         struct rtl8169_private *tp = netdev_priv(dev);
3489
3490         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3491             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3492             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3493                 rtl8168_driver_stop(tp);
3494         }
3495
3496         cancel_delayed_work_sync(&tp->task);
3497
3498         unregister_netdev(dev);
3499
3500         rtl_release_firmware(tp);
3501
3502         if (pci_dev_run_wake(pdev))
3503                 pm_runtime_get_noresume(&pdev->dev);
3504
3505         /* restore original MAC address */
3506         rtl_rar_set(tp, dev->perm_addr);
3507
3508         rtl_disable_msi(pdev, tp);
3509         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3510         pci_set_drvdata(pdev, NULL);
3511 }
3512
3513 static void rtl_request_firmware(struct rtl8169_private *tp)
3514 {
3515         /* Return early if the firmware is already loaded / cached. */
3516         if (IS_ERR(tp->fw)) {
3517                 const char *name;
3518
3519                 name = rtl_lookup_firmware_name(tp);
3520                 if (name) {
3521                         int rc;
3522
3523                         rc = request_firmware(&tp->fw, name, &tp->pci_dev->dev);
3524                         if (rc >= 0)
3525                                 return;
3526
3527                         netif_warn(tp, ifup, tp->dev, "unable to load "
3528                                 "firmware patch %s (%d)\n", name, rc);
3529                 }
3530                 tp->fw = NULL;
3531         }
3532 }
3533
3534 static int rtl8169_open(struct net_device *dev)
3535 {
3536         struct rtl8169_private *tp = netdev_priv(dev);
3537         void __iomem *ioaddr = tp->mmio_addr;
3538         struct pci_dev *pdev = tp->pci_dev;
3539         int retval = -ENOMEM;
3540
3541         pm_runtime_get_sync(&pdev->dev);
3542
3543         /*
3544          * Rx and Tx desscriptors needs 256 bytes alignment.
3545          * dma_alloc_coherent provides more.
3546          */
3547         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3548                                              &tp->TxPhyAddr, GFP_KERNEL);
3549         if (!tp->TxDescArray)
3550                 goto err_pm_runtime_put;
3551
3552         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3553                                              &tp->RxPhyAddr, GFP_KERNEL);
3554         if (!tp->RxDescArray)
3555                 goto err_free_tx_0;
3556
3557         retval = rtl8169_init_ring(dev);
3558         if (retval < 0)
3559                 goto err_free_rx_1;
3560
3561         INIT_DELAYED_WORK(&tp->task, NULL);
3562
3563         smp_mb();
3564
3565         rtl_request_firmware(tp);
3566
3567         retval = request_irq(dev->irq, rtl8169_interrupt,
3568                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3569                              dev->name, dev);
3570         if (retval < 0)
3571                 goto err_release_fw_2;
3572
3573         napi_enable(&tp->napi);
3574
3575         rtl8169_init_phy(dev, tp);
3576
3577         rtl8169_set_features(dev, dev->features);
3578
3579         rtl_pll_power_up(tp);
3580
3581         rtl_hw_start(dev);
3582
3583         tp->saved_wolopts = 0;
3584         pm_runtime_put_noidle(&pdev->dev);
3585
3586         rtl8169_check_link_status(dev, tp, ioaddr);
3587 out:
3588         return retval;
3589
3590 err_release_fw_2:
3591         rtl_release_firmware(tp);
3592         rtl8169_rx_clear(tp);
3593 err_free_rx_1:
3594         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3595                           tp->RxPhyAddr);
3596         tp->RxDescArray = NULL;
3597 err_free_tx_0:
3598         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3599                           tp->TxPhyAddr);
3600         tp->TxDescArray = NULL;
3601 err_pm_runtime_put:
3602         pm_runtime_put_noidle(&pdev->dev);
3603         goto out;
3604 }
3605
3606 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3607 {
3608         void __iomem *ioaddr = tp->mmio_addr;
3609
3610         /* Disable interrupts */
3611         rtl8169_irq_mask_and_ack(ioaddr);
3612
3613         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3614             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3615             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3616                 while (RTL_R8(TxPoll) & NPQ)
3617                         udelay(20);
3618
3619         }
3620
3621         /* Reset the chipset */
3622         RTL_W8(ChipCmd, CmdReset);
3623
3624         /* PCI commit */
3625         RTL_R8(ChipCmd);
3626 }
3627
3628 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3629 {
3630         void __iomem *ioaddr = tp->mmio_addr;
3631         u32 cfg = rtl8169_rx_config;
3632
3633         cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
3634         RTL_W32(RxConfig, cfg);
3635
3636         /* Set DMA burst size and Interframe Gap Time */
3637         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3638                 (InterFrameGap << TxInterFrameGapShift));
3639 }
3640
3641 static void rtl_hw_start(struct net_device *dev)
3642 {
3643         struct rtl8169_private *tp = netdev_priv(dev);
3644
3645         rtl_hw_reset(tp);
3646
3647         tp->hw_start(dev);
3648
3649         netif_start_queue(dev);
3650 }
3651
3652 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3653                                          void __iomem *ioaddr)
3654 {
3655         /*
3656          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3657          * register to be written before TxDescAddrLow to work.
3658          * Switching from MMIO to I/O access fixes the issue as well.
3659          */
3660         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3661         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3662         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3663         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3664 }
3665
3666 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3667 {
3668         u16 cmd;
3669
3670         cmd = RTL_R16(CPlusCmd);
3671         RTL_W16(CPlusCmd, cmd);
3672         return cmd;
3673 }
3674
3675 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3676 {
3677         /* Low hurts. Let's disable the filtering. */
3678         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3679 }
3680
3681 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3682 {
3683         static const struct {
3684                 u32 mac_version;
3685                 u32 clk;
3686                 u32 val;
3687         } cfg2_info [] = {
3688                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3689                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3690                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3691                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3692         }, *p = cfg2_info;
3693         unsigned int i;
3694         u32 clk;
3695
3696         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3697         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3698                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3699                         RTL_W32(0x7c, p->val);
3700                         break;
3701                 }
3702         }
3703 }
3704
3705 static void rtl_hw_start_8169(struct net_device *dev)
3706 {
3707         struct rtl8169_private *tp = netdev_priv(dev);
3708         void __iomem *ioaddr = tp->mmio_addr;
3709         struct pci_dev *pdev = tp->pci_dev;
3710
3711         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3712                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3713                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3714         }
3715
3716         RTL_W8(Cfg9346, Cfg9346_Unlock);
3717         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3718             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3719             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3720             tp->mac_version == RTL_GIGA_MAC_VER_04)
3721                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3722
3723         RTL_W8(EarlyTxThres, NoEarlyTx);
3724
3725         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3726
3727         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3728             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3729             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3730             tp->mac_version == RTL_GIGA_MAC_VER_04)
3731                 rtl_set_rx_tx_config_registers(tp);
3732
3733         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3734
3735         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3736             tp->mac_version == RTL_GIGA_MAC_VER_03) {
3737                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3738                         "Bit-3 and bit-14 MUST be 1\n");
3739                 tp->cp_cmd |= (1 << 14);
3740         }
3741
3742         RTL_W16(CPlusCmd, tp->cp_cmd);
3743
3744         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3745
3746         /*
3747          * Undocumented corner. Supposedly:
3748          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3749          */
3750         RTL_W16(IntrMitigate, 0x0000);
3751
3752         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3753
3754         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3755             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3756             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3757             tp->mac_version != RTL_GIGA_MAC_VER_04) {
3758                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3759                 rtl_set_rx_tx_config_registers(tp);
3760         }
3761
3762         RTL_W8(Cfg9346, Cfg9346_Lock);
3763
3764         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3765         RTL_R8(IntrMask);
3766
3767         RTL_W32(RxMissed, 0);
3768
3769         rtl_set_rx_mode(dev);
3770
3771         /* no early-rx interrupts */
3772         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3773
3774         /* Enable all known interrupts by setting the interrupt mask. */
3775         RTL_W16(IntrMask, tp->intr_event);
3776 }
3777
3778 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3779 {
3780         struct net_device *dev = pci_get_drvdata(pdev);
3781         struct rtl8169_private *tp = netdev_priv(dev);
3782         int cap = tp->pcie_cap;
3783
3784         if (cap) {
3785                 u16 ctl;
3786
3787                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3788                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3789                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3790         }
3791 }
3792
3793 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3794 {
3795         u32 csi;
3796
3797         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3798         rtl_csi_write(ioaddr, 0x070c, csi | bits);
3799 }
3800
3801 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3802 {
3803         rtl_csi_access_enable(ioaddr, 0x17000000);
3804 }
3805
3806 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3807 {
3808         rtl_csi_access_enable(ioaddr, 0x27000000);
3809 }
3810
3811 struct ephy_info {
3812         unsigned int offset;
3813         u16 mask;
3814         u16 bits;
3815 };
3816
3817 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3818 {
3819         u16 w;
3820
3821         while (len-- > 0) {
3822                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3823                 rtl_ephy_write(ioaddr, e->offset, w);
3824                 e++;
3825         }
3826 }
3827
3828 static void rtl_disable_clock_request(struct pci_dev *pdev)
3829 {
3830         struct net_device *dev = pci_get_drvdata(pdev);
3831         struct rtl8169_private *tp = netdev_priv(dev);
3832         int cap = tp->pcie_cap;
3833
3834         if (cap) {
3835                 u16 ctl;
3836
3837                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3838                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3839                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3840         }
3841 }
3842
3843 static void rtl_enable_clock_request(struct pci_dev *pdev)
3844 {
3845         struct net_device *dev = pci_get_drvdata(pdev);
3846         struct rtl8169_private *tp = netdev_priv(dev);
3847         int cap = tp->pcie_cap;
3848
3849         if (cap) {
3850                 u16 ctl;
3851
3852                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3853                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3854                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3855         }
3856 }
3857
3858 #define R8168_CPCMD_QUIRK_MASK (\
3859         EnableBist | \
3860         Mac_dbgo_oe | \
3861         Force_half_dup | \
3862         Force_rxflow_en | \
3863         Force_txflow_en | \
3864         Cxpl_dbg_sel | \
3865         ASF | \
3866         PktCntrDisable | \
3867         Mac_dbgo_sel)
3868
3869 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3870 {
3871         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3872
3873         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3874
3875         rtl_tx_performance_tweak(pdev,
3876                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3877 }
3878
3879 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3880 {
3881         rtl_hw_start_8168bb(ioaddr, pdev);
3882
3883         RTL_W8(MaxTxPacketSize, TxPacketMax);
3884
3885         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3886 }
3887
3888 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3889 {
3890         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3891
3892         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3893
3894         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3895
3896         rtl_disable_clock_request(pdev);
3897
3898         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3899 }
3900
3901 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3902 {
3903         static const struct ephy_info e_info_8168cp[] = {
3904                 { 0x01, 0,      0x0001 },
3905                 { 0x02, 0x0800, 0x1000 },
3906                 { 0x03, 0,      0x0042 },
3907                 { 0x06, 0x0080, 0x0000 },
3908                 { 0x07, 0,      0x2000 }
3909         };
3910
3911         rtl_csi_access_enable_2(ioaddr);
3912
3913         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3914
3915         __rtl_hw_start_8168cp(ioaddr, pdev);
3916 }
3917
3918 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3919 {
3920         rtl_csi_access_enable_2(ioaddr);
3921
3922         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3923
3924         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3925
3926         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3927 }
3928
3929 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3930 {
3931         rtl_csi_access_enable_2(ioaddr);
3932
3933         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3934
3935         /* Magic. */
3936         RTL_W8(DBG_REG, 0x20);
3937
3938         RTL_W8(MaxTxPacketSize, TxPacketMax);
3939
3940         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3941
3942         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3943 }
3944
3945 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3946 {
3947         static const struct ephy_info e_info_8168c_1[] = {
3948                 { 0x02, 0x0800, 0x1000 },
3949                 { 0x03, 0,      0x0002 },
3950                 { 0x06, 0x0080, 0x0000 }
3951         };
3952
3953         rtl_csi_access_enable_2(ioaddr);
3954
3955         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3956
3957         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3958
3959         __rtl_hw_start_8168cp(ioaddr, pdev);
3960 }
3961
3962 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3963 {
3964         static const struct ephy_info e_info_8168c_2[] = {
3965                 { 0x01, 0,      0x0001 },
3966                 { 0x03, 0x0400, 0x0220 }
3967         };
3968
3969         rtl_csi_access_enable_2(ioaddr);
3970
3971         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3972
3973         __rtl_hw_start_8168cp(ioaddr, pdev);
3974 }
3975
3976 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3977 {
3978         rtl_hw_start_8168c_2(ioaddr, pdev);
3979 }
3980
3981 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3982 {
3983         rtl_csi_access_enable_2(ioaddr);
3984
3985         __rtl_hw_start_8168cp(ioaddr, pdev);
3986 }
3987
3988 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3989 {
3990         rtl_csi_access_enable_2(ioaddr);
3991
3992         rtl_disable_clock_request(pdev);
3993
3994         RTL_W8(MaxTxPacketSize, TxPacketMax);
3995
3996         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3997
3998         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3999 }
4000
4001 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4002 {
4003         rtl_csi_access_enable_1(ioaddr);
4004
4005         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4006
4007         RTL_W8(MaxTxPacketSize, TxPacketMax);
4008
4009         rtl_disable_clock_request(pdev);
4010 }
4011
4012 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4013 {
4014         static const struct ephy_info e_info_8168d_4[] = {
4015                 { 0x0b, ~0,     0x48 },
4016                 { 0x19, 0x20,   0x50 },
4017                 { 0x0c, ~0,     0x20 }
4018         };
4019         int i;
4020
4021         rtl_csi_access_enable_1(ioaddr);
4022
4023         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4024
4025         RTL_W8(MaxTxPacketSize, TxPacketMax);
4026
4027         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4028                 const struct ephy_info *e = e_info_8168d_4 + i;
4029                 u16 w;
4030
4031                 w = rtl_ephy_read(ioaddr, e->offset);
4032                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4033         }
4034
4035         rtl_enable_clock_request(pdev);
4036 }
4037
4038 static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4039 {
4040         static const struct ephy_info e_info_8168e[] = {
4041                 { 0x00, 0x0200, 0x0100 },
4042                 { 0x00, 0x0000, 0x0004 },
4043                 { 0x06, 0x0002, 0x0001 },
4044                 { 0x06, 0x0000, 0x0030 },
4045                 { 0x07, 0x0000, 0x2000 },
4046                 { 0x00, 0x0000, 0x0020 },
4047                 { 0x03, 0x5800, 0x2000 },
4048                 { 0x03, 0x0000, 0x0001 },
4049                 { 0x01, 0x0800, 0x1000 },
4050                 { 0x07, 0x0000, 0x4000 },
4051                 { 0x1e, 0x0000, 0x2000 },
4052                 { 0x19, 0xffff, 0xfe6c },
4053                 { 0x0a, 0x0000, 0x0040 }
4054         };
4055
4056         rtl_csi_access_enable_2(ioaddr);
4057
4058         rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4059
4060         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4061
4062         RTL_W8(MaxTxPacketSize, TxPacketMax);
4063
4064         rtl_disable_clock_request(pdev);
4065
4066         /* Reset tx FIFO pointer */
4067         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4068         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4069
4070         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4071 }
4072
4073 static void rtl_hw_start_8168(struct net_device *dev)
4074 {
4075         struct rtl8169_private *tp = netdev_priv(dev);
4076         void __iomem *ioaddr = tp->mmio_addr;
4077         struct pci_dev *pdev = tp->pci_dev;
4078
4079         RTL_W8(Cfg9346, Cfg9346_Unlock);
4080
4081         RTL_W8(MaxTxPacketSize, TxPacketMax);
4082
4083         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4084
4085         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4086
4087         RTL_W16(CPlusCmd, tp->cp_cmd);
4088
4089         RTL_W16(IntrMitigate, 0x5151);
4090
4091         /* Work around for RxFIFO overflow. */
4092         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4093             tp->mac_version == RTL_GIGA_MAC_VER_22) {
4094                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4095                 tp->intr_event &= ~RxOverflow;
4096         }
4097
4098         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4099
4100         rtl_set_rx_mode(dev);
4101
4102         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4103                 (InterFrameGap << TxInterFrameGapShift));
4104
4105         RTL_R8(IntrMask);
4106
4107         switch (tp->mac_version) {
4108         case RTL_GIGA_MAC_VER_11:
4109                 rtl_hw_start_8168bb(ioaddr, pdev);
4110                 break;
4111
4112         case RTL_GIGA_MAC_VER_12:
4113         case RTL_GIGA_MAC_VER_17:
4114                 rtl_hw_start_8168bef(ioaddr, pdev);
4115                 break;
4116
4117         case RTL_GIGA_MAC_VER_18:
4118                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4119                 break;
4120
4121         case RTL_GIGA_MAC_VER_19:
4122                 rtl_hw_start_8168c_1(ioaddr, pdev);
4123                 break;
4124
4125         case RTL_GIGA_MAC_VER_20:
4126                 rtl_hw_start_8168c_2(ioaddr, pdev);
4127                 break;
4128
4129         case RTL_GIGA_MAC_VER_21:
4130                 rtl_hw_start_8168c_3(ioaddr, pdev);
4131                 break;
4132
4133         case RTL_GIGA_MAC_VER_22:
4134                 rtl_hw_start_8168c_4(ioaddr, pdev);
4135                 break;
4136
4137         case RTL_GIGA_MAC_VER_23:
4138                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4139                 break;
4140
4141         case RTL_GIGA_MAC_VER_24:
4142                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4143                 break;
4144
4145         case RTL_GIGA_MAC_VER_25:
4146         case RTL_GIGA_MAC_VER_26:
4147         case RTL_GIGA_MAC_VER_27:
4148                 rtl_hw_start_8168d(ioaddr, pdev);
4149                 break;
4150
4151         case RTL_GIGA_MAC_VER_28:
4152                 rtl_hw_start_8168d_4(ioaddr, pdev);
4153                 break;
4154
4155         case RTL_GIGA_MAC_VER_31:
4156                 rtl_hw_start_8168dp(ioaddr, pdev);
4157                 break;
4158
4159         case RTL_GIGA_MAC_VER_32:
4160         case RTL_GIGA_MAC_VER_33:
4161                 rtl_hw_start_8168e(ioaddr, pdev);
4162                 break;
4163
4164         default:
4165                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4166                         dev->name, tp->mac_version);
4167                 break;
4168         }
4169
4170         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4171
4172         RTL_W8(Cfg9346, Cfg9346_Lock);
4173
4174         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4175
4176         RTL_W16(IntrMask, tp->intr_event);
4177 }
4178
4179 #define R810X_CPCMD_QUIRK_MASK (\
4180         EnableBist | \
4181         Mac_dbgo_oe | \
4182         Force_half_dup | \
4183         Force_rxflow_en | \
4184         Force_txflow_en | \
4185         Cxpl_dbg_sel | \
4186         ASF | \
4187         PktCntrDisable | \
4188         Mac_dbgo_sel)
4189
4190 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4191 {
4192         static const struct ephy_info e_info_8102e_1[] = {
4193                 { 0x01, 0, 0x6e65 },
4194                 { 0x02, 0, 0x091f },
4195                 { 0x03, 0, 0xc2f9 },
4196                 { 0x06, 0, 0xafb5 },
4197                 { 0x07, 0, 0x0e00 },
4198                 { 0x19, 0, 0xec80 },
4199                 { 0x01, 0, 0x2e65 },
4200                 { 0x01, 0, 0x6e65 }
4201         };
4202         u8 cfg1;
4203
4204         rtl_csi_access_enable_2(ioaddr);
4205
4206         RTL_W8(DBG_REG, FIX_NAK_1);
4207
4208         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4209
4210         RTL_W8(Config1,
4211                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4212         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4213
4214         cfg1 = RTL_R8(Config1);
4215         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4216                 RTL_W8(Config1, cfg1 & ~LEDS0);
4217
4218         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4219 }
4220
4221 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4222 {
4223         rtl_csi_access_enable_2(ioaddr);
4224
4225         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4226
4227         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4228         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4229 }
4230
4231 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4232 {
4233         rtl_hw_start_8102e_2(ioaddr, pdev);
4234
4235         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4236 }
4237
4238 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4239 {
4240         static const struct ephy_info e_info_8105e_1[] = {
4241                 { 0x07, 0, 0x4000 },
4242                 { 0x19, 0, 0x0200 },
4243                 { 0x19, 0, 0x0020 },
4244                 { 0x1e, 0, 0x2000 },
4245                 { 0x03, 0, 0x0001 },
4246                 { 0x19, 0, 0x0100 },
4247                 { 0x19, 0, 0x0004 },
4248                 { 0x0a, 0, 0x0020 }
4249         };
4250
4251         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4252         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4253
4254         /* Disable Early Tally Counter */
4255         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4256
4257         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4258         RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4259
4260         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4261 }
4262
4263 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4264 {
4265         rtl_hw_start_8105e_1(ioaddr, pdev);
4266         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4267 }
4268
4269 static void rtl_hw_start_8101(struct net_device *dev)
4270 {
4271         struct rtl8169_private *tp = netdev_priv(dev);
4272         void __iomem *ioaddr = tp->mmio_addr;
4273         struct pci_dev *pdev = tp->pci_dev;
4274
4275         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4276             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4277                 int cap = tp->pcie_cap;
4278
4279                 if (cap) {
4280                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4281                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4282                 }
4283         }
4284
4285         RTL_W8(Cfg9346, Cfg9346_Unlock);
4286
4287         switch (tp->mac_version) {
4288         case RTL_GIGA_MAC_VER_07:
4289                 rtl_hw_start_8102e_1(ioaddr, pdev);
4290                 break;
4291
4292         case RTL_GIGA_MAC_VER_08:
4293                 rtl_hw_start_8102e_3(ioaddr, pdev);
4294                 break;
4295
4296         case RTL_GIGA_MAC_VER_09:
4297                 rtl_hw_start_8102e_2(ioaddr, pdev);
4298                 break;
4299
4300         case RTL_GIGA_MAC_VER_29:
4301                 rtl_hw_start_8105e_1(ioaddr, pdev);
4302                 break;
4303         case RTL_GIGA_MAC_VER_30:
4304                 rtl_hw_start_8105e_2(ioaddr, pdev);
4305                 break;
4306         }
4307
4308         RTL_W8(Cfg9346, Cfg9346_Lock);
4309
4310         RTL_W8(MaxTxPacketSize, TxPacketMax);
4311
4312         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4313
4314         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4315         RTL_W16(CPlusCmd, tp->cp_cmd);
4316
4317         RTL_W16(IntrMitigate, 0x0000);
4318
4319         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4320
4321         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4322         rtl_set_rx_tx_config_registers(tp);
4323
4324         RTL_R8(IntrMask);
4325
4326         rtl_set_rx_mode(dev);
4327
4328         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4329
4330         RTL_W16(IntrMask, tp->intr_event);
4331 }
4332
4333 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4334 {
4335         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4336                 return -EINVAL;
4337
4338         dev->mtu = new_mtu;
4339         netdev_update_features(dev);
4340
4341         return 0;
4342 }
4343
4344 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4345 {
4346         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4347         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4348 }
4349
4350 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4351                                      void **data_buff, struct RxDesc *desc)
4352 {
4353         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4354                          DMA_FROM_DEVICE);
4355
4356         kfree(*data_buff);
4357         *data_buff = NULL;
4358         rtl8169_make_unusable_by_asic(desc);
4359 }
4360
4361 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4362 {
4363         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4364
4365         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4366 }
4367
4368 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4369                                        u32 rx_buf_sz)
4370 {
4371         desc->addr = cpu_to_le64(mapping);
4372         wmb();
4373         rtl8169_mark_to_asic(desc, rx_buf_sz);
4374 }
4375
4376 static inline void *rtl8169_align(void *data)
4377 {
4378         return (void *)ALIGN((long)data, 16);
4379 }
4380
4381 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4382                                              struct RxDesc *desc)
4383 {
4384         void *data;
4385         dma_addr_t mapping;
4386         struct device *d = &tp->pci_dev->dev;
4387         struct net_device *dev = tp->dev;
4388         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4389
4390         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4391         if (!data)
4392                 return NULL;
4393
4394         if (rtl8169_align(data) != data) {
4395                 kfree(data);
4396                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4397                 if (!data)
4398                         return NULL;
4399         }
4400
4401         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4402                                  DMA_FROM_DEVICE);
4403         if (unlikely(dma_mapping_error(d, mapping))) {
4404                 if (net_ratelimit())
4405                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4406                 goto err_out;
4407         }
4408
4409         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4410         return data;
4411
4412 err_out:
4413         kfree(data);
4414         return NULL;
4415 }
4416
4417 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4418 {
4419         unsigned int i;
4420
4421         for (i = 0; i < NUM_RX_DESC; i++) {
4422                 if (tp->Rx_databuff[i]) {
4423                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4424                                             tp->RxDescArray + i);
4425                 }
4426         }
4427 }
4428
4429 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4430 {
4431         desc->opts1 |= cpu_to_le32(RingEnd);
4432 }
4433
4434 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4435 {
4436         unsigned int i;
4437
4438         for (i = 0; i < NUM_RX_DESC; i++) {
4439                 void *data;
4440
4441                 if (tp->Rx_databuff[i])
4442                         continue;
4443
4444                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4445                 if (!data) {
4446                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4447                         goto err_out;
4448                 }
4449                 tp->Rx_databuff[i] = data;
4450         }
4451
4452         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4453         return 0;
4454
4455 err_out:
4456         rtl8169_rx_clear(tp);
4457         return -ENOMEM;
4458 }
4459
4460 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4461 {
4462         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4463 }
4464
4465 static int rtl8169_init_ring(struct net_device *dev)
4466 {
4467         struct rtl8169_private *tp = netdev_priv(dev);
4468
4469         rtl8169_init_ring_indexes(tp);
4470
4471         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4472         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4473
4474         return rtl8169_rx_fill(tp);
4475 }
4476
4477 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4478                                  struct TxDesc *desc)
4479 {
4480         unsigned int len = tx_skb->len;
4481
4482         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4483
4484         desc->opts1 = 0x00;
4485         desc->opts2 = 0x00;
4486         desc->addr = 0x00;
4487         tx_skb->len = 0;
4488 }
4489
4490 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4491                                    unsigned int n)
4492 {
4493         unsigned int i;
4494
4495         for (i = 0; i < n; i++) {
4496                 unsigned int entry = (start + i) % NUM_TX_DESC;
4497                 struct ring_info *tx_skb = tp->tx_skb + entry;
4498                 unsigned int len = tx_skb->len;
4499
4500                 if (len) {
4501                         struct sk_buff *skb = tx_skb->skb;
4502
4503                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4504                                              tp->TxDescArray + entry);
4505                         if (skb) {
4506                                 tp->dev->stats.tx_dropped++;
4507                                 dev_kfree_skb(skb);
4508                                 tx_skb->skb = NULL;
4509                         }
4510                 }
4511         }
4512 }
4513
4514 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4515 {
4516         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4517         tp->cur_tx = tp->dirty_tx = 0;
4518 }
4519
4520 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4521 {
4522         struct rtl8169_private *tp = netdev_priv(dev);
4523
4524         PREPARE_DELAYED_WORK(&tp->task, task);
4525         schedule_delayed_work(&tp->task, 4);
4526 }
4527
4528 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4529 {
4530         struct rtl8169_private *tp = netdev_priv(dev);
4531         void __iomem *ioaddr = tp->mmio_addr;
4532
4533         synchronize_irq(dev->irq);
4534
4535         /* Wait for any pending NAPI task to complete */
4536         napi_disable(&tp->napi);
4537
4538         rtl8169_irq_mask_and_ack(ioaddr);
4539
4540         tp->intr_mask = 0xffff;
4541         RTL_W16(IntrMask, tp->intr_event);
4542         napi_enable(&tp->napi);
4543 }
4544
4545 static void rtl8169_reinit_task(struct work_struct *work)
4546 {
4547         struct rtl8169_private *tp =
4548                 container_of(work, struct rtl8169_private, task.work);
4549         struct net_device *dev = tp->dev;
4550         int ret;
4551
4552         rtnl_lock();
4553
4554         if (!netif_running(dev))
4555                 goto out_unlock;
4556
4557         rtl8169_wait_for_quiescence(dev);
4558         rtl8169_close(dev);
4559
4560         ret = rtl8169_open(dev);
4561         if (unlikely(ret < 0)) {
4562                 if (net_ratelimit())
4563                         netif_err(tp, drv, dev,
4564                                   "reinit failure (status = %d). Rescheduling\n",
4565                                   ret);
4566                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4567         }
4568
4569 out_unlock:
4570         rtnl_unlock();
4571 }
4572
4573 static void rtl8169_reset_task(struct work_struct *work)
4574 {
4575         struct rtl8169_private *tp =
4576                 container_of(work, struct rtl8169_private, task.work);
4577         struct net_device *dev = tp->dev;
4578         int i;
4579
4580         rtnl_lock();
4581
4582         if (!netif_running(dev))
4583                 goto out_unlock;
4584
4585         rtl8169_wait_for_quiescence(dev);
4586
4587         for (i = 0; i < NUM_RX_DESC; i++)
4588                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4589
4590         rtl8169_tx_clear(tp);
4591
4592         rtl8169_init_ring_indexes(tp);
4593         rtl_hw_start(dev);
4594         netif_wake_queue(dev);
4595         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4596
4597 out_unlock:
4598         rtnl_unlock();
4599 }
4600
4601 static void rtl8169_tx_timeout(struct net_device *dev)
4602 {
4603         struct rtl8169_private *tp = netdev_priv(dev);
4604
4605         rtl8169_hw_reset(tp);
4606
4607         /* Let's wait a bit while any (async) irq lands on */
4608         rtl8169_schedule_work(dev, rtl8169_reset_task);
4609 }
4610
4611 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4612                               u32 *opts)
4613 {
4614         struct skb_shared_info *info = skb_shinfo(skb);
4615         unsigned int cur_frag, entry;
4616         struct TxDesc * uninitialized_var(txd);
4617         struct device *d = &tp->pci_dev->dev;
4618
4619         entry = tp->cur_tx;
4620         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4621                 skb_frag_t *frag = info->frags + cur_frag;
4622                 dma_addr_t mapping;
4623                 u32 status, len;
4624                 void *addr;
4625
4626                 entry = (entry + 1) % NUM_TX_DESC;
4627
4628                 txd = tp->TxDescArray + entry;
4629                 len = frag->size;
4630                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4631                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4632                 if (unlikely(dma_mapping_error(d, mapping))) {
4633                         if (net_ratelimit())
4634                                 netif_err(tp, drv, tp->dev,
4635                                           "Failed to map TX fragments DMA!\n");
4636                         goto err_out;
4637                 }
4638
4639                 /* Anti gcc 2.95.3 bugware (sic) */
4640                 status = opts[0] | len |
4641                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
4642
4643                 txd->opts1 = cpu_to_le32(status);
4644                 txd->opts2 = cpu_to_le32(opts[1]);
4645                 txd->addr = cpu_to_le64(mapping);
4646
4647                 tp->tx_skb[entry].len = len;
4648         }
4649
4650         if (cur_frag) {
4651                 tp->tx_skb[entry].skb = skb;
4652                 txd->opts1 |= cpu_to_le32(LastFrag);
4653         }
4654
4655         return cur_frag;
4656
4657 err_out:
4658         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4659         return -EIO;
4660 }
4661
4662 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4663                                     struct sk_buff *skb, u32 *opts)
4664 {
4665         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
4666         u32 mss = skb_shinfo(skb)->gso_size;
4667         int offset = info->opts_offset;
4668
4669         if (mss) {
4670                 opts[0] |= TD_LSO;
4671                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4672         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4673                 const struct iphdr *ip = ip_hdr(skb);
4674
4675                 if (ip->protocol == IPPROTO_TCP)
4676                         opts[offset] |= info->checksum.tcp;
4677                 else if (ip->protocol == IPPROTO_UDP)
4678                         opts[offset] |= info->checksum.udp;
4679                 else
4680                         WARN_ON_ONCE(1);
4681         }
4682 }
4683
4684 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4685                                       struct net_device *dev)
4686 {
4687         struct rtl8169_private *tp = netdev_priv(dev);
4688         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4689         struct TxDesc *txd = tp->TxDescArray + entry;
4690         void __iomem *ioaddr = tp->mmio_addr;
4691         struct device *d = &tp->pci_dev->dev;
4692         dma_addr_t mapping;
4693         u32 status, len;
4694         u32 opts[2];
4695         int frags;
4696
4697         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4698                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4699                 goto err_stop_0;
4700         }
4701
4702         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4703                 goto err_stop_0;
4704
4705         len = skb_headlen(skb);
4706         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4707         if (unlikely(dma_mapping_error(d, mapping))) {
4708                 if (net_ratelimit())
4709                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4710                 goto err_dma_0;
4711         }
4712
4713         tp->tx_skb[entry].len = len;
4714         txd->addr = cpu_to_le64(mapping);
4715
4716         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4717         opts[0] = DescOwn;
4718
4719         rtl8169_tso_csum(tp, skb, opts);
4720
4721         frags = rtl8169_xmit_frags(tp, skb, opts);
4722         if (frags < 0)
4723                 goto err_dma_1;
4724         else if (frags)
4725                 opts[0] |= FirstFrag;
4726         else {
4727                 opts[0] |= FirstFrag | LastFrag;
4728                 tp->tx_skb[entry].skb = skb;
4729         }
4730
4731         txd->opts2 = cpu_to_le32(opts[1]);
4732
4733         wmb();
4734
4735         /* Anti gcc 2.95.3 bugware (sic) */
4736         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4737         txd->opts1 = cpu_to_le32(status);
4738
4739         tp->cur_tx += frags + 1;
4740
4741         wmb();
4742
4743         RTL_W8(TxPoll, NPQ);
4744
4745         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4746                 netif_stop_queue(dev);
4747                 smp_rmb();
4748                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4749                         netif_wake_queue(dev);
4750         }
4751
4752         return NETDEV_TX_OK;
4753
4754 err_dma_1:
4755         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4756 err_dma_0:
4757         dev_kfree_skb(skb);
4758         dev->stats.tx_dropped++;
4759         return NETDEV_TX_OK;
4760
4761 err_stop_0:
4762         netif_stop_queue(dev);
4763         dev->stats.tx_dropped++;
4764         return NETDEV_TX_BUSY;
4765 }
4766
4767 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4768 {
4769         struct rtl8169_private *tp = netdev_priv(dev);
4770         struct pci_dev *pdev = tp->pci_dev;
4771         u16 pci_status, pci_cmd;
4772
4773         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4774         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4775
4776         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4777                   pci_cmd, pci_status);
4778
4779         /*
4780          * The recovery sequence below admits a very elaborated explanation:
4781          * - it seems to work;
4782          * - I did not see what else could be done;
4783          * - it makes iop3xx happy.
4784          *
4785          * Feel free to adjust to your needs.
4786          */
4787         if (pdev->broken_parity_status)
4788                 pci_cmd &= ~PCI_COMMAND_PARITY;
4789         else
4790                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4791
4792         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4793
4794         pci_write_config_word(pdev, PCI_STATUS,
4795                 pci_status & (PCI_STATUS_DETECTED_PARITY |
4796                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4797                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4798
4799         /* The infamous DAC f*ckup only happens at boot time */
4800         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4801                 void __iomem *ioaddr = tp->mmio_addr;
4802
4803                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4804                 tp->cp_cmd &= ~PCIDAC;
4805                 RTL_W16(CPlusCmd, tp->cp_cmd);
4806                 dev->features &= ~NETIF_F_HIGHDMA;
4807         }
4808
4809         rtl8169_hw_reset(tp);
4810
4811         rtl8169_schedule_work(dev, rtl8169_reinit_task);
4812 }
4813
4814 static void rtl8169_tx_interrupt(struct net_device *dev,
4815                                  struct rtl8169_private *tp,
4816                                  void __iomem *ioaddr)
4817 {
4818         unsigned int dirty_tx, tx_left;
4819
4820         dirty_tx = tp->dirty_tx;
4821         smp_rmb();
4822         tx_left = tp->cur_tx - dirty_tx;
4823
4824         while (tx_left > 0) {
4825                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4826                 struct ring_info *tx_skb = tp->tx_skb + entry;
4827                 u32 status;
4828
4829                 rmb();
4830                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4831                 if (status & DescOwn)
4832                         break;
4833
4834                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4835                                      tp->TxDescArray + entry);
4836                 if (status & LastFrag) {
4837                         dev->stats.tx_packets++;
4838                         dev->stats.tx_bytes += tx_skb->skb->len;
4839                         dev_kfree_skb(tx_skb->skb);
4840                         tx_skb->skb = NULL;
4841                 }
4842                 dirty_tx++;
4843                 tx_left--;
4844         }
4845
4846         if (tp->dirty_tx != dirty_tx) {
4847                 tp->dirty_tx = dirty_tx;
4848                 smp_wmb();
4849                 if (netif_queue_stopped(dev) &&
4850                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4851                         netif_wake_queue(dev);
4852                 }
4853                 /*
4854                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4855                  * too close. Let's kick an extra TxPoll request when a burst
4856                  * of start_xmit activity is detected (if it is not detected,
4857                  * it is slow enough). -- FR
4858                  */
4859                 smp_rmb();
4860                 if (tp->cur_tx != dirty_tx)
4861                         RTL_W8(TxPoll, NPQ);
4862         }
4863 }
4864
4865 static inline int rtl8169_fragmented_frame(u32 status)
4866 {
4867         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4868 }
4869
4870 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4871 {
4872         u32 status = opts1 & RxProtoMask;
4873
4874         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4875             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4876                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4877         else
4878                 skb_checksum_none_assert(skb);
4879 }
4880
4881 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4882                                            struct rtl8169_private *tp,
4883                                            int pkt_size,
4884                                            dma_addr_t addr)
4885 {
4886         struct sk_buff *skb;
4887         struct device *d = &tp->pci_dev->dev;
4888
4889         data = rtl8169_align(data);
4890         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4891         prefetch(data);
4892         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4893         if (skb)
4894                 memcpy(skb->data, data, pkt_size);
4895         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4896
4897         return skb;
4898 }
4899
4900 static int rtl8169_rx_interrupt(struct net_device *dev,
4901                                 struct rtl8169_private *tp,
4902                                 void __iomem *ioaddr, u32 budget)
4903 {
4904         unsigned int cur_rx, rx_left;
4905         unsigned int count;
4906
4907         cur_rx = tp->cur_rx;
4908         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4909         rx_left = min(rx_left, budget);
4910
4911         for (; rx_left > 0; rx_left--, cur_rx++) {
4912                 unsigned int entry = cur_rx % NUM_RX_DESC;
4913                 struct RxDesc *desc = tp->RxDescArray + entry;
4914                 u32 status;
4915
4916                 rmb();
4917                 status = le32_to_cpu(desc->opts1);
4918
4919                 if (status & DescOwn)
4920                         break;
4921                 if (unlikely(status & RxRES)) {
4922                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4923                                    status);
4924                         dev->stats.rx_errors++;
4925                         if (status & (RxRWT | RxRUNT))
4926                                 dev->stats.rx_length_errors++;
4927                         if (status & RxCRC)
4928                                 dev->stats.rx_crc_errors++;
4929                         if (status & RxFOVF) {
4930                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4931                                 dev->stats.rx_fifo_errors++;
4932                         }
4933                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4934                 } else {
4935                         struct sk_buff *skb;
4936                         dma_addr_t addr = le64_to_cpu(desc->addr);
4937                         int pkt_size = (status & 0x00001FFF) - 4;
4938
4939                         /*
4940                          * The driver does not support incoming fragmented
4941                          * frames. They are seen as a symptom of over-mtu
4942                          * sized frames.
4943                          */
4944                         if (unlikely(rtl8169_fragmented_frame(status))) {
4945                                 dev->stats.rx_dropped++;
4946                                 dev->stats.rx_length_errors++;
4947                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
4948                                 continue;
4949                         }
4950
4951                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4952                                                   tp, pkt_size, addr);
4953                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4954                         if (!skb) {
4955                                 dev->stats.rx_dropped++;
4956                                 continue;
4957                         }
4958
4959                         rtl8169_rx_csum(skb, status);
4960                         skb_put(skb, pkt_size);
4961                         skb->protocol = eth_type_trans(skb, dev);
4962
4963                         rtl8169_rx_vlan_tag(desc, skb);
4964
4965                         napi_gro_receive(&tp->napi, skb);
4966
4967                         dev->stats.rx_bytes += pkt_size;
4968                         dev->stats.rx_packets++;
4969                 }
4970
4971                 /* Work around for AMD plateform. */
4972                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4973                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4974                         desc->opts2 = 0;
4975                         cur_rx++;
4976                 }
4977         }
4978
4979         count = cur_rx - tp->cur_rx;
4980         tp->cur_rx = cur_rx;
4981
4982         tp->dirty_rx += count;
4983
4984         return count;
4985 }
4986
4987 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4988 {
4989         struct net_device *dev = dev_instance;
4990         struct rtl8169_private *tp = netdev_priv(dev);
4991         void __iomem *ioaddr = tp->mmio_addr;
4992         int handled = 0;
4993         int status;
4994
4995         /* loop handling interrupts until we have no new ones or
4996          * we hit a invalid/hotplug case.
4997          */
4998         status = RTL_R16(IntrStatus);
4999         while (status && status != 0xffff) {
5000                 handled = 1;
5001
5002                 /* Handle all of the error cases first. These will reset
5003                  * the chip, so just exit the loop.
5004                  */
5005                 if (unlikely(!netif_running(dev))) {
5006                         rtl8169_asic_down(ioaddr);
5007                         break;
5008                 }
5009
5010                 if (unlikely(status & RxFIFOOver)) {
5011                         switch (tp->mac_version) {
5012                         /* Work around for rx fifo overflow */
5013                         case RTL_GIGA_MAC_VER_11:
5014                         case RTL_GIGA_MAC_VER_22:
5015                         case RTL_GIGA_MAC_VER_26:
5016                                 netif_stop_queue(dev);
5017                                 rtl8169_tx_timeout(dev);
5018                                 goto done;
5019                         /* Testers needed. */
5020                         case RTL_GIGA_MAC_VER_17:
5021                         case RTL_GIGA_MAC_VER_19:
5022                         case RTL_GIGA_MAC_VER_20:
5023                         case RTL_GIGA_MAC_VER_21:
5024                         case RTL_GIGA_MAC_VER_23:
5025                         case RTL_GIGA_MAC_VER_24:
5026                         case RTL_GIGA_MAC_VER_27:
5027                         case RTL_GIGA_MAC_VER_28:
5028                         case RTL_GIGA_MAC_VER_31:
5029                         /* Experimental science. Pktgen proof. */
5030                         case RTL_GIGA_MAC_VER_12:
5031                         case RTL_GIGA_MAC_VER_25:
5032                                 if (status == RxFIFOOver)
5033                                         goto done;
5034                                 break;
5035                         default:
5036                                 break;
5037                         }
5038                 }
5039
5040                 if (unlikely(status & SYSErr)) {
5041                         rtl8169_pcierr_interrupt(dev);
5042                         break;
5043                 }
5044
5045                 if (status & LinkChg)
5046                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5047
5048                 /* We need to see the lastest version of tp->intr_mask to
5049                  * avoid ignoring an MSI interrupt and having to wait for
5050                  * another event which may never come.
5051                  */
5052                 smp_rmb();
5053                 if (status & tp->intr_mask & tp->napi_event) {
5054                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5055                         tp->intr_mask = ~tp->napi_event;
5056
5057                         if (likely(napi_schedule_prep(&tp->napi)))
5058                                 __napi_schedule(&tp->napi);
5059                         else
5060                                 netif_info(tp, intr, dev,
5061                                            "interrupt %04x in poll\n", status);
5062                 }
5063
5064                 /* We only get a new MSI interrupt when all active irq
5065                  * sources on the chip have been acknowledged. So, ack
5066                  * everything we've seen and check if new sources have become
5067                  * active to avoid blocking all interrupts from the chip.
5068                  */
5069                 RTL_W16(IntrStatus,
5070                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5071                 status = RTL_R16(IntrStatus);
5072         }
5073 done:
5074         return IRQ_RETVAL(handled);
5075 }
5076
5077 static int rtl8169_poll(struct napi_struct *napi, int budget)
5078 {
5079         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5080         struct net_device *dev = tp->dev;
5081         void __iomem *ioaddr = tp->mmio_addr;
5082         int work_done;
5083
5084         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5085         rtl8169_tx_interrupt(dev, tp, ioaddr);
5086
5087         if (work_done < budget) {
5088                 napi_complete(napi);
5089
5090                 /* We need for force the visibility of tp->intr_mask
5091                  * for other CPUs, as we can loose an MSI interrupt
5092                  * and potentially wait for a retransmit timeout if we don't.
5093                  * The posted write to IntrMask is safe, as it will
5094                  * eventually make it to the chip and we won't loose anything
5095                  * until it does.
5096                  */
5097                 tp->intr_mask = 0xffff;
5098                 wmb();
5099                 RTL_W16(IntrMask, tp->intr_event);
5100         }
5101
5102         return work_done;
5103 }
5104
5105 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5106 {
5107         struct rtl8169_private *tp = netdev_priv(dev);
5108
5109         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5110                 return;
5111
5112         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5113         RTL_W32(RxMissed, 0);
5114 }
5115
5116 static void rtl8169_down(struct net_device *dev)
5117 {
5118         struct rtl8169_private *tp = netdev_priv(dev);
5119         void __iomem *ioaddr = tp->mmio_addr;
5120
5121         del_timer_sync(&tp->timer);
5122
5123         netif_stop_queue(dev);
5124
5125         napi_disable(&tp->napi);
5126
5127         spin_lock_irq(&tp->lock);
5128
5129         rtl8169_asic_down(ioaddr);
5130         /*
5131          * At this point device interrupts can not be enabled in any function,
5132          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5133          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5134          */
5135         rtl8169_rx_missed(dev, ioaddr);
5136
5137         spin_unlock_irq(&tp->lock);
5138
5139         synchronize_irq(dev->irq);
5140
5141         /* Give a racing hard_start_xmit a few cycles to complete. */
5142         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5143
5144         rtl8169_tx_clear(tp);
5145
5146         rtl8169_rx_clear(tp);
5147
5148         rtl_pll_power_down(tp);
5149 }
5150
5151 static int rtl8169_close(struct net_device *dev)
5152 {
5153         struct rtl8169_private *tp = netdev_priv(dev);
5154         struct pci_dev *pdev = tp->pci_dev;
5155
5156         pm_runtime_get_sync(&pdev->dev);
5157
5158         /* Update counters before going down */
5159         rtl8169_update_counters(dev);
5160
5161         rtl8169_down(dev);
5162
5163         free_irq(dev->irq, dev);
5164
5165         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5166                           tp->RxPhyAddr);
5167         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5168                           tp->TxPhyAddr);
5169         tp->TxDescArray = NULL;
5170         tp->RxDescArray = NULL;
5171
5172         pm_runtime_put_sync(&pdev->dev);
5173
5174         return 0;
5175 }
5176
5177 static void rtl_set_rx_mode(struct net_device *dev)
5178 {
5179         struct rtl8169_private *tp = netdev_priv(dev);
5180         void __iomem *ioaddr = tp->mmio_addr;
5181         unsigned long flags;
5182         u32 mc_filter[2];       /* Multicast hash filter */
5183         int rx_mode;
5184         u32 tmp = 0;
5185
5186         if (dev->flags & IFF_PROMISC) {
5187                 /* Unconditionally log net taps. */
5188                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5189                 rx_mode =
5190                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5191                     AcceptAllPhys;
5192                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5193         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5194                    (dev->flags & IFF_ALLMULTI)) {
5195                 /* Too many to filter perfectly -- accept all multicasts. */
5196                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5197                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5198         } else {
5199                 struct netdev_hw_addr *ha;
5200
5201                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5202                 mc_filter[1] = mc_filter[0] = 0;
5203                 netdev_for_each_mc_addr(ha, dev) {
5204                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5205                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5206                         rx_mode |= AcceptMulticast;
5207                 }
5208         }
5209
5210         spin_lock_irqsave(&tp->lock, flags);
5211
5212         tmp = rtl8169_rx_config | rx_mode |
5213               (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
5214
5215         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5216                 u32 data = mc_filter[0];
5217
5218                 mc_filter[0] = swab32(mc_filter[1]);
5219                 mc_filter[1] = swab32(data);
5220         }
5221
5222         RTL_W32(MAR0 + 4, mc_filter[1]);
5223         RTL_W32(MAR0 + 0, mc_filter[0]);
5224
5225         RTL_W32(RxConfig, tmp);
5226
5227         spin_unlock_irqrestore(&tp->lock, flags);
5228 }
5229
5230 /**
5231  *  rtl8169_get_stats - Get rtl8169 read/write statistics
5232  *  @dev: The Ethernet Device to get statistics for
5233  *
5234  *  Get TX/RX statistics for rtl8169
5235  */
5236 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5237 {
5238         struct rtl8169_private *tp = netdev_priv(dev);
5239         void __iomem *ioaddr = tp->mmio_addr;
5240         unsigned long flags;
5241
5242         if (netif_running(dev)) {
5243                 spin_lock_irqsave(&tp->lock, flags);
5244                 rtl8169_rx_missed(dev, ioaddr);
5245                 spin_unlock_irqrestore(&tp->lock, flags);
5246         }
5247
5248         return &dev->stats;
5249 }
5250
5251 static void rtl8169_net_suspend(struct net_device *dev)
5252 {
5253         struct rtl8169_private *tp = netdev_priv(dev);
5254
5255         if (!netif_running(dev))
5256                 return;
5257
5258         rtl_pll_power_down(tp);
5259
5260         netif_device_detach(dev);
5261         netif_stop_queue(dev);
5262 }
5263
5264 #ifdef CONFIG_PM
5265
5266 static int rtl8169_suspend(struct device *device)
5267 {
5268         struct pci_dev *pdev = to_pci_dev(device);
5269         struct net_device *dev = pci_get_drvdata(pdev);
5270
5271         rtl8169_net_suspend(dev);
5272
5273         return 0;
5274 }
5275
5276 static void __rtl8169_resume(struct net_device *dev)
5277 {
5278         struct rtl8169_private *tp = netdev_priv(dev);
5279
5280         netif_device_attach(dev);
5281
5282         rtl_pll_power_up(tp);
5283
5284         rtl8169_schedule_work(dev, rtl8169_reset_task);
5285 }
5286
5287 static int rtl8169_resume(struct device *device)
5288 {
5289         struct pci_dev *pdev = to_pci_dev(device);
5290         struct net_device *dev = pci_get_drvdata(pdev);
5291         struct rtl8169_private *tp = netdev_priv(dev);
5292
5293         rtl8169_init_phy(dev, tp);
5294
5295         if (netif_running(dev))
5296                 __rtl8169_resume(dev);
5297
5298         return 0;
5299 }
5300
5301 static int rtl8169_runtime_suspend(struct device *device)
5302 {
5303         struct pci_dev *pdev = to_pci_dev(device);
5304         struct net_device *dev = pci_get_drvdata(pdev);
5305         struct rtl8169_private *tp = netdev_priv(dev);
5306
5307         if (!tp->TxDescArray)
5308                 return 0;
5309
5310         spin_lock_irq(&tp->lock);
5311         tp->saved_wolopts = __rtl8169_get_wol(tp);
5312         __rtl8169_set_wol(tp, WAKE_ANY);
5313         spin_unlock_irq(&tp->lock);
5314
5315         rtl8169_net_suspend(dev);
5316
5317         return 0;
5318 }
5319
5320 static int rtl8169_runtime_resume(struct device *device)
5321 {
5322         struct pci_dev *pdev = to_pci_dev(device);
5323         struct net_device *dev = pci_get_drvdata(pdev);
5324         struct rtl8169_private *tp = netdev_priv(dev);
5325
5326         if (!tp->TxDescArray)
5327                 return 0;
5328
5329         spin_lock_irq(&tp->lock);
5330         __rtl8169_set_wol(tp, tp->saved_wolopts);
5331         tp->saved_wolopts = 0;
5332         spin_unlock_irq(&tp->lock);
5333
5334         rtl8169_init_phy(dev, tp);
5335
5336         __rtl8169_resume(dev);
5337
5338         return 0;
5339 }
5340
5341 static int rtl8169_runtime_idle(struct device *device)
5342 {
5343         struct pci_dev *pdev = to_pci_dev(device);
5344         struct net_device *dev = pci_get_drvdata(pdev);
5345         struct rtl8169_private *tp = netdev_priv(dev);
5346
5347         return tp->TxDescArray ? -EBUSY : 0;
5348 }
5349
5350 static const struct dev_pm_ops rtl8169_pm_ops = {
5351         .suspend                = rtl8169_suspend,
5352         .resume                 = rtl8169_resume,
5353         .freeze                 = rtl8169_suspend,
5354         .thaw                   = rtl8169_resume,
5355         .poweroff               = rtl8169_suspend,
5356         .restore                = rtl8169_resume,
5357         .runtime_suspend        = rtl8169_runtime_suspend,
5358         .runtime_resume         = rtl8169_runtime_resume,
5359         .runtime_idle           = rtl8169_runtime_idle,
5360 };
5361
5362 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5363
5364 #else /* !CONFIG_PM */
5365
5366 #define RTL8169_PM_OPS  NULL
5367
5368 #endif /* !CONFIG_PM */
5369
5370 static void rtl_shutdown(struct pci_dev *pdev)
5371 {
5372         struct net_device *dev = pci_get_drvdata(pdev);
5373         struct rtl8169_private *tp = netdev_priv(dev);
5374         void __iomem *ioaddr = tp->mmio_addr;
5375
5376         rtl8169_net_suspend(dev);
5377
5378         /* Restore original MAC address */
5379         rtl_rar_set(tp, dev->perm_addr);
5380
5381         spin_lock_irq(&tp->lock);
5382
5383         rtl8169_asic_down(ioaddr);
5384
5385         spin_unlock_irq(&tp->lock);
5386
5387         if (system_state == SYSTEM_POWER_OFF) {
5388                 /* WoL fails with some 8168 when the receiver is disabled. */
5389                 if (tp->features & RTL_FEATURE_WOL) {
5390                         pci_clear_master(pdev);
5391
5392                         RTL_W8(ChipCmd, CmdRxEnb);
5393                         /* PCI commit */
5394                         RTL_R8(ChipCmd);
5395                 }
5396
5397                 pci_wake_from_d3(pdev, true);
5398                 pci_set_power_state(pdev, PCI_D3hot);
5399         }
5400 }
5401
5402 static struct pci_driver rtl8169_pci_driver = {
5403         .name           = MODULENAME,
5404         .id_table       = rtl8169_pci_tbl,
5405         .probe          = rtl8169_init_one,
5406         .remove         = __devexit_p(rtl8169_remove_one),
5407         .shutdown       = rtl_shutdown,
5408         .driver.pm      = RTL8169_PM_OPS,
5409 };
5410
5411 static int __init rtl8169_init_module(void)
5412 {
5413         return pci_register_driver(&rtl8169_pci_driver);
5414 }
5415
5416 static void __exit rtl8169_cleanup_module(void)
5417 {
5418         pci_unregister_driver(&rtl8169_pci_driver);
5419 }
5420
5421 module_init(rtl8169_init_module);
5422 module_exit(rtl8169_cleanup_module);