r8169: convert to new VLAN model.
[linux-2.6.git] / drivers / net / r8169.c
1 /*
2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3  *
4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6  * Copyright (c) a lot of people too. Please respect their work.
7  *
8  * See MAINTAINERS file for support contact information.
9  */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28
29 #include <asm/system.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32
33 #define RTL8169_VERSION "2.3LK-NAPI"
34 #define MODULENAME "r8169"
35 #define PFX MODULENAME ": "
36
37 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
38 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
39 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
40
41 #ifdef RTL8169_DEBUG
42 #define assert(expr) \
43         if (!(expr)) {                                  \
44                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
45                 #expr,__FILE__,__func__,__LINE__);              \
46         }
47 #define dprintk(fmt, args...) \
48         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
49 #else
50 #define assert(expr) do {} while (0)
51 #define dprintk(fmt, args...)   do {} while (0)
52 #endif /* RTL8169_DEBUG */
53
54 #define R8169_MSG_DEFAULT \
55         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
56
57 #define TX_BUFFS_AVAIL(tp) \
58         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
59
60 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
61    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
62 static const int multicast_filter_limit = 32;
63
64 /* MAC address length */
65 #define MAC_ADDR_LEN    6
66
67 #define MAX_READ_REQUEST_SHIFT  12
68 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
69 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
70 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
71 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
72 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
73
74 #define R8169_REGS_SIZE         256
75 #define R8169_NAPI_WEIGHT       64
76 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
77 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
78 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
79 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
80 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
81
82 #define RTL8169_TX_TIMEOUT      (6*HZ)
83 #define RTL8169_PHY_TIMEOUT     (10*HZ)
84
85 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
86 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
87 #define RTL_EEPROM_SIG_ADDR     0x0000
88
89 /* write/read MMIO register */
90 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
91 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
92 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
93 #define RTL_R8(reg)             readb (ioaddr + (reg))
94 #define RTL_R16(reg)            readw (ioaddr + (reg))
95 #define RTL_R32(reg)            readl (ioaddr + (reg))
96
97 enum mac_version {
98         RTL_GIGA_MAC_NONE   = 0x00,
99         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
100         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
101         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
102         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
103         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
104         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
105         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
106         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
107         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
108         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
109         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
110         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
111         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
112         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
113         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
114         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
115         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
116         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
117         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
118         RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
119         RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
120         RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
121         RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
122         RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
123         RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
124         RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
125         RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
126         RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
127         RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E
128         RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E
129 };
130
131 #define _R(NAME,MAC,MASK) \
132         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
133
134 static const struct {
135         const char *name;
136         u8 mac_version;
137         u32 RxConfigMask;       /* Clears the bits supported by this chip */
138 } rtl_chip_info[] = {
139         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
140         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
141         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
142         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
143         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
144         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
145         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
146         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
147         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
148         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
149         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
150         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
151         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
152         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
153         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
154         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
155         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
156         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
157         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
158         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
159         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
160         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
161         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
162         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
163         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
164         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
165         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
166         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_28, 0xff7e1880), // PCI-E
167         _R("RTL8105e",          RTL_GIGA_MAC_VER_29, 0xff7e1880), // PCI-E
168         _R("RTL8105e",          RTL_GIGA_MAC_VER_30, 0xff7e1880)  // PCI-E
169 };
170 #undef _R
171
172 enum cfg_version {
173         RTL_CFG_0 = 0x00,
174         RTL_CFG_1,
175         RTL_CFG_2
176 };
177
178 static void rtl_hw_start_8169(struct net_device *);
179 static void rtl_hw_start_8168(struct net_device *);
180 static void rtl_hw_start_8101(struct net_device *);
181
182 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
183         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
184         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
185         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
186         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
187         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
188         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
189         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
190         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
191         { PCI_VENDOR_ID_LINKSYS,                0x1032,
192                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
193         { 0x0001,                               0x8168,
194                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
195         {0,},
196 };
197
198 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
199
200 static int rx_buf_sz = 16383;
201 static int use_dac;
202 static struct {
203         u32 msg_enable;
204 } debug = { -1 };
205
206 enum rtl_registers {
207         MAC0            = 0,    /* Ethernet hardware address. */
208         MAC4            = 4,
209         MAR0            = 8,    /* Multicast filter. */
210         CounterAddrLow          = 0x10,
211         CounterAddrHigh         = 0x14,
212         TxDescStartAddrLow      = 0x20,
213         TxDescStartAddrHigh     = 0x24,
214         TxHDescStartAddrLow     = 0x28,
215         TxHDescStartAddrHigh    = 0x2c,
216         FLASH           = 0x30,
217         ERSR            = 0x36,
218         ChipCmd         = 0x37,
219         TxPoll          = 0x38,
220         IntrMask        = 0x3c,
221         IntrStatus      = 0x3e,
222         TxConfig        = 0x40,
223         RxConfig        = 0x44,
224         RxMissed        = 0x4c,
225         Cfg9346         = 0x50,
226         Config0         = 0x51,
227         Config1         = 0x52,
228         Config2         = 0x53,
229         Config3         = 0x54,
230         Config4         = 0x55,
231         Config5         = 0x56,
232         MultiIntr       = 0x5c,
233         PHYAR           = 0x60,
234         PHYstatus       = 0x6c,
235         RxMaxSize       = 0xda,
236         CPlusCmd        = 0xe0,
237         IntrMitigate    = 0xe2,
238         RxDescAddrLow   = 0xe4,
239         RxDescAddrHigh  = 0xe8,
240         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
241
242 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
243
244         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
245
246 #define TxPacketMax     (8064 >> 7)
247
248         FuncEvent       = 0xf0,
249         FuncEventMask   = 0xf4,
250         FuncPresetState = 0xf8,
251         FuncForceEvent  = 0xfc,
252 };
253
254 enum rtl8110_registers {
255         TBICSR                  = 0x64,
256         TBI_ANAR                = 0x68,
257         TBI_LPAR                = 0x6a,
258 };
259
260 enum rtl8168_8101_registers {
261         CSIDR                   = 0x64,
262         CSIAR                   = 0x68,
263 #define CSIAR_FLAG                      0x80000000
264 #define CSIAR_WRITE_CMD                 0x80000000
265 #define CSIAR_BYTE_ENABLE               0x0f
266 #define CSIAR_BYTE_ENABLE_SHIFT         12
267 #define CSIAR_ADDR_MASK                 0x0fff
268         PMCH                    = 0x6f,
269         EPHYAR                  = 0x80,
270 #define EPHYAR_FLAG                     0x80000000
271 #define EPHYAR_WRITE_CMD                0x80000000
272 #define EPHYAR_REG_MASK                 0x1f
273 #define EPHYAR_REG_SHIFT                16
274 #define EPHYAR_DATA_MASK                0xffff
275         DLLPR                   = 0xd0,
276 #define PM_SWITCH                       (1 << 6)
277         DBG_REG                 = 0xd1,
278 #define FIX_NAK_1                       (1 << 4)
279 #define FIX_NAK_2                       (1 << 3)
280         TWSI                    = 0xd2,
281         MCU                     = 0xd3,
282 #define EN_NDP                          (1 << 3)
283 #define EN_OOB_RESET                    (1 << 2)
284         EFUSEAR                 = 0xdc,
285 #define EFUSEAR_FLAG                    0x80000000
286 #define EFUSEAR_WRITE_CMD               0x80000000
287 #define EFUSEAR_READ_CMD                0x00000000
288 #define EFUSEAR_REG_MASK                0x03ff
289 #define EFUSEAR_REG_SHIFT               8
290 #define EFUSEAR_DATA_MASK               0xff
291 };
292
293 enum rtl8168_registers {
294         ERIDR                   = 0x70,
295         ERIAR                   = 0x74,
296 #define ERIAR_FLAG                      0x80000000
297 #define ERIAR_WRITE_CMD                 0x80000000
298 #define ERIAR_READ_CMD                  0x00000000
299 #define ERIAR_ADDR_BYTE_ALIGN           4
300 #define ERIAR_EXGMAC                    0
301 #define ERIAR_MSIX                      1
302 #define ERIAR_ASF                       2
303 #define ERIAR_TYPE_SHIFT                16
304 #define ERIAR_BYTEEN                    0x0f
305 #define ERIAR_BYTEEN_SHIFT              12
306         EPHY_RXER_NUM           = 0x7c,
307         OCPDR                   = 0xb0, /* OCP GPHY access */
308 #define OCPDR_WRITE_CMD                 0x80000000
309 #define OCPDR_READ_CMD                  0x00000000
310 #define OCPDR_REG_MASK                  0x7f
311 #define OCPDR_GPHY_REG_SHIFT            16
312 #define OCPDR_DATA_MASK                 0xffff
313         OCPAR                   = 0xb4,
314 #define OCPAR_FLAG                      0x80000000
315 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
316 #define OCPAR_GPHY_READ_CMD             0x0000f060
317         RDSAR1                  = 0xd0  /* 8168c only. Undocumented on 8168dp */
318 };
319
320 enum rtl_register_content {
321         /* InterruptStatusBits */
322         SYSErr          = 0x8000,
323         PCSTimeout      = 0x4000,
324         SWInt           = 0x0100,
325         TxDescUnavail   = 0x0080,
326         RxFIFOOver      = 0x0040,
327         LinkChg         = 0x0020,
328         RxOverflow      = 0x0010,
329         TxErr           = 0x0008,
330         TxOK            = 0x0004,
331         RxErr           = 0x0002,
332         RxOK            = 0x0001,
333
334         /* RxStatusDesc */
335         RxFOVF  = (1 << 23),
336         RxRWT   = (1 << 22),
337         RxRES   = (1 << 21),
338         RxRUNT  = (1 << 20),
339         RxCRC   = (1 << 19),
340
341         /* ChipCmdBits */
342         CmdReset        = 0x10,
343         CmdRxEnb        = 0x08,
344         CmdTxEnb        = 0x04,
345         RxBufEmpty      = 0x01,
346
347         /* TXPoll register p.5 */
348         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
349         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
350         FSWInt          = 0x01,         /* Forced software interrupt */
351
352         /* Cfg9346Bits */
353         Cfg9346_Lock    = 0x00,
354         Cfg9346_Unlock  = 0xc0,
355
356         /* rx_mode_bits */
357         AcceptErr       = 0x20,
358         AcceptRunt      = 0x10,
359         AcceptBroadcast = 0x08,
360         AcceptMulticast = 0x04,
361         AcceptMyPhys    = 0x02,
362         AcceptAllPhys   = 0x01,
363
364         /* RxConfigBits */
365         RxCfgFIFOShift  = 13,
366         RxCfgDMAShift   =  8,
367
368         /* TxConfigBits */
369         TxInterFrameGapShift = 24,
370         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
371
372         /* Config1 register p.24 */
373         LEDS1           = (1 << 7),
374         LEDS0           = (1 << 6),
375         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
376         Speed_down      = (1 << 4),
377         MEMMAP          = (1 << 3),
378         IOMAP           = (1 << 2),
379         VPD             = (1 << 1),
380         PMEnable        = (1 << 0),     /* Power Management Enable */
381
382         /* Config2 register p. 25 */
383         PCI_Clock_66MHz = 0x01,
384         PCI_Clock_33MHz = 0x00,
385
386         /* Config3 register p.25 */
387         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
388         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
389         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
390
391         /* Config5 register p.27 */
392         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
393         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
394         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
395         LanWake         = (1 << 1),     /* LanWake enable/disable */
396         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
397
398         /* TBICSR p.28 */
399         TBIReset        = 0x80000000,
400         TBILoopback     = 0x40000000,
401         TBINwEnable     = 0x20000000,
402         TBINwRestart    = 0x10000000,
403         TBILinkOk       = 0x02000000,
404         TBINwComplete   = 0x01000000,
405
406         /* CPlusCmd p.31 */
407         EnableBist      = (1 << 15),    // 8168 8101
408         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
409         Normal_mode     = (1 << 13),    // unused
410         Force_half_dup  = (1 << 12),    // 8168 8101
411         Force_rxflow_en = (1 << 11),    // 8168 8101
412         Force_txflow_en = (1 << 10),    // 8168 8101
413         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
414         ASF             = (1 << 8),     // 8168 8101
415         PktCntrDisable  = (1 << 7),     // 8168 8101
416         Mac_dbgo_sel    = 0x001c,       // 8168
417         RxVlan          = (1 << 6),
418         RxChkSum        = (1 << 5),
419         PCIDAC          = (1 << 4),
420         PCIMulRW        = (1 << 3),
421         INTT_0          = 0x0000,       // 8168
422         INTT_1          = 0x0001,       // 8168
423         INTT_2          = 0x0002,       // 8168
424         INTT_3          = 0x0003,       // 8168
425
426         /* rtl8169_PHYstatus */
427         TBI_Enable      = 0x80,
428         TxFlowCtrl      = 0x40,
429         RxFlowCtrl      = 0x20,
430         _1000bpsF       = 0x10,
431         _100bps         = 0x08,
432         _10bps          = 0x04,
433         LinkStatus      = 0x02,
434         FullDup         = 0x01,
435
436         /* _TBICSRBit */
437         TBILinkOK       = 0x02000000,
438
439         /* DumpCounterCommand */
440         CounterDump     = 0x8,
441 };
442
443 enum desc_status_bit {
444         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
445         RingEnd         = (1 << 30), /* End of descriptor ring */
446         FirstFrag       = (1 << 29), /* First segment of a packet */
447         LastFrag        = (1 << 28), /* Final segment of a packet */
448
449         /* Tx private */
450         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
451         MSSShift        = 16,        /* MSS value position */
452         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
453         IPCS            = (1 << 18), /* Calculate IP checksum */
454         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
455         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
456         TxVlanTag       = (1 << 17), /* Add VLAN tag */
457
458         /* Rx private */
459         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
460         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
461
462 #define RxProtoUDP      (PID1)
463 #define RxProtoTCP      (PID0)
464 #define RxProtoIP       (PID1 | PID0)
465 #define RxProtoMask     RxProtoIP
466
467         IPFail          = (1 << 16), /* IP checksum failed */
468         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
469         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
470         RxVlanTag       = (1 << 16), /* VLAN tag available */
471 };
472
473 #define RsvdMask        0x3fffc000
474
475 struct TxDesc {
476         __le32 opts1;
477         __le32 opts2;
478         __le64 addr;
479 };
480
481 struct RxDesc {
482         __le32 opts1;
483         __le32 opts2;
484         __le64 addr;
485 };
486
487 struct ring_info {
488         struct sk_buff  *skb;
489         u32             len;
490         u8              __pad[sizeof(void *) - sizeof(u32)];
491 };
492
493 enum features {
494         RTL_FEATURE_WOL         = (1 << 0),
495         RTL_FEATURE_MSI         = (1 << 1),
496         RTL_FEATURE_GMII        = (1 << 2),
497 };
498
499 struct rtl8169_counters {
500         __le64  tx_packets;
501         __le64  rx_packets;
502         __le64  tx_errors;
503         __le32  rx_errors;
504         __le16  rx_missed;
505         __le16  align_errors;
506         __le32  tx_one_collision;
507         __le32  tx_multi_collision;
508         __le64  rx_unicast;
509         __le64  rx_broadcast;
510         __le32  rx_multicast;
511         __le16  tx_aborted;
512         __le16  tx_underun;
513 };
514
515 struct rtl8169_private {
516         void __iomem *mmio_addr;        /* memory map physical address */
517         struct pci_dev *pci_dev;        /* Index of PCI device */
518         struct net_device *dev;
519         struct napi_struct napi;
520         spinlock_t lock;                /* spin lock flag */
521         u32 msg_enable;
522         int chipset;
523         int mac_version;
524         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
525         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
526         u32 dirty_rx;
527         u32 dirty_tx;
528         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
529         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
530         dma_addr_t TxPhyAddr;
531         dma_addr_t RxPhyAddr;
532         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
533         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
534         struct timer_list timer;
535         u16 cp_cmd;
536         u16 intr_event;
537         u16 napi_event;
538         u16 intr_mask;
539         int phy_1000_ctrl_reg;
540
541         struct mdio_ops {
542                 void (*write)(void __iomem *, int, int);
543                 int (*read)(void __iomem *, int);
544         } mdio_ops;
545
546         struct pll_power_ops {
547                 void (*down)(struct rtl8169_private *);
548                 void (*up)(struct rtl8169_private *);
549         } pll_power_ops;
550
551         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
552         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
553         void (*phy_reset_enable)(struct rtl8169_private *tp);
554         void (*hw_start)(struct net_device *);
555         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
556         unsigned int (*link_ok)(void __iomem *);
557         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
558         int pcie_cap;
559         struct delayed_work task;
560         unsigned features;
561
562         struct mii_if_info mii;
563         struct rtl8169_counters counters;
564         u32 saved_wolopts;
565
566         const struct firmware *fw;
567 };
568
569 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
570 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
571 module_param(use_dac, int, 0);
572 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
573 module_param_named(debug, debug.msg_enable, int, 0);
574 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
575 MODULE_LICENSE("GPL");
576 MODULE_VERSION(RTL8169_VERSION);
577 MODULE_FIRMWARE(FIRMWARE_8168D_1);
578 MODULE_FIRMWARE(FIRMWARE_8168D_2);
579 MODULE_FIRMWARE(FIRMWARE_8105E_1);
580
581 static int rtl8169_open(struct net_device *dev);
582 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
583                                       struct net_device *dev);
584 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
585 static int rtl8169_init_ring(struct net_device *dev);
586 static void rtl_hw_start(struct net_device *dev);
587 static int rtl8169_close(struct net_device *dev);
588 static void rtl_set_rx_mode(struct net_device *dev);
589 static void rtl8169_tx_timeout(struct net_device *dev);
590 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
591 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
592                                 void __iomem *, u32 budget);
593 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
594 static void rtl8169_down(struct net_device *dev);
595 static void rtl8169_rx_clear(struct rtl8169_private *tp);
596 static int rtl8169_poll(struct napi_struct *napi, int budget);
597
598 static const unsigned int rtl8169_rx_config =
599         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
600
601 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
602 {
603         void __iomem *ioaddr = tp->mmio_addr;
604         int i;
605
606         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
607         for (i = 0; i < 20; i++) {
608                 udelay(100);
609                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
610                         break;
611         }
612         return RTL_R32(OCPDR);
613 }
614
615 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
616 {
617         void __iomem *ioaddr = tp->mmio_addr;
618         int i;
619
620         RTL_W32(OCPDR, data);
621         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
622         for (i = 0; i < 20; i++) {
623                 udelay(100);
624                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
625                         break;
626         }
627 }
628
629 static void rtl8168_oob_notify(void __iomem *ioaddr, u8 cmd)
630 {
631         int i;
632
633         RTL_W8(ERIDR, cmd);
634         RTL_W32(ERIAR, 0x800010e8);
635         msleep(2);
636         for (i = 0; i < 5; i++) {
637                 udelay(100);
638                 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
639                         break;
640         }
641
642         ocp_write(ioaddr, 0x1, 0x30, 0x00000001);
643 }
644
645 #define OOB_CMD_RESET           0x00
646 #define OOB_CMD_DRIVER_START    0x05
647 #define OOB_CMD_DRIVER_STOP     0x06
648
649 static void rtl8168_driver_start(struct rtl8169_private *tp)
650 {
651         int i;
652
653         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
654
655         for (i = 0; i < 10; i++) {
656                 msleep(10);
657                 if (ocp_read(tp, 0x0f, 0x0010) & 0x00000800)
658                         break;
659         }
660 }
661
662 static void rtl8168_driver_stop(struct rtl8169_private *tp)
663 {
664         int i;
665
666         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
667
668         for (i = 0; i < 10; i++) {
669                 msleep(10);
670                 if ((ocp_read(tp, 0x0f, 0x0010) & 0x00000800) == 0)
671                         break;
672         }
673 }
674
675
676 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
677 {
678         int i;
679
680         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
681
682         for (i = 20; i > 0; i--) {
683                 /*
684                  * Check if the RTL8169 has completed writing to the specified
685                  * MII register.
686                  */
687                 if (!(RTL_R32(PHYAR) & 0x80000000))
688                         break;
689                 udelay(25);
690         }
691         /*
692          * According to hardware specs a 20us delay is required after write
693          * complete indication, but before sending next command.
694          */
695         udelay(20);
696 }
697
698 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
699 {
700         int i, value = -1;
701
702         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
703
704         for (i = 20; i > 0; i--) {
705                 /*
706                  * Check if the RTL8169 has completed retrieving data from
707                  * the specified MII register.
708                  */
709                 if (RTL_R32(PHYAR) & 0x80000000) {
710                         value = RTL_R32(PHYAR) & 0xffff;
711                         break;
712                 }
713                 udelay(25);
714         }
715         /*
716          * According to hardware specs a 20us delay is required after read
717          * complete indication, but before sending next command.
718          */
719         udelay(20);
720
721         return value;
722 }
723
724 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
725 {
726         int i;
727
728         RTL_W32(OCPDR, data |
729                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
730         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
731         RTL_W32(EPHY_RXER_NUM, 0);
732
733         for (i = 0; i < 100; i++) {
734                 mdelay(1);
735                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
736                         break;
737         }
738 }
739
740 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
741 {
742         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
743                 (value & OCPDR_DATA_MASK));
744 }
745
746 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
747 {
748         int i;
749
750         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
751
752         mdelay(1);
753         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
754         RTL_W32(EPHY_RXER_NUM, 0);
755
756         for (i = 0; i < 100; i++) {
757                 mdelay(1);
758                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
759                         break;
760         }
761
762         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
763 }
764
765 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
766
767 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
768 {
769         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
770 }
771
772 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
773 {
774         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
775 }
776
777 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
778 {
779         r8168dp_2_mdio_start(ioaddr);
780
781         r8169_mdio_write(ioaddr, reg_addr, value);
782
783         r8168dp_2_mdio_stop(ioaddr);
784 }
785
786 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
787 {
788         int value;
789
790         r8168dp_2_mdio_start(ioaddr);
791
792         value = r8169_mdio_read(ioaddr, reg_addr);
793
794         r8168dp_2_mdio_stop(ioaddr);
795
796         return value;
797 }
798
799 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
800 {
801         tp->mdio_ops.write(tp->mmio_addr, location, val);
802 }
803
804 static int rtl_readphy(struct rtl8169_private *tp, int location)
805 {
806         return tp->mdio_ops.read(tp->mmio_addr, location);
807 }
808
809 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
810 {
811         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
812 }
813
814 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
815 {
816         int val;
817
818         val = rtl_readphy(tp, reg_addr);
819         rtl_writephy(tp, reg_addr, (val | p) & ~m);
820 }
821
822 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
823                            int val)
824 {
825         struct rtl8169_private *tp = netdev_priv(dev);
826
827         rtl_writephy(tp, location, val);
828 }
829
830 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
831 {
832         struct rtl8169_private *tp = netdev_priv(dev);
833
834         return rtl_readphy(tp, location);
835 }
836
837 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
838 {
839         unsigned int i;
840
841         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
842                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
843
844         for (i = 0; i < 100; i++) {
845                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
846                         break;
847                 udelay(10);
848         }
849 }
850
851 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
852 {
853         u16 value = 0xffff;
854         unsigned int i;
855
856         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
857
858         for (i = 0; i < 100; i++) {
859                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
860                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
861                         break;
862                 }
863                 udelay(10);
864         }
865
866         return value;
867 }
868
869 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
870 {
871         unsigned int i;
872
873         RTL_W32(CSIDR, value);
874         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
875                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
876
877         for (i = 0; i < 100; i++) {
878                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
879                         break;
880                 udelay(10);
881         }
882 }
883
884 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
885 {
886         u32 value = ~0x00;
887         unsigned int i;
888
889         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
890                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
891
892         for (i = 0; i < 100; i++) {
893                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
894                         value = RTL_R32(CSIDR);
895                         break;
896                 }
897                 udelay(10);
898         }
899
900         return value;
901 }
902
903 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
904 {
905         u8 value = 0xff;
906         unsigned int i;
907
908         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
909
910         for (i = 0; i < 300; i++) {
911                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
912                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
913                         break;
914                 }
915                 udelay(100);
916         }
917
918         return value;
919 }
920
921 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
922 {
923         RTL_W16(IntrMask, 0x0000);
924
925         RTL_W16(IntrStatus, 0xffff);
926 }
927
928 static void rtl8169_asic_down(void __iomem *ioaddr)
929 {
930         RTL_W8(ChipCmd, 0x00);
931         rtl8169_irq_mask_and_ack(ioaddr);
932         RTL_R16(CPlusCmd);
933 }
934
935 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
936 {
937         void __iomem *ioaddr = tp->mmio_addr;
938
939         return RTL_R32(TBICSR) & TBIReset;
940 }
941
942 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
943 {
944         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
945 }
946
947 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
948 {
949         return RTL_R32(TBICSR) & TBILinkOk;
950 }
951
952 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
953 {
954         return RTL_R8(PHYstatus) & LinkStatus;
955 }
956
957 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
958 {
959         void __iomem *ioaddr = tp->mmio_addr;
960
961         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
962 }
963
964 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
965 {
966         unsigned int val;
967
968         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
969         rtl_writephy(tp, MII_BMCR, val & 0xffff);
970 }
971
972 static void __rtl8169_check_link_status(struct net_device *dev,
973                                       struct rtl8169_private *tp,
974                                       void __iomem *ioaddr,
975                                       bool pm)
976 {
977         unsigned long flags;
978
979         spin_lock_irqsave(&tp->lock, flags);
980         if (tp->link_ok(ioaddr)) {
981                 /* This is to cancel a scheduled suspend if there's one. */
982                 if (pm)
983                         pm_request_resume(&tp->pci_dev->dev);
984                 netif_carrier_on(dev);
985                 if (net_ratelimit())
986                         netif_info(tp, ifup, dev, "link up\n");
987         } else {
988                 netif_carrier_off(dev);
989                 netif_info(tp, ifdown, dev, "link down\n");
990                 if (pm)
991                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
992         }
993         spin_unlock_irqrestore(&tp->lock, flags);
994 }
995
996 static void rtl8169_check_link_status(struct net_device *dev,
997                                       struct rtl8169_private *tp,
998                                       void __iomem *ioaddr)
999 {
1000         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1001 }
1002
1003 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1004
1005 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1006 {
1007         void __iomem *ioaddr = tp->mmio_addr;
1008         u8 options;
1009         u32 wolopts = 0;
1010
1011         options = RTL_R8(Config1);
1012         if (!(options & PMEnable))
1013                 return 0;
1014
1015         options = RTL_R8(Config3);
1016         if (options & LinkUp)
1017                 wolopts |= WAKE_PHY;
1018         if (options & MagicPacket)
1019                 wolopts |= WAKE_MAGIC;
1020
1021         options = RTL_R8(Config5);
1022         if (options & UWF)
1023                 wolopts |= WAKE_UCAST;
1024         if (options & BWF)
1025                 wolopts |= WAKE_BCAST;
1026         if (options & MWF)
1027                 wolopts |= WAKE_MCAST;
1028
1029         return wolopts;
1030 }
1031
1032 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1033 {
1034         struct rtl8169_private *tp = netdev_priv(dev);
1035
1036         spin_lock_irq(&tp->lock);
1037
1038         wol->supported = WAKE_ANY;
1039         wol->wolopts = __rtl8169_get_wol(tp);
1040
1041         spin_unlock_irq(&tp->lock);
1042 }
1043
1044 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1045 {
1046         void __iomem *ioaddr = tp->mmio_addr;
1047         unsigned int i;
1048         static const struct {
1049                 u32 opt;
1050                 u16 reg;
1051                 u8  mask;
1052         } cfg[] = {
1053                 { WAKE_ANY,   Config1, PMEnable },
1054                 { WAKE_PHY,   Config3, LinkUp },
1055                 { WAKE_MAGIC, Config3, MagicPacket },
1056                 { WAKE_UCAST, Config5, UWF },
1057                 { WAKE_BCAST, Config5, BWF },
1058                 { WAKE_MCAST, Config5, MWF },
1059                 { WAKE_ANY,   Config5, LanWake }
1060         };
1061
1062         RTL_W8(Cfg9346, Cfg9346_Unlock);
1063
1064         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1065                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1066                 if (wolopts & cfg[i].opt)
1067                         options |= cfg[i].mask;
1068                 RTL_W8(cfg[i].reg, options);
1069         }
1070
1071         RTL_W8(Cfg9346, Cfg9346_Lock);
1072 }
1073
1074 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1075 {
1076         struct rtl8169_private *tp = netdev_priv(dev);
1077
1078         spin_lock_irq(&tp->lock);
1079
1080         if (wol->wolopts)
1081                 tp->features |= RTL_FEATURE_WOL;
1082         else
1083                 tp->features &= ~RTL_FEATURE_WOL;
1084         __rtl8169_set_wol(tp, wol->wolopts);
1085         spin_unlock_irq(&tp->lock);
1086
1087         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1088
1089         return 0;
1090 }
1091
1092 static void rtl8169_get_drvinfo(struct net_device *dev,
1093                                 struct ethtool_drvinfo *info)
1094 {
1095         struct rtl8169_private *tp = netdev_priv(dev);
1096
1097         strcpy(info->driver, MODULENAME);
1098         strcpy(info->version, RTL8169_VERSION);
1099         strcpy(info->bus_info, pci_name(tp->pci_dev));
1100 }
1101
1102 static int rtl8169_get_regs_len(struct net_device *dev)
1103 {
1104         return R8169_REGS_SIZE;
1105 }
1106
1107 static int rtl8169_set_speed_tbi(struct net_device *dev,
1108                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1109 {
1110         struct rtl8169_private *tp = netdev_priv(dev);
1111         void __iomem *ioaddr = tp->mmio_addr;
1112         int ret = 0;
1113         u32 reg;
1114
1115         reg = RTL_R32(TBICSR);
1116         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1117             (duplex == DUPLEX_FULL)) {
1118                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1119         } else if (autoneg == AUTONEG_ENABLE)
1120                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1121         else {
1122                 netif_warn(tp, link, dev,
1123                            "incorrect speed setting refused in TBI mode\n");
1124                 ret = -EOPNOTSUPP;
1125         }
1126
1127         return ret;
1128 }
1129
1130 static int rtl8169_set_speed_xmii(struct net_device *dev,
1131                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1132 {
1133         struct rtl8169_private *tp = netdev_priv(dev);
1134         int giga_ctrl, bmcr;
1135         int rc = -EINVAL;
1136
1137         rtl_writephy(tp, 0x1f, 0x0000);
1138
1139         if (autoneg == AUTONEG_ENABLE) {
1140                 int auto_nego;
1141
1142                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1143                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1144                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1145
1146                 if (adv & ADVERTISED_10baseT_Half)
1147                         auto_nego |= ADVERTISE_10HALF;
1148                 if (adv & ADVERTISED_10baseT_Full)
1149                         auto_nego |= ADVERTISE_10FULL;
1150                 if (adv & ADVERTISED_100baseT_Half)
1151                         auto_nego |= ADVERTISE_100HALF;
1152                 if (adv & ADVERTISED_100baseT_Full)
1153                         auto_nego |= ADVERTISE_100FULL;
1154
1155                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1156
1157                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1158                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1159
1160                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1161                 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1162                     (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1163                     (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1164                     (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1165                     (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1166                     (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1167                     (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1168                     (tp->mac_version != RTL_GIGA_MAC_VER_16) &&
1169                     (tp->mac_version != RTL_GIGA_MAC_VER_29) &&
1170                     (tp->mac_version != RTL_GIGA_MAC_VER_30)) {
1171                         if (adv & ADVERTISED_1000baseT_Half)
1172                                 giga_ctrl |= ADVERTISE_1000HALF;
1173                         if (adv & ADVERTISED_1000baseT_Full)
1174                                 giga_ctrl |= ADVERTISE_1000FULL;
1175                 } else if (adv & (ADVERTISED_1000baseT_Half |
1176                                   ADVERTISED_1000baseT_Full)) {
1177                         netif_info(tp, link, dev,
1178                                    "PHY does not support 1000Mbps\n");
1179                         goto out;
1180                 }
1181
1182                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1183
1184                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1185                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1186         } else {
1187                 giga_ctrl = 0;
1188
1189                 if (speed == SPEED_10)
1190                         bmcr = 0;
1191                 else if (speed == SPEED_100)
1192                         bmcr = BMCR_SPEED100;
1193                 else
1194                         goto out;
1195
1196                 if (duplex == DUPLEX_FULL)
1197                         bmcr |= BMCR_FULLDPLX;
1198         }
1199
1200         tp->phy_1000_ctrl_reg = giga_ctrl;
1201
1202         rtl_writephy(tp, MII_BMCR, bmcr);
1203
1204         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1205             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1206                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1207                         rtl_writephy(tp, 0x17, 0x2138);
1208                         rtl_writephy(tp, 0x0e, 0x0260);
1209                 } else {
1210                         rtl_writephy(tp, 0x17, 0x2108);
1211                         rtl_writephy(tp, 0x0e, 0x0000);
1212                 }
1213         }
1214
1215         rc = 0;
1216 out:
1217         return rc;
1218 }
1219
1220 static int rtl8169_set_speed(struct net_device *dev,
1221                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1222 {
1223         struct rtl8169_private *tp = netdev_priv(dev);
1224         int ret;
1225
1226         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1227
1228         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1229                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1230
1231         return ret;
1232 }
1233
1234 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1235 {
1236         struct rtl8169_private *tp = netdev_priv(dev);
1237         unsigned long flags;
1238         int ret;
1239
1240         spin_lock_irqsave(&tp->lock, flags);
1241         ret = rtl8169_set_speed(dev,
1242                 cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising);
1243         spin_unlock_irqrestore(&tp->lock, flags);
1244
1245         return ret;
1246 }
1247
1248 static u32 rtl8169_get_rx_csum(struct net_device *dev)
1249 {
1250         struct rtl8169_private *tp = netdev_priv(dev);
1251
1252         return tp->cp_cmd & RxChkSum;
1253 }
1254
1255 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1256 {
1257         struct rtl8169_private *tp = netdev_priv(dev);
1258         void __iomem *ioaddr = tp->mmio_addr;
1259         unsigned long flags;
1260
1261         spin_lock_irqsave(&tp->lock, flags);
1262
1263         if (data)
1264                 tp->cp_cmd |= RxChkSum;
1265         else
1266                 tp->cp_cmd &= ~RxChkSum;
1267
1268         RTL_W16(CPlusCmd, tp->cp_cmd);
1269         RTL_R16(CPlusCmd);
1270
1271         spin_unlock_irqrestore(&tp->lock, flags);
1272
1273         return 0;
1274 }
1275
1276 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1277                                       struct sk_buff *skb)
1278 {
1279         return (vlan_tx_tag_present(skb)) ?
1280                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1281 }
1282
1283 #define NETIF_F_HW_VLAN_TX_RX   (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX)
1284
1285 static void rtl8169_vlan_mode(struct net_device *dev)
1286 {
1287         struct rtl8169_private *tp = netdev_priv(dev);
1288         void __iomem *ioaddr = tp->mmio_addr;
1289         unsigned long flags;
1290
1291         spin_lock_irqsave(&tp->lock, flags);
1292         if (dev->features & NETIF_F_HW_VLAN_RX)
1293                 tp->cp_cmd |= RxVlan;
1294         else
1295                 tp->cp_cmd &= ~RxVlan;
1296         RTL_W16(CPlusCmd, tp->cp_cmd);
1297         /* PCI commit */
1298         RTL_R16(CPlusCmd);
1299         spin_unlock_irqrestore(&tp->lock, flags);
1300
1301         dev->vlan_features = dev->features &~ NETIF_F_HW_VLAN_TX_RX;
1302 }
1303
1304 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1305 {
1306         u32 opts2 = le32_to_cpu(desc->opts2);
1307
1308         if (opts2 & RxVlanTag)
1309                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1310
1311         desc->opts2 = 0;
1312 }
1313
1314 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1315 {
1316         struct rtl8169_private *tp = netdev_priv(dev);
1317         void __iomem *ioaddr = tp->mmio_addr;
1318         u32 status;
1319
1320         cmd->supported =
1321                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1322         cmd->port = PORT_FIBRE;
1323         cmd->transceiver = XCVR_INTERNAL;
1324
1325         status = RTL_R32(TBICSR);
1326         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1327         cmd->autoneg = !!(status & TBINwEnable);
1328
1329         cmd->speed = SPEED_1000;
1330         cmd->duplex = DUPLEX_FULL; /* Always set */
1331
1332         return 0;
1333 }
1334
1335 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1336 {
1337         struct rtl8169_private *tp = netdev_priv(dev);
1338
1339         return mii_ethtool_gset(&tp->mii, cmd);
1340 }
1341
1342 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1343 {
1344         struct rtl8169_private *tp = netdev_priv(dev);
1345         unsigned long flags;
1346         int rc;
1347
1348         spin_lock_irqsave(&tp->lock, flags);
1349
1350         rc = tp->get_settings(dev, cmd);
1351
1352         spin_unlock_irqrestore(&tp->lock, flags);
1353         return rc;
1354 }
1355
1356 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1357                              void *p)
1358 {
1359         struct rtl8169_private *tp = netdev_priv(dev);
1360         unsigned long flags;
1361
1362         if (regs->len > R8169_REGS_SIZE)
1363                 regs->len = R8169_REGS_SIZE;
1364
1365         spin_lock_irqsave(&tp->lock, flags);
1366         memcpy_fromio(p, tp->mmio_addr, regs->len);
1367         spin_unlock_irqrestore(&tp->lock, flags);
1368 }
1369
1370 static u32 rtl8169_get_msglevel(struct net_device *dev)
1371 {
1372         struct rtl8169_private *tp = netdev_priv(dev);
1373
1374         return tp->msg_enable;
1375 }
1376
1377 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1378 {
1379         struct rtl8169_private *tp = netdev_priv(dev);
1380
1381         tp->msg_enable = value;
1382 }
1383
1384 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1385         "tx_packets",
1386         "rx_packets",
1387         "tx_errors",
1388         "rx_errors",
1389         "rx_missed",
1390         "align_errors",
1391         "tx_single_collisions",
1392         "tx_multi_collisions",
1393         "unicast",
1394         "broadcast",
1395         "multicast",
1396         "tx_aborted",
1397         "tx_underrun",
1398 };
1399
1400 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1401 {
1402         switch (sset) {
1403         case ETH_SS_STATS:
1404                 return ARRAY_SIZE(rtl8169_gstrings);
1405         default:
1406                 return -EOPNOTSUPP;
1407         }
1408 }
1409
1410 static void rtl8169_update_counters(struct net_device *dev)
1411 {
1412         struct rtl8169_private *tp = netdev_priv(dev);
1413         void __iomem *ioaddr = tp->mmio_addr;
1414         struct rtl8169_counters *counters;
1415         dma_addr_t paddr;
1416         u32 cmd;
1417         int wait = 1000;
1418         struct device *d = &tp->pci_dev->dev;
1419
1420         /*
1421          * Some chips are unable to dump tally counters when the receiver
1422          * is disabled.
1423          */
1424         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1425                 return;
1426
1427         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1428         if (!counters)
1429                 return;
1430
1431         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1432         cmd = (u64)paddr & DMA_BIT_MASK(32);
1433         RTL_W32(CounterAddrLow, cmd);
1434         RTL_W32(CounterAddrLow, cmd | CounterDump);
1435
1436         while (wait--) {
1437                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1438                         /* copy updated counters */
1439                         memcpy(&tp->counters, counters, sizeof(*counters));
1440                         break;
1441                 }
1442                 udelay(10);
1443         }
1444
1445         RTL_W32(CounterAddrLow, 0);
1446         RTL_W32(CounterAddrHigh, 0);
1447
1448         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1449 }
1450
1451 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1452                                       struct ethtool_stats *stats, u64 *data)
1453 {
1454         struct rtl8169_private *tp = netdev_priv(dev);
1455
1456         ASSERT_RTNL();
1457
1458         rtl8169_update_counters(dev);
1459
1460         data[0] = le64_to_cpu(tp->counters.tx_packets);
1461         data[1] = le64_to_cpu(tp->counters.rx_packets);
1462         data[2] = le64_to_cpu(tp->counters.tx_errors);
1463         data[3] = le32_to_cpu(tp->counters.rx_errors);
1464         data[4] = le16_to_cpu(tp->counters.rx_missed);
1465         data[5] = le16_to_cpu(tp->counters.align_errors);
1466         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1467         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1468         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1469         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1470         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1471         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1472         data[12] = le16_to_cpu(tp->counters.tx_underun);
1473 }
1474
1475 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1476 {
1477         switch(stringset) {
1478         case ETH_SS_STATS:
1479                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1480                 break;
1481         }
1482 }
1483
1484 static int rtl8169_set_flags(struct net_device *dev, u32 data)
1485 {
1486         struct rtl8169_private *tp = netdev_priv(dev);
1487         unsigned long old_feat = dev->features;
1488         int rc;
1489
1490         if ((tp->mac_version == RTL_GIGA_MAC_VER_05) &&
1491             !(data & ETH_FLAG_RXVLAN)) {
1492                 netif_info(tp, drv, dev, "8110SCd requires hardware Rx VLAN\n");
1493                 return -EINVAL;
1494         }
1495
1496         rc = ethtool_op_set_flags(dev, data, ETH_FLAG_TXVLAN | ETH_FLAG_RXVLAN);
1497         if (rc)
1498                 return rc;
1499
1500         if ((old_feat ^ dev->features) & NETIF_F_HW_VLAN_RX)
1501                 rtl8169_vlan_mode(dev);
1502
1503         return 0;
1504 }
1505
1506 static const struct ethtool_ops rtl8169_ethtool_ops = {
1507         .get_drvinfo            = rtl8169_get_drvinfo,
1508         .get_regs_len           = rtl8169_get_regs_len,
1509         .get_link               = ethtool_op_get_link,
1510         .get_settings           = rtl8169_get_settings,
1511         .set_settings           = rtl8169_set_settings,
1512         .get_msglevel           = rtl8169_get_msglevel,
1513         .set_msglevel           = rtl8169_set_msglevel,
1514         .get_rx_csum            = rtl8169_get_rx_csum,
1515         .set_rx_csum            = rtl8169_set_rx_csum,
1516         .set_tx_csum            = ethtool_op_set_tx_csum,
1517         .set_sg                 = ethtool_op_set_sg,
1518         .set_tso                = ethtool_op_set_tso,
1519         .get_regs               = rtl8169_get_regs,
1520         .get_wol                = rtl8169_get_wol,
1521         .set_wol                = rtl8169_set_wol,
1522         .get_strings            = rtl8169_get_strings,
1523         .get_sset_count         = rtl8169_get_sset_count,
1524         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1525         .set_flags              = rtl8169_set_flags,
1526         .get_flags              = ethtool_op_get_flags,
1527 };
1528
1529 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1530                                     void __iomem *ioaddr)
1531 {
1532         /*
1533          * The driver currently handles the 8168Bf and the 8168Be identically
1534          * but they can be identified more specifically through the test below
1535          * if needed:
1536          *
1537          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1538          *
1539          * Same thing for the 8101Eb and the 8101Ec:
1540          *
1541          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1542          */
1543         static const struct {
1544                 u32 mask;
1545                 u32 val;
1546                 int mac_version;
1547         } mac_info[] = {
1548                 /* 8168D family. */
1549                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1550                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1551                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1552
1553                 /* 8168DP family. */
1554                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1555                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1556
1557                 /* 8168C family. */
1558                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1559                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1560                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1561                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1562                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1563                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1564                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1565                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1566                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1567
1568                 /* 8168B family. */
1569                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1570                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1571                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1572                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1573
1574                 /* 8101 family. */
1575                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1576                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1577                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1578                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1579                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1580                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1581                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1582                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1583                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1584                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1585                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1586                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1587                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1588                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1589                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1590                 /* FIXME: where did these entries come from ? -- FR */
1591                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1592                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1593
1594                 /* 8110 family. */
1595                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1596                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1597                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1598                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1599                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1600                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1601
1602                 /* Catch-all */
1603                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1604         }, *p = mac_info;
1605         u32 reg;
1606
1607         reg = RTL_R32(TxConfig);
1608         while ((reg & p->mask) != p->val)
1609                 p++;
1610         tp->mac_version = p->mac_version;
1611 }
1612
1613 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1614 {
1615         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1616 }
1617
1618 struct phy_reg {
1619         u16 reg;
1620         u16 val;
1621 };
1622
1623 static void rtl_writephy_batch(struct rtl8169_private *tp,
1624                                const struct phy_reg *regs, int len)
1625 {
1626         while (len-- > 0) {
1627                 rtl_writephy(tp, regs->reg, regs->val);
1628                 regs++;
1629         }
1630 }
1631
1632 #define PHY_READ                0x00000000
1633 #define PHY_DATA_OR             0x10000000
1634 #define PHY_DATA_AND            0x20000000
1635 #define PHY_BJMPN               0x30000000
1636 #define PHY_READ_EFUSE          0x40000000
1637 #define PHY_READ_MAC_BYTE       0x50000000
1638 #define PHY_WRITE_MAC_BYTE      0x60000000
1639 #define PHY_CLEAR_READCOUNT     0x70000000
1640 #define PHY_WRITE               0x80000000
1641 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1642 #define PHY_COMP_EQ_SKIPN       0xa0000000
1643 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1644 #define PHY_WRITE_PREVIOUS      0xc0000000
1645 #define PHY_SKIPN               0xd0000000
1646 #define PHY_DELAY_MS            0xe0000000
1647 #define PHY_WRITE_ERI_WORD      0xf0000000
1648
1649 static void
1650 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1651 {
1652         __le32 *phytable = (__le32 *)fw->data;
1653         struct net_device *dev = tp->dev;
1654         size_t index, fw_size = fw->size / sizeof(*phytable);
1655         u32 predata, count;
1656
1657         if (fw->size % sizeof(*phytable)) {
1658                 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1659                 return;
1660         }
1661
1662         for (index = 0; index < fw_size; index++) {
1663                 u32 action = le32_to_cpu(phytable[index]);
1664                 u32 regno = (action & 0x0fff0000) >> 16;
1665
1666                 switch(action & 0xf0000000) {
1667                 case PHY_READ:
1668                 case PHY_DATA_OR:
1669                 case PHY_DATA_AND:
1670                 case PHY_READ_EFUSE:
1671                 case PHY_CLEAR_READCOUNT:
1672                 case PHY_WRITE:
1673                 case PHY_WRITE_PREVIOUS:
1674                 case PHY_DELAY_MS:
1675                         break;
1676
1677                 case PHY_BJMPN:
1678                         if (regno > index) {
1679                                 netif_err(tp, probe, tp->dev,
1680                                         "Out of range of firmware\n");
1681                                 return;
1682                         }
1683                         break;
1684                 case PHY_READCOUNT_EQ_SKIP:
1685                         if (index + 2 >= fw_size) {
1686                                 netif_err(tp, probe, tp->dev,
1687                                         "Out of range of firmware\n");
1688                                 return;
1689                         }
1690                         break;
1691                 case PHY_COMP_EQ_SKIPN:
1692                 case PHY_COMP_NEQ_SKIPN:
1693                 case PHY_SKIPN:
1694                         if (index + 1 + regno >= fw_size) {
1695                                 netif_err(tp, probe, tp->dev,
1696                                         "Out of range of firmware\n");
1697                                 return;
1698                         }
1699                         break;
1700
1701                 case PHY_READ_MAC_BYTE:
1702                 case PHY_WRITE_MAC_BYTE:
1703                 case PHY_WRITE_ERI_WORD:
1704                 default:
1705                         netif_err(tp, probe, tp->dev,
1706                                   "Invalid action 0x%08x\n", action);
1707                         return;
1708                 }
1709         }
1710
1711         predata = 0;
1712         count = 0;
1713
1714         for (index = 0; index < fw_size; ) {
1715                 u32 action = le32_to_cpu(phytable[index]);
1716                 u32 data = action & 0x0000ffff;
1717                 u32 regno = (action & 0x0fff0000) >> 16;
1718
1719                 if (!action)
1720                         break;
1721
1722                 switch(action & 0xf0000000) {
1723                 case PHY_READ:
1724                         predata = rtl_readphy(tp, regno);
1725                         count++;
1726                         index++;
1727                         break;
1728                 case PHY_DATA_OR:
1729                         predata |= data;
1730                         index++;
1731                         break;
1732                 case PHY_DATA_AND:
1733                         predata &= data;
1734                         index++;
1735                         break;
1736                 case PHY_BJMPN:
1737                         index -= regno;
1738                         break;
1739                 case PHY_READ_EFUSE:
1740                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1741                         index++;
1742                         break;
1743                 case PHY_CLEAR_READCOUNT:
1744                         count = 0;
1745                         index++;
1746                         break;
1747                 case PHY_WRITE:
1748                         rtl_writephy(tp, regno, data);
1749                         index++;
1750                         break;
1751                 case PHY_READCOUNT_EQ_SKIP:
1752                         if (count == data)
1753                                 index += 2;
1754                         else
1755                                 index += 1;
1756                         break;
1757                 case PHY_COMP_EQ_SKIPN:
1758                         if (predata == data)
1759                                 index += regno;
1760                         index++;
1761                         break;
1762                 case PHY_COMP_NEQ_SKIPN:
1763                         if (predata != data)
1764                                 index += regno;
1765                         index++;
1766                         break;
1767                 case PHY_WRITE_PREVIOUS:
1768                         rtl_writephy(tp, regno, predata);
1769                         index++;
1770                         break;
1771                 case PHY_SKIPN:
1772                         index += regno + 1;
1773                         break;
1774                 case PHY_DELAY_MS:
1775                         mdelay(data);
1776                         index++;
1777                         break;
1778
1779                 case PHY_READ_MAC_BYTE:
1780                 case PHY_WRITE_MAC_BYTE:
1781                 case PHY_WRITE_ERI_WORD:
1782                 default:
1783                         BUG();
1784                 }
1785         }
1786 }
1787
1788 static void rtl_release_firmware(struct rtl8169_private *tp)
1789 {
1790         release_firmware(tp->fw);
1791         tp->fw = NULL;
1792 }
1793
1794 static int rtl_apply_firmware(struct rtl8169_private *tp, const char *fw_name)
1795 {
1796         const struct firmware **fw = &tp->fw;
1797         int rc = !*fw;
1798
1799         if (rc) {
1800                 rc = request_firmware(fw, fw_name, &tp->pci_dev->dev);
1801                 if (rc < 0)
1802                         goto out;
1803         }
1804
1805         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1806         rtl_phy_write_fw(tp, *fw);
1807 out:
1808         return rc;
1809 }
1810
1811 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1812 {
1813         static const struct phy_reg phy_reg_init[] = {
1814                 { 0x1f, 0x0001 },
1815                 { 0x06, 0x006e },
1816                 { 0x08, 0x0708 },
1817                 { 0x15, 0x4000 },
1818                 { 0x18, 0x65c7 },
1819
1820                 { 0x1f, 0x0001 },
1821                 { 0x03, 0x00a1 },
1822                 { 0x02, 0x0008 },
1823                 { 0x01, 0x0120 },
1824                 { 0x00, 0x1000 },
1825                 { 0x04, 0x0800 },
1826                 { 0x04, 0x0000 },
1827
1828                 { 0x03, 0xff41 },
1829                 { 0x02, 0xdf60 },
1830                 { 0x01, 0x0140 },
1831                 { 0x00, 0x0077 },
1832                 { 0x04, 0x7800 },
1833                 { 0x04, 0x7000 },
1834
1835                 { 0x03, 0x802f },
1836                 { 0x02, 0x4f02 },
1837                 { 0x01, 0x0409 },
1838                 { 0x00, 0xf0f9 },
1839                 { 0x04, 0x9800 },
1840                 { 0x04, 0x9000 },
1841
1842                 { 0x03, 0xdf01 },
1843                 { 0x02, 0xdf20 },
1844                 { 0x01, 0xff95 },
1845                 { 0x00, 0xba00 },
1846                 { 0x04, 0xa800 },
1847                 { 0x04, 0xa000 },
1848
1849                 { 0x03, 0xff41 },
1850                 { 0x02, 0xdf20 },
1851                 { 0x01, 0x0140 },
1852                 { 0x00, 0x00bb },
1853                 { 0x04, 0xb800 },
1854                 { 0x04, 0xb000 },
1855
1856                 { 0x03, 0xdf41 },
1857                 { 0x02, 0xdc60 },
1858                 { 0x01, 0x6340 },
1859                 { 0x00, 0x007d },
1860                 { 0x04, 0xd800 },
1861                 { 0x04, 0xd000 },
1862
1863                 { 0x03, 0xdf01 },
1864                 { 0x02, 0xdf20 },
1865                 { 0x01, 0x100a },
1866                 { 0x00, 0xa0ff },
1867                 { 0x04, 0xf800 },
1868                 { 0x04, 0xf000 },
1869
1870                 { 0x1f, 0x0000 },
1871                 { 0x0b, 0x0000 },
1872                 { 0x00, 0x9200 }
1873         };
1874
1875         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1876 }
1877
1878 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1879 {
1880         static const struct phy_reg phy_reg_init[] = {
1881                 { 0x1f, 0x0002 },
1882                 { 0x01, 0x90d0 },
1883                 { 0x1f, 0x0000 }
1884         };
1885
1886         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1887 }
1888
1889 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1890 {
1891         struct pci_dev *pdev = tp->pci_dev;
1892         u16 vendor_id, device_id;
1893
1894         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1895         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1896
1897         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1898                 return;
1899
1900         rtl_writephy(tp, 0x1f, 0x0001);
1901         rtl_writephy(tp, 0x10, 0xf01b);
1902         rtl_writephy(tp, 0x1f, 0x0000);
1903 }
1904
1905 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
1906 {
1907         static const struct phy_reg phy_reg_init[] = {
1908                 { 0x1f, 0x0001 },
1909                 { 0x04, 0x0000 },
1910                 { 0x03, 0x00a1 },
1911                 { 0x02, 0x0008 },
1912                 { 0x01, 0x0120 },
1913                 { 0x00, 0x1000 },
1914                 { 0x04, 0x0800 },
1915                 { 0x04, 0x9000 },
1916                 { 0x03, 0x802f },
1917                 { 0x02, 0x4f02 },
1918                 { 0x01, 0x0409 },
1919                 { 0x00, 0xf099 },
1920                 { 0x04, 0x9800 },
1921                 { 0x04, 0xa000 },
1922                 { 0x03, 0xdf01 },
1923                 { 0x02, 0xdf20 },
1924                 { 0x01, 0xff95 },
1925                 { 0x00, 0xba00 },
1926                 { 0x04, 0xa800 },
1927                 { 0x04, 0xf000 },
1928                 { 0x03, 0xdf01 },
1929                 { 0x02, 0xdf20 },
1930                 { 0x01, 0x101a },
1931                 { 0x00, 0xa0ff },
1932                 { 0x04, 0xf800 },
1933                 { 0x04, 0x0000 },
1934                 { 0x1f, 0x0000 },
1935
1936                 { 0x1f, 0x0001 },
1937                 { 0x10, 0xf41b },
1938                 { 0x14, 0xfb54 },
1939                 { 0x18, 0xf5c7 },
1940                 { 0x1f, 0x0000 },
1941
1942                 { 0x1f, 0x0001 },
1943                 { 0x17, 0x0cc0 },
1944                 { 0x1f, 0x0000 }
1945         };
1946
1947         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1948
1949         rtl8169scd_hw_phy_config_quirk(tp);
1950 }
1951
1952 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
1953 {
1954         static const struct phy_reg phy_reg_init[] = {
1955                 { 0x1f, 0x0001 },
1956                 { 0x04, 0x0000 },
1957                 { 0x03, 0x00a1 },
1958                 { 0x02, 0x0008 },
1959                 { 0x01, 0x0120 },
1960                 { 0x00, 0x1000 },
1961                 { 0x04, 0x0800 },
1962                 { 0x04, 0x9000 },
1963                 { 0x03, 0x802f },
1964                 { 0x02, 0x4f02 },
1965                 { 0x01, 0x0409 },
1966                 { 0x00, 0xf099 },
1967                 { 0x04, 0x9800 },
1968                 { 0x04, 0xa000 },
1969                 { 0x03, 0xdf01 },
1970                 { 0x02, 0xdf20 },
1971                 { 0x01, 0xff95 },
1972                 { 0x00, 0xba00 },
1973                 { 0x04, 0xa800 },
1974                 { 0x04, 0xf000 },
1975                 { 0x03, 0xdf01 },
1976                 { 0x02, 0xdf20 },
1977                 { 0x01, 0x101a },
1978                 { 0x00, 0xa0ff },
1979                 { 0x04, 0xf800 },
1980                 { 0x04, 0x0000 },
1981                 { 0x1f, 0x0000 },
1982
1983                 { 0x1f, 0x0001 },
1984                 { 0x0b, 0x8480 },
1985                 { 0x1f, 0x0000 },
1986
1987                 { 0x1f, 0x0001 },
1988                 { 0x18, 0x67c7 },
1989                 { 0x04, 0x2000 },
1990                 { 0x03, 0x002f },
1991                 { 0x02, 0x4360 },
1992                 { 0x01, 0x0109 },
1993                 { 0x00, 0x3022 },
1994                 { 0x04, 0x2800 },
1995                 { 0x1f, 0x0000 },
1996
1997                 { 0x1f, 0x0001 },
1998                 { 0x17, 0x0cc0 },
1999                 { 0x1f, 0x0000 }
2000         };
2001
2002         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2003 }
2004
2005 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2006 {
2007         static const struct phy_reg phy_reg_init[] = {
2008                 { 0x10, 0xf41b },
2009                 { 0x1f, 0x0000 }
2010         };
2011
2012         rtl_writephy(tp, 0x1f, 0x0001);
2013         rtl_patchphy(tp, 0x16, 1 << 0);
2014
2015         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2016 }
2017
2018 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2019 {
2020         static const struct phy_reg phy_reg_init[] = {
2021                 { 0x1f, 0x0001 },
2022                 { 0x10, 0xf41b },
2023                 { 0x1f, 0x0000 }
2024         };
2025
2026         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2027 }
2028
2029 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2030 {
2031         static const struct phy_reg phy_reg_init[] = {
2032                 { 0x1f, 0x0000 },
2033                 { 0x1d, 0x0f00 },
2034                 { 0x1f, 0x0002 },
2035                 { 0x0c, 0x1ec8 },
2036                 { 0x1f, 0x0000 }
2037         };
2038
2039         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2040 }
2041
2042 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2043 {
2044         static const struct phy_reg phy_reg_init[] = {
2045                 { 0x1f, 0x0001 },
2046                 { 0x1d, 0x3d98 },
2047                 { 0x1f, 0x0000 }
2048         };
2049
2050         rtl_writephy(tp, 0x1f, 0x0000);
2051         rtl_patchphy(tp, 0x14, 1 << 5);
2052         rtl_patchphy(tp, 0x0d, 1 << 5);
2053
2054         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2055 }
2056
2057 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2058 {
2059         static const struct phy_reg phy_reg_init[] = {
2060                 { 0x1f, 0x0001 },
2061                 { 0x12, 0x2300 },
2062                 { 0x1f, 0x0002 },
2063                 { 0x00, 0x88d4 },
2064                 { 0x01, 0x82b1 },
2065                 { 0x03, 0x7002 },
2066                 { 0x08, 0x9e30 },
2067                 { 0x09, 0x01f0 },
2068                 { 0x0a, 0x5500 },
2069                 { 0x0c, 0x00c8 },
2070                 { 0x1f, 0x0003 },
2071                 { 0x12, 0xc096 },
2072                 { 0x16, 0x000a },
2073                 { 0x1f, 0x0000 },
2074                 { 0x1f, 0x0000 },
2075                 { 0x09, 0x2000 },
2076                 { 0x09, 0x0000 }
2077         };
2078
2079         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2080
2081         rtl_patchphy(tp, 0x14, 1 << 5);
2082         rtl_patchphy(tp, 0x0d, 1 << 5);
2083         rtl_writephy(tp, 0x1f, 0x0000);
2084 }
2085
2086 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2087 {
2088         static const struct phy_reg phy_reg_init[] = {
2089                 { 0x1f, 0x0001 },
2090                 { 0x12, 0x2300 },
2091                 { 0x03, 0x802f },
2092                 { 0x02, 0x4f02 },
2093                 { 0x01, 0x0409 },
2094                 { 0x00, 0xf099 },
2095                 { 0x04, 0x9800 },
2096                 { 0x04, 0x9000 },
2097                 { 0x1d, 0x3d98 },
2098                 { 0x1f, 0x0002 },
2099                 { 0x0c, 0x7eb8 },
2100                 { 0x06, 0x0761 },
2101                 { 0x1f, 0x0003 },
2102                 { 0x16, 0x0f0a },
2103                 { 0x1f, 0x0000 }
2104         };
2105
2106         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2107
2108         rtl_patchphy(tp, 0x16, 1 << 0);
2109         rtl_patchphy(tp, 0x14, 1 << 5);
2110         rtl_patchphy(tp, 0x0d, 1 << 5);
2111         rtl_writephy(tp, 0x1f, 0x0000);
2112 }
2113
2114 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2115 {
2116         static const struct phy_reg phy_reg_init[] = {
2117                 { 0x1f, 0x0001 },
2118                 { 0x12, 0x2300 },
2119                 { 0x1d, 0x3d98 },
2120                 { 0x1f, 0x0002 },
2121                 { 0x0c, 0x7eb8 },
2122                 { 0x06, 0x5461 },
2123                 { 0x1f, 0x0003 },
2124                 { 0x16, 0x0f0a },
2125                 { 0x1f, 0x0000 }
2126         };
2127
2128         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2129
2130         rtl_patchphy(tp, 0x16, 1 << 0);
2131         rtl_patchphy(tp, 0x14, 1 << 5);
2132         rtl_patchphy(tp, 0x0d, 1 << 5);
2133         rtl_writephy(tp, 0x1f, 0x0000);
2134 }
2135
2136 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2137 {
2138         rtl8168c_3_hw_phy_config(tp);
2139 }
2140
2141 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2142 {
2143         static const struct phy_reg phy_reg_init_0[] = {
2144                 /* Channel Estimation */
2145                 { 0x1f, 0x0001 },
2146                 { 0x06, 0x4064 },
2147                 { 0x07, 0x2863 },
2148                 { 0x08, 0x059c },
2149                 { 0x09, 0x26b4 },
2150                 { 0x0a, 0x6a19 },
2151                 { 0x0b, 0xdcc8 },
2152                 { 0x10, 0xf06d },
2153                 { 0x14, 0x7f68 },
2154                 { 0x18, 0x7fd9 },
2155                 { 0x1c, 0xf0ff },
2156                 { 0x1d, 0x3d9c },
2157                 { 0x1f, 0x0003 },
2158                 { 0x12, 0xf49f },
2159                 { 0x13, 0x070b },
2160                 { 0x1a, 0x05ad },
2161                 { 0x14, 0x94c0 },
2162
2163                 /*
2164                  * Tx Error Issue
2165                  * enhance line driver power
2166                  */
2167                 { 0x1f, 0x0002 },
2168                 { 0x06, 0x5561 },
2169                 { 0x1f, 0x0005 },
2170                 { 0x05, 0x8332 },
2171                 { 0x06, 0x5561 },
2172
2173                 /*
2174                  * Can not link to 1Gbps with bad cable
2175                  * Decrease SNR threshold form 21.07dB to 19.04dB
2176                  */
2177                 { 0x1f, 0x0001 },
2178                 { 0x17, 0x0cc0 },
2179
2180                 { 0x1f, 0x0000 },
2181                 { 0x0d, 0xf880 }
2182         };
2183         void __iomem *ioaddr = tp->mmio_addr;
2184
2185         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2186
2187         /*
2188          * Rx Error Issue
2189          * Fine Tune Switching regulator parameter
2190          */
2191         rtl_writephy(tp, 0x1f, 0x0002);
2192         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2193         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2194
2195         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2196                 static const struct phy_reg phy_reg_init[] = {
2197                         { 0x1f, 0x0002 },
2198                         { 0x05, 0x669a },
2199                         { 0x1f, 0x0005 },
2200                         { 0x05, 0x8330 },
2201                         { 0x06, 0x669a },
2202                         { 0x1f, 0x0002 }
2203                 };
2204                 int val;
2205
2206                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2207
2208                 val = rtl_readphy(tp, 0x0d);
2209
2210                 if ((val & 0x00ff) != 0x006c) {
2211                         static const u32 set[] = {
2212                                 0x0065, 0x0066, 0x0067, 0x0068,
2213                                 0x0069, 0x006a, 0x006b, 0x006c
2214                         };
2215                         int i;
2216
2217                         rtl_writephy(tp, 0x1f, 0x0002);
2218
2219                         val &= 0xff00;
2220                         for (i = 0; i < ARRAY_SIZE(set); i++)
2221                                 rtl_writephy(tp, 0x0d, val | set[i]);
2222                 }
2223         } else {
2224                 static const struct phy_reg phy_reg_init[] = {
2225                         { 0x1f, 0x0002 },
2226                         { 0x05, 0x6662 },
2227                         { 0x1f, 0x0005 },
2228                         { 0x05, 0x8330 },
2229                         { 0x06, 0x6662 }
2230                 };
2231
2232                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2233         }
2234
2235         /* RSET couple improve */
2236         rtl_writephy(tp, 0x1f, 0x0002);
2237         rtl_patchphy(tp, 0x0d, 0x0300);
2238         rtl_patchphy(tp, 0x0f, 0x0010);
2239
2240         /* Fine tune PLL performance */
2241         rtl_writephy(tp, 0x1f, 0x0002);
2242         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2243         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2244
2245         rtl_writephy(tp, 0x1f, 0x0005);
2246         rtl_writephy(tp, 0x05, 0x001b);
2247         if ((rtl_readphy(tp, 0x06) != 0xbf00) ||
2248             (rtl_apply_firmware(tp, FIRMWARE_8168D_1) < 0)) {
2249                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2250         }
2251
2252         rtl_writephy(tp, 0x1f, 0x0000);
2253 }
2254
2255 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2256 {
2257         static const struct phy_reg phy_reg_init_0[] = {
2258                 /* Channel Estimation */
2259                 { 0x1f, 0x0001 },
2260                 { 0x06, 0x4064 },
2261                 { 0x07, 0x2863 },
2262                 { 0x08, 0x059c },
2263                 { 0x09, 0x26b4 },
2264                 { 0x0a, 0x6a19 },
2265                 { 0x0b, 0xdcc8 },
2266                 { 0x10, 0xf06d },
2267                 { 0x14, 0x7f68 },
2268                 { 0x18, 0x7fd9 },
2269                 { 0x1c, 0xf0ff },
2270                 { 0x1d, 0x3d9c },
2271                 { 0x1f, 0x0003 },
2272                 { 0x12, 0xf49f },
2273                 { 0x13, 0x070b },
2274                 { 0x1a, 0x05ad },
2275                 { 0x14, 0x94c0 },
2276
2277                 /*
2278                  * Tx Error Issue
2279                  * enhance line driver power
2280                  */
2281                 { 0x1f, 0x0002 },
2282                 { 0x06, 0x5561 },
2283                 { 0x1f, 0x0005 },
2284                 { 0x05, 0x8332 },
2285                 { 0x06, 0x5561 },
2286
2287                 /*
2288                  * Can not link to 1Gbps with bad cable
2289                  * Decrease SNR threshold form 21.07dB to 19.04dB
2290                  */
2291                 { 0x1f, 0x0001 },
2292                 { 0x17, 0x0cc0 },
2293
2294                 { 0x1f, 0x0000 },
2295                 { 0x0d, 0xf880 }
2296         };
2297         void __iomem *ioaddr = tp->mmio_addr;
2298
2299         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2300
2301         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2302                 static const struct phy_reg phy_reg_init[] = {
2303                         { 0x1f, 0x0002 },
2304                         { 0x05, 0x669a },
2305                         { 0x1f, 0x0005 },
2306                         { 0x05, 0x8330 },
2307                         { 0x06, 0x669a },
2308
2309                         { 0x1f, 0x0002 }
2310                 };
2311                 int val;
2312
2313                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2314
2315                 val = rtl_readphy(tp, 0x0d);
2316                 if ((val & 0x00ff) != 0x006c) {
2317                         static const u32 set[] = {
2318                                 0x0065, 0x0066, 0x0067, 0x0068,
2319                                 0x0069, 0x006a, 0x006b, 0x006c
2320                         };
2321                         int i;
2322
2323                         rtl_writephy(tp, 0x1f, 0x0002);
2324
2325                         val &= 0xff00;
2326                         for (i = 0; i < ARRAY_SIZE(set); i++)
2327                                 rtl_writephy(tp, 0x0d, val | set[i]);
2328                 }
2329         } else {
2330                 static const struct phy_reg phy_reg_init[] = {
2331                         { 0x1f, 0x0002 },
2332                         { 0x05, 0x2642 },
2333                         { 0x1f, 0x0005 },
2334                         { 0x05, 0x8330 },
2335                         { 0x06, 0x2642 }
2336                 };
2337
2338                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2339         }
2340
2341         /* Fine tune PLL performance */
2342         rtl_writephy(tp, 0x1f, 0x0002);
2343         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2344         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2345
2346         /* Switching regulator Slew rate */
2347         rtl_writephy(tp, 0x1f, 0x0002);
2348         rtl_patchphy(tp, 0x0f, 0x0017);
2349
2350         rtl_writephy(tp, 0x1f, 0x0005);
2351         rtl_writephy(tp, 0x05, 0x001b);
2352         if ((rtl_readphy(tp, 0x06) != 0xb300) ||
2353             (rtl_apply_firmware(tp, FIRMWARE_8168D_2) < 0)) {
2354                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2355         }
2356
2357         rtl_writephy(tp, 0x1f, 0x0000);
2358 }
2359
2360 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2361 {
2362         static const struct phy_reg phy_reg_init[] = {
2363                 { 0x1f, 0x0002 },
2364                 { 0x10, 0x0008 },
2365                 { 0x0d, 0x006c },
2366
2367                 { 0x1f, 0x0000 },
2368                 { 0x0d, 0xf880 },
2369
2370                 { 0x1f, 0x0001 },
2371                 { 0x17, 0x0cc0 },
2372
2373                 { 0x1f, 0x0001 },
2374                 { 0x0b, 0xa4d8 },
2375                 { 0x09, 0x281c },
2376                 { 0x07, 0x2883 },
2377                 { 0x0a, 0x6b35 },
2378                 { 0x1d, 0x3da4 },
2379                 { 0x1c, 0xeffd },
2380                 { 0x14, 0x7f52 },
2381                 { 0x18, 0x7fc6 },
2382                 { 0x08, 0x0601 },
2383                 { 0x06, 0x4063 },
2384                 { 0x10, 0xf074 },
2385                 { 0x1f, 0x0003 },
2386                 { 0x13, 0x0789 },
2387                 { 0x12, 0xf4bd },
2388                 { 0x1a, 0x04fd },
2389                 { 0x14, 0x84b0 },
2390                 { 0x1f, 0x0000 },
2391                 { 0x00, 0x9200 },
2392
2393                 { 0x1f, 0x0005 },
2394                 { 0x01, 0x0340 },
2395                 { 0x1f, 0x0001 },
2396                 { 0x04, 0x4000 },
2397                 { 0x03, 0x1d21 },
2398                 { 0x02, 0x0c32 },
2399                 { 0x01, 0x0200 },
2400                 { 0x00, 0x5554 },
2401                 { 0x04, 0x4800 },
2402                 { 0x04, 0x4000 },
2403                 { 0x04, 0xf000 },
2404                 { 0x03, 0xdf01 },
2405                 { 0x02, 0xdf20 },
2406                 { 0x01, 0x101a },
2407                 { 0x00, 0xa0ff },
2408                 { 0x04, 0xf800 },
2409                 { 0x04, 0xf000 },
2410                 { 0x1f, 0x0000 },
2411
2412                 { 0x1f, 0x0007 },
2413                 { 0x1e, 0x0023 },
2414                 { 0x16, 0x0000 },
2415                 { 0x1f, 0x0000 }
2416         };
2417
2418         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2419 }
2420
2421 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2422 {
2423         static const struct phy_reg phy_reg_init[] = {
2424                 { 0x1f, 0x0001 },
2425                 { 0x17, 0x0cc0 },
2426
2427                 { 0x1f, 0x0007 },
2428                 { 0x1e, 0x002d },
2429                 { 0x18, 0x0040 },
2430                 { 0x1f, 0x0000 }
2431         };
2432
2433         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2434         rtl_patchphy(tp, 0x0d, 1 << 5);
2435 }
2436
2437 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2438 {
2439         static const struct phy_reg phy_reg_init[] = {
2440                 { 0x1f, 0x0003 },
2441                 { 0x08, 0x441d },
2442                 { 0x01, 0x9100 },
2443                 { 0x1f, 0x0000 }
2444         };
2445
2446         rtl_writephy(tp, 0x1f, 0x0000);
2447         rtl_patchphy(tp, 0x11, 1 << 12);
2448         rtl_patchphy(tp, 0x19, 1 << 13);
2449         rtl_patchphy(tp, 0x10, 1 << 15);
2450
2451         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2452 }
2453
2454 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2455 {
2456         static const struct phy_reg phy_reg_init[] = {
2457                 { 0x1f, 0x0005 },
2458                 { 0x1a, 0x0000 },
2459                 { 0x1f, 0x0000 },
2460
2461                 { 0x1f, 0x0004 },
2462                 { 0x1c, 0x0000 },
2463                 { 0x1f, 0x0000 },
2464
2465                 { 0x1f, 0x0001 },
2466                 { 0x15, 0x7701 },
2467                 { 0x1f, 0x0000 }
2468         };
2469
2470         /* Disable ALDPS before ram code */
2471         rtl_writephy(tp, 0x1f, 0x0000);
2472         rtl_writephy(tp, 0x18, 0x0310);
2473         msleep(100);
2474
2475         if (rtl_apply_firmware(tp, FIRMWARE_8105E_1) < 0)
2476                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2477
2478         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2479 }
2480
2481 static void rtl_hw_phy_config(struct net_device *dev)
2482 {
2483         struct rtl8169_private *tp = netdev_priv(dev);
2484
2485         rtl8169_print_mac_version(tp);
2486
2487         switch (tp->mac_version) {
2488         case RTL_GIGA_MAC_VER_01:
2489                 break;
2490         case RTL_GIGA_MAC_VER_02:
2491         case RTL_GIGA_MAC_VER_03:
2492                 rtl8169s_hw_phy_config(tp);
2493                 break;
2494         case RTL_GIGA_MAC_VER_04:
2495                 rtl8169sb_hw_phy_config(tp);
2496                 break;
2497         case RTL_GIGA_MAC_VER_05:
2498                 rtl8169scd_hw_phy_config(tp);
2499                 break;
2500         case RTL_GIGA_MAC_VER_06:
2501                 rtl8169sce_hw_phy_config(tp);
2502                 break;
2503         case RTL_GIGA_MAC_VER_07:
2504         case RTL_GIGA_MAC_VER_08:
2505         case RTL_GIGA_MAC_VER_09:
2506                 rtl8102e_hw_phy_config(tp);
2507                 break;
2508         case RTL_GIGA_MAC_VER_11:
2509                 rtl8168bb_hw_phy_config(tp);
2510                 break;
2511         case RTL_GIGA_MAC_VER_12:
2512                 rtl8168bef_hw_phy_config(tp);
2513                 break;
2514         case RTL_GIGA_MAC_VER_17:
2515                 rtl8168bef_hw_phy_config(tp);
2516                 break;
2517         case RTL_GIGA_MAC_VER_18:
2518                 rtl8168cp_1_hw_phy_config(tp);
2519                 break;
2520         case RTL_GIGA_MAC_VER_19:
2521                 rtl8168c_1_hw_phy_config(tp);
2522                 break;
2523         case RTL_GIGA_MAC_VER_20:
2524                 rtl8168c_2_hw_phy_config(tp);
2525                 break;
2526         case RTL_GIGA_MAC_VER_21:
2527                 rtl8168c_3_hw_phy_config(tp);
2528                 break;
2529         case RTL_GIGA_MAC_VER_22:
2530                 rtl8168c_4_hw_phy_config(tp);
2531                 break;
2532         case RTL_GIGA_MAC_VER_23:
2533         case RTL_GIGA_MAC_VER_24:
2534                 rtl8168cp_2_hw_phy_config(tp);
2535                 break;
2536         case RTL_GIGA_MAC_VER_25:
2537                 rtl8168d_1_hw_phy_config(tp);
2538                 break;
2539         case RTL_GIGA_MAC_VER_26:
2540                 rtl8168d_2_hw_phy_config(tp);
2541                 break;
2542         case RTL_GIGA_MAC_VER_27:
2543                 rtl8168d_3_hw_phy_config(tp);
2544                 break;
2545         case RTL_GIGA_MAC_VER_28:
2546                 rtl8168d_4_hw_phy_config(tp);
2547                 break;
2548         case RTL_GIGA_MAC_VER_29:
2549         case RTL_GIGA_MAC_VER_30:
2550                 rtl8105e_hw_phy_config(tp);
2551                 break;
2552
2553         default:
2554                 break;
2555         }
2556 }
2557
2558 static void rtl8169_phy_timer(unsigned long __opaque)
2559 {
2560         struct net_device *dev = (struct net_device *)__opaque;
2561         struct rtl8169_private *tp = netdev_priv(dev);
2562         struct timer_list *timer = &tp->timer;
2563         void __iomem *ioaddr = tp->mmio_addr;
2564         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2565
2566         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2567
2568         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2569                 return;
2570
2571         spin_lock_irq(&tp->lock);
2572
2573         if (tp->phy_reset_pending(tp)) {
2574                 /*
2575                  * A busy loop could burn quite a few cycles on nowadays CPU.
2576                  * Let's delay the execution of the timer for a few ticks.
2577                  */
2578                 timeout = HZ/10;
2579                 goto out_mod_timer;
2580         }
2581
2582         if (tp->link_ok(ioaddr))
2583                 goto out_unlock;
2584
2585         netif_warn(tp, link, dev, "PHY reset until link up\n");
2586
2587         tp->phy_reset_enable(tp);
2588
2589 out_mod_timer:
2590         mod_timer(timer, jiffies + timeout);
2591 out_unlock:
2592         spin_unlock_irq(&tp->lock);
2593 }
2594
2595 static inline void rtl8169_delete_timer(struct net_device *dev)
2596 {
2597         struct rtl8169_private *tp = netdev_priv(dev);
2598         struct timer_list *timer = &tp->timer;
2599
2600         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2601                 return;
2602
2603         del_timer_sync(timer);
2604 }
2605
2606 static inline void rtl8169_request_timer(struct net_device *dev)
2607 {
2608         struct rtl8169_private *tp = netdev_priv(dev);
2609         struct timer_list *timer = &tp->timer;
2610
2611         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2612                 return;
2613
2614         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2615 }
2616
2617 #ifdef CONFIG_NET_POLL_CONTROLLER
2618 /*
2619  * Polling 'interrupt' - used by things like netconsole to send skbs
2620  * without having to re-enable interrupts. It's not called while
2621  * the interrupt routine is executing.
2622  */
2623 static void rtl8169_netpoll(struct net_device *dev)
2624 {
2625         struct rtl8169_private *tp = netdev_priv(dev);
2626         struct pci_dev *pdev = tp->pci_dev;
2627
2628         disable_irq(pdev->irq);
2629         rtl8169_interrupt(pdev->irq, dev);
2630         enable_irq(pdev->irq);
2631 }
2632 #endif
2633
2634 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2635                                   void __iomem *ioaddr)
2636 {
2637         iounmap(ioaddr);
2638         pci_release_regions(pdev);
2639         pci_clear_mwi(pdev);
2640         pci_disable_device(pdev);
2641         free_netdev(dev);
2642 }
2643
2644 static void rtl8169_phy_reset(struct net_device *dev,
2645                               struct rtl8169_private *tp)
2646 {
2647         unsigned int i;
2648
2649         tp->phy_reset_enable(tp);
2650         for (i = 0; i < 100; i++) {
2651                 if (!tp->phy_reset_pending(tp))
2652                         return;
2653                 msleep(1);
2654         }
2655         netif_err(tp, link, dev, "PHY reset failed\n");
2656 }
2657
2658 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2659 {
2660         void __iomem *ioaddr = tp->mmio_addr;
2661
2662         rtl_hw_phy_config(dev);
2663
2664         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2665                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2666                 RTL_W8(0x82, 0x01);
2667         }
2668
2669         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2670
2671         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2672                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2673
2674         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2675                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2676                 RTL_W8(0x82, 0x01);
2677                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2678                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2679         }
2680
2681         rtl8169_phy_reset(dev, tp);
2682
2683         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2684                 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2685                 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2686                 tp->mii.supports_gmii ?
2687                         ADVERTISED_1000baseT_Half |
2688                         ADVERTISED_1000baseT_Full : 0);
2689
2690         if (RTL_R8(PHYstatus) & TBI_Enable)
2691                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2692 }
2693
2694 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2695 {
2696         void __iomem *ioaddr = tp->mmio_addr;
2697         u32 high;
2698         u32 low;
2699
2700         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2701         high = addr[4] | (addr[5] << 8);
2702
2703         spin_lock_irq(&tp->lock);
2704
2705         RTL_W8(Cfg9346, Cfg9346_Unlock);
2706
2707         RTL_W32(MAC4, high);
2708         RTL_R32(MAC4);
2709
2710         RTL_W32(MAC0, low);
2711         RTL_R32(MAC0);
2712
2713         RTL_W8(Cfg9346, Cfg9346_Lock);
2714
2715         spin_unlock_irq(&tp->lock);
2716 }
2717
2718 static int rtl_set_mac_address(struct net_device *dev, void *p)
2719 {
2720         struct rtl8169_private *tp = netdev_priv(dev);
2721         struct sockaddr *addr = p;
2722
2723         if (!is_valid_ether_addr(addr->sa_data))
2724                 return -EADDRNOTAVAIL;
2725
2726         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2727
2728         rtl_rar_set(tp, dev->dev_addr);
2729
2730         return 0;
2731 }
2732
2733 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2734 {
2735         struct rtl8169_private *tp = netdev_priv(dev);
2736         struct mii_ioctl_data *data = if_mii(ifr);
2737
2738         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2739 }
2740
2741 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2742 {
2743         switch (cmd) {
2744         case SIOCGMIIPHY:
2745                 data->phy_id = 32; /* Internal PHY */
2746                 return 0;
2747
2748         case SIOCGMIIREG:
2749                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2750                 return 0;
2751
2752         case SIOCSMIIREG:
2753                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2754                 return 0;
2755         }
2756         return -EOPNOTSUPP;
2757 }
2758
2759 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2760 {
2761         return -EOPNOTSUPP;
2762 }
2763
2764 static const struct rtl_cfg_info {
2765         void (*hw_start)(struct net_device *);
2766         unsigned int region;
2767         unsigned int align;
2768         u16 intr_event;
2769         u16 napi_event;
2770         unsigned features;
2771         u8 default_ver;
2772 } rtl_cfg_infos [] = {
2773         [RTL_CFG_0] = {
2774                 .hw_start       = rtl_hw_start_8169,
2775                 .region         = 1,
2776                 .align          = 0,
2777                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2778                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2779                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2780                 .features       = RTL_FEATURE_GMII,
2781                 .default_ver    = RTL_GIGA_MAC_VER_01,
2782         },
2783         [RTL_CFG_1] = {
2784                 .hw_start       = rtl_hw_start_8168,
2785                 .region         = 2,
2786                 .align          = 8,
2787                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2788                                   TxErr | TxOK | RxOK | RxErr,
2789                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
2790                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2791                 .default_ver    = RTL_GIGA_MAC_VER_11,
2792         },
2793         [RTL_CFG_2] = {
2794                 .hw_start       = rtl_hw_start_8101,
2795                 .region         = 2,
2796                 .align          = 8,
2797                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2798                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2799                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2800                 .features       = RTL_FEATURE_MSI,
2801                 .default_ver    = RTL_GIGA_MAC_VER_13,
2802         }
2803 };
2804
2805 /* Cfg9346_Unlock assumed. */
2806 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2807                             const struct rtl_cfg_info *cfg)
2808 {
2809         unsigned msi = 0;
2810         u8 cfg2;
2811
2812         cfg2 = RTL_R8(Config2) & ~MSIEnable;
2813         if (cfg->features & RTL_FEATURE_MSI) {
2814                 if (pci_enable_msi(pdev)) {
2815                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2816                 } else {
2817                         cfg2 |= MSIEnable;
2818                         msi = RTL_FEATURE_MSI;
2819                 }
2820         }
2821         RTL_W8(Config2, cfg2);
2822         return msi;
2823 }
2824
2825 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2826 {
2827         if (tp->features & RTL_FEATURE_MSI) {
2828                 pci_disable_msi(pdev);
2829                 tp->features &= ~RTL_FEATURE_MSI;
2830         }
2831 }
2832
2833 static const struct net_device_ops rtl8169_netdev_ops = {
2834         .ndo_open               = rtl8169_open,
2835         .ndo_stop               = rtl8169_close,
2836         .ndo_get_stats          = rtl8169_get_stats,
2837         .ndo_start_xmit         = rtl8169_start_xmit,
2838         .ndo_tx_timeout         = rtl8169_tx_timeout,
2839         .ndo_validate_addr      = eth_validate_addr,
2840         .ndo_change_mtu         = rtl8169_change_mtu,
2841         .ndo_set_mac_address    = rtl_set_mac_address,
2842         .ndo_do_ioctl           = rtl8169_ioctl,
2843         .ndo_set_multicast_list = rtl_set_rx_mode,
2844 #ifdef CONFIG_NET_POLL_CONTROLLER
2845         .ndo_poll_controller    = rtl8169_netpoll,
2846 #endif
2847
2848 };
2849
2850 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2851 {
2852         struct mdio_ops *ops = &tp->mdio_ops;
2853
2854         switch (tp->mac_version) {
2855         case RTL_GIGA_MAC_VER_27:
2856                 ops->write      = r8168dp_1_mdio_write;
2857                 ops->read       = r8168dp_1_mdio_read;
2858                 break;
2859         case RTL_GIGA_MAC_VER_28:
2860                 ops->write      = r8168dp_2_mdio_write;
2861                 ops->read       = r8168dp_2_mdio_read;
2862                 break;
2863         default:
2864                 ops->write      = r8169_mdio_write;
2865                 ops->read       = r8169_mdio_read;
2866                 break;
2867         }
2868 }
2869
2870 static void r810x_phy_power_down(struct rtl8169_private *tp)
2871 {
2872         rtl_writephy(tp, 0x1f, 0x0000);
2873         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2874 }
2875
2876 static void r810x_phy_power_up(struct rtl8169_private *tp)
2877 {
2878         rtl_writephy(tp, 0x1f, 0x0000);
2879         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2880 }
2881
2882 static void r810x_pll_power_down(struct rtl8169_private *tp)
2883 {
2884         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2885                 rtl_writephy(tp, 0x1f, 0x0000);
2886                 rtl_writephy(tp, MII_BMCR, 0x0000);
2887                 return;
2888         }
2889
2890         r810x_phy_power_down(tp);
2891 }
2892
2893 static void r810x_pll_power_up(struct rtl8169_private *tp)
2894 {
2895         r810x_phy_power_up(tp);
2896 }
2897
2898 static void r8168_phy_power_up(struct rtl8169_private *tp)
2899 {
2900         rtl_writephy(tp, 0x1f, 0x0000);
2901         rtl_writephy(tp, 0x0e, 0x0000);
2902         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2903 }
2904
2905 static void r8168_phy_power_down(struct rtl8169_private *tp)
2906 {
2907         rtl_writephy(tp, 0x1f, 0x0000);
2908         rtl_writephy(tp, 0x0e, 0x0200);
2909         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2910 }
2911
2912 static void r8168_pll_power_down(struct rtl8169_private *tp)
2913 {
2914         void __iomem *ioaddr = tp->mmio_addr;
2915
2916         if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2917                 return;
2918
2919         if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
2920              (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
2921             (RTL_R16(CPlusCmd) & ASF)) {
2922                 return;
2923         }
2924
2925         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2926                 rtl_writephy(tp, 0x1f, 0x0000);
2927                 rtl_writephy(tp, MII_BMCR, 0x0000);
2928
2929                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
2930                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2931                 return;
2932         }
2933
2934         r8168_phy_power_down(tp);
2935
2936         switch (tp->mac_version) {
2937         case RTL_GIGA_MAC_VER_25:
2938         case RTL_GIGA_MAC_VER_26:
2939                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
2940                 break;
2941         }
2942 }
2943
2944 static void r8168_pll_power_up(struct rtl8169_private *tp)
2945 {
2946         void __iomem *ioaddr = tp->mmio_addr;
2947
2948         if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2949                 return;
2950
2951         switch (tp->mac_version) {
2952         case RTL_GIGA_MAC_VER_25:
2953         case RTL_GIGA_MAC_VER_26:
2954                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
2955                 break;
2956         }
2957
2958         r8168_phy_power_up(tp);
2959 }
2960
2961 static void rtl_pll_power_op(struct rtl8169_private *tp,
2962                              void (*op)(struct rtl8169_private *))
2963 {
2964         if (op)
2965                 op(tp);
2966 }
2967
2968 static void rtl_pll_power_down(struct rtl8169_private *tp)
2969 {
2970         rtl_pll_power_op(tp, tp->pll_power_ops.down);
2971 }
2972
2973 static void rtl_pll_power_up(struct rtl8169_private *tp)
2974 {
2975         rtl_pll_power_op(tp, tp->pll_power_ops.up);
2976 }
2977
2978 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
2979 {
2980         struct pll_power_ops *ops = &tp->pll_power_ops;
2981
2982         switch (tp->mac_version) {
2983         case RTL_GIGA_MAC_VER_07:
2984         case RTL_GIGA_MAC_VER_08:
2985         case RTL_GIGA_MAC_VER_09:
2986         case RTL_GIGA_MAC_VER_10:
2987         case RTL_GIGA_MAC_VER_16:
2988         case RTL_GIGA_MAC_VER_29:
2989         case RTL_GIGA_MAC_VER_30:
2990                 ops->down       = r810x_pll_power_down;
2991                 ops->up         = r810x_pll_power_up;
2992                 break;
2993
2994         case RTL_GIGA_MAC_VER_11:
2995         case RTL_GIGA_MAC_VER_12:
2996         case RTL_GIGA_MAC_VER_17:
2997         case RTL_GIGA_MAC_VER_18:
2998         case RTL_GIGA_MAC_VER_19:
2999         case RTL_GIGA_MAC_VER_20:
3000         case RTL_GIGA_MAC_VER_21:
3001         case RTL_GIGA_MAC_VER_22:
3002         case RTL_GIGA_MAC_VER_23:
3003         case RTL_GIGA_MAC_VER_24:
3004         case RTL_GIGA_MAC_VER_25:
3005         case RTL_GIGA_MAC_VER_26:
3006         case RTL_GIGA_MAC_VER_27:
3007         case RTL_GIGA_MAC_VER_28:
3008                 ops->down       = r8168_pll_power_down;
3009                 ops->up         = r8168_pll_power_up;
3010                 break;
3011
3012         default:
3013                 ops->down       = NULL;
3014                 ops->up         = NULL;
3015                 break;
3016         }
3017 }
3018
3019 static int __devinit
3020 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3021 {
3022         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3023         const unsigned int region = cfg->region;
3024         struct rtl8169_private *tp;
3025         struct mii_if_info *mii;
3026         struct net_device *dev;
3027         void __iomem *ioaddr;
3028         unsigned int i;
3029         int rc;
3030
3031         if (netif_msg_drv(&debug)) {
3032                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3033                        MODULENAME, RTL8169_VERSION);
3034         }
3035
3036         dev = alloc_etherdev(sizeof (*tp));
3037         if (!dev) {
3038                 if (netif_msg_drv(&debug))
3039                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3040                 rc = -ENOMEM;
3041                 goto out;
3042         }
3043
3044         SET_NETDEV_DEV(dev, &pdev->dev);
3045         dev->netdev_ops = &rtl8169_netdev_ops;
3046         tp = netdev_priv(dev);
3047         tp->dev = dev;
3048         tp->pci_dev = pdev;
3049         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3050
3051         mii = &tp->mii;
3052         mii->dev = dev;
3053         mii->mdio_read = rtl_mdio_read;
3054         mii->mdio_write = rtl_mdio_write;
3055         mii->phy_id_mask = 0x1f;
3056         mii->reg_num_mask = 0x1f;
3057         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3058
3059         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3060         rc = pci_enable_device(pdev);
3061         if (rc < 0) {
3062                 netif_err(tp, probe, dev, "enable failure\n");
3063                 goto err_out_free_dev_1;
3064         }
3065
3066         if (pci_set_mwi(pdev) < 0)
3067                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3068
3069         /* make sure PCI base addr 1 is MMIO */
3070         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3071                 netif_err(tp, probe, dev,
3072                           "region #%d not an MMIO resource, aborting\n",
3073                           region);
3074                 rc = -ENODEV;
3075                 goto err_out_mwi_2;
3076         }
3077
3078         /* check for weird/broken PCI region reporting */
3079         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3080                 netif_err(tp, probe, dev,
3081                           "Invalid PCI region size(s), aborting\n");
3082                 rc = -ENODEV;
3083                 goto err_out_mwi_2;
3084         }
3085
3086         rc = pci_request_regions(pdev, MODULENAME);
3087         if (rc < 0) {
3088                 netif_err(tp, probe, dev, "could not request regions\n");
3089                 goto err_out_mwi_2;
3090         }
3091
3092         tp->cp_cmd = PCIMulRW | RxChkSum;
3093
3094         if ((sizeof(dma_addr_t) > 4) &&
3095             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3096                 tp->cp_cmd |= PCIDAC;
3097                 dev->features |= NETIF_F_HIGHDMA;
3098         } else {
3099                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3100                 if (rc < 0) {
3101                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3102                         goto err_out_free_res_3;
3103                 }
3104         }
3105
3106         /* ioremap MMIO region */
3107         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3108         if (!ioaddr) {
3109                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3110                 rc = -EIO;
3111                 goto err_out_free_res_3;
3112         }
3113
3114         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3115         if (!tp->pcie_cap)
3116                 netif_info(tp, probe, dev, "no PCI Express capability\n");
3117
3118         RTL_W16(IntrMask, 0x0000);
3119
3120         /* Soft reset the chip. */
3121         RTL_W8(ChipCmd, CmdReset);
3122
3123         /* Check that the chip has finished the reset. */
3124         for (i = 0; i < 100; i++) {
3125                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3126                         break;
3127                 msleep_interruptible(1);
3128         }
3129
3130         RTL_W16(IntrStatus, 0xffff);
3131
3132         pci_set_master(pdev);
3133
3134         /* Identify chip attached to board */
3135         rtl8169_get_mac_version(tp, ioaddr);
3136
3137         /*
3138          * Pretend we are using VLANs; This bypasses a nasty bug where
3139          * Interrupts stop flowing on high load on 8110SCd controllers.
3140          */
3141         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3142                 tp->cp_cmd |= RxVlan;
3143
3144         rtl_init_mdio_ops(tp);
3145         rtl_init_pll_power_ops(tp);
3146
3147         /* Use appropriate default if unknown */
3148         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3149                 netif_notice(tp, probe, dev,
3150                              "unknown MAC, using family default\n");
3151                 tp->mac_version = cfg->default_ver;
3152         }
3153
3154         rtl8169_print_mac_version(tp);
3155
3156         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3157                 if (tp->mac_version == rtl_chip_info[i].mac_version)
3158                         break;
3159         }
3160         if (i == ARRAY_SIZE(rtl_chip_info)) {
3161                 dev_err(&pdev->dev,
3162                         "driver bug, MAC version not found in rtl_chip_info\n");
3163                 goto err_out_msi_4;
3164         }
3165         tp->chipset = i;
3166
3167         RTL_W8(Cfg9346, Cfg9346_Unlock);
3168         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3169         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3170         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3171                 tp->features |= RTL_FEATURE_WOL;
3172         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3173                 tp->features |= RTL_FEATURE_WOL;
3174         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3175         RTL_W8(Cfg9346, Cfg9346_Lock);
3176
3177         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3178             (RTL_R8(PHYstatus) & TBI_Enable)) {
3179                 tp->set_speed = rtl8169_set_speed_tbi;
3180                 tp->get_settings = rtl8169_gset_tbi;
3181                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3182                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3183                 tp->link_ok = rtl8169_tbi_link_ok;
3184                 tp->do_ioctl = rtl_tbi_ioctl;
3185
3186                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3187         } else {
3188                 tp->set_speed = rtl8169_set_speed_xmii;
3189                 tp->get_settings = rtl8169_gset_xmii;
3190                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3191                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3192                 tp->link_ok = rtl8169_xmii_link_ok;
3193                 tp->do_ioctl = rtl_xmii_ioctl;
3194         }
3195
3196         spin_lock_init(&tp->lock);
3197
3198         tp->mmio_addr = ioaddr;
3199
3200         /* Get MAC address */
3201         for (i = 0; i < MAC_ADDR_LEN; i++)
3202                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3203         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3204
3205         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3206         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3207         dev->irq = pdev->irq;
3208         dev->base_addr = (unsigned long) ioaddr;
3209
3210         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3211
3212         dev->features |= NETIF_F_HW_VLAN_TX_RX | NETIF_F_GRO;
3213
3214         tp->intr_mask = 0xffff;
3215         tp->hw_start = cfg->hw_start;
3216         tp->intr_event = cfg->intr_event;
3217         tp->napi_event = cfg->napi_event;
3218
3219         init_timer(&tp->timer);
3220         tp->timer.data = (unsigned long) dev;
3221         tp->timer.function = rtl8169_phy_timer;
3222
3223         rc = register_netdev(dev);
3224         if (rc < 0)
3225                 goto err_out_msi_4;
3226
3227         pci_set_drvdata(pdev, dev);
3228
3229         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3230                    rtl_chip_info[tp->chipset].name,
3231                    dev->base_addr, dev->dev_addr,
3232                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3233
3234         if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3235             (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3236                 rtl8168_driver_start(tp);
3237         }
3238
3239         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3240
3241         if (pci_dev_run_wake(pdev))
3242                 pm_runtime_put_noidle(&pdev->dev);
3243
3244         netif_carrier_off(dev);
3245
3246 out:
3247         return rc;
3248
3249 err_out_msi_4:
3250         rtl_disable_msi(pdev, tp);
3251         iounmap(ioaddr);
3252 err_out_free_res_3:
3253         pci_release_regions(pdev);
3254 err_out_mwi_2:
3255         pci_clear_mwi(pdev);
3256         pci_disable_device(pdev);
3257 err_out_free_dev_1:
3258         free_netdev(dev);
3259         goto out;
3260 }
3261
3262 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3263 {
3264         struct net_device *dev = pci_get_drvdata(pdev);
3265         struct rtl8169_private *tp = netdev_priv(dev);
3266
3267         if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3268             (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3269                 rtl8168_driver_stop(tp);
3270         }
3271
3272         cancel_delayed_work_sync(&tp->task);
3273
3274         rtl_release_firmware(tp);
3275
3276         unregister_netdev(dev);
3277
3278         if (pci_dev_run_wake(pdev))
3279                 pm_runtime_get_noresume(&pdev->dev);
3280
3281         /* restore original MAC address */
3282         rtl_rar_set(tp, dev->perm_addr);
3283
3284         rtl_disable_msi(pdev, tp);
3285         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3286         pci_set_drvdata(pdev, NULL);
3287 }
3288
3289 static int rtl8169_open(struct net_device *dev)
3290 {
3291         struct rtl8169_private *tp = netdev_priv(dev);
3292         void __iomem *ioaddr = tp->mmio_addr;
3293         struct pci_dev *pdev = tp->pci_dev;
3294         int retval = -ENOMEM;
3295
3296         pm_runtime_get_sync(&pdev->dev);
3297
3298         /*
3299          * Rx and Tx desscriptors needs 256 bytes alignment.
3300          * dma_alloc_coherent provides more.
3301          */
3302         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3303                                              &tp->TxPhyAddr, GFP_KERNEL);
3304         if (!tp->TxDescArray)
3305                 goto err_pm_runtime_put;
3306
3307         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3308                                              &tp->RxPhyAddr, GFP_KERNEL);
3309         if (!tp->RxDescArray)
3310                 goto err_free_tx_0;
3311
3312         retval = rtl8169_init_ring(dev);
3313         if (retval < 0)
3314                 goto err_free_rx_1;
3315
3316         INIT_DELAYED_WORK(&tp->task, NULL);
3317
3318         smp_mb();
3319
3320         retval = request_irq(dev->irq, rtl8169_interrupt,
3321                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3322                              dev->name, dev);
3323         if (retval < 0)
3324                 goto err_release_ring_2;
3325
3326         napi_enable(&tp->napi);
3327
3328         rtl8169_init_phy(dev, tp);
3329
3330         rtl8169_vlan_mode(dev);
3331
3332         rtl_pll_power_up(tp);
3333
3334         rtl_hw_start(dev);
3335
3336         rtl8169_request_timer(dev);
3337
3338         tp->saved_wolopts = 0;
3339         pm_runtime_put_noidle(&pdev->dev);
3340
3341         rtl8169_check_link_status(dev, tp, ioaddr);
3342 out:
3343         return retval;
3344
3345 err_release_ring_2:
3346         rtl8169_rx_clear(tp);
3347 err_free_rx_1:
3348         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3349                           tp->RxPhyAddr);
3350         tp->RxDescArray = NULL;
3351 err_free_tx_0:
3352         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3353                           tp->TxPhyAddr);
3354         tp->TxDescArray = NULL;
3355 err_pm_runtime_put:
3356         pm_runtime_put_noidle(&pdev->dev);
3357         goto out;
3358 }
3359
3360 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3361 {
3362         void __iomem *ioaddr = tp->mmio_addr;
3363
3364         /* Disable interrupts */
3365         rtl8169_irq_mask_and_ack(ioaddr);
3366
3367         if (tp->mac_version == RTL_GIGA_MAC_VER_28) {
3368                 while (RTL_R8(TxPoll) & NPQ)
3369                         udelay(20);
3370
3371         }
3372
3373         /* Reset the chipset */
3374         RTL_W8(ChipCmd, CmdReset);
3375
3376         /* PCI commit */
3377         RTL_R8(ChipCmd);
3378 }
3379
3380 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3381 {
3382         void __iomem *ioaddr = tp->mmio_addr;
3383         u32 cfg = rtl8169_rx_config;
3384
3385         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3386         RTL_W32(RxConfig, cfg);
3387
3388         /* Set DMA burst size and Interframe Gap Time */
3389         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3390                 (InterFrameGap << TxInterFrameGapShift));
3391 }
3392
3393 static void rtl_hw_start(struct net_device *dev)
3394 {
3395         struct rtl8169_private *tp = netdev_priv(dev);
3396         void __iomem *ioaddr = tp->mmio_addr;
3397         unsigned int i;
3398
3399         /* Soft reset the chip. */
3400         RTL_W8(ChipCmd, CmdReset);
3401
3402         /* Check that the chip has finished the reset. */
3403         for (i = 0; i < 100; i++) {
3404                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3405                         break;
3406                 msleep_interruptible(1);
3407         }
3408
3409         tp->hw_start(dev);
3410
3411         netif_start_queue(dev);
3412 }
3413
3414
3415 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3416                                          void __iomem *ioaddr)
3417 {
3418         /*
3419          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3420          * register to be written before TxDescAddrLow to work.
3421          * Switching from MMIO to I/O access fixes the issue as well.
3422          */
3423         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3424         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3425         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3426         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3427 }
3428
3429 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3430 {
3431         u16 cmd;
3432
3433         cmd = RTL_R16(CPlusCmd);
3434         RTL_W16(CPlusCmd, cmd);
3435         return cmd;
3436 }
3437
3438 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3439 {
3440         /* Low hurts. Let's disable the filtering. */
3441         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3442 }
3443
3444 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3445 {
3446         static const struct {
3447                 u32 mac_version;
3448                 u32 clk;
3449                 u32 val;
3450         } cfg2_info [] = {
3451                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3452                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3453                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3454                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3455         }, *p = cfg2_info;
3456         unsigned int i;
3457         u32 clk;
3458
3459         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3460         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3461                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3462                         RTL_W32(0x7c, p->val);
3463                         break;
3464                 }
3465         }
3466 }
3467
3468 static void rtl_hw_start_8169(struct net_device *dev)
3469 {
3470         struct rtl8169_private *tp = netdev_priv(dev);
3471         void __iomem *ioaddr = tp->mmio_addr;
3472         struct pci_dev *pdev = tp->pci_dev;
3473
3474         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3475                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3476                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3477         }
3478
3479         RTL_W8(Cfg9346, Cfg9346_Unlock);
3480         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3481             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3482             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3483             (tp->mac_version == RTL_GIGA_MAC_VER_04))
3484                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3485
3486         RTL_W8(EarlyTxThres, NoEarlyTx);
3487
3488         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3489
3490         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3491             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3492             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3493             (tp->mac_version == RTL_GIGA_MAC_VER_04))
3494                 rtl_set_rx_tx_config_registers(tp);
3495
3496         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3497
3498         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3499             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3500                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3501                         "Bit-3 and bit-14 MUST be 1\n");
3502                 tp->cp_cmd |= (1 << 14);
3503         }
3504
3505         RTL_W16(CPlusCmd, tp->cp_cmd);
3506
3507         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3508
3509         /*
3510          * Undocumented corner. Supposedly:
3511          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3512          */
3513         RTL_W16(IntrMitigate, 0x0000);
3514
3515         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3516
3517         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3518             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3519             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3520             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3521                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3522                 rtl_set_rx_tx_config_registers(tp);
3523         }
3524
3525         RTL_W8(Cfg9346, Cfg9346_Lock);
3526
3527         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3528         RTL_R8(IntrMask);
3529
3530         RTL_W32(RxMissed, 0);
3531
3532         rtl_set_rx_mode(dev);
3533
3534         /* no early-rx interrupts */
3535         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3536
3537         /* Enable all known interrupts by setting the interrupt mask. */
3538         RTL_W16(IntrMask, tp->intr_event);
3539 }
3540
3541 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3542 {
3543         struct net_device *dev = pci_get_drvdata(pdev);
3544         struct rtl8169_private *tp = netdev_priv(dev);
3545         int cap = tp->pcie_cap;
3546
3547         if (cap) {
3548                 u16 ctl;
3549
3550                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3551                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3552                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3553         }
3554 }
3555
3556 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3557 {
3558         u32 csi;
3559
3560         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3561         rtl_csi_write(ioaddr, 0x070c, csi | bits);
3562 }
3563
3564 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3565 {
3566         rtl_csi_access_enable(ioaddr, 0x17000000);
3567 }
3568
3569 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3570 {
3571         rtl_csi_access_enable(ioaddr, 0x27000000);
3572 }
3573
3574 struct ephy_info {
3575         unsigned int offset;
3576         u16 mask;
3577         u16 bits;
3578 };
3579
3580 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3581 {
3582         u16 w;
3583
3584         while (len-- > 0) {
3585                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3586                 rtl_ephy_write(ioaddr, e->offset, w);
3587                 e++;
3588         }
3589 }
3590
3591 static void rtl_disable_clock_request(struct pci_dev *pdev)
3592 {
3593         struct net_device *dev = pci_get_drvdata(pdev);
3594         struct rtl8169_private *tp = netdev_priv(dev);
3595         int cap = tp->pcie_cap;
3596
3597         if (cap) {
3598                 u16 ctl;
3599
3600                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3601                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3602                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3603         }
3604 }
3605
3606 static void rtl_enable_clock_request(struct pci_dev *pdev)
3607 {
3608         struct net_device *dev = pci_get_drvdata(pdev);
3609         struct rtl8169_private *tp = netdev_priv(dev);
3610         int cap = tp->pcie_cap;
3611
3612         if (cap) {
3613                 u16 ctl;
3614
3615                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3616                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3617                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3618         }
3619 }
3620
3621 #define R8168_CPCMD_QUIRK_MASK (\
3622         EnableBist | \
3623         Mac_dbgo_oe | \
3624         Force_half_dup | \
3625         Force_rxflow_en | \
3626         Force_txflow_en | \
3627         Cxpl_dbg_sel | \
3628         ASF | \
3629         PktCntrDisable | \
3630         Mac_dbgo_sel)
3631
3632 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3633 {
3634         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3635
3636         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3637
3638         rtl_tx_performance_tweak(pdev,
3639                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3640 }
3641
3642 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3643 {
3644         rtl_hw_start_8168bb(ioaddr, pdev);
3645
3646         RTL_W8(MaxTxPacketSize, TxPacketMax);
3647
3648         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3649 }
3650
3651 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3652 {
3653         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3654
3655         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3656
3657         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3658
3659         rtl_disable_clock_request(pdev);
3660
3661         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3662 }
3663
3664 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3665 {
3666         static const struct ephy_info e_info_8168cp[] = {
3667                 { 0x01, 0,      0x0001 },
3668                 { 0x02, 0x0800, 0x1000 },
3669                 { 0x03, 0,      0x0042 },
3670                 { 0x06, 0x0080, 0x0000 },
3671                 { 0x07, 0,      0x2000 }
3672         };
3673
3674         rtl_csi_access_enable_2(ioaddr);
3675
3676         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3677
3678         __rtl_hw_start_8168cp(ioaddr, pdev);
3679 }
3680
3681 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3682 {
3683         rtl_csi_access_enable_2(ioaddr);
3684
3685         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3686
3687         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3688
3689         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3690 }
3691
3692 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3693 {
3694         rtl_csi_access_enable_2(ioaddr);
3695
3696         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3697
3698         /* Magic. */
3699         RTL_W8(DBG_REG, 0x20);
3700
3701         RTL_W8(MaxTxPacketSize, TxPacketMax);
3702
3703         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3704
3705         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3706 }
3707
3708 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3709 {
3710         static const struct ephy_info e_info_8168c_1[] = {
3711                 { 0x02, 0x0800, 0x1000 },
3712                 { 0x03, 0,      0x0002 },
3713                 { 0x06, 0x0080, 0x0000 }
3714         };
3715
3716         rtl_csi_access_enable_2(ioaddr);
3717
3718         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3719
3720         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3721
3722         __rtl_hw_start_8168cp(ioaddr, pdev);
3723 }
3724
3725 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3726 {
3727         static const struct ephy_info e_info_8168c_2[] = {
3728                 { 0x01, 0,      0x0001 },
3729                 { 0x03, 0x0400, 0x0220 }
3730         };
3731
3732         rtl_csi_access_enable_2(ioaddr);
3733
3734         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3735
3736         __rtl_hw_start_8168cp(ioaddr, pdev);
3737 }
3738
3739 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3740 {
3741         rtl_hw_start_8168c_2(ioaddr, pdev);
3742 }
3743
3744 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3745 {
3746         rtl_csi_access_enable_2(ioaddr);
3747
3748         __rtl_hw_start_8168cp(ioaddr, pdev);
3749 }
3750
3751 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3752 {
3753         rtl_csi_access_enable_2(ioaddr);
3754
3755         rtl_disable_clock_request(pdev);
3756
3757         RTL_W8(MaxTxPacketSize, TxPacketMax);
3758
3759         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3760
3761         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3762 }
3763
3764 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
3765 {
3766         static const struct ephy_info e_info_8168d_4[] = {
3767                 { 0x0b, ~0,     0x48 },
3768                 { 0x19, 0x20,   0x50 },
3769                 { 0x0c, ~0,     0x20 }
3770         };
3771         int i;
3772
3773         rtl_csi_access_enable_1(ioaddr);
3774
3775         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3776
3777         RTL_W8(MaxTxPacketSize, TxPacketMax);
3778
3779         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
3780                 const struct ephy_info *e = e_info_8168d_4 + i;
3781                 u16 w;
3782
3783                 w = rtl_ephy_read(ioaddr, e->offset);
3784                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
3785         }
3786
3787         rtl_enable_clock_request(pdev);
3788 }
3789
3790 static void rtl_hw_start_8168(struct net_device *dev)
3791 {
3792         struct rtl8169_private *tp = netdev_priv(dev);
3793         void __iomem *ioaddr = tp->mmio_addr;
3794         struct pci_dev *pdev = tp->pci_dev;
3795
3796         RTL_W8(Cfg9346, Cfg9346_Unlock);
3797
3798         RTL_W8(MaxTxPacketSize, TxPacketMax);
3799
3800         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3801
3802         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3803
3804         RTL_W16(CPlusCmd, tp->cp_cmd);
3805
3806         RTL_W16(IntrMitigate, 0x5151);
3807
3808         /* Work around for RxFIFO overflow. */
3809         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
3810             tp->mac_version == RTL_GIGA_MAC_VER_22) {
3811                 tp->intr_event |= RxFIFOOver | PCSTimeout;
3812                 tp->intr_event &= ~RxOverflow;
3813         }
3814
3815         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3816
3817         rtl_set_rx_mode(dev);
3818
3819         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3820                 (InterFrameGap << TxInterFrameGapShift));
3821
3822         RTL_R8(IntrMask);
3823
3824         switch (tp->mac_version) {
3825         case RTL_GIGA_MAC_VER_11:
3826                 rtl_hw_start_8168bb(ioaddr, pdev);
3827         break;
3828
3829         case RTL_GIGA_MAC_VER_12:
3830         case RTL_GIGA_MAC_VER_17:
3831                 rtl_hw_start_8168bef(ioaddr, pdev);
3832         break;
3833
3834         case RTL_GIGA_MAC_VER_18:
3835                 rtl_hw_start_8168cp_1(ioaddr, pdev);
3836         break;
3837
3838         case RTL_GIGA_MAC_VER_19:
3839                 rtl_hw_start_8168c_1(ioaddr, pdev);
3840         break;
3841
3842         case RTL_GIGA_MAC_VER_20:
3843                 rtl_hw_start_8168c_2(ioaddr, pdev);
3844         break;
3845
3846         case RTL_GIGA_MAC_VER_21:
3847                 rtl_hw_start_8168c_3(ioaddr, pdev);
3848         break;
3849
3850         case RTL_GIGA_MAC_VER_22:
3851                 rtl_hw_start_8168c_4(ioaddr, pdev);
3852         break;
3853
3854         case RTL_GIGA_MAC_VER_23:
3855                 rtl_hw_start_8168cp_2(ioaddr, pdev);
3856         break;
3857
3858         case RTL_GIGA_MAC_VER_24:
3859                 rtl_hw_start_8168cp_3(ioaddr, pdev);
3860         break;
3861
3862         case RTL_GIGA_MAC_VER_25:
3863         case RTL_GIGA_MAC_VER_26:
3864         case RTL_GIGA_MAC_VER_27:
3865                 rtl_hw_start_8168d(ioaddr, pdev);
3866         break;
3867
3868         case RTL_GIGA_MAC_VER_28:
3869                 rtl_hw_start_8168d_4(ioaddr, pdev);
3870         break;
3871
3872         default:
3873                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3874                         dev->name, tp->mac_version);
3875         break;
3876         }
3877
3878         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3879
3880         RTL_W8(Cfg9346, Cfg9346_Lock);
3881
3882         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3883
3884         RTL_W16(IntrMask, tp->intr_event);
3885 }
3886
3887 #define R810X_CPCMD_QUIRK_MASK (\
3888         EnableBist | \
3889         Mac_dbgo_oe | \
3890         Force_half_dup | \
3891         Force_rxflow_en | \
3892         Force_txflow_en | \
3893         Cxpl_dbg_sel | \
3894         ASF | \
3895         PktCntrDisable | \
3896         PCIDAC | \
3897         PCIMulRW)
3898
3899 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3900 {
3901         static const struct ephy_info e_info_8102e_1[] = {
3902                 { 0x01, 0, 0x6e65 },
3903                 { 0x02, 0, 0x091f },
3904                 { 0x03, 0, 0xc2f9 },
3905                 { 0x06, 0, 0xafb5 },
3906                 { 0x07, 0, 0x0e00 },
3907                 { 0x19, 0, 0xec80 },
3908                 { 0x01, 0, 0x2e65 },
3909                 { 0x01, 0, 0x6e65 }
3910         };
3911         u8 cfg1;
3912
3913         rtl_csi_access_enable_2(ioaddr);
3914
3915         RTL_W8(DBG_REG, FIX_NAK_1);
3916
3917         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3918
3919         RTL_W8(Config1,
3920                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3921         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3922
3923         cfg1 = RTL_R8(Config1);
3924         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3925                 RTL_W8(Config1, cfg1 & ~LEDS0);
3926
3927         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3928
3929         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3930 }
3931
3932 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3933 {
3934         rtl_csi_access_enable_2(ioaddr);
3935
3936         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3937
3938         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3939         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3940
3941         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3942 }
3943
3944 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3945 {
3946         rtl_hw_start_8102e_2(ioaddr, pdev);
3947
3948         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3949 }
3950
3951 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3952 {
3953         static const struct ephy_info e_info_8105e_1[] = {
3954                 { 0x07, 0, 0x4000 },
3955                 { 0x19, 0, 0x0200 },
3956                 { 0x19, 0, 0x0020 },
3957                 { 0x1e, 0, 0x2000 },
3958                 { 0x03, 0, 0x0001 },
3959                 { 0x19, 0, 0x0100 },
3960                 { 0x19, 0, 0x0004 },
3961                 { 0x0a, 0, 0x0020 }
3962         };
3963
3964         /* Force LAN exit from ASPM if Rx/Tx are not idel */
3965         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
3966
3967         /* disable Early Tally Counter */
3968         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
3969
3970         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
3971         RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
3972
3973         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
3974 }
3975
3976 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3977 {
3978         rtl_hw_start_8105e_1(ioaddr, pdev);
3979         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
3980 }
3981
3982 static void rtl_hw_start_8101(struct net_device *dev)
3983 {
3984         struct rtl8169_private *tp = netdev_priv(dev);
3985         void __iomem *ioaddr = tp->mmio_addr;
3986         struct pci_dev *pdev = tp->pci_dev;
3987
3988         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3989             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3990                 int cap = tp->pcie_cap;
3991
3992                 if (cap) {
3993                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3994                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
3995                 }
3996         }
3997
3998         switch (tp->mac_version) {
3999         case RTL_GIGA_MAC_VER_07:
4000                 rtl_hw_start_8102e_1(ioaddr, pdev);
4001                 break;
4002
4003         case RTL_GIGA_MAC_VER_08:
4004                 rtl_hw_start_8102e_3(ioaddr, pdev);
4005                 break;
4006
4007         case RTL_GIGA_MAC_VER_09:
4008                 rtl_hw_start_8102e_2(ioaddr, pdev);
4009                 break;
4010
4011         case RTL_GIGA_MAC_VER_29:
4012                 rtl_hw_start_8105e_1(ioaddr, pdev);
4013                 break;
4014         case RTL_GIGA_MAC_VER_30:
4015                 rtl_hw_start_8105e_2(ioaddr, pdev);
4016                 break;
4017         }
4018
4019         RTL_W8(Cfg9346, Cfg9346_Unlock);
4020
4021         RTL_W8(MaxTxPacketSize, TxPacketMax);
4022
4023         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4024
4025         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4026
4027         RTL_W16(CPlusCmd, tp->cp_cmd);
4028
4029         RTL_W16(IntrMitigate, 0x0000);
4030
4031         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4032
4033         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4034         rtl_set_rx_tx_config_registers(tp);
4035
4036         RTL_W8(Cfg9346, Cfg9346_Lock);
4037
4038         RTL_R8(IntrMask);
4039
4040         rtl_set_rx_mode(dev);
4041
4042         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4043
4044         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4045
4046         RTL_W16(IntrMask, tp->intr_event);
4047 }
4048
4049 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4050 {
4051         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4052                 return -EINVAL;
4053
4054         dev->mtu = new_mtu;
4055         return 0;
4056 }
4057
4058 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4059 {
4060         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4061         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4062 }
4063
4064 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4065                                      void **data_buff, struct RxDesc *desc)
4066 {
4067         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4068                          DMA_FROM_DEVICE);
4069
4070         kfree(*data_buff);
4071         *data_buff = NULL;
4072         rtl8169_make_unusable_by_asic(desc);
4073 }
4074
4075 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4076 {
4077         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4078
4079         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4080 }
4081
4082 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4083                                        u32 rx_buf_sz)
4084 {
4085         desc->addr = cpu_to_le64(mapping);
4086         wmb();
4087         rtl8169_mark_to_asic(desc, rx_buf_sz);
4088 }
4089
4090 static inline void *rtl8169_align(void *data)
4091 {
4092         return (void *)ALIGN((long)data, 16);
4093 }
4094
4095 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4096                                              struct RxDesc *desc)
4097 {
4098         void *data;
4099         dma_addr_t mapping;
4100         struct device *d = &tp->pci_dev->dev;
4101         struct net_device *dev = tp->dev;
4102         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4103
4104         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4105         if (!data)
4106                 return NULL;
4107
4108         if (rtl8169_align(data) != data) {
4109                 kfree(data);
4110                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4111                 if (!data)
4112                         return NULL;
4113         }
4114
4115         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4116                                  DMA_FROM_DEVICE);
4117         if (unlikely(dma_mapping_error(d, mapping))) {
4118                 if (net_ratelimit())
4119                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4120                 goto err_out;
4121         }
4122
4123         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4124         return data;
4125
4126 err_out:
4127         kfree(data);
4128         return NULL;
4129 }
4130
4131 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4132 {
4133         unsigned int i;
4134
4135         for (i = 0; i < NUM_RX_DESC; i++) {
4136                 if (tp->Rx_databuff[i]) {
4137                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4138                                             tp->RxDescArray + i);
4139                 }
4140         }
4141 }
4142
4143 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4144 {
4145         desc->opts1 |= cpu_to_le32(RingEnd);
4146 }
4147
4148 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4149 {
4150         unsigned int i;
4151
4152         for (i = 0; i < NUM_RX_DESC; i++) {
4153                 void *data;
4154
4155                 if (tp->Rx_databuff[i])
4156                         continue;
4157
4158                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4159                 if (!data) {
4160                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4161                         goto err_out;
4162                 }
4163                 tp->Rx_databuff[i] = data;
4164         }
4165
4166         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4167         return 0;
4168
4169 err_out:
4170         rtl8169_rx_clear(tp);
4171         return -ENOMEM;
4172 }
4173
4174 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4175 {
4176         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4177 }
4178
4179 static int rtl8169_init_ring(struct net_device *dev)
4180 {
4181         struct rtl8169_private *tp = netdev_priv(dev);
4182
4183         rtl8169_init_ring_indexes(tp);
4184
4185         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4186         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4187
4188         return rtl8169_rx_fill(tp);
4189 }
4190
4191 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4192                                  struct TxDesc *desc)
4193 {
4194         unsigned int len = tx_skb->len;
4195
4196         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4197
4198         desc->opts1 = 0x00;
4199         desc->opts2 = 0x00;
4200         desc->addr = 0x00;
4201         tx_skb->len = 0;
4202 }
4203
4204 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4205                                    unsigned int n)
4206 {
4207         unsigned int i;
4208
4209         for (i = 0; i < n; i++) {
4210                 unsigned int entry = (start + i) % NUM_TX_DESC;
4211                 struct ring_info *tx_skb = tp->tx_skb + entry;
4212                 unsigned int len = tx_skb->len;
4213
4214                 if (len) {
4215                         struct sk_buff *skb = tx_skb->skb;
4216
4217                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4218                                              tp->TxDescArray + entry);
4219                         if (skb) {
4220                                 tp->dev->stats.tx_dropped++;
4221                                 dev_kfree_skb(skb);
4222                                 tx_skb->skb = NULL;
4223                         }
4224                 }
4225         }
4226 }
4227
4228 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4229 {
4230         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4231         tp->cur_tx = tp->dirty_tx = 0;
4232 }
4233
4234 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4235 {
4236         struct rtl8169_private *tp = netdev_priv(dev);
4237
4238         PREPARE_DELAYED_WORK(&tp->task, task);
4239         schedule_delayed_work(&tp->task, 4);
4240 }
4241
4242 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4243 {
4244         struct rtl8169_private *tp = netdev_priv(dev);
4245         void __iomem *ioaddr = tp->mmio_addr;
4246
4247         synchronize_irq(dev->irq);
4248
4249         /* Wait for any pending NAPI task to complete */
4250         napi_disable(&tp->napi);
4251
4252         rtl8169_irq_mask_and_ack(ioaddr);
4253
4254         tp->intr_mask = 0xffff;
4255         RTL_W16(IntrMask, tp->intr_event);
4256         napi_enable(&tp->napi);
4257 }
4258
4259 static void rtl8169_reinit_task(struct work_struct *work)
4260 {
4261         struct rtl8169_private *tp =
4262                 container_of(work, struct rtl8169_private, task.work);
4263         struct net_device *dev = tp->dev;
4264         int ret;
4265
4266         rtnl_lock();
4267
4268         if (!netif_running(dev))
4269                 goto out_unlock;
4270
4271         rtl8169_wait_for_quiescence(dev);
4272         rtl8169_close(dev);
4273
4274         ret = rtl8169_open(dev);
4275         if (unlikely(ret < 0)) {
4276                 if (net_ratelimit())
4277                         netif_err(tp, drv, dev,
4278                                   "reinit failure (status = %d). Rescheduling\n",
4279                                   ret);
4280                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4281         }
4282
4283 out_unlock:
4284         rtnl_unlock();
4285 }
4286
4287 static void rtl8169_reset_task(struct work_struct *work)
4288 {
4289         struct rtl8169_private *tp =
4290                 container_of(work, struct rtl8169_private, task.work);
4291         struct net_device *dev = tp->dev;
4292
4293         rtnl_lock();
4294
4295         if (!netif_running(dev))
4296                 goto out_unlock;
4297
4298         rtl8169_wait_for_quiescence(dev);
4299
4300         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4301         rtl8169_tx_clear(tp);
4302
4303         if (tp->dirty_rx == tp->cur_rx) {
4304                 rtl8169_init_ring_indexes(tp);
4305                 rtl_hw_start(dev);
4306                 netif_wake_queue(dev);
4307                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4308         } else {
4309                 if (net_ratelimit())
4310                         netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4311                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4312         }
4313
4314 out_unlock:
4315         rtnl_unlock();
4316 }
4317
4318 static void rtl8169_tx_timeout(struct net_device *dev)
4319 {
4320         struct rtl8169_private *tp = netdev_priv(dev);
4321
4322         rtl8169_hw_reset(tp);
4323
4324         /* Let's wait a bit while any (async) irq lands on */
4325         rtl8169_schedule_work(dev, rtl8169_reset_task);
4326 }
4327
4328 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4329                               u32 opts1)
4330 {
4331         struct skb_shared_info *info = skb_shinfo(skb);
4332         unsigned int cur_frag, entry;
4333         struct TxDesc * uninitialized_var(txd);
4334         struct device *d = &tp->pci_dev->dev;
4335
4336         entry = tp->cur_tx;
4337         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4338                 skb_frag_t *frag = info->frags + cur_frag;
4339                 dma_addr_t mapping;
4340                 u32 status, len;
4341                 void *addr;
4342
4343                 entry = (entry + 1) % NUM_TX_DESC;
4344
4345                 txd = tp->TxDescArray + entry;
4346                 len = frag->size;
4347                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4348                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4349                 if (unlikely(dma_mapping_error(d, mapping))) {
4350                         if (net_ratelimit())
4351                                 netif_err(tp, drv, tp->dev,
4352                                           "Failed to map TX fragments DMA!\n");
4353                         goto err_out;
4354                 }
4355
4356                 /* anti gcc 2.95.3 bugware (sic) */
4357                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4358
4359                 txd->opts1 = cpu_to_le32(status);
4360                 txd->addr = cpu_to_le64(mapping);
4361
4362                 tp->tx_skb[entry].len = len;
4363         }
4364
4365         if (cur_frag) {
4366                 tp->tx_skb[entry].skb = skb;
4367                 txd->opts1 |= cpu_to_le32(LastFrag);
4368         }
4369
4370         return cur_frag;
4371
4372 err_out:
4373         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4374         return -EIO;
4375 }
4376
4377 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4378 {
4379         if (dev->features & NETIF_F_TSO) {
4380                 u32 mss = skb_shinfo(skb)->gso_size;
4381
4382                 if (mss)
4383                         return LargeSend | ((mss & MSSMask) << MSSShift);
4384         }
4385         if (skb->ip_summed == CHECKSUM_PARTIAL) {
4386                 const struct iphdr *ip = ip_hdr(skb);
4387
4388                 if (ip->protocol == IPPROTO_TCP)
4389                         return IPCS | TCPCS;
4390                 else if (ip->protocol == IPPROTO_UDP)
4391                         return IPCS | UDPCS;
4392                 WARN_ON(1);     /* we need a WARN() */
4393         }
4394         return 0;
4395 }
4396
4397 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4398                                       struct net_device *dev)
4399 {
4400         struct rtl8169_private *tp = netdev_priv(dev);
4401         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4402         struct TxDesc *txd = tp->TxDescArray + entry;
4403         void __iomem *ioaddr = tp->mmio_addr;
4404         struct device *d = &tp->pci_dev->dev;
4405         dma_addr_t mapping;
4406         u32 status, len;
4407         u32 opts1;
4408         int frags;
4409
4410         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4411                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4412                 goto err_stop_0;
4413         }
4414
4415         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4416                 goto err_stop_0;
4417
4418         len = skb_headlen(skb);
4419         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4420         if (unlikely(dma_mapping_error(d, mapping))) {
4421                 if (net_ratelimit())
4422                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4423                 goto err_dma_0;
4424         }
4425
4426         tp->tx_skb[entry].len = len;
4427         txd->addr = cpu_to_le64(mapping);
4428         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4429
4430         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4431
4432         frags = rtl8169_xmit_frags(tp, skb, opts1);
4433         if (frags < 0)
4434                 goto err_dma_1;
4435         else if (frags)
4436                 opts1 |= FirstFrag;
4437         else {
4438                 opts1 |= FirstFrag | LastFrag;
4439                 tp->tx_skb[entry].skb = skb;
4440         }
4441
4442         wmb();
4443
4444         /* anti gcc 2.95.3 bugware (sic) */
4445         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4446         txd->opts1 = cpu_to_le32(status);
4447
4448         tp->cur_tx += frags + 1;
4449
4450         wmb();
4451
4452         RTL_W8(TxPoll, NPQ);    /* set polling bit */
4453
4454         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4455                 netif_stop_queue(dev);
4456                 smp_rmb();
4457                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4458                         netif_wake_queue(dev);
4459         }
4460
4461         return NETDEV_TX_OK;
4462
4463 err_dma_1:
4464         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4465 err_dma_0:
4466         dev_kfree_skb(skb);
4467         dev->stats.tx_dropped++;
4468         return NETDEV_TX_OK;
4469
4470 err_stop_0:
4471         netif_stop_queue(dev);
4472         dev->stats.tx_dropped++;
4473         return NETDEV_TX_BUSY;
4474 }
4475
4476 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4477 {
4478         struct rtl8169_private *tp = netdev_priv(dev);
4479         struct pci_dev *pdev = tp->pci_dev;
4480         u16 pci_status, pci_cmd;
4481
4482         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4483         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4484
4485         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4486                   pci_cmd, pci_status);
4487
4488         /*
4489          * The recovery sequence below admits a very elaborated explanation:
4490          * - it seems to work;
4491          * - I did not see what else could be done;
4492          * - it makes iop3xx happy.
4493          *
4494          * Feel free to adjust to your needs.
4495          */
4496         if (pdev->broken_parity_status)
4497                 pci_cmd &= ~PCI_COMMAND_PARITY;
4498         else
4499                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4500
4501         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4502
4503         pci_write_config_word(pdev, PCI_STATUS,
4504                 pci_status & (PCI_STATUS_DETECTED_PARITY |
4505                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4506                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4507
4508         /* The infamous DAC f*ckup only happens at boot time */
4509         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4510                 void __iomem *ioaddr = tp->mmio_addr;
4511
4512                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4513                 tp->cp_cmd &= ~PCIDAC;
4514                 RTL_W16(CPlusCmd, tp->cp_cmd);
4515                 dev->features &= ~NETIF_F_HIGHDMA;
4516         }
4517
4518         rtl8169_hw_reset(tp);
4519
4520         rtl8169_schedule_work(dev, rtl8169_reinit_task);
4521 }
4522
4523 static void rtl8169_tx_interrupt(struct net_device *dev,
4524                                  struct rtl8169_private *tp,
4525                                  void __iomem *ioaddr)
4526 {
4527         unsigned int dirty_tx, tx_left;
4528
4529         dirty_tx = tp->dirty_tx;
4530         smp_rmb();
4531         tx_left = tp->cur_tx - dirty_tx;
4532
4533         while (tx_left > 0) {
4534                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4535                 struct ring_info *tx_skb = tp->tx_skb + entry;
4536                 u32 status;
4537
4538                 rmb();
4539                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4540                 if (status & DescOwn)
4541                         break;
4542
4543                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4544                                      tp->TxDescArray + entry);
4545                 if (status & LastFrag) {
4546                         dev->stats.tx_packets++;
4547                         dev->stats.tx_bytes += tx_skb->skb->len;
4548                         dev_kfree_skb(tx_skb->skb);
4549                         tx_skb->skb = NULL;
4550                 }
4551                 dirty_tx++;
4552                 tx_left--;
4553         }
4554
4555         if (tp->dirty_tx != dirty_tx) {
4556                 tp->dirty_tx = dirty_tx;
4557                 smp_wmb();
4558                 if (netif_queue_stopped(dev) &&
4559                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4560                         netif_wake_queue(dev);
4561                 }
4562                 /*
4563                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4564                  * too close. Let's kick an extra TxPoll request when a burst
4565                  * of start_xmit activity is detected (if it is not detected,
4566                  * it is slow enough). -- FR
4567                  */
4568                 smp_rmb();
4569                 if (tp->cur_tx != dirty_tx)
4570                         RTL_W8(TxPoll, NPQ);
4571         }
4572 }
4573
4574 static inline int rtl8169_fragmented_frame(u32 status)
4575 {
4576         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4577 }
4578
4579 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4580 {
4581         u32 status = opts1 & RxProtoMask;
4582
4583         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4584             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4585                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4586         else
4587                 skb_checksum_none_assert(skb);
4588 }
4589
4590 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4591                                            struct rtl8169_private *tp,
4592                                            int pkt_size,
4593                                            dma_addr_t addr)
4594 {
4595         struct sk_buff *skb;
4596         struct device *d = &tp->pci_dev->dev;
4597
4598         data = rtl8169_align(data);
4599         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4600         prefetch(data);
4601         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4602         if (skb)
4603                 memcpy(skb->data, data, pkt_size);
4604         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4605
4606         return skb;
4607 }
4608
4609 /*
4610  * Warning : rtl8169_rx_interrupt() might be called :
4611  * 1) from NAPI (softirq) context
4612  *      (polling = 1 : we should call netif_receive_skb())
4613  * 2) from process context (rtl8169_reset_task())
4614  *      (polling = 0 : we must call netif_rx() instead)
4615  */
4616 static int rtl8169_rx_interrupt(struct net_device *dev,
4617                                 struct rtl8169_private *tp,
4618                                 void __iomem *ioaddr, u32 budget)
4619 {
4620         unsigned int cur_rx, rx_left;
4621         unsigned int count;
4622         int polling = (budget != ~(u32)0) ? 1 : 0;
4623
4624         cur_rx = tp->cur_rx;
4625         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4626         rx_left = min(rx_left, budget);
4627
4628         for (; rx_left > 0; rx_left--, cur_rx++) {
4629                 unsigned int entry = cur_rx % NUM_RX_DESC;
4630                 struct RxDesc *desc = tp->RxDescArray + entry;
4631                 u32 status;
4632
4633                 rmb();
4634                 status = le32_to_cpu(desc->opts1);
4635
4636                 if (status & DescOwn)
4637                         break;
4638                 if (unlikely(status & RxRES)) {
4639                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4640                                    status);
4641                         dev->stats.rx_errors++;
4642                         if (status & (RxRWT | RxRUNT))
4643                                 dev->stats.rx_length_errors++;
4644                         if (status & RxCRC)
4645                                 dev->stats.rx_crc_errors++;
4646                         if (status & RxFOVF) {
4647                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4648                                 dev->stats.rx_fifo_errors++;
4649                         }
4650                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4651                 } else {
4652                         struct sk_buff *skb;
4653                         dma_addr_t addr = le64_to_cpu(desc->addr);
4654                         int pkt_size = (status & 0x00001FFF) - 4;
4655
4656                         /*
4657                          * The driver does not support incoming fragmented
4658                          * frames. They are seen as a symptom of over-mtu
4659                          * sized frames.
4660                          */
4661                         if (unlikely(rtl8169_fragmented_frame(status))) {
4662                                 dev->stats.rx_dropped++;
4663                                 dev->stats.rx_length_errors++;
4664                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
4665                                 continue;
4666                         }
4667
4668                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4669                                                   tp, pkt_size, addr);
4670                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4671                         if (!skb) {
4672                                 dev->stats.rx_dropped++;
4673                                 continue;
4674                         }
4675
4676                         rtl8169_rx_csum(skb, status);
4677                         skb_put(skb, pkt_size);
4678                         skb->protocol = eth_type_trans(skb, dev);
4679
4680                         rtl8169_rx_vlan_tag(desc, skb);
4681
4682                         if (likely(polling))
4683                                 napi_gro_receive(&tp->napi, skb);
4684                         else
4685                                 netif_rx(skb);
4686
4687                         dev->stats.rx_bytes += pkt_size;
4688                         dev->stats.rx_packets++;
4689                 }
4690
4691                 /* Work around for AMD plateform. */
4692                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4693                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4694                         desc->opts2 = 0;
4695                         cur_rx++;
4696                 }
4697         }
4698
4699         count = cur_rx - tp->cur_rx;
4700         tp->cur_rx = cur_rx;
4701
4702         tp->dirty_rx += count;
4703
4704         return count;
4705 }
4706
4707 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4708 {
4709         struct net_device *dev = dev_instance;
4710         struct rtl8169_private *tp = netdev_priv(dev);
4711         void __iomem *ioaddr = tp->mmio_addr;
4712         int handled = 0;
4713         int status;
4714
4715         /* loop handling interrupts until we have no new ones or
4716          * we hit a invalid/hotplug case.
4717          */
4718         status = RTL_R16(IntrStatus);
4719         while (status && status != 0xffff) {
4720                 handled = 1;
4721
4722                 /* Handle all of the error cases first. These will reset
4723                  * the chip, so just exit the loop.
4724                  */
4725                 if (unlikely(!netif_running(dev))) {
4726                         rtl8169_asic_down(ioaddr);
4727                         break;
4728                 }
4729
4730                 if (unlikely(status & RxFIFOOver)) {
4731                         switch (tp->mac_version) {
4732                         /* Work around for rx fifo overflow */
4733                         case RTL_GIGA_MAC_VER_11:
4734                         case RTL_GIGA_MAC_VER_22:
4735                         case RTL_GIGA_MAC_VER_26:
4736                                 netif_stop_queue(dev);
4737                                 rtl8169_tx_timeout(dev);
4738                                 goto done;
4739                         /* Testers needed. */
4740                         case RTL_GIGA_MAC_VER_17:
4741                         case RTL_GIGA_MAC_VER_19:
4742                         case RTL_GIGA_MAC_VER_20:
4743                         case RTL_GIGA_MAC_VER_21:
4744                         case RTL_GIGA_MAC_VER_23:
4745                         case RTL_GIGA_MAC_VER_24:
4746                         case RTL_GIGA_MAC_VER_27:
4747                         case RTL_GIGA_MAC_VER_28:
4748                         /* Experimental science. Pktgen proof. */
4749                         case RTL_GIGA_MAC_VER_12:
4750                         case RTL_GIGA_MAC_VER_25:
4751                                 if (status == RxFIFOOver)
4752                                         goto done;
4753                                 break;
4754                         default:
4755                                 break;
4756                         }
4757                 }
4758
4759                 if (unlikely(status & SYSErr)) {
4760                         rtl8169_pcierr_interrupt(dev);
4761                         break;
4762                 }
4763
4764                 if (status & LinkChg)
4765                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
4766
4767                 /* We need to see the lastest version of tp->intr_mask to
4768                  * avoid ignoring an MSI interrupt and having to wait for
4769                  * another event which may never come.
4770                  */
4771                 smp_rmb();
4772                 if (status & tp->intr_mask & tp->napi_event) {
4773                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4774                         tp->intr_mask = ~tp->napi_event;
4775
4776                         if (likely(napi_schedule_prep(&tp->napi)))
4777                                 __napi_schedule(&tp->napi);
4778                         else
4779                                 netif_info(tp, intr, dev,
4780                                            "interrupt %04x in poll\n", status);
4781                 }
4782
4783                 /* We only get a new MSI interrupt when all active irq
4784                  * sources on the chip have been acknowledged. So, ack
4785                  * everything we've seen and check if new sources have become
4786                  * active to avoid blocking all interrupts from the chip.
4787                  */
4788                 RTL_W16(IntrStatus,
4789                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
4790                 status = RTL_R16(IntrStatus);
4791         }
4792 done:
4793         return IRQ_RETVAL(handled);
4794 }
4795
4796 static int rtl8169_poll(struct napi_struct *napi, int budget)
4797 {
4798         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4799         struct net_device *dev = tp->dev;
4800         void __iomem *ioaddr = tp->mmio_addr;
4801         int work_done;
4802
4803         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4804         rtl8169_tx_interrupt(dev, tp, ioaddr);
4805
4806         if (work_done < budget) {
4807                 napi_complete(napi);
4808
4809                 /* We need for force the visibility of tp->intr_mask
4810                  * for other CPUs, as we can loose an MSI interrupt
4811                  * and potentially wait for a retransmit timeout if we don't.
4812                  * The posted write to IntrMask is safe, as it will
4813                  * eventually make it to the chip and we won't loose anything
4814                  * until it does.
4815                  */
4816                 tp->intr_mask = 0xffff;
4817                 wmb();
4818                 RTL_W16(IntrMask, tp->intr_event);
4819         }
4820
4821         return work_done;
4822 }
4823
4824 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4825 {
4826         struct rtl8169_private *tp = netdev_priv(dev);
4827
4828         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4829                 return;
4830
4831         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4832         RTL_W32(RxMissed, 0);
4833 }
4834
4835 static void rtl8169_down(struct net_device *dev)
4836 {
4837         struct rtl8169_private *tp = netdev_priv(dev);
4838         void __iomem *ioaddr = tp->mmio_addr;
4839
4840         rtl8169_delete_timer(dev);
4841
4842         netif_stop_queue(dev);
4843
4844         napi_disable(&tp->napi);
4845
4846         spin_lock_irq(&tp->lock);
4847
4848         rtl8169_asic_down(ioaddr);
4849         /*
4850          * At this point device interrupts can not be enabled in any function,
4851          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4852          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4853          */
4854         rtl8169_rx_missed(dev, ioaddr);
4855
4856         spin_unlock_irq(&tp->lock);
4857
4858         synchronize_irq(dev->irq);
4859
4860         /* Give a racing hard_start_xmit a few cycles to complete. */
4861         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
4862
4863         rtl8169_tx_clear(tp);
4864
4865         rtl8169_rx_clear(tp);
4866
4867         rtl_pll_power_down(tp);
4868 }
4869
4870 static int rtl8169_close(struct net_device *dev)
4871 {
4872         struct rtl8169_private *tp = netdev_priv(dev);
4873         struct pci_dev *pdev = tp->pci_dev;
4874
4875         pm_runtime_get_sync(&pdev->dev);
4876
4877         /* update counters before going down */
4878         rtl8169_update_counters(dev);
4879
4880         rtl8169_down(dev);
4881
4882         free_irq(dev->irq, dev);
4883
4884         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4885                           tp->RxPhyAddr);
4886         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4887                           tp->TxPhyAddr);
4888         tp->TxDescArray = NULL;
4889         tp->RxDescArray = NULL;
4890
4891         pm_runtime_put_sync(&pdev->dev);
4892
4893         return 0;
4894 }
4895
4896 static void rtl_set_rx_mode(struct net_device *dev)
4897 {
4898         struct rtl8169_private *tp = netdev_priv(dev);
4899         void __iomem *ioaddr = tp->mmio_addr;
4900         unsigned long flags;
4901         u32 mc_filter[2];       /* Multicast hash filter */
4902         int rx_mode;
4903         u32 tmp = 0;
4904
4905         if (dev->flags & IFF_PROMISC) {
4906                 /* Unconditionally log net taps. */
4907                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4908                 rx_mode =
4909                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4910                     AcceptAllPhys;
4911                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4912         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4913                    (dev->flags & IFF_ALLMULTI)) {
4914                 /* Too many to filter perfectly -- accept all multicasts. */
4915                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4916                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4917         } else {
4918                 struct netdev_hw_addr *ha;
4919
4920                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4921                 mc_filter[1] = mc_filter[0] = 0;
4922                 netdev_for_each_mc_addr(ha, dev) {
4923                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4924                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4925                         rx_mode |= AcceptMulticast;
4926                 }
4927         }
4928
4929         spin_lock_irqsave(&tp->lock, flags);
4930
4931         tmp = rtl8169_rx_config | rx_mode |
4932               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4933
4934         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4935                 u32 data = mc_filter[0];
4936
4937                 mc_filter[0] = swab32(mc_filter[1]);
4938                 mc_filter[1] = swab32(data);
4939         }
4940
4941         RTL_W32(MAR0 + 4, mc_filter[1]);
4942         RTL_W32(MAR0 + 0, mc_filter[0]);
4943
4944         RTL_W32(RxConfig, tmp);
4945
4946         spin_unlock_irqrestore(&tp->lock, flags);
4947 }
4948
4949 /**
4950  *  rtl8169_get_stats - Get rtl8169 read/write statistics
4951  *  @dev: The Ethernet Device to get statistics for
4952  *
4953  *  Get TX/RX statistics for rtl8169
4954  */
4955 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4956 {
4957         struct rtl8169_private *tp = netdev_priv(dev);
4958         void __iomem *ioaddr = tp->mmio_addr;
4959         unsigned long flags;
4960
4961         if (netif_running(dev)) {
4962                 spin_lock_irqsave(&tp->lock, flags);
4963                 rtl8169_rx_missed(dev, ioaddr);
4964                 spin_unlock_irqrestore(&tp->lock, flags);
4965         }
4966
4967         return &dev->stats;
4968 }
4969
4970 static void rtl8169_net_suspend(struct net_device *dev)
4971 {
4972         struct rtl8169_private *tp = netdev_priv(dev);
4973
4974         if (!netif_running(dev))
4975                 return;
4976
4977         rtl_pll_power_down(tp);
4978
4979         netif_device_detach(dev);
4980         netif_stop_queue(dev);
4981 }
4982
4983 #ifdef CONFIG_PM
4984
4985 static int rtl8169_suspend(struct device *device)
4986 {
4987         struct pci_dev *pdev = to_pci_dev(device);
4988         struct net_device *dev = pci_get_drvdata(pdev);
4989
4990         rtl8169_net_suspend(dev);
4991
4992         return 0;
4993 }
4994
4995 static void __rtl8169_resume(struct net_device *dev)
4996 {
4997         struct rtl8169_private *tp = netdev_priv(dev);
4998
4999         netif_device_attach(dev);
5000
5001         rtl_pll_power_up(tp);
5002
5003         rtl8169_schedule_work(dev, rtl8169_reset_task);
5004 }
5005
5006 static int rtl8169_resume(struct device *device)
5007 {
5008         struct pci_dev *pdev = to_pci_dev(device);
5009         struct net_device *dev = pci_get_drvdata(pdev);
5010         struct rtl8169_private *tp = netdev_priv(dev);
5011
5012         rtl8169_init_phy(dev, tp);
5013
5014         if (netif_running(dev))
5015                 __rtl8169_resume(dev);
5016
5017         return 0;
5018 }
5019
5020 static int rtl8169_runtime_suspend(struct device *device)
5021 {
5022         struct pci_dev *pdev = to_pci_dev(device);
5023         struct net_device *dev = pci_get_drvdata(pdev);
5024         struct rtl8169_private *tp = netdev_priv(dev);
5025
5026         if (!tp->TxDescArray)
5027                 return 0;
5028
5029         spin_lock_irq(&tp->lock);
5030         tp->saved_wolopts = __rtl8169_get_wol(tp);
5031         __rtl8169_set_wol(tp, WAKE_ANY);
5032         spin_unlock_irq(&tp->lock);
5033
5034         rtl8169_net_suspend(dev);
5035
5036         return 0;
5037 }
5038
5039 static int rtl8169_runtime_resume(struct device *device)
5040 {
5041         struct pci_dev *pdev = to_pci_dev(device);
5042         struct net_device *dev = pci_get_drvdata(pdev);
5043         struct rtl8169_private *tp = netdev_priv(dev);
5044
5045         if (!tp->TxDescArray)
5046                 return 0;
5047
5048         spin_lock_irq(&tp->lock);
5049         __rtl8169_set_wol(tp, tp->saved_wolopts);
5050         tp->saved_wolopts = 0;
5051         spin_unlock_irq(&tp->lock);
5052
5053         rtl8169_init_phy(dev, tp);
5054
5055         __rtl8169_resume(dev);
5056
5057         return 0;
5058 }
5059
5060 static int rtl8169_runtime_idle(struct device *device)
5061 {
5062         struct pci_dev *pdev = to_pci_dev(device);
5063         struct net_device *dev = pci_get_drvdata(pdev);
5064         struct rtl8169_private *tp = netdev_priv(dev);
5065
5066         return tp->TxDescArray ? -EBUSY : 0;
5067 }
5068
5069 static const struct dev_pm_ops rtl8169_pm_ops = {
5070         .suspend = rtl8169_suspend,
5071         .resume = rtl8169_resume,
5072         .freeze = rtl8169_suspend,
5073         .thaw = rtl8169_resume,
5074         .poweroff = rtl8169_suspend,
5075         .restore = rtl8169_resume,
5076         .runtime_suspend = rtl8169_runtime_suspend,
5077         .runtime_resume = rtl8169_runtime_resume,
5078         .runtime_idle = rtl8169_runtime_idle,
5079 };
5080
5081 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5082
5083 #else /* !CONFIG_PM */
5084
5085 #define RTL8169_PM_OPS  NULL
5086
5087 #endif /* !CONFIG_PM */
5088
5089 static void rtl_shutdown(struct pci_dev *pdev)
5090 {
5091         struct net_device *dev = pci_get_drvdata(pdev);
5092         struct rtl8169_private *tp = netdev_priv(dev);
5093         void __iomem *ioaddr = tp->mmio_addr;
5094
5095         rtl8169_net_suspend(dev);
5096
5097         /* restore original MAC address */
5098         rtl_rar_set(tp, dev->perm_addr);
5099
5100         spin_lock_irq(&tp->lock);
5101
5102         rtl8169_asic_down(ioaddr);
5103
5104         spin_unlock_irq(&tp->lock);
5105
5106         if (system_state == SYSTEM_POWER_OFF) {
5107                 /* WoL fails with some 8168 when the receiver is disabled. */
5108                 if (tp->features & RTL_FEATURE_WOL) {
5109                         pci_clear_master(pdev);
5110
5111                         RTL_W8(ChipCmd, CmdRxEnb);
5112                         /* PCI commit */
5113                         RTL_R8(ChipCmd);
5114                 }
5115
5116                 pci_wake_from_d3(pdev, true);
5117                 pci_set_power_state(pdev, PCI_D3hot);
5118         }
5119 }
5120
5121 static struct pci_driver rtl8169_pci_driver = {
5122         .name           = MODULENAME,
5123         .id_table       = rtl8169_pci_tbl,
5124         .probe          = rtl8169_init_one,
5125         .remove         = __devexit_p(rtl8169_remove_one),
5126         .shutdown       = rtl_shutdown,
5127         .driver.pm      = RTL8169_PM_OPS,
5128 };
5129
5130 static int __init rtl8169_init_module(void)
5131 {
5132         return pci_register_driver(&rtl8169_pci_driver);
5133 }
5134
5135 static void __exit rtl8169_cleanup_module(void)
5136 {
5137         pci_unregister_driver(&rtl8169_pci_driver);
5138 }
5139
5140 module_init(rtl8169_init_module);
5141 module_exit(rtl8169_cleanup_module);