r8169: remove some code duplication.
[linux-2.6.git] / drivers / net / r8169.c
1 /*
2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3  *
4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6  * Copyright (c) a lot of people too. Please respect their work.
7  *
8  * See MAINTAINERS file for support contact information.
9  */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29
30 #include <asm/system.h>
31 #include <asm/io.h>
32 #include <asm/irq.h>
33
34 #define RTL8169_VERSION "2.3LK-NAPI"
35 #define MODULENAME "r8169"
36 #define PFX MODULENAME ": "
37
38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
43
44 #ifdef RTL8169_DEBUG
45 #define assert(expr) \
46         if (!(expr)) {                                  \
47                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
48                 #expr,__FILE__,__func__,__LINE__);              \
49         }
50 #define dprintk(fmt, args...) \
51         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
52 #else
53 #define assert(expr) do {} while (0)
54 #define dprintk(fmt, args...)   do {} while (0)
55 #endif /* RTL8169_DEBUG */
56
57 #define R8169_MSG_DEFAULT \
58         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
59
60 #define TX_BUFFS_AVAIL(tp) \
61         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
62
63 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
64    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
65 static const int multicast_filter_limit = 32;
66
67 /* MAC address length */
68 #define MAC_ADDR_LEN    6
69
70 #define MAX_READ_REQUEST_SHIFT  12
71 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
72 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
73 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
74 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
75 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
76
77 #define R8169_REGS_SIZE         256
78 #define R8169_NAPI_WEIGHT       64
79 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
80 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
81 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
82 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
83 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
84
85 #define RTL8169_TX_TIMEOUT      (6*HZ)
86 #define RTL8169_PHY_TIMEOUT     (10*HZ)
87
88 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
89 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
90 #define RTL_EEPROM_SIG_ADDR     0x0000
91
92 /* write/read MMIO register */
93 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
94 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
95 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
96 #define RTL_R8(reg)             readb (ioaddr + (reg))
97 #define RTL_R16(reg)            readw (ioaddr + (reg))
98 #define RTL_R32(reg)            readl (ioaddr + (reg))
99
100 enum mac_version {
101         RTL_GIGA_MAC_NONE   = 0x00,
102         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
103         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
104         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
105         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
106         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
107         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
108         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
109         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
110         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
111         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
112         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
113         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
114         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
115         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
116         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
117         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
118         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
119         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
120         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
121         RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
122         RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
123         RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
124         RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
125         RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
126         RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
127         RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
128         RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
129         RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
130         RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E
131         RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E
132         RTL_GIGA_MAC_VER_31 = 0x1f, // 8168DP
133         RTL_GIGA_MAC_VER_32 = 0x20, // 8168E
134         RTL_GIGA_MAC_VER_33 = 0x21, // 8168E
135 };
136
137 enum rtl_tx_desc_version {
138         RTL_TD_0        = 0,
139         RTL_TD_1        = 1,
140 };
141
142 #define _R(NAME,MAC,TD) \
143         { .name = NAME, .mac_version = MAC, .txd_version = TD }
144
145 static const struct {
146         const char *name;
147         u8 mac_version;
148         enum rtl_tx_desc_version txd_version;
149 } rtl_chip_info[] = {
150         _R("RTL8169",           RTL_GIGA_MAC_VER_01, RTL_TD_0), // 8169
151         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, RTL_TD_0), // 8169S
152         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, RTL_TD_0), // 8110S
153         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, RTL_TD_0), // 8169SB
154         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, RTL_TD_0), // 8110SCd
155         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, RTL_TD_0), // 8110SCe
156         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, RTL_TD_1), // PCI-E
157         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, RTL_TD_1), // PCI-E
158         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, RTL_TD_1), // PCI-E
159         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, RTL_TD_0), // PCI-E
160         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, RTL_TD_0), // PCI-E
161         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, RTL_TD_0), // PCI-E
162         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, RTL_TD_0), // PCI-E 8139
163         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, RTL_TD_0), // PCI-E 8139
164         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, RTL_TD_0), // PCI-E 8139
165         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, RTL_TD_0), // PCI-E
166         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, RTL_TD_0), // PCI-E
167         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, RTL_TD_1), // PCI-E
168         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, RTL_TD_1), // PCI-E
169         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, RTL_TD_1), // PCI-E
170         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_21, RTL_TD_1), // PCI-E
171         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_22, RTL_TD_1), // PCI-E
172         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_23, RTL_TD_1), // PCI-E
173         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_24, RTL_TD_1), // PCI-E
174         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_25, RTL_TD_1), // PCI-E
175         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_26, RTL_TD_1), // PCI-E
176         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_27, RTL_TD_1), // PCI-E
177         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_28, RTL_TD_1), // PCI-E
178         _R("RTL8105e",          RTL_GIGA_MAC_VER_29, RTL_TD_1), // PCI-E
179         _R("RTL8105e",          RTL_GIGA_MAC_VER_30, RTL_TD_1), // PCI-E
180         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_31, RTL_TD_1), // PCI-E
181         _R("RTL8168e/8111e",    RTL_GIGA_MAC_VER_32, RTL_TD_1), // PCI-E
182         _R("RTL8168e/8111e",    RTL_GIGA_MAC_VER_33, RTL_TD_1)  // PCI-E
183 };
184 #undef _R
185
186 static const struct rtl_firmware_info {
187         int mac_version;
188         const char *fw_name;
189 } rtl_firmware_infos[] = {
190         { .mac_version = RTL_GIGA_MAC_VER_25, .fw_name = FIRMWARE_8168D_1 },
191         { .mac_version = RTL_GIGA_MAC_VER_26, .fw_name = FIRMWARE_8168D_2 },
192         { .mac_version = RTL_GIGA_MAC_VER_29, .fw_name = FIRMWARE_8105E_1 },
193         { .mac_version = RTL_GIGA_MAC_VER_30, .fw_name = FIRMWARE_8105E_1 },
194         { .mac_version = RTL_GIGA_MAC_VER_32, .fw_name = FIRMWARE_8168E_1 },
195         { .mac_version = RTL_GIGA_MAC_VER_33, .fw_name = FIRMWARE_8168E_2 }
196 };
197
198 enum cfg_version {
199         RTL_CFG_0 = 0x00,
200         RTL_CFG_1,
201         RTL_CFG_2
202 };
203
204 static void rtl_hw_start_8169(struct net_device *);
205 static void rtl_hw_start_8168(struct net_device *);
206 static void rtl_hw_start_8101(struct net_device *);
207
208 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
209         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
210         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
211         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
212         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
213         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
214         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
215         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
216         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
217         { PCI_VENDOR_ID_LINKSYS,                0x1032,
218                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
219         { 0x0001,                               0x8168,
220                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
221         {0,},
222 };
223
224 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
225
226 static int rx_buf_sz = 16383;
227 static int use_dac;
228 static struct {
229         u32 msg_enable;
230 } debug = { -1 };
231
232 enum rtl_registers {
233         MAC0            = 0,    /* Ethernet hardware address. */
234         MAC4            = 4,
235         MAR0            = 8,    /* Multicast filter. */
236         CounterAddrLow          = 0x10,
237         CounterAddrHigh         = 0x14,
238         TxDescStartAddrLow      = 0x20,
239         TxDescStartAddrHigh     = 0x24,
240         TxHDescStartAddrLow     = 0x28,
241         TxHDescStartAddrHigh    = 0x2c,
242         FLASH           = 0x30,
243         ERSR            = 0x36,
244         ChipCmd         = 0x37,
245         TxPoll          = 0x38,
246         IntrMask        = 0x3c,
247         IntrStatus      = 0x3e,
248         TxConfig        = 0x40,
249         RxConfig        = 0x44,
250
251 #define RTL_RX_CONFIG_MASK              0xff7e1880u
252
253         RxMissed        = 0x4c,
254         Cfg9346         = 0x50,
255         Config0         = 0x51,
256         Config1         = 0x52,
257         Config2         = 0x53,
258         Config3         = 0x54,
259         Config4         = 0x55,
260         Config5         = 0x56,
261         MultiIntr       = 0x5c,
262         PHYAR           = 0x60,
263         PHYstatus       = 0x6c,
264         RxMaxSize       = 0xda,
265         CPlusCmd        = 0xe0,
266         IntrMitigate    = 0xe2,
267         RxDescAddrLow   = 0xe4,
268         RxDescAddrHigh  = 0xe8,
269         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
270
271 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
272
273         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
274
275 #define TxPacketMax     (8064 >> 7)
276
277         FuncEvent       = 0xf0,
278         FuncEventMask   = 0xf4,
279         FuncPresetState = 0xf8,
280         FuncForceEvent  = 0xfc,
281 };
282
283 enum rtl8110_registers {
284         TBICSR                  = 0x64,
285         TBI_ANAR                = 0x68,
286         TBI_LPAR                = 0x6a,
287 };
288
289 enum rtl8168_8101_registers {
290         CSIDR                   = 0x64,
291         CSIAR                   = 0x68,
292 #define CSIAR_FLAG                      0x80000000
293 #define CSIAR_WRITE_CMD                 0x80000000
294 #define CSIAR_BYTE_ENABLE               0x0f
295 #define CSIAR_BYTE_ENABLE_SHIFT         12
296 #define CSIAR_ADDR_MASK                 0x0fff
297         PMCH                    = 0x6f,
298         EPHYAR                  = 0x80,
299 #define EPHYAR_FLAG                     0x80000000
300 #define EPHYAR_WRITE_CMD                0x80000000
301 #define EPHYAR_REG_MASK                 0x1f
302 #define EPHYAR_REG_SHIFT                16
303 #define EPHYAR_DATA_MASK                0xffff
304         DLLPR                   = 0xd0,
305 #define PM_SWITCH                       (1 << 6)
306         DBG_REG                 = 0xd1,
307 #define FIX_NAK_1                       (1 << 4)
308 #define FIX_NAK_2                       (1 << 3)
309         TWSI                    = 0xd2,
310         MCU                     = 0xd3,
311 #define EN_NDP                          (1 << 3)
312 #define EN_OOB_RESET                    (1 << 2)
313         EFUSEAR                 = 0xdc,
314 #define EFUSEAR_FLAG                    0x80000000
315 #define EFUSEAR_WRITE_CMD               0x80000000
316 #define EFUSEAR_READ_CMD                0x00000000
317 #define EFUSEAR_REG_MASK                0x03ff
318 #define EFUSEAR_REG_SHIFT               8
319 #define EFUSEAR_DATA_MASK               0xff
320 };
321
322 enum rtl8168_registers {
323         ERIDR                   = 0x70,
324         ERIAR                   = 0x74,
325 #define ERIAR_FLAG                      0x80000000
326 #define ERIAR_WRITE_CMD                 0x80000000
327 #define ERIAR_READ_CMD                  0x00000000
328 #define ERIAR_ADDR_BYTE_ALIGN           4
329 #define ERIAR_EXGMAC                    0
330 #define ERIAR_MSIX                      1
331 #define ERIAR_ASF                       2
332 #define ERIAR_TYPE_SHIFT                16
333 #define ERIAR_BYTEEN                    0x0f
334 #define ERIAR_BYTEEN_SHIFT              12
335         EPHY_RXER_NUM           = 0x7c,
336         OCPDR                   = 0xb0, /* OCP GPHY access */
337 #define OCPDR_WRITE_CMD                 0x80000000
338 #define OCPDR_READ_CMD                  0x00000000
339 #define OCPDR_REG_MASK                  0x7f
340 #define OCPDR_GPHY_REG_SHIFT            16
341 #define OCPDR_DATA_MASK                 0xffff
342         OCPAR                   = 0xb4,
343 #define OCPAR_FLAG                      0x80000000
344 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
345 #define OCPAR_GPHY_READ_CMD             0x0000f060
346         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
347         MISC                    = 0xf0, /* 8168e only. */
348 #define TXPLA_RST                       (1 << 29)
349 };
350
351 enum rtl_register_content {
352         /* InterruptStatusBits */
353         SYSErr          = 0x8000,
354         PCSTimeout      = 0x4000,
355         SWInt           = 0x0100,
356         TxDescUnavail   = 0x0080,
357         RxFIFOOver      = 0x0040,
358         LinkChg         = 0x0020,
359         RxOverflow      = 0x0010,
360         TxErr           = 0x0008,
361         TxOK            = 0x0004,
362         RxErr           = 0x0002,
363         RxOK            = 0x0001,
364
365         /* RxStatusDesc */
366         RxFOVF  = (1 << 23),
367         RxRWT   = (1 << 22),
368         RxRES   = (1 << 21),
369         RxRUNT  = (1 << 20),
370         RxCRC   = (1 << 19),
371
372         /* ChipCmdBits */
373         CmdReset        = 0x10,
374         CmdRxEnb        = 0x08,
375         CmdTxEnb        = 0x04,
376         RxBufEmpty      = 0x01,
377
378         /* TXPoll register p.5 */
379         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
380         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
381         FSWInt          = 0x01,         /* Forced software interrupt */
382
383         /* Cfg9346Bits */
384         Cfg9346_Lock    = 0x00,
385         Cfg9346_Unlock  = 0xc0,
386
387         /* rx_mode_bits */
388         AcceptErr       = 0x20,
389         AcceptRunt      = 0x10,
390         AcceptBroadcast = 0x08,
391         AcceptMulticast = 0x04,
392         AcceptMyPhys    = 0x02,
393         AcceptAllPhys   = 0x01,
394
395         /* RxConfigBits */
396         RxCfgFIFOShift  = 13,
397         RxCfgDMAShift   =  8,
398
399         /* TxConfigBits */
400         TxInterFrameGapShift = 24,
401         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
402
403         /* Config1 register p.24 */
404         LEDS1           = (1 << 7),
405         LEDS0           = (1 << 6),
406         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
407         Speed_down      = (1 << 4),
408         MEMMAP          = (1 << 3),
409         IOMAP           = (1 << 2),
410         VPD             = (1 << 1),
411         PMEnable        = (1 << 0),     /* Power Management Enable */
412
413         /* Config2 register p. 25 */
414         PCI_Clock_66MHz = 0x01,
415         PCI_Clock_33MHz = 0x00,
416
417         /* Config3 register p.25 */
418         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
419         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
420         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
421
422         /* Config5 register p.27 */
423         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
424         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
425         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
426         Spi_en          = (1 << 3),
427         LanWake         = (1 << 1),     /* LanWake enable/disable */
428         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
429
430         /* TBICSR p.28 */
431         TBIReset        = 0x80000000,
432         TBILoopback     = 0x40000000,
433         TBINwEnable     = 0x20000000,
434         TBINwRestart    = 0x10000000,
435         TBILinkOk       = 0x02000000,
436         TBINwComplete   = 0x01000000,
437
438         /* CPlusCmd p.31 */
439         EnableBist      = (1 << 15),    // 8168 8101
440         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
441         Normal_mode     = (1 << 13),    // unused
442         Force_half_dup  = (1 << 12),    // 8168 8101
443         Force_rxflow_en = (1 << 11),    // 8168 8101
444         Force_txflow_en = (1 << 10),    // 8168 8101
445         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
446         ASF             = (1 << 8),     // 8168 8101
447         PktCntrDisable  = (1 << 7),     // 8168 8101
448         Mac_dbgo_sel    = 0x001c,       // 8168
449         RxVlan          = (1 << 6),
450         RxChkSum        = (1 << 5),
451         PCIDAC          = (1 << 4),
452         PCIMulRW        = (1 << 3),
453         INTT_0          = 0x0000,       // 8168
454         INTT_1          = 0x0001,       // 8168
455         INTT_2          = 0x0002,       // 8168
456         INTT_3          = 0x0003,       // 8168
457
458         /* rtl8169_PHYstatus */
459         TBI_Enable      = 0x80,
460         TxFlowCtrl      = 0x40,
461         RxFlowCtrl      = 0x20,
462         _1000bpsF       = 0x10,
463         _100bps         = 0x08,
464         _10bps          = 0x04,
465         LinkStatus      = 0x02,
466         FullDup         = 0x01,
467
468         /* _TBICSRBit */
469         TBILinkOK       = 0x02000000,
470
471         /* DumpCounterCommand */
472         CounterDump     = 0x8,
473 };
474
475 enum rtl_desc_bit {
476         /* First doubleword. */
477         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
478         RingEnd         = (1 << 30), /* End of descriptor ring */
479         FirstFrag       = (1 << 29), /* First segment of a packet */
480         LastFrag        = (1 << 28), /* Final segment of a packet */
481 };
482
483 /* Generic case. */
484 enum rtl_tx_desc_bit {
485         /* First doubleword. */
486         TD_LSO          = (1 << 27),            /* Large Send Offload */
487 #define TD_MSS_MAX                      0x07ffu /* MSS value */
488
489         /* Second doubleword. */
490         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
491 };
492
493 /* 8169, 8168b and 810x except 8102e. */
494 enum rtl_tx_desc_bit_0 {
495         /* First doubleword. */
496 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
497         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
498         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
499         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
500 };
501
502 /* 8102e, 8168c and beyond. */
503 enum rtl_tx_desc_bit_1 {
504         /* Second doubleword. */
505 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
506         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
507         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
508         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
509 };
510
511 static const struct rtl_tx_desc_info {
512         struct {
513                 u32 udp;
514                 u32 tcp;
515         } checksum;
516         u16 mss_shift;
517         u16 opts_offset;
518 } tx_desc_info [] = {
519         [RTL_TD_0] = {
520                 .checksum = {
521                         .udp    = TD0_IP_CS | TD0_UDP_CS,
522                         .tcp    = TD0_IP_CS | TD0_TCP_CS
523                 },
524                 .mss_shift      = TD0_MSS_SHIFT,
525                 .opts_offset    = 0
526         },
527         [RTL_TD_1] = {
528                 .checksum = {
529                         .udp    = TD1_IP_CS | TD1_UDP_CS,
530                         .tcp    = TD1_IP_CS | TD1_TCP_CS
531                 },
532                 .mss_shift      = TD1_MSS_SHIFT,
533                 .opts_offset    = 1
534         }
535 };
536
537 enum rtl_rx_desc_bit {
538         /* Rx private */
539         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
540         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
541
542 #define RxProtoUDP      (PID1)
543 #define RxProtoTCP      (PID0)
544 #define RxProtoIP       (PID1 | PID0)
545 #define RxProtoMask     RxProtoIP
546
547         IPFail          = (1 << 16), /* IP checksum failed */
548         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
549         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
550         RxVlanTag       = (1 << 16), /* VLAN tag available */
551 };
552
553 #define RsvdMask        0x3fffc000
554
555 struct TxDesc {
556         __le32 opts1;
557         __le32 opts2;
558         __le64 addr;
559 };
560
561 struct RxDesc {
562         __le32 opts1;
563         __le32 opts2;
564         __le64 addr;
565 };
566
567 struct ring_info {
568         struct sk_buff  *skb;
569         u32             len;
570         u8              __pad[sizeof(void *) - sizeof(u32)];
571 };
572
573 enum features {
574         RTL_FEATURE_WOL         = (1 << 0),
575         RTL_FEATURE_MSI         = (1 << 1),
576         RTL_FEATURE_GMII        = (1 << 2),
577 };
578
579 struct rtl8169_counters {
580         __le64  tx_packets;
581         __le64  rx_packets;
582         __le64  tx_errors;
583         __le32  rx_errors;
584         __le16  rx_missed;
585         __le16  align_errors;
586         __le32  tx_one_collision;
587         __le32  tx_multi_collision;
588         __le64  rx_unicast;
589         __le64  rx_broadcast;
590         __le32  rx_multicast;
591         __le16  tx_aborted;
592         __le16  tx_underun;
593 };
594
595 struct rtl8169_private {
596         void __iomem *mmio_addr;        /* memory map physical address */
597         struct pci_dev *pci_dev;
598         struct net_device *dev;
599         struct napi_struct napi;
600         spinlock_t lock;
601         u32 msg_enable;
602         u16 txd_version;
603         u16 mac_version;
604         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
605         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
606         u32 dirty_rx;
607         u32 dirty_tx;
608         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
609         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
610         dma_addr_t TxPhyAddr;
611         dma_addr_t RxPhyAddr;
612         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
613         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
614         struct timer_list timer;
615         u16 cp_cmd;
616         u16 intr_event;
617         u16 napi_event;
618         u16 intr_mask;
619         int phy_1000_ctrl_reg;
620
621         struct mdio_ops {
622                 void (*write)(void __iomem *, int, int);
623                 int (*read)(void __iomem *, int);
624         } mdio_ops;
625
626         struct pll_power_ops {
627                 void (*down)(struct rtl8169_private *);
628                 void (*up)(struct rtl8169_private *);
629         } pll_power_ops;
630
631         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
632         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
633         void (*phy_reset_enable)(struct rtl8169_private *tp);
634         void (*hw_start)(struct net_device *);
635         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
636         unsigned int (*link_ok)(void __iomem *);
637         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
638         int pcie_cap;
639         struct delayed_work task;
640         unsigned features;
641
642         struct mii_if_info mii;
643         struct rtl8169_counters counters;
644         u32 saved_wolopts;
645
646         const struct firmware *fw;
647 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN);
648 };
649
650 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
651 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
652 module_param(use_dac, int, 0);
653 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
654 module_param_named(debug, debug.msg_enable, int, 0);
655 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
656 MODULE_LICENSE("GPL");
657 MODULE_VERSION(RTL8169_VERSION);
658 MODULE_FIRMWARE(FIRMWARE_8168D_1);
659 MODULE_FIRMWARE(FIRMWARE_8168D_2);
660 MODULE_FIRMWARE(FIRMWARE_8168E_1);
661 MODULE_FIRMWARE(FIRMWARE_8168E_2);
662 MODULE_FIRMWARE(FIRMWARE_8105E_1);
663
664 static int rtl8169_open(struct net_device *dev);
665 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
666                                       struct net_device *dev);
667 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
668 static int rtl8169_init_ring(struct net_device *dev);
669 static void rtl_hw_start(struct net_device *dev);
670 static int rtl8169_close(struct net_device *dev);
671 static void rtl_set_rx_mode(struct net_device *dev);
672 static void rtl8169_tx_timeout(struct net_device *dev);
673 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
674 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
675                                 void __iomem *, u32 budget);
676 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
677 static void rtl8169_down(struct net_device *dev);
678 static void rtl8169_rx_clear(struct rtl8169_private *tp);
679 static int rtl8169_poll(struct napi_struct *napi, int budget);
680
681 static const unsigned int rtl8169_rx_config =
682         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
683
684 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
685 {
686         void __iomem *ioaddr = tp->mmio_addr;
687         int i;
688
689         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
690         for (i = 0; i < 20; i++) {
691                 udelay(100);
692                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
693                         break;
694         }
695         return RTL_R32(OCPDR);
696 }
697
698 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
699 {
700         void __iomem *ioaddr = tp->mmio_addr;
701         int i;
702
703         RTL_W32(OCPDR, data);
704         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
705         for (i = 0; i < 20; i++) {
706                 udelay(100);
707                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
708                         break;
709         }
710 }
711
712 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
713 {
714         void __iomem *ioaddr = tp->mmio_addr;
715         int i;
716
717         RTL_W8(ERIDR, cmd);
718         RTL_W32(ERIAR, 0x800010e8);
719         msleep(2);
720         for (i = 0; i < 5; i++) {
721                 udelay(100);
722                 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
723                         break;
724         }
725
726         ocp_write(tp, 0x1, 0x30, 0x00000001);
727 }
728
729 #define OOB_CMD_RESET           0x00
730 #define OOB_CMD_DRIVER_START    0x05
731 #define OOB_CMD_DRIVER_STOP     0x06
732
733 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
734 {
735         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
736 }
737
738 static void rtl8168_driver_start(struct rtl8169_private *tp)
739 {
740         u16 reg;
741         int i;
742
743         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
744
745         reg = rtl8168_get_ocp_reg(tp);
746
747         for (i = 0; i < 10; i++) {
748                 msleep(10);
749                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
750                         break;
751         }
752 }
753
754 static void rtl8168_driver_stop(struct rtl8169_private *tp)
755 {
756         u16 reg;
757         int i;
758
759         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
760
761         reg = rtl8168_get_ocp_reg(tp);
762
763         for (i = 0; i < 10; i++) {
764                 msleep(10);
765                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
766                         break;
767         }
768 }
769
770 static int r8168dp_check_dash(struct rtl8169_private *tp)
771 {
772         u16 reg = rtl8168_get_ocp_reg(tp);
773
774         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
775 }
776
777 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
778 {
779         int i;
780
781         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
782
783         for (i = 20; i > 0; i--) {
784                 /*
785                  * Check if the RTL8169 has completed writing to the specified
786                  * MII register.
787                  */
788                 if (!(RTL_R32(PHYAR) & 0x80000000))
789                         break;
790                 udelay(25);
791         }
792         /*
793          * According to hardware specs a 20us delay is required after write
794          * complete indication, but before sending next command.
795          */
796         udelay(20);
797 }
798
799 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
800 {
801         int i, value = -1;
802
803         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
804
805         for (i = 20; i > 0; i--) {
806                 /*
807                  * Check if the RTL8169 has completed retrieving data from
808                  * the specified MII register.
809                  */
810                 if (RTL_R32(PHYAR) & 0x80000000) {
811                         value = RTL_R32(PHYAR) & 0xffff;
812                         break;
813                 }
814                 udelay(25);
815         }
816         /*
817          * According to hardware specs a 20us delay is required after read
818          * complete indication, but before sending next command.
819          */
820         udelay(20);
821
822         return value;
823 }
824
825 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
826 {
827         int i;
828
829         RTL_W32(OCPDR, data |
830                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
831         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
832         RTL_W32(EPHY_RXER_NUM, 0);
833
834         for (i = 0; i < 100; i++) {
835                 mdelay(1);
836                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
837                         break;
838         }
839 }
840
841 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
842 {
843         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
844                 (value & OCPDR_DATA_MASK));
845 }
846
847 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
848 {
849         int i;
850
851         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
852
853         mdelay(1);
854         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
855         RTL_W32(EPHY_RXER_NUM, 0);
856
857         for (i = 0; i < 100; i++) {
858                 mdelay(1);
859                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
860                         break;
861         }
862
863         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
864 }
865
866 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
867
868 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
869 {
870         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
871 }
872
873 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
874 {
875         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
876 }
877
878 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
879 {
880         r8168dp_2_mdio_start(ioaddr);
881
882         r8169_mdio_write(ioaddr, reg_addr, value);
883
884         r8168dp_2_mdio_stop(ioaddr);
885 }
886
887 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
888 {
889         int value;
890
891         r8168dp_2_mdio_start(ioaddr);
892
893         value = r8169_mdio_read(ioaddr, reg_addr);
894
895         r8168dp_2_mdio_stop(ioaddr);
896
897         return value;
898 }
899
900 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
901 {
902         tp->mdio_ops.write(tp->mmio_addr, location, val);
903 }
904
905 static int rtl_readphy(struct rtl8169_private *tp, int location)
906 {
907         return tp->mdio_ops.read(tp->mmio_addr, location);
908 }
909
910 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
911 {
912         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
913 }
914
915 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
916 {
917         int val;
918
919         val = rtl_readphy(tp, reg_addr);
920         rtl_writephy(tp, reg_addr, (val | p) & ~m);
921 }
922
923 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
924                            int val)
925 {
926         struct rtl8169_private *tp = netdev_priv(dev);
927
928         rtl_writephy(tp, location, val);
929 }
930
931 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
932 {
933         struct rtl8169_private *tp = netdev_priv(dev);
934
935         return rtl_readphy(tp, location);
936 }
937
938 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
939 {
940         unsigned int i;
941
942         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
943                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
944
945         for (i = 0; i < 100; i++) {
946                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
947                         break;
948                 udelay(10);
949         }
950 }
951
952 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
953 {
954         u16 value = 0xffff;
955         unsigned int i;
956
957         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
958
959         for (i = 0; i < 100; i++) {
960                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
961                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
962                         break;
963                 }
964                 udelay(10);
965         }
966
967         return value;
968 }
969
970 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
971 {
972         unsigned int i;
973
974         RTL_W32(CSIDR, value);
975         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
976                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
977
978         for (i = 0; i < 100; i++) {
979                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
980                         break;
981                 udelay(10);
982         }
983 }
984
985 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
986 {
987         u32 value = ~0x00;
988         unsigned int i;
989
990         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
991                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
992
993         for (i = 0; i < 100; i++) {
994                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
995                         value = RTL_R32(CSIDR);
996                         break;
997                 }
998                 udelay(10);
999         }
1000
1001         return value;
1002 }
1003
1004 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1005 {
1006         u8 value = 0xff;
1007         unsigned int i;
1008
1009         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1010
1011         for (i = 0; i < 300; i++) {
1012                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1013                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1014                         break;
1015                 }
1016                 udelay(100);
1017         }
1018
1019         return value;
1020 }
1021
1022 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1023 {
1024         RTL_W16(IntrMask, 0x0000);
1025
1026         RTL_W16(IntrStatus, 0xffff);
1027 }
1028
1029 static void rtl8169_asic_down(void __iomem *ioaddr)
1030 {
1031         RTL_W8(ChipCmd, 0x00);
1032         rtl8169_irq_mask_and_ack(ioaddr);
1033         RTL_R16(CPlusCmd);
1034 }
1035
1036 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1037 {
1038         void __iomem *ioaddr = tp->mmio_addr;
1039
1040         return RTL_R32(TBICSR) & TBIReset;
1041 }
1042
1043 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1044 {
1045         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1046 }
1047
1048 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1049 {
1050         return RTL_R32(TBICSR) & TBILinkOk;
1051 }
1052
1053 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1054 {
1055         return RTL_R8(PHYstatus) & LinkStatus;
1056 }
1057
1058 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1059 {
1060         void __iomem *ioaddr = tp->mmio_addr;
1061
1062         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1063 }
1064
1065 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1066 {
1067         unsigned int val;
1068
1069         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1070         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1071 }
1072
1073 static void __rtl8169_check_link_status(struct net_device *dev,
1074                                         struct rtl8169_private *tp,
1075                                         void __iomem *ioaddr, bool pm)
1076 {
1077         unsigned long flags;
1078
1079         spin_lock_irqsave(&tp->lock, flags);
1080         if (tp->link_ok(ioaddr)) {
1081                 /* This is to cancel a scheduled suspend if there's one. */
1082                 if (pm)
1083                         pm_request_resume(&tp->pci_dev->dev);
1084                 netif_carrier_on(dev);
1085                 if (net_ratelimit())
1086                         netif_info(tp, ifup, dev, "link up\n");
1087         } else {
1088                 netif_carrier_off(dev);
1089                 netif_info(tp, ifdown, dev, "link down\n");
1090                 if (pm)
1091                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
1092         }
1093         spin_unlock_irqrestore(&tp->lock, flags);
1094 }
1095
1096 static void rtl8169_check_link_status(struct net_device *dev,
1097                                       struct rtl8169_private *tp,
1098                                       void __iomem *ioaddr)
1099 {
1100         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1101 }
1102
1103 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1104
1105 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1106 {
1107         void __iomem *ioaddr = tp->mmio_addr;
1108         u8 options;
1109         u32 wolopts = 0;
1110
1111         options = RTL_R8(Config1);
1112         if (!(options & PMEnable))
1113                 return 0;
1114
1115         options = RTL_R8(Config3);
1116         if (options & LinkUp)
1117                 wolopts |= WAKE_PHY;
1118         if (options & MagicPacket)
1119                 wolopts |= WAKE_MAGIC;
1120
1121         options = RTL_R8(Config5);
1122         if (options & UWF)
1123                 wolopts |= WAKE_UCAST;
1124         if (options & BWF)
1125                 wolopts |= WAKE_BCAST;
1126         if (options & MWF)
1127                 wolopts |= WAKE_MCAST;
1128
1129         return wolopts;
1130 }
1131
1132 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1133 {
1134         struct rtl8169_private *tp = netdev_priv(dev);
1135
1136         spin_lock_irq(&tp->lock);
1137
1138         wol->supported = WAKE_ANY;
1139         wol->wolopts = __rtl8169_get_wol(tp);
1140
1141         spin_unlock_irq(&tp->lock);
1142 }
1143
1144 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1145 {
1146         void __iomem *ioaddr = tp->mmio_addr;
1147         unsigned int i;
1148         static const struct {
1149                 u32 opt;
1150                 u16 reg;
1151                 u8  mask;
1152         } cfg[] = {
1153                 { WAKE_ANY,   Config1, PMEnable },
1154                 { WAKE_PHY,   Config3, LinkUp },
1155                 { WAKE_MAGIC, Config3, MagicPacket },
1156                 { WAKE_UCAST, Config5, UWF },
1157                 { WAKE_BCAST, Config5, BWF },
1158                 { WAKE_MCAST, Config5, MWF },
1159                 { WAKE_ANY,   Config5, LanWake }
1160         };
1161
1162         RTL_W8(Cfg9346, Cfg9346_Unlock);
1163
1164         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1165                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1166                 if (wolopts & cfg[i].opt)
1167                         options |= cfg[i].mask;
1168                 RTL_W8(cfg[i].reg, options);
1169         }
1170
1171         RTL_W8(Cfg9346, Cfg9346_Lock);
1172 }
1173
1174 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1175 {
1176         struct rtl8169_private *tp = netdev_priv(dev);
1177
1178         spin_lock_irq(&tp->lock);
1179
1180         if (wol->wolopts)
1181                 tp->features |= RTL_FEATURE_WOL;
1182         else
1183                 tp->features &= ~RTL_FEATURE_WOL;
1184         __rtl8169_set_wol(tp, wol->wolopts);
1185         spin_unlock_irq(&tp->lock);
1186
1187         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1188
1189         return 0;
1190 }
1191
1192 static void rtl8169_get_drvinfo(struct net_device *dev,
1193                                 struct ethtool_drvinfo *info)
1194 {
1195         struct rtl8169_private *tp = netdev_priv(dev);
1196
1197         strcpy(info->driver, MODULENAME);
1198         strcpy(info->version, RTL8169_VERSION);
1199         strcpy(info->bus_info, pci_name(tp->pci_dev));
1200 }
1201
1202 static int rtl8169_get_regs_len(struct net_device *dev)
1203 {
1204         return R8169_REGS_SIZE;
1205 }
1206
1207 static int rtl8169_set_speed_tbi(struct net_device *dev,
1208                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1209 {
1210         struct rtl8169_private *tp = netdev_priv(dev);
1211         void __iomem *ioaddr = tp->mmio_addr;
1212         int ret = 0;
1213         u32 reg;
1214
1215         reg = RTL_R32(TBICSR);
1216         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1217             (duplex == DUPLEX_FULL)) {
1218                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1219         } else if (autoneg == AUTONEG_ENABLE)
1220                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1221         else {
1222                 netif_warn(tp, link, dev,
1223                            "incorrect speed setting refused in TBI mode\n");
1224                 ret = -EOPNOTSUPP;
1225         }
1226
1227         return ret;
1228 }
1229
1230 static int rtl8169_set_speed_xmii(struct net_device *dev,
1231                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1232 {
1233         struct rtl8169_private *tp = netdev_priv(dev);
1234         int giga_ctrl, bmcr;
1235         int rc = -EINVAL;
1236
1237         rtl_writephy(tp, 0x1f, 0x0000);
1238
1239         if (autoneg == AUTONEG_ENABLE) {
1240                 int auto_nego;
1241
1242                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1243                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1244                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1245
1246                 if (adv & ADVERTISED_10baseT_Half)
1247                         auto_nego |= ADVERTISE_10HALF;
1248                 if (adv & ADVERTISED_10baseT_Full)
1249                         auto_nego |= ADVERTISE_10FULL;
1250                 if (adv & ADVERTISED_100baseT_Half)
1251                         auto_nego |= ADVERTISE_100HALF;
1252                 if (adv & ADVERTISED_100baseT_Full)
1253                         auto_nego |= ADVERTISE_100FULL;
1254
1255                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1256
1257                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1258                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1259
1260                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1261                 if (tp->mac_version != RTL_GIGA_MAC_VER_07 &&
1262                     tp->mac_version != RTL_GIGA_MAC_VER_08 &&
1263                     tp->mac_version != RTL_GIGA_MAC_VER_09 &&
1264                     tp->mac_version != RTL_GIGA_MAC_VER_10 &&
1265                     tp->mac_version != RTL_GIGA_MAC_VER_13 &&
1266                     tp->mac_version != RTL_GIGA_MAC_VER_14 &&
1267                     tp->mac_version != RTL_GIGA_MAC_VER_15 &&
1268                     tp->mac_version != RTL_GIGA_MAC_VER_16 &&
1269                     tp->mac_version != RTL_GIGA_MAC_VER_29 &&
1270                     tp->mac_version != RTL_GIGA_MAC_VER_30) {
1271                         if (adv & ADVERTISED_1000baseT_Half)
1272                                 giga_ctrl |= ADVERTISE_1000HALF;
1273                         if (adv & ADVERTISED_1000baseT_Full)
1274                                 giga_ctrl |= ADVERTISE_1000FULL;
1275                 } else if (adv & (ADVERTISED_1000baseT_Half |
1276                                   ADVERTISED_1000baseT_Full)) {
1277                         netif_info(tp, link, dev,
1278                                    "PHY does not support 1000Mbps\n");
1279                         goto out;
1280                 }
1281
1282                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1283
1284                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1285                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1286         } else {
1287                 giga_ctrl = 0;
1288
1289                 if (speed == SPEED_10)
1290                         bmcr = 0;
1291                 else if (speed == SPEED_100)
1292                         bmcr = BMCR_SPEED100;
1293                 else
1294                         goto out;
1295
1296                 if (duplex == DUPLEX_FULL)
1297                         bmcr |= BMCR_FULLDPLX;
1298         }
1299
1300         tp->phy_1000_ctrl_reg = giga_ctrl;
1301
1302         rtl_writephy(tp, MII_BMCR, bmcr);
1303
1304         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1305             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1306                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1307                         rtl_writephy(tp, 0x17, 0x2138);
1308                         rtl_writephy(tp, 0x0e, 0x0260);
1309                 } else {
1310                         rtl_writephy(tp, 0x17, 0x2108);
1311                         rtl_writephy(tp, 0x0e, 0x0000);
1312                 }
1313         }
1314
1315         rc = 0;
1316 out:
1317         return rc;
1318 }
1319
1320 static int rtl8169_set_speed(struct net_device *dev,
1321                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1322 {
1323         struct rtl8169_private *tp = netdev_priv(dev);
1324         int ret;
1325
1326         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1327
1328         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1329                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1330
1331         return ret;
1332 }
1333
1334 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1335 {
1336         struct rtl8169_private *tp = netdev_priv(dev);
1337         unsigned long flags;
1338         int ret;
1339
1340         spin_lock_irqsave(&tp->lock, flags);
1341         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1342                                 cmd->duplex, cmd->advertising);
1343         spin_unlock_irqrestore(&tp->lock, flags);
1344
1345         return ret;
1346 }
1347
1348 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1349 {
1350         if (dev->mtu > TD_MSS_MAX)
1351                 features &= ~NETIF_F_ALL_TSO;
1352
1353         return features;
1354 }
1355
1356 static int rtl8169_set_features(struct net_device *dev, u32 features)
1357 {
1358         struct rtl8169_private *tp = netdev_priv(dev);
1359         void __iomem *ioaddr = tp->mmio_addr;
1360         unsigned long flags;
1361
1362         spin_lock_irqsave(&tp->lock, flags);
1363
1364         if (features & NETIF_F_RXCSUM)
1365                 tp->cp_cmd |= RxChkSum;
1366         else
1367                 tp->cp_cmd &= ~RxChkSum;
1368
1369         if (dev->features & NETIF_F_HW_VLAN_RX)
1370                 tp->cp_cmd |= RxVlan;
1371         else
1372                 tp->cp_cmd &= ~RxVlan;
1373
1374         RTL_W16(CPlusCmd, tp->cp_cmd);
1375         RTL_R16(CPlusCmd);
1376
1377         spin_unlock_irqrestore(&tp->lock, flags);
1378
1379         return 0;
1380 }
1381
1382 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1383                                       struct sk_buff *skb)
1384 {
1385         return (vlan_tx_tag_present(skb)) ?
1386                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1387 }
1388
1389 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1390 {
1391         u32 opts2 = le32_to_cpu(desc->opts2);
1392
1393         if (opts2 & RxVlanTag)
1394                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1395
1396         desc->opts2 = 0;
1397 }
1398
1399 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1400 {
1401         struct rtl8169_private *tp = netdev_priv(dev);
1402         void __iomem *ioaddr = tp->mmio_addr;
1403         u32 status;
1404
1405         cmd->supported =
1406                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1407         cmd->port = PORT_FIBRE;
1408         cmd->transceiver = XCVR_INTERNAL;
1409
1410         status = RTL_R32(TBICSR);
1411         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1412         cmd->autoneg = !!(status & TBINwEnable);
1413
1414         ethtool_cmd_speed_set(cmd, SPEED_1000);
1415         cmd->duplex = DUPLEX_FULL; /* Always set */
1416
1417         return 0;
1418 }
1419
1420 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1421 {
1422         struct rtl8169_private *tp = netdev_priv(dev);
1423
1424         return mii_ethtool_gset(&tp->mii, cmd);
1425 }
1426
1427 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1428 {
1429         struct rtl8169_private *tp = netdev_priv(dev);
1430         unsigned long flags;
1431         int rc;
1432
1433         spin_lock_irqsave(&tp->lock, flags);
1434
1435         rc = tp->get_settings(dev, cmd);
1436
1437         spin_unlock_irqrestore(&tp->lock, flags);
1438         return rc;
1439 }
1440
1441 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1442                              void *p)
1443 {
1444         struct rtl8169_private *tp = netdev_priv(dev);
1445         unsigned long flags;
1446
1447         if (regs->len > R8169_REGS_SIZE)
1448                 regs->len = R8169_REGS_SIZE;
1449
1450         spin_lock_irqsave(&tp->lock, flags);
1451         memcpy_fromio(p, tp->mmio_addr, regs->len);
1452         spin_unlock_irqrestore(&tp->lock, flags);
1453 }
1454
1455 static u32 rtl8169_get_msglevel(struct net_device *dev)
1456 {
1457         struct rtl8169_private *tp = netdev_priv(dev);
1458
1459         return tp->msg_enable;
1460 }
1461
1462 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1463 {
1464         struct rtl8169_private *tp = netdev_priv(dev);
1465
1466         tp->msg_enable = value;
1467 }
1468
1469 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1470         "tx_packets",
1471         "rx_packets",
1472         "tx_errors",
1473         "rx_errors",
1474         "rx_missed",
1475         "align_errors",
1476         "tx_single_collisions",
1477         "tx_multi_collisions",
1478         "unicast",
1479         "broadcast",
1480         "multicast",
1481         "tx_aborted",
1482         "tx_underrun",
1483 };
1484
1485 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1486 {
1487         switch (sset) {
1488         case ETH_SS_STATS:
1489                 return ARRAY_SIZE(rtl8169_gstrings);
1490         default:
1491                 return -EOPNOTSUPP;
1492         }
1493 }
1494
1495 static void rtl8169_update_counters(struct net_device *dev)
1496 {
1497         struct rtl8169_private *tp = netdev_priv(dev);
1498         void __iomem *ioaddr = tp->mmio_addr;
1499         struct device *d = &tp->pci_dev->dev;
1500         struct rtl8169_counters *counters;
1501         dma_addr_t paddr;
1502         u32 cmd;
1503         int wait = 1000;
1504
1505         /*
1506          * Some chips are unable to dump tally counters when the receiver
1507          * is disabled.
1508          */
1509         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1510                 return;
1511
1512         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1513         if (!counters)
1514                 return;
1515
1516         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1517         cmd = (u64)paddr & DMA_BIT_MASK(32);
1518         RTL_W32(CounterAddrLow, cmd);
1519         RTL_W32(CounterAddrLow, cmd | CounterDump);
1520
1521         while (wait--) {
1522                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1523                         memcpy(&tp->counters, counters, sizeof(*counters));
1524                         break;
1525                 }
1526                 udelay(10);
1527         }
1528
1529         RTL_W32(CounterAddrLow, 0);
1530         RTL_W32(CounterAddrHigh, 0);
1531
1532         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1533 }
1534
1535 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1536                                       struct ethtool_stats *stats, u64 *data)
1537 {
1538         struct rtl8169_private *tp = netdev_priv(dev);
1539
1540         ASSERT_RTNL();
1541
1542         rtl8169_update_counters(dev);
1543
1544         data[0] = le64_to_cpu(tp->counters.tx_packets);
1545         data[1] = le64_to_cpu(tp->counters.rx_packets);
1546         data[2] = le64_to_cpu(tp->counters.tx_errors);
1547         data[3] = le32_to_cpu(tp->counters.rx_errors);
1548         data[4] = le16_to_cpu(tp->counters.rx_missed);
1549         data[5] = le16_to_cpu(tp->counters.align_errors);
1550         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1551         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1552         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1553         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1554         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1555         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1556         data[12] = le16_to_cpu(tp->counters.tx_underun);
1557 }
1558
1559 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1560 {
1561         switch(stringset) {
1562         case ETH_SS_STATS:
1563                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1564                 break;
1565         }
1566 }
1567
1568 static const struct ethtool_ops rtl8169_ethtool_ops = {
1569         .get_drvinfo            = rtl8169_get_drvinfo,
1570         .get_regs_len           = rtl8169_get_regs_len,
1571         .get_link               = ethtool_op_get_link,
1572         .get_settings           = rtl8169_get_settings,
1573         .set_settings           = rtl8169_set_settings,
1574         .get_msglevel           = rtl8169_get_msglevel,
1575         .set_msglevel           = rtl8169_set_msglevel,
1576         .get_regs               = rtl8169_get_regs,
1577         .get_wol                = rtl8169_get_wol,
1578         .set_wol                = rtl8169_set_wol,
1579         .get_strings            = rtl8169_get_strings,
1580         .get_sset_count         = rtl8169_get_sset_count,
1581         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1582 };
1583
1584 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1585                                     void __iomem *ioaddr)
1586 {
1587         /*
1588          * The driver currently handles the 8168Bf and the 8168Be identically
1589          * but they can be identified more specifically through the test below
1590          * if needed:
1591          *
1592          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1593          *
1594          * Same thing for the 8101Eb and the 8101Ec:
1595          *
1596          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1597          */
1598         static const struct {
1599                 u32 mask;
1600                 u32 val;
1601                 int mac_version;
1602         } mac_info[] = {
1603                 /* 8168E family. */
1604                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1605                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1606                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1607
1608                 /* 8168D family. */
1609                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1610                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1611                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1612
1613                 /* 8168DP family. */
1614                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1615                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1616                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1617
1618                 /* 8168C family. */
1619                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1620                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1621                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1622                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1623                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1624                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1625                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1626                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1627                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1628
1629                 /* 8168B family. */
1630                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1631                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1632                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1633                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1634
1635                 /* 8101 family. */
1636                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1637                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1638                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1639                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1640                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1641                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1642                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1643                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1644                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1645                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1646                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1647                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1648                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1649                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1650                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1651                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1652                 /* FIXME: where did these entries come from ? -- FR */
1653                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1654                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1655
1656                 /* 8110 family. */
1657                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1658                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1659                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1660                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1661                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1662                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1663
1664                 /* Catch-all */
1665                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1666         }, *p = mac_info;
1667         u32 reg;
1668
1669         reg = RTL_R32(TxConfig);
1670         while ((reg & p->mask) != p->val)
1671                 p++;
1672         tp->mac_version = p->mac_version;
1673 }
1674
1675 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1676 {
1677         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1678 }
1679
1680 struct phy_reg {
1681         u16 reg;
1682         u16 val;
1683 };
1684
1685 static void rtl_writephy_batch(struct rtl8169_private *tp,
1686                                const struct phy_reg *regs, int len)
1687 {
1688         while (len-- > 0) {
1689                 rtl_writephy(tp, regs->reg, regs->val);
1690                 regs++;
1691         }
1692 }
1693
1694 #define PHY_READ                0x00000000
1695 #define PHY_DATA_OR             0x10000000
1696 #define PHY_DATA_AND            0x20000000
1697 #define PHY_BJMPN               0x30000000
1698 #define PHY_READ_EFUSE          0x40000000
1699 #define PHY_READ_MAC_BYTE       0x50000000
1700 #define PHY_WRITE_MAC_BYTE      0x60000000
1701 #define PHY_CLEAR_READCOUNT     0x70000000
1702 #define PHY_WRITE               0x80000000
1703 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1704 #define PHY_COMP_EQ_SKIPN       0xa0000000
1705 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1706 #define PHY_WRITE_PREVIOUS      0xc0000000
1707 #define PHY_SKIPN               0xd0000000
1708 #define PHY_DELAY_MS            0xe0000000
1709 #define PHY_WRITE_ERI_WORD      0xf0000000
1710
1711 static void
1712 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1713 {
1714         __le32 *phytable = (__le32 *)fw->data;
1715         struct net_device *dev = tp->dev;
1716         size_t index, fw_size = fw->size / sizeof(*phytable);
1717         u32 predata, count;
1718
1719         if (fw->size % sizeof(*phytable)) {
1720                 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1721                 return;
1722         }
1723
1724         for (index = 0; index < fw_size; index++) {
1725                 u32 action = le32_to_cpu(phytable[index]);
1726                 u32 regno = (action & 0x0fff0000) >> 16;
1727
1728                 switch(action & 0xf0000000) {
1729                 case PHY_READ:
1730                 case PHY_DATA_OR:
1731                 case PHY_DATA_AND:
1732                 case PHY_READ_EFUSE:
1733                 case PHY_CLEAR_READCOUNT:
1734                 case PHY_WRITE:
1735                 case PHY_WRITE_PREVIOUS:
1736                 case PHY_DELAY_MS:
1737                         break;
1738
1739                 case PHY_BJMPN:
1740                         if (regno > index) {
1741                                 netif_err(tp, probe, tp->dev,
1742                                           "Out of range of firmware\n");
1743                                 return;
1744                         }
1745                         break;
1746                 case PHY_READCOUNT_EQ_SKIP:
1747                         if (index + 2 >= fw_size) {
1748                                 netif_err(tp, probe, tp->dev,
1749                                           "Out of range of firmware\n");
1750                                 return;
1751                         }
1752                         break;
1753                 case PHY_COMP_EQ_SKIPN:
1754                 case PHY_COMP_NEQ_SKIPN:
1755                 case PHY_SKIPN:
1756                         if (index + 1 + regno >= fw_size) {
1757                                 netif_err(tp, probe, tp->dev,
1758                                           "Out of range of firmware\n");
1759                                 return;
1760                         }
1761                         break;
1762
1763                 case PHY_READ_MAC_BYTE:
1764                 case PHY_WRITE_MAC_BYTE:
1765                 case PHY_WRITE_ERI_WORD:
1766                 default:
1767                         netif_err(tp, probe, tp->dev,
1768                                   "Invalid action 0x%08x\n", action);
1769                         return;
1770                 }
1771         }
1772
1773         predata = 0;
1774         count = 0;
1775
1776         for (index = 0; index < fw_size; ) {
1777                 u32 action = le32_to_cpu(phytable[index]);
1778                 u32 data = action & 0x0000ffff;
1779                 u32 regno = (action & 0x0fff0000) >> 16;
1780
1781                 if (!action)
1782                         break;
1783
1784                 switch(action & 0xf0000000) {
1785                 case PHY_READ:
1786                         predata = rtl_readphy(tp, regno);
1787                         count++;
1788                         index++;
1789                         break;
1790                 case PHY_DATA_OR:
1791                         predata |= data;
1792                         index++;
1793                         break;
1794                 case PHY_DATA_AND:
1795                         predata &= data;
1796                         index++;
1797                         break;
1798                 case PHY_BJMPN:
1799                         index -= regno;
1800                         break;
1801                 case PHY_READ_EFUSE:
1802                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1803                         index++;
1804                         break;
1805                 case PHY_CLEAR_READCOUNT:
1806                         count = 0;
1807                         index++;
1808                         break;
1809                 case PHY_WRITE:
1810                         rtl_writephy(tp, regno, data);
1811                         index++;
1812                         break;
1813                 case PHY_READCOUNT_EQ_SKIP:
1814                         index += (count == data) ? 2 : 1;
1815                         break;
1816                 case PHY_COMP_EQ_SKIPN:
1817                         if (predata == data)
1818                                 index += regno;
1819                         index++;
1820                         break;
1821                 case PHY_COMP_NEQ_SKIPN:
1822                         if (predata != data)
1823                                 index += regno;
1824                         index++;
1825                         break;
1826                 case PHY_WRITE_PREVIOUS:
1827                         rtl_writephy(tp, regno, predata);
1828                         index++;
1829                         break;
1830                 case PHY_SKIPN:
1831                         index += regno + 1;
1832                         break;
1833                 case PHY_DELAY_MS:
1834                         mdelay(data);
1835                         index++;
1836                         break;
1837
1838                 case PHY_READ_MAC_BYTE:
1839                 case PHY_WRITE_MAC_BYTE:
1840                 case PHY_WRITE_ERI_WORD:
1841                 default:
1842                         BUG();
1843                 }
1844         }
1845 }
1846
1847 static void rtl_release_firmware(struct rtl8169_private *tp)
1848 {
1849         if (!IS_ERR_OR_NULL(tp->fw))
1850                 release_firmware(tp->fw);
1851         tp->fw = RTL_FIRMWARE_UNKNOWN;
1852 }
1853
1854 static void rtl_apply_firmware(struct rtl8169_private *tp)
1855 {
1856         const struct firmware *fw = tp->fw;
1857
1858         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1859         if (!IS_ERR_OR_NULL(fw))
1860                 rtl_phy_write_fw(tp, fw);
1861 }
1862
1863 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1864 {
1865         if (rtl_readphy(tp, reg) != val)
1866                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1867         else
1868                 rtl_apply_firmware(tp);
1869 }
1870
1871 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1872 {
1873         static const struct phy_reg phy_reg_init[] = {
1874                 { 0x1f, 0x0001 },
1875                 { 0x06, 0x006e },
1876                 { 0x08, 0x0708 },
1877                 { 0x15, 0x4000 },
1878                 { 0x18, 0x65c7 },
1879
1880                 { 0x1f, 0x0001 },
1881                 { 0x03, 0x00a1 },
1882                 { 0x02, 0x0008 },
1883                 { 0x01, 0x0120 },
1884                 { 0x00, 0x1000 },
1885                 { 0x04, 0x0800 },
1886                 { 0x04, 0x0000 },
1887
1888                 { 0x03, 0xff41 },
1889                 { 0x02, 0xdf60 },
1890                 { 0x01, 0x0140 },
1891                 { 0x00, 0x0077 },
1892                 { 0x04, 0x7800 },
1893                 { 0x04, 0x7000 },
1894
1895                 { 0x03, 0x802f },
1896                 { 0x02, 0x4f02 },
1897                 { 0x01, 0x0409 },
1898                 { 0x00, 0xf0f9 },
1899                 { 0x04, 0x9800 },
1900                 { 0x04, 0x9000 },
1901
1902                 { 0x03, 0xdf01 },
1903                 { 0x02, 0xdf20 },
1904                 { 0x01, 0xff95 },
1905                 { 0x00, 0xba00 },
1906                 { 0x04, 0xa800 },
1907                 { 0x04, 0xa000 },
1908
1909                 { 0x03, 0xff41 },
1910                 { 0x02, 0xdf20 },
1911                 { 0x01, 0x0140 },
1912                 { 0x00, 0x00bb },
1913                 { 0x04, 0xb800 },
1914                 { 0x04, 0xb000 },
1915
1916                 { 0x03, 0xdf41 },
1917                 { 0x02, 0xdc60 },
1918                 { 0x01, 0x6340 },
1919                 { 0x00, 0x007d },
1920                 { 0x04, 0xd800 },
1921                 { 0x04, 0xd000 },
1922
1923                 { 0x03, 0xdf01 },
1924                 { 0x02, 0xdf20 },
1925                 { 0x01, 0x100a },
1926                 { 0x00, 0xa0ff },
1927                 { 0x04, 0xf800 },
1928                 { 0x04, 0xf000 },
1929
1930                 { 0x1f, 0x0000 },
1931                 { 0x0b, 0x0000 },
1932                 { 0x00, 0x9200 }
1933         };
1934
1935         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1936 }
1937
1938 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1939 {
1940         static const struct phy_reg phy_reg_init[] = {
1941                 { 0x1f, 0x0002 },
1942                 { 0x01, 0x90d0 },
1943                 { 0x1f, 0x0000 }
1944         };
1945
1946         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1947 }
1948
1949 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1950 {
1951         struct pci_dev *pdev = tp->pci_dev;
1952         u16 vendor_id, device_id;
1953
1954         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1955         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1956
1957         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1958                 return;
1959
1960         rtl_writephy(tp, 0x1f, 0x0001);
1961         rtl_writephy(tp, 0x10, 0xf01b);
1962         rtl_writephy(tp, 0x1f, 0x0000);
1963 }
1964
1965 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
1966 {
1967         static const struct phy_reg phy_reg_init[] = {
1968                 { 0x1f, 0x0001 },
1969                 { 0x04, 0x0000 },
1970                 { 0x03, 0x00a1 },
1971                 { 0x02, 0x0008 },
1972                 { 0x01, 0x0120 },
1973                 { 0x00, 0x1000 },
1974                 { 0x04, 0x0800 },
1975                 { 0x04, 0x9000 },
1976                 { 0x03, 0x802f },
1977                 { 0x02, 0x4f02 },
1978                 { 0x01, 0x0409 },
1979                 { 0x00, 0xf099 },
1980                 { 0x04, 0x9800 },
1981                 { 0x04, 0xa000 },
1982                 { 0x03, 0xdf01 },
1983                 { 0x02, 0xdf20 },
1984                 { 0x01, 0xff95 },
1985                 { 0x00, 0xba00 },
1986                 { 0x04, 0xa800 },
1987                 { 0x04, 0xf000 },
1988                 { 0x03, 0xdf01 },
1989                 { 0x02, 0xdf20 },
1990                 { 0x01, 0x101a },
1991                 { 0x00, 0xa0ff },
1992                 { 0x04, 0xf800 },
1993                 { 0x04, 0x0000 },
1994                 { 0x1f, 0x0000 },
1995
1996                 { 0x1f, 0x0001 },
1997                 { 0x10, 0xf41b },
1998                 { 0x14, 0xfb54 },
1999                 { 0x18, 0xf5c7 },
2000                 { 0x1f, 0x0000 },
2001
2002                 { 0x1f, 0x0001 },
2003                 { 0x17, 0x0cc0 },
2004                 { 0x1f, 0x0000 }
2005         };
2006
2007         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2008
2009         rtl8169scd_hw_phy_config_quirk(tp);
2010 }
2011
2012 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2013 {
2014         static const struct phy_reg phy_reg_init[] = {
2015                 { 0x1f, 0x0001 },
2016                 { 0x04, 0x0000 },
2017                 { 0x03, 0x00a1 },
2018                 { 0x02, 0x0008 },
2019                 { 0x01, 0x0120 },
2020                 { 0x00, 0x1000 },
2021                 { 0x04, 0x0800 },
2022                 { 0x04, 0x9000 },
2023                 { 0x03, 0x802f },
2024                 { 0x02, 0x4f02 },
2025                 { 0x01, 0x0409 },
2026                 { 0x00, 0xf099 },
2027                 { 0x04, 0x9800 },
2028                 { 0x04, 0xa000 },
2029                 { 0x03, 0xdf01 },
2030                 { 0x02, 0xdf20 },
2031                 { 0x01, 0xff95 },
2032                 { 0x00, 0xba00 },
2033                 { 0x04, 0xa800 },
2034                 { 0x04, 0xf000 },
2035                 { 0x03, 0xdf01 },
2036                 { 0x02, 0xdf20 },
2037                 { 0x01, 0x101a },
2038                 { 0x00, 0xa0ff },
2039                 { 0x04, 0xf800 },
2040                 { 0x04, 0x0000 },
2041                 { 0x1f, 0x0000 },
2042
2043                 { 0x1f, 0x0001 },
2044                 { 0x0b, 0x8480 },
2045                 { 0x1f, 0x0000 },
2046
2047                 { 0x1f, 0x0001 },
2048                 { 0x18, 0x67c7 },
2049                 { 0x04, 0x2000 },
2050                 { 0x03, 0x002f },
2051                 { 0x02, 0x4360 },
2052                 { 0x01, 0x0109 },
2053                 { 0x00, 0x3022 },
2054                 { 0x04, 0x2800 },
2055                 { 0x1f, 0x0000 },
2056
2057                 { 0x1f, 0x0001 },
2058                 { 0x17, 0x0cc0 },
2059                 { 0x1f, 0x0000 }
2060         };
2061
2062         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2063 }
2064
2065 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2066 {
2067         static const struct phy_reg phy_reg_init[] = {
2068                 { 0x10, 0xf41b },
2069                 { 0x1f, 0x0000 }
2070         };
2071
2072         rtl_writephy(tp, 0x1f, 0x0001);
2073         rtl_patchphy(tp, 0x16, 1 << 0);
2074
2075         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2076 }
2077
2078 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2079 {
2080         static const struct phy_reg phy_reg_init[] = {
2081                 { 0x1f, 0x0001 },
2082                 { 0x10, 0xf41b },
2083                 { 0x1f, 0x0000 }
2084         };
2085
2086         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2087 }
2088
2089 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2090 {
2091         static const struct phy_reg phy_reg_init[] = {
2092                 { 0x1f, 0x0000 },
2093                 { 0x1d, 0x0f00 },
2094                 { 0x1f, 0x0002 },
2095                 { 0x0c, 0x1ec8 },
2096                 { 0x1f, 0x0000 }
2097         };
2098
2099         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2100 }
2101
2102 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2103 {
2104         static const struct phy_reg phy_reg_init[] = {
2105                 { 0x1f, 0x0001 },
2106                 { 0x1d, 0x3d98 },
2107                 { 0x1f, 0x0000 }
2108         };
2109
2110         rtl_writephy(tp, 0x1f, 0x0000);
2111         rtl_patchphy(tp, 0x14, 1 << 5);
2112         rtl_patchphy(tp, 0x0d, 1 << 5);
2113
2114         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2115 }
2116
2117 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2118 {
2119         static const struct phy_reg phy_reg_init[] = {
2120                 { 0x1f, 0x0001 },
2121                 { 0x12, 0x2300 },
2122                 { 0x1f, 0x0002 },
2123                 { 0x00, 0x88d4 },
2124                 { 0x01, 0x82b1 },
2125                 { 0x03, 0x7002 },
2126                 { 0x08, 0x9e30 },
2127                 { 0x09, 0x01f0 },
2128                 { 0x0a, 0x5500 },
2129                 { 0x0c, 0x00c8 },
2130                 { 0x1f, 0x0003 },
2131                 { 0x12, 0xc096 },
2132                 { 0x16, 0x000a },
2133                 { 0x1f, 0x0000 },
2134                 { 0x1f, 0x0000 },
2135                 { 0x09, 0x2000 },
2136                 { 0x09, 0x0000 }
2137         };
2138
2139         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2140
2141         rtl_patchphy(tp, 0x14, 1 << 5);
2142         rtl_patchphy(tp, 0x0d, 1 << 5);
2143         rtl_writephy(tp, 0x1f, 0x0000);
2144 }
2145
2146 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2147 {
2148         static const struct phy_reg phy_reg_init[] = {
2149                 { 0x1f, 0x0001 },
2150                 { 0x12, 0x2300 },
2151                 { 0x03, 0x802f },
2152                 { 0x02, 0x4f02 },
2153                 { 0x01, 0x0409 },
2154                 { 0x00, 0xf099 },
2155                 { 0x04, 0x9800 },
2156                 { 0x04, 0x9000 },
2157                 { 0x1d, 0x3d98 },
2158                 { 0x1f, 0x0002 },
2159                 { 0x0c, 0x7eb8 },
2160                 { 0x06, 0x0761 },
2161                 { 0x1f, 0x0003 },
2162                 { 0x16, 0x0f0a },
2163                 { 0x1f, 0x0000 }
2164         };
2165
2166         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2167
2168         rtl_patchphy(tp, 0x16, 1 << 0);
2169         rtl_patchphy(tp, 0x14, 1 << 5);
2170         rtl_patchphy(tp, 0x0d, 1 << 5);
2171         rtl_writephy(tp, 0x1f, 0x0000);
2172 }
2173
2174 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2175 {
2176         static const struct phy_reg phy_reg_init[] = {
2177                 { 0x1f, 0x0001 },
2178                 { 0x12, 0x2300 },
2179                 { 0x1d, 0x3d98 },
2180                 { 0x1f, 0x0002 },
2181                 { 0x0c, 0x7eb8 },
2182                 { 0x06, 0x5461 },
2183                 { 0x1f, 0x0003 },
2184                 { 0x16, 0x0f0a },
2185                 { 0x1f, 0x0000 }
2186         };
2187
2188         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2189
2190         rtl_patchphy(tp, 0x16, 1 << 0);
2191         rtl_patchphy(tp, 0x14, 1 << 5);
2192         rtl_patchphy(tp, 0x0d, 1 << 5);
2193         rtl_writephy(tp, 0x1f, 0x0000);
2194 }
2195
2196 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2197 {
2198         rtl8168c_3_hw_phy_config(tp);
2199 }
2200
2201 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2202 {
2203         static const struct phy_reg phy_reg_init_0[] = {
2204                 /* Channel Estimation */
2205                 { 0x1f, 0x0001 },
2206                 { 0x06, 0x4064 },
2207                 { 0x07, 0x2863 },
2208                 { 0x08, 0x059c },
2209                 { 0x09, 0x26b4 },
2210                 { 0x0a, 0x6a19 },
2211                 { 0x0b, 0xdcc8 },
2212                 { 0x10, 0xf06d },
2213                 { 0x14, 0x7f68 },
2214                 { 0x18, 0x7fd9 },
2215                 { 0x1c, 0xf0ff },
2216                 { 0x1d, 0x3d9c },
2217                 { 0x1f, 0x0003 },
2218                 { 0x12, 0xf49f },
2219                 { 0x13, 0x070b },
2220                 { 0x1a, 0x05ad },
2221                 { 0x14, 0x94c0 },
2222
2223                 /*
2224                  * Tx Error Issue
2225                  * Enhance line driver power
2226                  */
2227                 { 0x1f, 0x0002 },
2228                 { 0x06, 0x5561 },
2229                 { 0x1f, 0x0005 },
2230                 { 0x05, 0x8332 },
2231                 { 0x06, 0x5561 },
2232
2233                 /*
2234                  * Can not link to 1Gbps with bad cable
2235                  * Decrease SNR threshold form 21.07dB to 19.04dB
2236                  */
2237                 { 0x1f, 0x0001 },
2238                 { 0x17, 0x0cc0 },
2239
2240                 { 0x1f, 0x0000 },
2241                 { 0x0d, 0xf880 }
2242         };
2243         void __iomem *ioaddr = tp->mmio_addr;
2244
2245         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2246
2247         /*
2248          * Rx Error Issue
2249          * Fine Tune Switching regulator parameter
2250          */
2251         rtl_writephy(tp, 0x1f, 0x0002);
2252         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2253         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2254
2255         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2256                 static const struct phy_reg phy_reg_init[] = {
2257                         { 0x1f, 0x0002 },
2258                         { 0x05, 0x669a },
2259                         { 0x1f, 0x0005 },
2260                         { 0x05, 0x8330 },
2261                         { 0x06, 0x669a },
2262                         { 0x1f, 0x0002 }
2263                 };
2264                 int val;
2265
2266                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2267
2268                 val = rtl_readphy(tp, 0x0d);
2269
2270                 if ((val & 0x00ff) != 0x006c) {
2271                         static const u32 set[] = {
2272                                 0x0065, 0x0066, 0x0067, 0x0068,
2273                                 0x0069, 0x006a, 0x006b, 0x006c
2274                         };
2275                         int i;
2276
2277                         rtl_writephy(tp, 0x1f, 0x0002);
2278
2279                         val &= 0xff00;
2280                         for (i = 0; i < ARRAY_SIZE(set); i++)
2281                                 rtl_writephy(tp, 0x0d, val | set[i]);
2282                 }
2283         } else {
2284                 static const struct phy_reg phy_reg_init[] = {
2285                         { 0x1f, 0x0002 },
2286                         { 0x05, 0x6662 },
2287                         { 0x1f, 0x0005 },
2288                         { 0x05, 0x8330 },
2289                         { 0x06, 0x6662 }
2290                 };
2291
2292                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2293         }
2294
2295         /* RSET couple improve */
2296         rtl_writephy(tp, 0x1f, 0x0002);
2297         rtl_patchphy(tp, 0x0d, 0x0300);
2298         rtl_patchphy(tp, 0x0f, 0x0010);
2299
2300         /* Fine tune PLL performance */
2301         rtl_writephy(tp, 0x1f, 0x0002);
2302         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2303         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2304
2305         rtl_writephy(tp, 0x1f, 0x0005);
2306         rtl_writephy(tp, 0x05, 0x001b);
2307
2308         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2309
2310         rtl_writephy(tp, 0x1f, 0x0000);
2311 }
2312
2313 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2314 {
2315         static const struct phy_reg phy_reg_init_0[] = {
2316                 /* Channel Estimation */
2317                 { 0x1f, 0x0001 },
2318                 { 0x06, 0x4064 },
2319                 { 0x07, 0x2863 },
2320                 { 0x08, 0x059c },
2321                 { 0x09, 0x26b4 },
2322                 { 0x0a, 0x6a19 },
2323                 { 0x0b, 0xdcc8 },
2324                 { 0x10, 0xf06d },
2325                 { 0x14, 0x7f68 },
2326                 { 0x18, 0x7fd9 },
2327                 { 0x1c, 0xf0ff },
2328                 { 0x1d, 0x3d9c },
2329                 { 0x1f, 0x0003 },
2330                 { 0x12, 0xf49f },
2331                 { 0x13, 0x070b },
2332                 { 0x1a, 0x05ad },
2333                 { 0x14, 0x94c0 },
2334
2335                 /*
2336                  * Tx Error Issue
2337                  * Enhance line driver power
2338                  */
2339                 { 0x1f, 0x0002 },
2340                 { 0x06, 0x5561 },
2341                 { 0x1f, 0x0005 },
2342                 { 0x05, 0x8332 },
2343                 { 0x06, 0x5561 },
2344
2345                 /*
2346                  * Can not link to 1Gbps with bad cable
2347                  * Decrease SNR threshold form 21.07dB to 19.04dB
2348                  */
2349                 { 0x1f, 0x0001 },
2350                 { 0x17, 0x0cc0 },
2351
2352                 { 0x1f, 0x0000 },
2353                 { 0x0d, 0xf880 }
2354         };
2355         void __iomem *ioaddr = tp->mmio_addr;
2356
2357         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2358
2359         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2360                 static const struct phy_reg phy_reg_init[] = {
2361                         { 0x1f, 0x0002 },
2362                         { 0x05, 0x669a },
2363                         { 0x1f, 0x0005 },
2364                         { 0x05, 0x8330 },
2365                         { 0x06, 0x669a },
2366
2367                         { 0x1f, 0x0002 }
2368                 };
2369                 int val;
2370
2371                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2372
2373                 val = rtl_readphy(tp, 0x0d);
2374                 if ((val & 0x00ff) != 0x006c) {
2375                         static const u32 set[] = {
2376                                 0x0065, 0x0066, 0x0067, 0x0068,
2377                                 0x0069, 0x006a, 0x006b, 0x006c
2378                         };
2379                         int i;
2380
2381                         rtl_writephy(tp, 0x1f, 0x0002);
2382
2383                         val &= 0xff00;
2384                         for (i = 0; i < ARRAY_SIZE(set); i++)
2385                                 rtl_writephy(tp, 0x0d, val | set[i]);
2386                 }
2387         } else {
2388                 static const struct phy_reg phy_reg_init[] = {
2389                         { 0x1f, 0x0002 },
2390                         { 0x05, 0x2642 },
2391                         { 0x1f, 0x0005 },
2392                         { 0x05, 0x8330 },
2393                         { 0x06, 0x2642 }
2394                 };
2395
2396                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2397         }
2398
2399         /* Fine tune PLL performance */
2400         rtl_writephy(tp, 0x1f, 0x0002);
2401         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2402         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2403
2404         /* Switching regulator Slew rate */
2405         rtl_writephy(tp, 0x1f, 0x0002);
2406         rtl_patchphy(tp, 0x0f, 0x0017);
2407
2408         rtl_writephy(tp, 0x1f, 0x0005);
2409         rtl_writephy(tp, 0x05, 0x001b);
2410
2411         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2412
2413         rtl_writephy(tp, 0x1f, 0x0000);
2414 }
2415
2416 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2417 {
2418         static const struct phy_reg phy_reg_init[] = {
2419                 { 0x1f, 0x0002 },
2420                 { 0x10, 0x0008 },
2421                 { 0x0d, 0x006c },
2422
2423                 { 0x1f, 0x0000 },
2424                 { 0x0d, 0xf880 },
2425
2426                 { 0x1f, 0x0001 },
2427                 { 0x17, 0x0cc0 },
2428
2429                 { 0x1f, 0x0001 },
2430                 { 0x0b, 0xa4d8 },
2431                 { 0x09, 0x281c },
2432                 { 0x07, 0x2883 },
2433                 { 0x0a, 0x6b35 },
2434                 { 0x1d, 0x3da4 },
2435                 { 0x1c, 0xeffd },
2436                 { 0x14, 0x7f52 },
2437                 { 0x18, 0x7fc6 },
2438                 { 0x08, 0x0601 },
2439                 { 0x06, 0x4063 },
2440                 { 0x10, 0xf074 },
2441                 { 0x1f, 0x0003 },
2442                 { 0x13, 0x0789 },
2443                 { 0x12, 0xf4bd },
2444                 { 0x1a, 0x04fd },
2445                 { 0x14, 0x84b0 },
2446                 { 0x1f, 0x0000 },
2447                 { 0x00, 0x9200 },
2448
2449                 { 0x1f, 0x0005 },
2450                 { 0x01, 0x0340 },
2451                 { 0x1f, 0x0001 },
2452                 { 0x04, 0x4000 },
2453                 { 0x03, 0x1d21 },
2454                 { 0x02, 0x0c32 },
2455                 { 0x01, 0x0200 },
2456                 { 0x00, 0x5554 },
2457                 { 0x04, 0x4800 },
2458                 { 0x04, 0x4000 },
2459                 { 0x04, 0xf000 },
2460                 { 0x03, 0xdf01 },
2461                 { 0x02, 0xdf20 },
2462                 { 0x01, 0x101a },
2463                 { 0x00, 0xa0ff },
2464                 { 0x04, 0xf800 },
2465                 { 0x04, 0xf000 },
2466                 { 0x1f, 0x0000 },
2467
2468                 { 0x1f, 0x0007 },
2469                 { 0x1e, 0x0023 },
2470                 { 0x16, 0x0000 },
2471                 { 0x1f, 0x0000 }
2472         };
2473
2474         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2475 }
2476
2477 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2478 {
2479         static const struct phy_reg phy_reg_init[] = {
2480                 { 0x1f, 0x0001 },
2481                 { 0x17, 0x0cc0 },
2482
2483                 { 0x1f, 0x0007 },
2484                 { 0x1e, 0x002d },
2485                 { 0x18, 0x0040 },
2486                 { 0x1f, 0x0000 }
2487         };
2488
2489         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2490         rtl_patchphy(tp, 0x0d, 1 << 5);
2491 }
2492
2493 static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2494 {
2495         static const struct phy_reg phy_reg_init[] = {
2496                 /* Enable Delay cap */
2497                 { 0x1f, 0x0005 },
2498                 { 0x05, 0x8b80 },
2499                 { 0x06, 0xc896 },
2500                 { 0x1f, 0x0000 },
2501
2502                 /* Channel estimation fine tune */
2503                 { 0x1f, 0x0001 },
2504                 { 0x0b, 0x6c20 },
2505                 { 0x07, 0x2872 },
2506                 { 0x1c, 0xefff },
2507                 { 0x1f, 0x0003 },
2508                 { 0x14, 0x6420 },
2509                 { 0x1f, 0x0000 },
2510
2511                 /* Update PFM & 10M TX idle timer */
2512                 { 0x1f, 0x0007 },
2513                 { 0x1e, 0x002f },
2514                 { 0x15, 0x1919 },
2515                 { 0x1f, 0x0000 },
2516
2517                 { 0x1f, 0x0007 },
2518                 { 0x1e, 0x00ac },
2519                 { 0x18, 0x0006 },
2520                 { 0x1f, 0x0000 }
2521         };
2522
2523         rtl_apply_firmware(tp);
2524
2525         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2526
2527         /* DCO enable for 10M IDLE Power */
2528         rtl_writephy(tp, 0x1f, 0x0007);
2529         rtl_writephy(tp, 0x1e, 0x0023);
2530         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2531         rtl_writephy(tp, 0x1f, 0x0000);
2532
2533         /* For impedance matching */
2534         rtl_writephy(tp, 0x1f, 0x0002);
2535         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2536         rtl_writephy(tp, 0x1f, 0x0000);
2537
2538         /* PHY auto speed down */
2539         rtl_writephy(tp, 0x1f, 0x0007);
2540         rtl_writephy(tp, 0x1e, 0x002d);
2541         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2542         rtl_writephy(tp, 0x1f, 0x0000);
2543         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2544
2545         rtl_writephy(tp, 0x1f, 0x0005);
2546         rtl_writephy(tp, 0x05, 0x8b86);
2547         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2548         rtl_writephy(tp, 0x1f, 0x0000);
2549
2550         rtl_writephy(tp, 0x1f, 0x0005);
2551         rtl_writephy(tp, 0x05, 0x8b85);
2552         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2553         rtl_writephy(tp, 0x1f, 0x0007);
2554         rtl_writephy(tp, 0x1e, 0x0020);
2555         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2556         rtl_writephy(tp, 0x1f, 0x0006);
2557         rtl_writephy(tp, 0x00, 0x5a00);
2558         rtl_writephy(tp, 0x1f, 0x0000);
2559         rtl_writephy(tp, 0x0d, 0x0007);
2560         rtl_writephy(tp, 0x0e, 0x003c);
2561         rtl_writephy(tp, 0x0d, 0x4007);
2562         rtl_writephy(tp, 0x0e, 0x0000);
2563         rtl_writephy(tp, 0x0d, 0x0000);
2564 }
2565
2566 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2567 {
2568         static const struct phy_reg phy_reg_init[] = {
2569                 { 0x1f, 0x0003 },
2570                 { 0x08, 0x441d },
2571                 { 0x01, 0x9100 },
2572                 { 0x1f, 0x0000 }
2573         };
2574
2575         rtl_writephy(tp, 0x1f, 0x0000);
2576         rtl_patchphy(tp, 0x11, 1 << 12);
2577         rtl_patchphy(tp, 0x19, 1 << 13);
2578         rtl_patchphy(tp, 0x10, 1 << 15);
2579
2580         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2581 }
2582
2583 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2584 {
2585         static const struct phy_reg phy_reg_init[] = {
2586                 { 0x1f, 0x0005 },
2587                 { 0x1a, 0x0000 },
2588                 { 0x1f, 0x0000 },
2589
2590                 { 0x1f, 0x0004 },
2591                 { 0x1c, 0x0000 },
2592                 { 0x1f, 0x0000 },
2593
2594                 { 0x1f, 0x0001 },
2595                 { 0x15, 0x7701 },
2596                 { 0x1f, 0x0000 }
2597         };
2598
2599         /* Disable ALDPS before ram code */
2600         rtl_writephy(tp, 0x1f, 0x0000);
2601         rtl_writephy(tp, 0x18, 0x0310);
2602         msleep(100);
2603
2604         rtl_apply_firmware(tp);
2605
2606         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2607 }
2608
2609 static void rtl_hw_phy_config(struct net_device *dev)
2610 {
2611         struct rtl8169_private *tp = netdev_priv(dev);
2612
2613         rtl8169_print_mac_version(tp);
2614
2615         switch (tp->mac_version) {
2616         case RTL_GIGA_MAC_VER_01:
2617                 break;
2618         case RTL_GIGA_MAC_VER_02:
2619         case RTL_GIGA_MAC_VER_03:
2620                 rtl8169s_hw_phy_config(tp);
2621                 break;
2622         case RTL_GIGA_MAC_VER_04:
2623                 rtl8169sb_hw_phy_config(tp);
2624                 break;
2625         case RTL_GIGA_MAC_VER_05:
2626                 rtl8169scd_hw_phy_config(tp);
2627                 break;
2628         case RTL_GIGA_MAC_VER_06:
2629                 rtl8169sce_hw_phy_config(tp);
2630                 break;
2631         case RTL_GIGA_MAC_VER_07:
2632         case RTL_GIGA_MAC_VER_08:
2633         case RTL_GIGA_MAC_VER_09:
2634                 rtl8102e_hw_phy_config(tp);
2635                 break;
2636         case RTL_GIGA_MAC_VER_11:
2637                 rtl8168bb_hw_phy_config(tp);
2638                 break;
2639         case RTL_GIGA_MAC_VER_12:
2640                 rtl8168bef_hw_phy_config(tp);
2641                 break;
2642         case RTL_GIGA_MAC_VER_17:
2643                 rtl8168bef_hw_phy_config(tp);
2644                 break;
2645         case RTL_GIGA_MAC_VER_18:
2646                 rtl8168cp_1_hw_phy_config(tp);
2647                 break;
2648         case RTL_GIGA_MAC_VER_19:
2649                 rtl8168c_1_hw_phy_config(tp);
2650                 break;
2651         case RTL_GIGA_MAC_VER_20:
2652                 rtl8168c_2_hw_phy_config(tp);
2653                 break;
2654         case RTL_GIGA_MAC_VER_21:
2655                 rtl8168c_3_hw_phy_config(tp);
2656                 break;
2657         case RTL_GIGA_MAC_VER_22:
2658                 rtl8168c_4_hw_phy_config(tp);
2659                 break;
2660         case RTL_GIGA_MAC_VER_23:
2661         case RTL_GIGA_MAC_VER_24:
2662                 rtl8168cp_2_hw_phy_config(tp);
2663                 break;
2664         case RTL_GIGA_MAC_VER_25:
2665                 rtl8168d_1_hw_phy_config(tp);
2666                 break;
2667         case RTL_GIGA_MAC_VER_26:
2668                 rtl8168d_2_hw_phy_config(tp);
2669                 break;
2670         case RTL_GIGA_MAC_VER_27:
2671                 rtl8168d_3_hw_phy_config(tp);
2672                 break;
2673         case RTL_GIGA_MAC_VER_28:
2674                 rtl8168d_4_hw_phy_config(tp);
2675                 break;
2676         case RTL_GIGA_MAC_VER_29:
2677         case RTL_GIGA_MAC_VER_30:
2678                 rtl8105e_hw_phy_config(tp);
2679                 break;
2680         case RTL_GIGA_MAC_VER_31:
2681                 /* None. */
2682                 break;
2683         case RTL_GIGA_MAC_VER_32:
2684         case RTL_GIGA_MAC_VER_33:
2685                 rtl8168e_hw_phy_config(tp);
2686                 break;
2687
2688         default:
2689                 break;
2690         }
2691 }
2692
2693 static void rtl8169_phy_timer(unsigned long __opaque)
2694 {
2695         struct net_device *dev = (struct net_device *)__opaque;
2696         struct rtl8169_private *tp = netdev_priv(dev);
2697         struct timer_list *timer = &tp->timer;
2698         void __iomem *ioaddr = tp->mmio_addr;
2699         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2700
2701         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2702
2703         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2704                 return;
2705
2706         spin_lock_irq(&tp->lock);
2707
2708         if (tp->phy_reset_pending(tp)) {
2709                 /*
2710                  * A busy loop could burn quite a few cycles on nowadays CPU.
2711                  * Let's delay the execution of the timer for a few ticks.
2712                  */
2713                 timeout = HZ/10;
2714                 goto out_mod_timer;
2715         }
2716
2717         if (tp->link_ok(ioaddr))
2718                 goto out_unlock;
2719
2720         netif_warn(tp, link, dev, "PHY reset until link up\n");
2721
2722         tp->phy_reset_enable(tp);
2723
2724 out_mod_timer:
2725         mod_timer(timer, jiffies + timeout);
2726 out_unlock:
2727         spin_unlock_irq(&tp->lock);
2728 }
2729
2730 static inline void rtl8169_delete_timer(struct net_device *dev)
2731 {
2732         struct rtl8169_private *tp = netdev_priv(dev);
2733         struct timer_list *timer = &tp->timer;
2734
2735         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2736                 return;
2737
2738         del_timer_sync(timer);
2739 }
2740
2741 static inline void rtl8169_request_timer(struct net_device *dev)
2742 {
2743         struct rtl8169_private *tp = netdev_priv(dev);
2744         struct timer_list *timer = &tp->timer;
2745
2746         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2747                 return;
2748
2749         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2750 }
2751
2752 #ifdef CONFIG_NET_POLL_CONTROLLER
2753 /*
2754  * Polling 'interrupt' - used by things like netconsole to send skbs
2755  * without having to re-enable interrupts. It's not called while
2756  * the interrupt routine is executing.
2757  */
2758 static void rtl8169_netpoll(struct net_device *dev)
2759 {
2760         struct rtl8169_private *tp = netdev_priv(dev);
2761         struct pci_dev *pdev = tp->pci_dev;
2762
2763         disable_irq(pdev->irq);
2764         rtl8169_interrupt(pdev->irq, dev);
2765         enable_irq(pdev->irq);
2766 }
2767 #endif
2768
2769 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2770                                   void __iomem *ioaddr)
2771 {
2772         iounmap(ioaddr);
2773         pci_release_regions(pdev);
2774         pci_clear_mwi(pdev);
2775         pci_disable_device(pdev);
2776         free_netdev(dev);
2777 }
2778
2779 static void rtl8169_phy_reset(struct net_device *dev,
2780                               struct rtl8169_private *tp)
2781 {
2782         unsigned int i;
2783
2784         tp->phy_reset_enable(tp);
2785         for (i = 0; i < 100; i++) {
2786                 if (!tp->phy_reset_pending(tp))
2787                         return;
2788                 msleep(1);
2789         }
2790         netif_err(tp, link, dev, "PHY reset failed\n");
2791 }
2792
2793 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2794 {
2795         void __iomem *ioaddr = tp->mmio_addr;
2796
2797         rtl_hw_phy_config(dev);
2798
2799         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2800                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2801                 RTL_W8(0x82, 0x01);
2802         }
2803
2804         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2805
2806         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2807                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2808
2809         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2810                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2811                 RTL_W8(0x82, 0x01);
2812                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2813                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2814         }
2815
2816         rtl8169_phy_reset(dev, tp);
2817
2818         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2819                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2820                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2821                           (tp->mii.supports_gmii ?
2822                            ADVERTISED_1000baseT_Half |
2823                            ADVERTISED_1000baseT_Full : 0));
2824
2825         if (RTL_R8(PHYstatus) & TBI_Enable)
2826                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2827 }
2828
2829 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2830 {
2831         void __iomem *ioaddr = tp->mmio_addr;
2832         u32 high;
2833         u32 low;
2834
2835         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2836         high = addr[4] | (addr[5] << 8);
2837
2838         spin_lock_irq(&tp->lock);
2839
2840         RTL_W8(Cfg9346, Cfg9346_Unlock);
2841
2842         RTL_W32(MAC4, high);
2843         RTL_R32(MAC4);
2844
2845         RTL_W32(MAC0, low);
2846         RTL_R32(MAC0);
2847
2848         RTL_W8(Cfg9346, Cfg9346_Lock);
2849
2850         spin_unlock_irq(&tp->lock);
2851 }
2852
2853 static int rtl_set_mac_address(struct net_device *dev, void *p)
2854 {
2855         struct rtl8169_private *tp = netdev_priv(dev);
2856         struct sockaddr *addr = p;
2857
2858         if (!is_valid_ether_addr(addr->sa_data))
2859                 return -EADDRNOTAVAIL;
2860
2861         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2862
2863         rtl_rar_set(tp, dev->dev_addr);
2864
2865         return 0;
2866 }
2867
2868 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2869 {
2870         struct rtl8169_private *tp = netdev_priv(dev);
2871         struct mii_ioctl_data *data = if_mii(ifr);
2872
2873         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2874 }
2875
2876 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2877                           struct mii_ioctl_data *data, int cmd)
2878 {
2879         switch (cmd) {
2880         case SIOCGMIIPHY:
2881                 data->phy_id = 32; /* Internal PHY */
2882                 return 0;
2883
2884         case SIOCGMIIREG:
2885                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2886                 return 0;
2887
2888         case SIOCSMIIREG:
2889                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2890                 return 0;
2891         }
2892         return -EOPNOTSUPP;
2893 }
2894
2895 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2896 {
2897         return -EOPNOTSUPP;
2898 }
2899
2900 static const struct rtl_cfg_info {
2901         void (*hw_start)(struct net_device *);
2902         unsigned int region;
2903         unsigned int align;
2904         u16 intr_event;
2905         u16 napi_event;
2906         unsigned features;
2907         u8 default_ver;
2908 } rtl_cfg_infos [] = {
2909         [RTL_CFG_0] = {
2910                 .hw_start       = rtl_hw_start_8169,
2911                 .region         = 1,
2912                 .align          = 0,
2913                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2914                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2915                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2916                 .features       = RTL_FEATURE_GMII,
2917                 .default_ver    = RTL_GIGA_MAC_VER_01,
2918         },
2919         [RTL_CFG_1] = {
2920                 .hw_start       = rtl_hw_start_8168,
2921                 .region         = 2,
2922                 .align          = 8,
2923                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2924                                   TxErr | TxOK | RxOK | RxErr,
2925                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
2926                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2927                 .default_ver    = RTL_GIGA_MAC_VER_11,
2928         },
2929         [RTL_CFG_2] = {
2930                 .hw_start       = rtl_hw_start_8101,
2931                 .region         = 2,
2932                 .align          = 8,
2933                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2934                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2935                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2936                 .features       = RTL_FEATURE_MSI,
2937                 .default_ver    = RTL_GIGA_MAC_VER_13,
2938         }
2939 };
2940
2941 /* Cfg9346_Unlock assumed. */
2942 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2943                             const struct rtl_cfg_info *cfg)
2944 {
2945         unsigned msi = 0;
2946         u8 cfg2;
2947
2948         cfg2 = RTL_R8(Config2) & ~MSIEnable;
2949         if (cfg->features & RTL_FEATURE_MSI) {
2950                 if (pci_enable_msi(pdev)) {
2951                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2952                 } else {
2953                         cfg2 |= MSIEnable;
2954                         msi = RTL_FEATURE_MSI;
2955                 }
2956         }
2957         RTL_W8(Config2, cfg2);
2958         return msi;
2959 }
2960
2961 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2962 {
2963         if (tp->features & RTL_FEATURE_MSI) {
2964                 pci_disable_msi(pdev);
2965                 tp->features &= ~RTL_FEATURE_MSI;
2966         }
2967 }
2968
2969 static const struct net_device_ops rtl8169_netdev_ops = {
2970         .ndo_open               = rtl8169_open,
2971         .ndo_stop               = rtl8169_close,
2972         .ndo_get_stats          = rtl8169_get_stats,
2973         .ndo_start_xmit         = rtl8169_start_xmit,
2974         .ndo_tx_timeout         = rtl8169_tx_timeout,
2975         .ndo_validate_addr      = eth_validate_addr,
2976         .ndo_change_mtu         = rtl8169_change_mtu,
2977         .ndo_fix_features       = rtl8169_fix_features,
2978         .ndo_set_features       = rtl8169_set_features,
2979         .ndo_set_mac_address    = rtl_set_mac_address,
2980         .ndo_do_ioctl           = rtl8169_ioctl,
2981         .ndo_set_multicast_list = rtl_set_rx_mode,
2982 #ifdef CONFIG_NET_POLL_CONTROLLER
2983         .ndo_poll_controller    = rtl8169_netpoll,
2984 #endif
2985
2986 };
2987
2988 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2989 {
2990         struct mdio_ops *ops = &tp->mdio_ops;
2991
2992         switch (tp->mac_version) {
2993         case RTL_GIGA_MAC_VER_27:
2994                 ops->write      = r8168dp_1_mdio_write;
2995                 ops->read       = r8168dp_1_mdio_read;
2996                 break;
2997         case RTL_GIGA_MAC_VER_28:
2998         case RTL_GIGA_MAC_VER_31:
2999                 ops->write      = r8168dp_2_mdio_write;
3000                 ops->read       = r8168dp_2_mdio_read;
3001                 break;
3002         default:
3003                 ops->write      = r8169_mdio_write;
3004                 ops->read       = r8169_mdio_read;
3005                 break;
3006         }
3007 }
3008
3009 static void r810x_phy_power_down(struct rtl8169_private *tp)
3010 {
3011         rtl_writephy(tp, 0x1f, 0x0000);
3012         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3013 }
3014
3015 static void r810x_phy_power_up(struct rtl8169_private *tp)
3016 {
3017         rtl_writephy(tp, 0x1f, 0x0000);
3018         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3019 }
3020
3021 static void r810x_pll_power_down(struct rtl8169_private *tp)
3022 {
3023         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3024                 rtl_writephy(tp, 0x1f, 0x0000);
3025                 rtl_writephy(tp, MII_BMCR, 0x0000);
3026                 return;
3027         }
3028
3029         r810x_phy_power_down(tp);
3030 }
3031
3032 static void r810x_pll_power_up(struct rtl8169_private *tp)
3033 {
3034         r810x_phy_power_up(tp);
3035 }
3036
3037 static void r8168_phy_power_up(struct rtl8169_private *tp)
3038 {
3039         rtl_writephy(tp, 0x1f, 0x0000);
3040         switch (tp->mac_version) {
3041         case RTL_GIGA_MAC_VER_11:
3042         case RTL_GIGA_MAC_VER_12:
3043         case RTL_GIGA_MAC_VER_17:
3044         case RTL_GIGA_MAC_VER_18:
3045         case RTL_GIGA_MAC_VER_19:
3046         case RTL_GIGA_MAC_VER_20:
3047         case RTL_GIGA_MAC_VER_21:
3048         case RTL_GIGA_MAC_VER_22:
3049         case RTL_GIGA_MAC_VER_23:
3050         case RTL_GIGA_MAC_VER_24:
3051         case RTL_GIGA_MAC_VER_25:
3052         case RTL_GIGA_MAC_VER_26:
3053         case RTL_GIGA_MAC_VER_27:
3054         case RTL_GIGA_MAC_VER_28:
3055         case RTL_GIGA_MAC_VER_31:
3056                 rtl_writephy(tp, 0x0e, 0x0000);
3057                 break;
3058         default:
3059                 break;
3060         }
3061         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3062 }
3063
3064 static void r8168_phy_power_down(struct rtl8169_private *tp)
3065 {
3066         rtl_writephy(tp, 0x1f, 0x0000);
3067         switch (tp->mac_version) {
3068         case RTL_GIGA_MAC_VER_32:
3069         case RTL_GIGA_MAC_VER_33:
3070                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3071                 break;
3072
3073         case RTL_GIGA_MAC_VER_11:
3074         case RTL_GIGA_MAC_VER_12:
3075         case RTL_GIGA_MAC_VER_17:
3076         case RTL_GIGA_MAC_VER_18:
3077         case RTL_GIGA_MAC_VER_19:
3078         case RTL_GIGA_MAC_VER_20:
3079         case RTL_GIGA_MAC_VER_21:
3080         case RTL_GIGA_MAC_VER_22:
3081         case RTL_GIGA_MAC_VER_23:
3082         case RTL_GIGA_MAC_VER_24:
3083         case RTL_GIGA_MAC_VER_25:
3084         case RTL_GIGA_MAC_VER_26:
3085         case RTL_GIGA_MAC_VER_27:
3086         case RTL_GIGA_MAC_VER_28:
3087         case RTL_GIGA_MAC_VER_31:
3088                 rtl_writephy(tp, 0x0e, 0x0200);
3089         default:
3090                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3091                 break;
3092         }
3093 }
3094
3095 static void r8168_pll_power_down(struct rtl8169_private *tp)
3096 {
3097         void __iomem *ioaddr = tp->mmio_addr;
3098
3099         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3100              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3101              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3102             r8168dp_check_dash(tp)) {
3103                 return;
3104         }
3105
3106         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3107              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3108             (RTL_R16(CPlusCmd) & ASF)) {
3109                 return;
3110         }
3111
3112         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3113             tp->mac_version == RTL_GIGA_MAC_VER_33)
3114                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3115
3116         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3117                 rtl_writephy(tp, 0x1f, 0x0000);
3118                 rtl_writephy(tp, MII_BMCR, 0x0000);
3119
3120                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3121                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3122                 return;
3123         }
3124
3125         r8168_phy_power_down(tp);
3126
3127         switch (tp->mac_version) {
3128         case RTL_GIGA_MAC_VER_25:
3129         case RTL_GIGA_MAC_VER_26:
3130         case RTL_GIGA_MAC_VER_27:
3131         case RTL_GIGA_MAC_VER_28:
3132         case RTL_GIGA_MAC_VER_31:
3133         case RTL_GIGA_MAC_VER_32:
3134         case RTL_GIGA_MAC_VER_33:
3135                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3136                 break;
3137         }
3138 }
3139
3140 static void r8168_pll_power_up(struct rtl8169_private *tp)
3141 {
3142         void __iomem *ioaddr = tp->mmio_addr;
3143
3144         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3145              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3146              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3147             r8168dp_check_dash(tp)) {
3148                 return;
3149         }
3150
3151         switch (tp->mac_version) {
3152         case RTL_GIGA_MAC_VER_25:
3153         case RTL_GIGA_MAC_VER_26:
3154         case RTL_GIGA_MAC_VER_27:
3155         case RTL_GIGA_MAC_VER_28:
3156         case RTL_GIGA_MAC_VER_31:
3157         case RTL_GIGA_MAC_VER_32:
3158         case RTL_GIGA_MAC_VER_33:
3159                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3160                 break;
3161         }
3162
3163         r8168_phy_power_up(tp);
3164 }
3165
3166 static void rtl_pll_power_op(struct rtl8169_private *tp,
3167                              void (*op)(struct rtl8169_private *))
3168 {
3169         if (op)
3170                 op(tp);
3171 }
3172
3173 static void rtl_pll_power_down(struct rtl8169_private *tp)
3174 {
3175         rtl_pll_power_op(tp, tp->pll_power_ops.down);
3176 }
3177
3178 static void rtl_pll_power_up(struct rtl8169_private *tp)
3179 {
3180         rtl_pll_power_op(tp, tp->pll_power_ops.up);
3181 }
3182
3183 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3184 {
3185         struct pll_power_ops *ops = &tp->pll_power_ops;
3186
3187         switch (tp->mac_version) {
3188         case RTL_GIGA_MAC_VER_07:
3189         case RTL_GIGA_MAC_VER_08:
3190         case RTL_GIGA_MAC_VER_09:
3191         case RTL_GIGA_MAC_VER_10:
3192         case RTL_GIGA_MAC_VER_16:
3193         case RTL_GIGA_MAC_VER_29:
3194         case RTL_GIGA_MAC_VER_30:
3195                 ops->down       = r810x_pll_power_down;
3196                 ops->up         = r810x_pll_power_up;
3197                 break;
3198
3199         case RTL_GIGA_MAC_VER_11:
3200         case RTL_GIGA_MAC_VER_12:
3201         case RTL_GIGA_MAC_VER_17:
3202         case RTL_GIGA_MAC_VER_18:
3203         case RTL_GIGA_MAC_VER_19:
3204         case RTL_GIGA_MAC_VER_20:
3205         case RTL_GIGA_MAC_VER_21:
3206         case RTL_GIGA_MAC_VER_22:
3207         case RTL_GIGA_MAC_VER_23:
3208         case RTL_GIGA_MAC_VER_24:
3209         case RTL_GIGA_MAC_VER_25:
3210         case RTL_GIGA_MAC_VER_26:
3211         case RTL_GIGA_MAC_VER_27:
3212         case RTL_GIGA_MAC_VER_28:
3213         case RTL_GIGA_MAC_VER_31:
3214         case RTL_GIGA_MAC_VER_32:
3215         case RTL_GIGA_MAC_VER_33:
3216                 ops->down       = r8168_pll_power_down;
3217                 ops->up         = r8168_pll_power_up;
3218                 break;
3219
3220         default:
3221                 ops->down       = NULL;
3222                 ops->up         = NULL;
3223                 break;
3224         }
3225 }
3226
3227 static void rtl_hw_reset(struct rtl8169_private *tp)
3228 {
3229         void __iomem *ioaddr = tp->mmio_addr;
3230         int i;
3231
3232         /* Soft reset the chip. */
3233         RTL_W8(ChipCmd, CmdReset);
3234
3235         /* Check that the chip has finished the reset. */
3236         for (i = 0; i < 100; i++) {
3237                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3238                         break;
3239                 msleep_interruptible(1);
3240         }
3241 }
3242
3243 static int __devinit
3244 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3245 {
3246         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3247         const unsigned int region = cfg->region;
3248         struct rtl8169_private *tp;
3249         struct mii_if_info *mii;
3250         struct net_device *dev;
3251         void __iomem *ioaddr;
3252         int chipset, i;
3253         int rc;
3254
3255         if (netif_msg_drv(&debug)) {
3256                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3257                        MODULENAME, RTL8169_VERSION);
3258         }
3259
3260         dev = alloc_etherdev(sizeof (*tp));
3261         if (!dev) {
3262                 if (netif_msg_drv(&debug))
3263                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3264                 rc = -ENOMEM;
3265                 goto out;
3266         }
3267
3268         SET_NETDEV_DEV(dev, &pdev->dev);
3269         dev->netdev_ops = &rtl8169_netdev_ops;
3270         tp = netdev_priv(dev);
3271         tp->dev = dev;
3272         tp->pci_dev = pdev;
3273         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3274
3275         mii = &tp->mii;
3276         mii->dev = dev;
3277         mii->mdio_read = rtl_mdio_read;
3278         mii->mdio_write = rtl_mdio_write;
3279         mii->phy_id_mask = 0x1f;
3280         mii->reg_num_mask = 0x1f;
3281         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3282
3283         /* disable ASPM completely as that cause random device stop working
3284          * problems as well as full system hangs for some PCIe devices users */
3285         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3286                                      PCIE_LINK_STATE_CLKPM);
3287
3288         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3289         rc = pci_enable_device(pdev);
3290         if (rc < 0) {
3291                 netif_err(tp, probe, dev, "enable failure\n");
3292                 goto err_out_free_dev_1;
3293         }
3294
3295         if (pci_set_mwi(pdev) < 0)
3296                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3297
3298         /* make sure PCI base addr 1 is MMIO */
3299         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3300                 netif_err(tp, probe, dev,
3301                           "region #%d not an MMIO resource, aborting\n",
3302                           region);
3303                 rc = -ENODEV;
3304                 goto err_out_mwi_2;
3305         }
3306
3307         /* check for weird/broken PCI region reporting */
3308         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3309                 netif_err(tp, probe, dev,
3310                           "Invalid PCI region size(s), aborting\n");
3311                 rc = -ENODEV;
3312                 goto err_out_mwi_2;
3313         }
3314
3315         rc = pci_request_regions(pdev, MODULENAME);
3316         if (rc < 0) {
3317                 netif_err(tp, probe, dev, "could not request regions\n");
3318                 goto err_out_mwi_2;
3319         }
3320
3321         tp->cp_cmd = RxChkSum;
3322
3323         if ((sizeof(dma_addr_t) > 4) &&
3324             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3325                 tp->cp_cmd |= PCIDAC;
3326                 dev->features |= NETIF_F_HIGHDMA;
3327         } else {
3328                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3329                 if (rc < 0) {
3330                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3331                         goto err_out_free_res_3;
3332                 }
3333         }
3334
3335         /* ioremap MMIO region */
3336         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3337         if (!ioaddr) {
3338                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3339                 rc = -EIO;
3340                 goto err_out_free_res_3;
3341         }
3342         tp->mmio_addr = ioaddr;
3343
3344         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3345         if (!tp->pcie_cap)
3346                 netif_info(tp, probe, dev, "no PCI Express capability\n");
3347
3348         RTL_W16(IntrMask, 0x0000);
3349
3350         rtl_hw_reset(tp);
3351
3352         RTL_W16(IntrStatus, 0xffff);
3353
3354         pci_set_master(pdev);
3355
3356         /* Identify chip attached to board */
3357         rtl8169_get_mac_version(tp, ioaddr);
3358
3359         /*
3360          * Pretend we are using VLANs; This bypasses a nasty bug where
3361          * Interrupts stop flowing on high load on 8110SCd controllers.
3362          */
3363         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3364                 tp->cp_cmd |= RxVlan;
3365
3366         rtl_init_mdio_ops(tp);
3367         rtl_init_pll_power_ops(tp);
3368
3369         /* Use appropriate default if unknown */
3370         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3371                 netif_notice(tp, probe, dev,
3372                              "unknown MAC, using family default\n");
3373                 tp->mac_version = cfg->default_ver;
3374         }
3375
3376         rtl8169_print_mac_version(tp);
3377
3378         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3379                 if (tp->mac_version == rtl_chip_info[i].mac_version)
3380                         break;
3381         }
3382         if (i == ARRAY_SIZE(rtl_chip_info)) {
3383                 dev_err(&pdev->dev,
3384                         "driver bug, MAC version not found in rtl_chip_info\n");
3385                 goto err_out_msi_4;
3386         }
3387         chipset = i;
3388         tp->txd_version = rtl_chip_info[chipset].txd_version;
3389
3390         RTL_W8(Cfg9346, Cfg9346_Unlock);
3391         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3392         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3393         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3394                 tp->features |= RTL_FEATURE_WOL;
3395         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3396                 tp->features |= RTL_FEATURE_WOL;
3397         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3398         RTL_W8(Cfg9346, Cfg9346_Lock);
3399
3400         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3401             (RTL_R8(PHYstatus) & TBI_Enable)) {
3402                 tp->set_speed = rtl8169_set_speed_tbi;
3403                 tp->get_settings = rtl8169_gset_tbi;
3404                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3405                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3406                 tp->link_ok = rtl8169_tbi_link_ok;
3407                 tp->do_ioctl = rtl_tbi_ioctl;
3408
3409                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3410         } else {
3411                 tp->set_speed = rtl8169_set_speed_xmii;
3412                 tp->get_settings = rtl8169_gset_xmii;
3413                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3414                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3415                 tp->link_ok = rtl8169_xmii_link_ok;
3416                 tp->do_ioctl = rtl_xmii_ioctl;
3417         }
3418
3419         spin_lock_init(&tp->lock);
3420
3421         /* Get MAC address */
3422         for (i = 0; i < MAC_ADDR_LEN; i++)
3423                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3424         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3425
3426         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3427         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3428         dev->irq = pdev->irq;
3429         dev->base_addr = (unsigned long) ioaddr;
3430
3431         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3432
3433         /* don't enable SG, IP_CSUM and TSO by default - it might not work
3434          * properly for all devices */
3435         dev->features |= NETIF_F_RXCSUM |
3436                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3437
3438         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3439                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3440         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3441                 NETIF_F_HIGHDMA;
3442
3443         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3444                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3445                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3446
3447         tp->intr_mask = 0xffff;
3448         tp->hw_start = cfg->hw_start;
3449         tp->intr_event = cfg->intr_event;
3450         tp->napi_event = cfg->napi_event;
3451
3452         init_timer(&tp->timer);
3453         tp->timer.data = (unsigned long) dev;
3454         tp->timer.function = rtl8169_phy_timer;
3455
3456         tp->fw = RTL_FIRMWARE_UNKNOWN;
3457
3458         rc = register_netdev(dev);
3459         if (rc < 0)
3460                 goto err_out_msi_4;
3461
3462         pci_set_drvdata(pdev, dev);
3463
3464         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3465                    rtl_chip_info[chipset].name, dev->base_addr, dev->dev_addr,
3466                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3467
3468         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3469             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3470             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3471                 rtl8168_driver_start(tp);
3472         }
3473
3474         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3475
3476         if (pci_dev_run_wake(pdev))
3477                 pm_runtime_put_noidle(&pdev->dev);
3478
3479         netif_carrier_off(dev);
3480
3481 out:
3482         return rc;
3483
3484 err_out_msi_4:
3485         rtl_disable_msi(pdev, tp);
3486         iounmap(ioaddr);
3487 err_out_free_res_3:
3488         pci_release_regions(pdev);
3489 err_out_mwi_2:
3490         pci_clear_mwi(pdev);
3491         pci_disable_device(pdev);
3492 err_out_free_dev_1:
3493         free_netdev(dev);
3494         goto out;
3495 }
3496
3497 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3498 {
3499         struct net_device *dev = pci_get_drvdata(pdev);
3500         struct rtl8169_private *tp = netdev_priv(dev);
3501
3502         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3503             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3504             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3505                 rtl8168_driver_stop(tp);
3506         }
3507
3508         cancel_delayed_work_sync(&tp->task);
3509
3510         unregister_netdev(dev);
3511
3512         rtl_release_firmware(tp);
3513
3514         if (pci_dev_run_wake(pdev))
3515                 pm_runtime_get_noresume(&pdev->dev);
3516
3517         /* restore original MAC address */
3518         rtl_rar_set(tp, dev->perm_addr);
3519
3520         rtl_disable_msi(pdev, tp);
3521         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3522         pci_set_drvdata(pdev, NULL);
3523 }
3524
3525 static void rtl_request_firmware(struct rtl8169_private *tp)
3526 {
3527         int i;
3528
3529         /* Return early if the firmware is already loaded / cached. */
3530         if (!IS_ERR(tp->fw))
3531                 goto out;
3532
3533         for (i = 0; i < ARRAY_SIZE(rtl_firmware_infos); i++) {
3534                 const struct rtl_firmware_info *info = rtl_firmware_infos + i;
3535
3536                 if (info->mac_version == tp->mac_version) {
3537                         const char *name = info->fw_name;
3538                         int rc;
3539
3540                         rc = request_firmware(&tp->fw, name, &tp->pci_dev->dev);
3541                         if (rc < 0) {
3542                                 netif_warn(tp, ifup, tp->dev, "unable to load "
3543                                         "firmware patch %s (%d)\n", name, rc);
3544                                 goto out_disable_request_firmware;
3545                         }
3546                         goto out;
3547                 }
3548         }
3549
3550 out_disable_request_firmware:
3551         tp->fw = NULL;
3552 out:
3553         return;
3554 }
3555
3556 static int rtl8169_open(struct net_device *dev)
3557 {
3558         struct rtl8169_private *tp = netdev_priv(dev);
3559         void __iomem *ioaddr = tp->mmio_addr;
3560         struct pci_dev *pdev = tp->pci_dev;
3561         int retval = -ENOMEM;
3562
3563         pm_runtime_get_sync(&pdev->dev);
3564
3565         /*
3566          * Rx and Tx desscriptors needs 256 bytes alignment.
3567          * dma_alloc_coherent provides more.
3568          */
3569         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3570                                              &tp->TxPhyAddr, GFP_KERNEL);
3571         if (!tp->TxDescArray)
3572                 goto err_pm_runtime_put;
3573
3574         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3575                                              &tp->RxPhyAddr, GFP_KERNEL);
3576         if (!tp->RxDescArray)
3577                 goto err_free_tx_0;
3578
3579         retval = rtl8169_init_ring(dev);
3580         if (retval < 0)
3581                 goto err_free_rx_1;
3582
3583         INIT_DELAYED_WORK(&tp->task, NULL);
3584
3585         smp_mb();
3586
3587         rtl_request_firmware(tp);
3588
3589         retval = request_irq(dev->irq, rtl8169_interrupt,
3590                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3591                              dev->name, dev);
3592         if (retval < 0)
3593                 goto err_release_fw_2;
3594
3595         napi_enable(&tp->napi);
3596
3597         rtl8169_init_phy(dev, tp);
3598
3599         rtl8169_set_features(dev, dev->features);
3600
3601         rtl_pll_power_up(tp);
3602
3603         rtl_hw_start(dev);
3604
3605         rtl8169_request_timer(dev);
3606
3607         tp->saved_wolopts = 0;
3608         pm_runtime_put_noidle(&pdev->dev);
3609
3610         rtl8169_check_link_status(dev, tp, ioaddr);
3611 out:
3612         return retval;
3613
3614 err_release_fw_2:
3615         rtl_release_firmware(tp);
3616         rtl8169_rx_clear(tp);
3617 err_free_rx_1:
3618         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3619                           tp->RxPhyAddr);
3620         tp->RxDescArray = NULL;
3621 err_free_tx_0:
3622         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3623                           tp->TxPhyAddr);
3624         tp->TxDescArray = NULL;
3625 err_pm_runtime_put:
3626         pm_runtime_put_noidle(&pdev->dev);
3627         goto out;
3628 }
3629
3630 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3631 {
3632         void __iomem *ioaddr = tp->mmio_addr;
3633
3634         /* Disable interrupts */
3635         rtl8169_irq_mask_and_ack(ioaddr);
3636
3637         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3638             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3639             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3640                 while (RTL_R8(TxPoll) & NPQ)
3641                         udelay(20);
3642
3643         }
3644
3645         /* Reset the chipset */
3646         RTL_W8(ChipCmd, CmdReset);
3647
3648         /* PCI commit */
3649         RTL_R8(ChipCmd);
3650 }
3651
3652 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3653 {
3654         void __iomem *ioaddr = tp->mmio_addr;
3655         u32 cfg = rtl8169_rx_config;
3656
3657         cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
3658         RTL_W32(RxConfig, cfg);
3659
3660         /* Set DMA burst size and Interframe Gap Time */
3661         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3662                 (InterFrameGap << TxInterFrameGapShift));
3663 }
3664
3665 static void rtl_hw_start(struct net_device *dev)
3666 {
3667         struct rtl8169_private *tp = netdev_priv(dev);
3668
3669         rtl_hw_reset(tp);
3670
3671         tp->hw_start(dev);
3672
3673         netif_start_queue(dev);
3674 }
3675
3676 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3677                                          void __iomem *ioaddr)
3678 {
3679         /*
3680          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3681          * register to be written before TxDescAddrLow to work.
3682          * Switching from MMIO to I/O access fixes the issue as well.
3683          */
3684         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3685         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3686         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3687         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3688 }
3689
3690 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3691 {
3692         u16 cmd;
3693
3694         cmd = RTL_R16(CPlusCmd);
3695         RTL_W16(CPlusCmd, cmd);
3696         return cmd;
3697 }
3698
3699 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3700 {
3701         /* Low hurts. Let's disable the filtering. */
3702         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3703 }
3704
3705 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3706 {
3707         static const struct {
3708                 u32 mac_version;
3709                 u32 clk;
3710                 u32 val;
3711         } cfg2_info [] = {
3712                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3713                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3714                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3715                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3716         }, *p = cfg2_info;
3717         unsigned int i;
3718         u32 clk;
3719
3720         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3721         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3722                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3723                         RTL_W32(0x7c, p->val);
3724                         break;
3725                 }
3726         }
3727 }
3728
3729 static void rtl_hw_start_8169(struct net_device *dev)
3730 {
3731         struct rtl8169_private *tp = netdev_priv(dev);
3732         void __iomem *ioaddr = tp->mmio_addr;
3733         struct pci_dev *pdev = tp->pci_dev;
3734
3735         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3736                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3737                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3738         }
3739
3740         RTL_W8(Cfg9346, Cfg9346_Unlock);
3741         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3742             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3743             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3744             tp->mac_version == RTL_GIGA_MAC_VER_04)
3745                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3746
3747         RTL_W8(EarlyTxThres, NoEarlyTx);
3748
3749         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3750
3751         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3752             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3753             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3754             tp->mac_version == RTL_GIGA_MAC_VER_04)
3755                 rtl_set_rx_tx_config_registers(tp);
3756
3757         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3758
3759         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3760             tp->mac_version == RTL_GIGA_MAC_VER_03) {
3761                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3762                         "Bit-3 and bit-14 MUST be 1\n");
3763                 tp->cp_cmd |= (1 << 14);
3764         }
3765
3766         RTL_W16(CPlusCmd, tp->cp_cmd);
3767
3768         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3769
3770         /*
3771          * Undocumented corner. Supposedly:
3772          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3773          */
3774         RTL_W16(IntrMitigate, 0x0000);
3775
3776         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3777
3778         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3779             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3780             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3781             tp->mac_version != RTL_GIGA_MAC_VER_04) {
3782                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3783                 rtl_set_rx_tx_config_registers(tp);
3784         }
3785
3786         RTL_W8(Cfg9346, Cfg9346_Lock);
3787
3788         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3789         RTL_R8(IntrMask);
3790
3791         RTL_W32(RxMissed, 0);
3792
3793         rtl_set_rx_mode(dev);
3794
3795         /* no early-rx interrupts */
3796         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3797
3798         /* Enable all known interrupts by setting the interrupt mask. */
3799         RTL_W16(IntrMask, tp->intr_event);
3800 }
3801
3802 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3803 {
3804         struct net_device *dev = pci_get_drvdata(pdev);
3805         struct rtl8169_private *tp = netdev_priv(dev);
3806         int cap = tp->pcie_cap;
3807
3808         if (cap) {
3809                 u16 ctl;
3810
3811                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3812                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3813                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3814         }
3815 }
3816
3817 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3818 {
3819         u32 csi;
3820
3821         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3822         rtl_csi_write(ioaddr, 0x070c, csi | bits);
3823 }
3824
3825 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3826 {
3827         rtl_csi_access_enable(ioaddr, 0x17000000);
3828 }
3829
3830 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3831 {
3832         rtl_csi_access_enable(ioaddr, 0x27000000);
3833 }
3834
3835 struct ephy_info {
3836         unsigned int offset;
3837         u16 mask;
3838         u16 bits;
3839 };
3840
3841 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3842 {
3843         u16 w;
3844
3845         while (len-- > 0) {
3846                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3847                 rtl_ephy_write(ioaddr, e->offset, w);
3848                 e++;
3849         }
3850 }
3851
3852 static void rtl_disable_clock_request(struct pci_dev *pdev)
3853 {
3854         struct net_device *dev = pci_get_drvdata(pdev);
3855         struct rtl8169_private *tp = netdev_priv(dev);
3856         int cap = tp->pcie_cap;
3857
3858         if (cap) {
3859                 u16 ctl;
3860
3861                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3862                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3863                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3864         }
3865 }
3866
3867 static void rtl_enable_clock_request(struct pci_dev *pdev)
3868 {
3869         struct net_device *dev = pci_get_drvdata(pdev);
3870         struct rtl8169_private *tp = netdev_priv(dev);
3871         int cap = tp->pcie_cap;
3872
3873         if (cap) {
3874                 u16 ctl;
3875
3876                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3877                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3878                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3879         }
3880 }
3881
3882 #define R8168_CPCMD_QUIRK_MASK (\
3883         EnableBist | \
3884         Mac_dbgo_oe | \
3885         Force_half_dup | \
3886         Force_rxflow_en | \
3887         Force_txflow_en | \
3888         Cxpl_dbg_sel | \
3889         ASF | \
3890         PktCntrDisable | \
3891         Mac_dbgo_sel)
3892
3893 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3894 {
3895         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3896
3897         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3898
3899         rtl_tx_performance_tweak(pdev,
3900                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3901 }
3902
3903 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3904 {
3905         rtl_hw_start_8168bb(ioaddr, pdev);
3906
3907         RTL_W8(MaxTxPacketSize, TxPacketMax);
3908
3909         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3910 }
3911
3912 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3913 {
3914         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3915
3916         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3917
3918         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3919
3920         rtl_disable_clock_request(pdev);
3921
3922         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3923 }
3924
3925 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3926 {
3927         static const struct ephy_info e_info_8168cp[] = {
3928                 { 0x01, 0,      0x0001 },
3929                 { 0x02, 0x0800, 0x1000 },
3930                 { 0x03, 0,      0x0042 },
3931                 { 0x06, 0x0080, 0x0000 },
3932                 { 0x07, 0,      0x2000 }
3933         };
3934
3935         rtl_csi_access_enable_2(ioaddr);
3936
3937         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3938
3939         __rtl_hw_start_8168cp(ioaddr, pdev);
3940 }
3941
3942 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3943 {
3944         rtl_csi_access_enable_2(ioaddr);
3945
3946         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3947
3948         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3949
3950         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3951 }
3952
3953 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3954 {
3955         rtl_csi_access_enable_2(ioaddr);
3956
3957         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3958
3959         /* Magic. */
3960         RTL_W8(DBG_REG, 0x20);
3961
3962         RTL_W8(MaxTxPacketSize, TxPacketMax);
3963
3964         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3965
3966         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3967 }
3968
3969 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3970 {
3971         static const struct ephy_info e_info_8168c_1[] = {
3972                 { 0x02, 0x0800, 0x1000 },
3973                 { 0x03, 0,      0x0002 },
3974                 { 0x06, 0x0080, 0x0000 }
3975         };
3976
3977         rtl_csi_access_enable_2(ioaddr);
3978
3979         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3980
3981         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3982
3983         __rtl_hw_start_8168cp(ioaddr, pdev);
3984 }
3985
3986 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3987 {
3988         static const struct ephy_info e_info_8168c_2[] = {
3989                 { 0x01, 0,      0x0001 },
3990                 { 0x03, 0x0400, 0x0220 }
3991         };
3992
3993         rtl_csi_access_enable_2(ioaddr);
3994
3995         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3996
3997         __rtl_hw_start_8168cp(ioaddr, pdev);
3998 }
3999
4000 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4001 {
4002         rtl_hw_start_8168c_2(ioaddr, pdev);
4003 }
4004
4005 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4006 {
4007         rtl_csi_access_enable_2(ioaddr);
4008
4009         __rtl_hw_start_8168cp(ioaddr, pdev);
4010 }
4011
4012 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4013 {
4014         rtl_csi_access_enable_2(ioaddr);
4015
4016         rtl_disable_clock_request(pdev);
4017
4018         RTL_W8(MaxTxPacketSize, TxPacketMax);
4019
4020         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4021
4022         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4023 }
4024
4025 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4026 {
4027         rtl_csi_access_enable_1(ioaddr);
4028
4029         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4030
4031         RTL_W8(MaxTxPacketSize, TxPacketMax);
4032
4033         rtl_disable_clock_request(pdev);
4034 }
4035
4036 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4037 {
4038         static const struct ephy_info e_info_8168d_4[] = {
4039                 { 0x0b, ~0,     0x48 },
4040                 { 0x19, 0x20,   0x50 },
4041                 { 0x0c, ~0,     0x20 }
4042         };
4043         int i;
4044
4045         rtl_csi_access_enable_1(ioaddr);
4046
4047         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4048
4049         RTL_W8(MaxTxPacketSize, TxPacketMax);
4050
4051         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4052                 const struct ephy_info *e = e_info_8168d_4 + i;
4053                 u16 w;
4054
4055                 w = rtl_ephy_read(ioaddr, e->offset);
4056                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4057         }
4058
4059         rtl_enable_clock_request(pdev);
4060 }
4061
4062 static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4063 {
4064         static const struct ephy_info e_info_8168e[] = {
4065                 { 0x00, 0x0200, 0x0100 },
4066                 { 0x00, 0x0000, 0x0004 },
4067                 { 0x06, 0x0002, 0x0001 },
4068                 { 0x06, 0x0000, 0x0030 },
4069                 { 0x07, 0x0000, 0x2000 },
4070                 { 0x00, 0x0000, 0x0020 },
4071                 { 0x03, 0x5800, 0x2000 },
4072                 { 0x03, 0x0000, 0x0001 },
4073                 { 0x01, 0x0800, 0x1000 },
4074                 { 0x07, 0x0000, 0x4000 },
4075                 { 0x1e, 0x0000, 0x2000 },
4076                 { 0x19, 0xffff, 0xfe6c },
4077                 { 0x0a, 0x0000, 0x0040 }
4078         };
4079
4080         rtl_csi_access_enable_2(ioaddr);
4081
4082         rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4083
4084         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4085
4086         RTL_W8(MaxTxPacketSize, TxPacketMax);
4087
4088         rtl_disable_clock_request(pdev);
4089
4090         /* Reset tx FIFO pointer */
4091         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4092         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4093
4094         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4095 }
4096
4097 static void rtl_hw_start_8168(struct net_device *dev)
4098 {
4099         struct rtl8169_private *tp = netdev_priv(dev);
4100         void __iomem *ioaddr = tp->mmio_addr;
4101         struct pci_dev *pdev = tp->pci_dev;
4102
4103         RTL_W8(Cfg9346, Cfg9346_Unlock);
4104
4105         RTL_W8(MaxTxPacketSize, TxPacketMax);
4106
4107         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4108
4109         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4110
4111         RTL_W16(CPlusCmd, tp->cp_cmd);
4112
4113         RTL_W16(IntrMitigate, 0x5151);
4114
4115         /* Work around for RxFIFO overflow. */
4116         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4117             tp->mac_version == RTL_GIGA_MAC_VER_22) {
4118                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4119                 tp->intr_event &= ~RxOverflow;
4120         }
4121
4122         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4123
4124         rtl_set_rx_mode(dev);
4125
4126         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4127                 (InterFrameGap << TxInterFrameGapShift));
4128
4129         RTL_R8(IntrMask);
4130
4131         switch (tp->mac_version) {
4132         case RTL_GIGA_MAC_VER_11:
4133                 rtl_hw_start_8168bb(ioaddr, pdev);
4134                 break;
4135
4136         case RTL_GIGA_MAC_VER_12:
4137         case RTL_GIGA_MAC_VER_17:
4138                 rtl_hw_start_8168bef(ioaddr, pdev);
4139                 break;
4140
4141         case RTL_GIGA_MAC_VER_18:
4142                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4143                 break;
4144
4145         case RTL_GIGA_MAC_VER_19:
4146                 rtl_hw_start_8168c_1(ioaddr, pdev);
4147                 break;
4148
4149         case RTL_GIGA_MAC_VER_20:
4150                 rtl_hw_start_8168c_2(ioaddr, pdev);
4151                 break;
4152
4153         case RTL_GIGA_MAC_VER_21:
4154                 rtl_hw_start_8168c_3(ioaddr, pdev);
4155                 break;
4156
4157         case RTL_GIGA_MAC_VER_22:
4158                 rtl_hw_start_8168c_4(ioaddr, pdev);
4159                 break;
4160
4161         case RTL_GIGA_MAC_VER_23:
4162                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4163                 break;
4164
4165         case RTL_GIGA_MAC_VER_24:
4166                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4167                 break;
4168
4169         case RTL_GIGA_MAC_VER_25:
4170         case RTL_GIGA_MAC_VER_26:
4171         case RTL_GIGA_MAC_VER_27:
4172                 rtl_hw_start_8168d(ioaddr, pdev);
4173                 break;
4174
4175         case RTL_GIGA_MAC_VER_28:
4176                 rtl_hw_start_8168d_4(ioaddr, pdev);
4177                 break;
4178
4179         case RTL_GIGA_MAC_VER_31:
4180                 rtl_hw_start_8168dp(ioaddr, pdev);
4181                 break;
4182
4183         case RTL_GIGA_MAC_VER_32:
4184         case RTL_GIGA_MAC_VER_33:
4185                 rtl_hw_start_8168e(ioaddr, pdev);
4186                 break;
4187
4188         default:
4189                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4190                         dev->name, tp->mac_version);
4191                 break;
4192         }
4193
4194         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4195
4196         RTL_W8(Cfg9346, Cfg9346_Lock);
4197
4198         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4199
4200         RTL_W16(IntrMask, tp->intr_event);
4201 }
4202
4203 #define R810X_CPCMD_QUIRK_MASK (\
4204         EnableBist | \
4205         Mac_dbgo_oe | \
4206         Force_half_dup | \
4207         Force_rxflow_en | \
4208         Force_txflow_en | \
4209         Cxpl_dbg_sel | \
4210         ASF | \
4211         PktCntrDisable | \
4212         Mac_dbgo_sel)
4213
4214 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4215 {
4216         static const struct ephy_info e_info_8102e_1[] = {
4217                 { 0x01, 0, 0x6e65 },
4218                 { 0x02, 0, 0x091f },
4219                 { 0x03, 0, 0xc2f9 },
4220                 { 0x06, 0, 0xafb5 },
4221                 { 0x07, 0, 0x0e00 },
4222                 { 0x19, 0, 0xec80 },
4223                 { 0x01, 0, 0x2e65 },
4224                 { 0x01, 0, 0x6e65 }
4225         };
4226         u8 cfg1;
4227
4228         rtl_csi_access_enable_2(ioaddr);
4229
4230         RTL_W8(DBG_REG, FIX_NAK_1);
4231
4232         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4233
4234         RTL_W8(Config1,
4235                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4236         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4237
4238         cfg1 = RTL_R8(Config1);
4239         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4240                 RTL_W8(Config1, cfg1 & ~LEDS0);
4241
4242         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4243 }
4244
4245 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4246 {
4247         rtl_csi_access_enable_2(ioaddr);
4248
4249         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4250
4251         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4252         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4253 }
4254
4255 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4256 {
4257         rtl_hw_start_8102e_2(ioaddr, pdev);
4258
4259         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4260 }
4261
4262 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4263 {
4264         static const struct ephy_info e_info_8105e_1[] = {
4265                 { 0x07, 0, 0x4000 },
4266                 { 0x19, 0, 0x0200 },
4267                 { 0x19, 0, 0x0020 },
4268                 { 0x1e, 0, 0x2000 },
4269                 { 0x03, 0, 0x0001 },
4270                 { 0x19, 0, 0x0100 },
4271                 { 0x19, 0, 0x0004 },
4272                 { 0x0a, 0, 0x0020 }
4273         };
4274
4275         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4276         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4277
4278         /* Disable Early Tally Counter */
4279         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4280
4281         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4282         RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4283
4284         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4285 }
4286
4287 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4288 {
4289         rtl_hw_start_8105e_1(ioaddr, pdev);
4290         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4291 }
4292
4293 static void rtl_hw_start_8101(struct net_device *dev)
4294 {
4295         struct rtl8169_private *tp = netdev_priv(dev);
4296         void __iomem *ioaddr = tp->mmio_addr;
4297         struct pci_dev *pdev = tp->pci_dev;
4298
4299         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4300             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4301                 int cap = tp->pcie_cap;
4302
4303                 if (cap) {
4304                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4305                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4306                 }
4307         }
4308
4309         RTL_W8(Cfg9346, Cfg9346_Unlock);
4310
4311         switch (tp->mac_version) {
4312         case RTL_GIGA_MAC_VER_07:
4313                 rtl_hw_start_8102e_1(ioaddr, pdev);
4314                 break;
4315
4316         case RTL_GIGA_MAC_VER_08:
4317                 rtl_hw_start_8102e_3(ioaddr, pdev);
4318                 break;
4319
4320         case RTL_GIGA_MAC_VER_09:
4321                 rtl_hw_start_8102e_2(ioaddr, pdev);
4322                 break;
4323
4324         case RTL_GIGA_MAC_VER_29:
4325                 rtl_hw_start_8105e_1(ioaddr, pdev);
4326                 break;
4327         case RTL_GIGA_MAC_VER_30:
4328                 rtl_hw_start_8105e_2(ioaddr, pdev);
4329                 break;
4330         }
4331
4332         RTL_W8(Cfg9346, Cfg9346_Lock);
4333
4334         RTL_W8(MaxTxPacketSize, TxPacketMax);
4335
4336         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4337
4338         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4339         RTL_W16(CPlusCmd, tp->cp_cmd);
4340
4341         RTL_W16(IntrMitigate, 0x0000);
4342
4343         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4344
4345         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4346         rtl_set_rx_tx_config_registers(tp);
4347
4348         RTL_R8(IntrMask);
4349
4350         rtl_set_rx_mode(dev);
4351
4352         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4353
4354         RTL_W16(IntrMask, tp->intr_event);
4355 }
4356
4357 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4358 {
4359         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4360                 return -EINVAL;
4361
4362         dev->mtu = new_mtu;
4363         netdev_update_features(dev);
4364
4365         return 0;
4366 }
4367
4368 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4369 {
4370         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4371         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4372 }
4373
4374 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4375                                      void **data_buff, struct RxDesc *desc)
4376 {
4377         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4378                          DMA_FROM_DEVICE);
4379
4380         kfree(*data_buff);
4381         *data_buff = NULL;
4382         rtl8169_make_unusable_by_asic(desc);
4383 }
4384
4385 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4386 {
4387         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4388
4389         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4390 }
4391
4392 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4393                                        u32 rx_buf_sz)
4394 {
4395         desc->addr = cpu_to_le64(mapping);
4396         wmb();
4397         rtl8169_mark_to_asic(desc, rx_buf_sz);
4398 }
4399
4400 static inline void *rtl8169_align(void *data)
4401 {
4402         return (void *)ALIGN((long)data, 16);
4403 }
4404
4405 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4406                                              struct RxDesc *desc)
4407 {
4408         void *data;
4409         dma_addr_t mapping;
4410         struct device *d = &tp->pci_dev->dev;
4411         struct net_device *dev = tp->dev;
4412         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4413
4414         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4415         if (!data)
4416                 return NULL;
4417
4418         if (rtl8169_align(data) != data) {
4419                 kfree(data);
4420                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4421                 if (!data)
4422                         return NULL;
4423         }
4424
4425         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4426                                  DMA_FROM_DEVICE);
4427         if (unlikely(dma_mapping_error(d, mapping))) {
4428                 if (net_ratelimit())
4429                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4430                 goto err_out;
4431         }
4432
4433         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4434         return data;
4435
4436 err_out:
4437         kfree(data);
4438         return NULL;
4439 }
4440
4441 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4442 {
4443         unsigned int i;
4444
4445         for (i = 0; i < NUM_RX_DESC; i++) {
4446                 if (tp->Rx_databuff[i]) {
4447                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4448                                             tp->RxDescArray + i);
4449                 }
4450         }
4451 }
4452
4453 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4454 {
4455         desc->opts1 |= cpu_to_le32(RingEnd);
4456 }
4457
4458 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4459 {
4460         unsigned int i;
4461
4462         for (i = 0; i < NUM_RX_DESC; i++) {
4463                 void *data;
4464
4465                 if (tp->Rx_databuff[i])
4466                         continue;
4467
4468                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4469                 if (!data) {
4470                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4471                         goto err_out;
4472                 }
4473                 tp->Rx_databuff[i] = data;
4474         }
4475
4476         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4477         return 0;
4478
4479 err_out:
4480         rtl8169_rx_clear(tp);
4481         return -ENOMEM;
4482 }
4483
4484 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4485 {
4486         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4487 }
4488
4489 static int rtl8169_init_ring(struct net_device *dev)
4490 {
4491         struct rtl8169_private *tp = netdev_priv(dev);
4492
4493         rtl8169_init_ring_indexes(tp);
4494
4495         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4496         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4497
4498         return rtl8169_rx_fill(tp);
4499 }
4500
4501 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4502                                  struct TxDesc *desc)
4503 {
4504         unsigned int len = tx_skb->len;
4505
4506         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4507
4508         desc->opts1 = 0x00;
4509         desc->opts2 = 0x00;
4510         desc->addr = 0x00;
4511         tx_skb->len = 0;
4512 }
4513
4514 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4515                                    unsigned int n)
4516 {
4517         unsigned int i;
4518
4519         for (i = 0; i < n; i++) {
4520                 unsigned int entry = (start + i) % NUM_TX_DESC;
4521                 struct ring_info *tx_skb = tp->tx_skb + entry;
4522                 unsigned int len = tx_skb->len;
4523
4524                 if (len) {
4525                         struct sk_buff *skb = tx_skb->skb;
4526
4527                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4528                                              tp->TxDescArray + entry);
4529                         if (skb) {
4530                                 tp->dev->stats.tx_dropped++;
4531                                 dev_kfree_skb(skb);
4532                                 tx_skb->skb = NULL;
4533                         }
4534                 }
4535         }
4536 }
4537
4538 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4539 {
4540         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4541         tp->cur_tx = tp->dirty_tx = 0;
4542 }
4543
4544 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4545 {
4546         struct rtl8169_private *tp = netdev_priv(dev);
4547
4548         PREPARE_DELAYED_WORK(&tp->task, task);
4549         schedule_delayed_work(&tp->task, 4);
4550 }
4551
4552 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4553 {
4554         struct rtl8169_private *tp = netdev_priv(dev);
4555         void __iomem *ioaddr = tp->mmio_addr;
4556
4557         synchronize_irq(dev->irq);
4558
4559         /* Wait for any pending NAPI task to complete */
4560         napi_disable(&tp->napi);
4561
4562         rtl8169_irq_mask_and_ack(ioaddr);
4563
4564         tp->intr_mask = 0xffff;
4565         RTL_W16(IntrMask, tp->intr_event);
4566         napi_enable(&tp->napi);
4567 }
4568
4569 static void rtl8169_reinit_task(struct work_struct *work)
4570 {
4571         struct rtl8169_private *tp =
4572                 container_of(work, struct rtl8169_private, task.work);
4573         struct net_device *dev = tp->dev;
4574         int ret;
4575
4576         rtnl_lock();
4577
4578         if (!netif_running(dev))
4579                 goto out_unlock;
4580
4581         rtl8169_wait_for_quiescence(dev);
4582         rtl8169_close(dev);
4583
4584         ret = rtl8169_open(dev);
4585         if (unlikely(ret < 0)) {
4586                 if (net_ratelimit())
4587                         netif_err(tp, drv, dev,
4588                                   "reinit failure (status = %d). Rescheduling\n",
4589                                   ret);
4590                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4591         }
4592
4593 out_unlock:
4594         rtnl_unlock();
4595 }
4596
4597 static void rtl8169_reset_task(struct work_struct *work)
4598 {
4599         struct rtl8169_private *tp =
4600                 container_of(work, struct rtl8169_private, task.work);
4601         struct net_device *dev = tp->dev;
4602
4603         rtnl_lock();
4604
4605         if (!netif_running(dev))
4606                 goto out_unlock;
4607
4608         rtl8169_wait_for_quiescence(dev);
4609
4610         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4611         rtl8169_tx_clear(tp);
4612
4613         if (tp->dirty_rx == tp->cur_rx) {
4614                 rtl8169_init_ring_indexes(tp);
4615                 rtl_hw_start(dev);
4616                 netif_wake_queue(dev);
4617                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4618         } else {
4619                 if (net_ratelimit())
4620                         netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4621                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4622         }
4623
4624 out_unlock:
4625         rtnl_unlock();
4626 }
4627
4628 static void rtl8169_tx_timeout(struct net_device *dev)
4629 {
4630         struct rtl8169_private *tp = netdev_priv(dev);
4631
4632         rtl8169_hw_reset(tp);
4633
4634         /* Let's wait a bit while any (async) irq lands on */
4635         rtl8169_schedule_work(dev, rtl8169_reset_task);
4636 }
4637
4638 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4639                               u32 *opts)
4640 {
4641         struct skb_shared_info *info = skb_shinfo(skb);
4642         unsigned int cur_frag, entry;
4643         struct TxDesc * uninitialized_var(txd);
4644         struct device *d = &tp->pci_dev->dev;
4645
4646         entry = tp->cur_tx;
4647         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4648                 skb_frag_t *frag = info->frags + cur_frag;
4649                 dma_addr_t mapping;
4650                 u32 status, len;
4651                 void *addr;
4652
4653                 entry = (entry + 1) % NUM_TX_DESC;
4654
4655                 txd = tp->TxDescArray + entry;
4656                 len = frag->size;
4657                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4658                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4659                 if (unlikely(dma_mapping_error(d, mapping))) {
4660                         if (net_ratelimit())
4661                                 netif_err(tp, drv, tp->dev,
4662                                           "Failed to map TX fragments DMA!\n");
4663                         goto err_out;
4664                 }
4665
4666                 /* Anti gcc 2.95.3 bugware (sic) */
4667                 status = opts[0] | len |
4668                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
4669
4670                 txd->opts1 = cpu_to_le32(status);
4671                 txd->opts2 = cpu_to_le32(opts[1]);
4672                 txd->addr = cpu_to_le64(mapping);
4673
4674                 tp->tx_skb[entry].len = len;
4675         }
4676
4677         if (cur_frag) {
4678                 tp->tx_skb[entry].skb = skb;
4679                 txd->opts1 |= cpu_to_le32(LastFrag);
4680         }
4681
4682         return cur_frag;
4683
4684 err_out:
4685         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4686         return -EIO;
4687 }
4688
4689 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4690                                     struct sk_buff *skb, u32 *opts)
4691 {
4692         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
4693         u32 mss = skb_shinfo(skb)->gso_size;
4694         int offset = info->opts_offset;
4695
4696         if (mss) {
4697                 opts[0] |= TD_LSO;
4698                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4699         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4700                 const struct iphdr *ip = ip_hdr(skb);
4701
4702                 if (ip->protocol == IPPROTO_TCP)
4703                         opts[offset] |= info->checksum.tcp;
4704                 else if (ip->protocol == IPPROTO_UDP)
4705                         opts[offset] |= info->checksum.udp;
4706                 else
4707                         WARN_ON_ONCE(1);
4708         }
4709 }
4710
4711 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4712                                       struct net_device *dev)
4713 {
4714         struct rtl8169_private *tp = netdev_priv(dev);
4715         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4716         struct TxDesc *txd = tp->TxDescArray + entry;
4717         void __iomem *ioaddr = tp->mmio_addr;
4718         struct device *d = &tp->pci_dev->dev;
4719         dma_addr_t mapping;
4720         u32 status, len;
4721         u32 opts[2];
4722         int frags;
4723
4724         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4725                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4726                 goto err_stop_0;
4727         }
4728
4729         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4730                 goto err_stop_0;
4731
4732         len = skb_headlen(skb);
4733         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4734         if (unlikely(dma_mapping_error(d, mapping))) {
4735                 if (net_ratelimit())
4736                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4737                 goto err_dma_0;
4738         }
4739
4740         tp->tx_skb[entry].len = len;
4741         txd->addr = cpu_to_le64(mapping);
4742
4743         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4744         opts[0] = DescOwn;
4745
4746         rtl8169_tso_csum(tp, skb, opts);
4747
4748         frags = rtl8169_xmit_frags(tp, skb, opts);
4749         if (frags < 0)
4750                 goto err_dma_1;
4751         else if (frags)
4752                 opts[0] |= FirstFrag;
4753         else {
4754                 opts[0] |= FirstFrag | LastFrag;
4755                 tp->tx_skb[entry].skb = skb;
4756         }
4757
4758         txd->opts2 = cpu_to_le32(opts[1]);
4759
4760         wmb();
4761
4762         /* Anti gcc 2.95.3 bugware (sic) */
4763         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4764         txd->opts1 = cpu_to_le32(status);
4765
4766         tp->cur_tx += frags + 1;
4767
4768         wmb();
4769
4770         RTL_W8(TxPoll, NPQ);
4771
4772         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4773                 netif_stop_queue(dev);
4774                 smp_rmb();
4775                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4776                         netif_wake_queue(dev);
4777         }
4778
4779         return NETDEV_TX_OK;
4780
4781 err_dma_1:
4782         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4783 err_dma_0:
4784         dev_kfree_skb(skb);
4785         dev->stats.tx_dropped++;
4786         return NETDEV_TX_OK;
4787
4788 err_stop_0:
4789         netif_stop_queue(dev);
4790         dev->stats.tx_dropped++;
4791         return NETDEV_TX_BUSY;
4792 }
4793
4794 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4795 {
4796         struct rtl8169_private *tp = netdev_priv(dev);
4797         struct pci_dev *pdev = tp->pci_dev;
4798         u16 pci_status, pci_cmd;
4799
4800         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4801         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4802
4803         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4804                   pci_cmd, pci_status);
4805
4806         /*
4807          * The recovery sequence below admits a very elaborated explanation:
4808          * - it seems to work;
4809          * - I did not see what else could be done;
4810          * - it makes iop3xx happy.
4811          *
4812          * Feel free to adjust to your needs.
4813          */
4814         if (pdev->broken_parity_status)
4815                 pci_cmd &= ~PCI_COMMAND_PARITY;
4816         else
4817                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4818
4819         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4820
4821         pci_write_config_word(pdev, PCI_STATUS,
4822                 pci_status & (PCI_STATUS_DETECTED_PARITY |
4823                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4824                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4825
4826         /* The infamous DAC f*ckup only happens at boot time */
4827         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4828                 void __iomem *ioaddr = tp->mmio_addr;
4829
4830                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4831                 tp->cp_cmd &= ~PCIDAC;
4832                 RTL_W16(CPlusCmd, tp->cp_cmd);
4833                 dev->features &= ~NETIF_F_HIGHDMA;
4834         }
4835
4836         rtl8169_hw_reset(tp);
4837
4838         rtl8169_schedule_work(dev, rtl8169_reinit_task);
4839 }
4840
4841 static void rtl8169_tx_interrupt(struct net_device *dev,
4842                                  struct rtl8169_private *tp,
4843                                  void __iomem *ioaddr)
4844 {
4845         unsigned int dirty_tx, tx_left;
4846
4847         dirty_tx = tp->dirty_tx;
4848         smp_rmb();
4849         tx_left = tp->cur_tx - dirty_tx;
4850
4851         while (tx_left > 0) {
4852                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4853                 struct ring_info *tx_skb = tp->tx_skb + entry;
4854                 u32 status;
4855
4856                 rmb();
4857                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4858                 if (status & DescOwn)
4859                         break;
4860
4861                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4862                                      tp->TxDescArray + entry);
4863                 if (status & LastFrag) {
4864                         dev->stats.tx_packets++;
4865                         dev->stats.tx_bytes += tx_skb->skb->len;
4866                         dev_kfree_skb(tx_skb->skb);
4867                         tx_skb->skb = NULL;
4868                 }
4869                 dirty_tx++;
4870                 tx_left--;
4871         }
4872
4873         if (tp->dirty_tx != dirty_tx) {
4874                 tp->dirty_tx = dirty_tx;
4875                 smp_wmb();
4876                 if (netif_queue_stopped(dev) &&
4877                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4878                         netif_wake_queue(dev);
4879                 }
4880                 /*
4881                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4882                  * too close. Let's kick an extra TxPoll request when a burst
4883                  * of start_xmit activity is detected (if it is not detected,
4884                  * it is slow enough). -- FR
4885                  */
4886                 smp_rmb();
4887                 if (tp->cur_tx != dirty_tx)
4888                         RTL_W8(TxPoll, NPQ);
4889         }
4890 }
4891
4892 static inline int rtl8169_fragmented_frame(u32 status)
4893 {
4894         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4895 }
4896
4897 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4898 {
4899         u32 status = opts1 & RxProtoMask;
4900
4901         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4902             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4903                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4904         else
4905                 skb_checksum_none_assert(skb);
4906 }
4907
4908 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4909                                            struct rtl8169_private *tp,
4910                                            int pkt_size,
4911                                            dma_addr_t addr)
4912 {
4913         struct sk_buff *skb;
4914         struct device *d = &tp->pci_dev->dev;
4915
4916         data = rtl8169_align(data);
4917         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4918         prefetch(data);
4919         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4920         if (skb)
4921                 memcpy(skb->data, data, pkt_size);
4922         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4923
4924         return skb;
4925 }
4926
4927 /*
4928  * Warning : rtl8169_rx_interrupt() might be called :
4929  * 1) from NAPI (softirq) context
4930  *      (polling = 1 : we should call netif_receive_skb())
4931  * 2) from process context (rtl8169_reset_task())
4932  *      (polling = 0 : we must call netif_rx() instead)
4933  */
4934 static int rtl8169_rx_interrupt(struct net_device *dev,
4935                                 struct rtl8169_private *tp,
4936                                 void __iomem *ioaddr, u32 budget)
4937 {
4938         unsigned int cur_rx, rx_left;
4939         unsigned int count;
4940         int polling = (budget != ~(u32)0) ? 1 : 0;
4941
4942         cur_rx = tp->cur_rx;
4943         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4944         rx_left = min(rx_left, budget);
4945
4946         for (; rx_left > 0; rx_left--, cur_rx++) {
4947                 unsigned int entry = cur_rx % NUM_RX_DESC;
4948                 struct RxDesc *desc = tp->RxDescArray + entry;
4949                 u32 status;
4950
4951                 rmb();
4952                 status = le32_to_cpu(desc->opts1);
4953
4954                 if (status & DescOwn)
4955                         break;
4956                 if (unlikely(status & RxRES)) {
4957                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4958                                    status);
4959                         dev->stats.rx_errors++;
4960                         if (status & (RxRWT | RxRUNT))
4961                                 dev->stats.rx_length_errors++;
4962                         if (status & RxCRC)
4963                                 dev->stats.rx_crc_errors++;
4964                         if (status & RxFOVF) {
4965                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4966                                 dev->stats.rx_fifo_errors++;
4967                         }
4968                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4969                 } else {
4970                         struct sk_buff *skb;
4971                         dma_addr_t addr = le64_to_cpu(desc->addr);
4972                         int pkt_size = (status & 0x00001FFF) - 4;
4973
4974                         /*
4975                          * The driver does not support incoming fragmented
4976                          * frames. They are seen as a symptom of over-mtu
4977                          * sized frames.
4978                          */
4979                         if (unlikely(rtl8169_fragmented_frame(status))) {
4980                                 dev->stats.rx_dropped++;
4981                                 dev->stats.rx_length_errors++;
4982                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
4983                                 continue;
4984                         }
4985
4986                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4987                                                   tp, pkt_size, addr);
4988                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4989                         if (!skb) {
4990                                 dev->stats.rx_dropped++;
4991                                 continue;
4992                         }
4993
4994                         rtl8169_rx_csum(skb, status);
4995                         skb_put(skb, pkt_size);
4996                         skb->protocol = eth_type_trans(skb, dev);
4997
4998                         rtl8169_rx_vlan_tag(desc, skb);
4999
5000                         if (likely(polling))
5001                                 napi_gro_receive(&tp->napi, skb);
5002                         else
5003                                 netif_rx(skb);
5004
5005                         dev->stats.rx_bytes += pkt_size;
5006                         dev->stats.rx_packets++;
5007                 }
5008
5009                 /* Work around for AMD plateform. */
5010                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5011                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5012                         desc->opts2 = 0;
5013                         cur_rx++;
5014                 }
5015         }
5016
5017         count = cur_rx - tp->cur_rx;
5018         tp->cur_rx = cur_rx;
5019
5020         tp->dirty_rx += count;
5021
5022         return count;
5023 }
5024
5025 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5026 {
5027         struct net_device *dev = dev_instance;
5028         struct rtl8169_private *tp = netdev_priv(dev);
5029         void __iomem *ioaddr = tp->mmio_addr;
5030         int handled = 0;
5031         int status;
5032
5033         /* loop handling interrupts until we have no new ones or
5034          * we hit a invalid/hotplug case.
5035          */
5036         status = RTL_R16(IntrStatus);
5037         while (status && status != 0xffff) {
5038                 handled = 1;
5039
5040                 /* Handle all of the error cases first. These will reset
5041                  * the chip, so just exit the loop.
5042                  */
5043                 if (unlikely(!netif_running(dev))) {
5044                         rtl8169_asic_down(ioaddr);
5045                         break;
5046                 }
5047
5048                 if (unlikely(status & RxFIFOOver)) {
5049                         switch (tp->mac_version) {
5050                         /* Work around for rx fifo overflow */
5051                         case RTL_GIGA_MAC_VER_11:
5052                         case RTL_GIGA_MAC_VER_22:
5053                         case RTL_GIGA_MAC_VER_26:
5054                                 netif_stop_queue(dev);
5055                                 rtl8169_tx_timeout(dev);
5056                                 goto done;
5057                         /* Testers needed. */
5058                         case RTL_GIGA_MAC_VER_17:
5059                         case RTL_GIGA_MAC_VER_19:
5060                         case RTL_GIGA_MAC_VER_20:
5061                         case RTL_GIGA_MAC_VER_21:
5062                         case RTL_GIGA_MAC_VER_23:
5063                         case RTL_GIGA_MAC_VER_24:
5064                         case RTL_GIGA_MAC_VER_27:
5065                         case RTL_GIGA_MAC_VER_28:
5066                         case RTL_GIGA_MAC_VER_31:
5067                         /* Experimental science. Pktgen proof. */
5068                         case RTL_GIGA_MAC_VER_12:
5069                         case RTL_GIGA_MAC_VER_25:
5070                                 if (status == RxFIFOOver)
5071                                         goto done;
5072                                 break;
5073                         default:
5074                                 break;
5075                         }
5076                 }
5077
5078                 if (unlikely(status & SYSErr)) {
5079                         rtl8169_pcierr_interrupt(dev);
5080                         break;
5081                 }
5082
5083                 if (status & LinkChg)
5084                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5085
5086                 /* We need to see the lastest version of tp->intr_mask to
5087                  * avoid ignoring an MSI interrupt and having to wait for
5088                  * another event which may never come.
5089                  */
5090                 smp_rmb();
5091                 if (status & tp->intr_mask & tp->napi_event) {
5092                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5093                         tp->intr_mask = ~tp->napi_event;
5094
5095                         if (likely(napi_schedule_prep(&tp->napi)))
5096                                 __napi_schedule(&tp->napi);
5097                         else
5098                                 netif_info(tp, intr, dev,
5099                                            "interrupt %04x in poll\n", status);
5100                 }
5101
5102                 /* We only get a new MSI interrupt when all active irq
5103                  * sources on the chip have been acknowledged. So, ack
5104                  * everything we've seen and check if new sources have become
5105                  * active to avoid blocking all interrupts from the chip.
5106                  */
5107                 RTL_W16(IntrStatus,
5108                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5109                 status = RTL_R16(IntrStatus);
5110         }
5111 done:
5112         return IRQ_RETVAL(handled);
5113 }
5114
5115 static int rtl8169_poll(struct napi_struct *napi, int budget)
5116 {
5117         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5118         struct net_device *dev = tp->dev;
5119         void __iomem *ioaddr = tp->mmio_addr;
5120         int work_done;
5121
5122         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5123         rtl8169_tx_interrupt(dev, tp, ioaddr);
5124
5125         if (work_done < budget) {
5126                 napi_complete(napi);
5127
5128                 /* We need for force the visibility of tp->intr_mask
5129                  * for other CPUs, as we can loose an MSI interrupt
5130                  * and potentially wait for a retransmit timeout if we don't.
5131                  * The posted write to IntrMask is safe, as it will
5132                  * eventually make it to the chip and we won't loose anything
5133                  * until it does.
5134                  */
5135                 tp->intr_mask = 0xffff;
5136                 wmb();
5137                 RTL_W16(IntrMask, tp->intr_event);
5138         }
5139
5140         return work_done;
5141 }
5142
5143 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5144 {
5145         struct rtl8169_private *tp = netdev_priv(dev);
5146
5147         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5148                 return;
5149
5150         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5151         RTL_W32(RxMissed, 0);
5152 }
5153
5154 static void rtl8169_down(struct net_device *dev)
5155 {
5156         struct rtl8169_private *tp = netdev_priv(dev);
5157         void __iomem *ioaddr = tp->mmio_addr;
5158
5159         rtl8169_delete_timer(dev);
5160
5161         netif_stop_queue(dev);
5162
5163         napi_disable(&tp->napi);
5164
5165         spin_lock_irq(&tp->lock);
5166
5167         rtl8169_asic_down(ioaddr);
5168         /*
5169          * At this point device interrupts can not be enabled in any function,
5170          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5171          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5172          */
5173         rtl8169_rx_missed(dev, ioaddr);
5174
5175         spin_unlock_irq(&tp->lock);
5176
5177         synchronize_irq(dev->irq);
5178
5179         /* Give a racing hard_start_xmit a few cycles to complete. */
5180         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5181
5182         rtl8169_tx_clear(tp);
5183
5184         rtl8169_rx_clear(tp);
5185
5186         rtl_pll_power_down(tp);
5187 }
5188
5189 static int rtl8169_close(struct net_device *dev)
5190 {
5191         struct rtl8169_private *tp = netdev_priv(dev);
5192         struct pci_dev *pdev = tp->pci_dev;
5193
5194         pm_runtime_get_sync(&pdev->dev);
5195
5196         /* Update counters before going down */
5197         rtl8169_update_counters(dev);
5198
5199         rtl8169_down(dev);
5200
5201         free_irq(dev->irq, dev);
5202
5203         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5204                           tp->RxPhyAddr);
5205         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5206                           tp->TxPhyAddr);
5207         tp->TxDescArray = NULL;
5208         tp->RxDescArray = NULL;
5209
5210         pm_runtime_put_sync(&pdev->dev);
5211
5212         return 0;
5213 }
5214
5215 static void rtl_set_rx_mode(struct net_device *dev)
5216 {
5217         struct rtl8169_private *tp = netdev_priv(dev);
5218         void __iomem *ioaddr = tp->mmio_addr;
5219         unsigned long flags;
5220         u32 mc_filter[2];       /* Multicast hash filter */
5221         int rx_mode;
5222         u32 tmp = 0;
5223
5224         if (dev->flags & IFF_PROMISC) {
5225                 /* Unconditionally log net taps. */
5226                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5227                 rx_mode =
5228                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5229                     AcceptAllPhys;
5230                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5231         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5232                    (dev->flags & IFF_ALLMULTI)) {
5233                 /* Too many to filter perfectly -- accept all multicasts. */
5234                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5235                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5236         } else {
5237                 struct netdev_hw_addr *ha;
5238
5239                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5240                 mc_filter[1] = mc_filter[0] = 0;
5241                 netdev_for_each_mc_addr(ha, dev) {
5242                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5243                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5244                         rx_mode |= AcceptMulticast;
5245                 }
5246         }
5247
5248         spin_lock_irqsave(&tp->lock, flags);
5249
5250         tmp = rtl8169_rx_config | rx_mode |
5251               (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
5252
5253         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5254                 u32 data = mc_filter[0];
5255
5256                 mc_filter[0] = swab32(mc_filter[1]);
5257                 mc_filter[1] = swab32(data);
5258         }
5259
5260         RTL_W32(MAR0 + 4, mc_filter[1]);
5261         RTL_W32(MAR0 + 0, mc_filter[0]);
5262
5263         RTL_W32(RxConfig, tmp);
5264
5265         spin_unlock_irqrestore(&tp->lock, flags);
5266 }
5267
5268 /**
5269  *  rtl8169_get_stats - Get rtl8169 read/write statistics
5270  *  @dev: The Ethernet Device to get statistics for
5271  *
5272  *  Get TX/RX statistics for rtl8169
5273  */
5274 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5275 {
5276         struct rtl8169_private *tp = netdev_priv(dev);
5277         void __iomem *ioaddr = tp->mmio_addr;
5278         unsigned long flags;
5279
5280         if (netif_running(dev)) {
5281                 spin_lock_irqsave(&tp->lock, flags);
5282                 rtl8169_rx_missed(dev, ioaddr);
5283                 spin_unlock_irqrestore(&tp->lock, flags);
5284         }
5285
5286         return &dev->stats;
5287 }
5288
5289 static void rtl8169_net_suspend(struct net_device *dev)
5290 {
5291         struct rtl8169_private *tp = netdev_priv(dev);
5292
5293         if (!netif_running(dev))
5294                 return;
5295
5296         rtl_pll_power_down(tp);
5297
5298         netif_device_detach(dev);
5299         netif_stop_queue(dev);
5300 }
5301
5302 #ifdef CONFIG_PM
5303
5304 static int rtl8169_suspend(struct device *device)
5305 {
5306         struct pci_dev *pdev = to_pci_dev(device);
5307         struct net_device *dev = pci_get_drvdata(pdev);
5308
5309         rtl8169_net_suspend(dev);
5310
5311         return 0;
5312 }
5313
5314 static void __rtl8169_resume(struct net_device *dev)
5315 {
5316         struct rtl8169_private *tp = netdev_priv(dev);
5317
5318         netif_device_attach(dev);
5319
5320         rtl_pll_power_up(tp);
5321
5322         rtl8169_schedule_work(dev, rtl8169_reset_task);
5323 }
5324
5325 static int rtl8169_resume(struct device *device)
5326 {
5327         struct pci_dev *pdev = to_pci_dev(device);
5328         struct net_device *dev = pci_get_drvdata(pdev);
5329         struct rtl8169_private *tp = netdev_priv(dev);
5330
5331         rtl8169_init_phy(dev, tp);
5332
5333         if (netif_running(dev))
5334                 __rtl8169_resume(dev);
5335
5336         return 0;
5337 }
5338
5339 static int rtl8169_runtime_suspend(struct device *device)
5340 {
5341         struct pci_dev *pdev = to_pci_dev(device);
5342         struct net_device *dev = pci_get_drvdata(pdev);
5343         struct rtl8169_private *tp = netdev_priv(dev);
5344
5345         if (!tp->TxDescArray)
5346                 return 0;
5347
5348         spin_lock_irq(&tp->lock);
5349         tp->saved_wolopts = __rtl8169_get_wol(tp);
5350         __rtl8169_set_wol(tp, WAKE_ANY);
5351         spin_unlock_irq(&tp->lock);
5352
5353         rtl8169_net_suspend(dev);
5354
5355         return 0;
5356 }
5357
5358 static int rtl8169_runtime_resume(struct device *device)
5359 {
5360         struct pci_dev *pdev = to_pci_dev(device);
5361         struct net_device *dev = pci_get_drvdata(pdev);
5362         struct rtl8169_private *tp = netdev_priv(dev);
5363
5364         if (!tp->TxDescArray)
5365                 return 0;
5366
5367         spin_lock_irq(&tp->lock);
5368         __rtl8169_set_wol(tp, tp->saved_wolopts);
5369         tp->saved_wolopts = 0;
5370         spin_unlock_irq(&tp->lock);
5371
5372         rtl8169_init_phy(dev, tp);
5373
5374         __rtl8169_resume(dev);
5375
5376         return 0;
5377 }
5378
5379 static int rtl8169_runtime_idle(struct device *device)
5380 {
5381         struct pci_dev *pdev = to_pci_dev(device);
5382         struct net_device *dev = pci_get_drvdata(pdev);
5383         struct rtl8169_private *tp = netdev_priv(dev);
5384
5385         return tp->TxDescArray ? -EBUSY : 0;
5386 }
5387
5388 static const struct dev_pm_ops rtl8169_pm_ops = {
5389         .suspend                = rtl8169_suspend,
5390         .resume                 = rtl8169_resume,
5391         .freeze                 = rtl8169_suspend,
5392         .thaw                   = rtl8169_resume,
5393         .poweroff               = rtl8169_suspend,
5394         .restore                = rtl8169_resume,
5395         .runtime_suspend        = rtl8169_runtime_suspend,
5396         .runtime_resume         = rtl8169_runtime_resume,
5397         .runtime_idle           = rtl8169_runtime_idle,
5398 };
5399
5400 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5401
5402 #else /* !CONFIG_PM */
5403
5404 #define RTL8169_PM_OPS  NULL
5405
5406 #endif /* !CONFIG_PM */
5407
5408 static void rtl_shutdown(struct pci_dev *pdev)
5409 {
5410         struct net_device *dev = pci_get_drvdata(pdev);
5411         struct rtl8169_private *tp = netdev_priv(dev);
5412         void __iomem *ioaddr = tp->mmio_addr;
5413
5414         rtl8169_net_suspend(dev);
5415
5416         /* Restore original MAC address */
5417         rtl_rar_set(tp, dev->perm_addr);
5418
5419         spin_lock_irq(&tp->lock);
5420
5421         rtl8169_asic_down(ioaddr);
5422
5423         spin_unlock_irq(&tp->lock);
5424
5425         if (system_state == SYSTEM_POWER_OFF) {
5426                 /* WoL fails with some 8168 when the receiver is disabled. */
5427                 if (tp->features & RTL_FEATURE_WOL) {
5428                         pci_clear_master(pdev);
5429
5430                         RTL_W8(ChipCmd, CmdRxEnb);
5431                         /* PCI commit */
5432                         RTL_R8(ChipCmd);
5433                 }
5434
5435                 pci_wake_from_d3(pdev, true);
5436                 pci_set_power_state(pdev, PCI_D3hot);
5437         }
5438 }
5439
5440 static struct pci_driver rtl8169_pci_driver = {
5441         .name           = MODULENAME,
5442         .id_table       = rtl8169_pci_tbl,
5443         .probe          = rtl8169_init_one,
5444         .remove         = __devexit_p(rtl8169_remove_one),
5445         .shutdown       = rtl_shutdown,
5446         .driver.pm      = RTL8169_PM_OPS,
5447 };
5448
5449 static int __init rtl8169_init_module(void)
5450 {
5451         return pci_register_driver(&rtl8169_pci_driver);
5452 }
5453
5454 static void __exit rtl8169_cleanup_module(void)
5455 {
5456         pci_unregister_driver(&rtl8169_pci_driver);
5457 }
5458
5459 module_init(rtl8169_init_module);
5460 module_exit(rtl8169_cleanup_module);