r8169: rtl_csi_access_enable rename.
[linux-2.6.git] / drivers / net / r8169.c
1 /*
2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3  *
4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6  * Copyright (c) a lot of people too. Please respect their work.
7  *
8  * See MAINTAINERS file for support contact information.
9  */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28
29 #include <asm/system.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32
33 #define RTL8169_VERSION "2.3LK-NAPI"
34 #define MODULENAME "r8169"
35 #define PFX MODULENAME ": "
36
37 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
38 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
39
40 #ifdef RTL8169_DEBUG
41 #define assert(expr) \
42         if (!(expr)) {                                  \
43                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
44                 #expr,__FILE__,__func__,__LINE__);              \
45         }
46 #define dprintk(fmt, args...) \
47         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
48 #else
49 #define assert(expr) do {} while (0)
50 #define dprintk(fmt, args...)   do {} while (0)
51 #endif /* RTL8169_DEBUG */
52
53 #define R8169_MSG_DEFAULT \
54         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
55
56 #define TX_BUFFS_AVAIL(tp) \
57         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
58
59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
60    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
61 static const int multicast_filter_limit = 32;
62
63 /* MAC address length */
64 #define MAC_ADDR_LEN    6
65
66 #define MAX_READ_REQUEST_SHIFT  12
67 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
68 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
69 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
70 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
72
73 #define R8169_REGS_SIZE         256
74 #define R8169_NAPI_WEIGHT       64
75 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
80
81 #define RTL8169_TX_TIMEOUT      (6*HZ)
82 #define RTL8169_PHY_TIMEOUT     (10*HZ)
83
84 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
85 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
86 #define RTL_EEPROM_SIG_ADDR     0x0000
87
88 /* write/read MMIO register */
89 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
90 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
91 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
92 #define RTL_R8(reg)             readb (ioaddr + (reg))
93 #define RTL_R16(reg)            readw (ioaddr + (reg))
94 #define RTL_R32(reg)            readl (ioaddr + (reg))
95
96 enum mac_version {
97         RTL_GIGA_MAC_NONE   = 0x00,
98         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
99         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
100         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
101         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
102         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
103         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
104         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
105         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
106         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
107         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
108         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
109         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
110         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
111         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
112         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
113         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
114         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
115         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
116         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
117         RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
118         RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
119         RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
120         RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
121         RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
122         RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
123         RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
124         RTL_GIGA_MAC_VER_27 = 0x1b  // 8168DP
125 };
126
127 #define _R(NAME,MAC,MASK) \
128         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
129
130 static const struct {
131         const char *name;
132         u8 mac_version;
133         u32 RxConfigMask;       /* Clears the bits supported by this chip */
134 } rtl_chip_info[] = {
135         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
136         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
137         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
138         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
139         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
140         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
141         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
142         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
143         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
144         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
145         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
146         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
147         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
148         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
149         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
150         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
151         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
152         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
153         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
154         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
155         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
156         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
157         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
158         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
159         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
160         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
161         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_27, 0xff7e1880)  // PCI-E
162 };
163 #undef _R
164
165 enum cfg_version {
166         RTL_CFG_0 = 0x00,
167         RTL_CFG_1,
168         RTL_CFG_2
169 };
170
171 static void rtl_hw_start_8169(struct net_device *);
172 static void rtl_hw_start_8168(struct net_device *);
173 static void rtl_hw_start_8101(struct net_device *);
174
175 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
176         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
177         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
178         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
179         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
180         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
181         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
182         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
183         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
184         { PCI_VENDOR_ID_LINKSYS,                0x1032,
185                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
186         { 0x0001,                               0x8168,
187                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
188         {0,},
189 };
190
191 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
192
193 static int rx_buf_sz = 16383;
194 static int use_dac;
195 static struct {
196         u32 msg_enable;
197 } debug = { -1 };
198
199 enum rtl_registers {
200         MAC0            = 0,    /* Ethernet hardware address. */
201         MAC4            = 4,
202         MAR0            = 8,    /* Multicast filter. */
203         CounterAddrLow          = 0x10,
204         CounterAddrHigh         = 0x14,
205         TxDescStartAddrLow      = 0x20,
206         TxDescStartAddrHigh     = 0x24,
207         TxHDescStartAddrLow     = 0x28,
208         TxHDescStartAddrHigh    = 0x2c,
209         FLASH           = 0x30,
210         ERSR            = 0x36,
211         ChipCmd         = 0x37,
212         TxPoll          = 0x38,
213         IntrMask        = 0x3c,
214         IntrStatus      = 0x3e,
215         TxConfig        = 0x40,
216         RxConfig        = 0x44,
217         RxMissed        = 0x4c,
218         Cfg9346         = 0x50,
219         Config0         = 0x51,
220         Config1         = 0x52,
221         Config2         = 0x53,
222         Config3         = 0x54,
223         Config4         = 0x55,
224         Config5         = 0x56,
225         MultiIntr       = 0x5c,
226         PHYAR           = 0x60,
227         PHYstatus       = 0x6c,
228         RxMaxSize       = 0xda,
229         CPlusCmd        = 0xe0,
230         IntrMitigate    = 0xe2,
231         RxDescAddrLow   = 0xe4,
232         RxDescAddrHigh  = 0xe8,
233         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
234
235 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
236
237         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
238
239 #define TxPacketMax     (8064 >> 7)
240
241         FuncEvent       = 0xf0,
242         FuncEventMask   = 0xf4,
243         FuncPresetState = 0xf8,
244         FuncForceEvent  = 0xfc,
245 };
246
247 enum rtl8110_registers {
248         TBICSR                  = 0x64,
249         TBI_ANAR                = 0x68,
250         TBI_LPAR                = 0x6a,
251 };
252
253 enum rtl8168_8101_registers {
254         CSIDR                   = 0x64,
255         CSIAR                   = 0x68,
256 #define CSIAR_FLAG                      0x80000000
257 #define CSIAR_WRITE_CMD                 0x80000000
258 #define CSIAR_BYTE_ENABLE               0x0f
259 #define CSIAR_BYTE_ENABLE_SHIFT         12
260 #define CSIAR_ADDR_MASK                 0x0fff
261         PMCH                    = 0x6f,
262         EPHYAR                  = 0x80,
263 #define EPHYAR_FLAG                     0x80000000
264 #define EPHYAR_WRITE_CMD                0x80000000
265 #define EPHYAR_REG_MASK                 0x1f
266 #define EPHYAR_REG_SHIFT                16
267 #define EPHYAR_DATA_MASK                0xffff
268         DBG_REG                 = 0xd1,
269 #define FIX_NAK_1                       (1 << 4)
270 #define FIX_NAK_2                       (1 << 3)
271         EFUSEAR                 = 0xdc,
272 #define EFUSEAR_FLAG                    0x80000000
273 #define EFUSEAR_WRITE_CMD               0x80000000
274 #define EFUSEAR_READ_CMD                0x00000000
275 #define EFUSEAR_REG_MASK                0x03ff
276 #define EFUSEAR_REG_SHIFT               8
277 #define EFUSEAR_DATA_MASK               0xff
278 };
279
280 enum rtl8168_registers {
281         ERIDR                   = 0x70,
282         ERIAR                   = 0x74,
283 #define ERIAR_FLAG                      0x80000000
284 #define ERIAR_WRITE_CMD                 0x80000000
285 #define ERIAR_READ_CMD                  0x00000000
286 #define ERIAR_ADDR_BYTE_ALIGN           4
287 #define ERIAR_EXGMAC                    0
288 #define ERIAR_MSIX                      1
289 #define ERIAR_ASF                       2
290 #define ERIAR_TYPE_SHIFT                16
291 #define ERIAR_BYTEEN                    0x0f
292 #define ERIAR_BYTEEN_SHIFT              12
293         EPHY_RXER_NUM           = 0x7c,
294         OCPDR                   = 0xb0, /* OCP GPHY access */
295 #define OCPDR_WRITE_CMD                 0x80000000
296 #define OCPDR_READ_CMD                  0x00000000
297 #define OCPDR_REG_MASK                  0x7f
298 #define OCPDR_GPHY_REG_SHIFT            16
299 #define OCPDR_DATA_MASK                 0xffff
300         OCPAR                   = 0xb4,
301 #define OCPAR_FLAG                      0x80000000
302 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
303 #define OCPAR_GPHY_READ_CMD             0x0000f060
304 };
305
306 enum rtl_register_content {
307         /* InterruptStatusBits */
308         SYSErr          = 0x8000,
309         PCSTimeout      = 0x4000,
310         SWInt           = 0x0100,
311         TxDescUnavail   = 0x0080,
312         RxFIFOOver      = 0x0040,
313         LinkChg         = 0x0020,
314         RxOverflow      = 0x0010,
315         TxErr           = 0x0008,
316         TxOK            = 0x0004,
317         RxErr           = 0x0002,
318         RxOK            = 0x0001,
319
320         /* RxStatusDesc */
321         RxFOVF  = (1 << 23),
322         RxRWT   = (1 << 22),
323         RxRES   = (1 << 21),
324         RxRUNT  = (1 << 20),
325         RxCRC   = (1 << 19),
326
327         /* ChipCmdBits */
328         CmdReset        = 0x10,
329         CmdRxEnb        = 0x08,
330         CmdTxEnb        = 0x04,
331         RxBufEmpty      = 0x01,
332
333         /* TXPoll register p.5 */
334         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
335         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
336         FSWInt          = 0x01,         /* Forced software interrupt */
337
338         /* Cfg9346Bits */
339         Cfg9346_Lock    = 0x00,
340         Cfg9346_Unlock  = 0xc0,
341
342         /* rx_mode_bits */
343         AcceptErr       = 0x20,
344         AcceptRunt      = 0x10,
345         AcceptBroadcast = 0x08,
346         AcceptMulticast = 0x04,
347         AcceptMyPhys    = 0x02,
348         AcceptAllPhys   = 0x01,
349
350         /* RxConfigBits */
351         RxCfgFIFOShift  = 13,
352         RxCfgDMAShift   =  8,
353
354         /* TxConfigBits */
355         TxInterFrameGapShift = 24,
356         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
357
358         /* Config1 register p.24 */
359         LEDS1           = (1 << 7),
360         LEDS0           = (1 << 6),
361         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
362         Speed_down      = (1 << 4),
363         MEMMAP          = (1 << 3),
364         IOMAP           = (1 << 2),
365         VPD             = (1 << 1),
366         PMEnable        = (1 << 0),     /* Power Management Enable */
367
368         /* Config2 register p. 25 */
369         PCI_Clock_66MHz = 0x01,
370         PCI_Clock_33MHz = 0x00,
371
372         /* Config3 register p.25 */
373         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
374         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
375         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
376
377         /* Config5 register p.27 */
378         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
379         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
380         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
381         LanWake         = (1 << 1),     /* LanWake enable/disable */
382         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
383
384         /* TBICSR p.28 */
385         TBIReset        = 0x80000000,
386         TBILoopback     = 0x40000000,
387         TBINwEnable     = 0x20000000,
388         TBINwRestart    = 0x10000000,
389         TBILinkOk       = 0x02000000,
390         TBINwComplete   = 0x01000000,
391
392         /* CPlusCmd p.31 */
393         EnableBist      = (1 << 15),    // 8168 8101
394         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
395         Normal_mode     = (1 << 13),    // unused
396         Force_half_dup  = (1 << 12),    // 8168 8101
397         Force_rxflow_en = (1 << 11),    // 8168 8101
398         Force_txflow_en = (1 << 10),    // 8168 8101
399         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
400         ASF             = (1 << 8),     // 8168 8101
401         PktCntrDisable  = (1 << 7),     // 8168 8101
402         Mac_dbgo_sel    = 0x001c,       // 8168
403         RxVlan          = (1 << 6),
404         RxChkSum        = (1 << 5),
405         PCIDAC          = (1 << 4),
406         PCIMulRW        = (1 << 3),
407         INTT_0          = 0x0000,       // 8168
408         INTT_1          = 0x0001,       // 8168
409         INTT_2          = 0x0002,       // 8168
410         INTT_3          = 0x0003,       // 8168
411
412         /* rtl8169_PHYstatus */
413         TBI_Enable      = 0x80,
414         TxFlowCtrl      = 0x40,
415         RxFlowCtrl      = 0x20,
416         _1000bpsF       = 0x10,
417         _100bps         = 0x08,
418         _10bps          = 0x04,
419         LinkStatus      = 0x02,
420         FullDup         = 0x01,
421
422         /* _TBICSRBit */
423         TBILinkOK       = 0x02000000,
424
425         /* DumpCounterCommand */
426         CounterDump     = 0x8,
427 };
428
429 enum desc_status_bit {
430         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
431         RingEnd         = (1 << 30), /* End of descriptor ring */
432         FirstFrag       = (1 << 29), /* First segment of a packet */
433         LastFrag        = (1 << 28), /* Final segment of a packet */
434
435         /* Tx private */
436         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
437         MSSShift        = 16,        /* MSS value position */
438         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
439         IPCS            = (1 << 18), /* Calculate IP checksum */
440         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
441         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
442         TxVlanTag       = (1 << 17), /* Add VLAN tag */
443
444         /* Rx private */
445         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
446         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
447
448 #define RxProtoUDP      (PID1)
449 #define RxProtoTCP      (PID0)
450 #define RxProtoIP       (PID1 | PID0)
451 #define RxProtoMask     RxProtoIP
452
453         IPFail          = (1 << 16), /* IP checksum failed */
454         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
455         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
456         RxVlanTag       = (1 << 16), /* VLAN tag available */
457 };
458
459 #define RsvdMask        0x3fffc000
460
461 struct TxDesc {
462         __le32 opts1;
463         __le32 opts2;
464         __le64 addr;
465 };
466
467 struct RxDesc {
468         __le32 opts1;
469         __le32 opts2;
470         __le64 addr;
471 };
472
473 struct ring_info {
474         struct sk_buff  *skb;
475         u32             len;
476         u8              __pad[sizeof(void *) - sizeof(u32)];
477 };
478
479 enum features {
480         RTL_FEATURE_WOL         = (1 << 0),
481         RTL_FEATURE_MSI         = (1 << 1),
482         RTL_FEATURE_GMII        = (1 << 2),
483 };
484
485 struct rtl8169_counters {
486         __le64  tx_packets;
487         __le64  rx_packets;
488         __le64  tx_errors;
489         __le32  rx_errors;
490         __le16  rx_missed;
491         __le16  align_errors;
492         __le32  tx_one_collision;
493         __le32  tx_multi_collision;
494         __le64  rx_unicast;
495         __le64  rx_broadcast;
496         __le32  rx_multicast;
497         __le16  tx_aborted;
498         __le16  tx_underun;
499 };
500
501 struct rtl8169_private {
502         void __iomem *mmio_addr;        /* memory map physical address */
503         struct pci_dev *pci_dev;        /* Index of PCI device */
504         struct net_device *dev;
505         struct napi_struct napi;
506         spinlock_t lock;                /* spin lock flag */
507         u32 msg_enable;
508         int chipset;
509         int mac_version;
510         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
511         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
512         u32 dirty_rx;
513         u32 dirty_tx;
514         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
515         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
516         dma_addr_t TxPhyAddr;
517         dma_addr_t RxPhyAddr;
518         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
519         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
520         struct timer_list timer;
521         u16 cp_cmd;
522         u16 intr_event;
523         u16 napi_event;
524         u16 intr_mask;
525         int phy_1000_ctrl_reg;
526 #ifdef CONFIG_R8169_VLAN
527         struct vlan_group *vlgrp;
528 #endif
529
530         struct mdio_ops {
531                 void (*write)(void __iomem *, int, int);
532                 int (*read)(void __iomem *, int);
533         } mdio_ops;
534
535         struct pll_power_ops {
536                 void (*down)(struct rtl8169_private *);
537                 void (*up)(struct rtl8169_private *);
538         } pll_power_ops;
539
540         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
541         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
542         void (*phy_reset_enable)(struct rtl8169_private *tp);
543         void (*hw_start)(struct net_device *);
544         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
545         unsigned int (*link_ok)(void __iomem *);
546         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
547         int pcie_cap;
548         struct delayed_work task;
549         unsigned features;
550
551         struct mii_if_info mii;
552         struct rtl8169_counters counters;
553         u32 saved_wolopts;
554 };
555
556 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
557 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
558 module_param(use_dac, int, 0);
559 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
560 module_param_named(debug, debug.msg_enable, int, 0);
561 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
562 MODULE_LICENSE("GPL");
563 MODULE_VERSION(RTL8169_VERSION);
564 MODULE_FIRMWARE(FIRMWARE_8168D_1);
565 MODULE_FIRMWARE(FIRMWARE_8168D_2);
566
567 static int rtl8169_open(struct net_device *dev);
568 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
569                                       struct net_device *dev);
570 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
571 static int rtl8169_init_ring(struct net_device *dev);
572 static void rtl_hw_start(struct net_device *dev);
573 static int rtl8169_close(struct net_device *dev);
574 static void rtl_set_rx_mode(struct net_device *dev);
575 static void rtl8169_tx_timeout(struct net_device *dev);
576 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
577 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
578                                 void __iomem *, u32 budget);
579 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
580 static void rtl8169_down(struct net_device *dev);
581 static void rtl8169_rx_clear(struct rtl8169_private *tp);
582 static int rtl8169_poll(struct napi_struct *napi, int budget);
583
584 static const unsigned int rtl8169_rx_config =
585         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
586
587 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
588 {
589         void __iomem *ioaddr = tp->mmio_addr;
590         int i;
591
592         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
593         for (i = 0; i < 20; i++) {
594                 udelay(100);
595                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
596                         break;
597         }
598         return RTL_R32(OCPDR);
599 }
600
601 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
602 {
603         void __iomem *ioaddr = tp->mmio_addr;
604         int i;
605
606         RTL_W32(OCPDR, data);
607         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
608         for (i = 0; i < 20; i++) {
609                 udelay(100);
610                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
611                         break;
612         }
613 }
614
615 static void rtl8168_oob_notify(void __iomem *ioaddr, u8 cmd)
616 {
617         int i;
618
619         RTL_W8(ERIDR, cmd);
620         RTL_W32(ERIAR, 0x800010e8);
621         msleep(2);
622         for (i = 0; i < 5; i++) {
623                 udelay(100);
624                 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
625                         break;
626         }
627
628         ocp_write(ioaddr, 0x1, 0x30, 0x00000001);
629 }
630
631 #define OOB_CMD_RESET           0x00
632 #define OOB_CMD_DRIVER_START    0x05
633 #define OOB_CMD_DRIVER_STOP     0x06
634
635 static void rtl8168_driver_start(struct rtl8169_private *tp)
636 {
637         int i;
638
639         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
640
641         for (i = 0; i < 10; i++) {
642                 msleep(10);
643                 if (ocp_read(tp, 0x0f, 0x0010) & 0x00000800)
644                         break;
645         }
646 }
647
648 static void rtl8168_driver_stop(struct rtl8169_private *tp)
649 {
650         int i;
651
652         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
653
654         for (i = 0; i < 10; i++) {
655                 msleep(10);
656                 if ((ocp_read(tp, 0x0f, 0x0010) & 0x00000800) == 0)
657                         break;
658         }
659 }
660
661
662 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
663 {
664         int i;
665
666         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
667
668         for (i = 20; i > 0; i--) {
669                 /*
670                  * Check if the RTL8169 has completed writing to the specified
671                  * MII register.
672                  */
673                 if (!(RTL_R32(PHYAR) & 0x80000000))
674                         break;
675                 udelay(25);
676         }
677         /*
678          * According to hardware specs a 20us delay is required after write
679          * complete indication, but before sending next command.
680          */
681         udelay(20);
682 }
683
684 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
685 {
686         int i, value = -1;
687
688         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
689
690         for (i = 20; i > 0; i--) {
691                 /*
692                  * Check if the RTL8169 has completed retrieving data from
693                  * the specified MII register.
694                  */
695                 if (RTL_R32(PHYAR) & 0x80000000) {
696                         value = RTL_R32(PHYAR) & 0xffff;
697                         break;
698                 }
699                 udelay(25);
700         }
701         /*
702          * According to hardware specs a 20us delay is required after read
703          * complete indication, but before sending next command.
704          */
705         udelay(20);
706
707         return value;
708 }
709
710 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
711 {
712         int i;
713
714         RTL_W32(OCPDR, data |
715                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
716         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
717         RTL_W32(EPHY_RXER_NUM, 0);
718
719         for (i = 0; i < 100; i++) {
720                 mdelay(1);
721                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
722                         break;
723         }
724 }
725
726 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
727 {
728         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
729                 (value & OCPDR_DATA_MASK));
730 }
731
732 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
733 {
734         int i;
735
736         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
737
738         mdelay(1);
739         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
740         RTL_W32(EPHY_RXER_NUM, 0);
741
742         for (i = 0; i < 100; i++) {
743                 mdelay(1);
744                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
745                         break;
746         }
747
748         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
749 }
750
751 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
752 {
753         tp->mdio_ops.write(tp->mmio_addr, location, val);
754 }
755
756 static int rtl_readphy(struct rtl8169_private *tp, int location)
757 {
758         return tp->mdio_ops.read(tp->mmio_addr, location);
759 }
760
761 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
762 {
763         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
764 }
765
766 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
767 {
768         int val;
769
770         val = rtl_readphy(tp, reg_addr);
771         rtl_writephy(tp, reg_addr, (val | p) & ~m);
772 }
773
774 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
775                            int val)
776 {
777         struct rtl8169_private *tp = netdev_priv(dev);
778
779         rtl_writephy(tp, location, val);
780 }
781
782 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
783 {
784         struct rtl8169_private *tp = netdev_priv(dev);
785
786         return rtl_readphy(tp, location);
787 }
788
789 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
790 {
791         unsigned int i;
792
793         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
794                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
795
796         for (i = 0; i < 100; i++) {
797                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
798                         break;
799                 udelay(10);
800         }
801 }
802
803 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
804 {
805         u16 value = 0xffff;
806         unsigned int i;
807
808         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
809
810         for (i = 0; i < 100; i++) {
811                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
812                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
813                         break;
814                 }
815                 udelay(10);
816         }
817
818         return value;
819 }
820
821 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
822 {
823         unsigned int i;
824
825         RTL_W32(CSIDR, value);
826         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
827                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
828
829         for (i = 0; i < 100; i++) {
830                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
831                         break;
832                 udelay(10);
833         }
834 }
835
836 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
837 {
838         u32 value = ~0x00;
839         unsigned int i;
840
841         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
842                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
843
844         for (i = 0; i < 100; i++) {
845                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
846                         value = RTL_R32(CSIDR);
847                         break;
848                 }
849                 udelay(10);
850         }
851
852         return value;
853 }
854
855 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
856 {
857         u8 value = 0xff;
858         unsigned int i;
859
860         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
861
862         for (i = 0; i < 300; i++) {
863                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
864                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
865                         break;
866                 }
867                 udelay(100);
868         }
869
870         return value;
871 }
872
873 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
874 {
875         RTL_W16(IntrMask, 0x0000);
876
877         RTL_W16(IntrStatus, 0xffff);
878 }
879
880 static void rtl8169_asic_down(void __iomem *ioaddr)
881 {
882         RTL_W8(ChipCmd, 0x00);
883         rtl8169_irq_mask_and_ack(ioaddr);
884         RTL_R16(CPlusCmd);
885 }
886
887 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
888 {
889         void __iomem *ioaddr = tp->mmio_addr;
890
891         return RTL_R32(TBICSR) & TBIReset;
892 }
893
894 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
895 {
896         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
897 }
898
899 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
900 {
901         return RTL_R32(TBICSR) & TBILinkOk;
902 }
903
904 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
905 {
906         return RTL_R8(PHYstatus) & LinkStatus;
907 }
908
909 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
910 {
911         void __iomem *ioaddr = tp->mmio_addr;
912
913         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
914 }
915
916 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
917 {
918         unsigned int val;
919
920         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
921         rtl_writephy(tp, MII_BMCR, val & 0xffff);
922 }
923
924 static void __rtl8169_check_link_status(struct net_device *dev,
925                                       struct rtl8169_private *tp,
926                                       void __iomem *ioaddr,
927                                       bool pm)
928 {
929         unsigned long flags;
930
931         spin_lock_irqsave(&tp->lock, flags);
932         if (tp->link_ok(ioaddr)) {
933                 /* This is to cancel a scheduled suspend if there's one. */
934                 if (pm)
935                         pm_request_resume(&tp->pci_dev->dev);
936                 netif_carrier_on(dev);
937                 netif_info(tp, ifup, dev, "link up\n");
938         } else {
939                 netif_carrier_off(dev);
940                 netif_info(tp, ifdown, dev, "link down\n");
941                 if (pm)
942                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
943         }
944         spin_unlock_irqrestore(&tp->lock, flags);
945 }
946
947 static void rtl8169_check_link_status(struct net_device *dev,
948                                       struct rtl8169_private *tp,
949                                       void __iomem *ioaddr)
950 {
951         __rtl8169_check_link_status(dev, tp, ioaddr, false);
952 }
953
954 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
955
956 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
957 {
958         void __iomem *ioaddr = tp->mmio_addr;
959         u8 options;
960         u32 wolopts = 0;
961
962         options = RTL_R8(Config1);
963         if (!(options & PMEnable))
964                 return 0;
965
966         options = RTL_R8(Config3);
967         if (options & LinkUp)
968                 wolopts |= WAKE_PHY;
969         if (options & MagicPacket)
970                 wolopts |= WAKE_MAGIC;
971
972         options = RTL_R8(Config5);
973         if (options & UWF)
974                 wolopts |= WAKE_UCAST;
975         if (options & BWF)
976                 wolopts |= WAKE_BCAST;
977         if (options & MWF)
978                 wolopts |= WAKE_MCAST;
979
980         return wolopts;
981 }
982
983 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
984 {
985         struct rtl8169_private *tp = netdev_priv(dev);
986
987         spin_lock_irq(&tp->lock);
988
989         wol->supported = WAKE_ANY;
990         wol->wolopts = __rtl8169_get_wol(tp);
991
992         spin_unlock_irq(&tp->lock);
993 }
994
995 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
996 {
997         void __iomem *ioaddr = tp->mmio_addr;
998         unsigned int i;
999         static const struct {
1000                 u32 opt;
1001                 u16 reg;
1002                 u8  mask;
1003         } cfg[] = {
1004                 { WAKE_ANY,   Config1, PMEnable },
1005                 { WAKE_PHY,   Config3, LinkUp },
1006                 { WAKE_MAGIC, Config3, MagicPacket },
1007                 { WAKE_UCAST, Config5, UWF },
1008                 { WAKE_BCAST, Config5, BWF },
1009                 { WAKE_MCAST, Config5, MWF },
1010                 { WAKE_ANY,   Config5, LanWake }
1011         };
1012
1013         RTL_W8(Cfg9346, Cfg9346_Unlock);
1014
1015         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1016                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1017                 if (wolopts & cfg[i].opt)
1018                         options |= cfg[i].mask;
1019                 RTL_W8(cfg[i].reg, options);
1020         }
1021
1022         RTL_W8(Cfg9346, Cfg9346_Lock);
1023 }
1024
1025 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1026 {
1027         struct rtl8169_private *tp = netdev_priv(dev);
1028
1029         spin_lock_irq(&tp->lock);
1030
1031         if (wol->wolopts)
1032                 tp->features |= RTL_FEATURE_WOL;
1033         else
1034                 tp->features &= ~RTL_FEATURE_WOL;
1035         __rtl8169_set_wol(tp, wol->wolopts);
1036         spin_unlock_irq(&tp->lock);
1037
1038         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1039
1040         return 0;
1041 }
1042
1043 static void rtl8169_get_drvinfo(struct net_device *dev,
1044                                 struct ethtool_drvinfo *info)
1045 {
1046         struct rtl8169_private *tp = netdev_priv(dev);
1047
1048         strcpy(info->driver, MODULENAME);
1049         strcpy(info->version, RTL8169_VERSION);
1050         strcpy(info->bus_info, pci_name(tp->pci_dev));
1051 }
1052
1053 static int rtl8169_get_regs_len(struct net_device *dev)
1054 {
1055         return R8169_REGS_SIZE;
1056 }
1057
1058 static int rtl8169_set_speed_tbi(struct net_device *dev,
1059                                  u8 autoneg, u16 speed, u8 duplex)
1060 {
1061         struct rtl8169_private *tp = netdev_priv(dev);
1062         void __iomem *ioaddr = tp->mmio_addr;
1063         int ret = 0;
1064         u32 reg;
1065
1066         reg = RTL_R32(TBICSR);
1067         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1068             (duplex == DUPLEX_FULL)) {
1069                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1070         } else if (autoneg == AUTONEG_ENABLE)
1071                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1072         else {
1073                 netif_warn(tp, link, dev,
1074                            "incorrect speed setting refused in TBI mode\n");
1075                 ret = -EOPNOTSUPP;
1076         }
1077
1078         return ret;
1079 }
1080
1081 static int rtl8169_set_speed_xmii(struct net_device *dev,
1082                                   u8 autoneg, u16 speed, u8 duplex)
1083 {
1084         struct rtl8169_private *tp = netdev_priv(dev);
1085         int giga_ctrl, bmcr;
1086
1087         if (autoneg == AUTONEG_ENABLE) {
1088                 int auto_nego;
1089
1090                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1091                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1092                               ADVERTISE_100HALF | ADVERTISE_100FULL);
1093                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1094
1095                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1096                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1097
1098                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1099                 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1100                     (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1101                     (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1102                     (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1103                     (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1104                     (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1105                     (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1106                     (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
1107                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1108                 } else {
1109                         netif_info(tp, link, dev,
1110                                    "PHY does not support 1000Mbps\n");
1111                 }
1112
1113                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1114
1115                 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
1116                     (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
1117                     (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
1118                         /*
1119                          * Wake up the PHY.
1120                          * Vendor specific (0x1f) and reserved (0x0e) MII
1121                          * registers.
1122                          */
1123                         rtl_writephy(tp, 0x1f, 0x0000);
1124                         rtl_writephy(tp, 0x0e, 0x0000);
1125                 }
1126
1127                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1128                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1129         } else {
1130                 giga_ctrl = 0;
1131
1132                 if (speed == SPEED_10)
1133                         bmcr = 0;
1134                 else if (speed == SPEED_100)
1135                         bmcr = BMCR_SPEED100;
1136                 else
1137                         return -EINVAL;
1138
1139                 if (duplex == DUPLEX_FULL)
1140                         bmcr |= BMCR_FULLDPLX;
1141
1142                 rtl_writephy(tp, 0x1f, 0x0000);
1143         }
1144
1145         tp->phy_1000_ctrl_reg = giga_ctrl;
1146
1147         rtl_writephy(tp, MII_BMCR, bmcr);
1148
1149         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1150             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1151                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1152                         rtl_writephy(tp, 0x17, 0x2138);
1153                         rtl_writephy(tp, 0x0e, 0x0260);
1154                 } else {
1155                         rtl_writephy(tp, 0x17, 0x2108);
1156                         rtl_writephy(tp, 0x0e, 0x0000);
1157                 }
1158         }
1159
1160         return 0;
1161 }
1162
1163 static int rtl8169_set_speed(struct net_device *dev,
1164                              u8 autoneg, u16 speed, u8 duplex)
1165 {
1166         struct rtl8169_private *tp = netdev_priv(dev);
1167         int ret;
1168
1169         ret = tp->set_speed(dev, autoneg, speed, duplex);
1170
1171         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1172                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1173
1174         return ret;
1175 }
1176
1177 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1178 {
1179         struct rtl8169_private *tp = netdev_priv(dev);
1180         unsigned long flags;
1181         int ret;
1182
1183         spin_lock_irqsave(&tp->lock, flags);
1184         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1185         spin_unlock_irqrestore(&tp->lock, flags);
1186
1187         return ret;
1188 }
1189
1190 static u32 rtl8169_get_rx_csum(struct net_device *dev)
1191 {
1192         struct rtl8169_private *tp = netdev_priv(dev);
1193
1194         return tp->cp_cmd & RxChkSum;
1195 }
1196
1197 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1198 {
1199         struct rtl8169_private *tp = netdev_priv(dev);
1200         void __iomem *ioaddr = tp->mmio_addr;
1201         unsigned long flags;
1202
1203         spin_lock_irqsave(&tp->lock, flags);
1204
1205         if (data)
1206                 tp->cp_cmd |= RxChkSum;
1207         else
1208                 tp->cp_cmd &= ~RxChkSum;
1209
1210         RTL_W16(CPlusCmd, tp->cp_cmd);
1211         RTL_R16(CPlusCmd);
1212
1213         spin_unlock_irqrestore(&tp->lock, flags);
1214
1215         return 0;
1216 }
1217
1218 #ifdef CONFIG_R8169_VLAN
1219
1220 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1221                                       struct sk_buff *skb)
1222 {
1223         return (vlan_tx_tag_present(skb)) ?
1224                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1225 }
1226
1227 static void rtl8169_vlan_rx_register(struct net_device *dev,
1228                                      struct vlan_group *grp)
1229 {
1230         struct rtl8169_private *tp = netdev_priv(dev);
1231         void __iomem *ioaddr = tp->mmio_addr;
1232         unsigned long flags;
1233
1234         spin_lock_irqsave(&tp->lock, flags);
1235         tp->vlgrp = grp;
1236         /*
1237          * Do not disable RxVlan on 8110SCd.
1238          */
1239         if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1240                 tp->cp_cmd |= RxVlan;
1241         else
1242                 tp->cp_cmd &= ~RxVlan;
1243         RTL_W16(CPlusCmd, tp->cp_cmd);
1244         RTL_R16(CPlusCmd);
1245         spin_unlock_irqrestore(&tp->lock, flags);
1246 }
1247
1248 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1249                                struct sk_buff *skb, int polling)
1250 {
1251         u32 opts2 = le32_to_cpu(desc->opts2);
1252         struct vlan_group *vlgrp = tp->vlgrp;
1253         int ret;
1254
1255         if (vlgrp && (opts2 & RxVlanTag)) {
1256                 u16 vtag = swab16(opts2 & 0xffff);
1257
1258                 if (likely(polling))
1259                         vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1260                 else
1261                         __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1262                 ret = 0;
1263         } else
1264                 ret = -1;
1265         desc->opts2 = 0;
1266         return ret;
1267 }
1268
1269 #else /* !CONFIG_R8169_VLAN */
1270
1271 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1272                                       struct sk_buff *skb)
1273 {
1274         return 0;
1275 }
1276
1277 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1278                                struct sk_buff *skb, int polling)
1279 {
1280         return -1;
1281 }
1282
1283 #endif
1284
1285 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1286 {
1287         struct rtl8169_private *tp = netdev_priv(dev);
1288         void __iomem *ioaddr = tp->mmio_addr;
1289         u32 status;
1290
1291         cmd->supported =
1292                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1293         cmd->port = PORT_FIBRE;
1294         cmd->transceiver = XCVR_INTERNAL;
1295
1296         status = RTL_R32(TBICSR);
1297         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1298         cmd->autoneg = !!(status & TBINwEnable);
1299
1300         cmd->speed = SPEED_1000;
1301         cmd->duplex = DUPLEX_FULL; /* Always set */
1302
1303         return 0;
1304 }
1305
1306 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1307 {
1308         struct rtl8169_private *tp = netdev_priv(dev);
1309
1310         return mii_ethtool_gset(&tp->mii, cmd);
1311 }
1312
1313 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1314 {
1315         struct rtl8169_private *tp = netdev_priv(dev);
1316         unsigned long flags;
1317         int rc;
1318
1319         spin_lock_irqsave(&tp->lock, flags);
1320
1321         rc = tp->get_settings(dev, cmd);
1322
1323         spin_unlock_irqrestore(&tp->lock, flags);
1324         return rc;
1325 }
1326
1327 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1328                              void *p)
1329 {
1330         struct rtl8169_private *tp = netdev_priv(dev);
1331         unsigned long flags;
1332
1333         if (regs->len > R8169_REGS_SIZE)
1334                 regs->len = R8169_REGS_SIZE;
1335
1336         spin_lock_irqsave(&tp->lock, flags);
1337         memcpy_fromio(p, tp->mmio_addr, regs->len);
1338         spin_unlock_irqrestore(&tp->lock, flags);
1339 }
1340
1341 static u32 rtl8169_get_msglevel(struct net_device *dev)
1342 {
1343         struct rtl8169_private *tp = netdev_priv(dev);
1344
1345         return tp->msg_enable;
1346 }
1347
1348 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1349 {
1350         struct rtl8169_private *tp = netdev_priv(dev);
1351
1352         tp->msg_enable = value;
1353 }
1354
1355 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1356         "tx_packets",
1357         "rx_packets",
1358         "tx_errors",
1359         "rx_errors",
1360         "rx_missed",
1361         "align_errors",
1362         "tx_single_collisions",
1363         "tx_multi_collisions",
1364         "unicast",
1365         "broadcast",
1366         "multicast",
1367         "tx_aborted",
1368         "tx_underrun",
1369 };
1370
1371 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1372 {
1373         switch (sset) {
1374         case ETH_SS_STATS:
1375                 return ARRAY_SIZE(rtl8169_gstrings);
1376         default:
1377                 return -EOPNOTSUPP;
1378         }
1379 }
1380
1381 static void rtl8169_update_counters(struct net_device *dev)
1382 {
1383         struct rtl8169_private *tp = netdev_priv(dev);
1384         void __iomem *ioaddr = tp->mmio_addr;
1385         struct rtl8169_counters *counters;
1386         dma_addr_t paddr;
1387         u32 cmd;
1388         int wait = 1000;
1389         struct device *d = &tp->pci_dev->dev;
1390
1391         /*
1392          * Some chips are unable to dump tally counters when the receiver
1393          * is disabled.
1394          */
1395         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1396                 return;
1397
1398         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1399         if (!counters)
1400                 return;
1401
1402         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1403         cmd = (u64)paddr & DMA_BIT_MASK(32);
1404         RTL_W32(CounterAddrLow, cmd);
1405         RTL_W32(CounterAddrLow, cmd | CounterDump);
1406
1407         while (wait--) {
1408                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1409                         /* copy updated counters */
1410                         memcpy(&tp->counters, counters, sizeof(*counters));
1411                         break;
1412                 }
1413                 udelay(10);
1414         }
1415
1416         RTL_W32(CounterAddrLow, 0);
1417         RTL_W32(CounterAddrHigh, 0);
1418
1419         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1420 }
1421
1422 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1423                                       struct ethtool_stats *stats, u64 *data)
1424 {
1425         struct rtl8169_private *tp = netdev_priv(dev);
1426
1427         ASSERT_RTNL();
1428
1429         rtl8169_update_counters(dev);
1430
1431         data[0] = le64_to_cpu(tp->counters.tx_packets);
1432         data[1] = le64_to_cpu(tp->counters.rx_packets);
1433         data[2] = le64_to_cpu(tp->counters.tx_errors);
1434         data[3] = le32_to_cpu(tp->counters.rx_errors);
1435         data[4] = le16_to_cpu(tp->counters.rx_missed);
1436         data[5] = le16_to_cpu(tp->counters.align_errors);
1437         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1438         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1439         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1440         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1441         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1442         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1443         data[12] = le16_to_cpu(tp->counters.tx_underun);
1444 }
1445
1446 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1447 {
1448         switch(stringset) {
1449         case ETH_SS_STATS:
1450                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1451                 break;
1452         }
1453 }
1454
1455 static const struct ethtool_ops rtl8169_ethtool_ops = {
1456         .get_drvinfo            = rtl8169_get_drvinfo,
1457         .get_regs_len           = rtl8169_get_regs_len,
1458         .get_link               = ethtool_op_get_link,
1459         .get_settings           = rtl8169_get_settings,
1460         .set_settings           = rtl8169_set_settings,
1461         .get_msglevel           = rtl8169_get_msglevel,
1462         .set_msglevel           = rtl8169_set_msglevel,
1463         .get_rx_csum            = rtl8169_get_rx_csum,
1464         .set_rx_csum            = rtl8169_set_rx_csum,
1465         .set_tx_csum            = ethtool_op_set_tx_csum,
1466         .set_sg                 = ethtool_op_set_sg,
1467         .set_tso                = ethtool_op_set_tso,
1468         .get_regs               = rtl8169_get_regs,
1469         .get_wol                = rtl8169_get_wol,
1470         .set_wol                = rtl8169_set_wol,
1471         .get_strings            = rtl8169_get_strings,
1472         .get_sset_count         = rtl8169_get_sset_count,
1473         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1474 };
1475
1476 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1477                                     void __iomem *ioaddr)
1478 {
1479         /*
1480          * The driver currently handles the 8168Bf and the 8168Be identically
1481          * but they can be identified more specifically through the test below
1482          * if needed:
1483          *
1484          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1485          *
1486          * Same thing for the 8101Eb and the 8101Ec:
1487          *
1488          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1489          */
1490         static const struct {
1491                 u32 mask;
1492                 u32 val;
1493                 int mac_version;
1494         } mac_info[] = {
1495                 /* 8168D family. */
1496                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1497                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1498                 { 0x7c800000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1499                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1500
1501                 /* 8168C family. */
1502                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1503                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1504                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1505                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1506                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1507                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1508                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1509                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1510                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1511
1512                 /* 8168B family. */
1513                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1514                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1515                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1516                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1517
1518                 /* 8101 family. */
1519                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1520                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1521                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1522                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1523                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1524                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1525                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1526                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1527                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1528                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1529                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1530                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1531                 /* FIXME: where did these entries come from ? -- FR */
1532                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1533                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1534
1535                 /* 8110 family. */
1536                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1537                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1538                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1539                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1540                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1541                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1542
1543                 /* Catch-all */
1544                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1545         }, *p = mac_info;
1546         u32 reg;
1547
1548         reg = RTL_R32(TxConfig);
1549         while ((reg & p->mask) != p->val)
1550                 p++;
1551         tp->mac_version = p->mac_version;
1552 }
1553
1554 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1555 {
1556         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1557 }
1558
1559 struct phy_reg {
1560         u16 reg;
1561         u16 val;
1562 };
1563
1564 static void rtl_writephy_batch(struct rtl8169_private *tp,
1565                                const struct phy_reg *regs, int len)
1566 {
1567         while (len-- > 0) {
1568                 rtl_writephy(tp, regs->reg, regs->val);
1569                 regs++;
1570         }
1571 }
1572
1573 #define PHY_READ                0x00000000
1574 #define PHY_DATA_OR             0x10000000
1575 #define PHY_DATA_AND            0x20000000
1576 #define PHY_BJMPN               0x30000000
1577 #define PHY_READ_EFUSE          0x40000000
1578 #define PHY_READ_MAC_BYTE       0x50000000
1579 #define PHY_WRITE_MAC_BYTE      0x60000000
1580 #define PHY_CLEAR_READCOUNT     0x70000000
1581 #define PHY_WRITE               0x80000000
1582 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1583 #define PHY_COMP_EQ_SKIPN       0xa0000000
1584 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1585 #define PHY_WRITE_PREVIOUS      0xc0000000
1586 #define PHY_SKIPN               0xd0000000
1587 #define PHY_DELAY_MS            0xe0000000
1588 #define PHY_WRITE_ERI_WORD      0xf0000000
1589
1590 static void
1591 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1592 {
1593         __le32 *phytable = (__le32 *)fw->data;
1594         struct net_device *dev = tp->dev;
1595         size_t i;
1596
1597         if (fw->size % sizeof(*phytable)) {
1598                 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1599                 return;
1600         }
1601
1602         for (i = 0; i < fw->size / sizeof(*phytable); i++) {
1603                 u32 action = le32_to_cpu(phytable[i]);
1604
1605                 if (!action)
1606                         break;
1607
1608                 if ((action & 0xf0000000) != PHY_WRITE) {
1609                         netif_err(tp, probe, dev,
1610                                   "unknown action 0x%08x\n", action);
1611                         return;
1612                 }
1613         }
1614
1615         while (i-- != 0) {
1616                 u32 action = le32_to_cpu(*phytable);
1617                 u32 data = action & 0x0000ffff;
1618                 u32 reg = (action & 0x0fff0000) >> 16;
1619
1620                 switch(action & 0xf0000000) {
1621                 case PHY_WRITE:
1622                         rtl_writephy(tp, reg, data);
1623                         phytable++;
1624                         break;
1625                 default:
1626                         BUG();
1627                 }
1628         }
1629 }
1630
1631 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1632 {
1633         static const struct phy_reg phy_reg_init[] = {
1634                 { 0x1f, 0x0001 },
1635                 { 0x06, 0x006e },
1636                 { 0x08, 0x0708 },
1637                 { 0x15, 0x4000 },
1638                 { 0x18, 0x65c7 },
1639
1640                 { 0x1f, 0x0001 },
1641                 { 0x03, 0x00a1 },
1642                 { 0x02, 0x0008 },
1643                 { 0x01, 0x0120 },
1644                 { 0x00, 0x1000 },
1645                 { 0x04, 0x0800 },
1646                 { 0x04, 0x0000 },
1647
1648                 { 0x03, 0xff41 },
1649                 { 0x02, 0xdf60 },
1650                 { 0x01, 0x0140 },
1651                 { 0x00, 0x0077 },
1652                 { 0x04, 0x7800 },
1653                 { 0x04, 0x7000 },
1654
1655                 { 0x03, 0x802f },
1656                 { 0x02, 0x4f02 },
1657                 { 0x01, 0x0409 },
1658                 { 0x00, 0xf0f9 },
1659                 { 0x04, 0x9800 },
1660                 { 0x04, 0x9000 },
1661
1662                 { 0x03, 0xdf01 },
1663                 { 0x02, 0xdf20 },
1664                 { 0x01, 0xff95 },
1665                 { 0x00, 0xba00 },
1666                 { 0x04, 0xa800 },
1667                 { 0x04, 0xa000 },
1668
1669                 { 0x03, 0xff41 },
1670                 { 0x02, 0xdf20 },
1671                 { 0x01, 0x0140 },
1672                 { 0x00, 0x00bb },
1673                 { 0x04, 0xb800 },
1674                 { 0x04, 0xb000 },
1675
1676                 { 0x03, 0xdf41 },
1677                 { 0x02, 0xdc60 },
1678                 { 0x01, 0x6340 },
1679                 { 0x00, 0x007d },
1680                 { 0x04, 0xd800 },
1681                 { 0x04, 0xd000 },
1682
1683                 { 0x03, 0xdf01 },
1684                 { 0x02, 0xdf20 },
1685                 { 0x01, 0x100a },
1686                 { 0x00, 0xa0ff },
1687                 { 0x04, 0xf800 },
1688                 { 0x04, 0xf000 },
1689
1690                 { 0x1f, 0x0000 },
1691                 { 0x0b, 0x0000 },
1692                 { 0x00, 0x9200 }
1693         };
1694
1695         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1696 }
1697
1698 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1699 {
1700         static const struct phy_reg phy_reg_init[] = {
1701                 { 0x1f, 0x0002 },
1702                 { 0x01, 0x90d0 },
1703                 { 0x1f, 0x0000 }
1704         };
1705
1706         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1707 }
1708
1709 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1710 {
1711         struct pci_dev *pdev = tp->pci_dev;
1712         u16 vendor_id, device_id;
1713
1714         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1715         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1716
1717         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1718                 return;
1719
1720         rtl_writephy(tp, 0x1f, 0x0001);
1721         rtl_writephy(tp, 0x10, 0xf01b);
1722         rtl_writephy(tp, 0x1f, 0x0000);
1723 }
1724
1725 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
1726 {
1727         static const struct phy_reg phy_reg_init[] = {
1728                 { 0x1f, 0x0001 },
1729                 { 0x04, 0x0000 },
1730                 { 0x03, 0x00a1 },
1731                 { 0x02, 0x0008 },
1732                 { 0x01, 0x0120 },
1733                 { 0x00, 0x1000 },
1734                 { 0x04, 0x0800 },
1735                 { 0x04, 0x9000 },
1736                 { 0x03, 0x802f },
1737                 { 0x02, 0x4f02 },
1738                 { 0x01, 0x0409 },
1739                 { 0x00, 0xf099 },
1740                 { 0x04, 0x9800 },
1741                 { 0x04, 0xa000 },
1742                 { 0x03, 0xdf01 },
1743                 { 0x02, 0xdf20 },
1744                 { 0x01, 0xff95 },
1745                 { 0x00, 0xba00 },
1746                 { 0x04, 0xa800 },
1747                 { 0x04, 0xf000 },
1748                 { 0x03, 0xdf01 },
1749                 { 0x02, 0xdf20 },
1750                 { 0x01, 0x101a },
1751                 { 0x00, 0xa0ff },
1752                 { 0x04, 0xf800 },
1753                 { 0x04, 0x0000 },
1754                 { 0x1f, 0x0000 },
1755
1756                 { 0x1f, 0x0001 },
1757                 { 0x10, 0xf41b },
1758                 { 0x14, 0xfb54 },
1759                 { 0x18, 0xf5c7 },
1760                 { 0x1f, 0x0000 },
1761
1762                 { 0x1f, 0x0001 },
1763                 { 0x17, 0x0cc0 },
1764                 { 0x1f, 0x0000 }
1765         };
1766
1767         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1768
1769         rtl8169scd_hw_phy_config_quirk(tp);
1770 }
1771
1772 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
1773 {
1774         static const struct phy_reg phy_reg_init[] = {
1775                 { 0x1f, 0x0001 },
1776                 { 0x04, 0x0000 },
1777                 { 0x03, 0x00a1 },
1778                 { 0x02, 0x0008 },
1779                 { 0x01, 0x0120 },
1780                 { 0x00, 0x1000 },
1781                 { 0x04, 0x0800 },
1782                 { 0x04, 0x9000 },
1783                 { 0x03, 0x802f },
1784                 { 0x02, 0x4f02 },
1785                 { 0x01, 0x0409 },
1786                 { 0x00, 0xf099 },
1787                 { 0x04, 0x9800 },
1788                 { 0x04, 0xa000 },
1789                 { 0x03, 0xdf01 },
1790                 { 0x02, 0xdf20 },
1791                 { 0x01, 0xff95 },
1792                 { 0x00, 0xba00 },
1793                 { 0x04, 0xa800 },
1794                 { 0x04, 0xf000 },
1795                 { 0x03, 0xdf01 },
1796                 { 0x02, 0xdf20 },
1797                 { 0x01, 0x101a },
1798                 { 0x00, 0xa0ff },
1799                 { 0x04, 0xf800 },
1800                 { 0x04, 0x0000 },
1801                 { 0x1f, 0x0000 },
1802
1803                 { 0x1f, 0x0001 },
1804                 { 0x0b, 0x8480 },
1805                 { 0x1f, 0x0000 },
1806
1807                 { 0x1f, 0x0001 },
1808                 { 0x18, 0x67c7 },
1809                 { 0x04, 0x2000 },
1810                 { 0x03, 0x002f },
1811                 { 0x02, 0x4360 },
1812                 { 0x01, 0x0109 },
1813                 { 0x00, 0x3022 },
1814                 { 0x04, 0x2800 },
1815                 { 0x1f, 0x0000 },
1816
1817                 { 0x1f, 0x0001 },
1818                 { 0x17, 0x0cc0 },
1819                 { 0x1f, 0x0000 }
1820         };
1821
1822         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1823 }
1824
1825 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
1826 {
1827         static const struct phy_reg phy_reg_init[] = {
1828                 { 0x10, 0xf41b },
1829                 { 0x1f, 0x0000 }
1830         };
1831
1832         rtl_writephy(tp, 0x1f, 0x0001);
1833         rtl_patchphy(tp, 0x16, 1 << 0);
1834
1835         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1836 }
1837
1838 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
1839 {
1840         static const struct phy_reg phy_reg_init[] = {
1841                 { 0x1f, 0x0001 },
1842                 { 0x10, 0xf41b },
1843                 { 0x1f, 0x0000 }
1844         };
1845
1846         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1847 }
1848
1849 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
1850 {
1851         static const struct phy_reg phy_reg_init[] = {
1852                 { 0x1f, 0x0000 },
1853                 { 0x1d, 0x0f00 },
1854                 { 0x1f, 0x0002 },
1855                 { 0x0c, 0x1ec8 },
1856                 { 0x1f, 0x0000 }
1857         };
1858
1859         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1860 }
1861
1862 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
1863 {
1864         static const struct phy_reg phy_reg_init[] = {
1865                 { 0x1f, 0x0001 },
1866                 { 0x1d, 0x3d98 },
1867                 { 0x1f, 0x0000 }
1868         };
1869
1870         rtl_writephy(tp, 0x1f, 0x0000);
1871         rtl_patchphy(tp, 0x14, 1 << 5);
1872         rtl_patchphy(tp, 0x0d, 1 << 5);
1873
1874         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1875 }
1876
1877 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
1878 {
1879         static const struct phy_reg phy_reg_init[] = {
1880                 { 0x1f, 0x0001 },
1881                 { 0x12, 0x2300 },
1882                 { 0x1f, 0x0002 },
1883                 { 0x00, 0x88d4 },
1884                 { 0x01, 0x82b1 },
1885                 { 0x03, 0x7002 },
1886                 { 0x08, 0x9e30 },
1887                 { 0x09, 0x01f0 },
1888                 { 0x0a, 0x5500 },
1889                 { 0x0c, 0x00c8 },
1890                 { 0x1f, 0x0003 },
1891                 { 0x12, 0xc096 },
1892                 { 0x16, 0x000a },
1893                 { 0x1f, 0x0000 },
1894                 { 0x1f, 0x0000 },
1895                 { 0x09, 0x2000 },
1896                 { 0x09, 0x0000 }
1897         };
1898
1899         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1900
1901         rtl_patchphy(tp, 0x14, 1 << 5);
1902         rtl_patchphy(tp, 0x0d, 1 << 5);
1903         rtl_writephy(tp, 0x1f, 0x0000);
1904 }
1905
1906 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
1907 {
1908         static const struct phy_reg phy_reg_init[] = {
1909                 { 0x1f, 0x0001 },
1910                 { 0x12, 0x2300 },
1911                 { 0x03, 0x802f },
1912                 { 0x02, 0x4f02 },
1913                 { 0x01, 0x0409 },
1914                 { 0x00, 0xf099 },
1915                 { 0x04, 0x9800 },
1916                 { 0x04, 0x9000 },
1917                 { 0x1d, 0x3d98 },
1918                 { 0x1f, 0x0002 },
1919                 { 0x0c, 0x7eb8 },
1920                 { 0x06, 0x0761 },
1921                 { 0x1f, 0x0003 },
1922                 { 0x16, 0x0f0a },
1923                 { 0x1f, 0x0000 }
1924         };
1925
1926         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1927
1928         rtl_patchphy(tp, 0x16, 1 << 0);
1929         rtl_patchphy(tp, 0x14, 1 << 5);
1930         rtl_patchphy(tp, 0x0d, 1 << 5);
1931         rtl_writephy(tp, 0x1f, 0x0000);
1932 }
1933
1934 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
1935 {
1936         static const struct phy_reg phy_reg_init[] = {
1937                 { 0x1f, 0x0001 },
1938                 { 0x12, 0x2300 },
1939                 { 0x1d, 0x3d98 },
1940                 { 0x1f, 0x0002 },
1941                 { 0x0c, 0x7eb8 },
1942                 { 0x06, 0x5461 },
1943                 { 0x1f, 0x0003 },
1944                 { 0x16, 0x0f0a },
1945                 { 0x1f, 0x0000 }
1946         };
1947
1948         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1949
1950         rtl_patchphy(tp, 0x16, 1 << 0);
1951         rtl_patchphy(tp, 0x14, 1 << 5);
1952         rtl_patchphy(tp, 0x0d, 1 << 5);
1953         rtl_writephy(tp, 0x1f, 0x0000);
1954 }
1955
1956 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
1957 {
1958         rtl8168c_3_hw_phy_config(tp);
1959 }
1960
1961 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
1962 {
1963         static const struct phy_reg phy_reg_init_0[] = {
1964                 /* Channel Estimation */
1965                 { 0x1f, 0x0001 },
1966                 { 0x06, 0x4064 },
1967                 { 0x07, 0x2863 },
1968                 { 0x08, 0x059c },
1969                 { 0x09, 0x26b4 },
1970                 { 0x0a, 0x6a19 },
1971                 { 0x0b, 0xdcc8 },
1972                 { 0x10, 0xf06d },
1973                 { 0x14, 0x7f68 },
1974                 { 0x18, 0x7fd9 },
1975                 { 0x1c, 0xf0ff },
1976                 { 0x1d, 0x3d9c },
1977                 { 0x1f, 0x0003 },
1978                 { 0x12, 0xf49f },
1979                 { 0x13, 0x070b },
1980                 { 0x1a, 0x05ad },
1981                 { 0x14, 0x94c0 },
1982
1983                 /*
1984                  * Tx Error Issue
1985                  * enhance line driver power
1986                  */
1987                 { 0x1f, 0x0002 },
1988                 { 0x06, 0x5561 },
1989                 { 0x1f, 0x0005 },
1990                 { 0x05, 0x8332 },
1991                 { 0x06, 0x5561 },
1992
1993                 /*
1994                  * Can not link to 1Gbps with bad cable
1995                  * Decrease SNR threshold form 21.07dB to 19.04dB
1996                  */
1997                 { 0x1f, 0x0001 },
1998                 { 0x17, 0x0cc0 },
1999
2000                 { 0x1f, 0x0000 },
2001                 { 0x0d, 0xf880 }
2002         };
2003         void __iomem *ioaddr = tp->mmio_addr;
2004         const struct firmware *fw;
2005
2006         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2007
2008         /*
2009          * Rx Error Issue
2010          * Fine Tune Switching regulator parameter
2011          */
2012         rtl_writephy(tp, 0x1f, 0x0002);
2013         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2014         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2015
2016         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2017                 static const struct phy_reg phy_reg_init[] = {
2018                         { 0x1f, 0x0002 },
2019                         { 0x05, 0x669a },
2020                         { 0x1f, 0x0005 },
2021                         { 0x05, 0x8330 },
2022                         { 0x06, 0x669a },
2023                         { 0x1f, 0x0002 }
2024                 };
2025                 int val;
2026
2027                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2028
2029                 val = rtl_readphy(tp, 0x0d);
2030
2031                 if ((val & 0x00ff) != 0x006c) {
2032                         static const u32 set[] = {
2033                                 0x0065, 0x0066, 0x0067, 0x0068,
2034                                 0x0069, 0x006a, 0x006b, 0x006c
2035                         };
2036                         int i;
2037
2038                         rtl_writephy(tp, 0x1f, 0x0002);
2039
2040                         val &= 0xff00;
2041                         for (i = 0; i < ARRAY_SIZE(set); i++)
2042                                 rtl_writephy(tp, 0x0d, val | set[i]);
2043                 }
2044         } else {
2045                 static const struct phy_reg phy_reg_init[] = {
2046                         { 0x1f, 0x0002 },
2047                         { 0x05, 0x6662 },
2048                         { 0x1f, 0x0005 },
2049                         { 0x05, 0x8330 },
2050                         { 0x06, 0x6662 }
2051                 };
2052
2053                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2054         }
2055
2056         /* RSET couple improve */
2057         rtl_writephy(tp, 0x1f, 0x0002);
2058         rtl_patchphy(tp, 0x0d, 0x0300);
2059         rtl_patchphy(tp, 0x0f, 0x0010);
2060
2061         /* Fine tune PLL performance */
2062         rtl_writephy(tp, 0x1f, 0x0002);
2063         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2064         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2065
2066         rtl_writephy(tp, 0x1f, 0x0005);
2067         rtl_writephy(tp, 0x05, 0x001b);
2068         if (rtl_readphy(tp, 0x06) == 0xbf00 &&
2069             request_firmware(&fw, FIRMWARE_8168D_1, &tp->pci_dev->dev) == 0) {
2070                 rtl_phy_write_fw(tp, fw);
2071                 release_firmware(fw);
2072         } else {
2073                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2074         }
2075
2076         rtl_writephy(tp, 0x1f, 0x0000);
2077 }
2078
2079 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2080 {
2081         static const struct phy_reg phy_reg_init_0[] = {
2082                 /* Channel Estimation */
2083                 { 0x1f, 0x0001 },
2084                 { 0x06, 0x4064 },
2085                 { 0x07, 0x2863 },
2086                 { 0x08, 0x059c },
2087                 { 0x09, 0x26b4 },
2088                 { 0x0a, 0x6a19 },
2089                 { 0x0b, 0xdcc8 },
2090                 { 0x10, 0xf06d },
2091                 { 0x14, 0x7f68 },
2092                 { 0x18, 0x7fd9 },
2093                 { 0x1c, 0xf0ff },
2094                 { 0x1d, 0x3d9c },
2095                 { 0x1f, 0x0003 },
2096                 { 0x12, 0xf49f },
2097                 { 0x13, 0x070b },
2098                 { 0x1a, 0x05ad },
2099                 { 0x14, 0x94c0 },
2100
2101                 /*
2102                  * Tx Error Issue
2103                  * enhance line driver power
2104                  */
2105                 { 0x1f, 0x0002 },
2106                 { 0x06, 0x5561 },
2107                 { 0x1f, 0x0005 },
2108                 { 0x05, 0x8332 },
2109                 { 0x06, 0x5561 },
2110
2111                 /*
2112                  * Can not link to 1Gbps with bad cable
2113                  * Decrease SNR threshold form 21.07dB to 19.04dB
2114                  */
2115                 { 0x1f, 0x0001 },
2116                 { 0x17, 0x0cc0 },
2117
2118                 { 0x1f, 0x0000 },
2119                 { 0x0d, 0xf880 }
2120         };
2121         void __iomem *ioaddr = tp->mmio_addr;
2122         const struct firmware *fw;
2123
2124         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2125
2126         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2127                 static const struct phy_reg phy_reg_init[] = {
2128                         { 0x1f, 0x0002 },
2129                         { 0x05, 0x669a },
2130                         { 0x1f, 0x0005 },
2131                         { 0x05, 0x8330 },
2132                         { 0x06, 0x669a },
2133
2134                         { 0x1f, 0x0002 }
2135                 };
2136                 int val;
2137
2138                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2139
2140                 val = rtl_readphy(tp, 0x0d);
2141                 if ((val & 0x00ff) != 0x006c) {
2142                         static const u32 set[] = {
2143                                 0x0065, 0x0066, 0x0067, 0x0068,
2144                                 0x0069, 0x006a, 0x006b, 0x006c
2145                         };
2146                         int i;
2147
2148                         rtl_writephy(tp, 0x1f, 0x0002);
2149
2150                         val &= 0xff00;
2151                         for (i = 0; i < ARRAY_SIZE(set); i++)
2152                                 rtl_writephy(tp, 0x0d, val | set[i]);
2153                 }
2154         } else {
2155                 static const struct phy_reg phy_reg_init[] = {
2156                         { 0x1f, 0x0002 },
2157                         { 0x05, 0x2642 },
2158                         { 0x1f, 0x0005 },
2159                         { 0x05, 0x8330 },
2160                         { 0x06, 0x2642 }
2161                 };
2162
2163                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2164         }
2165
2166         /* Fine tune PLL performance */
2167         rtl_writephy(tp, 0x1f, 0x0002);
2168         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2169         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2170
2171         /* Switching regulator Slew rate */
2172         rtl_writephy(tp, 0x1f, 0x0002);
2173         rtl_patchphy(tp, 0x0f, 0x0017);
2174
2175         rtl_writephy(tp, 0x1f, 0x0005);
2176         rtl_writephy(tp, 0x05, 0x001b);
2177         if (rtl_readphy(tp, 0x06) == 0xb300 &&
2178             request_firmware(&fw, FIRMWARE_8168D_2, &tp->pci_dev->dev) == 0) {
2179                 rtl_phy_write_fw(tp, fw);
2180                 release_firmware(fw);
2181         } else {
2182                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2183         }
2184
2185         rtl_writephy(tp, 0x1f, 0x0000);
2186 }
2187
2188 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2189 {
2190         static const struct phy_reg phy_reg_init[] = {
2191                 { 0x1f, 0x0002 },
2192                 { 0x10, 0x0008 },
2193                 { 0x0d, 0x006c },
2194
2195                 { 0x1f, 0x0000 },
2196                 { 0x0d, 0xf880 },
2197
2198                 { 0x1f, 0x0001 },
2199                 { 0x17, 0x0cc0 },
2200
2201                 { 0x1f, 0x0001 },
2202                 { 0x0b, 0xa4d8 },
2203                 { 0x09, 0x281c },
2204                 { 0x07, 0x2883 },
2205                 { 0x0a, 0x6b35 },
2206                 { 0x1d, 0x3da4 },
2207                 { 0x1c, 0xeffd },
2208                 { 0x14, 0x7f52 },
2209                 { 0x18, 0x7fc6 },
2210                 { 0x08, 0x0601 },
2211                 { 0x06, 0x4063 },
2212                 { 0x10, 0xf074 },
2213                 { 0x1f, 0x0003 },
2214                 { 0x13, 0x0789 },
2215                 { 0x12, 0xf4bd },
2216                 { 0x1a, 0x04fd },
2217                 { 0x14, 0x84b0 },
2218                 { 0x1f, 0x0000 },
2219                 { 0x00, 0x9200 },
2220
2221                 { 0x1f, 0x0005 },
2222                 { 0x01, 0x0340 },
2223                 { 0x1f, 0x0001 },
2224                 { 0x04, 0x4000 },
2225                 { 0x03, 0x1d21 },
2226                 { 0x02, 0x0c32 },
2227                 { 0x01, 0x0200 },
2228                 { 0x00, 0x5554 },
2229                 { 0x04, 0x4800 },
2230                 { 0x04, 0x4000 },
2231                 { 0x04, 0xf000 },
2232                 { 0x03, 0xdf01 },
2233                 { 0x02, 0xdf20 },
2234                 { 0x01, 0x101a },
2235                 { 0x00, 0xa0ff },
2236                 { 0x04, 0xf800 },
2237                 { 0x04, 0xf000 },
2238                 { 0x1f, 0x0000 },
2239
2240                 { 0x1f, 0x0007 },
2241                 { 0x1e, 0x0023 },
2242                 { 0x16, 0x0000 },
2243                 { 0x1f, 0x0000 }
2244         };
2245
2246         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2247 }
2248
2249 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2250 {
2251         static const struct phy_reg phy_reg_init[] = {
2252                 { 0x1f, 0x0003 },
2253                 { 0x08, 0x441d },
2254                 { 0x01, 0x9100 },
2255                 { 0x1f, 0x0000 }
2256         };
2257
2258         rtl_writephy(tp, 0x1f, 0x0000);
2259         rtl_patchphy(tp, 0x11, 1 << 12);
2260         rtl_patchphy(tp, 0x19, 1 << 13);
2261         rtl_patchphy(tp, 0x10, 1 << 15);
2262
2263         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2264 }
2265
2266 static void rtl_hw_phy_config(struct net_device *dev)
2267 {
2268         struct rtl8169_private *tp = netdev_priv(dev);
2269
2270         rtl8169_print_mac_version(tp);
2271
2272         switch (tp->mac_version) {
2273         case RTL_GIGA_MAC_VER_01:
2274                 break;
2275         case RTL_GIGA_MAC_VER_02:
2276         case RTL_GIGA_MAC_VER_03:
2277                 rtl8169s_hw_phy_config(tp);
2278                 break;
2279         case RTL_GIGA_MAC_VER_04:
2280                 rtl8169sb_hw_phy_config(tp);
2281                 break;
2282         case RTL_GIGA_MAC_VER_05:
2283                 rtl8169scd_hw_phy_config(tp);
2284                 break;
2285         case RTL_GIGA_MAC_VER_06:
2286                 rtl8169sce_hw_phy_config(tp);
2287                 break;
2288         case RTL_GIGA_MAC_VER_07:
2289         case RTL_GIGA_MAC_VER_08:
2290         case RTL_GIGA_MAC_VER_09:
2291                 rtl8102e_hw_phy_config(tp);
2292                 break;
2293         case RTL_GIGA_MAC_VER_11:
2294                 rtl8168bb_hw_phy_config(tp);
2295                 break;
2296         case RTL_GIGA_MAC_VER_12:
2297                 rtl8168bef_hw_phy_config(tp);
2298                 break;
2299         case RTL_GIGA_MAC_VER_17:
2300                 rtl8168bef_hw_phy_config(tp);
2301                 break;
2302         case RTL_GIGA_MAC_VER_18:
2303                 rtl8168cp_1_hw_phy_config(tp);
2304                 break;
2305         case RTL_GIGA_MAC_VER_19:
2306                 rtl8168c_1_hw_phy_config(tp);
2307                 break;
2308         case RTL_GIGA_MAC_VER_20:
2309                 rtl8168c_2_hw_phy_config(tp);
2310                 break;
2311         case RTL_GIGA_MAC_VER_21:
2312                 rtl8168c_3_hw_phy_config(tp);
2313                 break;
2314         case RTL_GIGA_MAC_VER_22:
2315                 rtl8168c_4_hw_phy_config(tp);
2316                 break;
2317         case RTL_GIGA_MAC_VER_23:
2318         case RTL_GIGA_MAC_VER_24:
2319                 rtl8168cp_2_hw_phy_config(tp);
2320                 break;
2321         case RTL_GIGA_MAC_VER_25:
2322                 rtl8168d_1_hw_phy_config(tp);
2323                 break;
2324         case RTL_GIGA_MAC_VER_26:
2325                 rtl8168d_2_hw_phy_config(tp);
2326                 break;
2327         case RTL_GIGA_MAC_VER_27:
2328                 rtl8168d_3_hw_phy_config(tp);
2329                 break;
2330
2331         default:
2332                 break;
2333         }
2334 }
2335
2336 static void rtl8169_phy_timer(unsigned long __opaque)
2337 {
2338         struct net_device *dev = (struct net_device *)__opaque;
2339         struct rtl8169_private *tp = netdev_priv(dev);
2340         struct timer_list *timer = &tp->timer;
2341         void __iomem *ioaddr = tp->mmio_addr;
2342         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2343
2344         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2345
2346         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2347                 return;
2348
2349         spin_lock_irq(&tp->lock);
2350
2351         if (tp->phy_reset_pending(tp)) {
2352                 /*
2353                  * A busy loop could burn quite a few cycles on nowadays CPU.
2354                  * Let's delay the execution of the timer for a few ticks.
2355                  */
2356                 timeout = HZ/10;
2357                 goto out_mod_timer;
2358         }
2359
2360         if (tp->link_ok(ioaddr))
2361                 goto out_unlock;
2362
2363         netif_warn(tp, link, dev, "PHY reset until link up\n");
2364
2365         tp->phy_reset_enable(tp);
2366
2367 out_mod_timer:
2368         mod_timer(timer, jiffies + timeout);
2369 out_unlock:
2370         spin_unlock_irq(&tp->lock);
2371 }
2372
2373 static inline void rtl8169_delete_timer(struct net_device *dev)
2374 {
2375         struct rtl8169_private *tp = netdev_priv(dev);
2376         struct timer_list *timer = &tp->timer;
2377
2378         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2379                 return;
2380
2381         del_timer_sync(timer);
2382 }
2383
2384 static inline void rtl8169_request_timer(struct net_device *dev)
2385 {
2386         struct rtl8169_private *tp = netdev_priv(dev);
2387         struct timer_list *timer = &tp->timer;
2388
2389         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2390                 return;
2391
2392         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2393 }
2394
2395 #ifdef CONFIG_NET_POLL_CONTROLLER
2396 /*
2397  * Polling 'interrupt' - used by things like netconsole to send skbs
2398  * without having to re-enable interrupts. It's not called while
2399  * the interrupt routine is executing.
2400  */
2401 static void rtl8169_netpoll(struct net_device *dev)
2402 {
2403         struct rtl8169_private *tp = netdev_priv(dev);
2404         struct pci_dev *pdev = tp->pci_dev;
2405
2406         disable_irq(pdev->irq);
2407         rtl8169_interrupt(pdev->irq, dev);
2408         enable_irq(pdev->irq);
2409 }
2410 #endif
2411
2412 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2413                                   void __iomem *ioaddr)
2414 {
2415         iounmap(ioaddr);
2416         pci_release_regions(pdev);
2417         pci_clear_mwi(pdev);
2418         pci_disable_device(pdev);
2419         free_netdev(dev);
2420 }
2421
2422 static void rtl8169_phy_reset(struct net_device *dev,
2423                               struct rtl8169_private *tp)
2424 {
2425         unsigned int i;
2426
2427         tp->phy_reset_enable(tp);
2428         for (i = 0; i < 100; i++) {
2429                 if (!tp->phy_reset_pending(tp))
2430                         return;
2431                 msleep(1);
2432         }
2433         netif_err(tp, link, dev, "PHY reset failed\n");
2434 }
2435
2436 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2437 {
2438         void __iomem *ioaddr = tp->mmio_addr;
2439
2440         rtl_hw_phy_config(dev);
2441
2442         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2443                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2444                 RTL_W8(0x82, 0x01);
2445         }
2446
2447         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2448
2449         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2450                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2451
2452         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2453                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2454                 RTL_W8(0x82, 0x01);
2455                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2456                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2457         }
2458
2459         rtl8169_phy_reset(dev, tp);
2460
2461         /*
2462          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2463          * only 8101. Don't panic.
2464          */
2465         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2466
2467         if (RTL_R8(PHYstatus) & TBI_Enable)
2468                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2469 }
2470
2471 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2472 {
2473         void __iomem *ioaddr = tp->mmio_addr;
2474         u32 high;
2475         u32 low;
2476
2477         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2478         high = addr[4] | (addr[5] << 8);
2479
2480         spin_lock_irq(&tp->lock);
2481
2482         RTL_W8(Cfg9346, Cfg9346_Unlock);
2483
2484         RTL_W32(MAC4, high);
2485         RTL_R32(MAC4);
2486
2487         RTL_W32(MAC0, low);
2488         RTL_R32(MAC0);
2489
2490         RTL_W8(Cfg9346, Cfg9346_Lock);
2491
2492         spin_unlock_irq(&tp->lock);
2493 }
2494
2495 static int rtl_set_mac_address(struct net_device *dev, void *p)
2496 {
2497         struct rtl8169_private *tp = netdev_priv(dev);
2498         struct sockaddr *addr = p;
2499
2500         if (!is_valid_ether_addr(addr->sa_data))
2501                 return -EADDRNOTAVAIL;
2502
2503         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2504
2505         rtl_rar_set(tp, dev->dev_addr);
2506
2507         return 0;
2508 }
2509
2510 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2511 {
2512         struct rtl8169_private *tp = netdev_priv(dev);
2513         struct mii_ioctl_data *data = if_mii(ifr);
2514
2515         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2516 }
2517
2518 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2519 {
2520         switch (cmd) {
2521         case SIOCGMIIPHY:
2522                 data->phy_id = 32; /* Internal PHY */
2523                 return 0;
2524
2525         case SIOCGMIIREG:
2526                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2527                 return 0;
2528
2529         case SIOCSMIIREG:
2530                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2531                 return 0;
2532         }
2533         return -EOPNOTSUPP;
2534 }
2535
2536 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2537 {
2538         return -EOPNOTSUPP;
2539 }
2540
2541 static const struct rtl_cfg_info {
2542         void (*hw_start)(struct net_device *);
2543         unsigned int region;
2544         unsigned int align;
2545         u16 intr_event;
2546         u16 napi_event;
2547         unsigned features;
2548         u8 default_ver;
2549 } rtl_cfg_infos [] = {
2550         [RTL_CFG_0] = {
2551                 .hw_start       = rtl_hw_start_8169,
2552                 .region         = 1,
2553                 .align          = 0,
2554                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2555                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2556                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2557                 .features       = RTL_FEATURE_GMII,
2558                 .default_ver    = RTL_GIGA_MAC_VER_01,
2559         },
2560         [RTL_CFG_1] = {
2561                 .hw_start       = rtl_hw_start_8168,
2562                 .region         = 2,
2563                 .align          = 8,
2564                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2565                                   TxErr | TxOK | RxOK | RxErr,
2566                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
2567                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2568                 .default_ver    = RTL_GIGA_MAC_VER_11,
2569         },
2570         [RTL_CFG_2] = {
2571                 .hw_start       = rtl_hw_start_8101,
2572                 .region         = 2,
2573                 .align          = 8,
2574                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2575                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2576                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2577                 .features       = RTL_FEATURE_MSI,
2578                 .default_ver    = RTL_GIGA_MAC_VER_13,
2579         }
2580 };
2581
2582 /* Cfg9346_Unlock assumed. */
2583 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2584                             const struct rtl_cfg_info *cfg)
2585 {
2586         unsigned msi = 0;
2587         u8 cfg2;
2588
2589         cfg2 = RTL_R8(Config2) & ~MSIEnable;
2590         if (cfg->features & RTL_FEATURE_MSI) {
2591                 if (pci_enable_msi(pdev)) {
2592                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2593                 } else {
2594                         cfg2 |= MSIEnable;
2595                         msi = RTL_FEATURE_MSI;
2596                 }
2597         }
2598         RTL_W8(Config2, cfg2);
2599         return msi;
2600 }
2601
2602 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2603 {
2604         if (tp->features & RTL_FEATURE_MSI) {
2605                 pci_disable_msi(pdev);
2606                 tp->features &= ~RTL_FEATURE_MSI;
2607         }
2608 }
2609
2610 static const struct net_device_ops rtl8169_netdev_ops = {
2611         .ndo_open               = rtl8169_open,
2612         .ndo_stop               = rtl8169_close,
2613         .ndo_get_stats          = rtl8169_get_stats,
2614         .ndo_start_xmit         = rtl8169_start_xmit,
2615         .ndo_tx_timeout         = rtl8169_tx_timeout,
2616         .ndo_validate_addr      = eth_validate_addr,
2617         .ndo_change_mtu         = rtl8169_change_mtu,
2618         .ndo_set_mac_address    = rtl_set_mac_address,
2619         .ndo_do_ioctl           = rtl8169_ioctl,
2620         .ndo_set_multicast_list = rtl_set_rx_mode,
2621 #ifdef CONFIG_R8169_VLAN
2622         .ndo_vlan_rx_register   = rtl8169_vlan_rx_register,
2623 #endif
2624 #ifdef CONFIG_NET_POLL_CONTROLLER
2625         .ndo_poll_controller    = rtl8169_netpoll,
2626 #endif
2627
2628 };
2629
2630 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2631 {
2632         struct mdio_ops *ops = &tp->mdio_ops;
2633
2634         switch (tp->mac_version) {
2635         case RTL_GIGA_MAC_VER_27:
2636                 ops->write      = r8168dp_1_mdio_write;
2637                 ops->read       = r8168dp_1_mdio_read;
2638                 break;
2639         default:
2640                 ops->write      = r8169_mdio_write;
2641                 ops->read       = r8169_mdio_read;
2642                 break;
2643         }
2644 }
2645
2646 static void r810x_phy_power_down(struct rtl8169_private *tp)
2647 {
2648         rtl_writephy(tp, 0x1f, 0x0000);
2649         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2650 }
2651
2652 static void r810x_phy_power_up(struct rtl8169_private *tp)
2653 {
2654         rtl_writephy(tp, 0x1f, 0x0000);
2655         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2656 }
2657
2658 static void r810x_pll_power_down(struct rtl8169_private *tp)
2659 {
2660         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2661                 rtl_writephy(tp, 0x1f, 0x0000);
2662                 rtl_writephy(tp, MII_BMCR, 0x0000);
2663                 return;
2664         }
2665
2666         r810x_phy_power_down(tp);
2667 }
2668
2669 static void r810x_pll_power_up(struct rtl8169_private *tp)
2670 {
2671         r810x_phy_power_up(tp);
2672 }
2673
2674 static void r8168_phy_power_up(struct rtl8169_private *tp)
2675 {
2676         rtl_writephy(tp, 0x1f, 0x0000);
2677         rtl_writephy(tp, 0x0e, 0x0000);
2678         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2679 }
2680
2681 static void r8168_phy_power_down(struct rtl8169_private *tp)
2682 {
2683         rtl_writephy(tp, 0x1f, 0x0000);
2684         rtl_writephy(tp, 0x0e, 0x0200);
2685         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2686 }
2687
2688 static void r8168_pll_power_down(struct rtl8169_private *tp)
2689 {
2690         void __iomem *ioaddr = tp->mmio_addr;
2691
2692         if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2693                 return;
2694
2695         if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
2696              (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
2697             (RTL_R16(CPlusCmd) & ASF)) {
2698                 return;
2699         }
2700
2701         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2702                 rtl_writephy(tp, 0x1f, 0x0000);
2703                 rtl_writephy(tp, MII_BMCR, 0x0000);
2704
2705                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
2706                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2707                 return;
2708         }
2709
2710         r8168_phy_power_down(tp);
2711
2712         switch (tp->mac_version) {
2713         case RTL_GIGA_MAC_VER_25:
2714         case RTL_GIGA_MAC_VER_26:
2715                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
2716                 break;
2717         }
2718 }
2719
2720 static void r8168_pll_power_up(struct rtl8169_private *tp)
2721 {
2722         void __iomem *ioaddr = tp->mmio_addr;
2723
2724         if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2725                 return;
2726
2727         switch (tp->mac_version) {
2728         case RTL_GIGA_MAC_VER_25:
2729         case RTL_GIGA_MAC_VER_26:
2730                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
2731                 break;
2732         }
2733
2734         r8168_phy_power_up(tp);
2735 }
2736
2737 static void rtl_pll_power_op(struct rtl8169_private *tp,
2738                              void (*op)(struct rtl8169_private *))
2739 {
2740         if (op)
2741                 op(tp);
2742 }
2743
2744 static void rtl_pll_power_down(struct rtl8169_private *tp)
2745 {
2746         rtl_pll_power_op(tp, tp->pll_power_ops.down);
2747 }
2748
2749 static void rtl_pll_power_up(struct rtl8169_private *tp)
2750 {
2751         rtl_pll_power_op(tp, tp->pll_power_ops.up);
2752 }
2753
2754 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
2755 {
2756         struct pll_power_ops *ops = &tp->pll_power_ops;
2757
2758         switch (tp->mac_version) {
2759         case RTL_GIGA_MAC_VER_07:
2760         case RTL_GIGA_MAC_VER_08:
2761         case RTL_GIGA_MAC_VER_09:
2762         case RTL_GIGA_MAC_VER_10:
2763         case RTL_GIGA_MAC_VER_16:
2764                 ops->down       = r810x_pll_power_down;
2765                 ops->up         = r810x_pll_power_up;
2766                 break;
2767
2768         case RTL_GIGA_MAC_VER_11:
2769         case RTL_GIGA_MAC_VER_12:
2770         case RTL_GIGA_MAC_VER_17:
2771         case RTL_GIGA_MAC_VER_18:
2772         case RTL_GIGA_MAC_VER_19:
2773         case RTL_GIGA_MAC_VER_20:
2774         case RTL_GIGA_MAC_VER_21:
2775         case RTL_GIGA_MAC_VER_22:
2776         case RTL_GIGA_MAC_VER_23:
2777         case RTL_GIGA_MAC_VER_24:
2778         case RTL_GIGA_MAC_VER_25:
2779         case RTL_GIGA_MAC_VER_26:
2780         case RTL_GIGA_MAC_VER_27:
2781                 ops->down       = r8168_pll_power_down;
2782                 ops->up         = r8168_pll_power_up;
2783                 break;
2784
2785         default:
2786                 ops->down       = NULL;
2787                 ops->up         = NULL;
2788                 break;
2789         }
2790 }
2791
2792 static int __devinit
2793 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2794 {
2795         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2796         const unsigned int region = cfg->region;
2797         struct rtl8169_private *tp;
2798         struct mii_if_info *mii;
2799         struct net_device *dev;
2800         void __iomem *ioaddr;
2801         unsigned int i;
2802         int rc;
2803
2804         if (netif_msg_drv(&debug)) {
2805                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2806                        MODULENAME, RTL8169_VERSION);
2807         }
2808
2809         dev = alloc_etherdev(sizeof (*tp));
2810         if (!dev) {
2811                 if (netif_msg_drv(&debug))
2812                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
2813                 rc = -ENOMEM;
2814                 goto out;
2815         }
2816
2817         SET_NETDEV_DEV(dev, &pdev->dev);
2818         dev->netdev_ops = &rtl8169_netdev_ops;
2819         tp = netdev_priv(dev);
2820         tp->dev = dev;
2821         tp->pci_dev = pdev;
2822         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
2823
2824         mii = &tp->mii;
2825         mii->dev = dev;
2826         mii->mdio_read = rtl_mdio_read;
2827         mii->mdio_write = rtl_mdio_write;
2828         mii->phy_id_mask = 0x1f;
2829         mii->reg_num_mask = 0x1f;
2830         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2831
2832         /* enable device (incl. PCI PM wakeup and hotplug setup) */
2833         rc = pci_enable_device(pdev);
2834         if (rc < 0) {
2835                 netif_err(tp, probe, dev, "enable failure\n");
2836                 goto err_out_free_dev_1;
2837         }
2838
2839         if (pci_set_mwi(pdev) < 0)
2840                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
2841
2842         /* make sure PCI base addr 1 is MMIO */
2843         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
2844                 netif_err(tp, probe, dev,
2845                           "region #%d not an MMIO resource, aborting\n",
2846                           region);
2847                 rc = -ENODEV;
2848                 goto err_out_mwi_2;
2849         }
2850
2851         /* check for weird/broken PCI region reporting */
2852         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
2853                 netif_err(tp, probe, dev,
2854                           "Invalid PCI region size(s), aborting\n");
2855                 rc = -ENODEV;
2856                 goto err_out_mwi_2;
2857         }
2858
2859         rc = pci_request_regions(pdev, MODULENAME);
2860         if (rc < 0) {
2861                 netif_err(tp, probe, dev, "could not request regions\n");
2862                 goto err_out_mwi_2;
2863         }
2864
2865         tp->cp_cmd = PCIMulRW | RxChkSum;
2866
2867         if ((sizeof(dma_addr_t) > 4) &&
2868             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
2869                 tp->cp_cmd |= PCIDAC;
2870                 dev->features |= NETIF_F_HIGHDMA;
2871         } else {
2872                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2873                 if (rc < 0) {
2874                         netif_err(tp, probe, dev, "DMA configuration failed\n");
2875                         goto err_out_free_res_3;
2876                 }
2877         }
2878
2879         /* ioremap MMIO region */
2880         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
2881         if (!ioaddr) {
2882                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
2883                 rc = -EIO;
2884                 goto err_out_free_res_3;
2885         }
2886
2887         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2888         if (!tp->pcie_cap)
2889                 netif_info(tp, probe, dev, "no PCI Express capability\n");
2890
2891         RTL_W16(IntrMask, 0x0000);
2892
2893         /* Soft reset the chip. */
2894         RTL_W8(ChipCmd, CmdReset);
2895
2896         /* Check that the chip has finished the reset. */
2897         for (i = 0; i < 100; i++) {
2898                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2899                         break;
2900                 msleep_interruptible(1);
2901         }
2902
2903         RTL_W16(IntrStatus, 0xffff);
2904
2905         pci_set_master(pdev);
2906
2907         /* Identify chip attached to board */
2908         rtl8169_get_mac_version(tp, ioaddr);
2909
2910         rtl_init_mdio_ops(tp);
2911         rtl_init_pll_power_ops(tp);
2912
2913         /* Use appropriate default if unknown */
2914         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2915                 netif_notice(tp, probe, dev,
2916                              "unknown MAC, using family default\n");
2917                 tp->mac_version = cfg->default_ver;
2918         }
2919
2920         rtl8169_print_mac_version(tp);
2921
2922         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
2923                 if (tp->mac_version == rtl_chip_info[i].mac_version)
2924                         break;
2925         }
2926         if (i == ARRAY_SIZE(rtl_chip_info)) {
2927                 dev_err(&pdev->dev,
2928                         "driver bug, MAC version not found in rtl_chip_info\n");
2929                 goto err_out_msi_4;
2930         }
2931         tp->chipset = i;
2932
2933         RTL_W8(Cfg9346, Cfg9346_Unlock);
2934         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2935         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
2936         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2937                 tp->features |= RTL_FEATURE_WOL;
2938         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2939                 tp->features |= RTL_FEATURE_WOL;
2940         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
2941         RTL_W8(Cfg9346, Cfg9346_Lock);
2942
2943         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2944             (RTL_R8(PHYstatus) & TBI_Enable)) {
2945                 tp->set_speed = rtl8169_set_speed_tbi;
2946                 tp->get_settings = rtl8169_gset_tbi;
2947                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2948                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2949                 tp->link_ok = rtl8169_tbi_link_ok;
2950                 tp->do_ioctl = rtl_tbi_ioctl;
2951
2952                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
2953         } else {
2954                 tp->set_speed = rtl8169_set_speed_xmii;
2955                 tp->get_settings = rtl8169_gset_xmii;
2956                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2957                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2958                 tp->link_ok = rtl8169_xmii_link_ok;
2959                 tp->do_ioctl = rtl_xmii_ioctl;
2960         }
2961
2962         spin_lock_init(&tp->lock);
2963
2964         tp->mmio_addr = ioaddr;
2965
2966         /* Get MAC address */
2967         for (i = 0; i < MAC_ADDR_LEN; i++)
2968                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
2969         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2970
2971         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2972         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2973         dev->irq = pdev->irq;
2974         dev->base_addr = (unsigned long) ioaddr;
2975
2976         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
2977
2978 #ifdef CONFIG_R8169_VLAN
2979         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2980 #endif
2981         dev->features |= NETIF_F_GRO;
2982
2983         tp->intr_mask = 0xffff;
2984         tp->hw_start = cfg->hw_start;
2985         tp->intr_event = cfg->intr_event;
2986         tp->napi_event = cfg->napi_event;
2987
2988         init_timer(&tp->timer);
2989         tp->timer.data = (unsigned long) dev;
2990         tp->timer.function = rtl8169_phy_timer;
2991
2992         rc = register_netdev(dev);
2993         if (rc < 0)
2994                 goto err_out_msi_4;
2995
2996         pci_set_drvdata(pdev, dev);
2997
2998         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
2999                    rtl_chip_info[tp->chipset].name,
3000                    dev->base_addr, dev->dev_addr,
3001                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3002
3003         if (tp->mac_version == RTL_GIGA_MAC_VER_27)
3004                 rtl8168_driver_start(tp);
3005
3006         rtl8169_init_phy(dev, tp);
3007
3008         /*
3009          * Pretend we are using VLANs; This bypasses a nasty bug where
3010          * Interrupts stop flowing on high load on 8110SCd controllers.
3011          */
3012         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3013                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3014
3015         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3016
3017         if (pci_dev_run_wake(pdev))
3018                 pm_runtime_put_noidle(&pdev->dev);
3019
3020 out:
3021         return rc;
3022
3023 err_out_msi_4:
3024         rtl_disable_msi(pdev, tp);
3025         iounmap(ioaddr);
3026 err_out_free_res_3:
3027         pci_release_regions(pdev);
3028 err_out_mwi_2:
3029         pci_clear_mwi(pdev);
3030         pci_disable_device(pdev);
3031 err_out_free_dev_1:
3032         free_netdev(dev);
3033         goto out;
3034 }
3035
3036 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3037 {
3038         struct net_device *dev = pci_get_drvdata(pdev);
3039         struct rtl8169_private *tp = netdev_priv(dev);
3040
3041         if (tp->mac_version == RTL_GIGA_MAC_VER_27)
3042                 rtl8168_driver_stop(tp);
3043
3044         cancel_delayed_work_sync(&tp->task);
3045
3046         unregister_netdev(dev);
3047
3048         if (pci_dev_run_wake(pdev))
3049                 pm_runtime_get_noresume(&pdev->dev);
3050
3051         /* restore original MAC address */
3052         rtl_rar_set(tp, dev->perm_addr);
3053
3054         rtl_disable_msi(pdev, tp);
3055         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3056         pci_set_drvdata(pdev, NULL);
3057 }
3058
3059 static int rtl8169_open(struct net_device *dev)
3060 {
3061         struct rtl8169_private *tp = netdev_priv(dev);
3062         struct pci_dev *pdev = tp->pci_dev;
3063         int retval = -ENOMEM;
3064
3065         pm_runtime_get_sync(&pdev->dev);
3066
3067         /*
3068          * Rx and Tx desscriptors needs 256 bytes alignment.
3069          * dma_alloc_coherent provides more.
3070          */
3071         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3072                                              &tp->TxPhyAddr, GFP_KERNEL);
3073         if (!tp->TxDescArray)
3074                 goto err_pm_runtime_put;
3075
3076         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3077                                              &tp->RxPhyAddr, GFP_KERNEL);
3078         if (!tp->RxDescArray)
3079                 goto err_free_tx_0;
3080
3081         retval = rtl8169_init_ring(dev);
3082         if (retval < 0)
3083                 goto err_free_rx_1;
3084
3085         INIT_DELAYED_WORK(&tp->task, NULL);
3086
3087         smp_mb();
3088
3089         retval = request_irq(dev->irq, rtl8169_interrupt,
3090                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3091                              dev->name, dev);
3092         if (retval < 0)
3093                 goto err_release_ring_2;
3094
3095         napi_enable(&tp->napi);
3096
3097         rtl_pll_power_up(tp);
3098
3099         rtl_hw_start(dev);
3100
3101         rtl8169_request_timer(dev);
3102
3103         tp->saved_wolopts = 0;
3104         pm_runtime_put_noidle(&pdev->dev);
3105
3106         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3107 out:
3108         return retval;
3109
3110 err_release_ring_2:
3111         rtl8169_rx_clear(tp);
3112 err_free_rx_1:
3113         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3114                           tp->RxPhyAddr);
3115         tp->RxDescArray = NULL;
3116 err_free_tx_0:
3117         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3118                           tp->TxPhyAddr);
3119         tp->TxDescArray = NULL;
3120 err_pm_runtime_put:
3121         pm_runtime_put_noidle(&pdev->dev);
3122         goto out;
3123 }
3124
3125 static void rtl8169_hw_reset(void __iomem *ioaddr)
3126 {
3127         /* Disable interrupts */
3128         rtl8169_irq_mask_and_ack(ioaddr);
3129
3130         /* Reset the chipset */
3131         RTL_W8(ChipCmd, CmdReset);
3132
3133         /* PCI commit */
3134         RTL_R8(ChipCmd);
3135 }
3136
3137 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3138 {
3139         void __iomem *ioaddr = tp->mmio_addr;
3140         u32 cfg = rtl8169_rx_config;
3141
3142         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3143         RTL_W32(RxConfig, cfg);
3144
3145         /* Set DMA burst size and Interframe Gap Time */
3146         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3147                 (InterFrameGap << TxInterFrameGapShift));
3148 }
3149
3150 static void rtl_hw_start(struct net_device *dev)
3151 {
3152         struct rtl8169_private *tp = netdev_priv(dev);
3153         void __iomem *ioaddr = tp->mmio_addr;
3154         unsigned int i;
3155
3156         /* Soft reset the chip. */
3157         RTL_W8(ChipCmd, CmdReset);
3158
3159         /* Check that the chip has finished the reset. */
3160         for (i = 0; i < 100; i++) {
3161                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3162                         break;
3163                 msleep_interruptible(1);
3164         }
3165
3166         tp->hw_start(dev);
3167
3168         netif_start_queue(dev);
3169 }
3170
3171
3172 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3173                                          void __iomem *ioaddr)
3174 {
3175         /*
3176          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3177          * register to be written before TxDescAddrLow to work.
3178          * Switching from MMIO to I/O access fixes the issue as well.
3179          */
3180         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3181         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3182         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3183         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3184 }
3185
3186 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3187 {
3188         u16 cmd;
3189
3190         cmd = RTL_R16(CPlusCmd);
3191         RTL_W16(CPlusCmd, cmd);
3192         return cmd;
3193 }
3194
3195 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3196 {
3197         /* Low hurts. Let's disable the filtering. */
3198         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3199 }
3200
3201 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3202 {
3203         static const struct {
3204                 u32 mac_version;
3205                 u32 clk;
3206                 u32 val;
3207         } cfg2_info [] = {
3208                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3209                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3210                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3211                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3212         }, *p = cfg2_info;
3213         unsigned int i;
3214         u32 clk;
3215
3216         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3217         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3218                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3219                         RTL_W32(0x7c, p->val);
3220                         break;
3221                 }
3222         }
3223 }
3224
3225 static void rtl_hw_start_8169(struct net_device *dev)
3226 {
3227         struct rtl8169_private *tp = netdev_priv(dev);
3228         void __iomem *ioaddr = tp->mmio_addr;
3229         struct pci_dev *pdev = tp->pci_dev;
3230
3231         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3232                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3233                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3234         }
3235
3236         RTL_W8(Cfg9346, Cfg9346_Unlock);
3237         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3238             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3239             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3240             (tp->mac_version == RTL_GIGA_MAC_VER_04))
3241                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3242
3243         RTL_W8(EarlyTxThres, NoEarlyTx);
3244
3245         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3246
3247         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3248             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3249             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3250             (tp->mac_version == RTL_GIGA_MAC_VER_04))
3251                 rtl_set_rx_tx_config_registers(tp);
3252
3253         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3254
3255         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3256             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3257                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3258                         "Bit-3 and bit-14 MUST be 1\n");
3259                 tp->cp_cmd |= (1 << 14);
3260         }
3261
3262         RTL_W16(CPlusCmd, tp->cp_cmd);
3263
3264         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3265
3266         /*
3267          * Undocumented corner. Supposedly:
3268          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3269          */
3270         RTL_W16(IntrMitigate, 0x0000);
3271
3272         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3273
3274         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3275             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3276             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3277             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3278                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3279                 rtl_set_rx_tx_config_registers(tp);
3280         }
3281
3282         RTL_W8(Cfg9346, Cfg9346_Lock);
3283
3284         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3285         RTL_R8(IntrMask);
3286
3287         RTL_W32(RxMissed, 0);
3288
3289         rtl_set_rx_mode(dev);
3290
3291         /* no early-rx interrupts */
3292         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3293
3294         /* Enable all known interrupts by setting the interrupt mask. */
3295         RTL_W16(IntrMask, tp->intr_event);
3296 }
3297
3298 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3299 {
3300         struct net_device *dev = pci_get_drvdata(pdev);
3301         struct rtl8169_private *tp = netdev_priv(dev);
3302         int cap = tp->pcie_cap;
3303
3304         if (cap) {
3305                 u16 ctl;
3306
3307                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3308                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3309                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3310         }
3311 }
3312
3313 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3314 {
3315         u32 csi;
3316
3317         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3318         rtl_csi_write(ioaddr, 0x070c, csi | bits);
3319 }
3320
3321 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3322 {
3323         rtl_csi_access_enable(ioaddr, 0x27000000);
3324 }
3325
3326 struct ephy_info {
3327         unsigned int offset;
3328         u16 mask;
3329         u16 bits;
3330 };
3331
3332 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3333 {
3334         u16 w;
3335
3336         while (len-- > 0) {
3337                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3338                 rtl_ephy_write(ioaddr, e->offset, w);
3339                 e++;
3340         }
3341 }
3342
3343 static void rtl_disable_clock_request(struct pci_dev *pdev)
3344 {
3345         struct net_device *dev = pci_get_drvdata(pdev);
3346         struct rtl8169_private *tp = netdev_priv(dev);
3347         int cap = tp->pcie_cap;
3348
3349         if (cap) {
3350                 u16 ctl;
3351
3352                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3353                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3354                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3355         }
3356 }
3357
3358 #define R8168_CPCMD_QUIRK_MASK (\
3359         EnableBist | \
3360         Mac_dbgo_oe | \
3361         Force_half_dup | \
3362         Force_rxflow_en | \
3363         Force_txflow_en | \
3364         Cxpl_dbg_sel | \
3365         ASF | \
3366         PktCntrDisable | \
3367         Mac_dbgo_sel)
3368
3369 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3370 {
3371         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3372
3373         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3374
3375         rtl_tx_performance_tweak(pdev,
3376                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3377 }
3378
3379 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3380 {
3381         rtl_hw_start_8168bb(ioaddr, pdev);
3382
3383         RTL_W8(MaxTxPacketSize, TxPacketMax);
3384
3385         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3386 }
3387
3388 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3389 {
3390         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3391
3392         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3393
3394         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3395
3396         rtl_disable_clock_request(pdev);
3397
3398         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3399 }
3400
3401 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3402 {
3403         static const struct ephy_info e_info_8168cp[] = {
3404                 { 0x01, 0,      0x0001 },
3405                 { 0x02, 0x0800, 0x1000 },
3406                 { 0x03, 0,      0x0042 },
3407                 { 0x06, 0x0080, 0x0000 },
3408                 { 0x07, 0,      0x2000 }
3409         };
3410
3411         rtl_csi_access_enable_2(ioaddr);
3412
3413         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3414
3415         __rtl_hw_start_8168cp(ioaddr, pdev);
3416 }
3417
3418 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3419 {
3420         rtl_csi_access_enable_2(ioaddr);
3421
3422         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3423
3424         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3425
3426         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3427 }
3428
3429 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3430 {
3431         rtl_csi_access_enable_2(ioaddr);
3432
3433         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3434
3435         /* Magic. */
3436         RTL_W8(DBG_REG, 0x20);
3437
3438         RTL_W8(MaxTxPacketSize, TxPacketMax);
3439
3440         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3441
3442         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3443 }
3444
3445 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3446 {
3447         static const struct ephy_info e_info_8168c_1[] = {
3448                 { 0x02, 0x0800, 0x1000 },
3449                 { 0x03, 0,      0x0002 },
3450                 { 0x06, 0x0080, 0x0000 }
3451         };
3452
3453         rtl_csi_access_enable_2(ioaddr);
3454
3455         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3456
3457         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3458
3459         __rtl_hw_start_8168cp(ioaddr, pdev);
3460 }
3461
3462 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3463 {
3464         static const struct ephy_info e_info_8168c_2[] = {
3465                 { 0x01, 0,      0x0001 },
3466                 { 0x03, 0x0400, 0x0220 }
3467         };
3468
3469         rtl_csi_access_enable_2(ioaddr);
3470
3471         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3472
3473         __rtl_hw_start_8168cp(ioaddr, pdev);
3474 }
3475
3476 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3477 {
3478         rtl_hw_start_8168c_2(ioaddr, pdev);
3479 }
3480
3481 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3482 {
3483         rtl_csi_access_enable_2(ioaddr);
3484
3485         __rtl_hw_start_8168cp(ioaddr, pdev);
3486 }
3487
3488 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3489 {
3490         rtl_csi_access_enable_2(ioaddr);
3491
3492         rtl_disable_clock_request(pdev);
3493
3494         RTL_W8(MaxTxPacketSize, TxPacketMax);
3495
3496         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3497
3498         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3499 }
3500
3501 static void rtl_hw_start_8168(struct net_device *dev)
3502 {
3503         struct rtl8169_private *tp = netdev_priv(dev);
3504         void __iomem *ioaddr = tp->mmio_addr;
3505         struct pci_dev *pdev = tp->pci_dev;
3506
3507         RTL_W8(Cfg9346, Cfg9346_Unlock);
3508
3509         RTL_W8(MaxTxPacketSize, TxPacketMax);
3510
3511         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3512
3513         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3514
3515         RTL_W16(CPlusCmd, tp->cp_cmd);
3516
3517         RTL_W16(IntrMitigate, 0x5151);
3518
3519         /* Work around for RxFIFO overflow. */
3520         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3521                 tp->intr_event |= RxFIFOOver | PCSTimeout;
3522                 tp->intr_event &= ~RxOverflow;
3523         }
3524
3525         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3526
3527         rtl_set_rx_mode(dev);
3528
3529         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3530                 (InterFrameGap << TxInterFrameGapShift));
3531
3532         RTL_R8(IntrMask);
3533
3534         switch (tp->mac_version) {
3535         case RTL_GIGA_MAC_VER_11:
3536                 rtl_hw_start_8168bb(ioaddr, pdev);
3537         break;
3538
3539         case RTL_GIGA_MAC_VER_12:
3540         case RTL_GIGA_MAC_VER_17:
3541                 rtl_hw_start_8168bef(ioaddr, pdev);
3542         break;
3543
3544         case RTL_GIGA_MAC_VER_18:
3545                 rtl_hw_start_8168cp_1(ioaddr, pdev);
3546         break;
3547
3548         case RTL_GIGA_MAC_VER_19:
3549                 rtl_hw_start_8168c_1(ioaddr, pdev);
3550         break;
3551
3552         case RTL_GIGA_MAC_VER_20:
3553                 rtl_hw_start_8168c_2(ioaddr, pdev);
3554         break;
3555
3556         case RTL_GIGA_MAC_VER_21:
3557                 rtl_hw_start_8168c_3(ioaddr, pdev);
3558         break;
3559
3560         case RTL_GIGA_MAC_VER_22:
3561                 rtl_hw_start_8168c_4(ioaddr, pdev);
3562         break;
3563
3564         case RTL_GIGA_MAC_VER_23:
3565                 rtl_hw_start_8168cp_2(ioaddr, pdev);
3566         break;
3567
3568         case RTL_GIGA_MAC_VER_24:
3569                 rtl_hw_start_8168cp_3(ioaddr, pdev);
3570         break;
3571
3572         case RTL_GIGA_MAC_VER_25:
3573         case RTL_GIGA_MAC_VER_26:
3574         case RTL_GIGA_MAC_VER_27:
3575                 rtl_hw_start_8168d(ioaddr, pdev);
3576         break;
3577
3578         default:
3579                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3580                         dev->name, tp->mac_version);
3581         break;
3582         }
3583
3584         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3585
3586         RTL_W8(Cfg9346, Cfg9346_Lock);
3587
3588         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3589
3590         RTL_W16(IntrMask, tp->intr_event);
3591 }
3592
3593 #define R810X_CPCMD_QUIRK_MASK (\
3594         EnableBist | \
3595         Mac_dbgo_oe | \
3596         Force_half_dup | \
3597         Force_rxflow_en | \
3598         Force_txflow_en | \
3599         Cxpl_dbg_sel | \
3600         ASF | \
3601         PktCntrDisable | \
3602         PCIDAC | \
3603         PCIMulRW)
3604
3605 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3606 {
3607         static const struct ephy_info e_info_8102e_1[] = {
3608                 { 0x01, 0, 0x6e65 },
3609                 { 0x02, 0, 0x091f },
3610                 { 0x03, 0, 0xc2f9 },
3611                 { 0x06, 0, 0xafb5 },
3612                 { 0x07, 0, 0x0e00 },
3613                 { 0x19, 0, 0xec80 },
3614                 { 0x01, 0, 0x2e65 },
3615                 { 0x01, 0, 0x6e65 }
3616         };
3617         u8 cfg1;
3618
3619         rtl_csi_access_enable_2(ioaddr);
3620
3621         RTL_W8(DBG_REG, FIX_NAK_1);
3622
3623         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3624
3625         RTL_W8(Config1,
3626                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3627         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3628
3629         cfg1 = RTL_R8(Config1);
3630         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3631                 RTL_W8(Config1, cfg1 & ~LEDS0);
3632
3633         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3634
3635         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3636 }
3637
3638 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3639 {
3640         rtl_csi_access_enable_2(ioaddr);
3641
3642         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3643
3644         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3645         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3646
3647         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3648 }
3649
3650 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3651 {
3652         rtl_hw_start_8102e_2(ioaddr, pdev);
3653
3654         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3655 }
3656
3657 static void rtl_hw_start_8101(struct net_device *dev)
3658 {
3659         struct rtl8169_private *tp = netdev_priv(dev);
3660         void __iomem *ioaddr = tp->mmio_addr;
3661         struct pci_dev *pdev = tp->pci_dev;
3662
3663         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3664             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3665                 int cap = tp->pcie_cap;
3666
3667                 if (cap) {
3668                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3669                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
3670                 }
3671         }
3672
3673         switch (tp->mac_version) {
3674         case RTL_GIGA_MAC_VER_07:
3675                 rtl_hw_start_8102e_1(ioaddr, pdev);
3676                 break;
3677
3678         case RTL_GIGA_MAC_VER_08:
3679                 rtl_hw_start_8102e_3(ioaddr, pdev);
3680                 break;
3681
3682         case RTL_GIGA_MAC_VER_09:
3683                 rtl_hw_start_8102e_2(ioaddr, pdev);
3684                 break;
3685         }
3686
3687         RTL_W8(Cfg9346, Cfg9346_Unlock);
3688
3689         RTL_W8(MaxTxPacketSize, TxPacketMax);
3690
3691         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3692
3693         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3694
3695         RTL_W16(CPlusCmd, tp->cp_cmd);
3696
3697         RTL_W16(IntrMitigate, 0x0000);
3698
3699         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3700
3701         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3702         rtl_set_rx_tx_config_registers(tp);
3703
3704         RTL_W8(Cfg9346, Cfg9346_Lock);
3705
3706         RTL_R8(IntrMask);
3707
3708         rtl_set_rx_mode(dev);
3709
3710         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3711
3712         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3713
3714         RTL_W16(IntrMask, tp->intr_event);
3715 }
3716
3717 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3718 {
3719         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3720                 return -EINVAL;
3721
3722         dev->mtu = new_mtu;
3723         return 0;
3724 }
3725
3726 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3727 {
3728         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3729         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3730 }
3731
3732 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
3733                                      void **data_buff, struct RxDesc *desc)
3734 {
3735         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
3736                          DMA_FROM_DEVICE);
3737
3738         kfree(*data_buff);
3739         *data_buff = NULL;
3740         rtl8169_make_unusable_by_asic(desc);
3741 }
3742
3743 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3744 {
3745         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3746
3747         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3748 }
3749
3750 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3751                                        u32 rx_buf_sz)
3752 {
3753         desc->addr = cpu_to_le64(mapping);
3754         wmb();
3755         rtl8169_mark_to_asic(desc, rx_buf_sz);
3756 }
3757
3758 static inline void *rtl8169_align(void *data)
3759 {
3760         return (void *)ALIGN((long)data, 16);
3761 }
3762
3763 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3764                                              struct RxDesc *desc)
3765 {
3766         void *data;
3767         dma_addr_t mapping;
3768         struct device *d = &tp->pci_dev->dev;
3769         struct net_device *dev = tp->dev;
3770         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
3771
3772         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
3773         if (!data)
3774                 return NULL;
3775
3776         if (rtl8169_align(data) != data) {
3777                 kfree(data);
3778                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
3779                 if (!data)
3780                         return NULL;
3781         }
3782
3783         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
3784                                  DMA_FROM_DEVICE);
3785         if (unlikely(dma_mapping_error(d, mapping))) {
3786                 if (net_ratelimit())
3787                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3788                 goto err_out;
3789         }
3790
3791         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
3792         return data;
3793
3794 err_out:
3795         kfree(data);
3796         return NULL;
3797 }
3798
3799 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3800 {
3801         unsigned int i;
3802
3803         for (i = 0; i < NUM_RX_DESC; i++) {
3804                 if (tp->Rx_databuff[i]) {
3805                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
3806                                             tp->RxDescArray + i);
3807                 }
3808         }
3809 }
3810
3811 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3812 {
3813         desc->opts1 |= cpu_to_le32(RingEnd);
3814 }
3815
3816 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3817 {
3818         unsigned int i;
3819
3820         for (i = 0; i < NUM_RX_DESC; i++) {
3821                 void *data;
3822
3823                 if (tp->Rx_databuff[i])
3824                         continue;
3825
3826                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3827                 if (!data) {
3828                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
3829                         goto err_out;
3830                 }
3831                 tp->Rx_databuff[i] = data;
3832         }
3833
3834         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3835         return 0;
3836
3837 err_out:
3838         rtl8169_rx_clear(tp);
3839         return -ENOMEM;
3840 }
3841
3842 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3843 {
3844         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3845 }
3846
3847 static int rtl8169_init_ring(struct net_device *dev)
3848 {
3849         struct rtl8169_private *tp = netdev_priv(dev);
3850
3851         rtl8169_init_ring_indexes(tp);
3852
3853         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3854         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
3855
3856         return rtl8169_rx_fill(tp);
3857 }
3858
3859 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
3860                                  struct TxDesc *desc)
3861 {
3862         unsigned int len = tx_skb->len;
3863
3864         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
3865
3866         desc->opts1 = 0x00;
3867         desc->opts2 = 0x00;
3868         desc->addr = 0x00;
3869         tx_skb->len = 0;
3870 }
3871
3872 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3873                                    unsigned int n)
3874 {
3875         unsigned int i;
3876
3877         for (i = 0; i < n; i++) {
3878                 unsigned int entry = (start + i) % NUM_TX_DESC;
3879                 struct ring_info *tx_skb = tp->tx_skb + entry;
3880                 unsigned int len = tx_skb->len;
3881
3882                 if (len) {
3883                         struct sk_buff *skb = tx_skb->skb;
3884
3885                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
3886                                              tp->TxDescArray + entry);
3887                         if (skb) {
3888                                 tp->dev->stats.tx_dropped++;
3889                                 dev_kfree_skb(skb);
3890                                 tx_skb->skb = NULL;
3891                         }
3892                 }
3893         }
3894 }
3895
3896 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3897 {
3898         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3899         tp->cur_tx = tp->dirty_tx = 0;
3900 }
3901
3902 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
3903 {
3904         struct rtl8169_private *tp = netdev_priv(dev);
3905
3906         PREPARE_DELAYED_WORK(&tp->task, task);
3907         schedule_delayed_work(&tp->task, 4);
3908 }
3909
3910 static void rtl8169_wait_for_quiescence(struct net_device *dev)
3911 {
3912         struct rtl8169_private *tp = netdev_priv(dev);
3913         void __iomem *ioaddr = tp->mmio_addr;
3914
3915         synchronize_irq(dev->irq);
3916
3917         /* Wait for any pending NAPI task to complete */
3918         napi_disable(&tp->napi);
3919
3920         rtl8169_irq_mask_and_ack(ioaddr);
3921
3922         tp->intr_mask = 0xffff;
3923         RTL_W16(IntrMask, tp->intr_event);
3924         napi_enable(&tp->napi);
3925 }
3926
3927 static void rtl8169_reinit_task(struct work_struct *work)
3928 {
3929         struct rtl8169_private *tp =
3930                 container_of(work, struct rtl8169_private, task.work);
3931         struct net_device *dev = tp->dev;
3932         int ret;
3933
3934         rtnl_lock();
3935
3936         if (!netif_running(dev))
3937                 goto out_unlock;
3938
3939         rtl8169_wait_for_quiescence(dev);
3940         rtl8169_close(dev);
3941
3942         ret = rtl8169_open(dev);
3943         if (unlikely(ret < 0)) {
3944                 if (net_ratelimit())
3945                         netif_err(tp, drv, dev,
3946                                   "reinit failure (status = %d). Rescheduling\n",
3947                                   ret);
3948                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3949         }
3950
3951 out_unlock:
3952         rtnl_unlock();
3953 }
3954
3955 static void rtl8169_reset_task(struct work_struct *work)
3956 {
3957         struct rtl8169_private *tp =
3958                 container_of(work, struct rtl8169_private, task.work);
3959         struct net_device *dev = tp->dev;
3960
3961         rtnl_lock();
3962
3963         if (!netif_running(dev))
3964                 goto out_unlock;
3965
3966         rtl8169_wait_for_quiescence(dev);
3967
3968         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
3969         rtl8169_tx_clear(tp);
3970
3971         if (tp->dirty_rx == tp->cur_rx) {
3972                 rtl8169_init_ring_indexes(tp);
3973                 rtl_hw_start(dev);
3974                 netif_wake_queue(dev);
3975                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3976         } else {
3977                 if (net_ratelimit())
3978                         netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
3979                 rtl8169_schedule_work(dev, rtl8169_reset_task);
3980         }
3981
3982 out_unlock:
3983         rtnl_unlock();
3984 }
3985
3986 static void rtl8169_tx_timeout(struct net_device *dev)
3987 {
3988         struct rtl8169_private *tp = netdev_priv(dev);
3989
3990         rtl8169_hw_reset(tp->mmio_addr);
3991
3992         /* Let's wait a bit while any (async) irq lands on */
3993         rtl8169_schedule_work(dev, rtl8169_reset_task);
3994 }
3995
3996 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3997                               u32 opts1)
3998 {
3999         struct skb_shared_info *info = skb_shinfo(skb);
4000         unsigned int cur_frag, entry;
4001         struct TxDesc * uninitialized_var(txd);
4002         struct device *d = &tp->pci_dev->dev;
4003
4004         entry = tp->cur_tx;
4005         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4006                 skb_frag_t *frag = info->frags + cur_frag;
4007                 dma_addr_t mapping;
4008                 u32 status, len;
4009                 void *addr;
4010
4011                 entry = (entry + 1) % NUM_TX_DESC;
4012
4013                 txd = tp->TxDescArray + entry;
4014                 len = frag->size;
4015                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4016                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4017                 if (unlikely(dma_mapping_error(d, mapping))) {
4018                         if (net_ratelimit())
4019                                 netif_err(tp, drv, tp->dev,
4020                                           "Failed to map TX fragments DMA!\n");
4021                         goto err_out;
4022                 }
4023
4024                 /* anti gcc 2.95.3 bugware (sic) */
4025                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4026
4027                 txd->opts1 = cpu_to_le32(status);
4028                 txd->addr = cpu_to_le64(mapping);
4029
4030                 tp->tx_skb[entry].len = len;
4031         }
4032
4033         if (cur_frag) {
4034                 tp->tx_skb[entry].skb = skb;
4035                 txd->opts1 |= cpu_to_le32(LastFrag);
4036         }
4037
4038         return cur_frag;
4039
4040 err_out:
4041         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4042         return -EIO;
4043 }
4044
4045 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4046 {
4047         if (dev->features & NETIF_F_TSO) {
4048                 u32 mss = skb_shinfo(skb)->gso_size;
4049
4050                 if (mss)
4051                         return LargeSend | ((mss & MSSMask) << MSSShift);
4052         }
4053         if (skb->ip_summed == CHECKSUM_PARTIAL) {
4054                 const struct iphdr *ip = ip_hdr(skb);
4055
4056                 if (ip->protocol == IPPROTO_TCP)
4057                         return IPCS | TCPCS;
4058                 else if (ip->protocol == IPPROTO_UDP)
4059                         return IPCS | UDPCS;
4060                 WARN_ON(1);     /* we need a WARN() */
4061         }
4062         return 0;
4063 }
4064
4065 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4066                                       struct net_device *dev)
4067 {
4068         struct rtl8169_private *tp = netdev_priv(dev);
4069         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4070         struct TxDesc *txd = tp->TxDescArray + entry;
4071         void __iomem *ioaddr = tp->mmio_addr;
4072         struct device *d = &tp->pci_dev->dev;
4073         dma_addr_t mapping;
4074         u32 status, len;
4075         u32 opts1;
4076         int frags;
4077
4078         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4079                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4080                 goto err_stop_0;
4081         }
4082
4083         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4084                 goto err_stop_0;
4085
4086         len = skb_headlen(skb);
4087         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4088         if (unlikely(dma_mapping_error(d, mapping))) {
4089                 if (net_ratelimit())
4090                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4091                 goto err_dma_0;
4092         }
4093
4094         tp->tx_skb[entry].len = len;
4095         txd->addr = cpu_to_le64(mapping);
4096         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4097
4098         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4099
4100         frags = rtl8169_xmit_frags(tp, skb, opts1);
4101         if (frags < 0)
4102                 goto err_dma_1;
4103         else if (frags)
4104                 opts1 |= FirstFrag;
4105         else {
4106                 opts1 |= FirstFrag | LastFrag;
4107                 tp->tx_skb[entry].skb = skb;
4108         }
4109
4110         wmb();
4111
4112         /* anti gcc 2.95.3 bugware (sic) */
4113         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4114         txd->opts1 = cpu_to_le32(status);
4115
4116         tp->cur_tx += frags + 1;
4117
4118         wmb();
4119
4120         RTL_W8(TxPoll, NPQ);    /* set polling bit */
4121
4122         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4123                 netif_stop_queue(dev);
4124                 smp_rmb();
4125                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4126                         netif_wake_queue(dev);
4127         }
4128
4129         return NETDEV_TX_OK;
4130
4131 err_dma_1:
4132         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4133 err_dma_0:
4134         dev_kfree_skb(skb);
4135         dev->stats.tx_dropped++;
4136         return NETDEV_TX_OK;
4137
4138 err_stop_0:
4139         netif_stop_queue(dev);
4140         dev->stats.tx_dropped++;
4141         return NETDEV_TX_BUSY;
4142 }
4143
4144 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4145 {
4146         struct rtl8169_private *tp = netdev_priv(dev);
4147         struct pci_dev *pdev = tp->pci_dev;
4148         void __iomem *ioaddr = tp->mmio_addr;
4149         u16 pci_status, pci_cmd;
4150
4151         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4152         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4153
4154         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4155                   pci_cmd, pci_status);
4156
4157         /*
4158          * The recovery sequence below admits a very elaborated explanation:
4159          * - it seems to work;
4160          * - I did not see what else could be done;
4161          * - it makes iop3xx happy.
4162          *
4163          * Feel free to adjust to your needs.
4164          */
4165         if (pdev->broken_parity_status)
4166                 pci_cmd &= ~PCI_COMMAND_PARITY;
4167         else
4168                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4169
4170         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4171
4172         pci_write_config_word(pdev, PCI_STATUS,
4173                 pci_status & (PCI_STATUS_DETECTED_PARITY |
4174                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4175                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4176
4177         /* The infamous DAC f*ckup only happens at boot time */
4178         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4179                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4180                 tp->cp_cmd &= ~PCIDAC;
4181                 RTL_W16(CPlusCmd, tp->cp_cmd);
4182                 dev->features &= ~NETIF_F_HIGHDMA;
4183         }
4184
4185         rtl8169_hw_reset(ioaddr);
4186
4187         rtl8169_schedule_work(dev, rtl8169_reinit_task);
4188 }
4189
4190 static void rtl8169_tx_interrupt(struct net_device *dev,
4191                                  struct rtl8169_private *tp,
4192                                  void __iomem *ioaddr)
4193 {
4194         unsigned int dirty_tx, tx_left;
4195
4196         dirty_tx = tp->dirty_tx;
4197         smp_rmb();
4198         tx_left = tp->cur_tx - dirty_tx;
4199
4200         while (tx_left > 0) {
4201                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4202                 struct ring_info *tx_skb = tp->tx_skb + entry;
4203                 u32 status;
4204
4205                 rmb();
4206                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4207                 if (status & DescOwn)
4208                         break;
4209
4210                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4211                                      tp->TxDescArray + entry);
4212                 if (status & LastFrag) {
4213                         dev->stats.tx_packets++;
4214                         dev->stats.tx_bytes += tx_skb->skb->len;
4215                         dev_kfree_skb(tx_skb->skb);
4216                         tx_skb->skb = NULL;
4217                 }
4218                 dirty_tx++;
4219                 tx_left--;
4220         }
4221
4222         if (tp->dirty_tx != dirty_tx) {
4223                 tp->dirty_tx = dirty_tx;
4224                 smp_wmb();
4225                 if (netif_queue_stopped(dev) &&
4226                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4227                         netif_wake_queue(dev);
4228                 }
4229                 /*
4230                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4231                  * too close. Let's kick an extra TxPoll request when a burst
4232                  * of start_xmit activity is detected (if it is not detected,
4233                  * it is slow enough). -- FR
4234                  */
4235                 smp_rmb();
4236                 if (tp->cur_tx != dirty_tx)
4237                         RTL_W8(TxPoll, NPQ);
4238         }
4239 }
4240
4241 static inline int rtl8169_fragmented_frame(u32 status)
4242 {
4243         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4244 }
4245
4246 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4247 {
4248         u32 status = opts1 & RxProtoMask;
4249
4250         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4251             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4252                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4253         else
4254                 skb_checksum_none_assert(skb);
4255 }
4256
4257 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4258                                            struct rtl8169_private *tp,
4259                                            int pkt_size,
4260                                            dma_addr_t addr)
4261 {
4262         struct sk_buff *skb;
4263         struct device *d = &tp->pci_dev->dev;
4264
4265         data = rtl8169_align(data);
4266         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4267         prefetch(data);
4268         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4269         if (skb)
4270                 memcpy(skb->data, data, pkt_size);
4271         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4272
4273         return skb;
4274 }
4275
4276 /*
4277  * Warning : rtl8169_rx_interrupt() might be called :
4278  * 1) from NAPI (softirq) context
4279  *      (polling = 1 : we should call netif_receive_skb())
4280  * 2) from process context (rtl8169_reset_task())
4281  *      (polling = 0 : we must call netif_rx() instead)
4282  */
4283 static int rtl8169_rx_interrupt(struct net_device *dev,
4284                                 struct rtl8169_private *tp,
4285                                 void __iomem *ioaddr, u32 budget)
4286 {
4287         unsigned int cur_rx, rx_left;
4288         unsigned int count;
4289         int polling = (budget != ~(u32)0) ? 1 : 0;
4290
4291         cur_rx = tp->cur_rx;
4292         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4293         rx_left = min(rx_left, budget);
4294
4295         for (; rx_left > 0; rx_left--, cur_rx++) {
4296                 unsigned int entry = cur_rx % NUM_RX_DESC;
4297                 struct RxDesc *desc = tp->RxDescArray + entry;
4298                 u32 status;
4299
4300                 rmb();
4301                 status = le32_to_cpu(desc->opts1);
4302
4303                 if (status & DescOwn)
4304                         break;
4305                 if (unlikely(status & RxRES)) {
4306                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4307                                    status);
4308                         dev->stats.rx_errors++;
4309                         if (status & (RxRWT | RxRUNT))
4310                                 dev->stats.rx_length_errors++;
4311                         if (status & RxCRC)
4312                                 dev->stats.rx_crc_errors++;
4313                         if (status & RxFOVF) {
4314                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4315                                 dev->stats.rx_fifo_errors++;
4316                         }
4317                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4318                 } else {
4319                         struct sk_buff *skb;
4320                         dma_addr_t addr = le64_to_cpu(desc->addr);
4321                         int pkt_size = (status & 0x00001FFF) - 4;
4322
4323                         /*
4324                          * The driver does not support incoming fragmented
4325                          * frames. They are seen as a symptom of over-mtu
4326                          * sized frames.
4327                          */
4328                         if (unlikely(rtl8169_fragmented_frame(status))) {
4329                                 dev->stats.rx_dropped++;
4330                                 dev->stats.rx_length_errors++;
4331                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
4332                                 continue;
4333                         }
4334
4335                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4336                                                   tp, pkt_size, addr);
4337                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4338                         if (!skb) {
4339                                 dev->stats.rx_dropped++;
4340                                 continue;
4341                         }
4342
4343                         rtl8169_rx_csum(skb, status);
4344                         skb_put(skb, pkt_size);
4345                         skb->protocol = eth_type_trans(skb, dev);
4346
4347                         if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4348                                 if (likely(polling))
4349                                         napi_gro_receive(&tp->napi, skb);
4350                                 else
4351                                         netif_rx(skb);
4352                         }
4353
4354                         dev->stats.rx_bytes += pkt_size;
4355                         dev->stats.rx_packets++;
4356                 }
4357
4358                 /* Work around for AMD plateform. */
4359                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4360                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4361                         desc->opts2 = 0;
4362                         cur_rx++;
4363                 }
4364         }
4365
4366         count = cur_rx - tp->cur_rx;
4367         tp->cur_rx = cur_rx;
4368
4369         tp->dirty_rx += count;
4370
4371         return count;
4372 }
4373
4374 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4375 {
4376         struct net_device *dev = dev_instance;
4377         struct rtl8169_private *tp = netdev_priv(dev);
4378         void __iomem *ioaddr = tp->mmio_addr;
4379         int handled = 0;
4380         int status;
4381
4382         /* loop handling interrupts until we have no new ones or
4383          * we hit a invalid/hotplug case.
4384          */
4385         status = RTL_R16(IntrStatus);
4386         while (status && status != 0xffff) {
4387                 handled = 1;
4388
4389                 /* Handle all of the error cases first. These will reset
4390                  * the chip, so just exit the loop.
4391                  */
4392                 if (unlikely(!netif_running(dev))) {
4393                         rtl8169_asic_down(ioaddr);
4394                         break;
4395                 }
4396
4397                 /* Work around for rx fifo overflow */
4398                 if (unlikely(status & RxFIFOOver) &&
4399                 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4400                         netif_stop_queue(dev);
4401                         rtl8169_tx_timeout(dev);
4402                         break;
4403                 }
4404
4405                 if (unlikely(status & SYSErr)) {
4406                         rtl8169_pcierr_interrupt(dev);
4407                         break;
4408                 }
4409
4410                 if (status & LinkChg)
4411                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
4412
4413                 /* We need to see the lastest version of tp->intr_mask to
4414                  * avoid ignoring an MSI interrupt and having to wait for
4415                  * another event which may never come.
4416                  */
4417                 smp_rmb();
4418                 if (status & tp->intr_mask & tp->napi_event) {
4419                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4420                         tp->intr_mask = ~tp->napi_event;
4421
4422                         if (likely(napi_schedule_prep(&tp->napi)))
4423                                 __napi_schedule(&tp->napi);
4424                         else
4425                                 netif_info(tp, intr, dev,
4426                                            "interrupt %04x in poll\n", status);
4427                 }
4428
4429                 /* We only get a new MSI interrupt when all active irq
4430                  * sources on the chip have been acknowledged. So, ack
4431                  * everything we've seen and check if new sources have become
4432                  * active to avoid blocking all interrupts from the chip.
4433                  */
4434                 RTL_W16(IntrStatus,
4435                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
4436                 status = RTL_R16(IntrStatus);
4437         }
4438
4439         return IRQ_RETVAL(handled);
4440 }
4441
4442 static int rtl8169_poll(struct napi_struct *napi, int budget)
4443 {
4444         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4445         struct net_device *dev = tp->dev;
4446         void __iomem *ioaddr = tp->mmio_addr;
4447         int work_done;
4448
4449         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4450         rtl8169_tx_interrupt(dev, tp, ioaddr);
4451
4452         if (work_done < budget) {
4453                 napi_complete(napi);
4454
4455                 /* We need for force the visibility of tp->intr_mask
4456                  * for other CPUs, as we can loose an MSI interrupt
4457                  * and potentially wait for a retransmit timeout if we don't.
4458                  * The posted write to IntrMask is safe, as it will
4459                  * eventually make it to the chip and we won't loose anything
4460                  * until it does.
4461                  */
4462                 tp->intr_mask = 0xffff;
4463                 wmb();
4464                 RTL_W16(IntrMask, tp->intr_event);
4465         }
4466
4467         return work_done;
4468 }
4469
4470 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4471 {
4472         struct rtl8169_private *tp = netdev_priv(dev);
4473
4474         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4475                 return;
4476
4477         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4478         RTL_W32(RxMissed, 0);
4479 }
4480
4481 static void rtl8169_down(struct net_device *dev)
4482 {
4483         struct rtl8169_private *tp = netdev_priv(dev);
4484         void __iomem *ioaddr = tp->mmio_addr;
4485
4486         rtl8169_delete_timer(dev);
4487
4488         netif_stop_queue(dev);
4489
4490         napi_disable(&tp->napi);
4491
4492         spin_lock_irq(&tp->lock);
4493
4494         rtl8169_asic_down(ioaddr);
4495         /*
4496          * At this point device interrupts can not be enabled in any function,
4497          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4498          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4499          */
4500         rtl8169_rx_missed(dev, ioaddr);
4501
4502         spin_unlock_irq(&tp->lock);
4503
4504         synchronize_irq(dev->irq);
4505
4506         /* Give a racing hard_start_xmit a few cycles to complete. */
4507         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
4508
4509         rtl8169_tx_clear(tp);
4510
4511         rtl8169_rx_clear(tp);
4512
4513         rtl_pll_power_down(tp);
4514 }
4515
4516 static int rtl8169_close(struct net_device *dev)
4517 {
4518         struct rtl8169_private *tp = netdev_priv(dev);
4519         struct pci_dev *pdev = tp->pci_dev;
4520
4521         pm_runtime_get_sync(&pdev->dev);
4522
4523         /* update counters before going down */
4524         rtl8169_update_counters(dev);
4525
4526         rtl8169_down(dev);
4527
4528         free_irq(dev->irq, dev);
4529
4530         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4531                           tp->RxPhyAddr);
4532         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4533                           tp->TxPhyAddr);
4534         tp->TxDescArray = NULL;
4535         tp->RxDescArray = NULL;
4536
4537         pm_runtime_put_sync(&pdev->dev);
4538
4539         return 0;
4540 }
4541
4542 static void rtl_set_rx_mode(struct net_device *dev)
4543 {
4544         struct rtl8169_private *tp = netdev_priv(dev);
4545         void __iomem *ioaddr = tp->mmio_addr;
4546         unsigned long flags;
4547         u32 mc_filter[2];       /* Multicast hash filter */
4548         int rx_mode;
4549         u32 tmp = 0;
4550
4551         if (dev->flags & IFF_PROMISC) {
4552                 /* Unconditionally log net taps. */
4553                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4554                 rx_mode =
4555                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4556                     AcceptAllPhys;
4557                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4558         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4559                    (dev->flags & IFF_ALLMULTI)) {
4560                 /* Too many to filter perfectly -- accept all multicasts. */
4561                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4562                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4563         } else {
4564                 struct netdev_hw_addr *ha;
4565
4566                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4567                 mc_filter[1] = mc_filter[0] = 0;
4568                 netdev_for_each_mc_addr(ha, dev) {
4569                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4570                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4571                         rx_mode |= AcceptMulticast;
4572                 }
4573         }
4574
4575         spin_lock_irqsave(&tp->lock, flags);
4576
4577         tmp = rtl8169_rx_config | rx_mode |
4578               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4579
4580         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4581                 u32 data = mc_filter[0];
4582
4583                 mc_filter[0] = swab32(mc_filter[1]);
4584                 mc_filter[1] = swab32(data);
4585         }
4586
4587         RTL_W32(MAR0 + 4, mc_filter[1]);
4588         RTL_W32(MAR0 + 0, mc_filter[0]);
4589
4590         RTL_W32(RxConfig, tmp);
4591
4592         spin_unlock_irqrestore(&tp->lock, flags);
4593 }
4594
4595 /**
4596  *  rtl8169_get_stats - Get rtl8169 read/write statistics
4597  *  @dev: The Ethernet Device to get statistics for
4598  *
4599  *  Get TX/RX statistics for rtl8169
4600  */
4601 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4602 {
4603         struct rtl8169_private *tp = netdev_priv(dev);
4604         void __iomem *ioaddr = tp->mmio_addr;
4605         unsigned long flags;
4606
4607         if (netif_running(dev)) {
4608                 spin_lock_irqsave(&tp->lock, flags);
4609                 rtl8169_rx_missed(dev, ioaddr);
4610                 spin_unlock_irqrestore(&tp->lock, flags);
4611         }
4612
4613         return &dev->stats;
4614 }
4615
4616 static void rtl8169_net_suspend(struct net_device *dev)
4617 {
4618         struct rtl8169_private *tp = netdev_priv(dev);
4619
4620         if (!netif_running(dev))
4621                 return;
4622
4623         rtl_pll_power_down(tp);
4624
4625         netif_device_detach(dev);
4626         netif_stop_queue(dev);
4627 }
4628
4629 #ifdef CONFIG_PM
4630
4631 static int rtl8169_suspend(struct device *device)
4632 {
4633         struct pci_dev *pdev = to_pci_dev(device);
4634         struct net_device *dev = pci_get_drvdata(pdev);
4635
4636         rtl8169_net_suspend(dev);
4637
4638         return 0;
4639 }
4640
4641 static void __rtl8169_resume(struct net_device *dev)
4642 {
4643         struct rtl8169_private *tp = netdev_priv(dev);
4644
4645         netif_device_attach(dev);
4646
4647         rtl_pll_power_up(tp);
4648
4649         rtl8169_schedule_work(dev, rtl8169_reset_task);
4650 }
4651
4652 static int rtl8169_resume(struct device *device)
4653 {
4654         struct pci_dev *pdev = to_pci_dev(device);
4655         struct net_device *dev = pci_get_drvdata(pdev);
4656         struct rtl8169_private *tp = netdev_priv(dev);
4657
4658         rtl8169_init_phy(dev, tp);
4659
4660         if (netif_running(dev))
4661                 __rtl8169_resume(dev);
4662
4663         return 0;
4664 }
4665
4666 static int rtl8169_runtime_suspend(struct device *device)
4667 {
4668         struct pci_dev *pdev = to_pci_dev(device);
4669         struct net_device *dev = pci_get_drvdata(pdev);
4670         struct rtl8169_private *tp = netdev_priv(dev);
4671
4672         if (!tp->TxDescArray)
4673                 return 0;
4674
4675         spin_lock_irq(&tp->lock);
4676         tp->saved_wolopts = __rtl8169_get_wol(tp);
4677         __rtl8169_set_wol(tp, WAKE_ANY);
4678         spin_unlock_irq(&tp->lock);
4679
4680         rtl8169_net_suspend(dev);
4681
4682         return 0;
4683 }
4684
4685 static int rtl8169_runtime_resume(struct device *device)
4686 {
4687         struct pci_dev *pdev = to_pci_dev(device);
4688         struct net_device *dev = pci_get_drvdata(pdev);
4689         struct rtl8169_private *tp = netdev_priv(dev);
4690
4691         if (!tp->TxDescArray)
4692                 return 0;
4693
4694         spin_lock_irq(&tp->lock);
4695         __rtl8169_set_wol(tp, tp->saved_wolopts);
4696         tp->saved_wolopts = 0;
4697         spin_unlock_irq(&tp->lock);
4698
4699         rtl8169_init_phy(dev, tp);
4700
4701         __rtl8169_resume(dev);
4702
4703         return 0;
4704 }
4705
4706 static int rtl8169_runtime_idle(struct device *device)
4707 {
4708         struct pci_dev *pdev = to_pci_dev(device);
4709         struct net_device *dev = pci_get_drvdata(pdev);
4710         struct rtl8169_private *tp = netdev_priv(dev);
4711
4712         return tp->TxDescArray ? -EBUSY : 0;
4713 }
4714
4715 static const struct dev_pm_ops rtl8169_pm_ops = {
4716         .suspend = rtl8169_suspend,
4717         .resume = rtl8169_resume,
4718         .freeze = rtl8169_suspend,
4719         .thaw = rtl8169_resume,
4720         .poweroff = rtl8169_suspend,
4721         .restore = rtl8169_resume,
4722         .runtime_suspend = rtl8169_runtime_suspend,
4723         .runtime_resume = rtl8169_runtime_resume,
4724         .runtime_idle = rtl8169_runtime_idle,
4725 };
4726
4727 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
4728
4729 #else /* !CONFIG_PM */
4730
4731 #define RTL8169_PM_OPS  NULL
4732
4733 #endif /* !CONFIG_PM */
4734
4735 static void rtl_shutdown(struct pci_dev *pdev)
4736 {
4737         struct net_device *dev = pci_get_drvdata(pdev);
4738         struct rtl8169_private *tp = netdev_priv(dev);
4739         void __iomem *ioaddr = tp->mmio_addr;
4740
4741         rtl8169_net_suspend(dev);
4742
4743         /* restore original MAC address */
4744         rtl_rar_set(tp, dev->perm_addr);
4745
4746         spin_lock_irq(&tp->lock);
4747
4748         rtl8169_asic_down(ioaddr);
4749
4750         spin_unlock_irq(&tp->lock);
4751
4752         if (system_state == SYSTEM_POWER_OFF) {
4753                 /* WoL fails with some 8168 when the receiver is disabled. */
4754                 if (tp->features & RTL_FEATURE_WOL) {
4755                         pci_clear_master(pdev);
4756
4757                         RTL_W8(ChipCmd, CmdRxEnb);
4758                         /* PCI commit */
4759                         RTL_R8(ChipCmd);
4760                 }
4761
4762                 pci_wake_from_d3(pdev, true);
4763                 pci_set_power_state(pdev, PCI_D3hot);
4764         }
4765 }
4766
4767 static struct pci_driver rtl8169_pci_driver = {
4768         .name           = MODULENAME,
4769         .id_table       = rtl8169_pci_tbl,
4770         .probe          = rtl8169_init_one,
4771         .remove         = __devexit_p(rtl8169_remove_one),
4772         .shutdown       = rtl_shutdown,
4773         .driver.pm      = RTL8169_PM_OPS,
4774 };
4775
4776 static int __init rtl8169_init_module(void)
4777 {
4778         return pci_register_driver(&rtl8169_pci_driver);
4779 }
4780
4781 static void __exit rtl8169_cleanup_module(void)
4782 {
4783         pci_unregister_driver(&rtl8169_pci_driver);
4784 }
4785
4786 module_init(rtl8169_init_module);
4787 module_exit(rtl8169_cleanup_module);