net: Remove redundant NAPI functions
[linux-2.6.git] / drivers / net / r8169.c
1 /*
2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3  *
4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6  * Copyright (c) a lot of people too. Please respect their work.
7  *
8  * See MAINTAINERS file for support contact information.
9  */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26
27 #include <asm/system.h>
28 #include <asm/io.h>
29 #include <asm/irq.h>
30
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
34
35 #ifdef RTL8169_DEBUG
36 #define assert(expr) \
37         if (!(expr)) {                                  \
38                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39                 #expr,__FILE__,__func__,__LINE__);              \
40         }
41 #define dprintk(fmt, args...) \
42         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
43 #else
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...)   do {} while (0)
46 #endif /* RTL8169_DEBUG */
47
48 #define R8169_MSG_DEFAULT \
49         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
50
51 #define TX_BUFFS_AVAIL(tp) \
52         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static const int max_interrupt_work = 20;
56
57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
59 static const int multicast_filter_limit = 32;
60
61 /* MAC address length */
62 #define MAC_ADDR_LEN    6
63
64 #define MAX_READ_REQUEST_SHIFT  12
65 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
67 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
68 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
69 #define RxPacketMaxSize 0x3FE8  /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
72
73 #define R8169_REGS_SIZE         256
74 #define R8169_NAPI_WEIGHT       64
75 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
80
81 #define RTL8169_TX_TIMEOUT      (6*HZ)
82 #define RTL8169_PHY_TIMEOUT     (10*HZ)
83
84 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
85 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
86 #define RTL_EEPROM_SIG_ADDR     0x0000
87
88 /* write/read MMIO register */
89 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
90 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
91 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
92 #define RTL_R8(reg)             readb (ioaddr + (reg))
93 #define RTL_R16(reg)            readw (ioaddr + (reg))
94 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
95
96 enum mac_version {
97         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
98         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
99         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
100         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
101         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
102         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
103         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
104         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
105         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
106         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
107         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
108         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
109         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
110         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
111         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
112         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
113         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
114         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
115         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
116         RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
117         RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
118         RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
119         RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
120         RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
121         RTL_GIGA_MAC_VER_25 = 0x19  // 8168D
122 };
123
124 #define _R(NAME,MAC,MASK) \
125         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
126
127 static const struct {
128         const char *name;
129         u8 mac_version;
130         u32 RxConfigMask;       /* Clears the bits supported by this chip */
131 } rtl_chip_info[] = {
132         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
133         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
134         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
135         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
136         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
137         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
138         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
139         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
140         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
141         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
142         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
143         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
144         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
145         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
146         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
147         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
148         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
149         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
150         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
151         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
152         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
153         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
154         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
155         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
156         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_25, 0xff7e1880)  // PCI-E
157 };
158 #undef _R
159
160 enum cfg_version {
161         RTL_CFG_0 = 0x00,
162         RTL_CFG_1,
163         RTL_CFG_2
164 };
165
166 static void rtl_hw_start_8169(struct net_device *);
167 static void rtl_hw_start_8168(struct net_device *);
168 static void rtl_hw_start_8101(struct net_device *);
169
170 static struct pci_device_id rtl8169_pci_tbl[] = {
171         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
172         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
173         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
174         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
175         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
176         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
177         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
178         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
179         { PCI_VENDOR_ID_LINKSYS,                0x1032,
180                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
181         { 0x0001,                               0x8168,
182                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
183         {0,},
184 };
185
186 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
187
188 static int rx_copybreak = 200;
189 static int use_dac;
190 static struct {
191         u32 msg_enable;
192 } debug = { -1 };
193
194 enum rtl_registers {
195         MAC0            = 0,    /* Ethernet hardware address. */
196         MAC4            = 4,
197         MAR0            = 8,    /* Multicast filter. */
198         CounterAddrLow          = 0x10,
199         CounterAddrHigh         = 0x14,
200         TxDescStartAddrLow      = 0x20,
201         TxDescStartAddrHigh     = 0x24,
202         TxHDescStartAddrLow     = 0x28,
203         TxHDescStartAddrHigh    = 0x2c,
204         FLASH           = 0x30,
205         ERSR            = 0x36,
206         ChipCmd         = 0x37,
207         TxPoll          = 0x38,
208         IntrMask        = 0x3c,
209         IntrStatus      = 0x3e,
210         TxConfig        = 0x40,
211         RxConfig        = 0x44,
212         RxMissed        = 0x4c,
213         Cfg9346         = 0x50,
214         Config0         = 0x51,
215         Config1         = 0x52,
216         Config2         = 0x53,
217         Config3         = 0x54,
218         Config4         = 0x55,
219         Config5         = 0x56,
220         MultiIntr       = 0x5c,
221         PHYAR           = 0x60,
222         PHYstatus       = 0x6c,
223         RxMaxSize       = 0xda,
224         CPlusCmd        = 0xe0,
225         IntrMitigate    = 0xe2,
226         RxDescAddrLow   = 0xe4,
227         RxDescAddrHigh  = 0xe8,
228         EarlyTxThres    = 0xec,
229         FuncEvent       = 0xf0,
230         FuncEventMask   = 0xf4,
231         FuncPresetState = 0xf8,
232         FuncForceEvent  = 0xfc,
233 };
234
235 enum rtl8110_registers {
236         TBICSR                  = 0x64,
237         TBI_ANAR                = 0x68,
238         TBI_LPAR                = 0x6a,
239 };
240
241 enum rtl8168_8101_registers {
242         CSIDR                   = 0x64,
243         CSIAR                   = 0x68,
244 #define CSIAR_FLAG                      0x80000000
245 #define CSIAR_WRITE_CMD                 0x80000000
246 #define CSIAR_BYTE_ENABLE               0x0f
247 #define CSIAR_BYTE_ENABLE_SHIFT         12
248 #define CSIAR_ADDR_MASK                 0x0fff
249
250         EPHYAR                  = 0x80,
251 #define EPHYAR_FLAG                     0x80000000
252 #define EPHYAR_WRITE_CMD                0x80000000
253 #define EPHYAR_REG_MASK                 0x1f
254 #define EPHYAR_REG_SHIFT                16
255 #define EPHYAR_DATA_MASK                0xffff
256         DBG_REG                 = 0xd1,
257 #define FIX_NAK_1                       (1 << 4)
258 #define FIX_NAK_2                       (1 << 3)
259 };
260
261 enum rtl_register_content {
262         /* InterruptStatusBits */
263         SYSErr          = 0x8000,
264         PCSTimeout      = 0x4000,
265         SWInt           = 0x0100,
266         TxDescUnavail   = 0x0080,
267         RxFIFOOver      = 0x0040,
268         LinkChg         = 0x0020,
269         RxOverflow      = 0x0010,
270         TxErr           = 0x0008,
271         TxOK            = 0x0004,
272         RxErr           = 0x0002,
273         RxOK            = 0x0001,
274
275         /* RxStatusDesc */
276         RxFOVF  = (1 << 23),
277         RxRWT   = (1 << 22),
278         RxRES   = (1 << 21),
279         RxRUNT  = (1 << 20),
280         RxCRC   = (1 << 19),
281
282         /* ChipCmdBits */
283         CmdReset        = 0x10,
284         CmdRxEnb        = 0x08,
285         CmdTxEnb        = 0x04,
286         RxBufEmpty      = 0x01,
287
288         /* TXPoll register p.5 */
289         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
290         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
291         FSWInt          = 0x01,         /* Forced software interrupt */
292
293         /* Cfg9346Bits */
294         Cfg9346_Lock    = 0x00,
295         Cfg9346_Unlock  = 0xc0,
296
297         /* rx_mode_bits */
298         AcceptErr       = 0x20,
299         AcceptRunt      = 0x10,
300         AcceptBroadcast = 0x08,
301         AcceptMulticast = 0x04,
302         AcceptMyPhys    = 0x02,
303         AcceptAllPhys   = 0x01,
304
305         /* RxConfigBits */
306         RxCfgFIFOShift  = 13,
307         RxCfgDMAShift   =  8,
308
309         /* TxConfigBits */
310         TxInterFrameGapShift = 24,
311         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
312
313         /* Config1 register p.24 */
314         LEDS1           = (1 << 7),
315         LEDS0           = (1 << 6),
316         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
317         Speed_down      = (1 << 4),
318         MEMMAP          = (1 << 3),
319         IOMAP           = (1 << 2),
320         VPD             = (1 << 1),
321         PMEnable        = (1 << 0),     /* Power Management Enable */
322
323         /* Config2 register p. 25 */
324         PCI_Clock_66MHz = 0x01,
325         PCI_Clock_33MHz = 0x00,
326
327         /* Config3 register p.25 */
328         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
329         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
330         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
331
332         /* Config5 register p.27 */
333         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
334         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
335         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
336         LanWake         = (1 << 1),     /* LanWake enable/disable */
337         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
338
339         /* TBICSR p.28 */
340         TBIReset        = 0x80000000,
341         TBILoopback     = 0x40000000,
342         TBINwEnable     = 0x20000000,
343         TBINwRestart    = 0x10000000,
344         TBILinkOk       = 0x02000000,
345         TBINwComplete   = 0x01000000,
346
347         /* CPlusCmd p.31 */
348         EnableBist      = (1 << 15),    // 8168 8101
349         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
350         Normal_mode     = (1 << 13),    // unused
351         Force_half_dup  = (1 << 12),    // 8168 8101
352         Force_rxflow_en = (1 << 11),    // 8168 8101
353         Force_txflow_en = (1 << 10),    // 8168 8101
354         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
355         ASF             = (1 << 8),     // 8168 8101
356         PktCntrDisable  = (1 << 7),     // 8168 8101
357         Mac_dbgo_sel    = 0x001c,       // 8168
358         RxVlan          = (1 << 6),
359         RxChkSum        = (1 << 5),
360         PCIDAC          = (1 << 4),
361         PCIMulRW        = (1 << 3),
362         INTT_0          = 0x0000,       // 8168
363         INTT_1          = 0x0001,       // 8168
364         INTT_2          = 0x0002,       // 8168
365         INTT_3          = 0x0003,       // 8168
366
367         /* rtl8169_PHYstatus */
368         TBI_Enable      = 0x80,
369         TxFlowCtrl      = 0x40,
370         RxFlowCtrl      = 0x20,
371         _1000bpsF       = 0x10,
372         _100bps         = 0x08,
373         _10bps          = 0x04,
374         LinkStatus      = 0x02,
375         FullDup         = 0x01,
376
377         /* _TBICSRBit */
378         TBILinkOK       = 0x02000000,
379
380         /* DumpCounterCommand */
381         CounterDump     = 0x8,
382 };
383
384 enum desc_status_bit {
385         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
386         RingEnd         = (1 << 30), /* End of descriptor ring */
387         FirstFrag       = (1 << 29), /* First segment of a packet */
388         LastFrag        = (1 << 28), /* Final segment of a packet */
389
390         /* Tx private */
391         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
392         MSSShift        = 16,        /* MSS value position */
393         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
394         IPCS            = (1 << 18), /* Calculate IP checksum */
395         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
396         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
397         TxVlanTag       = (1 << 17), /* Add VLAN tag */
398
399         /* Rx private */
400         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
401         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
402
403 #define RxProtoUDP      (PID1)
404 #define RxProtoTCP      (PID0)
405 #define RxProtoIP       (PID1 | PID0)
406 #define RxProtoMask     RxProtoIP
407
408         IPFail          = (1 << 16), /* IP checksum failed */
409         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
410         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
411         RxVlanTag       = (1 << 16), /* VLAN tag available */
412 };
413
414 #define RsvdMask        0x3fffc000
415
416 struct TxDesc {
417         __le32 opts1;
418         __le32 opts2;
419         __le64 addr;
420 };
421
422 struct RxDesc {
423         __le32 opts1;
424         __le32 opts2;
425         __le64 addr;
426 };
427
428 struct ring_info {
429         struct sk_buff  *skb;
430         u32             len;
431         u8              __pad[sizeof(void *) - sizeof(u32)];
432 };
433
434 enum features {
435         RTL_FEATURE_WOL         = (1 << 0),
436         RTL_FEATURE_MSI         = (1 << 1),
437         RTL_FEATURE_GMII        = (1 << 2),
438 };
439
440 struct rtl8169_private {
441         void __iomem *mmio_addr;        /* memory map physical address */
442         struct pci_dev *pci_dev;        /* Index of PCI device */
443         struct net_device *dev;
444         struct napi_struct napi;
445         spinlock_t lock;                /* spin lock flag */
446         u32 msg_enable;
447         int chipset;
448         int mac_version;
449         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
450         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
451         u32 dirty_rx;
452         u32 dirty_tx;
453         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
454         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
455         dma_addr_t TxPhyAddr;
456         dma_addr_t RxPhyAddr;
457         struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
458         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
459         unsigned align;
460         unsigned rx_buf_sz;
461         struct timer_list timer;
462         u16 cp_cmd;
463         u16 intr_event;
464         u16 napi_event;
465         u16 intr_mask;
466         int phy_auto_nego_reg;
467         int phy_1000_ctrl_reg;
468 #ifdef CONFIG_R8169_VLAN
469         struct vlan_group *vlgrp;
470 #endif
471         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
472         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
473         void (*phy_reset_enable)(void __iomem *);
474         void (*hw_start)(struct net_device *);
475         unsigned int (*phy_reset_pending)(void __iomem *);
476         unsigned int (*link_ok)(void __iomem *);
477         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
478         int pcie_cap;
479         struct delayed_work task;
480         unsigned features;
481
482         struct mii_if_info mii;
483 };
484
485 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
486 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
487 module_param(rx_copybreak, int, 0);
488 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
489 module_param(use_dac, int, 0);
490 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
491 module_param_named(debug, debug.msg_enable, int, 0);
492 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
493 MODULE_LICENSE("GPL");
494 MODULE_VERSION(RTL8169_VERSION);
495
496 static int rtl8169_open(struct net_device *dev);
497 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
498 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
499 static int rtl8169_init_ring(struct net_device *dev);
500 static void rtl_hw_start(struct net_device *dev);
501 static int rtl8169_close(struct net_device *dev);
502 static void rtl_set_rx_mode(struct net_device *dev);
503 static void rtl8169_tx_timeout(struct net_device *dev);
504 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
505 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
506                                 void __iomem *, u32 budget);
507 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
508 static void rtl8169_down(struct net_device *dev);
509 static void rtl8169_rx_clear(struct rtl8169_private *tp);
510 static int rtl8169_poll(struct napi_struct *napi, int budget);
511
512 static const unsigned int rtl8169_rx_config =
513         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
514
515 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
516 {
517         int i;
518
519         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
520
521         for (i = 20; i > 0; i--) {
522                 /*
523                  * Check if the RTL8169 has completed writing to the specified
524                  * MII register.
525                  */
526                 if (!(RTL_R32(PHYAR) & 0x80000000))
527                         break;
528                 udelay(25);
529         }
530 }
531
532 static int mdio_read(void __iomem *ioaddr, int reg_addr)
533 {
534         int i, value = -1;
535
536         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
537
538         for (i = 20; i > 0; i--) {
539                 /*
540                  * Check if the RTL8169 has completed retrieving data from
541                  * the specified MII register.
542                  */
543                 if (RTL_R32(PHYAR) & 0x80000000) {
544                         value = RTL_R32(PHYAR) & 0xffff;
545                         break;
546                 }
547                 udelay(25);
548         }
549         return value;
550 }
551
552 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
553 {
554         mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
555 }
556
557 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
558                            int val)
559 {
560         struct rtl8169_private *tp = netdev_priv(dev);
561         void __iomem *ioaddr = tp->mmio_addr;
562
563         mdio_write(ioaddr, location, val);
564 }
565
566 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
567 {
568         struct rtl8169_private *tp = netdev_priv(dev);
569         void __iomem *ioaddr = tp->mmio_addr;
570
571         return mdio_read(ioaddr, location);
572 }
573
574 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
575 {
576         unsigned int i;
577
578         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
579                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
580
581         for (i = 0; i < 100; i++) {
582                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
583                         break;
584                 udelay(10);
585         }
586 }
587
588 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
589 {
590         u16 value = 0xffff;
591         unsigned int i;
592
593         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
594
595         for (i = 0; i < 100; i++) {
596                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
597                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
598                         break;
599                 }
600                 udelay(10);
601         }
602
603         return value;
604 }
605
606 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
607 {
608         unsigned int i;
609
610         RTL_W32(CSIDR, value);
611         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
612                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
613
614         for (i = 0; i < 100; i++) {
615                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
616                         break;
617                 udelay(10);
618         }
619 }
620
621 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
622 {
623         u32 value = ~0x00;
624         unsigned int i;
625
626         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
627                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
628
629         for (i = 0; i < 100; i++) {
630                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
631                         value = RTL_R32(CSIDR);
632                         break;
633                 }
634                 udelay(10);
635         }
636
637         return value;
638 }
639
640 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
641 {
642         RTL_W16(IntrMask, 0x0000);
643
644         RTL_W16(IntrStatus, 0xffff);
645 }
646
647 static void rtl8169_asic_down(void __iomem *ioaddr)
648 {
649         RTL_W8(ChipCmd, 0x00);
650         rtl8169_irq_mask_and_ack(ioaddr);
651         RTL_R16(CPlusCmd);
652 }
653
654 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
655 {
656         return RTL_R32(TBICSR) & TBIReset;
657 }
658
659 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
660 {
661         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
662 }
663
664 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
665 {
666         return RTL_R32(TBICSR) & TBILinkOk;
667 }
668
669 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
670 {
671         return RTL_R8(PHYstatus) & LinkStatus;
672 }
673
674 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
675 {
676         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
677 }
678
679 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
680 {
681         unsigned int val;
682
683         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
684         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
685 }
686
687 static void rtl8169_check_link_status(struct net_device *dev,
688                                       struct rtl8169_private *tp,
689                                       void __iomem *ioaddr)
690 {
691         unsigned long flags;
692
693         spin_lock_irqsave(&tp->lock, flags);
694         if (tp->link_ok(ioaddr)) {
695                 netif_carrier_on(dev);
696                 if (netif_msg_ifup(tp))
697                         printk(KERN_INFO PFX "%s: link up\n", dev->name);
698         } else {
699                 if (netif_msg_ifdown(tp))
700                         printk(KERN_INFO PFX "%s: link down\n", dev->name);
701                 netif_carrier_off(dev);
702         }
703         spin_unlock_irqrestore(&tp->lock, flags);
704 }
705
706 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
707 {
708         struct rtl8169_private *tp = netdev_priv(dev);
709         void __iomem *ioaddr = tp->mmio_addr;
710         u8 options;
711
712         wol->wolopts = 0;
713
714 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
715         wol->supported = WAKE_ANY;
716
717         spin_lock_irq(&tp->lock);
718
719         options = RTL_R8(Config1);
720         if (!(options & PMEnable))
721                 goto out_unlock;
722
723         options = RTL_R8(Config3);
724         if (options & LinkUp)
725                 wol->wolopts |= WAKE_PHY;
726         if (options & MagicPacket)
727                 wol->wolopts |= WAKE_MAGIC;
728
729         options = RTL_R8(Config5);
730         if (options & UWF)
731                 wol->wolopts |= WAKE_UCAST;
732         if (options & BWF)
733                 wol->wolopts |= WAKE_BCAST;
734         if (options & MWF)
735                 wol->wolopts |= WAKE_MCAST;
736
737 out_unlock:
738         spin_unlock_irq(&tp->lock);
739 }
740
741 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
742 {
743         struct rtl8169_private *tp = netdev_priv(dev);
744         void __iomem *ioaddr = tp->mmio_addr;
745         unsigned int i;
746         static struct {
747                 u32 opt;
748                 u16 reg;
749                 u8  mask;
750         } cfg[] = {
751                 { WAKE_ANY,   Config1, PMEnable },
752                 { WAKE_PHY,   Config3, LinkUp },
753                 { WAKE_MAGIC, Config3, MagicPacket },
754                 { WAKE_UCAST, Config5, UWF },
755                 { WAKE_BCAST, Config5, BWF },
756                 { WAKE_MCAST, Config5, MWF },
757                 { WAKE_ANY,   Config5, LanWake }
758         };
759
760         spin_lock_irq(&tp->lock);
761
762         RTL_W8(Cfg9346, Cfg9346_Unlock);
763
764         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
765                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
766                 if (wol->wolopts & cfg[i].opt)
767                         options |= cfg[i].mask;
768                 RTL_W8(cfg[i].reg, options);
769         }
770
771         RTL_W8(Cfg9346, Cfg9346_Lock);
772
773         if (wol->wolopts)
774                 tp->features |= RTL_FEATURE_WOL;
775         else
776                 tp->features &= ~RTL_FEATURE_WOL;
777         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
778
779         spin_unlock_irq(&tp->lock);
780
781         return 0;
782 }
783
784 static void rtl8169_get_drvinfo(struct net_device *dev,
785                                 struct ethtool_drvinfo *info)
786 {
787         struct rtl8169_private *tp = netdev_priv(dev);
788
789         strcpy(info->driver, MODULENAME);
790         strcpy(info->version, RTL8169_VERSION);
791         strcpy(info->bus_info, pci_name(tp->pci_dev));
792 }
793
794 static int rtl8169_get_regs_len(struct net_device *dev)
795 {
796         return R8169_REGS_SIZE;
797 }
798
799 static int rtl8169_set_speed_tbi(struct net_device *dev,
800                                  u8 autoneg, u16 speed, u8 duplex)
801 {
802         struct rtl8169_private *tp = netdev_priv(dev);
803         void __iomem *ioaddr = tp->mmio_addr;
804         int ret = 0;
805         u32 reg;
806
807         reg = RTL_R32(TBICSR);
808         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
809             (duplex == DUPLEX_FULL)) {
810                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
811         } else if (autoneg == AUTONEG_ENABLE)
812                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
813         else {
814                 if (netif_msg_link(tp)) {
815                         printk(KERN_WARNING "%s: "
816                                "incorrect speed setting refused in TBI mode\n",
817                                dev->name);
818                 }
819                 ret = -EOPNOTSUPP;
820         }
821
822         return ret;
823 }
824
825 static int rtl8169_set_speed_xmii(struct net_device *dev,
826                                   u8 autoneg, u16 speed, u8 duplex)
827 {
828         struct rtl8169_private *tp = netdev_priv(dev);
829         void __iomem *ioaddr = tp->mmio_addr;
830         int auto_nego, giga_ctrl;
831
832         auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
833         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
834                        ADVERTISE_100HALF | ADVERTISE_100FULL);
835         giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
836         giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
837
838         if (autoneg == AUTONEG_ENABLE) {
839                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
840                               ADVERTISE_100HALF | ADVERTISE_100FULL);
841                 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
842         } else {
843                 if (speed == SPEED_10)
844                         auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
845                 else if (speed == SPEED_100)
846                         auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
847                 else if (speed == SPEED_1000)
848                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
849
850                 if (duplex == DUPLEX_HALF)
851                         auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
852
853                 if (duplex == DUPLEX_FULL)
854                         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
855
856                 /* This tweak comes straight from Realtek's driver. */
857                 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
858                     ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
859                      (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
860                         auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
861                 }
862         }
863
864         /* The 8100e/8101e/8102e do Fast Ethernet only. */
865         if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
866             (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
867             (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
868             (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
869             (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
870             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
871             (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
872             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
873                 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
874                     netif_msg_link(tp)) {
875                         printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
876                                dev->name);
877                 }
878                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
879         }
880
881         auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
882
883         if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
884             (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
885             (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
886                 /*
887                  * Wake up the PHY.
888                  * Vendor specific (0x1f) and reserved (0x0e) MII registers.
889                  */
890                 mdio_write(ioaddr, 0x1f, 0x0000);
891                 mdio_write(ioaddr, 0x0e, 0x0000);
892         }
893
894         tp->phy_auto_nego_reg = auto_nego;
895         tp->phy_1000_ctrl_reg = giga_ctrl;
896
897         mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
898         mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
899         mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
900         return 0;
901 }
902
903 static int rtl8169_set_speed(struct net_device *dev,
904                              u8 autoneg, u16 speed, u8 duplex)
905 {
906         struct rtl8169_private *tp = netdev_priv(dev);
907         int ret;
908
909         ret = tp->set_speed(dev, autoneg, speed, duplex);
910
911         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
912                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
913
914         return ret;
915 }
916
917 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
918 {
919         struct rtl8169_private *tp = netdev_priv(dev);
920         unsigned long flags;
921         int ret;
922
923         spin_lock_irqsave(&tp->lock, flags);
924         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
925         spin_unlock_irqrestore(&tp->lock, flags);
926
927         return ret;
928 }
929
930 static u32 rtl8169_get_rx_csum(struct net_device *dev)
931 {
932         struct rtl8169_private *tp = netdev_priv(dev);
933
934         return tp->cp_cmd & RxChkSum;
935 }
936
937 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
938 {
939         struct rtl8169_private *tp = netdev_priv(dev);
940         void __iomem *ioaddr = tp->mmio_addr;
941         unsigned long flags;
942
943         spin_lock_irqsave(&tp->lock, flags);
944
945         if (data)
946                 tp->cp_cmd |= RxChkSum;
947         else
948                 tp->cp_cmd &= ~RxChkSum;
949
950         RTL_W16(CPlusCmd, tp->cp_cmd);
951         RTL_R16(CPlusCmd);
952
953         spin_unlock_irqrestore(&tp->lock, flags);
954
955         return 0;
956 }
957
958 #ifdef CONFIG_R8169_VLAN
959
960 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
961                                       struct sk_buff *skb)
962 {
963         return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
964                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
965 }
966
967 static void rtl8169_vlan_rx_register(struct net_device *dev,
968                                      struct vlan_group *grp)
969 {
970         struct rtl8169_private *tp = netdev_priv(dev);
971         void __iomem *ioaddr = tp->mmio_addr;
972         unsigned long flags;
973
974         spin_lock_irqsave(&tp->lock, flags);
975         tp->vlgrp = grp;
976         if (tp->vlgrp)
977                 tp->cp_cmd |= RxVlan;
978         else
979                 tp->cp_cmd &= ~RxVlan;
980         RTL_W16(CPlusCmd, tp->cp_cmd);
981         RTL_R16(CPlusCmd);
982         spin_unlock_irqrestore(&tp->lock, flags);
983 }
984
985 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
986                                struct sk_buff *skb)
987 {
988         u32 opts2 = le32_to_cpu(desc->opts2);
989         struct vlan_group *vlgrp = tp->vlgrp;
990         int ret;
991
992         if (vlgrp && (opts2 & RxVlanTag)) {
993                 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
994                 ret = 0;
995         } else
996                 ret = -1;
997         desc->opts2 = 0;
998         return ret;
999 }
1000
1001 #else /* !CONFIG_R8169_VLAN */
1002
1003 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1004                                       struct sk_buff *skb)
1005 {
1006         return 0;
1007 }
1008
1009 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1010                                struct sk_buff *skb)
1011 {
1012         return -1;
1013 }
1014
1015 #endif
1016
1017 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1018 {
1019         struct rtl8169_private *tp = netdev_priv(dev);
1020         void __iomem *ioaddr = tp->mmio_addr;
1021         u32 status;
1022
1023         cmd->supported =
1024                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1025         cmd->port = PORT_FIBRE;
1026         cmd->transceiver = XCVR_INTERNAL;
1027
1028         status = RTL_R32(TBICSR);
1029         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1030         cmd->autoneg = !!(status & TBINwEnable);
1031
1032         cmd->speed = SPEED_1000;
1033         cmd->duplex = DUPLEX_FULL; /* Always set */
1034
1035         return 0;
1036 }
1037
1038 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1039 {
1040         struct rtl8169_private *tp = netdev_priv(dev);
1041
1042         return mii_ethtool_gset(&tp->mii, cmd);
1043 }
1044
1045 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1046 {
1047         struct rtl8169_private *tp = netdev_priv(dev);
1048         unsigned long flags;
1049         int rc;
1050
1051         spin_lock_irqsave(&tp->lock, flags);
1052
1053         rc = tp->get_settings(dev, cmd);
1054
1055         spin_unlock_irqrestore(&tp->lock, flags);
1056         return rc;
1057 }
1058
1059 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1060                              void *p)
1061 {
1062         struct rtl8169_private *tp = netdev_priv(dev);
1063         unsigned long flags;
1064
1065         if (regs->len > R8169_REGS_SIZE)
1066                 regs->len = R8169_REGS_SIZE;
1067
1068         spin_lock_irqsave(&tp->lock, flags);
1069         memcpy_fromio(p, tp->mmio_addr, regs->len);
1070         spin_unlock_irqrestore(&tp->lock, flags);
1071 }
1072
1073 static u32 rtl8169_get_msglevel(struct net_device *dev)
1074 {
1075         struct rtl8169_private *tp = netdev_priv(dev);
1076
1077         return tp->msg_enable;
1078 }
1079
1080 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1081 {
1082         struct rtl8169_private *tp = netdev_priv(dev);
1083
1084         tp->msg_enable = value;
1085 }
1086
1087 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1088         "tx_packets",
1089         "rx_packets",
1090         "tx_errors",
1091         "rx_errors",
1092         "rx_missed",
1093         "align_errors",
1094         "tx_single_collisions",
1095         "tx_multi_collisions",
1096         "unicast",
1097         "broadcast",
1098         "multicast",
1099         "tx_aborted",
1100         "tx_underrun",
1101 };
1102
1103 struct rtl8169_counters {
1104         __le64  tx_packets;
1105         __le64  rx_packets;
1106         __le64  tx_errors;
1107         __le32  rx_errors;
1108         __le16  rx_missed;
1109         __le16  align_errors;
1110         __le32  tx_one_collision;
1111         __le32  tx_multi_collision;
1112         __le64  rx_unicast;
1113         __le64  rx_broadcast;
1114         __le32  rx_multicast;
1115         __le16  tx_aborted;
1116         __le16  tx_underun;
1117 };
1118
1119 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1120 {
1121         switch (sset) {
1122         case ETH_SS_STATS:
1123                 return ARRAY_SIZE(rtl8169_gstrings);
1124         default:
1125                 return -EOPNOTSUPP;
1126         }
1127 }
1128
1129 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1130                                       struct ethtool_stats *stats, u64 *data)
1131 {
1132         struct rtl8169_private *tp = netdev_priv(dev);
1133         void __iomem *ioaddr = tp->mmio_addr;
1134         struct rtl8169_counters *counters;
1135         dma_addr_t paddr;
1136         u32 cmd;
1137
1138         ASSERT_RTNL();
1139
1140         counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1141         if (!counters)
1142                 return;
1143
1144         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1145         cmd = (u64)paddr & DMA_32BIT_MASK;
1146         RTL_W32(CounterAddrLow, cmd);
1147         RTL_W32(CounterAddrLow, cmd | CounterDump);
1148
1149         while (RTL_R32(CounterAddrLow) & CounterDump) {
1150                 if (msleep_interruptible(1))
1151                         break;
1152         }
1153
1154         RTL_W32(CounterAddrLow, 0);
1155         RTL_W32(CounterAddrHigh, 0);
1156
1157         data[0] = le64_to_cpu(counters->tx_packets);
1158         data[1] = le64_to_cpu(counters->rx_packets);
1159         data[2] = le64_to_cpu(counters->tx_errors);
1160         data[3] = le32_to_cpu(counters->rx_errors);
1161         data[4] = le16_to_cpu(counters->rx_missed);
1162         data[5] = le16_to_cpu(counters->align_errors);
1163         data[6] = le32_to_cpu(counters->tx_one_collision);
1164         data[7] = le32_to_cpu(counters->tx_multi_collision);
1165         data[8] = le64_to_cpu(counters->rx_unicast);
1166         data[9] = le64_to_cpu(counters->rx_broadcast);
1167         data[10] = le32_to_cpu(counters->rx_multicast);
1168         data[11] = le16_to_cpu(counters->tx_aborted);
1169         data[12] = le16_to_cpu(counters->tx_underun);
1170
1171         pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1172 }
1173
1174 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1175 {
1176         switch(stringset) {
1177         case ETH_SS_STATS:
1178                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1179                 break;
1180         }
1181 }
1182
1183 static const struct ethtool_ops rtl8169_ethtool_ops = {
1184         .get_drvinfo            = rtl8169_get_drvinfo,
1185         .get_regs_len           = rtl8169_get_regs_len,
1186         .get_link               = ethtool_op_get_link,
1187         .get_settings           = rtl8169_get_settings,
1188         .set_settings           = rtl8169_set_settings,
1189         .get_msglevel           = rtl8169_get_msglevel,
1190         .set_msglevel           = rtl8169_set_msglevel,
1191         .get_rx_csum            = rtl8169_get_rx_csum,
1192         .set_rx_csum            = rtl8169_set_rx_csum,
1193         .set_tx_csum            = ethtool_op_set_tx_csum,
1194         .set_sg                 = ethtool_op_set_sg,
1195         .set_tso                = ethtool_op_set_tso,
1196         .get_regs               = rtl8169_get_regs,
1197         .get_wol                = rtl8169_get_wol,
1198         .set_wol                = rtl8169_set_wol,
1199         .get_strings            = rtl8169_get_strings,
1200         .get_sset_count         = rtl8169_get_sset_count,
1201         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1202 };
1203
1204 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1205                                        int bitnum, int bitval)
1206 {
1207         int val;
1208
1209         val = mdio_read(ioaddr, reg);
1210         val = (bitval == 1) ?
1211                 val | (bitval << bitnum) :  val & ~(0x0001 << bitnum);
1212         mdio_write(ioaddr, reg, val & 0xffff);
1213 }
1214
1215 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1216                                     void __iomem *ioaddr)
1217 {
1218         /*
1219          * The driver currently handles the 8168Bf and the 8168Be identically
1220          * but they can be identified more specifically through the test below
1221          * if needed:
1222          *
1223          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1224          *
1225          * Same thing for the 8101Eb and the 8101Ec:
1226          *
1227          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1228          */
1229         const struct {
1230                 u32 mask;
1231                 u32 val;
1232                 int mac_version;
1233         } mac_info[] = {
1234                 /* 8168D family. */
1235                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_25 },
1236
1237                 /* 8168C family. */
1238                 { 0x7cf00000, 0x3ca00000,       RTL_GIGA_MAC_VER_24 },
1239                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1240                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1241                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1242                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1243                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1244                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1245                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1246                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1247
1248                 /* 8168B family. */
1249                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1250                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1251                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1252                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1253
1254                 /* 8101 family. */
1255                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1256                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1257                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1258                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1259                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1260                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1261                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1262                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1263                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1264                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1265                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1266                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1267                 /* FIXME: where did these entries come from ? -- FR */
1268                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1269                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1270
1271                 /* 8110 family. */
1272                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1273                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1274                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1275                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1276                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1277                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1278
1279                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_VER_01 }   /* Catch-all */
1280         }, *p = mac_info;
1281         u32 reg;
1282
1283         reg = RTL_R32(TxConfig);
1284         while ((reg & p->mask) != p->val)
1285                 p++;
1286         tp->mac_version = p->mac_version;
1287
1288         if (p->mask == 0x00000000) {
1289                 struct pci_dev *pdev = tp->pci_dev;
1290
1291                 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1292         }
1293 }
1294
1295 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1296 {
1297         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1298 }
1299
1300 struct phy_reg {
1301         u16 reg;
1302         u16 val;
1303 };
1304
1305 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1306 {
1307         while (len-- > 0) {
1308                 mdio_write(ioaddr, regs->reg, regs->val);
1309                 regs++;
1310         }
1311 }
1312
1313 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1314 {
1315         struct {
1316                 u16 regs[5]; /* Beware of bit-sign propagation */
1317         } phy_magic[5] = { {
1318                 { 0x0000,       //w 4 15 12 0
1319                   0x00a1,       //w 3 15 0 00a1
1320                   0x0008,       //w 2 15 0 0008
1321                   0x1020,       //w 1 15 0 1020
1322                   0x1000 } },{  //w 0 15 0 1000
1323                 { 0x7000,       //w 4 15 12 7
1324                   0xff41,       //w 3 15 0 ff41
1325                   0xde60,       //w 2 15 0 de60
1326                   0x0140,       //w 1 15 0 0140
1327                   0x0077 } },{  //w 0 15 0 0077
1328                 { 0xa000,       //w 4 15 12 a
1329                   0xdf01,       //w 3 15 0 df01
1330                   0xdf20,       //w 2 15 0 df20
1331                   0xff95,       //w 1 15 0 ff95
1332                   0xfa00 } },{  //w 0 15 0 fa00
1333                 { 0xb000,       //w 4 15 12 b
1334                   0xff41,       //w 3 15 0 ff41
1335                   0xde20,       //w 2 15 0 de20
1336                   0x0140,       //w 1 15 0 0140
1337                   0x00bb } },{  //w 0 15 0 00bb
1338                 { 0xf000,       //w 4 15 12 f
1339                   0xdf01,       //w 3 15 0 df01
1340                   0xdf20,       //w 2 15 0 df20
1341                   0xff95,       //w 1 15 0 ff95
1342                   0xbf00 }      //w 0 15 0 bf00
1343                 }
1344         }, *p = phy_magic;
1345         unsigned int i;
1346
1347         mdio_write(ioaddr, 0x1f, 0x0001);               //w 31 2 0 1
1348         mdio_write(ioaddr, 0x15, 0x1000);               //w 21 15 0 1000
1349         mdio_write(ioaddr, 0x18, 0x65c7);               //w 24 15 0 65c7
1350         rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
1351
1352         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1353                 int val, pos = 4;
1354
1355                 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1356                 mdio_write(ioaddr, pos, val);
1357                 while (--pos >= 0)
1358                         mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1359                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1360                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1361         }
1362         mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1363 }
1364
1365 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1366 {
1367         struct phy_reg phy_reg_init[] = {
1368                 { 0x1f, 0x0002 },
1369                 { 0x01, 0x90d0 },
1370                 { 0x1f, 0x0000 }
1371         };
1372
1373         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1374 }
1375
1376 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1377 {
1378         struct phy_reg phy_reg_init[] = {
1379                 { 0x10, 0xf41b },
1380                 { 0x1f, 0x0000 }
1381         };
1382
1383         mdio_write(ioaddr, 0x1f, 0x0001);
1384         mdio_patch(ioaddr, 0x16, 1 << 0);
1385
1386         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1387 }
1388
1389 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1390 {
1391         struct phy_reg phy_reg_init[] = {
1392                 { 0x1f, 0x0001 },
1393                 { 0x10, 0xf41b },
1394                 { 0x1f, 0x0000 }
1395         };
1396
1397         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1398 }
1399
1400 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1401 {
1402         struct phy_reg phy_reg_init[] = {
1403                 { 0x1f, 0x0000 },
1404                 { 0x1d, 0x0f00 },
1405                 { 0x1f, 0x0002 },
1406                 { 0x0c, 0x1ec8 },
1407                 { 0x1f, 0x0000 }
1408         };
1409
1410         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1411 }
1412
1413 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1414 {
1415         struct phy_reg phy_reg_init[] = {
1416                 { 0x1f, 0x0001 },
1417                 { 0x1d, 0x3d98 },
1418                 { 0x1f, 0x0000 }
1419         };
1420
1421         mdio_write(ioaddr, 0x1f, 0x0000);
1422         mdio_patch(ioaddr, 0x14, 1 << 5);
1423         mdio_patch(ioaddr, 0x0d, 1 << 5);
1424
1425         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1426 }
1427
1428 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1429 {
1430         struct phy_reg phy_reg_init[] = {
1431                 { 0x1f, 0x0001 },
1432                 { 0x12, 0x2300 },
1433                 { 0x1f, 0x0002 },
1434                 { 0x00, 0x88d4 },
1435                 { 0x01, 0x82b1 },
1436                 { 0x03, 0x7002 },
1437                 { 0x08, 0x9e30 },
1438                 { 0x09, 0x01f0 },
1439                 { 0x0a, 0x5500 },
1440                 { 0x0c, 0x00c8 },
1441                 { 0x1f, 0x0003 },
1442                 { 0x12, 0xc096 },
1443                 { 0x16, 0x000a },
1444                 { 0x1f, 0x0000 },
1445                 { 0x1f, 0x0000 },
1446                 { 0x09, 0x2000 },
1447                 { 0x09, 0x0000 }
1448         };
1449
1450         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1451
1452         mdio_patch(ioaddr, 0x14, 1 << 5);
1453         mdio_patch(ioaddr, 0x0d, 1 << 5);
1454         mdio_write(ioaddr, 0x1f, 0x0000);
1455 }
1456
1457 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1458 {
1459         struct phy_reg phy_reg_init[] = {
1460                 { 0x1f, 0x0001 },
1461                 { 0x12, 0x2300 },
1462                 { 0x03, 0x802f },
1463                 { 0x02, 0x4f02 },
1464                 { 0x01, 0x0409 },
1465                 { 0x00, 0xf099 },
1466                 { 0x04, 0x9800 },
1467                 { 0x04, 0x9000 },
1468                 { 0x1d, 0x3d98 },
1469                 { 0x1f, 0x0002 },
1470                 { 0x0c, 0x7eb8 },
1471                 { 0x06, 0x0761 },
1472                 { 0x1f, 0x0003 },
1473                 { 0x16, 0x0f0a },
1474                 { 0x1f, 0x0000 }
1475         };
1476
1477         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1478
1479         mdio_patch(ioaddr, 0x16, 1 << 0);
1480         mdio_patch(ioaddr, 0x14, 1 << 5);
1481         mdio_patch(ioaddr, 0x0d, 1 << 5);
1482         mdio_write(ioaddr, 0x1f, 0x0000);
1483 }
1484
1485 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1486 {
1487         struct phy_reg phy_reg_init[] = {
1488                 { 0x1f, 0x0001 },
1489                 { 0x12, 0x2300 },
1490                 { 0x1d, 0x3d98 },
1491                 { 0x1f, 0x0002 },
1492                 { 0x0c, 0x7eb8 },
1493                 { 0x06, 0x5461 },
1494                 { 0x1f, 0x0003 },
1495                 { 0x16, 0x0f0a },
1496                 { 0x1f, 0x0000 }
1497         };
1498
1499         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1500
1501         mdio_patch(ioaddr, 0x16, 1 << 0);
1502         mdio_patch(ioaddr, 0x14, 1 << 5);
1503         mdio_patch(ioaddr, 0x0d, 1 << 5);
1504         mdio_write(ioaddr, 0x1f, 0x0000);
1505 }
1506
1507 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1508 {
1509         rtl8168c_3_hw_phy_config(ioaddr);
1510 }
1511
1512 static void rtl8168d_hw_phy_config(void __iomem *ioaddr)
1513 {
1514         struct phy_reg phy_reg_init_0[] = {
1515                 { 0x1f, 0x0001 },
1516                 { 0x09, 0x2770 },
1517                 { 0x08, 0x04d0 },
1518                 { 0x0b, 0xad15 },
1519                 { 0x0c, 0x5bf0 },
1520                 { 0x1c, 0xf101 },
1521                 { 0x1f, 0x0003 },
1522                 { 0x14, 0x94d7 },
1523                 { 0x12, 0xf4d6 },
1524                 { 0x09, 0xca0f },
1525                 { 0x1f, 0x0002 },
1526                 { 0x0b, 0x0b10 },
1527                 { 0x0c, 0xd1f7 },
1528                 { 0x1f, 0x0002 },
1529                 { 0x06, 0x5461 },
1530                 { 0x1f, 0x0002 },
1531                 { 0x05, 0x6662 },
1532                 { 0x1f, 0x0000 },
1533                 { 0x14, 0x0060 },
1534                 { 0x1f, 0x0000 },
1535                 { 0x0d, 0xf8a0 },
1536                 { 0x1f, 0x0005 },
1537                 { 0x05, 0xffc2 }
1538         };
1539
1540         rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
1541
1542         if (mdio_read(ioaddr, 0x06) == 0xc400) {
1543                 struct phy_reg phy_reg_init_1[] = {
1544                         { 0x1f, 0x0005 },
1545                         { 0x01, 0x0300 },
1546                         { 0x1f, 0x0000 },
1547                         { 0x11, 0x401c },
1548                         { 0x16, 0x4100 },
1549                         { 0x1f, 0x0005 },
1550                         { 0x07, 0x0010 },
1551                         { 0x05, 0x83dc },
1552                         { 0x06, 0x087d },
1553                         { 0x05, 0x8300 },
1554                         { 0x06, 0x0101 },
1555                         { 0x06, 0x05f8 },
1556                         { 0x06, 0xf9fa },
1557                         { 0x06, 0xfbef },
1558                         { 0x06, 0x79e2 },
1559                         { 0x06, 0x835f },
1560                         { 0x06, 0xe0f8 },
1561                         { 0x06, 0x9ae1 },
1562                         { 0x06, 0xf89b },
1563                         { 0x06, 0xef31 },
1564                         { 0x06, 0x3b65 },
1565                         { 0x06, 0xaa07 },
1566                         { 0x06, 0x81e4 },
1567                         { 0x06, 0xf89a },
1568                         { 0x06, 0xe5f8 },
1569                         { 0x06, 0x9baf },
1570                         { 0x06, 0x06ae },
1571                         { 0x05, 0x83dc },
1572                         { 0x06, 0x8300 },
1573                 };
1574
1575                 rtl_phy_write(ioaddr, phy_reg_init_1,
1576                               ARRAY_SIZE(phy_reg_init_1));
1577         }
1578
1579         mdio_write(ioaddr, 0x1f, 0x0000);
1580 }
1581
1582 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1583 {
1584         struct phy_reg phy_reg_init[] = {
1585                 { 0x1f, 0x0003 },
1586                 { 0x08, 0x441d },
1587                 { 0x01, 0x9100 },
1588                 { 0x1f, 0x0000 }
1589         };
1590
1591         mdio_write(ioaddr, 0x1f, 0x0000);
1592         mdio_patch(ioaddr, 0x11, 1 << 12);
1593         mdio_patch(ioaddr, 0x19, 1 << 13);
1594
1595         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1596 }
1597
1598 static void rtl_hw_phy_config(struct net_device *dev)
1599 {
1600         struct rtl8169_private *tp = netdev_priv(dev);
1601         void __iomem *ioaddr = tp->mmio_addr;
1602
1603         rtl8169_print_mac_version(tp);
1604
1605         switch (tp->mac_version) {
1606         case RTL_GIGA_MAC_VER_01:
1607                 break;
1608         case RTL_GIGA_MAC_VER_02:
1609         case RTL_GIGA_MAC_VER_03:
1610                 rtl8169s_hw_phy_config(ioaddr);
1611                 break;
1612         case RTL_GIGA_MAC_VER_04:
1613                 rtl8169sb_hw_phy_config(ioaddr);
1614                 break;
1615         case RTL_GIGA_MAC_VER_07:
1616         case RTL_GIGA_MAC_VER_08:
1617         case RTL_GIGA_MAC_VER_09:
1618                 rtl8102e_hw_phy_config(ioaddr);
1619                 break;
1620         case RTL_GIGA_MAC_VER_11:
1621                 rtl8168bb_hw_phy_config(ioaddr);
1622                 break;
1623         case RTL_GIGA_MAC_VER_12:
1624                 rtl8168bef_hw_phy_config(ioaddr);
1625                 break;
1626         case RTL_GIGA_MAC_VER_17:
1627                 rtl8168bef_hw_phy_config(ioaddr);
1628                 break;
1629         case RTL_GIGA_MAC_VER_18:
1630                 rtl8168cp_1_hw_phy_config(ioaddr);
1631                 break;
1632         case RTL_GIGA_MAC_VER_19:
1633                 rtl8168c_1_hw_phy_config(ioaddr);
1634                 break;
1635         case RTL_GIGA_MAC_VER_20:
1636                 rtl8168c_2_hw_phy_config(ioaddr);
1637                 break;
1638         case RTL_GIGA_MAC_VER_21:
1639                 rtl8168c_3_hw_phy_config(ioaddr);
1640                 break;
1641         case RTL_GIGA_MAC_VER_22:
1642                 rtl8168c_4_hw_phy_config(ioaddr);
1643                 break;
1644         case RTL_GIGA_MAC_VER_23:
1645         case RTL_GIGA_MAC_VER_24:
1646                 rtl8168cp_2_hw_phy_config(ioaddr);
1647                 break;
1648         case RTL_GIGA_MAC_VER_25:
1649                 rtl8168d_hw_phy_config(ioaddr);
1650                 break;
1651
1652         default:
1653                 break;
1654         }
1655 }
1656
1657 static void rtl8169_phy_timer(unsigned long __opaque)
1658 {
1659         struct net_device *dev = (struct net_device *)__opaque;
1660         struct rtl8169_private *tp = netdev_priv(dev);
1661         struct timer_list *timer = &tp->timer;
1662         void __iomem *ioaddr = tp->mmio_addr;
1663         unsigned long timeout = RTL8169_PHY_TIMEOUT;
1664
1665         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1666
1667         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1668                 return;
1669
1670         spin_lock_irq(&tp->lock);
1671
1672         if (tp->phy_reset_pending(ioaddr)) {
1673                 /*
1674                  * A busy loop could burn quite a few cycles on nowadays CPU.
1675                  * Let's delay the execution of the timer for a few ticks.
1676                  */
1677                 timeout = HZ/10;
1678                 goto out_mod_timer;
1679         }
1680
1681         if (tp->link_ok(ioaddr))
1682                 goto out_unlock;
1683
1684         if (netif_msg_link(tp))
1685                 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1686
1687         tp->phy_reset_enable(ioaddr);
1688
1689 out_mod_timer:
1690         mod_timer(timer, jiffies + timeout);
1691 out_unlock:
1692         spin_unlock_irq(&tp->lock);
1693 }
1694
1695 static inline void rtl8169_delete_timer(struct net_device *dev)
1696 {
1697         struct rtl8169_private *tp = netdev_priv(dev);
1698         struct timer_list *timer = &tp->timer;
1699
1700         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1701                 return;
1702
1703         del_timer_sync(timer);
1704 }
1705
1706 static inline void rtl8169_request_timer(struct net_device *dev)
1707 {
1708         struct rtl8169_private *tp = netdev_priv(dev);
1709         struct timer_list *timer = &tp->timer;
1710
1711         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1712                 return;
1713
1714         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1715 }
1716
1717 #ifdef CONFIG_NET_POLL_CONTROLLER
1718 /*
1719  * Polling 'interrupt' - used by things like netconsole to send skbs
1720  * without having to re-enable interrupts. It's not called while
1721  * the interrupt routine is executing.
1722  */
1723 static void rtl8169_netpoll(struct net_device *dev)
1724 {
1725         struct rtl8169_private *tp = netdev_priv(dev);
1726         struct pci_dev *pdev = tp->pci_dev;
1727
1728         disable_irq(pdev->irq);
1729         rtl8169_interrupt(pdev->irq, dev);
1730         enable_irq(pdev->irq);
1731 }
1732 #endif
1733
1734 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1735                                   void __iomem *ioaddr)
1736 {
1737         iounmap(ioaddr);
1738         pci_release_regions(pdev);
1739         pci_disable_device(pdev);
1740         free_netdev(dev);
1741 }
1742
1743 static void rtl8169_phy_reset(struct net_device *dev,
1744                               struct rtl8169_private *tp)
1745 {
1746         void __iomem *ioaddr = tp->mmio_addr;
1747         unsigned int i;
1748
1749         tp->phy_reset_enable(ioaddr);
1750         for (i = 0; i < 100; i++) {
1751                 if (!tp->phy_reset_pending(ioaddr))
1752                         return;
1753                 msleep(1);
1754         }
1755         if (netif_msg_link(tp))
1756                 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1757 }
1758
1759 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1760 {
1761         void __iomem *ioaddr = tp->mmio_addr;
1762
1763         rtl_hw_phy_config(dev);
1764
1765         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1766                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1767                 RTL_W8(0x82, 0x01);
1768         }
1769
1770         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1771
1772         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1773                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1774
1775         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1776                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1777                 RTL_W8(0x82, 0x01);
1778                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1779                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1780         }
1781
1782         rtl8169_phy_reset(dev, tp);
1783
1784         /*
1785          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1786          * only 8101. Don't panic.
1787          */
1788         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1789
1790         if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1791                 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1792 }
1793
1794 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1795 {
1796         void __iomem *ioaddr = tp->mmio_addr;
1797         u32 high;
1798         u32 low;
1799
1800         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1801         high = addr[4] | (addr[5] << 8);
1802
1803         spin_lock_irq(&tp->lock);
1804
1805         RTL_W8(Cfg9346, Cfg9346_Unlock);
1806         RTL_W32(MAC0, low);
1807         RTL_W32(MAC4, high);
1808         RTL_W8(Cfg9346, Cfg9346_Lock);
1809
1810         spin_unlock_irq(&tp->lock);
1811 }
1812
1813 static int rtl_set_mac_address(struct net_device *dev, void *p)
1814 {
1815         struct rtl8169_private *tp = netdev_priv(dev);
1816         struct sockaddr *addr = p;
1817
1818         if (!is_valid_ether_addr(addr->sa_data))
1819                 return -EADDRNOTAVAIL;
1820
1821         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1822
1823         rtl_rar_set(tp, dev->dev_addr);
1824
1825         return 0;
1826 }
1827
1828 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1829 {
1830         struct rtl8169_private *tp = netdev_priv(dev);
1831         struct mii_ioctl_data *data = if_mii(ifr);
1832
1833         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
1834 }
1835
1836 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1837 {
1838         switch (cmd) {
1839         case SIOCGMIIPHY:
1840                 data->phy_id = 32; /* Internal PHY */
1841                 return 0;
1842
1843         case SIOCGMIIREG:
1844                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1845                 return 0;
1846
1847         case SIOCSMIIREG:
1848                 if (!capable(CAP_NET_ADMIN))
1849                         return -EPERM;
1850                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1851                 return 0;
1852         }
1853         return -EOPNOTSUPP;
1854 }
1855
1856 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1857 {
1858         return -EOPNOTSUPP;
1859 }
1860
1861 static const struct rtl_cfg_info {
1862         void (*hw_start)(struct net_device *);
1863         unsigned int region;
1864         unsigned int align;
1865         u16 intr_event;
1866         u16 napi_event;
1867         unsigned features;
1868 } rtl_cfg_infos [] = {
1869         [RTL_CFG_0] = {
1870                 .hw_start       = rtl_hw_start_8169,
1871                 .region         = 1,
1872                 .align          = 0,
1873                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1874                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1875                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1876                 .features       = RTL_FEATURE_GMII
1877         },
1878         [RTL_CFG_1] = {
1879                 .hw_start       = rtl_hw_start_8168,
1880                 .region         = 2,
1881                 .align          = 8,
1882                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1883                                   TxErr | TxOK | RxOK | RxErr,
1884                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
1885                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI
1886         },
1887         [RTL_CFG_2] = {
1888                 .hw_start       = rtl_hw_start_8101,
1889                 .region         = 2,
1890                 .align          = 8,
1891                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1892                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1893                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1894                 .features       = RTL_FEATURE_MSI
1895         }
1896 };
1897
1898 /* Cfg9346_Unlock assumed. */
1899 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1900                             const struct rtl_cfg_info *cfg)
1901 {
1902         unsigned msi = 0;
1903         u8 cfg2;
1904
1905         cfg2 = RTL_R8(Config2) & ~MSIEnable;
1906         if (cfg->features & RTL_FEATURE_MSI) {
1907                 if (pci_enable_msi(pdev)) {
1908                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1909                 } else {
1910                         cfg2 |= MSIEnable;
1911                         msi = RTL_FEATURE_MSI;
1912                 }
1913         }
1914         RTL_W8(Config2, cfg2);
1915         return msi;
1916 }
1917
1918 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1919 {
1920         if (tp->features & RTL_FEATURE_MSI) {
1921                 pci_disable_msi(pdev);
1922                 tp->features &= ~RTL_FEATURE_MSI;
1923         }
1924 }
1925
1926 static const struct net_device_ops rtl8169_netdev_ops = {
1927         .ndo_open               = rtl8169_open,
1928         .ndo_stop               = rtl8169_close,
1929         .ndo_get_stats          = rtl8169_get_stats,
1930         .ndo_start_xmit         = rtl8169_start_xmit,
1931         .ndo_tx_timeout         = rtl8169_tx_timeout,
1932         .ndo_validate_addr      = eth_validate_addr,
1933         .ndo_change_mtu         = rtl8169_change_mtu,
1934         .ndo_set_mac_address    = rtl_set_mac_address,
1935         .ndo_do_ioctl           = rtl8169_ioctl,
1936         .ndo_set_multicast_list = rtl_set_rx_mode,
1937 #ifdef CONFIG_R8169_VLAN
1938         .ndo_vlan_rx_register   = rtl8169_vlan_rx_register,
1939 #endif
1940 #ifdef CONFIG_NET_POLL_CONTROLLER
1941         .ndo_poll_controller    = rtl8169_netpoll,
1942 #endif
1943
1944 };
1945
1946 static int __devinit
1947 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1948 {
1949         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1950         const unsigned int region = cfg->region;
1951         struct rtl8169_private *tp;
1952         struct mii_if_info *mii;
1953         struct net_device *dev;
1954         void __iomem *ioaddr;
1955         unsigned int i;
1956         int rc;
1957
1958         if (netif_msg_drv(&debug)) {
1959                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1960                        MODULENAME, RTL8169_VERSION);
1961         }
1962
1963         dev = alloc_etherdev(sizeof (*tp));
1964         if (!dev) {
1965                 if (netif_msg_drv(&debug))
1966                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1967                 rc = -ENOMEM;
1968                 goto out;
1969         }
1970
1971         SET_NETDEV_DEV(dev, &pdev->dev);
1972         dev->netdev_ops = &rtl8169_netdev_ops;
1973         tp = netdev_priv(dev);
1974         tp->dev = dev;
1975         tp->pci_dev = pdev;
1976         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1977
1978         mii = &tp->mii;
1979         mii->dev = dev;
1980         mii->mdio_read = rtl_mdio_read;
1981         mii->mdio_write = rtl_mdio_write;
1982         mii->phy_id_mask = 0x1f;
1983         mii->reg_num_mask = 0x1f;
1984         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1985
1986         /* enable device (incl. PCI PM wakeup and hotplug setup) */
1987         rc = pci_enable_device(pdev);
1988         if (rc < 0) {
1989                 if (netif_msg_probe(tp))
1990                         dev_err(&pdev->dev, "enable failure\n");
1991                 goto err_out_free_dev_1;
1992         }
1993
1994         rc = pci_set_mwi(pdev);
1995         if (rc < 0)
1996                 goto err_out_disable_2;
1997
1998         /* make sure PCI base addr 1 is MMIO */
1999         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
2000                 if (netif_msg_probe(tp)) {
2001                         dev_err(&pdev->dev,
2002                                 "region #%d not an MMIO resource, aborting\n",
2003                                 region);
2004                 }
2005                 rc = -ENODEV;
2006                 goto err_out_mwi_3;
2007         }
2008
2009         /* check for weird/broken PCI region reporting */
2010         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
2011                 if (netif_msg_probe(tp)) {
2012                         dev_err(&pdev->dev,
2013                                 "Invalid PCI region size(s), aborting\n");
2014                 }
2015                 rc = -ENODEV;
2016                 goto err_out_mwi_3;
2017         }
2018
2019         rc = pci_request_regions(pdev, MODULENAME);
2020         if (rc < 0) {
2021                 if (netif_msg_probe(tp))
2022                         dev_err(&pdev->dev, "could not request regions.\n");
2023                 goto err_out_mwi_3;
2024         }
2025
2026         tp->cp_cmd = PCIMulRW | RxChkSum;
2027
2028         if ((sizeof(dma_addr_t) > 4) &&
2029             !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
2030                 tp->cp_cmd |= PCIDAC;
2031                 dev->features |= NETIF_F_HIGHDMA;
2032         } else {
2033                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2034                 if (rc < 0) {
2035                         if (netif_msg_probe(tp)) {
2036                                 dev_err(&pdev->dev,
2037                                         "DMA configuration failed.\n");
2038                         }
2039                         goto err_out_free_res_4;
2040                 }
2041         }
2042
2043         pci_set_master(pdev);
2044
2045         /* ioremap MMIO region */
2046         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
2047         if (!ioaddr) {
2048                 if (netif_msg_probe(tp))
2049                         dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
2050                 rc = -EIO;
2051                 goto err_out_free_res_4;
2052         }
2053
2054         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2055         if (!tp->pcie_cap && netif_msg_probe(tp))
2056                 dev_info(&pdev->dev, "no PCI Express capability\n");
2057
2058         /* Unneeded ? Don't mess with Mrs. Murphy. */
2059         rtl8169_irq_mask_and_ack(ioaddr);
2060
2061         /* Soft reset the chip. */
2062         RTL_W8(ChipCmd, CmdReset);
2063
2064         /* Check that the chip has finished the reset. */
2065         for (i = 0; i < 100; i++) {
2066                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2067                         break;
2068                 msleep_interruptible(1);
2069         }
2070
2071         /* Identify chip attached to board */
2072         rtl8169_get_mac_version(tp, ioaddr);
2073
2074         rtl8169_print_mac_version(tp);
2075
2076         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
2077                 if (tp->mac_version == rtl_chip_info[i].mac_version)
2078                         break;
2079         }
2080         if (i == ARRAY_SIZE(rtl_chip_info)) {
2081                 /* Unknown chip: assume array element #0, original RTL-8169 */
2082                 if (netif_msg_probe(tp)) {
2083                         dev_printk(KERN_DEBUG, &pdev->dev,
2084                                 "unknown chip version, assuming %s\n",
2085                                 rtl_chip_info[0].name);
2086                 }
2087                 i = 0;
2088         }
2089         tp->chipset = i;
2090
2091         RTL_W8(Cfg9346, Cfg9346_Unlock);
2092         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2093         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
2094         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2095                 tp->features |= RTL_FEATURE_WOL;
2096         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2097                 tp->features |= RTL_FEATURE_WOL;
2098         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
2099         RTL_W8(Cfg9346, Cfg9346_Lock);
2100
2101         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2102             (RTL_R8(PHYstatus) & TBI_Enable)) {
2103                 tp->set_speed = rtl8169_set_speed_tbi;
2104                 tp->get_settings = rtl8169_gset_tbi;
2105                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2106                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2107                 tp->link_ok = rtl8169_tbi_link_ok;
2108                 tp->do_ioctl = rtl_tbi_ioctl;
2109
2110                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
2111         } else {
2112                 tp->set_speed = rtl8169_set_speed_xmii;
2113                 tp->get_settings = rtl8169_gset_xmii;
2114                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2115                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2116                 tp->link_ok = rtl8169_xmii_link_ok;
2117                 tp->do_ioctl = rtl_xmii_ioctl;
2118         }
2119
2120         spin_lock_init(&tp->lock);
2121
2122         tp->mmio_addr = ioaddr;
2123
2124         /* Get MAC address */
2125         for (i = 0; i < MAC_ADDR_LEN; i++)
2126                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
2127         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2128
2129         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2130         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2131         dev->irq = pdev->irq;
2132         dev->base_addr = (unsigned long) ioaddr;
2133
2134         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
2135
2136 #ifdef CONFIG_R8169_VLAN
2137         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2138 #endif
2139
2140         tp->intr_mask = 0xffff;
2141         tp->align = cfg->align;
2142         tp->hw_start = cfg->hw_start;
2143         tp->intr_event = cfg->intr_event;
2144         tp->napi_event = cfg->napi_event;
2145
2146         init_timer(&tp->timer);
2147         tp->timer.data = (unsigned long) dev;
2148         tp->timer.function = rtl8169_phy_timer;
2149
2150         rc = register_netdev(dev);
2151         if (rc < 0)
2152                 goto err_out_msi_5;
2153
2154         pci_set_drvdata(pdev, dev);
2155
2156         if (netif_msg_probe(tp)) {
2157                 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2158
2159                 printk(KERN_INFO "%s: %s at 0x%lx, "
2160                        "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2161                        "XID %08x IRQ %d\n",
2162                        dev->name,
2163                        rtl_chip_info[tp->chipset].name,
2164                        dev->base_addr,
2165                        dev->dev_addr[0], dev->dev_addr[1],
2166                        dev->dev_addr[2], dev->dev_addr[3],
2167                        dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
2168         }
2169
2170         rtl8169_init_phy(dev, tp);
2171         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
2172
2173 out:
2174         return rc;
2175
2176 err_out_msi_5:
2177         rtl_disable_msi(pdev, tp);
2178         iounmap(ioaddr);
2179 err_out_free_res_4:
2180         pci_release_regions(pdev);
2181 err_out_mwi_3:
2182         pci_clear_mwi(pdev);
2183 err_out_disable_2:
2184         pci_disable_device(pdev);
2185 err_out_free_dev_1:
2186         free_netdev(dev);
2187         goto out;
2188 }
2189
2190 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
2191 {
2192         struct net_device *dev = pci_get_drvdata(pdev);
2193         struct rtl8169_private *tp = netdev_priv(dev);
2194
2195         flush_scheduled_work();
2196
2197         unregister_netdev(dev);
2198         rtl_disable_msi(pdev, tp);
2199         rtl8169_release_board(pdev, dev, tp->mmio_addr);
2200         pci_set_drvdata(pdev, NULL);
2201 }
2202
2203 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2204                                   struct net_device *dev)
2205 {
2206         unsigned int mtu = dev->mtu;
2207
2208         tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2209 }
2210
2211 static int rtl8169_open(struct net_device *dev)
2212 {
2213         struct rtl8169_private *tp = netdev_priv(dev);
2214         struct pci_dev *pdev = tp->pci_dev;
2215         int retval = -ENOMEM;
2216
2217
2218         rtl8169_set_rxbufsize(tp, dev);
2219
2220         /*
2221          * Rx and Tx desscriptors needs 256 bytes alignment.
2222          * pci_alloc_consistent provides more.
2223          */
2224         tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2225                                                &tp->TxPhyAddr);
2226         if (!tp->TxDescArray)
2227                 goto out;
2228
2229         tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2230                                                &tp->RxPhyAddr);
2231         if (!tp->RxDescArray)
2232                 goto err_free_tx_0;
2233
2234         retval = rtl8169_init_ring(dev);
2235         if (retval < 0)
2236                 goto err_free_rx_1;
2237
2238         INIT_DELAYED_WORK(&tp->task, NULL);
2239
2240         smp_mb();
2241
2242         retval = request_irq(dev->irq, rtl8169_interrupt,
2243                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2244                              dev->name, dev);
2245         if (retval < 0)
2246                 goto err_release_ring_2;
2247
2248         napi_enable(&tp->napi);
2249
2250         rtl_hw_start(dev);
2251
2252         rtl8169_request_timer(dev);
2253
2254         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2255 out:
2256         return retval;
2257
2258 err_release_ring_2:
2259         rtl8169_rx_clear(tp);
2260 err_free_rx_1:
2261         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2262                             tp->RxPhyAddr);
2263 err_free_tx_0:
2264         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2265                             tp->TxPhyAddr);
2266         goto out;
2267 }
2268
2269 static void rtl8169_hw_reset(void __iomem *ioaddr)
2270 {
2271         /* Disable interrupts */
2272         rtl8169_irq_mask_and_ack(ioaddr);
2273
2274         /* Reset the chipset */
2275         RTL_W8(ChipCmd, CmdReset);
2276
2277         /* PCI commit */
2278         RTL_R8(ChipCmd);
2279 }
2280
2281 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
2282 {
2283         void __iomem *ioaddr = tp->mmio_addr;
2284         u32 cfg = rtl8169_rx_config;
2285
2286         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2287         RTL_W32(RxConfig, cfg);
2288
2289         /* Set DMA burst size and Interframe Gap Time */
2290         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2291                 (InterFrameGap << TxInterFrameGapShift));
2292 }
2293
2294 static void rtl_hw_start(struct net_device *dev)
2295 {
2296         struct rtl8169_private *tp = netdev_priv(dev);
2297         void __iomem *ioaddr = tp->mmio_addr;
2298         unsigned int i;
2299
2300         /* Soft reset the chip. */
2301         RTL_W8(ChipCmd, CmdReset);
2302
2303         /* Check that the chip has finished the reset. */
2304         for (i = 0; i < 100; i++) {
2305                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2306                         break;
2307                 msleep_interruptible(1);
2308         }
2309
2310         tp->hw_start(dev);
2311
2312         netif_start_queue(dev);
2313 }
2314
2315
2316 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2317                                          void __iomem *ioaddr)
2318 {
2319         /*
2320          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2321          * register to be written before TxDescAddrLow to work.
2322          * Switching from MMIO to I/O access fixes the issue as well.
2323          */
2324         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2325         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
2326         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2327         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
2328 }
2329
2330 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2331 {
2332         u16 cmd;
2333
2334         cmd = RTL_R16(CPlusCmd);
2335         RTL_W16(CPlusCmd, cmd);
2336         return cmd;
2337 }
2338
2339 static void rtl_set_rx_max_size(void __iomem *ioaddr)
2340 {
2341         /* Low hurts. Let's disable the filtering. */
2342         RTL_W16(RxMaxSize, 16383);
2343 }
2344
2345 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2346 {
2347         struct {
2348                 u32 mac_version;
2349                 u32 clk;
2350                 u32 val;
2351         } cfg2_info [] = {
2352                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2353                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2354                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2355                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2356         }, *p = cfg2_info;
2357         unsigned int i;
2358         u32 clk;
2359
2360         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2361         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2362                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2363                         RTL_W32(0x7c, p->val);
2364                         break;
2365                 }
2366         }
2367 }
2368
2369 static void rtl_hw_start_8169(struct net_device *dev)
2370 {
2371         struct rtl8169_private *tp = netdev_priv(dev);
2372         void __iomem *ioaddr = tp->mmio_addr;
2373         struct pci_dev *pdev = tp->pci_dev;
2374
2375         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2376                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2377                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2378         }
2379
2380         RTL_W8(Cfg9346, Cfg9346_Unlock);
2381         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2382             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2383             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2384             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2385                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2386
2387         RTL_W8(EarlyTxThres, EarlyTxThld);
2388
2389         rtl_set_rx_max_size(ioaddr);
2390
2391         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2392             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2393             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2394             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2395                 rtl_set_rx_tx_config_registers(tp);
2396
2397         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2398
2399         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2400             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2401                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2402                         "Bit-3 and bit-14 MUST be 1\n");
2403                 tp->cp_cmd |= (1 << 14);
2404         }
2405
2406         RTL_W16(CPlusCmd, tp->cp_cmd);
2407
2408         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2409
2410         /*
2411          * Undocumented corner. Supposedly:
2412          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2413          */
2414         RTL_W16(IntrMitigate, 0x0000);
2415
2416         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2417
2418         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2419             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2420             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2421             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2422                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2423                 rtl_set_rx_tx_config_registers(tp);
2424         }
2425
2426         RTL_W8(Cfg9346, Cfg9346_Lock);
2427
2428         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2429         RTL_R8(IntrMask);
2430
2431         RTL_W32(RxMissed, 0);
2432
2433         rtl_set_rx_mode(dev);
2434
2435         /* no early-rx interrupts */
2436         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2437
2438         /* Enable all known interrupts by setting the interrupt mask. */
2439         RTL_W16(IntrMask, tp->intr_event);
2440 }
2441
2442 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2443 {
2444         struct net_device *dev = pci_get_drvdata(pdev);
2445         struct rtl8169_private *tp = netdev_priv(dev);
2446         int cap = tp->pcie_cap;
2447
2448         if (cap) {
2449                 u16 ctl;
2450
2451                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2452                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2453                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2454         }
2455 }
2456
2457 static void rtl_csi_access_enable(void __iomem *ioaddr)
2458 {
2459         u32 csi;
2460
2461         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2462         rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2463 }
2464
2465 struct ephy_info {
2466         unsigned int offset;
2467         u16 mask;
2468         u16 bits;
2469 };
2470
2471 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2472 {
2473         u16 w;
2474
2475         while (len-- > 0) {
2476                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2477                 rtl_ephy_write(ioaddr, e->offset, w);
2478                 e++;
2479         }
2480 }
2481
2482 static void rtl_disable_clock_request(struct pci_dev *pdev)
2483 {
2484         struct net_device *dev = pci_get_drvdata(pdev);
2485         struct rtl8169_private *tp = netdev_priv(dev);
2486         int cap = tp->pcie_cap;
2487
2488         if (cap) {
2489                 u16 ctl;
2490
2491                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2492                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2493                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2494         }
2495 }
2496
2497 #define R8168_CPCMD_QUIRK_MASK (\
2498         EnableBist | \
2499         Mac_dbgo_oe | \
2500         Force_half_dup | \
2501         Force_rxflow_en | \
2502         Force_txflow_en | \
2503         Cxpl_dbg_sel | \
2504         ASF | \
2505         PktCntrDisable | \
2506         Mac_dbgo_sel)
2507
2508 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2509 {
2510         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2511
2512         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2513
2514         rtl_tx_performance_tweak(pdev,
2515                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
2516 }
2517
2518 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2519 {
2520         rtl_hw_start_8168bb(ioaddr, pdev);
2521
2522         RTL_W8(EarlyTxThres, EarlyTxThld);
2523
2524         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
2525 }
2526
2527 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2528 {
2529         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2530
2531         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2532
2533         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2534
2535         rtl_disable_clock_request(pdev);
2536
2537         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2538 }
2539
2540 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
2541 {
2542         static struct ephy_info e_info_8168cp[] = {
2543                 { 0x01, 0,      0x0001 },
2544                 { 0x02, 0x0800, 0x1000 },
2545                 { 0x03, 0,      0x0042 },
2546                 { 0x06, 0x0080, 0x0000 },
2547                 { 0x07, 0,      0x2000 }
2548         };
2549
2550         rtl_csi_access_enable(ioaddr);
2551
2552         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2553
2554         __rtl_hw_start_8168cp(ioaddr, pdev);
2555 }
2556
2557 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
2558 {
2559         rtl_csi_access_enable(ioaddr);
2560
2561         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2562
2563         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2564
2565         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2566 }
2567
2568 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
2569 {
2570         rtl_csi_access_enable(ioaddr);
2571
2572         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2573
2574         /* Magic. */
2575         RTL_W8(DBG_REG, 0x20);
2576
2577         RTL_W8(EarlyTxThres, EarlyTxThld);
2578
2579         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2580
2581         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2582 }
2583
2584 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2585 {
2586         static struct ephy_info e_info_8168c_1[] = {
2587                 { 0x02, 0x0800, 0x1000 },
2588                 { 0x03, 0,      0x0002 },
2589                 { 0x06, 0x0080, 0x0000 }
2590         };
2591
2592         rtl_csi_access_enable(ioaddr);
2593
2594         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2595
2596         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2597
2598         __rtl_hw_start_8168cp(ioaddr, pdev);
2599 }
2600
2601 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2602 {
2603         static struct ephy_info e_info_8168c_2[] = {
2604                 { 0x01, 0,      0x0001 },
2605                 { 0x03, 0x0400, 0x0220 }
2606         };
2607
2608         rtl_csi_access_enable(ioaddr);
2609
2610         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2611
2612         __rtl_hw_start_8168cp(ioaddr, pdev);
2613 }
2614
2615 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2616 {
2617         rtl_hw_start_8168c_2(ioaddr, pdev);
2618 }
2619
2620 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
2621 {
2622         rtl_csi_access_enable(ioaddr);
2623
2624         __rtl_hw_start_8168cp(ioaddr, pdev);
2625 }
2626
2627 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
2628 {
2629         rtl_csi_access_enable(ioaddr);
2630
2631         rtl_disable_clock_request(pdev);
2632
2633         RTL_W8(EarlyTxThres, EarlyTxThld);
2634
2635         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2636
2637         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2638 }
2639
2640 static void rtl_hw_start_8168(struct net_device *dev)
2641 {
2642         struct rtl8169_private *tp = netdev_priv(dev);
2643         void __iomem *ioaddr = tp->mmio_addr;
2644         struct pci_dev *pdev = tp->pci_dev;
2645
2646         RTL_W8(Cfg9346, Cfg9346_Unlock);
2647
2648         RTL_W8(EarlyTxThres, EarlyTxThld);
2649
2650         rtl_set_rx_max_size(ioaddr);
2651
2652         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2653
2654         RTL_W16(CPlusCmd, tp->cp_cmd);
2655
2656         RTL_W16(IntrMitigate, 0x5151);
2657
2658         /* Work around for RxFIFO overflow. */
2659         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2660                 tp->intr_event |= RxFIFOOver | PCSTimeout;
2661                 tp->intr_event &= ~RxOverflow;
2662         }
2663
2664         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2665
2666         rtl_set_rx_mode(dev);
2667
2668         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2669                 (InterFrameGap << TxInterFrameGapShift));
2670
2671         RTL_R8(IntrMask);
2672
2673         switch (tp->mac_version) {
2674         case RTL_GIGA_MAC_VER_11:
2675                 rtl_hw_start_8168bb(ioaddr, pdev);
2676         break;
2677
2678         case RTL_GIGA_MAC_VER_12:
2679         case RTL_GIGA_MAC_VER_17:
2680                 rtl_hw_start_8168bef(ioaddr, pdev);
2681         break;
2682
2683         case RTL_GIGA_MAC_VER_18:
2684                 rtl_hw_start_8168cp_1(ioaddr, pdev);
2685         break;
2686
2687         case RTL_GIGA_MAC_VER_19:
2688                 rtl_hw_start_8168c_1(ioaddr, pdev);
2689         break;
2690
2691         case RTL_GIGA_MAC_VER_20:
2692                 rtl_hw_start_8168c_2(ioaddr, pdev);
2693         break;
2694
2695         case RTL_GIGA_MAC_VER_21:
2696                 rtl_hw_start_8168c_3(ioaddr, pdev);
2697         break;
2698
2699         case RTL_GIGA_MAC_VER_22:
2700                 rtl_hw_start_8168c_4(ioaddr, pdev);
2701         break;
2702
2703         case RTL_GIGA_MAC_VER_23:
2704                 rtl_hw_start_8168cp_2(ioaddr, pdev);
2705         break;
2706
2707         case RTL_GIGA_MAC_VER_24:
2708                 rtl_hw_start_8168cp_3(ioaddr, pdev);
2709         break;
2710
2711         case RTL_GIGA_MAC_VER_25:
2712                 rtl_hw_start_8168d(ioaddr, pdev);
2713         break;
2714
2715         default:
2716                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2717                         dev->name, tp->mac_version);
2718         break;
2719         }
2720
2721         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2722
2723         RTL_W8(Cfg9346, Cfg9346_Lock);
2724
2725         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2726
2727         RTL_W16(IntrMask, tp->intr_event);
2728 }
2729
2730 #define R810X_CPCMD_QUIRK_MASK (\
2731         EnableBist | \
2732         Mac_dbgo_oe | \
2733         Force_half_dup | \
2734         Force_half_dup | \
2735         Force_txflow_en | \
2736         Cxpl_dbg_sel | \
2737         ASF | \
2738         PktCntrDisable | \
2739         PCIDAC | \
2740         PCIMulRW)
2741
2742 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2743 {
2744         static struct ephy_info e_info_8102e_1[] = {
2745                 { 0x01, 0, 0x6e65 },
2746                 { 0x02, 0, 0x091f },
2747                 { 0x03, 0, 0xc2f9 },
2748                 { 0x06, 0, 0xafb5 },
2749                 { 0x07, 0, 0x0e00 },
2750                 { 0x19, 0, 0xec80 },
2751                 { 0x01, 0, 0x2e65 },
2752                 { 0x01, 0, 0x6e65 }
2753         };
2754         u8 cfg1;
2755
2756         rtl_csi_access_enable(ioaddr);
2757
2758         RTL_W8(DBG_REG, FIX_NAK_1);
2759
2760         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2761
2762         RTL_W8(Config1,
2763                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2764         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2765
2766         cfg1 = RTL_R8(Config1);
2767         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2768                 RTL_W8(Config1, cfg1 & ~LEDS0);
2769
2770         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2771
2772         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2773 }
2774
2775 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2776 {
2777         rtl_csi_access_enable(ioaddr);
2778
2779         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2780
2781         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2782         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2783
2784         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2785 }
2786
2787 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2788 {
2789         rtl_hw_start_8102e_2(ioaddr, pdev);
2790
2791         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2792 }
2793
2794 static void rtl_hw_start_8101(struct net_device *dev)
2795 {
2796         struct rtl8169_private *tp = netdev_priv(dev);
2797         void __iomem *ioaddr = tp->mmio_addr;
2798         struct pci_dev *pdev = tp->pci_dev;
2799
2800         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2801             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2802                 int cap = tp->pcie_cap;
2803
2804                 if (cap) {
2805                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2806                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
2807                 }
2808         }
2809
2810         switch (tp->mac_version) {
2811         case RTL_GIGA_MAC_VER_07:
2812                 rtl_hw_start_8102e_1(ioaddr, pdev);
2813                 break;
2814
2815         case RTL_GIGA_MAC_VER_08:
2816                 rtl_hw_start_8102e_3(ioaddr, pdev);
2817                 break;
2818
2819         case RTL_GIGA_MAC_VER_09:
2820                 rtl_hw_start_8102e_2(ioaddr, pdev);
2821                 break;
2822         }
2823
2824         RTL_W8(Cfg9346, Cfg9346_Unlock);
2825
2826         RTL_W8(EarlyTxThres, EarlyTxThld);
2827
2828         rtl_set_rx_max_size(ioaddr);
2829
2830         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2831
2832         RTL_W16(CPlusCmd, tp->cp_cmd);
2833
2834         RTL_W16(IntrMitigate, 0x0000);
2835
2836         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2837
2838         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2839         rtl_set_rx_tx_config_registers(tp);
2840
2841         RTL_W8(Cfg9346, Cfg9346_Lock);
2842
2843         RTL_R8(IntrMask);
2844
2845         rtl_set_rx_mode(dev);
2846
2847         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2848
2849         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2850
2851         RTL_W16(IntrMask, tp->intr_event);
2852 }
2853
2854 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2855 {
2856         struct rtl8169_private *tp = netdev_priv(dev);
2857         int ret = 0;
2858
2859         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2860                 return -EINVAL;
2861
2862         dev->mtu = new_mtu;
2863
2864         if (!netif_running(dev))
2865                 goto out;
2866
2867         rtl8169_down(dev);
2868
2869         rtl8169_set_rxbufsize(tp, dev);
2870
2871         ret = rtl8169_init_ring(dev);
2872         if (ret < 0)
2873                 goto out;
2874
2875         napi_enable(&tp->napi);
2876
2877         rtl_hw_start(dev);
2878
2879         rtl8169_request_timer(dev);
2880
2881 out:
2882         return ret;
2883 }
2884
2885 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2886 {
2887         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2888         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2889 }
2890
2891 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2892                                 struct sk_buff **sk_buff, struct RxDesc *desc)
2893 {
2894         struct pci_dev *pdev = tp->pci_dev;
2895
2896         pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2897                          PCI_DMA_FROMDEVICE);
2898         dev_kfree_skb(*sk_buff);
2899         *sk_buff = NULL;
2900         rtl8169_make_unusable_by_asic(desc);
2901 }
2902
2903 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2904 {
2905         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2906
2907         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2908 }
2909
2910 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2911                                        u32 rx_buf_sz)
2912 {
2913         desc->addr = cpu_to_le64(mapping);
2914         wmb();
2915         rtl8169_mark_to_asic(desc, rx_buf_sz);
2916 }
2917
2918 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2919                                             struct net_device *dev,
2920                                             struct RxDesc *desc, int rx_buf_sz,
2921                                             unsigned int align)
2922 {
2923         struct sk_buff *skb;
2924         dma_addr_t mapping;
2925         unsigned int pad;
2926
2927         pad = align ? align : NET_IP_ALIGN;
2928
2929         skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2930         if (!skb)
2931                 goto err_out;
2932
2933         skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2934
2935         mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2936                                  PCI_DMA_FROMDEVICE);
2937
2938         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2939 out:
2940         return skb;
2941
2942 err_out:
2943         rtl8169_make_unusable_by_asic(desc);
2944         goto out;
2945 }
2946
2947 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2948 {
2949         unsigned int i;
2950
2951         for (i = 0; i < NUM_RX_DESC; i++) {
2952                 if (tp->Rx_skbuff[i]) {
2953                         rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2954                                             tp->RxDescArray + i);
2955                 }
2956         }
2957 }
2958
2959 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2960                            u32 start, u32 end)
2961 {
2962         u32 cur;
2963
2964         for (cur = start; end - cur != 0; cur++) {
2965                 struct sk_buff *skb;
2966                 unsigned int i = cur % NUM_RX_DESC;
2967
2968                 WARN_ON((s32)(end - cur) < 0);
2969
2970                 if (tp->Rx_skbuff[i])
2971                         continue;
2972
2973                 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2974                                            tp->RxDescArray + i,
2975                                            tp->rx_buf_sz, tp->align);
2976                 if (!skb)
2977                         break;
2978
2979                 tp->Rx_skbuff[i] = skb;
2980         }
2981         return cur - start;
2982 }
2983
2984 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2985 {
2986         desc->opts1 |= cpu_to_le32(RingEnd);
2987 }
2988
2989 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2990 {
2991         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2992 }
2993
2994 static int rtl8169_init_ring(struct net_device *dev)
2995 {
2996         struct rtl8169_private *tp = netdev_priv(dev);
2997
2998         rtl8169_init_ring_indexes(tp);
2999
3000         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3001         memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
3002
3003         if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
3004                 goto err_out;
3005
3006         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3007
3008         return 0;
3009
3010 err_out:
3011         rtl8169_rx_clear(tp);
3012         return -ENOMEM;
3013 }
3014
3015 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
3016                                  struct TxDesc *desc)
3017 {
3018         unsigned int len = tx_skb->len;
3019
3020         pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
3021         desc->opts1 = 0x00;
3022         desc->opts2 = 0x00;
3023         desc->addr = 0x00;
3024         tx_skb->len = 0;
3025 }
3026
3027 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3028 {
3029         unsigned int i;
3030
3031         for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
3032                 unsigned int entry = i % NUM_TX_DESC;
3033                 struct ring_info *tx_skb = tp->tx_skb + entry;
3034                 unsigned int len = tx_skb->len;
3035
3036                 if (len) {
3037                         struct sk_buff *skb = tx_skb->skb;
3038
3039                         rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
3040                                              tp->TxDescArray + entry);
3041                         if (skb) {
3042                                 dev_kfree_skb(skb);
3043                                 tx_skb->skb = NULL;
3044                         }
3045                         tp->dev->stats.tx_dropped++;
3046                 }
3047         }
3048         tp->cur_tx = tp->dirty_tx = 0;
3049 }
3050
3051 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
3052 {
3053         struct rtl8169_private *tp = netdev_priv(dev);
3054
3055         PREPARE_DELAYED_WORK(&tp->task, task);
3056         schedule_delayed_work(&tp->task, 4);
3057 }
3058
3059 static void rtl8169_wait_for_quiescence(struct net_device *dev)
3060 {
3061         struct rtl8169_private *tp = netdev_priv(dev);
3062         void __iomem *ioaddr = tp->mmio_addr;
3063
3064         synchronize_irq(dev->irq);
3065
3066         /* Wait for any pending NAPI task to complete */
3067         napi_disable(&tp->napi);
3068
3069         rtl8169_irq_mask_and_ack(ioaddr);
3070
3071         tp->intr_mask = 0xffff;
3072         RTL_W16(IntrMask, tp->intr_event);
3073         napi_enable(&tp->napi);
3074 }
3075
3076 static void rtl8169_reinit_task(struct work_struct *work)
3077 {
3078         struct rtl8169_private *tp =
3079                 container_of(work, struct rtl8169_private, task.work);
3080         struct net_device *dev = tp->dev;
3081         int ret;
3082
3083         rtnl_lock();
3084
3085         if (!netif_running(dev))
3086                 goto out_unlock;
3087
3088         rtl8169_wait_for_quiescence(dev);
3089         rtl8169_close(dev);
3090
3091         ret = rtl8169_open(dev);
3092         if (unlikely(ret < 0)) {
3093                 if (net_ratelimit() && netif_msg_drv(tp)) {
3094                         printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
3095                                " Rescheduling.\n", dev->name, ret);
3096                 }
3097                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3098         }
3099
3100 out_unlock:
3101         rtnl_unlock();
3102 }
3103
3104 static void rtl8169_reset_task(struct work_struct *work)
3105 {
3106         struct rtl8169_private *tp =
3107                 container_of(work, struct rtl8169_private, task.work);
3108         struct net_device *dev = tp->dev;
3109
3110         rtnl_lock();
3111
3112         if (!netif_running(dev))
3113                 goto out_unlock;
3114
3115         rtl8169_wait_for_quiescence(dev);
3116
3117         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
3118         rtl8169_tx_clear(tp);
3119
3120         if (tp->dirty_rx == tp->cur_rx) {
3121                 rtl8169_init_ring_indexes(tp);
3122                 rtl_hw_start(dev);
3123                 netif_wake_queue(dev);
3124                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3125         } else {
3126                 if (net_ratelimit() && netif_msg_intr(tp)) {
3127                         printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
3128                                dev->name);
3129                 }
3130                 rtl8169_schedule_work(dev, rtl8169_reset_task);
3131         }
3132
3133 out_unlock:
3134         rtnl_unlock();
3135 }
3136
3137 static void rtl8169_tx_timeout(struct net_device *dev)
3138 {
3139         struct rtl8169_private *tp = netdev_priv(dev);
3140
3141         rtl8169_hw_reset(tp->mmio_addr);
3142
3143         /* Let's wait a bit while any (async) irq lands on */
3144         rtl8169_schedule_work(dev, rtl8169_reset_task);
3145 }
3146
3147 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3148                               u32 opts1)
3149 {
3150         struct skb_shared_info *info = skb_shinfo(skb);
3151         unsigned int cur_frag, entry;
3152         struct TxDesc * uninitialized_var(txd);
3153
3154         entry = tp->cur_tx;
3155         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3156                 skb_frag_t *frag = info->frags + cur_frag;
3157                 dma_addr_t mapping;
3158                 u32 status, len;
3159                 void *addr;
3160
3161                 entry = (entry + 1) % NUM_TX_DESC;
3162
3163                 txd = tp->TxDescArray + entry;
3164                 len = frag->size;
3165                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3166                 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3167
3168                 /* anti gcc 2.95.3 bugware (sic) */
3169                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3170
3171                 txd->opts1 = cpu_to_le32(status);
3172                 txd->addr = cpu_to_le64(mapping);
3173
3174                 tp->tx_skb[entry].len = len;
3175         }
3176
3177         if (cur_frag) {
3178                 tp->tx_skb[entry].skb = skb;
3179                 txd->opts1 |= cpu_to_le32(LastFrag);
3180         }
3181
3182         return cur_frag;
3183 }
3184
3185 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3186 {
3187         if (dev->features & NETIF_F_TSO) {
3188                 u32 mss = skb_shinfo(skb)->gso_size;
3189
3190                 if (mss)
3191                         return LargeSend | ((mss & MSSMask) << MSSShift);
3192         }
3193         if (skb->ip_summed == CHECKSUM_PARTIAL) {
3194                 const struct iphdr *ip = ip_hdr(skb);
3195
3196                 if (ip->protocol == IPPROTO_TCP)
3197                         return IPCS | TCPCS;
3198                 else if (ip->protocol == IPPROTO_UDP)
3199                         return IPCS | UDPCS;
3200                 WARN_ON(1);     /* we need a WARN() */
3201         }
3202         return 0;
3203 }
3204
3205 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3206 {
3207         struct rtl8169_private *tp = netdev_priv(dev);
3208         unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3209         struct TxDesc *txd = tp->TxDescArray + entry;
3210         void __iomem *ioaddr = tp->mmio_addr;
3211         dma_addr_t mapping;
3212         u32 status, len;
3213         u32 opts1;
3214         int ret = NETDEV_TX_OK;
3215
3216         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
3217                 if (netif_msg_drv(tp)) {
3218                         printk(KERN_ERR
3219                                "%s: BUG! Tx Ring full when queue awake!\n",
3220                                dev->name);
3221                 }
3222                 goto err_stop;
3223         }
3224
3225         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3226                 goto err_stop;
3227
3228         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3229
3230         frags = rtl8169_xmit_frags(tp, skb, opts1);
3231         if (frags) {
3232                 len = skb_headlen(skb);
3233                 opts1 |= FirstFrag;
3234         } else {
3235                 len = skb->len;
3236
3237                 if (unlikely(len < ETH_ZLEN)) {
3238                         if (skb_padto(skb, ETH_ZLEN))
3239                                 goto err_update_stats;
3240                         len = ETH_ZLEN;
3241                 }
3242
3243                 opts1 |= FirstFrag | LastFrag;
3244                 tp->tx_skb[entry].skb = skb;
3245         }
3246
3247         mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3248
3249         tp->tx_skb[entry].len = len;
3250         txd->addr = cpu_to_le64(mapping);
3251         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3252
3253         wmb();
3254
3255         /* anti gcc 2.95.3 bugware (sic) */
3256         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3257         txd->opts1 = cpu_to_le32(status);
3258
3259         dev->trans_start = jiffies;
3260
3261         tp->cur_tx += frags + 1;
3262
3263         smp_wmb();
3264
3265         RTL_W8(TxPoll, NPQ);    /* set polling bit */
3266
3267         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3268                 netif_stop_queue(dev);
3269                 smp_rmb();
3270                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3271                         netif_wake_queue(dev);
3272         }
3273
3274 out:
3275         return ret;
3276
3277 err_stop:
3278         netif_stop_queue(dev);
3279         ret = NETDEV_TX_BUSY;
3280 err_update_stats:
3281         dev->stats.tx_dropped++;
3282         goto out;
3283 }
3284
3285 static void rtl8169_pcierr_interrupt(struct net_device *dev)
3286 {
3287         struct rtl8169_private *tp = netdev_priv(dev);
3288         struct pci_dev *pdev = tp->pci_dev;
3289         void __iomem *ioaddr = tp->mmio_addr;
3290         u16 pci_status, pci_cmd;
3291
3292         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3293         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3294
3295         if (netif_msg_intr(tp)) {
3296                 printk(KERN_ERR
3297                        "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3298                        dev->name, pci_cmd, pci_status);
3299         }
3300
3301         /*
3302          * The recovery sequence below admits a very elaborated explanation:
3303          * - it seems to work;
3304          * - I did not see what else could be done;
3305          * - it makes iop3xx happy.
3306          *
3307          * Feel free to adjust to your needs.
3308          */
3309         if (pdev->broken_parity_status)
3310                 pci_cmd &= ~PCI_COMMAND_PARITY;
3311         else
3312                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3313
3314         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
3315
3316         pci_write_config_word(pdev, PCI_STATUS,
3317                 pci_status & (PCI_STATUS_DETECTED_PARITY |
3318                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3319                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3320
3321         /* The infamous DAC f*ckup only happens at boot time */
3322         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
3323                 if (netif_msg_intr(tp))
3324                         printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
3325                 tp->cp_cmd &= ~PCIDAC;
3326                 RTL_W16(CPlusCmd, tp->cp_cmd);
3327                 dev->features &= ~NETIF_F_HIGHDMA;
3328         }
3329
3330         rtl8169_hw_reset(ioaddr);
3331
3332         rtl8169_schedule_work(dev, rtl8169_reinit_task);
3333 }
3334
3335 static void rtl8169_tx_interrupt(struct net_device *dev,
3336                                  struct rtl8169_private *tp,
3337                                  void __iomem *ioaddr)
3338 {
3339         unsigned int dirty_tx, tx_left;
3340
3341         dirty_tx = tp->dirty_tx;
3342         smp_rmb();
3343         tx_left = tp->cur_tx - dirty_tx;
3344
3345         while (tx_left > 0) {
3346                 unsigned int entry = dirty_tx % NUM_TX_DESC;
3347                 struct ring_info *tx_skb = tp->tx_skb + entry;
3348                 u32 len = tx_skb->len;
3349                 u32 status;
3350
3351                 rmb();
3352                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3353                 if (status & DescOwn)
3354                         break;
3355
3356                 dev->stats.tx_bytes += len;
3357                 dev->stats.tx_packets++;
3358
3359                 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3360
3361                 if (status & LastFrag) {
3362                         dev_kfree_skb_irq(tx_skb->skb);
3363                         tx_skb->skb = NULL;
3364                 }
3365                 dirty_tx++;
3366                 tx_left--;
3367         }
3368
3369         if (tp->dirty_tx != dirty_tx) {
3370                 tp->dirty_tx = dirty_tx;
3371                 smp_wmb();
3372                 if (netif_queue_stopped(dev) &&
3373                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3374                         netif_wake_queue(dev);
3375                 }
3376                 /*
3377                  * 8168 hack: TxPoll requests are lost when the Tx packets are
3378                  * too close. Let's kick an extra TxPoll request when a burst
3379                  * of start_xmit activity is detected (if it is not detected,
3380                  * it is slow enough). -- FR
3381                  */
3382                 smp_rmb();
3383                 if (tp->cur_tx != dirty_tx)
3384                         RTL_W8(TxPoll, NPQ);
3385         }
3386 }
3387
3388 static inline int rtl8169_fragmented_frame(u32 status)
3389 {
3390         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3391 }
3392
3393 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3394 {
3395         u32 opts1 = le32_to_cpu(desc->opts1);
3396         u32 status = opts1 & RxProtoMask;
3397
3398         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3399             ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3400             ((status == RxProtoIP) && !(opts1 & IPFail)))
3401                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3402         else
3403                 skb->ip_summed = CHECKSUM_NONE;
3404 }
3405
3406 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3407                                        struct rtl8169_private *tp, int pkt_size,
3408                                        dma_addr_t addr)
3409 {
3410         struct sk_buff *skb;
3411         bool done = false;
3412
3413         if (pkt_size >= rx_copybreak)
3414                 goto out;
3415
3416         skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
3417         if (!skb)
3418                 goto out;
3419
3420         pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3421                                     PCI_DMA_FROMDEVICE);
3422         skb_reserve(skb, NET_IP_ALIGN);
3423         skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3424         *sk_buff = skb;
3425         done = true;
3426 out:
3427         return done;
3428 }
3429
3430 static int rtl8169_rx_interrupt(struct net_device *dev,
3431                                 struct rtl8169_private *tp,
3432                                 void __iomem *ioaddr, u32 budget)
3433 {
3434         unsigned int cur_rx, rx_left;
3435         unsigned int delta, count;
3436
3437         cur_rx = tp->cur_rx;
3438         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3439         rx_left = min(rx_left, budget);
3440
3441         for (; rx_left > 0; rx_left--, cur_rx++) {
3442                 unsigned int entry = cur_rx % NUM_RX_DESC;
3443                 struct RxDesc *desc = tp->RxDescArray + entry;
3444                 u32 status;
3445
3446                 rmb();
3447                 status = le32_to_cpu(desc->opts1);
3448
3449                 if (status & DescOwn)
3450                         break;
3451                 if (unlikely(status & RxRES)) {
3452                         if (netif_msg_rx_err(tp)) {
3453                                 printk(KERN_INFO
3454                                        "%s: Rx ERROR. status = %08x\n",
3455                                        dev->name, status);
3456                         }
3457                         dev->stats.rx_errors++;
3458                         if (status & (RxRWT | RxRUNT))
3459                                 dev->stats.rx_length_errors++;
3460                         if (status & RxCRC)
3461                                 dev->stats.rx_crc_errors++;
3462                         if (status & RxFOVF) {
3463                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
3464                                 dev->stats.rx_fifo_errors++;
3465                         }
3466                         rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3467                 } else {
3468                         struct sk_buff *skb = tp->Rx_skbuff[entry];
3469                         dma_addr_t addr = le64_to_cpu(desc->addr);
3470                         int pkt_size = (status & 0x00001FFF) - 4;
3471                         struct pci_dev *pdev = tp->pci_dev;
3472
3473                         /*
3474                          * The driver does not support incoming fragmented
3475                          * frames. They are seen as a symptom of over-mtu
3476                          * sized frames.
3477                          */
3478                         if (unlikely(rtl8169_fragmented_frame(status))) {
3479                                 dev->stats.rx_dropped++;
3480                                 dev->stats.rx_length_errors++;
3481                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3482                                 continue;
3483                         }
3484
3485                         rtl8169_rx_csum(skb, desc);
3486
3487                         if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
3488                                 pci_dma_sync_single_for_device(pdev, addr,
3489                                         pkt_size, PCI_DMA_FROMDEVICE);
3490                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3491                         } else {
3492                                 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
3493                                                  PCI_DMA_FROMDEVICE);
3494                                 tp->Rx_skbuff[entry] = NULL;
3495                         }
3496
3497                         skb_put(skb, pkt_size);
3498                         skb->protocol = eth_type_trans(skb, dev);
3499
3500                         if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
3501                                 netif_receive_skb(skb);
3502
3503                         dev->stats.rx_bytes += pkt_size;
3504                         dev->stats.rx_packets++;
3505                 }
3506
3507                 /* Work around for AMD plateform. */
3508                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
3509                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3510                         desc->opts2 = 0;
3511                         cur_rx++;
3512                 }
3513         }
3514
3515         count = cur_rx - tp->cur_rx;
3516         tp->cur_rx = cur_rx;
3517
3518         delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
3519         if (!delta && count && netif_msg_intr(tp))
3520                 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3521         tp->dirty_rx += delta;
3522
3523         /*
3524          * FIXME: until there is periodic timer to try and refill the ring,
3525          * a temporary shortage may definitely kill the Rx process.
3526          * - disable the asic to try and avoid an overflow and kick it again
3527          *   after refill ?
3528          * - how do others driver handle this condition (Uh oh...).
3529          */
3530         if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
3531                 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3532
3533         return count;
3534 }
3535
3536 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
3537 {
3538         struct net_device *dev = dev_instance;
3539         struct rtl8169_private *tp = netdev_priv(dev);
3540         void __iomem *ioaddr = tp->mmio_addr;
3541         int handled = 0;
3542         int status;
3543
3544         status = RTL_R16(IntrStatus);
3545
3546         /* hotplug/major error/no more work/shared irq */
3547         if ((status == 0xffff) || !status)
3548                 goto out;
3549
3550         handled = 1;
3551
3552         if (unlikely(!netif_running(dev))) {
3553                 rtl8169_asic_down(ioaddr);
3554                 goto out;
3555         }
3556
3557         status &= tp->intr_mask;
3558         RTL_W16(IntrStatus,
3559                 (status & RxFIFOOver) ? (status | RxOverflow) : status);
3560
3561         if (!(status & tp->intr_event))
3562                 goto out;
3563
3564         /* Work around for rx fifo overflow */
3565         if (unlikely(status & RxFIFOOver) &&
3566             (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3567                 netif_stop_queue(dev);
3568                 rtl8169_tx_timeout(dev);
3569                 goto out;
3570         }
3571
3572         if (unlikely(status & SYSErr)) {
3573                 rtl8169_pcierr_interrupt(dev);
3574                 goto out;
3575         }
3576
3577         if (status & LinkChg)
3578                 rtl8169_check_link_status(dev, tp, ioaddr);
3579
3580         if (status & tp->napi_event) {
3581                 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3582                 tp->intr_mask = ~tp->napi_event;
3583
3584                 if (likely(napi_schedule_prep(&tp->napi)))
3585                         __napi_schedule(&tp->napi);
3586                 else if (netif_msg_intr(tp)) {
3587                         printk(KERN_INFO "%s: interrupt %04x in poll\n",
3588                                dev->name, status);
3589                 }
3590         }
3591 out:
3592         return IRQ_RETVAL(handled);
3593 }
3594
3595 static int rtl8169_poll(struct napi_struct *napi, int budget)
3596 {
3597         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3598         struct net_device *dev = tp->dev;
3599         void __iomem *ioaddr = tp->mmio_addr;
3600         int work_done;
3601
3602         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
3603         rtl8169_tx_interrupt(dev, tp, ioaddr);
3604
3605         if (work_done < budget) {
3606                 napi_complete(napi);
3607                 tp->intr_mask = 0xffff;
3608                 /*
3609                  * 20040426: the barrier is not strictly required but the
3610                  * behavior of the irq handler could be less predictable
3611                  * without it. Btw, the lack of flush for the posted pci
3612                  * write is safe - FR
3613                  */
3614                 smp_wmb();
3615                 RTL_W16(IntrMask, tp->intr_event);
3616         }
3617
3618         return work_done;
3619 }
3620
3621 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3622 {
3623         struct rtl8169_private *tp = netdev_priv(dev);
3624
3625         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3626                 return;
3627
3628         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3629         RTL_W32(RxMissed, 0);
3630 }
3631
3632 static void rtl8169_down(struct net_device *dev)
3633 {
3634         struct rtl8169_private *tp = netdev_priv(dev);
3635         void __iomem *ioaddr = tp->mmio_addr;
3636         unsigned int intrmask;
3637
3638         rtl8169_delete_timer(dev);
3639
3640         netif_stop_queue(dev);
3641
3642         napi_disable(&tp->napi);
3643
3644 core_down:
3645         spin_lock_irq(&tp->lock);
3646
3647         rtl8169_asic_down(ioaddr);
3648
3649         rtl8169_rx_missed(dev, ioaddr);
3650
3651         spin_unlock_irq(&tp->lock);
3652
3653         synchronize_irq(dev->irq);
3654
3655         /* Give a racing hard_start_xmit a few cycles to complete. */
3656         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
3657
3658         /*
3659          * And now for the 50k$ question: are IRQ disabled or not ?
3660          *
3661          * Two paths lead here:
3662          * 1) dev->close
3663          *    -> netif_running() is available to sync the current code and the
3664          *       IRQ handler. See rtl8169_interrupt for details.
3665          * 2) dev->change_mtu
3666          *    -> rtl8169_poll can not be issued again and re-enable the
3667          *       interruptions. Let's simply issue the IRQ down sequence again.
3668          *
3669          * No loop if hotpluged or major error (0xffff).
3670          */
3671         intrmask = RTL_R16(IntrMask);
3672         if (intrmask && (intrmask != 0xffff))
3673                 goto core_down;
3674
3675         rtl8169_tx_clear(tp);
3676
3677         rtl8169_rx_clear(tp);
3678 }
3679
3680 static int rtl8169_close(struct net_device *dev)
3681 {
3682         struct rtl8169_private *tp = netdev_priv(dev);
3683         struct pci_dev *pdev = tp->pci_dev;
3684
3685         rtl8169_down(dev);
3686
3687         free_irq(dev->irq, dev);
3688
3689         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3690                             tp->RxPhyAddr);
3691         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3692                             tp->TxPhyAddr);
3693         tp->TxDescArray = NULL;
3694         tp->RxDescArray = NULL;
3695
3696         return 0;
3697 }
3698
3699 static void rtl_set_rx_mode(struct net_device *dev)
3700 {
3701         struct rtl8169_private *tp = netdev_priv(dev);
3702         void __iomem *ioaddr = tp->mmio_addr;
3703         unsigned long flags;
3704         u32 mc_filter[2];       /* Multicast hash filter */
3705         int rx_mode;
3706         u32 tmp = 0;
3707
3708         if (dev->flags & IFF_PROMISC) {
3709                 /* Unconditionally log net taps. */
3710                 if (netif_msg_link(tp)) {
3711                         printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3712                                dev->name);
3713                 }
3714                 rx_mode =
3715                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3716                     AcceptAllPhys;
3717                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3718         } else if ((dev->mc_count > multicast_filter_limit)
3719                    || (dev->flags & IFF_ALLMULTI)) {
3720                 /* Too many to filter perfectly -- accept all multicasts. */
3721                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3722                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3723         } else {
3724                 struct dev_mc_list *mclist;
3725                 unsigned int i;
3726
3727                 rx_mode = AcceptBroadcast | AcceptMyPhys;
3728                 mc_filter[1] = mc_filter[0] = 0;
3729                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3730                      i++, mclist = mclist->next) {
3731                         int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3732                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3733                         rx_mode |= AcceptMulticast;
3734                 }
3735         }
3736
3737         spin_lock_irqsave(&tp->lock, flags);
3738
3739         tmp = rtl8169_rx_config | rx_mode |
3740               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3741
3742         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3743                 u32 data = mc_filter[0];
3744
3745                 mc_filter[0] = swab32(mc_filter[1]);
3746                 mc_filter[1] = swab32(data);
3747         }
3748
3749         RTL_W32(MAR0 + 0, mc_filter[0]);
3750         RTL_W32(MAR0 + 4, mc_filter[1]);
3751
3752         RTL_W32(RxConfig, tmp);
3753
3754         spin_unlock_irqrestore(&tp->lock, flags);
3755 }
3756
3757 /**
3758  *  rtl8169_get_stats - Get rtl8169 read/write statistics
3759  *  @dev: The Ethernet Device to get statistics for
3760  *
3761  *  Get TX/RX statistics for rtl8169
3762  */
3763 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3764 {
3765         struct rtl8169_private *tp = netdev_priv(dev);
3766         void __iomem *ioaddr = tp->mmio_addr;
3767         unsigned long flags;
3768
3769         if (netif_running(dev)) {
3770                 spin_lock_irqsave(&tp->lock, flags);
3771                 rtl8169_rx_missed(dev, ioaddr);
3772                 spin_unlock_irqrestore(&tp->lock, flags);
3773         }
3774
3775         return &dev->stats;
3776 }
3777
3778 #ifdef CONFIG_PM
3779
3780 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3781 {
3782         struct net_device *dev = pci_get_drvdata(pdev);
3783         struct rtl8169_private *tp = netdev_priv(dev);
3784         void __iomem *ioaddr = tp->mmio_addr;
3785
3786         if (!netif_running(dev))
3787                 goto out_pci_suspend;
3788
3789         netif_device_detach(dev);
3790         netif_stop_queue(dev);
3791
3792         spin_lock_irq(&tp->lock);
3793
3794         rtl8169_asic_down(ioaddr);
3795
3796         rtl8169_rx_missed(dev, ioaddr);
3797
3798         spin_unlock_irq(&tp->lock);
3799
3800 out_pci_suspend:
3801         pci_save_state(pdev);
3802         pci_enable_wake(pdev, pci_choose_state(pdev, state),
3803                 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3804         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3805
3806         return 0;
3807 }
3808
3809 static int rtl8169_resume(struct pci_dev *pdev)
3810 {
3811         struct net_device *dev = pci_get_drvdata(pdev);
3812
3813         pci_set_power_state(pdev, PCI_D0);
3814         pci_restore_state(pdev);
3815         pci_enable_wake(pdev, PCI_D0, 0);
3816
3817         if (!netif_running(dev))
3818                 goto out;
3819
3820         netif_device_attach(dev);
3821
3822         rtl8169_schedule_work(dev, rtl8169_reset_task);
3823 out:
3824         return 0;
3825 }
3826
3827 static void rtl_shutdown(struct pci_dev *pdev)
3828 {
3829         rtl8169_suspend(pdev, PMSG_SUSPEND);
3830 }
3831
3832 #endif /* CONFIG_PM */
3833
3834 static struct pci_driver rtl8169_pci_driver = {
3835         .name           = MODULENAME,
3836         .id_table       = rtl8169_pci_tbl,
3837         .probe          = rtl8169_init_one,
3838         .remove         = __devexit_p(rtl8169_remove_one),
3839 #ifdef CONFIG_PM
3840         .suspend        = rtl8169_suspend,
3841         .resume         = rtl8169_resume,
3842         .shutdown       = rtl_shutdown,
3843 #endif
3844 };
3845
3846 static int __init rtl8169_init_module(void)
3847 {
3848         return pci_register_driver(&rtl8169_pci_driver);
3849 }
3850
3851 static void __exit rtl8169_cleanup_module(void)
3852 {
3853         pci_unregister_driver(&rtl8169_pci_driver);
3854 }
3855
3856 module_init(rtl8169_init_module);
3857 module_exit(rtl8169_cleanup_module);