r8169: new phy init parameters for the 8168b
[linux-2.6.git] / drivers / net / r8169.c
1 /*
2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3  *
4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6  * Copyright (c) a lot of people too. Please respect their work.
7  *
8  * See MAINTAINERS file for support contact information.
9  */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26
27 #include <asm/system.h>
28 #include <asm/io.h>
29 #include <asm/irq.h>
30
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
34
35 #ifdef RTL8169_DEBUG
36 #define assert(expr) \
37         if (!(expr)) {                                  \
38                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39                 #expr,__FILE__,__func__,__LINE__);              \
40         }
41 #define dprintk(fmt, args...) \
42         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
43 #else
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...)   do {} while (0)
46 #endif /* RTL8169_DEBUG */
47
48 #define R8169_MSG_DEFAULT \
49         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
50
51 #define TX_BUFFS_AVAIL(tp) \
52         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static const int max_interrupt_work = 20;
56
57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
59 static const int multicast_filter_limit = 32;
60
61 /* MAC address length */
62 #define MAC_ADDR_LEN    6
63
64 #define MAX_READ_REQUEST_SHIFT  12
65 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
67 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
68 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
69 #define RxPacketMaxSize 0x3FE8  /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
72
73 #define R8169_REGS_SIZE         256
74 #define R8169_NAPI_WEIGHT       64
75 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
80
81 #define RTL8169_TX_TIMEOUT      (6*HZ)
82 #define RTL8169_PHY_TIMEOUT     (10*HZ)
83
84 /* write/read MMIO register */
85 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
86 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
87 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
88 #define RTL_R8(reg)             readb (ioaddr + (reg))
89 #define RTL_R16(reg)            readw (ioaddr + (reg))
90 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
91
92 enum mac_version {
93         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
94         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
95         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
96         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
97         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
98         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
99         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
100         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
101         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
102         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
103         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
104         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
105         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
106         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
107         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
108         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
109         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
110         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
111         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
112         RTL_GIGA_MAC_VER_20 = 0x14  // 8168C
113 };
114
115 #define _R(NAME,MAC,MASK) \
116         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
117
118 static const struct {
119         const char *name;
120         u8 mac_version;
121         u32 RxConfigMask;       /* Clears the bits supported by this chip */
122 } rtl_chip_info[] = {
123         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
124         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
125         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
126         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
127         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
128         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
129         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
130         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
131         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
132         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
133         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
134         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
135         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
136         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
137         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
138         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
139         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
140         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
141         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
142         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880)  // PCI-E
143 };
144 #undef _R
145
146 enum cfg_version {
147         RTL_CFG_0 = 0x00,
148         RTL_CFG_1,
149         RTL_CFG_2
150 };
151
152 static void rtl_hw_start_8169(struct net_device *);
153 static void rtl_hw_start_8168(struct net_device *);
154 static void rtl_hw_start_8101(struct net_device *);
155
156 static struct pci_device_id rtl8169_pci_tbl[] = {
157         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
158         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
159         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
160         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
161         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
162         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
163         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
164         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
165         { PCI_VENDOR_ID_LINKSYS,                0x1032,
166                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
167         { 0x0001,                               0x8168,
168                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
169         {0,},
170 };
171
172 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
173
174 static int rx_copybreak = 200;
175 static int use_dac;
176 static struct {
177         u32 msg_enable;
178 } debug = { -1 };
179
180 enum rtl_registers {
181         MAC0            = 0,    /* Ethernet hardware address. */
182         MAC4            = 4,
183         MAR0            = 8,    /* Multicast filter. */
184         CounterAddrLow          = 0x10,
185         CounterAddrHigh         = 0x14,
186         TxDescStartAddrLow      = 0x20,
187         TxDescStartAddrHigh     = 0x24,
188         TxHDescStartAddrLow     = 0x28,
189         TxHDescStartAddrHigh    = 0x2c,
190         FLASH           = 0x30,
191         ERSR            = 0x36,
192         ChipCmd         = 0x37,
193         TxPoll          = 0x38,
194         IntrMask        = 0x3c,
195         IntrStatus      = 0x3e,
196         TxConfig        = 0x40,
197         RxConfig        = 0x44,
198         RxMissed        = 0x4c,
199         Cfg9346         = 0x50,
200         Config0         = 0x51,
201         Config1         = 0x52,
202         Config2         = 0x53,
203         Config3         = 0x54,
204         Config4         = 0x55,
205         Config5         = 0x56,
206         MultiIntr       = 0x5c,
207         PHYAR           = 0x60,
208         PHYstatus       = 0x6c,
209         RxMaxSize       = 0xda,
210         CPlusCmd        = 0xe0,
211         IntrMitigate    = 0xe2,
212         RxDescAddrLow   = 0xe4,
213         RxDescAddrHigh  = 0xe8,
214         EarlyTxThres    = 0xec,
215         FuncEvent       = 0xf0,
216         FuncEventMask   = 0xf4,
217         FuncPresetState = 0xf8,
218         FuncForceEvent  = 0xfc,
219 };
220
221 enum rtl8110_registers {
222         TBICSR                  = 0x64,
223         TBI_ANAR                = 0x68,
224         TBI_LPAR                = 0x6a,
225 };
226
227 enum rtl8168_8101_registers {
228         CSIDR                   = 0x64,
229         CSIAR                   = 0x68,
230 #define CSIAR_FLAG                      0x80000000
231 #define CSIAR_WRITE_CMD                 0x80000000
232 #define CSIAR_BYTE_ENABLE               0x0f
233 #define CSIAR_BYTE_ENABLE_SHIFT         12
234 #define CSIAR_ADDR_MASK                 0x0fff
235
236         EPHYAR                  = 0x80,
237 #define EPHYAR_FLAG                     0x80000000
238 #define EPHYAR_WRITE_CMD                0x80000000
239 #define EPHYAR_REG_MASK                 0x1f
240 #define EPHYAR_REG_SHIFT                16
241 #define EPHYAR_DATA_MASK                0xffff
242         DBG_REG                 = 0xd1,
243 #define FIX_NAK_1                       (1 << 4)
244 #define FIX_NAK_2                       (1 << 3)
245 };
246
247 enum rtl_register_content {
248         /* InterruptStatusBits */
249         SYSErr          = 0x8000,
250         PCSTimeout      = 0x4000,
251         SWInt           = 0x0100,
252         TxDescUnavail   = 0x0080,
253         RxFIFOOver      = 0x0040,
254         LinkChg         = 0x0020,
255         RxOverflow      = 0x0010,
256         TxErr           = 0x0008,
257         TxOK            = 0x0004,
258         RxErr           = 0x0002,
259         RxOK            = 0x0001,
260
261         /* RxStatusDesc */
262         RxFOVF  = (1 << 23),
263         RxRWT   = (1 << 22),
264         RxRES   = (1 << 21),
265         RxRUNT  = (1 << 20),
266         RxCRC   = (1 << 19),
267
268         /* ChipCmdBits */
269         CmdReset        = 0x10,
270         CmdRxEnb        = 0x08,
271         CmdTxEnb        = 0x04,
272         RxBufEmpty      = 0x01,
273
274         /* TXPoll register p.5 */
275         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
276         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
277         FSWInt          = 0x01,         /* Forced software interrupt */
278
279         /* Cfg9346Bits */
280         Cfg9346_Lock    = 0x00,
281         Cfg9346_Unlock  = 0xc0,
282
283         /* rx_mode_bits */
284         AcceptErr       = 0x20,
285         AcceptRunt      = 0x10,
286         AcceptBroadcast = 0x08,
287         AcceptMulticast = 0x04,
288         AcceptMyPhys    = 0x02,
289         AcceptAllPhys   = 0x01,
290
291         /* RxConfigBits */
292         RxCfgFIFOShift  = 13,
293         RxCfgDMAShift   =  8,
294
295         /* TxConfigBits */
296         TxInterFrameGapShift = 24,
297         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
298
299         /* Config1 register p.24 */
300         LEDS1           = (1 << 7),
301         LEDS0           = (1 << 6),
302         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
303         Speed_down      = (1 << 4),
304         MEMMAP          = (1 << 3),
305         IOMAP           = (1 << 2),
306         VPD             = (1 << 1),
307         PMEnable        = (1 << 0),     /* Power Management Enable */
308
309         /* Config2 register p. 25 */
310         PCI_Clock_66MHz = 0x01,
311         PCI_Clock_33MHz = 0x00,
312
313         /* Config3 register p.25 */
314         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
315         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
316         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
317
318         /* Config5 register p.27 */
319         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
320         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
321         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
322         LanWake         = (1 << 1),     /* LanWake enable/disable */
323         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
324
325         /* TBICSR p.28 */
326         TBIReset        = 0x80000000,
327         TBILoopback     = 0x40000000,
328         TBINwEnable     = 0x20000000,
329         TBINwRestart    = 0x10000000,
330         TBILinkOk       = 0x02000000,
331         TBINwComplete   = 0x01000000,
332
333         /* CPlusCmd p.31 */
334         EnableBist      = (1 << 15),    // 8168 8101
335         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
336         Normal_mode     = (1 << 13),    // unused
337         Force_half_dup  = (1 << 12),    // 8168 8101
338         Force_rxflow_en = (1 << 11),    // 8168 8101
339         Force_txflow_en = (1 << 10),    // 8168 8101
340         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
341         ASF             = (1 << 8),     // 8168 8101
342         PktCntrDisable  = (1 << 7),     // 8168 8101
343         Mac_dbgo_sel    = 0x001c,       // 8168
344         RxVlan          = (1 << 6),
345         RxChkSum        = (1 << 5),
346         PCIDAC          = (1 << 4),
347         PCIMulRW        = (1 << 3),
348         INTT_0          = 0x0000,       // 8168
349         INTT_1          = 0x0001,       // 8168
350         INTT_2          = 0x0002,       // 8168
351         INTT_3          = 0x0003,       // 8168
352
353         /* rtl8169_PHYstatus */
354         TBI_Enable      = 0x80,
355         TxFlowCtrl      = 0x40,
356         RxFlowCtrl      = 0x20,
357         _1000bpsF       = 0x10,
358         _100bps         = 0x08,
359         _10bps          = 0x04,
360         LinkStatus      = 0x02,
361         FullDup         = 0x01,
362
363         /* _TBICSRBit */
364         TBILinkOK       = 0x02000000,
365
366         /* DumpCounterCommand */
367         CounterDump     = 0x8,
368 };
369
370 enum desc_status_bit {
371         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
372         RingEnd         = (1 << 30), /* End of descriptor ring */
373         FirstFrag       = (1 << 29), /* First segment of a packet */
374         LastFrag        = (1 << 28), /* Final segment of a packet */
375
376         /* Tx private */
377         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
378         MSSShift        = 16,        /* MSS value position */
379         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
380         IPCS            = (1 << 18), /* Calculate IP checksum */
381         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
382         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
383         TxVlanTag       = (1 << 17), /* Add VLAN tag */
384
385         /* Rx private */
386         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
387         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
388
389 #define RxProtoUDP      (PID1)
390 #define RxProtoTCP      (PID0)
391 #define RxProtoIP       (PID1 | PID0)
392 #define RxProtoMask     RxProtoIP
393
394         IPFail          = (1 << 16), /* IP checksum failed */
395         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
396         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
397         RxVlanTag       = (1 << 16), /* VLAN tag available */
398 };
399
400 #define RsvdMask        0x3fffc000
401
402 struct TxDesc {
403         __le32 opts1;
404         __le32 opts2;
405         __le64 addr;
406 };
407
408 struct RxDesc {
409         __le32 opts1;
410         __le32 opts2;
411         __le64 addr;
412 };
413
414 struct ring_info {
415         struct sk_buff  *skb;
416         u32             len;
417         u8              __pad[sizeof(void *) - sizeof(u32)];
418 };
419
420 enum features {
421         RTL_FEATURE_WOL         = (1 << 0),
422         RTL_FEATURE_MSI         = (1 << 1),
423         RTL_FEATURE_GMII        = (1 << 2),
424 };
425
426 struct rtl8169_private {
427         void __iomem *mmio_addr;        /* memory map physical address */
428         struct pci_dev *pci_dev;        /* Index of PCI device */
429         struct net_device *dev;
430         struct napi_struct napi;
431         spinlock_t lock;                /* spin lock flag */
432         u32 msg_enable;
433         int chipset;
434         int mac_version;
435         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
436         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
437         u32 dirty_rx;
438         u32 dirty_tx;
439         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
440         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
441         dma_addr_t TxPhyAddr;
442         dma_addr_t RxPhyAddr;
443         struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
444         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
445         unsigned align;
446         unsigned rx_buf_sz;
447         struct timer_list timer;
448         u16 cp_cmd;
449         u16 intr_event;
450         u16 napi_event;
451         u16 intr_mask;
452         int phy_auto_nego_reg;
453         int phy_1000_ctrl_reg;
454 #ifdef CONFIG_R8169_VLAN
455         struct vlan_group *vlgrp;
456 #endif
457         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
458         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
459         void (*phy_reset_enable)(void __iomem *);
460         void (*hw_start)(struct net_device *);
461         unsigned int (*phy_reset_pending)(void __iomem *);
462         unsigned int (*link_ok)(void __iomem *);
463         int pcie_cap;
464         struct delayed_work task;
465         unsigned features;
466
467         struct mii_if_info mii;
468 };
469
470 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
471 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
472 module_param(rx_copybreak, int, 0);
473 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
474 module_param(use_dac, int, 0);
475 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
476 module_param_named(debug, debug.msg_enable, int, 0);
477 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
478 MODULE_LICENSE("GPL");
479 MODULE_VERSION(RTL8169_VERSION);
480
481 static int rtl8169_open(struct net_device *dev);
482 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
483 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
484 static int rtl8169_init_ring(struct net_device *dev);
485 static void rtl_hw_start(struct net_device *dev);
486 static int rtl8169_close(struct net_device *dev);
487 static void rtl_set_rx_mode(struct net_device *dev);
488 static void rtl8169_tx_timeout(struct net_device *dev);
489 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
490 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
491                                 void __iomem *, u32 budget);
492 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
493 static void rtl8169_down(struct net_device *dev);
494 static void rtl8169_rx_clear(struct rtl8169_private *tp);
495 static int rtl8169_poll(struct napi_struct *napi, int budget);
496
497 static const unsigned int rtl8169_rx_config =
498         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
499
500 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
501 {
502         int i;
503
504         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
505
506         for (i = 20; i > 0; i--) {
507                 /*
508                  * Check if the RTL8169 has completed writing to the specified
509                  * MII register.
510                  */
511                 if (!(RTL_R32(PHYAR) & 0x80000000))
512                         break;
513                 udelay(25);
514         }
515 }
516
517 static int mdio_read(void __iomem *ioaddr, int reg_addr)
518 {
519         int i, value = -1;
520
521         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
522
523         for (i = 20; i > 0; i--) {
524                 /*
525                  * Check if the RTL8169 has completed retrieving data from
526                  * the specified MII register.
527                  */
528                 if (RTL_R32(PHYAR) & 0x80000000) {
529                         value = RTL_R32(PHYAR) & 0xffff;
530                         break;
531                 }
532                 udelay(25);
533         }
534         return value;
535 }
536
537 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
538 {
539         mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
540 }
541
542 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
543                            int val)
544 {
545         struct rtl8169_private *tp = netdev_priv(dev);
546         void __iomem *ioaddr = tp->mmio_addr;
547
548         mdio_write(ioaddr, location, val);
549 }
550
551 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
552 {
553         struct rtl8169_private *tp = netdev_priv(dev);
554         void __iomem *ioaddr = tp->mmio_addr;
555
556         return mdio_read(ioaddr, location);
557 }
558
559 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
560 {
561         unsigned int i;
562
563         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
564                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
565
566         for (i = 0; i < 100; i++) {
567                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
568                         break;
569                 udelay(10);
570         }
571 }
572
573 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
574 {
575         u16 value = 0xffff;
576         unsigned int i;
577
578         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
579
580         for (i = 0; i < 100; i++) {
581                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
582                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
583                         break;
584                 }
585                 udelay(10);
586         }
587
588         return value;
589 }
590
591 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
592 {
593         unsigned int i;
594
595         RTL_W32(CSIDR, value);
596         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
597                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
598
599         for (i = 0; i < 100; i++) {
600                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
601                         break;
602                 udelay(10);
603         }
604 }
605
606 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
607 {
608         u32 value = ~0x00;
609         unsigned int i;
610
611         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
612                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
613
614         for (i = 0; i < 100; i++) {
615                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
616                         value = RTL_R32(CSIDR);
617                         break;
618                 }
619                 udelay(10);
620         }
621
622         return value;
623 }
624
625 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
626 {
627         RTL_W16(IntrMask, 0x0000);
628
629         RTL_W16(IntrStatus, 0xffff);
630 }
631
632 static void rtl8169_asic_down(void __iomem *ioaddr)
633 {
634         RTL_W8(ChipCmd, 0x00);
635         rtl8169_irq_mask_and_ack(ioaddr);
636         RTL_R16(CPlusCmd);
637 }
638
639 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
640 {
641         return RTL_R32(TBICSR) & TBIReset;
642 }
643
644 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
645 {
646         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
647 }
648
649 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
650 {
651         return RTL_R32(TBICSR) & TBILinkOk;
652 }
653
654 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
655 {
656         return RTL_R8(PHYstatus) & LinkStatus;
657 }
658
659 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
660 {
661         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
662 }
663
664 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
665 {
666         unsigned int val;
667
668         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
669         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
670 }
671
672 static void rtl8169_check_link_status(struct net_device *dev,
673                                       struct rtl8169_private *tp,
674                                       void __iomem *ioaddr)
675 {
676         unsigned long flags;
677
678         spin_lock_irqsave(&tp->lock, flags);
679         if (tp->link_ok(ioaddr)) {
680                 netif_carrier_on(dev);
681                 if (netif_msg_ifup(tp))
682                         printk(KERN_INFO PFX "%s: link up\n", dev->name);
683         } else {
684                 if (netif_msg_ifdown(tp))
685                         printk(KERN_INFO PFX "%s: link down\n", dev->name);
686                 netif_carrier_off(dev);
687         }
688         spin_unlock_irqrestore(&tp->lock, flags);
689 }
690
691 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
692 {
693         struct rtl8169_private *tp = netdev_priv(dev);
694         void __iomem *ioaddr = tp->mmio_addr;
695         u8 options;
696
697         wol->wolopts = 0;
698
699 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
700         wol->supported = WAKE_ANY;
701
702         spin_lock_irq(&tp->lock);
703
704         options = RTL_R8(Config1);
705         if (!(options & PMEnable))
706                 goto out_unlock;
707
708         options = RTL_R8(Config3);
709         if (options & LinkUp)
710                 wol->wolopts |= WAKE_PHY;
711         if (options & MagicPacket)
712                 wol->wolopts |= WAKE_MAGIC;
713
714         options = RTL_R8(Config5);
715         if (options & UWF)
716                 wol->wolopts |= WAKE_UCAST;
717         if (options & BWF)
718                 wol->wolopts |= WAKE_BCAST;
719         if (options & MWF)
720                 wol->wolopts |= WAKE_MCAST;
721
722 out_unlock:
723         spin_unlock_irq(&tp->lock);
724 }
725
726 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
727 {
728         struct rtl8169_private *tp = netdev_priv(dev);
729         void __iomem *ioaddr = tp->mmio_addr;
730         unsigned int i;
731         static struct {
732                 u32 opt;
733                 u16 reg;
734                 u8  mask;
735         } cfg[] = {
736                 { WAKE_ANY,   Config1, PMEnable },
737                 { WAKE_PHY,   Config3, LinkUp },
738                 { WAKE_MAGIC, Config3, MagicPacket },
739                 { WAKE_UCAST, Config5, UWF },
740                 { WAKE_BCAST, Config5, BWF },
741                 { WAKE_MCAST, Config5, MWF },
742                 { WAKE_ANY,   Config5, LanWake }
743         };
744
745         spin_lock_irq(&tp->lock);
746
747         RTL_W8(Cfg9346, Cfg9346_Unlock);
748
749         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
750                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
751                 if (wol->wolopts & cfg[i].opt)
752                         options |= cfg[i].mask;
753                 RTL_W8(cfg[i].reg, options);
754         }
755
756         RTL_W8(Cfg9346, Cfg9346_Lock);
757
758         if (wol->wolopts)
759                 tp->features |= RTL_FEATURE_WOL;
760         else
761                 tp->features &= ~RTL_FEATURE_WOL;
762         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
763
764         spin_unlock_irq(&tp->lock);
765
766         return 0;
767 }
768
769 static void rtl8169_get_drvinfo(struct net_device *dev,
770                                 struct ethtool_drvinfo *info)
771 {
772         struct rtl8169_private *tp = netdev_priv(dev);
773
774         strcpy(info->driver, MODULENAME);
775         strcpy(info->version, RTL8169_VERSION);
776         strcpy(info->bus_info, pci_name(tp->pci_dev));
777 }
778
779 static int rtl8169_get_regs_len(struct net_device *dev)
780 {
781         return R8169_REGS_SIZE;
782 }
783
784 static int rtl8169_set_speed_tbi(struct net_device *dev,
785                                  u8 autoneg, u16 speed, u8 duplex)
786 {
787         struct rtl8169_private *tp = netdev_priv(dev);
788         void __iomem *ioaddr = tp->mmio_addr;
789         int ret = 0;
790         u32 reg;
791
792         reg = RTL_R32(TBICSR);
793         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
794             (duplex == DUPLEX_FULL)) {
795                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
796         } else if (autoneg == AUTONEG_ENABLE)
797                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
798         else {
799                 if (netif_msg_link(tp)) {
800                         printk(KERN_WARNING "%s: "
801                                "incorrect speed setting refused in TBI mode\n",
802                                dev->name);
803                 }
804                 ret = -EOPNOTSUPP;
805         }
806
807         return ret;
808 }
809
810 static int rtl8169_set_speed_xmii(struct net_device *dev,
811                                   u8 autoneg, u16 speed, u8 duplex)
812 {
813         struct rtl8169_private *tp = netdev_priv(dev);
814         void __iomem *ioaddr = tp->mmio_addr;
815         int auto_nego, giga_ctrl;
816
817         auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
818         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
819                        ADVERTISE_100HALF | ADVERTISE_100FULL);
820         giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
821         giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
822
823         if (autoneg == AUTONEG_ENABLE) {
824                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
825                               ADVERTISE_100HALF | ADVERTISE_100FULL);
826                 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
827         } else {
828                 if (speed == SPEED_10)
829                         auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
830                 else if (speed == SPEED_100)
831                         auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
832                 else if (speed == SPEED_1000)
833                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
834
835                 if (duplex == DUPLEX_HALF)
836                         auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
837
838                 if (duplex == DUPLEX_FULL)
839                         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
840
841                 /* This tweak comes straight from Realtek's driver. */
842                 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
843                     ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
844                      (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
845                         auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
846                 }
847         }
848
849         /* The 8100e/8101e/8102e do Fast Ethernet only. */
850         if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
851             (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
852             (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
853             (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
854             (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
855             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
856             (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
857             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
858                 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
859                     netif_msg_link(tp)) {
860                         printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
861                                dev->name);
862                 }
863                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
864         }
865
866         auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
867
868         if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
869             (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
870             (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
871                 /*
872                  * Wake up the PHY.
873                  * Vendor specific (0x1f) and reserved (0x0e) MII registers.
874                  */
875                 mdio_write(ioaddr, 0x1f, 0x0000);
876                 mdio_write(ioaddr, 0x0e, 0x0000);
877         }
878
879         tp->phy_auto_nego_reg = auto_nego;
880         tp->phy_1000_ctrl_reg = giga_ctrl;
881
882         mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
883         mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
884         mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
885         return 0;
886 }
887
888 static int rtl8169_set_speed(struct net_device *dev,
889                              u8 autoneg, u16 speed, u8 duplex)
890 {
891         struct rtl8169_private *tp = netdev_priv(dev);
892         int ret;
893
894         ret = tp->set_speed(dev, autoneg, speed, duplex);
895
896         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
897                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
898
899         return ret;
900 }
901
902 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
903 {
904         struct rtl8169_private *tp = netdev_priv(dev);
905         unsigned long flags;
906         int ret;
907
908         spin_lock_irqsave(&tp->lock, flags);
909         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
910         spin_unlock_irqrestore(&tp->lock, flags);
911
912         return ret;
913 }
914
915 static u32 rtl8169_get_rx_csum(struct net_device *dev)
916 {
917         struct rtl8169_private *tp = netdev_priv(dev);
918
919         return tp->cp_cmd & RxChkSum;
920 }
921
922 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
923 {
924         struct rtl8169_private *tp = netdev_priv(dev);
925         void __iomem *ioaddr = tp->mmio_addr;
926         unsigned long flags;
927
928         spin_lock_irqsave(&tp->lock, flags);
929
930         if (data)
931                 tp->cp_cmd |= RxChkSum;
932         else
933                 tp->cp_cmd &= ~RxChkSum;
934
935         RTL_W16(CPlusCmd, tp->cp_cmd);
936         RTL_R16(CPlusCmd);
937
938         spin_unlock_irqrestore(&tp->lock, flags);
939
940         return 0;
941 }
942
943 #ifdef CONFIG_R8169_VLAN
944
945 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
946                                       struct sk_buff *skb)
947 {
948         return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
949                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
950 }
951
952 static void rtl8169_vlan_rx_register(struct net_device *dev,
953                                      struct vlan_group *grp)
954 {
955         struct rtl8169_private *tp = netdev_priv(dev);
956         void __iomem *ioaddr = tp->mmio_addr;
957         unsigned long flags;
958
959         spin_lock_irqsave(&tp->lock, flags);
960         tp->vlgrp = grp;
961         if (tp->vlgrp)
962                 tp->cp_cmd |= RxVlan;
963         else
964                 tp->cp_cmd &= ~RxVlan;
965         RTL_W16(CPlusCmd, tp->cp_cmd);
966         RTL_R16(CPlusCmd);
967         spin_unlock_irqrestore(&tp->lock, flags);
968 }
969
970 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
971                                struct sk_buff *skb)
972 {
973         u32 opts2 = le32_to_cpu(desc->opts2);
974         struct vlan_group *vlgrp = tp->vlgrp;
975         int ret;
976
977         if (vlgrp && (opts2 & RxVlanTag)) {
978                 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
979                 ret = 0;
980         } else
981                 ret = -1;
982         desc->opts2 = 0;
983         return ret;
984 }
985
986 #else /* !CONFIG_R8169_VLAN */
987
988 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
989                                       struct sk_buff *skb)
990 {
991         return 0;
992 }
993
994 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
995                                struct sk_buff *skb)
996 {
997         return -1;
998 }
999
1000 #endif
1001
1002 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1003 {
1004         struct rtl8169_private *tp = netdev_priv(dev);
1005         void __iomem *ioaddr = tp->mmio_addr;
1006         u32 status;
1007
1008         cmd->supported =
1009                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1010         cmd->port = PORT_FIBRE;
1011         cmd->transceiver = XCVR_INTERNAL;
1012
1013         status = RTL_R32(TBICSR);
1014         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1015         cmd->autoneg = !!(status & TBINwEnable);
1016
1017         cmd->speed = SPEED_1000;
1018         cmd->duplex = DUPLEX_FULL; /* Always set */
1019
1020         return 0;
1021 }
1022
1023 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1024 {
1025         struct rtl8169_private *tp = netdev_priv(dev);
1026
1027         return mii_ethtool_gset(&tp->mii, cmd);
1028 }
1029
1030 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1031 {
1032         struct rtl8169_private *tp = netdev_priv(dev);
1033         unsigned long flags;
1034         int rc;
1035
1036         spin_lock_irqsave(&tp->lock, flags);
1037
1038         rc = tp->get_settings(dev, cmd);
1039
1040         spin_unlock_irqrestore(&tp->lock, flags);
1041         return rc;
1042 }
1043
1044 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1045                              void *p)
1046 {
1047         struct rtl8169_private *tp = netdev_priv(dev);
1048         unsigned long flags;
1049
1050         if (regs->len > R8169_REGS_SIZE)
1051                 regs->len = R8169_REGS_SIZE;
1052
1053         spin_lock_irqsave(&tp->lock, flags);
1054         memcpy_fromio(p, tp->mmio_addr, regs->len);
1055         spin_unlock_irqrestore(&tp->lock, flags);
1056 }
1057
1058 static u32 rtl8169_get_msglevel(struct net_device *dev)
1059 {
1060         struct rtl8169_private *tp = netdev_priv(dev);
1061
1062         return tp->msg_enable;
1063 }
1064
1065 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1066 {
1067         struct rtl8169_private *tp = netdev_priv(dev);
1068
1069         tp->msg_enable = value;
1070 }
1071
1072 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1073         "tx_packets",
1074         "rx_packets",
1075         "tx_errors",
1076         "rx_errors",
1077         "rx_missed",
1078         "align_errors",
1079         "tx_single_collisions",
1080         "tx_multi_collisions",
1081         "unicast",
1082         "broadcast",
1083         "multicast",
1084         "tx_aborted",
1085         "tx_underrun",
1086 };
1087
1088 struct rtl8169_counters {
1089         __le64  tx_packets;
1090         __le64  rx_packets;
1091         __le64  tx_errors;
1092         __le32  rx_errors;
1093         __le16  rx_missed;
1094         __le16  align_errors;
1095         __le32  tx_one_collision;
1096         __le32  tx_multi_collision;
1097         __le64  rx_unicast;
1098         __le64  rx_broadcast;
1099         __le32  rx_multicast;
1100         __le16  tx_aborted;
1101         __le16  tx_underun;
1102 };
1103
1104 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1105 {
1106         switch (sset) {
1107         case ETH_SS_STATS:
1108                 return ARRAY_SIZE(rtl8169_gstrings);
1109         default:
1110                 return -EOPNOTSUPP;
1111         }
1112 }
1113
1114 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1115                                       struct ethtool_stats *stats, u64 *data)
1116 {
1117         struct rtl8169_private *tp = netdev_priv(dev);
1118         void __iomem *ioaddr = tp->mmio_addr;
1119         struct rtl8169_counters *counters;
1120         dma_addr_t paddr;
1121         u32 cmd;
1122
1123         ASSERT_RTNL();
1124
1125         counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1126         if (!counters)
1127                 return;
1128
1129         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1130         cmd = (u64)paddr & DMA_32BIT_MASK;
1131         RTL_W32(CounterAddrLow, cmd);
1132         RTL_W32(CounterAddrLow, cmd | CounterDump);
1133
1134         while (RTL_R32(CounterAddrLow) & CounterDump) {
1135                 if (msleep_interruptible(1))
1136                         break;
1137         }
1138
1139         RTL_W32(CounterAddrLow, 0);
1140         RTL_W32(CounterAddrHigh, 0);
1141
1142         data[0] = le64_to_cpu(counters->tx_packets);
1143         data[1] = le64_to_cpu(counters->rx_packets);
1144         data[2] = le64_to_cpu(counters->tx_errors);
1145         data[3] = le32_to_cpu(counters->rx_errors);
1146         data[4] = le16_to_cpu(counters->rx_missed);
1147         data[5] = le16_to_cpu(counters->align_errors);
1148         data[6] = le32_to_cpu(counters->tx_one_collision);
1149         data[7] = le32_to_cpu(counters->tx_multi_collision);
1150         data[8] = le64_to_cpu(counters->rx_unicast);
1151         data[9] = le64_to_cpu(counters->rx_broadcast);
1152         data[10] = le32_to_cpu(counters->rx_multicast);
1153         data[11] = le16_to_cpu(counters->tx_aborted);
1154         data[12] = le16_to_cpu(counters->tx_underun);
1155
1156         pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1157 }
1158
1159 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1160 {
1161         switch(stringset) {
1162         case ETH_SS_STATS:
1163                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1164                 break;
1165         }
1166 }
1167
1168 static const struct ethtool_ops rtl8169_ethtool_ops = {
1169         .get_drvinfo            = rtl8169_get_drvinfo,
1170         .get_regs_len           = rtl8169_get_regs_len,
1171         .get_link               = ethtool_op_get_link,
1172         .get_settings           = rtl8169_get_settings,
1173         .set_settings           = rtl8169_set_settings,
1174         .get_msglevel           = rtl8169_get_msglevel,
1175         .set_msglevel           = rtl8169_set_msglevel,
1176         .get_rx_csum            = rtl8169_get_rx_csum,
1177         .set_rx_csum            = rtl8169_set_rx_csum,
1178         .set_tx_csum            = ethtool_op_set_tx_csum,
1179         .set_sg                 = ethtool_op_set_sg,
1180         .set_tso                = ethtool_op_set_tso,
1181         .get_regs               = rtl8169_get_regs,
1182         .get_wol                = rtl8169_get_wol,
1183         .set_wol                = rtl8169_set_wol,
1184         .get_strings            = rtl8169_get_strings,
1185         .get_sset_count         = rtl8169_get_sset_count,
1186         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1187 };
1188
1189 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1190                                        int bitnum, int bitval)
1191 {
1192         int val;
1193
1194         val = mdio_read(ioaddr, reg);
1195         val = (bitval == 1) ?
1196                 val | (bitval << bitnum) :  val & ~(0x0001 << bitnum);
1197         mdio_write(ioaddr, reg, val & 0xffff);
1198 }
1199
1200 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1201                                     void __iomem *ioaddr)
1202 {
1203         /*
1204          * The driver currently handles the 8168Bf and the 8168Be identically
1205          * but they can be identified more specifically through the test below
1206          * if needed:
1207          *
1208          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1209          *
1210          * Same thing for the 8101Eb and the 8101Ec:
1211          *
1212          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1213          */
1214         const struct {
1215                 u32 mask;
1216                 u32 val;
1217                 int mac_version;
1218         } mac_info[] = {
1219                 /* 8168B family. */
1220                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1221                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1222                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1223                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_20 },
1224
1225                 /* 8168B family. */
1226                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1227                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1228                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1229                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1230
1231                 /* 8101 family. */
1232                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1233                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1234                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1235                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1236                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1237                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1238                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1239                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1240                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1241                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1242                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1243                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1244                 /* FIXME: where did these entries come from ? -- FR */
1245                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1246                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1247
1248                 /* 8110 family. */
1249                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1250                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1251                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1252                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1253                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1254                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1255
1256                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_VER_01 }   /* Catch-all */
1257         }, *p = mac_info;
1258         u32 reg;
1259
1260         reg = RTL_R32(TxConfig);
1261         while ((reg & p->mask) != p->val)
1262                 p++;
1263         tp->mac_version = p->mac_version;
1264
1265         if (p->mask == 0x00000000) {
1266                 struct pci_dev *pdev = tp->pci_dev;
1267
1268                 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1269         }
1270 }
1271
1272 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1273 {
1274         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1275 }
1276
1277 struct phy_reg {
1278         u16 reg;
1279         u16 val;
1280 };
1281
1282 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1283 {
1284         while (len-- > 0) {
1285                 mdio_write(ioaddr, regs->reg, regs->val);
1286                 regs++;
1287         }
1288 }
1289
1290 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1291 {
1292         struct {
1293                 u16 regs[5]; /* Beware of bit-sign propagation */
1294         } phy_magic[5] = { {
1295                 { 0x0000,       //w 4 15 12 0
1296                   0x00a1,       //w 3 15 0 00a1
1297                   0x0008,       //w 2 15 0 0008
1298                   0x1020,       //w 1 15 0 1020
1299                   0x1000 } },{  //w 0 15 0 1000
1300                 { 0x7000,       //w 4 15 12 7
1301                   0xff41,       //w 3 15 0 ff41
1302                   0xde60,       //w 2 15 0 de60
1303                   0x0140,       //w 1 15 0 0140
1304                   0x0077 } },{  //w 0 15 0 0077
1305                 { 0xa000,       //w 4 15 12 a
1306                   0xdf01,       //w 3 15 0 df01
1307                   0xdf20,       //w 2 15 0 df20
1308                   0xff95,       //w 1 15 0 ff95
1309                   0xfa00 } },{  //w 0 15 0 fa00
1310                 { 0xb000,       //w 4 15 12 b
1311                   0xff41,       //w 3 15 0 ff41
1312                   0xde20,       //w 2 15 0 de20
1313                   0x0140,       //w 1 15 0 0140
1314                   0x00bb } },{  //w 0 15 0 00bb
1315                 { 0xf000,       //w 4 15 12 f
1316                   0xdf01,       //w 3 15 0 df01
1317                   0xdf20,       //w 2 15 0 df20
1318                   0xff95,       //w 1 15 0 ff95
1319                   0xbf00 }      //w 0 15 0 bf00
1320                 }
1321         }, *p = phy_magic;
1322         unsigned int i;
1323
1324         mdio_write(ioaddr, 0x1f, 0x0001);               //w 31 2 0 1
1325         mdio_write(ioaddr, 0x15, 0x1000);               //w 21 15 0 1000
1326         mdio_write(ioaddr, 0x18, 0x65c7);               //w 24 15 0 65c7
1327         rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
1328
1329         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1330                 int val, pos = 4;
1331
1332                 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1333                 mdio_write(ioaddr, pos, val);
1334                 while (--pos >= 0)
1335                         mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1336                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1337                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1338         }
1339         mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1340 }
1341
1342 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1343 {
1344         struct phy_reg phy_reg_init[] = {
1345                 { 0x1f, 0x0002 },
1346                 { 0x01, 0x90d0 },
1347                 { 0x1f, 0x0000 }
1348         };
1349
1350         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1351 }
1352
1353 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1354 {
1355         struct phy_reg phy_reg_init[] = {
1356                 { 0x10, 0xf41b },
1357                 { 0x1f, 0x0000 }
1358         };
1359
1360         mdio_write(ioaddr, 0x1f, 0x0001);
1361         mdio_patch(ioaddr, 0x16, 1 << 0);
1362
1363         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1364 }
1365
1366 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1367 {
1368         struct phy_reg phy_reg_init[] = {
1369                 { 0x1f, 0x0001 },
1370                 { 0x10, 0xf41b },
1371                 { 0x1f, 0x0000 }
1372         };
1373
1374         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1375 }
1376
1377 static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1378 {
1379         struct phy_reg phy_reg_init[] = {
1380                 { 0x1f, 0x0000 },
1381                 { 0x1d, 0x0f00 },
1382                 { 0x1f, 0x0002 },
1383                 { 0x0c, 0x1ec8 },
1384                 { 0x1f, 0x0000 }
1385         };
1386
1387         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1388 }
1389
1390 static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
1391 {
1392         struct phy_reg phy_reg_init[] = {
1393                 { 0x1f, 0x0001 },
1394                 { 0x12, 0x2300 },
1395                 { 0x1f, 0x0002 },
1396                 { 0x00, 0x88d4 },
1397                 { 0x01, 0x82b1 },
1398                 { 0x03, 0x7002 },
1399                 { 0x08, 0x9e30 },
1400                 { 0x09, 0x01f0 },
1401                 { 0x0a, 0x5500 },
1402                 { 0x0c, 0x00c8 },
1403                 { 0x1f, 0x0003 },
1404                 { 0x12, 0xc096 },
1405                 { 0x16, 0x000a },
1406                 { 0x1f, 0x0000 },
1407                 { 0x1f, 0x0000 },
1408                 { 0x09, 0x2000 },
1409                 { 0x09, 0x0000 }
1410         };
1411
1412         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1413
1414         mdio_patch(ioaddr, 0x14, 1 << 5);
1415         mdio_patch(ioaddr, 0x0d, 1 << 5);
1416         mdio_write(ioaddr, 0x1f, 0x0000);
1417 }
1418
1419 static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
1420 {
1421         struct phy_reg phy_reg_init[] = {
1422                 { 0x1f, 0x0001 },
1423                 { 0x12, 0x2300 },
1424                 { 0x03, 0x802f },
1425                 { 0x02, 0x4f02 },
1426                 { 0x01, 0x0409 },
1427                 { 0x00, 0xf099 },
1428                 { 0x04, 0x9800 },
1429                 { 0x04, 0x9000 },
1430                 { 0x1d, 0x3d98 },
1431                 { 0x1f, 0x0002 },
1432                 { 0x0c, 0x7eb8 },
1433                 { 0x06, 0x0761 },
1434                 { 0x1f, 0x0003 },
1435                 { 0x16, 0x0f0a },
1436                 { 0x1f, 0x0000 }
1437         };
1438
1439         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1440
1441         mdio_patch(ioaddr, 0x16, 1 << 0);
1442         mdio_patch(ioaddr, 0x14, 1 << 5);
1443         mdio_patch(ioaddr, 0x0d, 1 << 5);
1444         mdio_write(ioaddr, 0x1f, 0x0000);
1445 }
1446
1447 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1448 {
1449         struct phy_reg phy_reg_init[] = {
1450                 { 0x1f, 0x0003 },
1451                 { 0x08, 0x441d },
1452                 { 0x01, 0x9100 },
1453                 { 0x1f, 0x0000 }
1454         };
1455
1456         mdio_write(ioaddr, 0x1f, 0x0000);
1457         mdio_patch(ioaddr, 0x11, 1 << 12);
1458         mdio_patch(ioaddr, 0x19, 1 << 13);
1459
1460         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1461 }
1462
1463 static void rtl_hw_phy_config(struct net_device *dev)
1464 {
1465         struct rtl8169_private *tp = netdev_priv(dev);
1466         void __iomem *ioaddr = tp->mmio_addr;
1467
1468         rtl8169_print_mac_version(tp);
1469
1470         switch (tp->mac_version) {
1471         case RTL_GIGA_MAC_VER_01:
1472                 break;
1473         case RTL_GIGA_MAC_VER_02:
1474         case RTL_GIGA_MAC_VER_03:
1475                 rtl8169s_hw_phy_config(ioaddr);
1476                 break;
1477         case RTL_GIGA_MAC_VER_04:
1478                 rtl8169sb_hw_phy_config(ioaddr);
1479                 break;
1480         case RTL_GIGA_MAC_VER_07:
1481         case RTL_GIGA_MAC_VER_08:
1482         case RTL_GIGA_MAC_VER_09:
1483                 rtl8102e_hw_phy_config(ioaddr);
1484                 break;
1485         case RTL_GIGA_MAC_VER_11:
1486                 rtl8168bb_hw_phy_config(ioaddr);
1487                 break;
1488         case RTL_GIGA_MAC_VER_12:
1489                 rtl8168bef_hw_phy_config(ioaddr);
1490                 break;
1491         case RTL_GIGA_MAC_VER_17:
1492                 rtl8168bef_hw_phy_config(ioaddr);
1493                 break;
1494         case RTL_GIGA_MAC_VER_18:
1495                 rtl8168cp_hw_phy_config(ioaddr);
1496                 break;
1497         case RTL_GIGA_MAC_VER_19:
1498                 rtl8168c_hw_phy_config(ioaddr);
1499                 break;
1500         case RTL_GIGA_MAC_VER_20:
1501                 rtl8168cx_hw_phy_config(ioaddr);
1502                 break;
1503         default:
1504                 break;
1505         }
1506 }
1507
1508 static void rtl8169_phy_timer(unsigned long __opaque)
1509 {
1510         struct net_device *dev = (struct net_device *)__opaque;
1511         struct rtl8169_private *tp = netdev_priv(dev);
1512         struct timer_list *timer = &tp->timer;
1513         void __iomem *ioaddr = tp->mmio_addr;
1514         unsigned long timeout = RTL8169_PHY_TIMEOUT;
1515
1516         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1517
1518         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1519                 return;
1520
1521         spin_lock_irq(&tp->lock);
1522
1523         if (tp->phy_reset_pending(ioaddr)) {
1524                 /*
1525                  * A busy loop could burn quite a few cycles on nowadays CPU.
1526                  * Let's delay the execution of the timer for a few ticks.
1527                  */
1528                 timeout = HZ/10;
1529                 goto out_mod_timer;
1530         }
1531
1532         if (tp->link_ok(ioaddr))
1533                 goto out_unlock;
1534
1535         if (netif_msg_link(tp))
1536                 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1537
1538         tp->phy_reset_enable(ioaddr);
1539
1540 out_mod_timer:
1541         mod_timer(timer, jiffies + timeout);
1542 out_unlock:
1543         spin_unlock_irq(&tp->lock);
1544 }
1545
1546 static inline void rtl8169_delete_timer(struct net_device *dev)
1547 {
1548         struct rtl8169_private *tp = netdev_priv(dev);
1549         struct timer_list *timer = &tp->timer;
1550
1551         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1552                 return;
1553
1554         del_timer_sync(timer);
1555 }
1556
1557 static inline void rtl8169_request_timer(struct net_device *dev)
1558 {
1559         struct rtl8169_private *tp = netdev_priv(dev);
1560         struct timer_list *timer = &tp->timer;
1561
1562         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1563                 return;
1564
1565         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1566 }
1567
1568 #ifdef CONFIG_NET_POLL_CONTROLLER
1569 /*
1570  * Polling 'interrupt' - used by things like netconsole to send skbs
1571  * without having to re-enable interrupts. It's not called while
1572  * the interrupt routine is executing.
1573  */
1574 static void rtl8169_netpoll(struct net_device *dev)
1575 {
1576         struct rtl8169_private *tp = netdev_priv(dev);
1577         struct pci_dev *pdev = tp->pci_dev;
1578
1579         disable_irq(pdev->irq);
1580         rtl8169_interrupt(pdev->irq, dev);
1581         enable_irq(pdev->irq);
1582 }
1583 #endif
1584
1585 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1586                                   void __iomem *ioaddr)
1587 {
1588         iounmap(ioaddr);
1589         pci_release_regions(pdev);
1590         pci_disable_device(pdev);
1591         free_netdev(dev);
1592 }
1593
1594 static void rtl8169_phy_reset(struct net_device *dev,
1595                               struct rtl8169_private *tp)
1596 {
1597         void __iomem *ioaddr = tp->mmio_addr;
1598         unsigned int i;
1599
1600         tp->phy_reset_enable(ioaddr);
1601         for (i = 0; i < 100; i++) {
1602                 if (!tp->phy_reset_pending(ioaddr))
1603                         return;
1604                 msleep(1);
1605         }
1606         if (netif_msg_link(tp))
1607                 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1608 }
1609
1610 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1611 {
1612         void __iomem *ioaddr = tp->mmio_addr;
1613
1614         rtl_hw_phy_config(dev);
1615
1616         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1617                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1618                 RTL_W8(0x82, 0x01);
1619         }
1620
1621         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1622
1623         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1624                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1625
1626         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1627                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1628                 RTL_W8(0x82, 0x01);
1629                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1630                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1631         }
1632
1633         rtl8169_phy_reset(dev, tp);
1634
1635         /*
1636          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1637          * only 8101. Don't panic.
1638          */
1639         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1640
1641         if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1642                 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1643 }
1644
1645 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1646 {
1647         void __iomem *ioaddr = tp->mmio_addr;
1648         u32 high;
1649         u32 low;
1650
1651         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1652         high = addr[4] | (addr[5] << 8);
1653
1654         spin_lock_irq(&tp->lock);
1655
1656         RTL_W8(Cfg9346, Cfg9346_Unlock);
1657         RTL_W32(MAC0, low);
1658         RTL_W32(MAC4, high);
1659         RTL_W8(Cfg9346, Cfg9346_Lock);
1660
1661         spin_unlock_irq(&tp->lock);
1662 }
1663
1664 static int rtl_set_mac_address(struct net_device *dev, void *p)
1665 {
1666         struct rtl8169_private *tp = netdev_priv(dev);
1667         struct sockaddr *addr = p;
1668
1669         if (!is_valid_ether_addr(addr->sa_data))
1670                 return -EADDRNOTAVAIL;
1671
1672         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1673
1674         rtl_rar_set(tp, dev->dev_addr);
1675
1676         return 0;
1677 }
1678
1679 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1680 {
1681         struct rtl8169_private *tp = netdev_priv(dev);
1682         struct mii_ioctl_data *data = if_mii(ifr);
1683
1684         if (!netif_running(dev))
1685                 return -ENODEV;
1686
1687         switch (cmd) {
1688         case SIOCGMIIPHY:
1689                 data->phy_id = 32; /* Internal PHY */
1690                 return 0;
1691
1692         case SIOCGMIIREG:
1693                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1694                 return 0;
1695
1696         case SIOCSMIIREG:
1697                 if (!capable(CAP_NET_ADMIN))
1698                         return -EPERM;
1699                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1700                 return 0;
1701         }
1702         return -EOPNOTSUPP;
1703 }
1704
1705 static const struct rtl_cfg_info {
1706         void (*hw_start)(struct net_device *);
1707         unsigned int region;
1708         unsigned int align;
1709         u16 intr_event;
1710         u16 napi_event;
1711         unsigned features;
1712 } rtl_cfg_infos [] = {
1713         [RTL_CFG_0] = {
1714                 .hw_start       = rtl_hw_start_8169,
1715                 .region         = 1,
1716                 .align          = 0,
1717                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1718                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1719                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1720                 .features       = RTL_FEATURE_GMII
1721         },
1722         [RTL_CFG_1] = {
1723                 .hw_start       = rtl_hw_start_8168,
1724                 .region         = 2,
1725                 .align          = 8,
1726                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1727                                   TxErr | TxOK | RxOK | RxErr,
1728                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
1729                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI
1730         },
1731         [RTL_CFG_2] = {
1732                 .hw_start       = rtl_hw_start_8101,
1733                 .region         = 2,
1734                 .align          = 8,
1735                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1736                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1737                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1738                 .features       = RTL_FEATURE_MSI
1739         }
1740 };
1741
1742 /* Cfg9346_Unlock assumed. */
1743 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1744                             const struct rtl_cfg_info *cfg)
1745 {
1746         unsigned msi = 0;
1747         u8 cfg2;
1748
1749         cfg2 = RTL_R8(Config2) & ~MSIEnable;
1750         if (cfg->features & RTL_FEATURE_MSI) {
1751                 if (pci_enable_msi(pdev)) {
1752                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1753                 } else {
1754                         cfg2 |= MSIEnable;
1755                         msi = RTL_FEATURE_MSI;
1756                 }
1757         }
1758         RTL_W8(Config2, cfg2);
1759         return msi;
1760 }
1761
1762 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1763 {
1764         if (tp->features & RTL_FEATURE_MSI) {
1765                 pci_disable_msi(pdev);
1766                 tp->features &= ~RTL_FEATURE_MSI;
1767         }
1768 }
1769
1770 static int rtl_eeprom_read(struct pci_dev *pdev, int cap, int addr, __le32 *val)
1771 {
1772         int ret, count = 100;
1773         u16 status = 0;
1774         u32 value;
1775
1776         ret = pci_write_config_word(pdev, cap + PCI_VPD_ADDR, addr);
1777         if (ret < 0)
1778                 return ret;
1779
1780         do {
1781                 udelay(10);
1782                 ret = pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &status);
1783                 if (ret < 0)
1784                         return ret;
1785         } while (!(status & PCI_VPD_ADDR_F) && --count);
1786
1787         if (!(status & PCI_VPD_ADDR_F))
1788                 return -ETIMEDOUT;
1789
1790         ret = pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &value);
1791         if (ret < 0)
1792                 return ret;
1793
1794         *val = cpu_to_le32(value);
1795
1796         return 0;
1797 }
1798
1799 static void rtl_init_mac_address(struct rtl8169_private *tp,
1800                                  void __iomem *ioaddr)
1801 {
1802         struct pci_dev *pdev = tp->pci_dev;
1803         u8 cfg1;
1804         int vpd_cap;
1805         u8 mac[8];
1806         DECLARE_MAC_BUF(buf);
1807
1808         cfg1 = RTL_R8(Config1);
1809         if (!(cfg1  & VPD)) {
1810                 dprintk("VPD access not enabled, enabling\n");
1811                 RTL_W8(Cfg9346, Cfg9346_Unlock);
1812                 RTL_W8(Config1, cfg1 | VPD);
1813                 RTL_W8(Cfg9346, Cfg9346_Lock);
1814         }
1815
1816         vpd_cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
1817         if (!vpd_cap)
1818                 return;
1819
1820         /* MAC address is stored in EEPROM at offset 0x0e
1821          * Realtek says: "The VPD address does not have to be a DWORD-aligned
1822          * address as defined in the PCI 2.2 Specifications, but the VPD data
1823          * is always consecutive 4-byte data starting from the VPD address
1824          * specified."
1825          */
1826         if (rtl_eeprom_read(pdev, vpd_cap, 0x000e, (__le32*)&mac[0]) < 0 ||
1827             rtl_eeprom_read(pdev, vpd_cap, 0x0012, (__le32*)&mac[4]) < 0) {
1828                 dprintk("Reading MAC address from EEPROM failed\n");
1829                 return;
1830         }
1831
1832         dprintk("MAC address found in EEPROM: %s\n", print_mac(buf, mac));
1833
1834         /* Write MAC address */
1835         rtl_rar_set(tp, mac);
1836 }
1837
1838 static int __devinit
1839 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1840 {
1841         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1842         const unsigned int region = cfg->region;
1843         struct rtl8169_private *tp;
1844         struct mii_if_info *mii;
1845         struct net_device *dev;
1846         void __iomem *ioaddr;
1847         unsigned int i;
1848         int rc;
1849
1850         if (netif_msg_drv(&debug)) {
1851                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1852                        MODULENAME, RTL8169_VERSION);
1853         }
1854
1855         dev = alloc_etherdev(sizeof (*tp));
1856         if (!dev) {
1857                 if (netif_msg_drv(&debug))
1858                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1859                 rc = -ENOMEM;
1860                 goto out;
1861         }
1862
1863         SET_NETDEV_DEV(dev, &pdev->dev);
1864         tp = netdev_priv(dev);
1865         tp->dev = dev;
1866         tp->pci_dev = pdev;
1867         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1868
1869         mii = &tp->mii;
1870         mii->dev = dev;
1871         mii->mdio_read = rtl_mdio_read;
1872         mii->mdio_write = rtl_mdio_write;
1873         mii->phy_id_mask = 0x1f;
1874         mii->reg_num_mask = 0x1f;
1875         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1876
1877         /* enable device (incl. PCI PM wakeup and hotplug setup) */
1878         rc = pci_enable_device(pdev);
1879         if (rc < 0) {
1880                 if (netif_msg_probe(tp))
1881                         dev_err(&pdev->dev, "enable failure\n");
1882                 goto err_out_free_dev_1;
1883         }
1884
1885         rc = pci_set_mwi(pdev);
1886         if (rc < 0)
1887                 goto err_out_disable_2;
1888
1889         /* make sure PCI base addr 1 is MMIO */
1890         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1891                 if (netif_msg_probe(tp)) {
1892                         dev_err(&pdev->dev,
1893                                 "region #%d not an MMIO resource, aborting\n",
1894                                 region);
1895                 }
1896                 rc = -ENODEV;
1897                 goto err_out_mwi_3;
1898         }
1899
1900         /* check for weird/broken PCI region reporting */
1901         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1902                 if (netif_msg_probe(tp)) {
1903                         dev_err(&pdev->dev,
1904                                 "Invalid PCI region size(s), aborting\n");
1905                 }
1906                 rc = -ENODEV;
1907                 goto err_out_mwi_3;
1908         }
1909
1910         rc = pci_request_regions(pdev, MODULENAME);
1911         if (rc < 0) {
1912                 if (netif_msg_probe(tp))
1913                         dev_err(&pdev->dev, "could not request regions.\n");
1914                 goto err_out_mwi_3;
1915         }
1916
1917         tp->cp_cmd = PCIMulRW | RxChkSum;
1918
1919         if ((sizeof(dma_addr_t) > 4) &&
1920             !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1921                 tp->cp_cmd |= PCIDAC;
1922                 dev->features |= NETIF_F_HIGHDMA;
1923         } else {
1924                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1925                 if (rc < 0) {
1926                         if (netif_msg_probe(tp)) {
1927                                 dev_err(&pdev->dev,
1928                                         "DMA configuration failed.\n");
1929                         }
1930                         goto err_out_free_res_4;
1931                 }
1932         }
1933
1934         pci_set_master(pdev);
1935
1936         /* ioremap MMIO region */
1937         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1938         if (!ioaddr) {
1939                 if (netif_msg_probe(tp))
1940                         dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1941                 rc = -EIO;
1942                 goto err_out_free_res_4;
1943         }
1944
1945         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1946         if (!tp->pcie_cap && netif_msg_probe(tp))
1947                 dev_info(&pdev->dev, "no PCI Express capability\n");
1948
1949         /* Unneeded ? Don't mess with Mrs. Murphy. */
1950         rtl8169_irq_mask_and_ack(ioaddr);
1951
1952         /* Soft reset the chip. */
1953         RTL_W8(ChipCmd, CmdReset);
1954
1955         /* Check that the chip has finished the reset. */
1956         for (i = 0; i < 100; i++) {
1957                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1958                         break;
1959                 msleep_interruptible(1);
1960         }
1961
1962         /* Identify chip attached to board */
1963         rtl8169_get_mac_version(tp, ioaddr);
1964
1965         rtl8169_print_mac_version(tp);
1966
1967         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1968                 if (tp->mac_version == rtl_chip_info[i].mac_version)
1969                         break;
1970         }
1971         if (i == ARRAY_SIZE(rtl_chip_info)) {
1972                 /* Unknown chip: assume array element #0, original RTL-8169 */
1973                 if (netif_msg_probe(tp)) {
1974                         dev_printk(KERN_DEBUG, &pdev->dev,
1975                                 "unknown chip version, assuming %s\n",
1976                                 rtl_chip_info[0].name);
1977                 }
1978                 i = 0;
1979         }
1980         tp->chipset = i;
1981
1982         RTL_W8(Cfg9346, Cfg9346_Unlock);
1983         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1984         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1985         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
1986                 tp->features |= RTL_FEATURE_WOL;
1987         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
1988                 tp->features |= RTL_FEATURE_WOL;
1989         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
1990         RTL_W8(Cfg9346, Cfg9346_Lock);
1991
1992         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
1993             (RTL_R8(PHYstatus) & TBI_Enable)) {
1994                 tp->set_speed = rtl8169_set_speed_tbi;
1995                 tp->get_settings = rtl8169_gset_tbi;
1996                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1997                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1998                 tp->link_ok = rtl8169_tbi_link_ok;
1999
2000                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
2001         } else {
2002                 tp->set_speed = rtl8169_set_speed_xmii;
2003                 tp->get_settings = rtl8169_gset_xmii;
2004                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2005                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2006                 tp->link_ok = rtl8169_xmii_link_ok;
2007
2008                 dev->do_ioctl = rtl8169_ioctl;
2009         }
2010
2011         spin_lock_init(&tp->lock);
2012
2013         rtl_init_mac_address(tp, ioaddr);
2014
2015         /* Get MAC address */
2016         for (i = 0; i < MAC_ADDR_LEN; i++)
2017                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
2018         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2019
2020         dev->open = rtl8169_open;
2021         dev->hard_start_xmit = rtl8169_start_xmit;
2022         dev->get_stats = rtl8169_get_stats;
2023         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2024         dev->stop = rtl8169_close;
2025         dev->tx_timeout = rtl8169_tx_timeout;
2026         dev->set_multicast_list = rtl_set_rx_mode;
2027         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2028         dev->irq = pdev->irq;
2029         dev->base_addr = (unsigned long) ioaddr;
2030         dev->change_mtu = rtl8169_change_mtu;
2031         dev->set_mac_address = rtl_set_mac_address;
2032
2033         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
2034
2035 #ifdef CONFIG_R8169_VLAN
2036         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2037         dev->vlan_rx_register = rtl8169_vlan_rx_register;
2038 #endif
2039
2040 #ifdef CONFIG_NET_POLL_CONTROLLER
2041         dev->poll_controller = rtl8169_netpoll;
2042 #endif
2043
2044         tp->intr_mask = 0xffff;
2045         tp->mmio_addr = ioaddr;
2046         tp->align = cfg->align;
2047         tp->hw_start = cfg->hw_start;
2048         tp->intr_event = cfg->intr_event;
2049         tp->napi_event = cfg->napi_event;
2050
2051         init_timer(&tp->timer);
2052         tp->timer.data = (unsigned long) dev;
2053         tp->timer.function = rtl8169_phy_timer;
2054
2055         rc = register_netdev(dev);
2056         if (rc < 0)
2057                 goto err_out_msi_5;
2058
2059         pci_set_drvdata(pdev, dev);
2060
2061         if (netif_msg_probe(tp)) {
2062                 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2063
2064                 printk(KERN_INFO "%s: %s at 0x%lx, "
2065                        "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2066                        "XID %08x IRQ %d\n",
2067                        dev->name,
2068                        rtl_chip_info[tp->chipset].name,
2069                        dev->base_addr,
2070                        dev->dev_addr[0], dev->dev_addr[1],
2071                        dev->dev_addr[2], dev->dev_addr[3],
2072                        dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
2073         }
2074
2075         rtl8169_init_phy(dev, tp);
2076         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
2077
2078 out:
2079         return rc;
2080
2081 err_out_msi_5:
2082         rtl_disable_msi(pdev, tp);
2083         iounmap(ioaddr);
2084 err_out_free_res_4:
2085         pci_release_regions(pdev);
2086 err_out_mwi_3:
2087         pci_clear_mwi(pdev);
2088 err_out_disable_2:
2089         pci_disable_device(pdev);
2090 err_out_free_dev_1:
2091         free_netdev(dev);
2092         goto out;
2093 }
2094
2095 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
2096 {
2097         struct net_device *dev = pci_get_drvdata(pdev);
2098         struct rtl8169_private *tp = netdev_priv(dev);
2099
2100         flush_scheduled_work();
2101
2102         unregister_netdev(dev);
2103         rtl_disable_msi(pdev, tp);
2104         rtl8169_release_board(pdev, dev, tp->mmio_addr);
2105         pci_set_drvdata(pdev, NULL);
2106 }
2107
2108 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2109                                   struct net_device *dev)
2110 {
2111         unsigned int mtu = dev->mtu;
2112
2113         tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2114 }
2115
2116 static int rtl8169_open(struct net_device *dev)
2117 {
2118         struct rtl8169_private *tp = netdev_priv(dev);
2119         struct pci_dev *pdev = tp->pci_dev;
2120         int retval = -ENOMEM;
2121
2122
2123         rtl8169_set_rxbufsize(tp, dev);
2124
2125         /*
2126          * Rx and Tx desscriptors needs 256 bytes alignment.
2127          * pci_alloc_consistent provides more.
2128          */
2129         tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2130                                                &tp->TxPhyAddr);
2131         if (!tp->TxDescArray)
2132                 goto out;
2133
2134         tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2135                                                &tp->RxPhyAddr);
2136         if (!tp->RxDescArray)
2137                 goto err_free_tx_0;
2138
2139         retval = rtl8169_init_ring(dev);
2140         if (retval < 0)
2141                 goto err_free_rx_1;
2142
2143         INIT_DELAYED_WORK(&tp->task, NULL);
2144
2145         smp_mb();
2146
2147         retval = request_irq(dev->irq, rtl8169_interrupt,
2148                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2149                              dev->name, dev);
2150         if (retval < 0)
2151                 goto err_release_ring_2;
2152
2153         napi_enable(&tp->napi);
2154
2155         rtl_hw_start(dev);
2156
2157         rtl8169_request_timer(dev);
2158
2159         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2160 out:
2161         return retval;
2162
2163 err_release_ring_2:
2164         rtl8169_rx_clear(tp);
2165 err_free_rx_1:
2166         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2167                             tp->RxPhyAddr);
2168 err_free_tx_0:
2169         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2170                             tp->TxPhyAddr);
2171         goto out;
2172 }
2173
2174 static void rtl8169_hw_reset(void __iomem *ioaddr)
2175 {
2176         /* Disable interrupts */
2177         rtl8169_irq_mask_and_ack(ioaddr);
2178
2179         /* Reset the chipset */
2180         RTL_W8(ChipCmd, CmdReset);
2181
2182         /* PCI commit */
2183         RTL_R8(ChipCmd);
2184 }
2185
2186 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
2187 {
2188         void __iomem *ioaddr = tp->mmio_addr;
2189         u32 cfg = rtl8169_rx_config;
2190
2191         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2192         RTL_W32(RxConfig, cfg);
2193
2194         /* Set DMA burst size and Interframe Gap Time */
2195         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2196                 (InterFrameGap << TxInterFrameGapShift));
2197 }
2198
2199 static void rtl_hw_start(struct net_device *dev)
2200 {
2201         struct rtl8169_private *tp = netdev_priv(dev);
2202         void __iomem *ioaddr = tp->mmio_addr;
2203         unsigned int i;
2204
2205         /* Soft reset the chip. */
2206         RTL_W8(ChipCmd, CmdReset);
2207
2208         /* Check that the chip has finished the reset. */
2209         for (i = 0; i < 100; i++) {
2210                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2211                         break;
2212                 msleep_interruptible(1);
2213         }
2214
2215         tp->hw_start(dev);
2216
2217         netif_start_queue(dev);
2218 }
2219
2220
2221 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2222                                          void __iomem *ioaddr)
2223 {
2224         /*
2225          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2226          * register to be written before TxDescAddrLow to work.
2227          * Switching from MMIO to I/O access fixes the issue as well.
2228          */
2229         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2230         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
2231         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2232         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
2233 }
2234
2235 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2236 {
2237         u16 cmd;
2238
2239         cmd = RTL_R16(CPlusCmd);
2240         RTL_W16(CPlusCmd, cmd);
2241         return cmd;
2242 }
2243
2244 static void rtl_set_rx_max_size(void __iomem *ioaddr)
2245 {
2246         /* Low hurts. Let's disable the filtering. */
2247         RTL_W16(RxMaxSize, 16383);
2248 }
2249
2250 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2251 {
2252         struct {
2253                 u32 mac_version;
2254                 u32 clk;
2255                 u32 val;
2256         } cfg2_info [] = {
2257                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2258                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2259                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2260                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2261         }, *p = cfg2_info;
2262         unsigned int i;
2263         u32 clk;
2264
2265         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2266         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2267                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2268                         RTL_W32(0x7c, p->val);
2269                         break;
2270                 }
2271         }
2272 }
2273
2274 static void rtl_hw_start_8169(struct net_device *dev)
2275 {
2276         struct rtl8169_private *tp = netdev_priv(dev);
2277         void __iomem *ioaddr = tp->mmio_addr;
2278         struct pci_dev *pdev = tp->pci_dev;
2279
2280         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2281                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2282                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2283         }
2284
2285         RTL_W8(Cfg9346, Cfg9346_Unlock);
2286         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2287             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2288             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2289             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2290                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2291
2292         RTL_W8(EarlyTxThres, EarlyTxThld);
2293
2294         rtl_set_rx_max_size(ioaddr);
2295
2296         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2297             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2298             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2299             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2300                 rtl_set_rx_tx_config_registers(tp);
2301
2302         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2303
2304         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2305             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2306                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2307                         "Bit-3 and bit-14 MUST be 1\n");
2308                 tp->cp_cmd |= (1 << 14);
2309         }
2310
2311         RTL_W16(CPlusCmd, tp->cp_cmd);
2312
2313         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2314
2315         /*
2316          * Undocumented corner. Supposedly:
2317          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2318          */
2319         RTL_W16(IntrMitigate, 0x0000);
2320
2321         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2322
2323         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2324             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2325             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2326             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2327                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2328                 rtl_set_rx_tx_config_registers(tp);
2329         }
2330
2331         RTL_W8(Cfg9346, Cfg9346_Lock);
2332
2333         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2334         RTL_R8(IntrMask);
2335
2336         RTL_W32(RxMissed, 0);
2337
2338         rtl_set_rx_mode(dev);
2339
2340         /* no early-rx interrupts */
2341         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2342
2343         /* Enable all known interrupts by setting the interrupt mask. */
2344         RTL_W16(IntrMask, tp->intr_event);
2345 }
2346
2347 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2348 {
2349         struct net_device *dev = pci_get_drvdata(pdev);
2350         struct rtl8169_private *tp = netdev_priv(dev);
2351         int cap = tp->pcie_cap;
2352
2353         if (cap) {
2354                 u16 ctl;
2355
2356                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2357                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2358                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2359         }
2360 }
2361
2362 static void rtl_csi_access_enable(void __iomem *ioaddr)
2363 {
2364         u32 csi;
2365
2366         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2367         rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2368 }
2369
2370 struct ephy_info {
2371         unsigned int offset;
2372         u16 mask;
2373         u16 bits;
2374 };
2375
2376 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2377 {
2378         u16 w;
2379
2380         while (len-- > 0) {
2381                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2382                 rtl_ephy_write(ioaddr, e->offset, w);
2383                 e++;
2384         }
2385 }
2386
2387 static void rtl_hw_start_8168(struct net_device *dev)
2388 {
2389         struct rtl8169_private *tp = netdev_priv(dev);
2390         void __iomem *ioaddr = tp->mmio_addr;
2391         struct pci_dev *pdev = tp->pci_dev;
2392
2393         RTL_W8(Cfg9346, Cfg9346_Unlock);
2394
2395         RTL_W8(EarlyTxThres, EarlyTxThld);
2396
2397         rtl_set_rx_max_size(ioaddr);
2398
2399         rtl_set_rx_tx_config_registers(tp);
2400
2401         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2402
2403         RTL_W16(CPlusCmd, tp->cp_cmd);
2404
2405         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2406
2407         RTL_W16(IntrMitigate, 0x5151);
2408
2409         /* Work around for RxFIFO overflow. */
2410         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2411                 tp->intr_event |= RxFIFOOver | PCSTimeout;
2412                 tp->intr_event &= ~RxOverflow;
2413         }
2414
2415         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2416
2417         RTL_W8(Cfg9346, Cfg9346_Lock);
2418
2419         RTL_R8(IntrMask);
2420
2421         rtl_set_rx_mode(dev);
2422
2423         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2424
2425         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2426
2427         RTL_W16(IntrMask, tp->intr_event);
2428 }
2429
2430 #define R810X_CPCMD_QUIRK_MASK (\
2431         EnableBist | \
2432         Mac_dbgo_oe | \
2433         Force_half_dup | \
2434         Force_half_dup | \
2435         Force_txflow_en | \
2436         Cxpl_dbg_sel | \
2437         ASF | \
2438         PktCntrDisable | \
2439         PCIDAC | \
2440         PCIMulRW)
2441
2442 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2443 {
2444         static struct ephy_info e_info_8102e_1[] = {
2445                 { 0x01, 0, 0x6e65 },
2446                 { 0x02, 0, 0x091f },
2447                 { 0x03, 0, 0xc2f9 },
2448                 { 0x06, 0, 0xafb5 },
2449                 { 0x07, 0, 0x0e00 },
2450                 { 0x19, 0, 0xec80 },
2451                 { 0x01, 0, 0x2e65 },
2452                 { 0x01, 0, 0x6e65 }
2453         };
2454         u8 cfg1;
2455
2456         rtl_csi_access_enable(ioaddr);
2457
2458         RTL_W8(DBG_REG, FIX_NAK_1);
2459
2460         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2461
2462         RTL_W8(Config1,
2463                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2464         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2465
2466         cfg1 = RTL_R8(Config1);
2467         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2468                 RTL_W8(Config1, cfg1 & ~LEDS0);
2469
2470         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2471
2472         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2473 }
2474
2475 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2476 {
2477         rtl_csi_access_enable(ioaddr);
2478
2479         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2480
2481         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2482         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2483
2484         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2485 }
2486
2487 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2488 {
2489         rtl_hw_start_8102e_2(ioaddr, pdev);
2490
2491         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2492 }
2493
2494 static void rtl_hw_start_8101(struct net_device *dev)
2495 {
2496         struct rtl8169_private *tp = netdev_priv(dev);
2497         void __iomem *ioaddr = tp->mmio_addr;
2498         struct pci_dev *pdev = tp->pci_dev;
2499
2500         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2501             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2502                 int cap = tp->pcie_cap;
2503
2504                 if (cap) {
2505                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2506                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
2507                 }
2508         }
2509
2510         switch (tp->mac_version) {
2511         case RTL_GIGA_MAC_VER_07:
2512                 rtl_hw_start_8102e_1(ioaddr, pdev);
2513                 break;
2514
2515         case RTL_GIGA_MAC_VER_08:
2516                 rtl_hw_start_8102e_3(ioaddr, pdev);
2517                 break;
2518
2519         case RTL_GIGA_MAC_VER_09:
2520                 rtl_hw_start_8102e_2(ioaddr, pdev);
2521                 break;
2522         }
2523
2524         RTL_W8(Cfg9346, Cfg9346_Unlock);
2525
2526         RTL_W8(EarlyTxThres, EarlyTxThld);
2527
2528         rtl_set_rx_max_size(ioaddr);
2529
2530         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2531
2532         RTL_W16(CPlusCmd, tp->cp_cmd);
2533
2534         RTL_W16(IntrMitigate, 0x0000);
2535
2536         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2537
2538         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2539         rtl_set_rx_tx_config_registers(tp);
2540
2541         RTL_W8(Cfg9346, Cfg9346_Lock);
2542
2543         RTL_R8(IntrMask);
2544
2545         rtl_set_rx_mode(dev);
2546
2547         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2548
2549         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2550
2551         RTL_W16(IntrMask, tp->intr_event);
2552 }
2553
2554 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2555 {
2556         struct rtl8169_private *tp = netdev_priv(dev);
2557         int ret = 0;
2558
2559         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2560                 return -EINVAL;
2561
2562         dev->mtu = new_mtu;
2563
2564         if (!netif_running(dev))
2565                 goto out;
2566
2567         rtl8169_down(dev);
2568
2569         rtl8169_set_rxbufsize(tp, dev);
2570
2571         ret = rtl8169_init_ring(dev);
2572         if (ret < 0)
2573                 goto out;
2574
2575         napi_enable(&tp->napi);
2576
2577         rtl_hw_start(dev);
2578
2579         rtl8169_request_timer(dev);
2580
2581 out:
2582         return ret;
2583 }
2584
2585 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2586 {
2587         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2588         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2589 }
2590
2591 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2592                                 struct sk_buff **sk_buff, struct RxDesc *desc)
2593 {
2594         struct pci_dev *pdev = tp->pci_dev;
2595
2596         pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2597                          PCI_DMA_FROMDEVICE);
2598         dev_kfree_skb(*sk_buff);
2599         *sk_buff = NULL;
2600         rtl8169_make_unusable_by_asic(desc);
2601 }
2602
2603 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2604 {
2605         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2606
2607         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2608 }
2609
2610 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2611                                        u32 rx_buf_sz)
2612 {
2613         desc->addr = cpu_to_le64(mapping);
2614         wmb();
2615         rtl8169_mark_to_asic(desc, rx_buf_sz);
2616 }
2617
2618 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2619                                             struct net_device *dev,
2620                                             struct RxDesc *desc, int rx_buf_sz,
2621                                             unsigned int align)
2622 {
2623         struct sk_buff *skb;
2624         dma_addr_t mapping;
2625         unsigned int pad;
2626
2627         pad = align ? align : NET_IP_ALIGN;
2628
2629         skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2630         if (!skb)
2631                 goto err_out;
2632
2633         skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2634
2635         mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2636                                  PCI_DMA_FROMDEVICE);
2637
2638         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2639 out:
2640         return skb;
2641
2642 err_out:
2643         rtl8169_make_unusable_by_asic(desc);
2644         goto out;
2645 }
2646
2647 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2648 {
2649         unsigned int i;
2650
2651         for (i = 0; i < NUM_RX_DESC; i++) {
2652                 if (tp->Rx_skbuff[i]) {
2653                         rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2654                                             tp->RxDescArray + i);
2655                 }
2656         }
2657 }
2658
2659 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2660                            u32 start, u32 end)
2661 {
2662         u32 cur;
2663
2664         for (cur = start; end - cur != 0; cur++) {
2665                 struct sk_buff *skb;
2666                 unsigned int i = cur % NUM_RX_DESC;
2667
2668                 WARN_ON((s32)(end - cur) < 0);
2669
2670                 if (tp->Rx_skbuff[i])
2671                         continue;
2672
2673                 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2674                                            tp->RxDescArray + i,
2675                                            tp->rx_buf_sz, tp->align);
2676                 if (!skb)
2677                         break;
2678
2679                 tp->Rx_skbuff[i] = skb;
2680         }
2681         return cur - start;
2682 }
2683
2684 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2685 {
2686         desc->opts1 |= cpu_to_le32(RingEnd);
2687 }
2688
2689 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2690 {
2691         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2692 }
2693
2694 static int rtl8169_init_ring(struct net_device *dev)
2695 {
2696         struct rtl8169_private *tp = netdev_priv(dev);
2697
2698         rtl8169_init_ring_indexes(tp);
2699
2700         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2701         memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2702
2703         if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2704                 goto err_out;
2705
2706         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2707
2708         return 0;
2709
2710 err_out:
2711         rtl8169_rx_clear(tp);
2712         return -ENOMEM;
2713 }
2714
2715 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2716                                  struct TxDesc *desc)
2717 {
2718         unsigned int len = tx_skb->len;
2719
2720         pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2721         desc->opts1 = 0x00;
2722         desc->opts2 = 0x00;
2723         desc->addr = 0x00;
2724         tx_skb->len = 0;
2725 }
2726
2727 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2728 {
2729         unsigned int i;
2730
2731         for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2732                 unsigned int entry = i % NUM_TX_DESC;
2733                 struct ring_info *tx_skb = tp->tx_skb + entry;
2734                 unsigned int len = tx_skb->len;
2735
2736                 if (len) {
2737                         struct sk_buff *skb = tx_skb->skb;
2738
2739                         rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2740                                              tp->TxDescArray + entry);
2741                         if (skb) {
2742                                 dev_kfree_skb(skb);
2743                                 tx_skb->skb = NULL;
2744                         }
2745                         tp->dev->stats.tx_dropped++;
2746                 }
2747         }
2748         tp->cur_tx = tp->dirty_tx = 0;
2749 }
2750
2751 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2752 {
2753         struct rtl8169_private *tp = netdev_priv(dev);
2754
2755         PREPARE_DELAYED_WORK(&tp->task, task);
2756         schedule_delayed_work(&tp->task, 4);
2757 }
2758
2759 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2760 {
2761         struct rtl8169_private *tp = netdev_priv(dev);
2762         void __iomem *ioaddr = tp->mmio_addr;
2763
2764         synchronize_irq(dev->irq);
2765
2766         /* Wait for any pending NAPI task to complete */
2767         napi_disable(&tp->napi);
2768
2769         rtl8169_irq_mask_and_ack(ioaddr);
2770
2771         tp->intr_mask = 0xffff;
2772         RTL_W16(IntrMask, tp->intr_event);
2773         napi_enable(&tp->napi);
2774 }
2775
2776 static void rtl8169_reinit_task(struct work_struct *work)
2777 {
2778         struct rtl8169_private *tp =
2779                 container_of(work, struct rtl8169_private, task.work);
2780         struct net_device *dev = tp->dev;
2781         int ret;
2782
2783         rtnl_lock();
2784
2785         if (!netif_running(dev))
2786                 goto out_unlock;
2787
2788         rtl8169_wait_for_quiescence(dev);
2789         rtl8169_close(dev);
2790
2791         ret = rtl8169_open(dev);
2792         if (unlikely(ret < 0)) {
2793                 if (net_ratelimit() && netif_msg_drv(tp)) {
2794                         printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
2795                                " Rescheduling.\n", dev->name, ret);
2796                 }
2797                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2798         }
2799
2800 out_unlock:
2801         rtnl_unlock();
2802 }
2803
2804 static void rtl8169_reset_task(struct work_struct *work)
2805 {
2806         struct rtl8169_private *tp =
2807                 container_of(work, struct rtl8169_private, task.work);
2808         struct net_device *dev = tp->dev;
2809
2810         rtnl_lock();
2811
2812         if (!netif_running(dev))
2813                 goto out_unlock;
2814
2815         rtl8169_wait_for_quiescence(dev);
2816
2817         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
2818         rtl8169_tx_clear(tp);
2819
2820         if (tp->dirty_rx == tp->cur_rx) {
2821                 rtl8169_init_ring_indexes(tp);
2822                 rtl_hw_start(dev);
2823                 netif_wake_queue(dev);
2824                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2825         } else {
2826                 if (net_ratelimit() && netif_msg_intr(tp)) {
2827                         printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
2828                                dev->name);
2829                 }
2830                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2831         }
2832
2833 out_unlock:
2834         rtnl_unlock();
2835 }
2836
2837 static void rtl8169_tx_timeout(struct net_device *dev)
2838 {
2839         struct rtl8169_private *tp = netdev_priv(dev);
2840
2841         rtl8169_hw_reset(tp->mmio_addr);
2842
2843         /* Let's wait a bit while any (async) irq lands on */
2844         rtl8169_schedule_work(dev, rtl8169_reset_task);
2845 }
2846
2847 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2848                               u32 opts1)
2849 {
2850         struct skb_shared_info *info = skb_shinfo(skb);
2851         unsigned int cur_frag, entry;
2852         struct TxDesc * uninitialized_var(txd);
2853
2854         entry = tp->cur_tx;
2855         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2856                 skb_frag_t *frag = info->frags + cur_frag;
2857                 dma_addr_t mapping;
2858                 u32 status, len;
2859                 void *addr;
2860
2861                 entry = (entry + 1) % NUM_TX_DESC;
2862
2863                 txd = tp->TxDescArray + entry;
2864                 len = frag->size;
2865                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2866                 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2867
2868                 /* anti gcc 2.95.3 bugware (sic) */
2869                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2870
2871                 txd->opts1 = cpu_to_le32(status);
2872                 txd->addr = cpu_to_le64(mapping);
2873
2874                 tp->tx_skb[entry].len = len;
2875         }
2876
2877         if (cur_frag) {
2878                 tp->tx_skb[entry].skb = skb;
2879                 txd->opts1 |= cpu_to_le32(LastFrag);
2880         }
2881
2882         return cur_frag;
2883 }
2884
2885 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2886 {
2887         if (dev->features & NETIF_F_TSO) {
2888                 u32 mss = skb_shinfo(skb)->gso_size;
2889
2890                 if (mss)
2891                         return LargeSend | ((mss & MSSMask) << MSSShift);
2892         }
2893         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2894                 const struct iphdr *ip = ip_hdr(skb);
2895
2896                 if (ip->protocol == IPPROTO_TCP)
2897                         return IPCS | TCPCS;
2898                 else if (ip->protocol == IPPROTO_UDP)
2899                         return IPCS | UDPCS;
2900                 WARN_ON(1);     /* we need a WARN() */
2901         }
2902         return 0;
2903 }
2904
2905 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2906 {
2907         struct rtl8169_private *tp = netdev_priv(dev);
2908         unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2909         struct TxDesc *txd = tp->TxDescArray + entry;
2910         void __iomem *ioaddr = tp->mmio_addr;
2911         dma_addr_t mapping;
2912         u32 status, len;
2913         u32 opts1;
2914         int ret = NETDEV_TX_OK;
2915
2916         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2917                 if (netif_msg_drv(tp)) {
2918                         printk(KERN_ERR
2919                                "%s: BUG! Tx Ring full when queue awake!\n",
2920                                dev->name);
2921                 }
2922                 goto err_stop;
2923         }
2924
2925         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2926                 goto err_stop;
2927
2928         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2929
2930         frags = rtl8169_xmit_frags(tp, skb, opts1);
2931         if (frags) {
2932                 len = skb_headlen(skb);
2933                 opts1 |= FirstFrag;
2934         } else {
2935                 len = skb->len;
2936
2937                 if (unlikely(len < ETH_ZLEN)) {
2938                         if (skb_padto(skb, ETH_ZLEN))
2939                                 goto err_update_stats;
2940                         len = ETH_ZLEN;
2941                 }
2942
2943                 opts1 |= FirstFrag | LastFrag;
2944                 tp->tx_skb[entry].skb = skb;
2945         }
2946
2947         mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2948
2949         tp->tx_skb[entry].len = len;
2950         txd->addr = cpu_to_le64(mapping);
2951         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2952
2953         wmb();
2954
2955         /* anti gcc 2.95.3 bugware (sic) */
2956         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2957         txd->opts1 = cpu_to_le32(status);
2958
2959         dev->trans_start = jiffies;
2960
2961         tp->cur_tx += frags + 1;
2962
2963         smp_wmb();
2964
2965         RTL_W8(TxPoll, NPQ);    /* set polling bit */
2966
2967         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2968                 netif_stop_queue(dev);
2969                 smp_rmb();
2970                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2971                         netif_wake_queue(dev);
2972         }
2973
2974 out:
2975         return ret;
2976
2977 err_stop:
2978         netif_stop_queue(dev);
2979         ret = NETDEV_TX_BUSY;
2980 err_update_stats:
2981         dev->stats.tx_dropped++;
2982         goto out;
2983 }
2984
2985 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2986 {
2987         struct rtl8169_private *tp = netdev_priv(dev);
2988         struct pci_dev *pdev = tp->pci_dev;
2989         void __iomem *ioaddr = tp->mmio_addr;
2990         u16 pci_status, pci_cmd;
2991
2992         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2993         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2994
2995         if (netif_msg_intr(tp)) {
2996                 printk(KERN_ERR
2997                        "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2998                        dev->name, pci_cmd, pci_status);
2999         }
3000
3001         /*
3002          * The recovery sequence below admits a very elaborated explanation:
3003          * - it seems to work;
3004          * - I did not see what else could be done;
3005          * - it makes iop3xx happy.
3006          *
3007          * Feel free to adjust to your needs.
3008          */
3009         if (pdev->broken_parity_status)
3010                 pci_cmd &= ~PCI_COMMAND_PARITY;
3011         else
3012                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3013
3014         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
3015
3016         pci_write_config_word(pdev, PCI_STATUS,
3017                 pci_status & (PCI_STATUS_DETECTED_PARITY |
3018                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3019                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3020
3021         /* The infamous DAC f*ckup only happens at boot time */
3022         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
3023                 if (netif_msg_intr(tp))
3024                         printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
3025                 tp->cp_cmd &= ~PCIDAC;
3026                 RTL_W16(CPlusCmd, tp->cp_cmd);
3027                 dev->features &= ~NETIF_F_HIGHDMA;
3028         }
3029
3030         rtl8169_hw_reset(ioaddr);
3031
3032         rtl8169_schedule_work(dev, rtl8169_reinit_task);
3033 }
3034
3035 static void rtl8169_tx_interrupt(struct net_device *dev,
3036                                  struct rtl8169_private *tp,
3037                                  void __iomem *ioaddr)
3038 {
3039         unsigned int dirty_tx, tx_left;
3040
3041         dirty_tx = tp->dirty_tx;
3042         smp_rmb();
3043         tx_left = tp->cur_tx - dirty_tx;
3044
3045         while (tx_left > 0) {
3046                 unsigned int entry = dirty_tx % NUM_TX_DESC;
3047                 struct ring_info *tx_skb = tp->tx_skb + entry;
3048                 u32 len = tx_skb->len;
3049                 u32 status;
3050
3051                 rmb();
3052                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3053                 if (status & DescOwn)
3054                         break;
3055
3056                 dev->stats.tx_bytes += len;
3057                 dev->stats.tx_packets++;
3058
3059                 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3060
3061                 if (status & LastFrag) {
3062                         dev_kfree_skb_irq(tx_skb->skb);
3063                         tx_skb->skb = NULL;
3064                 }
3065                 dirty_tx++;
3066                 tx_left--;
3067         }
3068
3069         if (tp->dirty_tx != dirty_tx) {
3070                 tp->dirty_tx = dirty_tx;
3071                 smp_wmb();
3072                 if (netif_queue_stopped(dev) &&
3073                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3074                         netif_wake_queue(dev);
3075                 }
3076                 /*
3077                  * 8168 hack: TxPoll requests are lost when the Tx packets are
3078                  * too close. Let's kick an extra TxPoll request when a burst
3079                  * of start_xmit activity is detected (if it is not detected,
3080                  * it is slow enough). -- FR
3081                  */
3082                 smp_rmb();
3083                 if (tp->cur_tx != dirty_tx)
3084                         RTL_W8(TxPoll, NPQ);
3085         }
3086 }
3087
3088 static inline int rtl8169_fragmented_frame(u32 status)
3089 {
3090         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3091 }
3092
3093 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3094 {
3095         u32 opts1 = le32_to_cpu(desc->opts1);
3096         u32 status = opts1 & RxProtoMask;
3097
3098         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3099             ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3100             ((status == RxProtoIP) && !(opts1 & IPFail)))
3101                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3102         else
3103                 skb->ip_summed = CHECKSUM_NONE;
3104 }
3105
3106 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3107                                        struct rtl8169_private *tp, int pkt_size,
3108                                        dma_addr_t addr)
3109 {
3110         struct sk_buff *skb;
3111         bool done = false;
3112
3113         if (pkt_size >= rx_copybreak)
3114                 goto out;
3115
3116         skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
3117         if (!skb)
3118                 goto out;
3119
3120         pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3121                                     PCI_DMA_FROMDEVICE);
3122         skb_reserve(skb, NET_IP_ALIGN);
3123         skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3124         *sk_buff = skb;
3125         done = true;
3126 out:
3127         return done;
3128 }
3129
3130 static int rtl8169_rx_interrupt(struct net_device *dev,
3131                                 struct rtl8169_private *tp,
3132                                 void __iomem *ioaddr, u32 budget)
3133 {
3134         unsigned int cur_rx, rx_left;
3135         unsigned int delta, count;
3136
3137         cur_rx = tp->cur_rx;
3138         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3139         rx_left = min(rx_left, budget);
3140
3141         for (; rx_left > 0; rx_left--, cur_rx++) {
3142                 unsigned int entry = cur_rx % NUM_RX_DESC;
3143                 struct RxDesc *desc = tp->RxDescArray + entry;
3144                 u32 status;
3145
3146                 rmb();
3147                 status = le32_to_cpu(desc->opts1);
3148
3149                 if (status & DescOwn)
3150                         break;
3151                 if (unlikely(status & RxRES)) {
3152                         if (netif_msg_rx_err(tp)) {
3153                                 printk(KERN_INFO
3154                                        "%s: Rx ERROR. status = %08x\n",
3155                                        dev->name, status);
3156                         }
3157                         dev->stats.rx_errors++;
3158                         if (status & (RxRWT | RxRUNT))
3159                                 dev->stats.rx_length_errors++;
3160                         if (status & RxCRC)
3161                                 dev->stats.rx_crc_errors++;
3162                         if (status & RxFOVF) {
3163                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
3164                                 dev->stats.rx_fifo_errors++;
3165                         }
3166                         rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3167                 } else {
3168                         struct sk_buff *skb = tp->Rx_skbuff[entry];
3169                         dma_addr_t addr = le64_to_cpu(desc->addr);
3170                         int pkt_size = (status & 0x00001FFF) - 4;
3171                         struct pci_dev *pdev = tp->pci_dev;
3172
3173                         /*
3174                          * The driver does not support incoming fragmented
3175                          * frames. They are seen as a symptom of over-mtu
3176                          * sized frames.
3177                          */
3178                         if (unlikely(rtl8169_fragmented_frame(status))) {
3179                                 dev->stats.rx_dropped++;
3180                                 dev->stats.rx_length_errors++;
3181                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3182                                 continue;
3183                         }
3184
3185                         rtl8169_rx_csum(skb, desc);
3186
3187                         if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
3188                                 pci_dma_sync_single_for_device(pdev, addr,
3189                                         pkt_size, PCI_DMA_FROMDEVICE);
3190                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3191                         } else {
3192                                 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
3193                                                  PCI_DMA_FROMDEVICE);
3194                                 tp->Rx_skbuff[entry] = NULL;
3195                         }
3196
3197                         skb_put(skb, pkt_size);
3198                         skb->protocol = eth_type_trans(skb, dev);
3199
3200                         if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
3201                                 netif_receive_skb(skb);
3202
3203                         dev->last_rx = jiffies;
3204                         dev->stats.rx_bytes += pkt_size;
3205                         dev->stats.rx_packets++;
3206                 }
3207
3208                 /* Work around for AMD plateform. */
3209                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
3210                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3211                         desc->opts2 = 0;
3212                         cur_rx++;
3213                 }
3214         }
3215
3216         count = cur_rx - tp->cur_rx;
3217         tp->cur_rx = cur_rx;
3218
3219         delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
3220         if (!delta && count && netif_msg_intr(tp))
3221                 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3222         tp->dirty_rx += delta;
3223
3224         /*
3225          * FIXME: until there is periodic timer to try and refill the ring,
3226          * a temporary shortage may definitely kill the Rx process.
3227          * - disable the asic to try and avoid an overflow and kick it again
3228          *   after refill ?
3229          * - how do others driver handle this condition (Uh oh...).
3230          */
3231         if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
3232                 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3233
3234         return count;
3235 }
3236
3237 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
3238 {
3239         struct net_device *dev = dev_instance;
3240         struct rtl8169_private *tp = netdev_priv(dev);
3241         void __iomem *ioaddr = tp->mmio_addr;
3242         int handled = 0;
3243         int status;
3244
3245         status = RTL_R16(IntrStatus);
3246
3247         /* hotplug/major error/no more work/shared irq */
3248         if ((status == 0xffff) || !status)
3249                 goto out;
3250
3251         handled = 1;
3252
3253         if (unlikely(!netif_running(dev))) {
3254                 rtl8169_asic_down(ioaddr);
3255                 goto out;
3256         }
3257
3258         status &= tp->intr_mask;
3259         RTL_W16(IntrStatus,
3260                 (status & RxFIFOOver) ? (status | RxOverflow) : status);
3261
3262         if (!(status & tp->intr_event))
3263                 goto out;
3264
3265         /* Work around for rx fifo overflow */
3266         if (unlikely(status & RxFIFOOver) &&
3267             (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3268                 netif_stop_queue(dev);
3269                 rtl8169_tx_timeout(dev);
3270                 goto out;
3271         }
3272
3273         if (unlikely(status & SYSErr)) {
3274                 rtl8169_pcierr_interrupt(dev);
3275                 goto out;
3276         }
3277
3278         if (status & LinkChg)
3279                 rtl8169_check_link_status(dev, tp, ioaddr);
3280
3281         if (status & tp->napi_event) {
3282                 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3283                 tp->intr_mask = ~tp->napi_event;
3284
3285                 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
3286                         __netif_rx_schedule(dev, &tp->napi);
3287                 else if (netif_msg_intr(tp)) {
3288                         printk(KERN_INFO "%s: interrupt %04x in poll\n",
3289                                dev->name, status);
3290                 }
3291         }
3292 out:
3293         return IRQ_RETVAL(handled);
3294 }
3295
3296 static int rtl8169_poll(struct napi_struct *napi, int budget)
3297 {
3298         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3299         struct net_device *dev = tp->dev;
3300         void __iomem *ioaddr = tp->mmio_addr;
3301         int work_done;
3302
3303         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
3304         rtl8169_tx_interrupt(dev, tp, ioaddr);
3305
3306         if (work_done < budget) {
3307                 netif_rx_complete(dev, napi);
3308                 tp->intr_mask = 0xffff;
3309                 /*
3310                  * 20040426: the barrier is not strictly required but the
3311                  * behavior of the irq handler could be less predictable
3312                  * without it. Btw, the lack of flush for the posted pci
3313                  * write is safe - FR
3314                  */
3315                 smp_wmb();
3316                 RTL_W16(IntrMask, tp->intr_event);
3317         }
3318
3319         return work_done;
3320 }
3321
3322 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3323 {
3324         struct rtl8169_private *tp = netdev_priv(dev);
3325
3326         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3327                 return;
3328
3329         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3330         RTL_W32(RxMissed, 0);
3331 }
3332
3333 static void rtl8169_down(struct net_device *dev)
3334 {
3335         struct rtl8169_private *tp = netdev_priv(dev);
3336         void __iomem *ioaddr = tp->mmio_addr;
3337         unsigned int intrmask;
3338
3339         rtl8169_delete_timer(dev);
3340
3341         netif_stop_queue(dev);
3342
3343         napi_disable(&tp->napi);
3344
3345 core_down:
3346         spin_lock_irq(&tp->lock);
3347
3348         rtl8169_asic_down(ioaddr);
3349
3350         rtl8169_rx_missed(dev, ioaddr);
3351
3352         spin_unlock_irq(&tp->lock);
3353
3354         synchronize_irq(dev->irq);
3355
3356         /* Give a racing hard_start_xmit a few cycles to complete. */
3357         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
3358
3359         /*
3360          * And now for the 50k$ question: are IRQ disabled or not ?
3361          *
3362          * Two paths lead here:
3363          * 1) dev->close
3364          *    -> netif_running() is available to sync the current code and the
3365          *       IRQ handler. See rtl8169_interrupt for details.
3366          * 2) dev->change_mtu
3367          *    -> rtl8169_poll can not be issued again and re-enable the
3368          *       interruptions. Let's simply issue the IRQ down sequence again.
3369          *
3370          * No loop if hotpluged or major error (0xffff).
3371          */
3372         intrmask = RTL_R16(IntrMask);
3373         if (intrmask && (intrmask != 0xffff))
3374                 goto core_down;
3375
3376         rtl8169_tx_clear(tp);
3377
3378         rtl8169_rx_clear(tp);
3379 }
3380
3381 static int rtl8169_close(struct net_device *dev)
3382 {
3383         struct rtl8169_private *tp = netdev_priv(dev);
3384         struct pci_dev *pdev = tp->pci_dev;
3385
3386         rtl8169_down(dev);
3387
3388         free_irq(dev->irq, dev);
3389
3390         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3391                             tp->RxPhyAddr);
3392         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3393                             tp->TxPhyAddr);
3394         tp->TxDescArray = NULL;
3395         tp->RxDescArray = NULL;
3396
3397         return 0;
3398 }
3399
3400 static void rtl_set_rx_mode(struct net_device *dev)
3401 {
3402         struct rtl8169_private *tp = netdev_priv(dev);
3403         void __iomem *ioaddr = tp->mmio_addr;
3404         unsigned long flags;
3405         u32 mc_filter[2];       /* Multicast hash filter */
3406         int rx_mode;
3407         u32 tmp = 0;
3408
3409         if (dev->flags & IFF_PROMISC) {
3410                 /* Unconditionally log net taps. */
3411                 if (netif_msg_link(tp)) {
3412                         printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3413                                dev->name);
3414                 }
3415                 rx_mode =
3416                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3417                     AcceptAllPhys;
3418                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3419         } else if ((dev->mc_count > multicast_filter_limit)
3420                    || (dev->flags & IFF_ALLMULTI)) {
3421                 /* Too many to filter perfectly -- accept all multicasts. */
3422                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3423                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3424         } else {
3425                 struct dev_mc_list *mclist;
3426                 unsigned int i;
3427
3428                 rx_mode = AcceptBroadcast | AcceptMyPhys;
3429                 mc_filter[1] = mc_filter[0] = 0;
3430                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3431                      i++, mclist = mclist->next) {
3432                         int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3433                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3434                         rx_mode |= AcceptMulticast;
3435                 }
3436         }
3437
3438         spin_lock_irqsave(&tp->lock, flags);
3439
3440         tmp = rtl8169_rx_config | rx_mode |
3441               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3442
3443         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3444                 u32 data = mc_filter[0];
3445
3446                 mc_filter[0] = swab32(mc_filter[1]);
3447                 mc_filter[1] = swab32(data);
3448         }
3449
3450         RTL_W32(MAR0 + 0, mc_filter[0]);
3451         RTL_W32(MAR0 + 4, mc_filter[1]);
3452
3453         RTL_W32(RxConfig, tmp);
3454
3455         spin_unlock_irqrestore(&tp->lock, flags);
3456 }
3457
3458 /**
3459  *  rtl8169_get_stats - Get rtl8169 read/write statistics
3460  *  @dev: The Ethernet Device to get statistics for
3461  *
3462  *  Get TX/RX statistics for rtl8169
3463  */
3464 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3465 {
3466         struct rtl8169_private *tp = netdev_priv(dev);
3467         void __iomem *ioaddr = tp->mmio_addr;
3468         unsigned long flags;
3469
3470         if (netif_running(dev)) {
3471                 spin_lock_irqsave(&tp->lock, flags);
3472                 rtl8169_rx_missed(dev, ioaddr);
3473                 spin_unlock_irqrestore(&tp->lock, flags);
3474         }
3475
3476         return &dev->stats;
3477 }
3478
3479 #ifdef CONFIG_PM
3480
3481 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3482 {
3483         struct net_device *dev = pci_get_drvdata(pdev);
3484         struct rtl8169_private *tp = netdev_priv(dev);
3485         void __iomem *ioaddr = tp->mmio_addr;
3486
3487         if (!netif_running(dev))
3488                 goto out_pci_suspend;
3489
3490         netif_device_detach(dev);
3491         netif_stop_queue(dev);
3492
3493         spin_lock_irq(&tp->lock);
3494
3495         rtl8169_asic_down(ioaddr);
3496
3497         rtl8169_rx_missed(dev, ioaddr);
3498
3499         spin_unlock_irq(&tp->lock);
3500
3501 out_pci_suspend:
3502         pci_save_state(pdev);
3503         pci_enable_wake(pdev, pci_choose_state(pdev, state),
3504                 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3505         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3506
3507         return 0;
3508 }
3509
3510 static int rtl8169_resume(struct pci_dev *pdev)
3511 {
3512         struct net_device *dev = pci_get_drvdata(pdev);
3513
3514         pci_set_power_state(pdev, PCI_D0);
3515         pci_restore_state(pdev);
3516         pci_enable_wake(pdev, PCI_D0, 0);
3517
3518         if (!netif_running(dev))
3519                 goto out;
3520
3521         netif_device_attach(dev);
3522
3523         rtl8169_schedule_work(dev, rtl8169_reset_task);
3524 out:
3525         return 0;
3526 }
3527
3528 #endif /* CONFIG_PM */
3529
3530 static struct pci_driver rtl8169_pci_driver = {
3531         .name           = MODULENAME,
3532         .id_table       = rtl8169_pci_tbl,
3533         .probe          = rtl8169_init_one,
3534         .remove         = __devexit_p(rtl8169_remove_one),
3535 #ifdef CONFIG_PM
3536         .suspend        = rtl8169_suspend,
3537         .resume         = rtl8169_resume,
3538 #endif
3539 };
3540
3541 static int __init rtl8169_init_module(void)
3542 {
3543         return pci_register_driver(&rtl8169_pci_driver);
3544 }
3545
3546 static void __exit rtl8169_cleanup_module(void)
3547 {
3548         pci_unregister_driver(&rtl8169_pci_driver);
3549 }
3550
3551 module_init(rtl8169_init_module);
3552 module_exit(rtl8169_cleanup_module);