r8169: fix merge conflict fix.
[linux-2.6.git] / drivers / net / r8169.c
1 /*
2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3  *
4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6  * Copyright (c) a lot of people too. Please respect their work.
7  *
8  * See MAINTAINERS file for support contact information.
9  */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29
30 #include <asm/system.h>
31 #include <asm/io.h>
32 #include <asm/irq.h>
33
34 #define RTL8169_VERSION "2.3LK-NAPI"
35 #define MODULENAME "r8169"
36 #define PFX MODULENAME ": "
37
38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
43
44 #ifdef RTL8169_DEBUG
45 #define assert(expr) \
46         if (!(expr)) {                                  \
47                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
48                 #expr,__FILE__,__func__,__LINE__);              \
49         }
50 #define dprintk(fmt, args...) \
51         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
52 #else
53 #define assert(expr) do {} while (0)
54 #define dprintk(fmt, args...)   do {} while (0)
55 #endif /* RTL8169_DEBUG */
56
57 #define R8169_MSG_DEFAULT \
58         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
59
60 #define TX_BUFFS_AVAIL(tp) \
61         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
62
63 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
64    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
65 static const int multicast_filter_limit = 32;
66
67 /* MAC address length */
68 #define MAC_ADDR_LEN    6
69
70 #define MAX_READ_REQUEST_SHIFT  12
71 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
72 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
73 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
74 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
75 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
76
77 #define R8169_REGS_SIZE         256
78 #define R8169_NAPI_WEIGHT       64
79 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
80 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
81 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
82 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
83 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
84
85 #define RTL8169_TX_TIMEOUT      (6*HZ)
86 #define RTL8169_PHY_TIMEOUT     (10*HZ)
87
88 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
89 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
90 #define RTL_EEPROM_SIG_ADDR     0x0000
91
92 /* write/read MMIO register */
93 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
94 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
95 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
96 #define RTL_R8(reg)             readb (ioaddr + (reg))
97 #define RTL_R16(reg)            readw (ioaddr + (reg))
98 #define RTL_R32(reg)            readl (ioaddr + (reg))
99
100 enum mac_version {
101         RTL_GIGA_MAC_NONE   = 0x00,
102         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
103         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
104         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
105         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
106         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
107         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
108         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
109         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
110         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
111         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
112         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
113         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
114         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
115         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
116         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
117         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
118         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
119         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
120         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
121         RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
122         RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
123         RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
124         RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
125         RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
126         RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
127         RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
128         RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
129         RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
130         RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E
131         RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E
132         RTL_GIGA_MAC_VER_31 = 0x1f, // 8168DP
133         RTL_GIGA_MAC_VER_32 = 0x20, // 8168E
134         RTL_GIGA_MAC_VER_33 = 0x21, // 8168E
135 };
136
137 enum rtl_tx_desc_version {
138         RTL_TD_0        = 0,
139         RTL_TD_1        = 1,
140 };
141
142 #define _R(NAME,MAC,TD) \
143         { .name = NAME, .mac_version = MAC, .txd_version = TD }
144
145 static const struct {
146         const char *name;
147         u8 mac_version;
148         enum rtl_tx_desc_version txd_version;
149 } rtl_chip_info[] = {
150         _R("RTL8169",           RTL_GIGA_MAC_VER_01, RTL_TD_0), // 8169
151         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, RTL_TD_0), // 8169S
152         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, RTL_TD_0), // 8110S
153         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, RTL_TD_0), // 8169SB
154         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, RTL_TD_0), // 8110SCd
155         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, RTL_TD_0), // 8110SCe
156         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, RTL_TD_1), // PCI-E
157         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, RTL_TD_1), // PCI-E
158         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, RTL_TD_1), // PCI-E
159         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, RTL_TD_0), // PCI-E
160         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, RTL_TD_0), // PCI-E
161         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, RTL_TD_0), // PCI-E
162         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, RTL_TD_0), // PCI-E 8139
163         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, RTL_TD_0), // PCI-E 8139
164         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, RTL_TD_0), // PCI-E 8139
165         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, RTL_TD_0), // PCI-E
166         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, RTL_TD_0), // PCI-E
167         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, RTL_TD_1), // PCI-E
168         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, RTL_TD_1), // PCI-E
169         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, RTL_TD_1), // PCI-E
170         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_21, RTL_TD_1), // PCI-E
171         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_22, RTL_TD_1), // PCI-E
172         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_23, RTL_TD_1), // PCI-E
173         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_24, RTL_TD_1), // PCI-E
174         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_25, RTL_TD_1), // PCI-E
175         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_26, RTL_TD_1), // PCI-E
176         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_27, RTL_TD_1), // PCI-E
177         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_28, RTL_TD_1), // PCI-E
178         _R("RTL8105e",          RTL_GIGA_MAC_VER_29, RTL_TD_1), // PCI-E
179         _R("RTL8105e",          RTL_GIGA_MAC_VER_30, RTL_TD_1), // PCI-E
180         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_31, RTL_TD_1), // PCI-E
181         _R("RTL8168e/8111e",    RTL_GIGA_MAC_VER_32, RTL_TD_1), // PCI-E
182         _R("RTL8168e/8111e",    RTL_GIGA_MAC_VER_33, RTL_TD_1)  // PCI-E
183 };
184 #undef _R
185
186 static const struct rtl_firmware_info {
187         int mac_version;
188         const char *fw_name;
189 } rtl_firmware_infos[] = {
190         { .mac_version = RTL_GIGA_MAC_VER_25, .fw_name = FIRMWARE_8168D_1 },
191         { .mac_version = RTL_GIGA_MAC_VER_26, .fw_name = FIRMWARE_8168D_2 },
192         { .mac_version = RTL_GIGA_MAC_VER_29, .fw_name = FIRMWARE_8105E_1 },
193         { .mac_version = RTL_GIGA_MAC_VER_30, .fw_name = FIRMWARE_8105E_1 },
194         { .mac_version = RTL_GIGA_MAC_VER_32, .fw_name = FIRMWARE_8168E_1 },
195         { .mac_version = RTL_GIGA_MAC_VER_33, .fw_name = FIRMWARE_8168E_2 }
196 };
197
198 enum cfg_version {
199         RTL_CFG_0 = 0x00,
200         RTL_CFG_1,
201         RTL_CFG_2
202 };
203
204 static void rtl_hw_start_8169(struct net_device *);
205 static void rtl_hw_start_8168(struct net_device *);
206 static void rtl_hw_start_8101(struct net_device *);
207
208 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
209         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
210         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
211         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
212         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
213         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
214         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
215         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
216         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
217         { PCI_VENDOR_ID_LINKSYS,                0x1032,
218                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
219         { 0x0001,                               0x8168,
220                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
221         {0,},
222 };
223
224 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
225
226 static int rx_buf_sz = 16383;
227 static int use_dac;
228 static struct {
229         u32 msg_enable;
230 } debug = { -1 };
231
232 enum rtl_registers {
233         MAC0            = 0,    /* Ethernet hardware address. */
234         MAC4            = 4,
235         MAR0            = 8,    /* Multicast filter. */
236         CounterAddrLow          = 0x10,
237         CounterAddrHigh         = 0x14,
238         TxDescStartAddrLow      = 0x20,
239         TxDescStartAddrHigh     = 0x24,
240         TxHDescStartAddrLow     = 0x28,
241         TxHDescStartAddrHigh    = 0x2c,
242         FLASH           = 0x30,
243         ERSR            = 0x36,
244         ChipCmd         = 0x37,
245         TxPoll          = 0x38,
246         IntrMask        = 0x3c,
247         IntrStatus      = 0x3e,
248         TxConfig        = 0x40,
249         RxConfig        = 0x44,
250
251 #define RTL_RX_CONFIG_MASK              0xff7e1880u
252
253         RxMissed        = 0x4c,
254         Cfg9346         = 0x50,
255         Config0         = 0x51,
256         Config1         = 0x52,
257         Config2         = 0x53,
258         Config3         = 0x54,
259         Config4         = 0x55,
260         Config5         = 0x56,
261         MultiIntr       = 0x5c,
262         PHYAR           = 0x60,
263         PHYstatus       = 0x6c,
264         RxMaxSize       = 0xda,
265         CPlusCmd        = 0xe0,
266         IntrMitigate    = 0xe2,
267         RxDescAddrLow   = 0xe4,
268         RxDescAddrHigh  = 0xe8,
269         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
270
271 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
272
273         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
274
275 #define TxPacketMax     (8064 >> 7)
276
277         FuncEvent       = 0xf0,
278         FuncEventMask   = 0xf4,
279         FuncPresetState = 0xf8,
280         FuncForceEvent  = 0xfc,
281 };
282
283 enum rtl8110_registers {
284         TBICSR                  = 0x64,
285         TBI_ANAR                = 0x68,
286         TBI_LPAR                = 0x6a,
287 };
288
289 enum rtl8168_8101_registers {
290         CSIDR                   = 0x64,
291         CSIAR                   = 0x68,
292 #define CSIAR_FLAG                      0x80000000
293 #define CSIAR_WRITE_CMD                 0x80000000
294 #define CSIAR_BYTE_ENABLE               0x0f
295 #define CSIAR_BYTE_ENABLE_SHIFT         12
296 #define CSIAR_ADDR_MASK                 0x0fff
297         PMCH                    = 0x6f,
298         EPHYAR                  = 0x80,
299 #define EPHYAR_FLAG                     0x80000000
300 #define EPHYAR_WRITE_CMD                0x80000000
301 #define EPHYAR_REG_MASK                 0x1f
302 #define EPHYAR_REG_SHIFT                16
303 #define EPHYAR_DATA_MASK                0xffff
304         DLLPR                   = 0xd0,
305 #define PM_SWITCH                       (1 << 6)
306         DBG_REG                 = 0xd1,
307 #define FIX_NAK_1                       (1 << 4)
308 #define FIX_NAK_2                       (1 << 3)
309         TWSI                    = 0xd2,
310         MCU                     = 0xd3,
311 #define EN_NDP                          (1 << 3)
312 #define EN_OOB_RESET                    (1 << 2)
313         EFUSEAR                 = 0xdc,
314 #define EFUSEAR_FLAG                    0x80000000
315 #define EFUSEAR_WRITE_CMD               0x80000000
316 #define EFUSEAR_READ_CMD                0x00000000
317 #define EFUSEAR_REG_MASK                0x03ff
318 #define EFUSEAR_REG_SHIFT               8
319 #define EFUSEAR_DATA_MASK               0xff
320 };
321
322 enum rtl8168_registers {
323         ERIDR                   = 0x70,
324         ERIAR                   = 0x74,
325 #define ERIAR_FLAG                      0x80000000
326 #define ERIAR_WRITE_CMD                 0x80000000
327 #define ERIAR_READ_CMD                  0x00000000
328 #define ERIAR_ADDR_BYTE_ALIGN           4
329 #define ERIAR_EXGMAC                    0
330 #define ERIAR_MSIX                      1
331 #define ERIAR_ASF                       2
332 #define ERIAR_TYPE_SHIFT                16
333 #define ERIAR_BYTEEN                    0x0f
334 #define ERIAR_BYTEEN_SHIFT              12
335         EPHY_RXER_NUM           = 0x7c,
336         OCPDR                   = 0xb0, /* OCP GPHY access */
337 #define OCPDR_WRITE_CMD                 0x80000000
338 #define OCPDR_READ_CMD                  0x00000000
339 #define OCPDR_REG_MASK                  0x7f
340 #define OCPDR_GPHY_REG_SHIFT            16
341 #define OCPDR_DATA_MASK                 0xffff
342         OCPAR                   = 0xb4,
343 #define OCPAR_FLAG                      0x80000000
344 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
345 #define OCPAR_GPHY_READ_CMD             0x0000f060
346         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
347         MISC                    = 0xf0, /* 8168e only. */
348         txpla_rst                       = (1 << 29)
349 };
350
351 enum rtl_register_content {
352         /* InterruptStatusBits */
353         SYSErr          = 0x8000,
354         PCSTimeout      = 0x4000,
355         SWInt           = 0x0100,
356         TxDescUnavail   = 0x0080,
357         RxFIFOOver      = 0x0040,
358         LinkChg         = 0x0020,
359         RxOverflow      = 0x0010,
360         TxErr           = 0x0008,
361         TxOK            = 0x0004,
362         RxErr           = 0x0002,
363         RxOK            = 0x0001,
364
365         /* RxStatusDesc */
366         RxFOVF  = (1 << 23),
367         RxRWT   = (1 << 22),
368         RxRES   = (1 << 21),
369         RxRUNT  = (1 << 20),
370         RxCRC   = (1 << 19),
371
372         /* ChipCmdBits */
373         CmdReset        = 0x10,
374         CmdRxEnb        = 0x08,
375         CmdTxEnb        = 0x04,
376         RxBufEmpty      = 0x01,
377
378         /* TXPoll register p.5 */
379         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
380         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
381         FSWInt          = 0x01,         /* Forced software interrupt */
382
383         /* Cfg9346Bits */
384         Cfg9346_Lock    = 0x00,
385         Cfg9346_Unlock  = 0xc0,
386
387         /* rx_mode_bits */
388         AcceptErr       = 0x20,
389         AcceptRunt      = 0x10,
390         AcceptBroadcast = 0x08,
391         AcceptMulticast = 0x04,
392         AcceptMyPhys    = 0x02,
393         AcceptAllPhys   = 0x01,
394
395         /* RxConfigBits */
396         RxCfgFIFOShift  = 13,
397         RxCfgDMAShift   =  8,
398
399         /* TxConfigBits */
400         TxInterFrameGapShift = 24,
401         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
402
403         /* Config1 register p.24 */
404         LEDS1           = (1 << 7),
405         LEDS0           = (1 << 6),
406         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
407         Speed_down      = (1 << 4),
408         MEMMAP          = (1 << 3),
409         IOMAP           = (1 << 2),
410         VPD             = (1 << 1),
411         PMEnable        = (1 << 0),     /* Power Management Enable */
412
413         /* Config2 register p. 25 */
414         PCI_Clock_66MHz = 0x01,
415         PCI_Clock_33MHz = 0x00,
416
417         /* Config3 register p.25 */
418         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
419         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
420         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
421
422         /* Config5 register p.27 */
423         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
424         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
425         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
426         spi_en          = (1 << 3),
427         LanWake         = (1 << 1),     /* LanWake enable/disable */
428         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
429
430         /* TBICSR p.28 */
431         TBIReset        = 0x80000000,
432         TBILoopback     = 0x40000000,
433         TBINwEnable     = 0x20000000,
434         TBINwRestart    = 0x10000000,
435         TBILinkOk       = 0x02000000,
436         TBINwComplete   = 0x01000000,
437
438         /* CPlusCmd p.31 */
439         EnableBist      = (1 << 15),    // 8168 8101
440         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
441         Normal_mode     = (1 << 13),    // unused
442         Force_half_dup  = (1 << 12),    // 8168 8101
443         Force_rxflow_en = (1 << 11),    // 8168 8101
444         Force_txflow_en = (1 << 10),    // 8168 8101
445         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
446         ASF             = (1 << 8),     // 8168 8101
447         PktCntrDisable  = (1 << 7),     // 8168 8101
448         Mac_dbgo_sel    = 0x001c,       // 8168
449         RxVlan          = (1 << 6),
450         RxChkSum        = (1 << 5),
451         PCIDAC          = (1 << 4),
452         PCIMulRW        = (1 << 3),
453         INTT_0          = 0x0000,       // 8168
454         INTT_1          = 0x0001,       // 8168
455         INTT_2          = 0x0002,       // 8168
456         INTT_3          = 0x0003,       // 8168
457
458         /* rtl8169_PHYstatus */
459         TBI_Enable      = 0x80,
460         TxFlowCtrl      = 0x40,
461         RxFlowCtrl      = 0x20,
462         _1000bpsF       = 0x10,
463         _100bps         = 0x08,
464         _10bps          = 0x04,
465         LinkStatus      = 0x02,
466         FullDup         = 0x01,
467
468         /* _TBICSRBit */
469         TBILinkOK       = 0x02000000,
470
471         /* DumpCounterCommand */
472         CounterDump     = 0x8,
473 };
474
475 enum rtl_desc_bit {
476         /* First doubleword. */
477         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
478         RingEnd         = (1 << 30), /* End of descriptor ring */
479         FirstFrag       = (1 << 29), /* First segment of a packet */
480         LastFrag        = (1 << 28), /* Final segment of a packet */
481 };
482
483 /* Generic case. */
484 enum rtl_tx_desc_bit {
485         /* First doubleword. */
486         TD_LSO          = (1 << 27),            /* Large Send Offload */
487 #define TD_MSS_MAX                      0x07ffu /* MSS value */
488
489         /* Second doubleword. */
490         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
491 };
492
493 /* 8169, 8168b and 810x except 8102e. */
494 enum rtl_tx_desc_bit_0 {
495         /* First doubleword. */
496 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
497         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
498         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
499         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
500 };
501
502 /* 8102e, 8168c and beyond. */
503 enum rtl_tx_desc_bit_1 {
504         /* Second doubleword. */
505 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
506         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
507         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
508         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
509 };
510
511 static const struct rtl_tx_desc_info {
512         struct {
513                 u32 udp;
514                 u32 tcp;
515         } checksum;
516         u16 mss_shift;
517         u16 opts_offset;
518 } tx_desc_info [] = {
519         [RTL_TD_0] = {
520                 .checksum = {
521                         .udp    = TD0_IP_CS | TD0_UDP_CS,
522                         .tcp    = TD0_IP_CS | TD0_TCP_CS
523                 },
524                 .mss_shift      = TD0_MSS_SHIFT,
525                 .opts_offset    = 0
526         },
527         [RTL_TD_1] = {
528                 .checksum = {
529                         .udp    = TD1_IP_CS | TD1_UDP_CS,
530                         .tcp    = TD1_IP_CS | TD1_TCP_CS
531                 },
532                 .mss_shift      = TD1_MSS_SHIFT,
533                 .opts_offset    = 1
534         }
535 };
536
537 enum rtl_rx_desc_bit {
538         /* Rx private */
539         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
540         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
541
542 #define RxProtoUDP      (PID1)
543 #define RxProtoTCP      (PID0)
544 #define RxProtoIP       (PID1 | PID0)
545 #define RxProtoMask     RxProtoIP
546
547         IPFail          = (1 << 16), /* IP checksum failed */
548         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
549         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
550         RxVlanTag       = (1 << 16), /* VLAN tag available */
551 };
552
553 #define RsvdMask        0x3fffc000
554
555 struct TxDesc {
556         __le32 opts1;
557         __le32 opts2;
558         __le64 addr;
559 };
560
561 struct RxDesc {
562         __le32 opts1;
563         __le32 opts2;
564         __le64 addr;
565 };
566
567 struct ring_info {
568         struct sk_buff  *skb;
569         u32             len;
570         u8              __pad[sizeof(void *) - sizeof(u32)];
571 };
572
573 enum features {
574         RTL_FEATURE_WOL         = (1 << 0),
575         RTL_FEATURE_MSI         = (1 << 1),
576         RTL_FEATURE_GMII        = (1 << 2),
577 };
578
579 struct rtl8169_counters {
580         __le64  tx_packets;
581         __le64  rx_packets;
582         __le64  tx_errors;
583         __le32  rx_errors;
584         __le16  rx_missed;
585         __le16  align_errors;
586         __le32  tx_one_collision;
587         __le32  tx_multi_collision;
588         __le64  rx_unicast;
589         __le64  rx_broadcast;
590         __le32  rx_multicast;
591         __le16  tx_aborted;
592         __le16  tx_underun;
593 };
594
595 struct rtl8169_private {
596         void __iomem *mmio_addr;        /* memory map physical address */
597         struct pci_dev *pci_dev;        /* Index of PCI device */
598         struct net_device *dev;
599         struct napi_struct napi;
600         spinlock_t lock;                /* spin lock flag */
601         u32 msg_enable;
602         u16 txd_version;
603         u16 mac_version;
604         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
605         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
606         u32 dirty_rx;
607         u32 dirty_tx;
608         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
609         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
610         dma_addr_t TxPhyAddr;
611         dma_addr_t RxPhyAddr;
612         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
613         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
614         struct timer_list timer;
615         u16 cp_cmd;
616         u16 intr_event;
617         u16 napi_event;
618         u16 intr_mask;
619         int phy_1000_ctrl_reg;
620
621         struct mdio_ops {
622                 void (*write)(void __iomem *, int, int);
623                 int (*read)(void __iomem *, int);
624         } mdio_ops;
625
626         struct pll_power_ops {
627                 void (*down)(struct rtl8169_private *);
628                 void (*up)(struct rtl8169_private *);
629         } pll_power_ops;
630
631         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
632         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
633         void (*phy_reset_enable)(struct rtl8169_private *tp);
634         void (*hw_start)(struct net_device *);
635         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
636         unsigned int (*link_ok)(void __iomem *);
637         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
638         int pcie_cap;
639         struct delayed_work task;
640         unsigned features;
641
642         struct mii_if_info mii;
643         struct rtl8169_counters counters;
644         u32 saved_wolopts;
645
646         const struct firmware *fw;
647 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN);
648 };
649
650 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
651 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
652 module_param(use_dac, int, 0);
653 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
654 module_param_named(debug, debug.msg_enable, int, 0);
655 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
656 MODULE_LICENSE("GPL");
657 MODULE_VERSION(RTL8169_VERSION);
658 MODULE_FIRMWARE(FIRMWARE_8168D_1);
659 MODULE_FIRMWARE(FIRMWARE_8168D_2);
660 MODULE_FIRMWARE(FIRMWARE_8168E_1);
661 MODULE_FIRMWARE(FIRMWARE_8168E_2);
662 MODULE_FIRMWARE(FIRMWARE_8105E_1);
663
664 static int rtl8169_open(struct net_device *dev);
665 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
666                                       struct net_device *dev);
667 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
668 static int rtl8169_init_ring(struct net_device *dev);
669 static void rtl_hw_start(struct net_device *dev);
670 static int rtl8169_close(struct net_device *dev);
671 static void rtl_set_rx_mode(struct net_device *dev);
672 static void rtl8169_tx_timeout(struct net_device *dev);
673 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
674 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
675                                 void __iomem *, u32 budget);
676 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
677 static void rtl8169_down(struct net_device *dev);
678 static void rtl8169_rx_clear(struct rtl8169_private *tp);
679 static int rtl8169_poll(struct napi_struct *napi, int budget);
680
681 static const unsigned int rtl8169_rx_config =
682         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
683
684 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
685 {
686         void __iomem *ioaddr = tp->mmio_addr;
687         int i;
688
689         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
690         for (i = 0; i < 20; i++) {
691                 udelay(100);
692                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
693                         break;
694         }
695         return RTL_R32(OCPDR);
696 }
697
698 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
699 {
700         void __iomem *ioaddr = tp->mmio_addr;
701         int i;
702
703         RTL_W32(OCPDR, data);
704         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
705         for (i = 0; i < 20; i++) {
706                 udelay(100);
707                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
708                         break;
709         }
710 }
711
712 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
713 {
714         void __iomem *ioaddr = tp->mmio_addr;
715         int i;
716
717         RTL_W8(ERIDR, cmd);
718         RTL_W32(ERIAR, 0x800010e8);
719         msleep(2);
720         for (i = 0; i < 5; i++) {
721                 udelay(100);
722                 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
723                         break;
724         }
725
726         ocp_write(tp, 0x1, 0x30, 0x00000001);
727 }
728
729 #define OOB_CMD_RESET           0x00
730 #define OOB_CMD_DRIVER_START    0x05
731 #define OOB_CMD_DRIVER_STOP     0x06
732
733 static void rtl8168_driver_start(struct rtl8169_private *tp)
734 {
735         int i;
736         u32 reg;
737
738         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
739
740         if (tp->mac_version == RTL_GIGA_MAC_VER_31)
741                 reg = 0xb8;
742         else
743                 reg = 0x10;
744
745         for (i = 0; i < 10; i++) {
746                 msleep(10);
747                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
748                         break;
749         }
750 }
751
752 static void rtl8168_driver_stop(struct rtl8169_private *tp)
753 {
754         int i;
755         u32 reg;
756
757         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
758
759         if (tp->mac_version == RTL_GIGA_MAC_VER_31)
760                 reg = 0xb8;
761         else
762                 reg = 0x10;
763
764         for (i = 0; i < 10; i++) {
765                 msleep(10);
766                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
767                         break;
768         }
769 }
770
771 static int r8168dp_check_dash(struct rtl8169_private *tp)
772 {
773         u32 reg;
774
775         if (tp->mac_version == RTL_GIGA_MAC_VER_31)
776                 reg = 0xb8;
777         else
778                 reg = 0x10;
779
780         if (ocp_read(tp, 0xF, reg) & 0x00008000)
781                 return 1;
782         else
783                 return 0;
784 }
785
786 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
787 {
788         int i;
789
790         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
791
792         for (i = 20; i > 0; i--) {
793                 /*
794                  * Check if the RTL8169 has completed writing to the specified
795                  * MII register.
796                  */
797                 if (!(RTL_R32(PHYAR) & 0x80000000))
798                         break;
799                 udelay(25);
800         }
801         /*
802          * According to hardware specs a 20us delay is required after write
803          * complete indication, but before sending next command.
804          */
805         udelay(20);
806 }
807
808 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
809 {
810         int i, value = -1;
811
812         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
813
814         for (i = 20; i > 0; i--) {
815                 /*
816                  * Check if the RTL8169 has completed retrieving data from
817                  * the specified MII register.
818                  */
819                 if (RTL_R32(PHYAR) & 0x80000000) {
820                         value = RTL_R32(PHYAR) & 0xffff;
821                         break;
822                 }
823                 udelay(25);
824         }
825         /*
826          * According to hardware specs a 20us delay is required after read
827          * complete indication, but before sending next command.
828          */
829         udelay(20);
830
831         return value;
832 }
833
834 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
835 {
836         int i;
837
838         RTL_W32(OCPDR, data |
839                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
840         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
841         RTL_W32(EPHY_RXER_NUM, 0);
842
843         for (i = 0; i < 100; i++) {
844                 mdelay(1);
845                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
846                         break;
847         }
848 }
849
850 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
851 {
852         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
853                 (value & OCPDR_DATA_MASK));
854 }
855
856 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
857 {
858         int i;
859
860         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
861
862         mdelay(1);
863         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
864         RTL_W32(EPHY_RXER_NUM, 0);
865
866         for (i = 0; i < 100; i++) {
867                 mdelay(1);
868                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
869                         break;
870         }
871
872         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
873 }
874
875 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
876
877 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
878 {
879         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
880 }
881
882 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
883 {
884         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
885 }
886
887 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
888 {
889         r8168dp_2_mdio_start(ioaddr);
890
891         r8169_mdio_write(ioaddr, reg_addr, value);
892
893         r8168dp_2_mdio_stop(ioaddr);
894 }
895
896 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
897 {
898         int value;
899
900         r8168dp_2_mdio_start(ioaddr);
901
902         value = r8169_mdio_read(ioaddr, reg_addr);
903
904         r8168dp_2_mdio_stop(ioaddr);
905
906         return value;
907 }
908
909 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
910 {
911         tp->mdio_ops.write(tp->mmio_addr, location, val);
912 }
913
914 static int rtl_readphy(struct rtl8169_private *tp, int location)
915 {
916         return tp->mdio_ops.read(tp->mmio_addr, location);
917 }
918
919 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
920 {
921         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
922 }
923
924 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
925 {
926         int val;
927
928         val = rtl_readphy(tp, reg_addr);
929         rtl_writephy(tp, reg_addr, (val | p) & ~m);
930 }
931
932 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
933                            int val)
934 {
935         struct rtl8169_private *tp = netdev_priv(dev);
936
937         rtl_writephy(tp, location, val);
938 }
939
940 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
941 {
942         struct rtl8169_private *tp = netdev_priv(dev);
943
944         return rtl_readphy(tp, location);
945 }
946
947 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
948 {
949         unsigned int i;
950
951         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
952                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
953
954         for (i = 0; i < 100; i++) {
955                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
956                         break;
957                 udelay(10);
958         }
959 }
960
961 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
962 {
963         u16 value = 0xffff;
964         unsigned int i;
965
966         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
967
968         for (i = 0; i < 100; i++) {
969                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
970                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
971                         break;
972                 }
973                 udelay(10);
974         }
975
976         return value;
977 }
978
979 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
980 {
981         unsigned int i;
982
983         RTL_W32(CSIDR, value);
984         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
985                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
986
987         for (i = 0; i < 100; i++) {
988                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
989                         break;
990                 udelay(10);
991         }
992 }
993
994 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
995 {
996         u32 value = ~0x00;
997         unsigned int i;
998
999         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1000                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1001
1002         for (i = 0; i < 100; i++) {
1003                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1004                         value = RTL_R32(CSIDR);
1005                         break;
1006                 }
1007                 udelay(10);
1008         }
1009
1010         return value;
1011 }
1012
1013 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1014 {
1015         u8 value = 0xff;
1016         unsigned int i;
1017
1018         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1019
1020         for (i = 0; i < 300; i++) {
1021                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1022                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1023                         break;
1024                 }
1025                 udelay(100);
1026         }
1027
1028         return value;
1029 }
1030
1031 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1032 {
1033         RTL_W16(IntrMask, 0x0000);
1034
1035         RTL_W16(IntrStatus, 0xffff);
1036 }
1037
1038 static void rtl8169_asic_down(void __iomem *ioaddr)
1039 {
1040         RTL_W8(ChipCmd, 0x00);
1041         rtl8169_irq_mask_and_ack(ioaddr);
1042         RTL_R16(CPlusCmd);
1043 }
1044
1045 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1046 {
1047         void __iomem *ioaddr = tp->mmio_addr;
1048
1049         return RTL_R32(TBICSR) & TBIReset;
1050 }
1051
1052 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1053 {
1054         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1055 }
1056
1057 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1058 {
1059         return RTL_R32(TBICSR) & TBILinkOk;
1060 }
1061
1062 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1063 {
1064         return RTL_R8(PHYstatus) & LinkStatus;
1065 }
1066
1067 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1068 {
1069         void __iomem *ioaddr = tp->mmio_addr;
1070
1071         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1072 }
1073
1074 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1075 {
1076         unsigned int val;
1077
1078         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1079         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1080 }
1081
1082 static void __rtl8169_check_link_status(struct net_device *dev,
1083                                       struct rtl8169_private *tp,
1084                                       void __iomem *ioaddr,
1085                                       bool pm)
1086 {
1087         unsigned long flags;
1088
1089         spin_lock_irqsave(&tp->lock, flags);
1090         if (tp->link_ok(ioaddr)) {
1091                 /* This is to cancel a scheduled suspend if there's one. */
1092                 if (pm)
1093                         pm_request_resume(&tp->pci_dev->dev);
1094                 netif_carrier_on(dev);
1095                 if (net_ratelimit())
1096                         netif_info(tp, ifup, dev, "link up\n");
1097         } else {
1098                 netif_carrier_off(dev);
1099                 netif_info(tp, ifdown, dev, "link down\n");
1100                 if (pm)
1101                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
1102         }
1103         spin_unlock_irqrestore(&tp->lock, flags);
1104 }
1105
1106 static void rtl8169_check_link_status(struct net_device *dev,
1107                                       struct rtl8169_private *tp,
1108                                       void __iomem *ioaddr)
1109 {
1110         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1111 }
1112
1113 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1114
1115 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1116 {
1117         void __iomem *ioaddr = tp->mmio_addr;
1118         u8 options;
1119         u32 wolopts = 0;
1120
1121         options = RTL_R8(Config1);
1122         if (!(options & PMEnable))
1123                 return 0;
1124
1125         options = RTL_R8(Config3);
1126         if (options & LinkUp)
1127                 wolopts |= WAKE_PHY;
1128         if (options & MagicPacket)
1129                 wolopts |= WAKE_MAGIC;
1130
1131         options = RTL_R8(Config5);
1132         if (options & UWF)
1133                 wolopts |= WAKE_UCAST;
1134         if (options & BWF)
1135                 wolopts |= WAKE_BCAST;
1136         if (options & MWF)
1137                 wolopts |= WAKE_MCAST;
1138
1139         return wolopts;
1140 }
1141
1142 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1143 {
1144         struct rtl8169_private *tp = netdev_priv(dev);
1145
1146         spin_lock_irq(&tp->lock);
1147
1148         wol->supported = WAKE_ANY;
1149         wol->wolopts = __rtl8169_get_wol(tp);
1150
1151         spin_unlock_irq(&tp->lock);
1152 }
1153
1154 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1155 {
1156         void __iomem *ioaddr = tp->mmio_addr;
1157         unsigned int i;
1158         static const struct {
1159                 u32 opt;
1160                 u16 reg;
1161                 u8  mask;
1162         } cfg[] = {
1163                 { WAKE_ANY,   Config1, PMEnable },
1164                 { WAKE_PHY,   Config3, LinkUp },
1165                 { WAKE_MAGIC, Config3, MagicPacket },
1166                 { WAKE_UCAST, Config5, UWF },
1167                 { WAKE_BCAST, Config5, BWF },
1168                 { WAKE_MCAST, Config5, MWF },
1169                 { WAKE_ANY,   Config5, LanWake }
1170         };
1171
1172         RTL_W8(Cfg9346, Cfg9346_Unlock);
1173
1174         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1175                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1176                 if (wolopts & cfg[i].opt)
1177                         options |= cfg[i].mask;
1178                 RTL_W8(cfg[i].reg, options);
1179         }
1180
1181         RTL_W8(Cfg9346, Cfg9346_Lock);
1182 }
1183
1184 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1185 {
1186         struct rtl8169_private *tp = netdev_priv(dev);
1187
1188         spin_lock_irq(&tp->lock);
1189
1190         if (wol->wolopts)
1191                 tp->features |= RTL_FEATURE_WOL;
1192         else
1193                 tp->features &= ~RTL_FEATURE_WOL;
1194         __rtl8169_set_wol(tp, wol->wolopts);
1195         spin_unlock_irq(&tp->lock);
1196
1197         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1198
1199         return 0;
1200 }
1201
1202 static void rtl8169_get_drvinfo(struct net_device *dev,
1203                                 struct ethtool_drvinfo *info)
1204 {
1205         struct rtl8169_private *tp = netdev_priv(dev);
1206
1207         strcpy(info->driver, MODULENAME);
1208         strcpy(info->version, RTL8169_VERSION);
1209         strcpy(info->bus_info, pci_name(tp->pci_dev));
1210 }
1211
1212 static int rtl8169_get_regs_len(struct net_device *dev)
1213 {
1214         return R8169_REGS_SIZE;
1215 }
1216
1217 static int rtl8169_set_speed_tbi(struct net_device *dev,
1218                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1219 {
1220         struct rtl8169_private *tp = netdev_priv(dev);
1221         void __iomem *ioaddr = tp->mmio_addr;
1222         int ret = 0;
1223         u32 reg;
1224
1225         reg = RTL_R32(TBICSR);
1226         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1227             (duplex == DUPLEX_FULL)) {
1228                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1229         } else if (autoneg == AUTONEG_ENABLE)
1230                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1231         else {
1232                 netif_warn(tp, link, dev,
1233                            "incorrect speed setting refused in TBI mode\n");
1234                 ret = -EOPNOTSUPP;
1235         }
1236
1237         return ret;
1238 }
1239
1240 static int rtl8169_set_speed_xmii(struct net_device *dev,
1241                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1242 {
1243         struct rtl8169_private *tp = netdev_priv(dev);
1244         int giga_ctrl, bmcr;
1245         int rc = -EINVAL;
1246
1247         rtl_writephy(tp, 0x1f, 0x0000);
1248
1249         if (autoneg == AUTONEG_ENABLE) {
1250                 int auto_nego;
1251
1252                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1253                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1254                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1255
1256                 if (adv & ADVERTISED_10baseT_Half)
1257                         auto_nego |= ADVERTISE_10HALF;
1258                 if (adv & ADVERTISED_10baseT_Full)
1259                         auto_nego |= ADVERTISE_10FULL;
1260                 if (adv & ADVERTISED_100baseT_Half)
1261                         auto_nego |= ADVERTISE_100HALF;
1262                 if (adv & ADVERTISED_100baseT_Full)
1263                         auto_nego |= ADVERTISE_100FULL;
1264
1265                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1266
1267                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1268                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1269
1270                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1271                 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1272                     (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1273                     (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1274                     (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1275                     (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1276                     (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1277                     (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1278                     (tp->mac_version != RTL_GIGA_MAC_VER_16) &&
1279                     (tp->mac_version != RTL_GIGA_MAC_VER_29) &&
1280                     (tp->mac_version != RTL_GIGA_MAC_VER_30)) {
1281                         if (adv & ADVERTISED_1000baseT_Half)
1282                                 giga_ctrl |= ADVERTISE_1000HALF;
1283                         if (adv & ADVERTISED_1000baseT_Full)
1284                                 giga_ctrl |= ADVERTISE_1000FULL;
1285                 } else if (adv & (ADVERTISED_1000baseT_Half |
1286                                   ADVERTISED_1000baseT_Full)) {
1287                         netif_info(tp, link, dev,
1288                                    "PHY does not support 1000Mbps\n");
1289                         goto out;
1290                 }
1291
1292                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1293
1294                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1295                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1296         } else {
1297                 giga_ctrl = 0;
1298
1299                 if (speed == SPEED_10)
1300                         bmcr = 0;
1301                 else if (speed == SPEED_100)
1302                         bmcr = BMCR_SPEED100;
1303                 else
1304                         goto out;
1305
1306                 if (duplex == DUPLEX_FULL)
1307                         bmcr |= BMCR_FULLDPLX;
1308         }
1309
1310         tp->phy_1000_ctrl_reg = giga_ctrl;
1311
1312         rtl_writephy(tp, MII_BMCR, bmcr);
1313
1314         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1315             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1316                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1317                         rtl_writephy(tp, 0x17, 0x2138);
1318                         rtl_writephy(tp, 0x0e, 0x0260);
1319                 } else {
1320                         rtl_writephy(tp, 0x17, 0x2108);
1321                         rtl_writephy(tp, 0x0e, 0x0000);
1322                 }
1323         }
1324
1325         rc = 0;
1326 out:
1327         return rc;
1328 }
1329
1330 static int rtl8169_set_speed(struct net_device *dev,
1331                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1332 {
1333         struct rtl8169_private *tp = netdev_priv(dev);
1334         int ret;
1335
1336         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1337
1338         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1339                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1340
1341         return ret;
1342 }
1343
1344 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1345 {
1346         struct rtl8169_private *tp = netdev_priv(dev);
1347         unsigned long flags;
1348         int ret;
1349
1350         spin_lock_irqsave(&tp->lock, flags);
1351         ret = rtl8169_set_speed(dev,
1352                 cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising);
1353         spin_unlock_irqrestore(&tp->lock, flags);
1354
1355         return ret;
1356 }
1357
1358 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1359 {
1360         if (dev->mtu > TD_MSS_MAX)
1361                 features &= ~NETIF_F_ALL_TSO;
1362
1363         return features;
1364 }
1365
1366 static int rtl8169_set_features(struct net_device *dev, u32 features)
1367 {
1368         struct rtl8169_private *tp = netdev_priv(dev);
1369         void __iomem *ioaddr = tp->mmio_addr;
1370         unsigned long flags;
1371
1372         spin_lock_irqsave(&tp->lock, flags);
1373
1374         if (features & NETIF_F_RXCSUM)
1375                 tp->cp_cmd |= RxChkSum;
1376         else
1377                 tp->cp_cmd &= ~RxChkSum;
1378
1379         if (dev->features & NETIF_F_HW_VLAN_RX)
1380                 tp->cp_cmd |= RxVlan;
1381         else
1382                 tp->cp_cmd &= ~RxVlan;
1383
1384         RTL_W16(CPlusCmd, tp->cp_cmd);
1385         RTL_R16(CPlusCmd);
1386
1387         spin_unlock_irqrestore(&tp->lock, flags);
1388
1389         return 0;
1390 }
1391
1392 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1393                                       struct sk_buff *skb)
1394 {
1395         return (vlan_tx_tag_present(skb)) ?
1396                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1397 }
1398
1399 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1400 {
1401         u32 opts2 = le32_to_cpu(desc->opts2);
1402
1403         if (opts2 & RxVlanTag)
1404                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1405
1406         desc->opts2 = 0;
1407 }
1408
1409 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1410 {
1411         struct rtl8169_private *tp = netdev_priv(dev);
1412         void __iomem *ioaddr = tp->mmio_addr;
1413         u32 status;
1414
1415         cmd->supported =
1416                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1417         cmd->port = PORT_FIBRE;
1418         cmd->transceiver = XCVR_INTERNAL;
1419
1420         status = RTL_R32(TBICSR);
1421         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1422         cmd->autoneg = !!(status & TBINwEnable);
1423
1424         cmd->speed = SPEED_1000;
1425         cmd->duplex = DUPLEX_FULL; /* Always set */
1426
1427         return 0;
1428 }
1429
1430 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1431 {
1432         struct rtl8169_private *tp = netdev_priv(dev);
1433
1434         return mii_ethtool_gset(&tp->mii, cmd);
1435 }
1436
1437 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1438 {
1439         struct rtl8169_private *tp = netdev_priv(dev);
1440         unsigned long flags;
1441         int rc;
1442
1443         spin_lock_irqsave(&tp->lock, flags);
1444
1445         rc = tp->get_settings(dev, cmd);
1446
1447         spin_unlock_irqrestore(&tp->lock, flags);
1448         return rc;
1449 }
1450
1451 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1452                              void *p)
1453 {
1454         struct rtl8169_private *tp = netdev_priv(dev);
1455         unsigned long flags;
1456
1457         if (regs->len > R8169_REGS_SIZE)
1458                 regs->len = R8169_REGS_SIZE;
1459
1460         spin_lock_irqsave(&tp->lock, flags);
1461         memcpy_fromio(p, tp->mmio_addr, regs->len);
1462         spin_unlock_irqrestore(&tp->lock, flags);
1463 }
1464
1465 static u32 rtl8169_get_msglevel(struct net_device *dev)
1466 {
1467         struct rtl8169_private *tp = netdev_priv(dev);
1468
1469         return tp->msg_enable;
1470 }
1471
1472 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1473 {
1474         struct rtl8169_private *tp = netdev_priv(dev);
1475
1476         tp->msg_enable = value;
1477 }
1478
1479 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1480         "tx_packets",
1481         "rx_packets",
1482         "tx_errors",
1483         "rx_errors",
1484         "rx_missed",
1485         "align_errors",
1486         "tx_single_collisions",
1487         "tx_multi_collisions",
1488         "unicast",
1489         "broadcast",
1490         "multicast",
1491         "tx_aborted",
1492         "tx_underrun",
1493 };
1494
1495 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1496 {
1497         switch (sset) {
1498         case ETH_SS_STATS:
1499                 return ARRAY_SIZE(rtl8169_gstrings);
1500         default:
1501                 return -EOPNOTSUPP;
1502         }
1503 }
1504
1505 static void rtl8169_update_counters(struct net_device *dev)
1506 {
1507         struct rtl8169_private *tp = netdev_priv(dev);
1508         void __iomem *ioaddr = tp->mmio_addr;
1509         struct rtl8169_counters *counters;
1510         dma_addr_t paddr;
1511         u32 cmd;
1512         int wait = 1000;
1513         struct device *d = &tp->pci_dev->dev;
1514
1515         /*
1516          * Some chips are unable to dump tally counters when the receiver
1517          * is disabled.
1518          */
1519         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1520                 return;
1521
1522         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1523         if (!counters)
1524                 return;
1525
1526         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1527         cmd = (u64)paddr & DMA_BIT_MASK(32);
1528         RTL_W32(CounterAddrLow, cmd);
1529         RTL_W32(CounterAddrLow, cmd | CounterDump);
1530
1531         while (wait--) {
1532                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1533                         /* copy updated counters */
1534                         memcpy(&tp->counters, counters, sizeof(*counters));
1535                         break;
1536                 }
1537                 udelay(10);
1538         }
1539
1540         RTL_W32(CounterAddrLow, 0);
1541         RTL_W32(CounterAddrHigh, 0);
1542
1543         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1544 }
1545
1546 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1547                                       struct ethtool_stats *stats, u64 *data)
1548 {
1549         struct rtl8169_private *tp = netdev_priv(dev);
1550
1551         ASSERT_RTNL();
1552
1553         rtl8169_update_counters(dev);
1554
1555         data[0] = le64_to_cpu(tp->counters.tx_packets);
1556         data[1] = le64_to_cpu(tp->counters.rx_packets);
1557         data[2] = le64_to_cpu(tp->counters.tx_errors);
1558         data[3] = le32_to_cpu(tp->counters.rx_errors);
1559         data[4] = le16_to_cpu(tp->counters.rx_missed);
1560         data[5] = le16_to_cpu(tp->counters.align_errors);
1561         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1562         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1563         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1564         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1565         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1566         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1567         data[12] = le16_to_cpu(tp->counters.tx_underun);
1568 }
1569
1570 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1571 {
1572         switch(stringset) {
1573         case ETH_SS_STATS:
1574                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1575                 break;
1576         }
1577 }
1578
1579 static const struct ethtool_ops rtl8169_ethtool_ops = {
1580         .get_drvinfo            = rtl8169_get_drvinfo,
1581         .get_regs_len           = rtl8169_get_regs_len,
1582         .get_link               = ethtool_op_get_link,
1583         .get_settings           = rtl8169_get_settings,
1584         .set_settings           = rtl8169_set_settings,
1585         .get_msglevel           = rtl8169_get_msglevel,
1586         .set_msglevel           = rtl8169_set_msglevel,
1587         .get_regs               = rtl8169_get_regs,
1588         .get_wol                = rtl8169_get_wol,
1589         .set_wol                = rtl8169_set_wol,
1590         .get_strings            = rtl8169_get_strings,
1591         .get_sset_count         = rtl8169_get_sset_count,
1592         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1593 };
1594
1595 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1596                                     void __iomem *ioaddr)
1597 {
1598         /*
1599          * The driver currently handles the 8168Bf and the 8168Be identically
1600          * but they can be identified more specifically through the test below
1601          * if needed:
1602          *
1603          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1604          *
1605          * Same thing for the 8101Eb and the 8101Ec:
1606          *
1607          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1608          */
1609         static const struct {
1610                 u32 mask;
1611                 u32 val;
1612                 int mac_version;
1613         } mac_info[] = {
1614                 /* 8168E family. */
1615                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1616                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1617                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1618
1619                 /* 8168D family. */
1620                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1621                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1622                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1623
1624                 /* 8168DP family. */
1625                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1626                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1627                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1628
1629                 /* 8168C family. */
1630                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1631                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1632                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1633                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1634                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1635                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1636                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1637                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1638                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1639
1640                 /* 8168B family. */
1641                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1642                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1643                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1644                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1645
1646                 /* 8101 family. */
1647                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1648                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1649                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1650                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1651                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1652                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1653                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1654                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1655                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1656                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1657                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1658                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1659                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1660                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1661                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1662                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1663                 /* FIXME: where did these entries come from ? -- FR */
1664                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1665                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1666
1667                 /* 8110 family. */
1668                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1669                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1670                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1671                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1672                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1673                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1674
1675                 /* Catch-all */
1676                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1677         }, *p = mac_info;
1678         u32 reg;
1679
1680         reg = RTL_R32(TxConfig);
1681         while ((reg & p->mask) != p->val)
1682                 p++;
1683         tp->mac_version = p->mac_version;
1684 }
1685
1686 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1687 {
1688         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1689 }
1690
1691 struct phy_reg {
1692         u16 reg;
1693         u16 val;
1694 };
1695
1696 static void rtl_writephy_batch(struct rtl8169_private *tp,
1697                                const struct phy_reg *regs, int len)
1698 {
1699         while (len-- > 0) {
1700                 rtl_writephy(tp, regs->reg, regs->val);
1701                 regs++;
1702         }
1703 }
1704
1705 #define PHY_READ                0x00000000
1706 #define PHY_DATA_OR             0x10000000
1707 #define PHY_DATA_AND            0x20000000
1708 #define PHY_BJMPN               0x30000000
1709 #define PHY_READ_EFUSE          0x40000000
1710 #define PHY_READ_MAC_BYTE       0x50000000
1711 #define PHY_WRITE_MAC_BYTE      0x60000000
1712 #define PHY_CLEAR_READCOUNT     0x70000000
1713 #define PHY_WRITE               0x80000000
1714 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1715 #define PHY_COMP_EQ_SKIPN       0xa0000000
1716 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1717 #define PHY_WRITE_PREVIOUS      0xc0000000
1718 #define PHY_SKIPN               0xd0000000
1719 #define PHY_DELAY_MS            0xe0000000
1720 #define PHY_WRITE_ERI_WORD      0xf0000000
1721
1722 static void
1723 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1724 {
1725         __le32 *phytable = (__le32 *)fw->data;
1726         struct net_device *dev = tp->dev;
1727         size_t index, fw_size = fw->size / sizeof(*phytable);
1728         u32 predata, count;
1729
1730         if (fw->size % sizeof(*phytable)) {
1731                 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1732                 return;
1733         }
1734
1735         for (index = 0; index < fw_size; index++) {
1736                 u32 action = le32_to_cpu(phytable[index]);
1737                 u32 regno = (action & 0x0fff0000) >> 16;
1738
1739                 switch(action & 0xf0000000) {
1740                 case PHY_READ:
1741                 case PHY_DATA_OR:
1742                 case PHY_DATA_AND:
1743                 case PHY_READ_EFUSE:
1744                 case PHY_CLEAR_READCOUNT:
1745                 case PHY_WRITE:
1746                 case PHY_WRITE_PREVIOUS:
1747                 case PHY_DELAY_MS:
1748                         break;
1749
1750                 case PHY_BJMPN:
1751                         if (regno > index) {
1752                                 netif_err(tp, probe, tp->dev,
1753                                         "Out of range of firmware\n");
1754                                 return;
1755                         }
1756                         break;
1757                 case PHY_READCOUNT_EQ_SKIP:
1758                         if (index + 2 >= fw_size) {
1759                                 netif_err(tp, probe, tp->dev,
1760                                         "Out of range of firmware\n");
1761                                 return;
1762                         }
1763                         break;
1764                 case PHY_COMP_EQ_SKIPN:
1765                 case PHY_COMP_NEQ_SKIPN:
1766                 case PHY_SKIPN:
1767                         if (index + 1 + regno >= fw_size) {
1768                                 netif_err(tp, probe, tp->dev,
1769                                         "Out of range of firmware\n");
1770                                 return;
1771                         }
1772                         break;
1773
1774                 case PHY_READ_MAC_BYTE:
1775                 case PHY_WRITE_MAC_BYTE:
1776                 case PHY_WRITE_ERI_WORD:
1777                 default:
1778                         netif_err(tp, probe, tp->dev,
1779                                   "Invalid action 0x%08x\n", action);
1780                         return;
1781                 }
1782         }
1783
1784         predata = 0;
1785         count = 0;
1786
1787         for (index = 0; index < fw_size; ) {
1788                 u32 action = le32_to_cpu(phytable[index]);
1789                 u32 data = action & 0x0000ffff;
1790                 u32 regno = (action & 0x0fff0000) >> 16;
1791
1792                 if (!action)
1793                         break;
1794
1795                 switch(action & 0xf0000000) {
1796                 case PHY_READ:
1797                         predata = rtl_readphy(tp, regno);
1798                         count++;
1799                         index++;
1800                         break;
1801                 case PHY_DATA_OR:
1802                         predata |= data;
1803                         index++;
1804                         break;
1805                 case PHY_DATA_AND:
1806                         predata &= data;
1807                         index++;
1808                         break;
1809                 case PHY_BJMPN:
1810                         index -= regno;
1811                         break;
1812                 case PHY_READ_EFUSE:
1813                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1814                         index++;
1815                         break;
1816                 case PHY_CLEAR_READCOUNT:
1817                         count = 0;
1818                         index++;
1819                         break;
1820                 case PHY_WRITE:
1821                         rtl_writephy(tp, regno, data);
1822                         index++;
1823                         break;
1824                 case PHY_READCOUNT_EQ_SKIP:
1825                         if (count == data)
1826                                 index += 2;
1827                         else
1828                                 index += 1;
1829                         break;
1830                 case PHY_COMP_EQ_SKIPN:
1831                         if (predata == data)
1832                                 index += regno;
1833                         index++;
1834                         break;
1835                 case PHY_COMP_NEQ_SKIPN:
1836                         if (predata != data)
1837                                 index += regno;
1838                         index++;
1839                         break;
1840                 case PHY_WRITE_PREVIOUS:
1841                         rtl_writephy(tp, regno, predata);
1842                         index++;
1843                         break;
1844                 case PHY_SKIPN:
1845                         index += regno + 1;
1846                         break;
1847                 case PHY_DELAY_MS:
1848                         mdelay(data);
1849                         index++;
1850                         break;
1851
1852                 case PHY_READ_MAC_BYTE:
1853                 case PHY_WRITE_MAC_BYTE:
1854                 case PHY_WRITE_ERI_WORD:
1855                 default:
1856                         BUG();
1857                 }
1858         }
1859 }
1860
1861 static void rtl_release_firmware(struct rtl8169_private *tp)
1862 {
1863         if (!IS_ERR_OR_NULL(tp->fw))
1864                 release_firmware(tp->fw);
1865         tp->fw = RTL_FIRMWARE_UNKNOWN;
1866 }
1867
1868 static void rtl_apply_firmware(struct rtl8169_private *tp)
1869 {
1870         const struct firmware *fw = tp->fw;
1871
1872         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1873         if (!IS_ERR_OR_NULL(fw))
1874                 rtl_phy_write_fw(tp, fw);
1875 }
1876
1877 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1878 {
1879         if (rtl_readphy(tp, reg) != val)
1880                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1881         else
1882                 rtl_apply_firmware(tp);
1883 }
1884
1885 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1886 {
1887         static const struct phy_reg phy_reg_init[] = {
1888                 { 0x1f, 0x0001 },
1889                 { 0x06, 0x006e },
1890                 { 0x08, 0x0708 },
1891                 { 0x15, 0x4000 },
1892                 { 0x18, 0x65c7 },
1893
1894                 { 0x1f, 0x0001 },
1895                 { 0x03, 0x00a1 },
1896                 { 0x02, 0x0008 },
1897                 { 0x01, 0x0120 },
1898                 { 0x00, 0x1000 },
1899                 { 0x04, 0x0800 },
1900                 { 0x04, 0x0000 },
1901
1902                 { 0x03, 0xff41 },
1903                 { 0x02, 0xdf60 },
1904                 { 0x01, 0x0140 },
1905                 { 0x00, 0x0077 },
1906                 { 0x04, 0x7800 },
1907                 { 0x04, 0x7000 },
1908
1909                 { 0x03, 0x802f },
1910                 { 0x02, 0x4f02 },
1911                 { 0x01, 0x0409 },
1912                 { 0x00, 0xf0f9 },
1913                 { 0x04, 0x9800 },
1914                 { 0x04, 0x9000 },
1915
1916                 { 0x03, 0xdf01 },
1917                 { 0x02, 0xdf20 },
1918                 { 0x01, 0xff95 },
1919                 { 0x00, 0xba00 },
1920                 { 0x04, 0xa800 },
1921                 { 0x04, 0xa000 },
1922
1923                 { 0x03, 0xff41 },
1924                 { 0x02, 0xdf20 },
1925                 { 0x01, 0x0140 },
1926                 { 0x00, 0x00bb },
1927                 { 0x04, 0xb800 },
1928                 { 0x04, 0xb000 },
1929
1930                 { 0x03, 0xdf41 },
1931                 { 0x02, 0xdc60 },
1932                 { 0x01, 0x6340 },
1933                 { 0x00, 0x007d },
1934                 { 0x04, 0xd800 },
1935                 { 0x04, 0xd000 },
1936
1937                 { 0x03, 0xdf01 },
1938                 { 0x02, 0xdf20 },
1939                 { 0x01, 0x100a },
1940                 { 0x00, 0xa0ff },
1941                 { 0x04, 0xf800 },
1942                 { 0x04, 0xf000 },
1943
1944                 { 0x1f, 0x0000 },
1945                 { 0x0b, 0x0000 },
1946                 { 0x00, 0x9200 }
1947         };
1948
1949         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1950 }
1951
1952 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1953 {
1954         static const struct phy_reg phy_reg_init[] = {
1955                 { 0x1f, 0x0002 },
1956                 { 0x01, 0x90d0 },
1957                 { 0x1f, 0x0000 }
1958         };
1959
1960         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1961 }
1962
1963 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1964 {
1965         struct pci_dev *pdev = tp->pci_dev;
1966         u16 vendor_id, device_id;
1967
1968         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1969         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1970
1971         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1972                 return;
1973
1974         rtl_writephy(tp, 0x1f, 0x0001);
1975         rtl_writephy(tp, 0x10, 0xf01b);
1976         rtl_writephy(tp, 0x1f, 0x0000);
1977 }
1978
1979 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
1980 {
1981         static const struct phy_reg phy_reg_init[] = {
1982                 { 0x1f, 0x0001 },
1983                 { 0x04, 0x0000 },
1984                 { 0x03, 0x00a1 },
1985                 { 0x02, 0x0008 },
1986                 { 0x01, 0x0120 },
1987                 { 0x00, 0x1000 },
1988                 { 0x04, 0x0800 },
1989                 { 0x04, 0x9000 },
1990                 { 0x03, 0x802f },
1991                 { 0x02, 0x4f02 },
1992                 { 0x01, 0x0409 },
1993                 { 0x00, 0xf099 },
1994                 { 0x04, 0x9800 },
1995                 { 0x04, 0xa000 },
1996                 { 0x03, 0xdf01 },
1997                 { 0x02, 0xdf20 },
1998                 { 0x01, 0xff95 },
1999                 { 0x00, 0xba00 },
2000                 { 0x04, 0xa800 },
2001                 { 0x04, 0xf000 },
2002                 { 0x03, 0xdf01 },
2003                 { 0x02, 0xdf20 },
2004                 { 0x01, 0x101a },
2005                 { 0x00, 0xa0ff },
2006                 { 0x04, 0xf800 },
2007                 { 0x04, 0x0000 },
2008                 { 0x1f, 0x0000 },
2009
2010                 { 0x1f, 0x0001 },
2011                 { 0x10, 0xf41b },
2012                 { 0x14, 0xfb54 },
2013                 { 0x18, 0xf5c7 },
2014                 { 0x1f, 0x0000 },
2015
2016                 { 0x1f, 0x0001 },
2017                 { 0x17, 0x0cc0 },
2018                 { 0x1f, 0x0000 }
2019         };
2020
2021         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2022
2023         rtl8169scd_hw_phy_config_quirk(tp);
2024 }
2025
2026 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2027 {
2028         static const struct phy_reg phy_reg_init[] = {
2029                 { 0x1f, 0x0001 },
2030                 { 0x04, 0x0000 },
2031                 { 0x03, 0x00a1 },
2032                 { 0x02, 0x0008 },
2033                 { 0x01, 0x0120 },
2034                 { 0x00, 0x1000 },
2035                 { 0x04, 0x0800 },
2036                 { 0x04, 0x9000 },
2037                 { 0x03, 0x802f },
2038                 { 0x02, 0x4f02 },
2039                 { 0x01, 0x0409 },
2040                 { 0x00, 0xf099 },
2041                 { 0x04, 0x9800 },
2042                 { 0x04, 0xa000 },
2043                 { 0x03, 0xdf01 },
2044                 { 0x02, 0xdf20 },
2045                 { 0x01, 0xff95 },
2046                 { 0x00, 0xba00 },
2047                 { 0x04, 0xa800 },
2048                 { 0x04, 0xf000 },
2049                 { 0x03, 0xdf01 },
2050                 { 0x02, 0xdf20 },
2051                 { 0x01, 0x101a },
2052                 { 0x00, 0xa0ff },
2053                 { 0x04, 0xf800 },
2054                 { 0x04, 0x0000 },
2055                 { 0x1f, 0x0000 },
2056
2057                 { 0x1f, 0x0001 },
2058                 { 0x0b, 0x8480 },
2059                 { 0x1f, 0x0000 },
2060
2061                 { 0x1f, 0x0001 },
2062                 { 0x18, 0x67c7 },
2063                 { 0x04, 0x2000 },
2064                 { 0x03, 0x002f },
2065                 { 0x02, 0x4360 },
2066                 { 0x01, 0x0109 },
2067                 { 0x00, 0x3022 },
2068                 { 0x04, 0x2800 },
2069                 { 0x1f, 0x0000 },
2070
2071                 { 0x1f, 0x0001 },
2072                 { 0x17, 0x0cc0 },
2073                 { 0x1f, 0x0000 }
2074         };
2075
2076         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2077 }
2078
2079 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2080 {
2081         static const struct phy_reg phy_reg_init[] = {
2082                 { 0x10, 0xf41b },
2083                 { 0x1f, 0x0000 }
2084         };
2085
2086         rtl_writephy(tp, 0x1f, 0x0001);
2087         rtl_patchphy(tp, 0x16, 1 << 0);
2088
2089         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2090 }
2091
2092 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2093 {
2094         static const struct phy_reg phy_reg_init[] = {
2095                 { 0x1f, 0x0001 },
2096                 { 0x10, 0xf41b },
2097                 { 0x1f, 0x0000 }
2098         };
2099
2100         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2101 }
2102
2103 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2104 {
2105         static const struct phy_reg phy_reg_init[] = {
2106                 { 0x1f, 0x0000 },
2107                 { 0x1d, 0x0f00 },
2108                 { 0x1f, 0x0002 },
2109                 { 0x0c, 0x1ec8 },
2110                 { 0x1f, 0x0000 }
2111         };
2112
2113         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2114 }
2115
2116 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2117 {
2118         static const struct phy_reg phy_reg_init[] = {
2119                 { 0x1f, 0x0001 },
2120                 { 0x1d, 0x3d98 },
2121                 { 0x1f, 0x0000 }
2122         };
2123
2124         rtl_writephy(tp, 0x1f, 0x0000);
2125         rtl_patchphy(tp, 0x14, 1 << 5);
2126         rtl_patchphy(tp, 0x0d, 1 << 5);
2127
2128         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2129 }
2130
2131 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2132 {
2133         static const struct phy_reg phy_reg_init[] = {
2134                 { 0x1f, 0x0001 },
2135                 { 0x12, 0x2300 },
2136                 { 0x1f, 0x0002 },
2137                 { 0x00, 0x88d4 },
2138                 { 0x01, 0x82b1 },
2139                 { 0x03, 0x7002 },
2140                 { 0x08, 0x9e30 },
2141                 { 0x09, 0x01f0 },
2142                 { 0x0a, 0x5500 },
2143                 { 0x0c, 0x00c8 },
2144                 { 0x1f, 0x0003 },
2145                 { 0x12, 0xc096 },
2146                 { 0x16, 0x000a },
2147                 { 0x1f, 0x0000 },
2148                 { 0x1f, 0x0000 },
2149                 { 0x09, 0x2000 },
2150                 { 0x09, 0x0000 }
2151         };
2152
2153         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2154
2155         rtl_patchphy(tp, 0x14, 1 << 5);
2156         rtl_patchphy(tp, 0x0d, 1 << 5);
2157         rtl_writephy(tp, 0x1f, 0x0000);
2158 }
2159
2160 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2161 {
2162         static const struct phy_reg phy_reg_init[] = {
2163                 { 0x1f, 0x0001 },
2164                 { 0x12, 0x2300 },
2165                 { 0x03, 0x802f },
2166                 { 0x02, 0x4f02 },
2167                 { 0x01, 0x0409 },
2168                 { 0x00, 0xf099 },
2169                 { 0x04, 0x9800 },
2170                 { 0x04, 0x9000 },
2171                 { 0x1d, 0x3d98 },
2172                 { 0x1f, 0x0002 },
2173                 { 0x0c, 0x7eb8 },
2174                 { 0x06, 0x0761 },
2175                 { 0x1f, 0x0003 },
2176                 { 0x16, 0x0f0a },
2177                 { 0x1f, 0x0000 }
2178         };
2179
2180         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2181
2182         rtl_patchphy(tp, 0x16, 1 << 0);
2183         rtl_patchphy(tp, 0x14, 1 << 5);
2184         rtl_patchphy(tp, 0x0d, 1 << 5);
2185         rtl_writephy(tp, 0x1f, 0x0000);
2186 }
2187
2188 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2189 {
2190         static const struct phy_reg phy_reg_init[] = {
2191                 { 0x1f, 0x0001 },
2192                 { 0x12, 0x2300 },
2193                 { 0x1d, 0x3d98 },
2194                 { 0x1f, 0x0002 },
2195                 { 0x0c, 0x7eb8 },
2196                 { 0x06, 0x5461 },
2197                 { 0x1f, 0x0003 },
2198                 { 0x16, 0x0f0a },
2199                 { 0x1f, 0x0000 }
2200         };
2201
2202         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2203
2204         rtl_patchphy(tp, 0x16, 1 << 0);
2205         rtl_patchphy(tp, 0x14, 1 << 5);
2206         rtl_patchphy(tp, 0x0d, 1 << 5);
2207         rtl_writephy(tp, 0x1f, 0x0000);
2208 }
2209
2210 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2211 {
2212         rtl8168c_3_hw_phy_config(tp);
2213 }
2214
2215 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2216 {
2217         static const struct phy_reg phy_reg_init_0[] = {
2218                 /* Channel Estimation */
2219                 { 0x1f, 0x0001 },
2220                 { 0x06, 0x4064 },
2221                 { 0x07, 0x2863 },
2222                 { 0x08, 0x059c },
2223                 { 0x09, 0x26b4 },
2224                 { 0x0a, 0x6a19 },
2225                 { 0x0b, 0xdcc8 },
2226                 { 0x10, 0xf06d },
2227                 { 0x14, 0x7f68 },
2228                 { 0x18, 0x7fd9 },
2229                 { 0x1c, 0xf0ff },
2230                 { 0x1d, 0x3d9c },
2231                 { 0x1f, 0x0003 },
2232                 { 0x12, 0xf49f },
2233                 { 0x13, 0x070b },
2234                 { 0x1a, 0x05ad },
2235                 { 0x14, 0x94c0 },
2236
2237                 /*
2238                  * Tx Error Issue
2239                  * enhance line driver power
2240                  */
2241                 { 0x1f, 0x0002 },
2242                 { 0x06, 0x5561 },
2243                 { 0x1f, 0x0005 },
2244                 { 0x05, 0x8332 },
2245                 { 0x06, 0x5561 },
2246
2247                 /*
2248                  * Can not link to 1Gbps with bad cable
2249                  * Decrease SNR threshold form 21.07dB to 19.04dB
2250                  */
2251                 { 0x1f, 0x0001 },
2252                 { 0x17, 0x0cc0 },
2253
2254                 { 0x1f, 0x0000 },
2255                 { 0x0d, 0xf880 }
2256         };
2257         void __iomem *ioaddr = tp->mmio_addr;
2258
2259         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2260
2261         /*
2262          * Rx Error Issue
2263          * Fine Tune Switching regulator parameter
2264          */
2265         rtl_writephy(tp, 0x1f, 0x0002);
2266         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2267         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2268
2269         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2270                 static const struct phy_reg phy_reg_init[] = {
2271                         { 0x1f, 0x0002 },
2272                         { 0x05, 0x669a },
2273                         { 0x1f, 0x0005 },
2274                         { 0x05, 0x8330 },
2275                         { 0x06, 0x669a },
2276                         { 0x1f, 0x0002 }
2277                 };
2278                 int val;
2279
2280                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2281
2282                 val = rtl_readphy(tp, 0x0d);
2283
2284                 if ((val & 0x00ff) != 0x006c) {
2285                         static const u32 set[] = {
2286                                 0x0065, 0x0066, 0x0067, 0x0068,
2287                                 0x0069, 0x006a, 0x006b, 0x006c
2288                         };
2289                         int i;
2290
2291                         rtl_writephy(tp, 0x1f, 0x0002);
2292
2293                         val &= 0xff00;
2294                         for (i = 0; i < ARRAY_SIZE(set); i++)
2295                                 rtl_writephy(tp, 0x0d, val | set[i]);
2296                 }
2297         } else {
2298                 static const struct phy_reg phy_reg_init[] = {
2299                         { 0x1f, 0x0002 },
2300                         { 0x05, 0x6662 },
2301                         { 0x1f, 0x0005 },
2302                         { 0x05, 0x8330 },
2303                         { 0x06, 0x6662 }
2304                 };
2305
2306                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2307         }
2308
2309         /* RSET couple improve */
2310         rtl_writephy(tp, 0x1f, 0x0002);
2311         rtl_patchphy(tp, 0x0d, 0x0300);
2312         rtl_patchphy(tp, 0x0f, 0x0010);
2313
2314         /* Fine tune PLL performance */
2315         rtl_writephy(tp, 0x1f, 0x0002);
2316         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2317         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2318
2319         rtl_writephy(tp, 0x1f, 0x0005);
2320         rtl_writephy(tp, 0x05, 0x001b);
2321
2322         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2323
2324         rtl_writephy(tp, 0x1f, 0x0000);
2325 }
2326
2327 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2328 {
2329         static const struct phy_reg phy_reg_init_0[] = {
2330                 /* Channel Estimation */
2331                 { 0x1f, 0x0001 },
2332                 { 0x06, 0x4064 },
2333                 { 0x07, 0x2863 },
2334                 { 0x08, 0x059c },
2335                 { 0x09, 0x26b4 },
2336                 { 0x0a, 0x6a19 },
2337                 { 0x0b, 0xdcc8 },
2338                 { 0x10, 0xf06d },
2339                 { 0x14, 0x7f68 },
2340                 { 0x18, 0x7fd9 },
2341                 { 0x1c, 0xf0ff },
2342                 { 0x1d, 0x3d9c },
2343                 { 0x1f, 0x0003 },
2344                 { 0x12, 0xf49f },
2345                 { 0x13, 0x070b },
2346                 { 0x1a, 0x05ad },
2347                 { 0x14, 0x94c0 },
2348
2349                 /*
2350                  * Tx Error Issue
2351                  * enhance line driver power
2352                  */
2353                 { 0x1f, 0x0002 },
2354                 { 0x06, 0x5561 },
2355                 { 0x1f, 0x0005 },
2356                 { 0x05, 0x8332 },
2357                 { 0x06, 0x5561 },
2358
2359                 /*
2360                  * Can not link to 1Gbps with bad cable
2361                  * Decrease SNR threshold form 21.07dB to 19.04dB
2362                  */
2363                 { 0x1f, 0x0001 },
2364                 { 0x17, 0x0cc0 },
2365
2366                 { 0x1f, 0x0000 },
2367                 { 0x0d, 0xf880 }
2368         };
2369         void __iomem *ioaddr = tp->mmio_addr;
2370
2371         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2372
2373         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2374                 static const struct phy_reg phy_reg_init[] = {
2375                         { 0x1f, 0x0002 },
2376                         { 0x05, 0x669a },
2377                         { 0x1f, 0x0005 },
2378                         { 0x05, 0x8330 },
2379                         { 0x06, 0x669a },
2380
2381                         { 0x1f, 0x0002 }
2382                 };
2383                 int val;
2384
2385                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2386
2387                 val = rtl_readphy(tp, 0x0d);
2388                 if ((val & 0x00ff) != 0x006c) {
2389                         static const u32 set[] = {
2390                                 0x0065, 0x0066, 0x0067, 0x0068,
2391                                 0x0069, 0x006a, 0x006b, 0x006c
2392                         };
2393                         int i;
2394
2395                         rtl_writephy(tp, 0x1f, 0x0002);
2396
2397                         val &= 0xff00;
2398                         for (i = 0; i < ARRAY_SIZE(set); i++)
2399                                 rtl_writephy(tp, 0x0d, val | set[i]);
2400                 }
2401         } else {
2402                 static const struct phy_reg phy_reg_init[] = {
2403                         { 0x1f, 0x0002 },
2404                         { 0x05, 0x2642 },
2405                         { 0x1f, 0x0005 },
2406                         { 0x05, 0x8330 },
2407                         { 0x06, 0x2642 }
2408                 };
2409
2410                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2411         }
2412
2413         /* Fine tune PLL performance */
2414         rtl_writephy(tp, 0x1f, 0x0002);
2415         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2416         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2417
2418         /* Switching regulator Slew rate */
2419         rtl_writephy(tp, 0x1f, 0x0002);
2420         rtl_patchphy(tp, 0x0f, 0x0017);
2421
2422         rtl_writephy(tp, 0x1f, 0x0005);
2423         rtl_writephy(tp, 0x05, 0x001b);
2424
2425         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2426
2427         rtl_writephy(tp, 0x1f, 0x0000);
2428 }
2429
2430 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2431 {
2432         static const struct phy_reg phy_reg_init[] = {
2433                 { 0x1f, 0x0002 },
2434                 { 0x10, 0x0008 },
2435                 { 0x0d, 0x006c },
2436
2437                 { 0x1f, 0x0000 },
2438                 { 0x0d, 0xf880 },
2439
2440                 { 0x1f, 0x0001 },
2441                 { 0x17, 0x0cc0 },
2442
2443                 { 0x1f, 0x0001 },
2444                 { 0x0b, 0xa4d8 },
2445                 { 0x09, 0x281c },
2446                 { 0x07, 0x2883 },
2447                 { 0x0a, 0x6b35 },
2448                 { 0x1d, 0x3da4 },
2449                 { 0x1c, 0xeffd },
2450                 { 0x14, 0x7f52 },
2451                 { 0x18, 0x7fc6 },
2452                 { 0x08, 0x0601 },
2453                 { 0x06, 0x4063 },
2454                 { 0x10, 0xf074 },
2455                 { 0x1f, 0x0003 },
2456                 { 0x13, 0x0789 },
2457                 { 0x12, 0xf4bd },
2458                 { 0x1a, 0x04fd },
2459                 { 0x14, 0x84b0 },
2460                 { 0x1f, 0x0000 },
2461                 { 0x00, 0x9200 },
2462
2463                 { 0x1f, 0x0005 },
2464                 { 0x01, 0x0340 },
2465                 { 0x1f, 0x0001 },
2466                 { 0x04, 0x4000 },
2467                 { 0x03, 0x1d21 },
2468                 { 0x02, 0x0c32 },
2469                 { 0x01, 0x0200 },
2470                 { 0x00, 0x5554 },
2471                 { 0x04, 0x4800 },
2472                 { 0x04, 0x4000 },
2473                 { 0x04, 0xf000 },
2474                 { 0x03, 0xdf01 },
2475                 { 0x02, 0xdf20 },
2476                 { 0x01, 0x101a },
2477                 { 0x00, 0xa0ff },
2478                 { 0x04, 0xf800 },
2479                 { 0x04, 0xf000 },
2480                 { 0x1f, 0x0000 },
2481
2482                 { 0x1f, 0x0007 },
2483                 { 0x1e, 0x0023 },
2484                 { 0x16, 0x0000 },
2485                 { 0x1f, 0x0000 }
2486         };
2487
2488         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2489 }
2490
2491 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2492 {
2493         static const struct phy_reg phy_reg_init[] = {
2494                 { 0x1f, 0x0001 },
2495                 { 0x17, 0x0cc0 },
2496
2497                 { 0x1f, 0x0007 },
2498                 { 0x1e, 0x002d },
2499                 { 0x18, 0x0040 },
2500                 { 0x1f, 0x0000 }
2501         };
2502
2503         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2504         rtl_patchphy(tp, 0x0d, 1 << 5);
2505 }
2506
2507 static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2508 {
2509         static const struct phy_reg phy_reg_init[] = {
2510                 /* Enable Delay cap */
2511                 { 0x1f, 0x0005 },
2512                 { 0x05, 0x8b80 },
2513                 { 0x06, 0xc896 },
2514                 { 0x1f, 0x0000 },
2515
2516                 /* Channel estimation fine tune */
2517                 { 0x1f, 0x0001 },
2518                 { 0x0b, 0x6c20 },
2519                 { 0x07, 0x2872 },
2520                 { 0x1c, 0xefff },
2521                 { 0x1f, 0x0003 },
2522                 { 0x14, 0x6420 },
2523                 { 0x1f, 0x0000 },
2524
2525                 /* Update PFM & 10M TX idle timer */
2526                 { 0x1f, 0x0007 },
2527                 { 0x1e, 0x002f },
2528                 { 0x15, 0x1919 },
2529                 { 0x1f, 0x0000 },
2530
2531                 { 0x1f, 0x0007 },
2532                 { 0x1e, 0x00ac },
2533                 { 0x18, 0x0006 },
2534                 { 0x1f, 0x0000 }
2535         };
2536
2537         rtl_apply_firmware(tp);
2538
2539         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2540
2541         /* DCO enable for 10M IDLE Power */
2542         rtl_writephy(tp, 0x1f, 0x0007);
2543         rtl_writephy(tp, 0x1e, 0x0023);
2544         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2545         rtl_writephy(tp, 0x1f, 0x0000);
2546
2547         /* For impedance matching */
2548         rtl_writephy(tp, 0x1f, 0x0002);
2549         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2550         rtl_writephy(tp, 0x1F, 0x0000);
2551
2552         /* PHY auto speed down */
2553         rtl_writephy(tp, 0x1f, 0x0007);
2554         rtl_writephy(tp, 0x1e, 0x002d);
2555         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2556         rtl_writephy(tp, 0x1f, 0x0000);
2557         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2558
2559         rtl_writephy(tp, 0x1f, 0x0005);
2560         rtl_writephy(tp, 0x05, 0x8b86);
2561         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2562         rtl_writephy(tp, 0x1f, 0x0000);
2563
2564         rtl_writephy(tp, 0x1f, 0x0005);
2565         rtl_writephy(tp, 0x05, 0x8b85);
2566         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2567         rtl_writephy(tp, 0x1f, 0x0007);
2568         rtl_writephy(tp, 0x1e, 0x0020);
2569         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2570         rtl_writephy(tp, 0x1f, 0x0006);
2571         rtl_writephy(tp, 0x00, 0x5a00);
2572         rtl_writephy(tp, 0x1f, 0x0000);
2573         rtl_writephy(tp, 0x0d, 0x0007);
2574         rtl_writephy(tp, 0x0e, 0x003c);
2575         rtl_writephy(tp, 0x0d, 0x4007);
2576         rtl_writephy(tp, 0x0e, 0x0000);
2577         rtl_writephy(tp, 0x0d, 0x0000);
2578 }
2579
2580 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2581 {
2582         static const struct phy_reg phy_reg_init[] = {
2583                 { 0x1f, 0x0003 },
2584                 { 0x08, 0x441d },
2585                 { 0x01, 0x9100 },
2586                 { 0x1f, 0x0000 }
2587         };
2588
2589         rtl_writephy(tp, 0x1f, 0x0000);
2590         rtl_patchphy(tp, 0x11, 1 << 12);
2591         rtl_patchphy(tp, 0x19, 1 << 13);
2592         rtl_patchphy(tp, 0x10, 1 << 15);
2593
2594         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2595 }
2596
2597 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2598 {
2599         static const struct phy_reg phy_reg_init[] = {
2600                 { 0x1f, 0x0005 },
2601                 { 0x1a, 0x0000 },
2602                 { 0x1f, 0x0000 },
2603
2604                 { 0x1f, 0x0004 },
2605                 { 0x1c, 0x0000 },
2606                 { 0x1f, 0x0000 },
2607
2608                 { 0x1f, 0x0001 },
2609                 { 0x15, 0x7701 },
2610                 { 0x1f, 0x0000 }
2611         };
2612
2613         /* Disable ALDPS before ram code */
2614         rtl_writephy(tp, 0x1f, 0x0000);
2615         rtl_writephy(tp, 0x18, 0x0310);
2616         msleep(100);
2617
2618         rtl_apply_firmware(tp);
2619
2620         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2621 }
2622
2623 static void rtl_hw_phy_config(struct net_device *dev)
2624 {
2625         struct rtl8169_private *tp = netdev_priv(dev);
2626
2627         rtl8169_print_mac_version(tp);
2628
2629         switch (tp->mac_version) {
2630         case RTL_GIGA_MAC_VER_01:
2631                 break;
2632         case RTL_GIGA_MAC_VER_02:
2633         case RTL_GIGA_MAC_VER_03:
2634                 rtl8169s_hw_phy_config(tp);
2635                 break;
2636         case RTL_GIGA_MAC_VER_04:
2637                 rtl8169sb_hw_phy_config(tp);
2638                 break;
2639         case RTL_GIGA_MAC_VER_05:
2640                 rtl8169scd_hw_phy_config(tp);
2641                 break;
2642         case RTL_GIGA_MAC_VER_06:
2643                 rtl8169sce_hw_phy_config(tp);
2644                 break;
2645         case RTL_GIGA_MAC_VER_07:
2646         case RTL_GIGA_MAC_VER_08:
2647         case RTL_GIGA_MAC_VER_09:
2648                 rtl8102e_hw_phy_config(tp);
2649                 break;
2650         case RTL_GIGA_MAC_VER_11:
2651                 rtl8168bb_hw_phy_config(tp);
2652                 break;
2653         case RTL_GIGA_MAC_VER_12:
2654                 rtl8168bef_hw_phy_config(tp);
2655                 break;
2656         case RTL_GIGA_MAC_VER_17:
2657                 rtl8168bef_hw_phy_config(tp);
2658                 break;
2659         case RTL_GIGA_MAC_VER_18:
2660                 rtl8168cp_1_hw_phy_config(tp);
2661                 break;
2662         case RTL_GIGA_MAC_VER_19:
2663                 rtl8168c_1_hw_phy_config(tp);
2664                 break;
2665         case RTL_GIGA_MAC_VER_20:
2666                 rtl8168c_2_hw_phy_config(tp);
2667                 break;
2668         case RTL_GIGA_MAC_VER_21:
2669                 rtl8168c_3_hw_phy_config(tp);
2670                 break;
2671         case RTL_GIGA_MAC_VER_22:
2672                 rtl8168c_4_hw_phy_config(tp);
2673                 break;
2674         case RTL_GIGA_MAC_VER_23:
2675         case RTL_GIGA_MAC_VER_24:
2676                 rtl8168cp_2_hw_phy_config(tp);
2677                 break;
2678         case RTL_GIGA_MAC_VER_25:
2679                 rtl8168d_1_hw_phy_config(tp);
2680                 break;
2681         case RTL_GIGA_MAC_VER_26:
2682                 rtl8168d_2_hw_phy_config(tp);
2683                 break;
2684         case RTL_GIGA_MAC_VER_27:
2685                 rtl8168d_3_hw_phy_config(tp);
2686                 break;
2687         case RTL_GIGA_MAC_VER_28:
2688                 rtl8168d_4_hw_phy_config(tp);
2689                 break;
2690         case RTL_GIGA_MAC_VER_29:
2691         case RTL_GIGA_MAC_VER_30:
2692                 rtl8105e_hw_phy_config(tp);
2693                 break;
2694         case RTL_GIGA_MAC_VER_32:
2695         case RTL_GIGA_MAC_VER_33:
2696                 rtl8168e_hw_phy_config(tp);
2697                 break;
2698
2699         default:
2700                 break;
2701         }
2702 }
2703
2704 static void rtl8169_phy_timer(unsigned long __opaque)
2705 {
2706         struct net_device *dev = (struct net_device *)__opaque;
2707         struct rtl8169_private *tp = netdev_priv(dev);
2708         struct timer_list *timer = &tp->timer;
2709         void __iomem *ioaddr = tp->mmio_addr;
2710         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2711
2712         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2713
2714         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2715                 return;
2716
2717         spin_lock_irq(&tp->lock);
2718
2719         if (tp->phy_reset_pending(tp)) {
2720                 /*
2721                  * A busy loop could burn quite a few cycles on nowadays CPU.
2722                  * Let's delay the execution of the timer for a few ticks.
2723                  */
2724                 timeout = HZ/10;
2725                 goto out_mod_timer;
2726         }
2727
2728         if (tp->link_ok(ioaddr))
2729                 goto out_unlock;
2730
2731         netif_warn(tp, link, dev, "PHY reset until link up\n");
2732
2733         tp->phy_reset_enable(tp);
2734
2735 out_mod_timer:
2736         mod_timer(timer, jiffies + timeout);
2737 out_unlock:
2738         spin_unlock_irq(&tp->lock);
2739 }
2740
2741 static inline void rtl8169_delete_timer(struct net_device *dev)
2742 {
2743         struct rtl8169_private *tp = netdev_priv(dev);
2744         struct timer_list *timer = &tp->timer;
2745
2746         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2747                 return;
2748
2749         del_timer_sync(timer);
2750 }
2751
2752 static inline void rtl8169_request_timer(struct net_device *dev)
2753 {
2754         struct rtl8169_private *tp = netdev_priv(dev);
2755         struct timer_list *timer = &tp->timer;
2756
2757         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2758                 return;
2759
2760         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2761 }
2762
2763 #ifdef CONFIG_NET_POLL_CONTROLLER
2764 /*
2765  * Polling 'interrupt' - used by things like netconsole to send skbs
2766  * without having to re-enable interrupts. It's not called while
2767  * the interrupt routine is executing.
2768  */
2769 static void rtl8169_netpoll(struct net_device *dev)
2770 {
2771         struct rtl8169_private *tp = netdev_priv(dev);
2772         struct pci_dev *pdev = tp->pci_dev;
2773
2774         disable_irq(pdev->irq);
2775         rtl8169_interrupt(pdev->irq, dev);
2776         enable_irq(pdev->irq);
2777 }
2778 #endif
2779
2780 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2781                                   void __iomem *ioaddr)
2782 {
2783         iounmap(ioaddr);
2784         pci_release_regions(pdev);
2785         pci_clear_mwi(pdev);
2786         pci_disable_device(pdev);
2787         free_netdev(dev);
2788 }
2789
2790 static void rtl8169_phy_reset(struct net_device *dev,
2791                               struct rtl8169_private *tp)
2792 {
2793         unsigned int i;
2794
2795         tp->phy_reset_enable(tp);
2796         for (i = 0; i < 100; i++) {
2797                 if (!tp->phy_reset_pending(tp))
2798                         return;
2799                 msleep(1);
2800         }
2801         netif_err(tp, link, dev, "PHY reset failed\n");
2802 }
2803
2804 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2805 {
2806         void __iomem *ioaddr = tp->mmio_addr;
2807
2808         rtl_hw_phy_config(dev);
2809
2810         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2811                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2812                 RTL_W8(0x82, 0x01);
2813         }
2814
2815         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2816
2817         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2818                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2819
2820         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2821                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2822                 RTL_W8(0x82, 0x01);
2823                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2824                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2825         }
2826
2827         rtl8169_phy_reset(dev, tp);
2828
2829         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2830                 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2831                 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2832                 (tp->mii.supports_gmii ?
2833                         ADVERTISED_1000baseT_Half |
2834                         ADVERTISED_1000baseT_Full : 0));
2835
2836         if (RTL_R8(PHYstatus) & TBI_Enable)
2837                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2838 }
2839
2840 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2841 {
2842         void __iomem *ioaddr = tp->mmio_addr;
2843         u32 high;
2844         u32 low;
2845
2846         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2847         high = addr[4] | (addr[5] << 8);
2848
2849         spin_lock_irq(&tp->lock);
2850
2851         RTL_W8(Cfg9346, Cfg9346_Unlock);
2852
2853         RTL_W32(MAC4, high);
2854         RTL_R32(MAC4);
2855
2856         RTL_W32(MAC0, low);
2857         RTL_R32(MAC0);
2858
2859         RTL_W8(Cfg9346, Cfg9346_Lock);
2860
2861         spin_unlock_irq(&tp->lock);
2862 }
2863
2864 static int rtl_set_mac_address(struct net_device *dev, void *p)
2865 {
2866         struct rtl8169_private *tp = netdev_priv(dev);
2867         struct sockaddr *addr = p;
2868
2869         if (!is_valid_ether_addr(addr->sa_data))
2870                 return -EADDRNOTAVAIL;
2871
2872         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2873
2874         rtl_rar_set(tp, dev->dev_addr);
2875
2876         return 0;
2877 }
2878
2879 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2880 {
2881         struct rtl8169_private *tp = netdev_priv(dev);
2882         struct mii_ioctl_data *data = if_mii(ifr);
2883
2884         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2885 }
2886
2887 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2888 {
2889         switch (cmd) {
2890         case SIOCGMIIPHY:
2891                 data->phy_id = 32; /* Internal PHY */
2892                 return 0;
2893
2894         case SIOCGMIIREG:
2895                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2896                 return 0;
2897
2898         case SIOCSMIIREG:
2899                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2900                 return 0;
2901         }
2902         return -EOPNOTSUPP;
2903 }
2904
2905 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2906 {
2907         return -EOPNOTSUPP;
2908 }
2909
2910 static const struct rtl_cfg_info {
2911         void (*hw_start)(struct net_device *);
2912         unsigned int region;
2913         unsigned int align;
2914         u16 intr_event;
2915         u16 napi_event;
2916         unsigned features;
2917         u8 default_ver;
2918 } rtl_cfg_infos [] = {
2919         [RTL_CFG_0] = {
2920                 .hw_start       = rtl_hw_start_8169,
2921                 .region         = 1,
2922                 .align          = 0,
2923                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2924                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2925                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2926                 .features       = RTL_FEATURE_GMII,
2927                 .default_ver    = RTL_GIGA_MAC_VER_01,
2928         },
2929         [RTL_CFG_1] = {
2930                 .hw_start       = rtl_hw_start_8168,
2931                 .region         = 2,
2932                 .align          = 8,
2933                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2934                                   TxErr | TxOK | RxOK | RxErr,
2935                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
2936                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2937                 .default_ver    = RTL_GIGA_MAC_VER_11,
2938         },
2939         [RTL_CFG_2] = {
2940                 .hw_start       = rtl_hw_start_8101,
2941                 .region         = 2,
2942                 .align          = 8,
2943                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2944                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2945                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2946                 .features       = RTL_FEATURE_MSI,
2947                 .default_ver    = RTL_GIGA_MAC_VER_13,
2948         }
2949 };
2950
2951 /* Cfg9346_Unlock assumed. */
2952 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2953                             const struct rtl_cfg_info *cfg)
2954 {
2955         unsigned msi = 0;
2956         u8 cfg2;
2957
2958         cfg2 = RTL_R8(Config2) & ~MSIEnable;
2959         if (cfg->features & RTL_FEATURE_MSI) {
2960                 if (pci_enable_msi(pdev)) {
2961                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2962                 } else {
2963                         cfg2 |= MSIEnable;
2964                         msi = RTL_FEATURE_MSI;
2965                 }
2966         }
2967         RTL_W8(Config2, cfg2);
2968         return msi;
2969 }
2970
2971 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2972 {
2973         if (tp->features & RTL_FEATURE_MSI) {
2974                 pci_disable_msi(pdev);
2975                 tp->features &= ~RTL_FEATURE_MSI;
2976         }
2977 }
2978
2979 static const struct net_device_ops rtl8169_netdev_ops = {
2980         .ndo_open               = rtl8169_open,
2981         .ndo_stop               = rtl8169_close,
2982         .ndo_get_stats          = rtl8169_get_stats,
2983         .ndo_start_xmit         = rtl8169_start_xmit,
2984         .ndo_tx_timeout         = rtl8169_tx_timeout,
2985         .ndo_validate_addr      = eth_validate_addr,
2986         .ndo_change_mtu         = rtl8169_change_mtu,
2987         .ndo_fix_features       = rtl8169_fix_features,
2988         .ndo_set_features       = rtl8169_set_features,
2989         .ndo_set_mac_address    = rtl_set_mac_address,
2990         .ndo_do_ioctl           = rtl8169_ioctl,
2991         .ndo_set_multicast_list = rtl_set_rx_mode,
2992 #ifdef CONFIG_NET_POLL_CONTROLLER
2993         .ndo_poll_controller    = rtl8169_netpoll,
2994 #endif
2995
2996 };
2997
2998 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2999 {
3000         struct mdio_ops *ops = &tp->mdio_ops;
3001
3002         switch (tp->mac_version) {
3003         case RTL_GIGA_MAC_VER_27:
3004                 ops->write      = r8168dp_1_mdio_write;
3005                 ops->read       = r8168dp_1_mdio_read;
3006                 break;
3007         case RTL_GIGA_MAC_VER_28:
3008         case RTL_GIGA_MAC_VER_31:
3009                 ops->write      = r8168dp_2_mdio_write;
3010                 ops->read       = r8168dp_2_mdio_read;
3011                 break;
3012         default:
3013                 ops->write      = r8169_mdio_write;
3014                 ops->read       = r8169_mdio_read;
3015                 break;
3016         }
3017 }
3018
3019 static void r810x_phy_power_down(struct rtl8169_private *tp)
3020 {
3021         rtl_writephy(tp, 0x1f, 0x0000);
3022         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3023 }
3024
3025 static void r810x_phy_power_up(struct rtl8169_private *tp)
3026 {
3027         rtl_writephy(tp, 0x1f, 0x0000);
3028         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3029 }
3030
3031 static void r810x_pll_power_down(struct rtl8169_private *tp)
3032 {
3033         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3034                 rtl_writephy(tp, 0x1f, 0x0000);
3035                 rtl_writephy(tp, MII_BMCR, 0x0000);
3036                 return;
3037         }
3038
3039         r810x_phy_power_down(tp);
3040 }
3041
3042 static void r810x_pll_power_up(struct rtl8169_private *tp)
3043 {
3044         r810x_phy_power_up(tp);
3045 }
3046
3047 static void r8168_phy_power_up(struct rtl8169_private *tp)
3048 {
3049         rtl_writephy(tp, 0x1f, 0x0000);
3050         switch (tp->mac_version) {
3051         case RTL_GIGA_MAC_VER_11:
3052         case RTL_GIGA_MAC_VER_12:
3053         case RTL_GIGA_MAC_VER_17:
3054         case RTL_GIGA_MAC_VER_18:
3055         case RTL_GIGA_MAC_VER_19:
3056         case RTL_GIGA_MAC_VER_20:
3057         case RTL_GIGA_MAC_VER_21:
3058         case RTL_GIGA_MAC_VER_22:
3059         case RTL_GIGA_MAC_VER_23:
3060         case RTL_GIGA_MAC_VER_24:
3061         case RTL_GIGA_MAC_VER_25:
3062         case RTL_GIGA_MAC_VER_26:
3063         case RTL_GIGA_MAC_VER_27:
3064         case RTL_GIGA_MAC_VER_28:
3065         case RTL_GIGA_MAC_VER_31:
3066                 rtl_writephy(tp, 0x0e, 0x0000);
3067                 break;
3068         default:
3069                 break;
3070         }
3071         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3072 }
3073
3074 static void r8168_phy_power_down(struct rtl8169_private *tp)
3075 {
3076         rtl_writephy(tp, 0x1f, 0x0000);
3077         switch (tp->mac_version) {
3078         case RTL_GIGA_MAC_VER_32:
3079         case RTL_GIGA_MAC_VER_33:
3080                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3081                 break;
3082
3083         case RTL_GIGA_MAC_VER_11:
3084         case RTL_GIGA_MAC_VER_12:
3085         case RTL_GIGA_MAC_VER_17:
3086         case RTL_GIGA_MAC_VER_18:
3087         case RTL_GIGA_MAC_VER_19:
3088         case RTL_GIGA_MAC_VER_20:
3089         case RTL_GIGA_MAC_VER_21:
3090         case RTL_GIGA_MAC_VER_22:
3091         case RTL_GIGA_MAC_VER_23:
3092         case RTL_GIGA_MAC_VER_24:
3093         case RTL_GIGA_MAC_VER_25:
3094         case RTL_GIGA_MAC_VER_26:
3095         case RTL_GIGA_MAC_VER_27:
3096         case RTL_GIGA_MAC_VER_28:
3097         case RTL_GIGA_MAC_VER_31:
3098                 rtl_writephy(tp, 0x0e, 0x0200);
3099         default:
3100                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3101                 break;
3102         }
3103 }
3104
3105 static void r8168_pll_power_down(struct rtl8169_private *tp)
3106 {
3107         void __iomem *ioaddr = tp->mmio_addr;
3108
3109         if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3110              (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3111              (tp->mac_version == RTL_GIGA_MAC_VER_31)) &&
3112             r8168dp_check_dash(tp)) {
3113                 return;
3114         }
3115
3116         if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
3117              (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
3118             (RTL_R16(CPlusCmd) & ASF)) {
3119                 return;
3120         }
3121
3122         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3123             tp->mac_version == RTL_GIGA_MAC_VER_33)
3124                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3125
3126         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3127                 rtl_writephy(tp, 0x1f, 0x0000);
3128                 rtl_writephy(tp, MII_BMCR, 0x0000);
3129
3130                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3131                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3132                 return;
3133         }
3134
3135         r8168_phy_power_down(tp);
3136
3137         switch (tp->mac_version) {
3138         case RTL_GIGA_MAC_VER_25:
3139         case RTL_GIGA_MAC_VER_26:
3140         case RTL_GIGA_MAC_VER_27:
3141         case RTL_GIGA_MAC_VER_28:
3142         case RTL_GIGA_MAC_VER_31:
3143         case RTL_GIGA_MAC_VER_32:
3144         case RTL_GIGA_MAC_VER_33:
3145                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3146                 break;
3147         }
3148 }
3149
3150 static void r8168_pll_power_up(struct rtl8169_private *tp)
3151 {
3152         void __iomem *ioaddr = tp->mmio_addr;
3153
3154         if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3155              (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3156              (tp->mac_version == RTL_GIGA_MAC_VER_31)) &&
3157             r8168dp_check_dash(tp)) {
3158                 return;
3159         }
3160
3161         switch (tp->mac_version) {
3162         case RTL_GIGA_MAC_VER_25:
3163         case RTL_GIGA_MAC_VER_26:
3164         case RTL_GIGA_MAC_VER_27:
3165         case RTL_GIGA_MAC_VER_28:
3166         case RTL_GIGA_MAC_VER_31:
3167         case RTL_GIGA_MAC_VER_32:
3168         case RTL_GIGA_MAC_VER_33:
3169                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3170                 break;
3171         }
3172
3173         r8168_phy_power_up(tp);
3174 }
3175
3176 static void rtl_pll_power_op(struct rtl8169_private *tp,
3177                              void (*op)(struct rtl8169_private *))
3178 {
3179         if (op)
3180                 op(tp);
3181 }
3182
3183 static void rtl_pll_power_down(struct rtl8169_private *tp)
3184 {
3185         rtl_pll_power_op(tp, tp->pll_power_ops.down);
3186 }
3187
3188 static void rtl_pll_power_up(struct rtl8169_private *tp)
3189 {
3190         rtl_pll_power_op(tp, tp->pll_power_ops.up);
3191 }
3192
3193 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3194 {
3195         struct pll_power_ops *ops = &tp->pll_power_ops;
3196
3197         switch (tp->mac_version) {
3198         case RTL_GIGA_MAC_VER_07:
3199         case RTL_GIGA_MAC_VER_08:
3200         case RTL_GIGA_MAC_VER_09:
3201         case RTL_GIGA_MAC_VER_10:
3202         case RTL_GIGA_MAC_VER_16:
3203         case RTL_GIGA_MAC_VER_29:
3204         case RTL_GIGA_MAC_VER_30:
3205                 ops->down       = r810x_pll_power_down;
3206                 ops->up         = r810x_pll_power_up;
3207                 break;
3208
3209         case RTL_GIGA_MAC_VER_11:
3210         case RTL_GIGA_MAC_VER_12:
3211         case RTL_GIGA_MAC_VER_17:
3212         case RTL_GIGA_MAC_VER_18:
3213         case RTL_GIGA_MAC_VER_19:
3214         case RTL_GIGA_MAC_VER_20:
3215         case RTL_GIGA_MAC_VER_21:
3216         case RTL_GIGA_MAC_VER_22:
3217         case RTL_GIGA_MAC_VER_23:
3218         case RTL_GIGA_MAC_VER_24:
3219         case RTL_GIGA_MAC_VER_25:
3220         case RTL_GIGA_MAC_VER_26:
3221         case RTL_GIGA_MAC_VER_27:
3222         case RTL_GIGA_MAC_VER_28:
3223         case RTL_GIGA_MAC_VER_31:
3224         case RTL_GIGA_MAC_VER_32:
3225         case RTL_GIGA_MAC_VER_33:
3226                 ops->down       = r8168_pll_power_down;
3227                 ops->up         = r8168_pll_power_up;
3228                 break;
3229
3230         default:
3231                 ops->down       = NULL;
3232                 ops->up         = NULL;
3233                 break;
3234         }
3235 }
3236
3237 static int __devinit
3238 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3239 {
3240         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3241         const unsigned int region = cfg->region;
3242         struct rtl8169_private *tp;
3243         struct mii_if_info *mii;
3244         struct net_device *dev;
3245         void __iomem *ioaddr;
3246         int chipset, i;
3247         int rc;
3248
3249         if (netif_msg_drv(&debug)) {
3250                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3251                        MODULENAME, RTL8169_VERSION);
3252         }
3253
3254         dev = alloc_etherdev(sizeof (*tp));
3255         if (!dev) {
3256                 if (netif_msg_drv(&debug))
3257                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3258                 rc = -ENOMEM;
3259                 goto out;
3260         }
3261
3262         SET_NETDEV_DEV(dev, &pdev->dev);
3263         dev->netdev_ops = &rtl8169_netdev_ops;
3264         tp = netdev_priv(dev);
3265         tp->dev = dev;
3266         tp->pci_dev = pdev;
3267         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3268
3269         mii = &tp->mii;
3270         mii->dev = dev;
3271         mii->mdio_read = rtl_mdio_read;
3272         mii->mdio_write = rtl_mdio_write;
3273         mii->phy_id_mask = 0x1f;
3274         mii->reg_num_mask = 0x1f;
3275         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3276
3277         /* disable ASPM completely as that cause random device stop working
3278          * problems as well as full system hangs for some PCIe devices users */
3279         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3280                                      PCIE_LINK_STATE_CLKPM);
3281
3282         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3283         rc = pci_enable_device(pdev);
3284         if (rc < 0) {
3285                 netif_err(tp, probe, dev, "enable failure\n");
3286                 goto err_out_free_dev_1;
3287         }
3288
3289         if (pci_set_mwi(pdev) < 0)
3290                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3291
3292         /* make sure PCI base addr 1 is MMIO */
3293         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3294                 netif_err(tp, probe, dev,
3295                           "region #%d not an MMIO resource, aborting\n",
3296                           region);
3297                 rc = -ENODEV;
3298                 goto err_out_mwi_2;
3299         }
3300
3301         /* check for weird/broken PCI region reporting */
3302         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3303                 netif_err(tp, probe, dev,
3304                           "Invalid PCI region size(s), aborting\n");
3305                 rc = -ENODEV;
3306                 goto err_out_mwi_2;
3307         }
3308
3309         rc = pci_request_regions(pdev, MODULENAME);
3310         if (rc < 0) {
3311                 netif_err(tp, probe, dev, "could not request regions\n");
3312                 goto err_out_mwi_2;
3313         }
3314
3315         tp->cp_cmd = RxChkSum;
3316
3317         if ((sizeof(dma_addr_t) > 4) &&
3318             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3319                 tp->cp_cmd |= PCIDAC;
3320                 dev->features |= NETIF_F_HIGHDMA;
3321         } else {
3322                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3323                 if (rc < 0) {
3324                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3325                         goto err_out_free_res_3;
3326                 }
3327         }
3328
3329         /* ioremap MMIO region */
3330         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3331         if (!ioaddr) {
3332                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3333                 rc = -EIO;
3334                 goto err_out_free_res_3;
3335         }
3336
3337         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3338         if (!tp->pcie_cap)
3339                 netif_info(tp, probe, dev, "no PCI Express capability\n");
3340
3341         RTL_W16(IntrMask, 0x0000);
3342
3343         /* Soft reset the chip. */
3344         RTL_W8(ChipCmd, CmdReset);
3345
3346         /* Check that the chip has finished the reset. */
3347         for (i = 0; i < 100; i++) {
3348                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3349                         break;
3350                 msleep_interruptible(1);
3351         }
3352
3353         RTL_W16(IntrStatus, 0xffff);
3354
3355         pci_set_master(pdev);
3356
3357         /* Identify chip attached to board */
3358         rtl8169_get_mac_version(tp, ioaddr);
3359
3360         /*
3361          * Pretend we are using VLANs; This bypasses a nasty bug where
3362          * Interrupts stop flowing on high load on 8110SCd controllers.
3363          */
3364         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3365                 tp->cp_cmd |= RxVlan;
3366
3367         rtl_init_mdio_ops(tp);
3368         rtl_init_pll_power_ops(tp);
3369
3370         /* Use appropriate default if unknown */
3371         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3372                 netif_notice(tp, probe, dev,
3373                              "unknown MAC, using family default\n");
3374                 tp->mac_version = cfg->default_ver;
3375         }
3376
3377         rtl8169_print_mac_version(tp);
3378
3379         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3380                 if (tp->mac_version == rtl_chip_info[i].mac_version)
3381                         break;
3382         }
3383         if (i == ARRAY_SIZE(rtl_chip_info)) {
3384                 dev_err(&pdev->dev,
3385                         "driver bug, MAC version not found in rtl_chip_info\n");
3386                 goto err_out_msi_4;
3387         }
3388         chipset = i;
3389         tp->txd_version = rtl_chip_info[chipset].txd_version;
3390
3391         RTL_W8(Cfg9346, Cfg9346_Unlock);
3392         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3393         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3394         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3395                 tp->features |= RTL_FEATURE_WOL;
3396         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3397                 tp->features |= RTL_FEATURE_WOL;
3398         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3399         RTL_W8(Cfg9346, Cfg9346_Lock);
3400
3401         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3402             (RTL_R8(PHYstatus) & TBI_Enable)) {
3403                 tp->set_speed = rtl8169_set_speed_tbi;
3404                 tp->get_settings = rtl8169_gset_tbi;
3405                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3406                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3407                 tp->link_ok = rtl8169_tbi_link_ok;
3408                 tp->do_ioctl = rtl_tbi_ioctl;
3409
3410                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3411         } else {
3412                 tp->set_speed = rtl8169_set_speed_xmii;
3413                 tp->get_settings = rtl8169_gset_xmii;
3414                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3415                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3416                 tp->link_ok = rtl8169_xmii_link_ok;
3417                 tp->do_ioctl = rtl_xmii_ioctl;
3418         }
3419
3420         spin_lock_init(&tp->lock);
3421
3422         tp->mmio_addr = ioaddr;
3423
3424         /* Get MAC address */
3425         for (i = 0; i < MAC_ADDR_LEN; i++)
3426                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3427         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3428
3429         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3430         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3431         dev->irq = pdev->irq;
3432         dev->base_addr = (unsigned long) ioaddr;
3433
3434         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3435
3436         /* don't enable SG, IP_CSUM and TSO by default - it might not work
3437          * properly for all devices */
3438         dev->features |= NETIF_F_RXCSUM |
3439                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3440
3441         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3442                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3443         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3444                 NETIF_F_HIGHDMA;
3445
3446         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3447                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3448                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3449
3450         tp->intr_mask = 0xffff;
3451         tp->hw_start = cfg->hw_start;
3452         tp->intr_event = cfg->intr_event;
3453         tp->napi_event = cfg->napi_event;
3454
3455         init_timer(&tp->timer);
3456         tp->timer.data = (unsigned long) dev;
3457         tp->timer.function = rtl8169_phy_timer;
3458
3459         tp->fw = RTL_FIRMWARE_UNKNOWN;
3460
3461         rc = register_netdev(dev);
3462         if (rc < 0)
3463                 goto err_out_msi_4;
3464
3465         pci_set_drvdata(pdev, dev);
3466
3467         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3468                    rtl_chip_info[chipset].name, dev->base_addr, dev->dev_addr,
3469                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3470
3471         if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3472             (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3473             (tp->mac_version == RTL_GIGA_MAC_VER_31)) {
3474                 rtl8168_driver_start(tp);
3475         }
3476
3477         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3478
3479         if (pci_dev_run_wake(pdev))
3480                 pm_runtime_put_noidle(&pdev->dev);
3481
3482         netif_carrier_off(dev);
3483
3484 out:
3485         return rc;
3486
3487 err_out_msi_4:
3488         rtl_disable_msi(pdev, tp);
3489         iounmap(ioaddr);
3490 err_out_free_res_3:
3491         pci_release_regions(pdev);
3492 err_out_mwi_2:
3493         pci_clear_mwi(pdev);
3494         pci_disable_device(pdev);
3495 err_out_free_dev_1:
3496         free_netdev(dev);
3497         goto out;
3498 }
3499
3500 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3501 {
3502         struct net_device *dev = pci_get_drvdata(pdev);
3503         struct rtl8169_private *tp = netdev_priv(dev);
3504
3505         if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3506             (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3507             (tp->mac_version == RTL_GIGA_MAC_VER_31)) {
3508                 rtl8168_driver_stop(tp);
3509         }
3510
3511         cancel_delayed_work_sync(&tp->task);
3512
3513         unregister_netdev(dev);
3514
3515         rtl_release_firmware(tp);
3516
3517         if (pci_dev_run_wake(pdev))
3518                 pm_runtime_get_noresume(&pdev->dev);
3519
3520         /* restore original MAC address */
3521         rtl_rar_set(tp, dev->perm_addr);
3522
3523         rtl_disable_msi(pdev, tp);
3524         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3525         pci_set_drvdata(pdev, NULL);
3526 }
3527
3528 static void rtl_request_firmware(struct rtl8169_private *tp)
3529 {
3530         int i;
3531
3532         /* Return early if the firmware is already loaded / cached. */
3533         if (!IS_ERR(tp->fw))
3534                 goto out;
3535
3536         for (i = 0; i < ARRAY_SIZE(rtl_firmware_infos); i++) {
3537                 const struct rtl_firmware_info *info = rtl_firmware_infos + i;
3538
3539                 if (info->mac_version == tp->mac_version) {
3540                         const char *name = info->fw_name;
3541                         int rc;
3542
3543                         rc = request_firmware(&tp->fw, name, &tp->pci_dev->dev);
3544                         if (rc < 0) {
3545                                 netif_warn(tp, ifup, tp->dev, "unable to load "
3546                                         "firmware patch %s (%d)\n", name, rc);
3547                                 goto out_disable_request_firmware;
3548                         }
3549                         goto out;
3550                 }
3551         }
3552
3553 out_disable_request_firmware:
3554         tp->fw = NULL;
3555 out:
3556         return;
3557 }
3558
3559 static int rtl8169_open(struct net_device *dev)
3560 {
3561         struct rtl8169_private *tp = netdev_priv(dev);
3562         void __iomem *ioaddr = tp->mmio_addr;
3563         struct pci_dev *pdev = tp->pci_dev;
3564         int retval = -ENOMEM;
3565
3566         pm_runtime_get_sync(&pdev->dev);
3567
3568         /*
3569          * Rx and Tx desscriptors needs 256 bytes alignment.
3570          * dma_alloc_coherent provides more.
3571          */
3572         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3573                                              &tp->TxPhyAddr, GFP_KERNEL);
3574         if (!tp->TxDescArray)
3575                 goto err_pm_runtime_put;
3576
3577         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3578                                              &tp->RxPhyAddr, GFP_KERNEL);
3579         if (!tp->RxDescArray)
3580                 goto err_free_tx_0;
3581
3582         retval = rtl8169_init_ring(dev);
3583         if (retval < 0)
3584                 goto err_free_rx_1;
3585
3586         INIT_DELAYED_WORK(&tp->task, NULL);
3587
3588         smp_mb();
3589
3590         rtl_request_firmware(tp);
3591
3592         retval = request_irq(dev->irq, rtl8169_interrupt,
3593                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3594                              dev->name, dev);
3595         if (retval < 0)
3596                 goto err_release_fw_2;
3597
3598         napi_enable(&tp->napi);
3599
3600         rtl8169_init_phy(dev, tp);
3601
3602         rtl8169_set_features(dev, dev->features);
3603
3604         rtl_pll_power_up(tp);
3605
3606         rtl_hw_start(dev);
3607
3608         rtl8169_request_timer(dev);
3609
3610         tp->saved_wolopts = 0;
3611         pm_runtime_put_noidle(&pdev->dev);
3612
3613         rtl8169_check_link_status(dev, tp, ioaddr);
3614 out:
3615         return retval;
3616
3617 err_release_fw_2:
3618         rtl_release_firmware(tp);
3619         rtl8169_rx_clear(tp);
3620 err_free_rx_1:
3621         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3622                           tp->RxPhyAddr);
3623         tp->RxDescArray = NULL;
3624 err_free_tx_0:
3625         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3626                           tp->TxPhyAddr);
3627         tp->TxDescArray = NULL;
3628 err_pm_runtime_put:
3629         pm_runtime_put_noidle(&pdev->dev);
3630         goto out;
3631 }
3632
3633 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3634 {
3635         void __iomem *ioaddr = tp->mmio_addr;
3636
3637         /* Disable interrupts */
3638         rtl8169_irq_mask_and_ack(ioaddr);
3639
3640         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3641             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3642             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3643                 while (RTL_R8(TxPoll) & NPQ)
3644                         udelay(20);
3645
3646         }
3647
3648         /* Reset the chipset */
3649         RTL_W8(ChipCmd, CmdReset);
3650
3651         /* PCI commit */
3652         RTL_R8(ChipCmd);
3653 }
3654
3655 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3656 {
3657         void __iomem *ioaddr = tp->mmio_addr;
3658         u32 cfg = rtl8169_rx_config;
3659
3660         cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
3661         RTL_W32(RxConfig, cfg);
3662
3663         /* Set DMA burst size and Interframe Gap Time */
3664         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3665                 (InterFrameGap << TxInterFrameGapShift));
3666 }
3667
3668 static void rtl_hw_start(struct net_device *dev)
3669 {
3670         struct rtl8169_private *tp = netdev_priv(dev);
3671         void __iomem *ioaddr = tp->mmio_addr;
3672         unsigned int i;
3673
3674         /* Soft reset the chip. */
3675         RTL_W8(ChipCmd, CmdReset);
3676
3677         /* Check that the chip has finished the reset. */
3678         for (i = 0; i < 100; i++) {
3679                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3680                         break;
3681                 msleep_interruptible(1);
3682         }
3683
3684         tp->hw_start(dev);
3685
3686         netif_start_queue(dev);
3687 }
3688
3689
3690 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3691                                          void __iomem *ioaddr)
3692 {
3693         /*
3694          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3695          * register to be written before TxDescAddrLow to work.
3696          * Switching from MMIO to I/O access fixes the issue as well.
3697          */
3698         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3699         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3700         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3701         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3702 }
3703
3704 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3705 {
3706         u16 cmd;
3707
3708         cmd = RTL_R16(CPlusCmd);
3709         RTL_W16(CPlusCmd, cmd);
3710         return cmd;
3711 }
3712
3713 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3714 {
3715         /* Low hurts. Let's disable the filtering. */
3716         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3717 }
3718
3719 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3720 {
3721         static const struct {
3722                 u32 mac_version;
3723                 u32 clk;
3724                 u32 val;
3725         } cfg2_info [] = {
3726                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3727                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3728                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3729                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3730         }, *p = cfg2_info;
3731         unsigned int i;
3732         u32 clk;
3733
3734         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3735         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3736                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3737                         RTL_W32(0x7c, p->val);
3738                         break;
3739                 }
3740         }
3741 }
3742
3743 static void rtl_hw_start_8169(struct net_device *dev)
3744 {
3745         struct rtl8169_private *tp = netdev_priv(dev);
3746         void __iomem *ioaddr = tp->mmio_addr;
3747         struct pci_dev *pdev = tp->pci_dev;
3748
3749         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3750                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3751                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3752         }
3753
3754         RTL_W8(Cfg9346, Cfg9346_Unlock);
3755         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3756             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3757             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3758             (tp->mac_version == RTL_GIGA_MAC_VER_04))
3759                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3760
3761         RTL_W8(EarlyTxThres, NoEarlyTx);
3762
3763         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3764
3765         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3766             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3767             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3768             (tp->mac_version == RTL_GIGA_MAC_VER_04))
3769                 rtl_set_rx_tx_config_registers(tp);
3770
3771         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3772
3773         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3774             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3775                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3776                         "Bit-3 and bit-14 MUST be 1\n");
3777                 tp->cp_cmd |= (1 << 14);
3778         }
3779
3780         RTL_W16(CPlusCmd, tp->cp_cmd);
3781
3782         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3783
3784         /*
3785          * Undocumented corner. Supposedly:
3786          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3787          */
3788         RTL_W16(IntrMitigate, 0x0000);
3789
3790         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3791
3792         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3793             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3794             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3795             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3796                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3797                 rtl_set_rx_tx_config_registers(tp);
3798         }
3799
3800         RTL_W8(Cfg9346, Cfg9346_Lock);
3801
3802         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3803         RTL_R8(IntrMask);
3804
3805         RTL_W32(RxMissed, 0);
3806
3807         rtl_set_rx_mode(dev);
3808
3809         /* no early-rx interrupts */
3810         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3811
3812         /* Enable all known interrupts by setting the interrupt mask. */
3813         RTL_W16(IntrMask, tp->intr_event);
3814 }
3815
3816 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3817 {
3818         struct net_device *dev = pci_get_drvdata(pdev);
3819         struct rtl8169_private *tp = netdev_priv(dev);
3820         int cap = tp->pcie_cap;
3821
3822         if (cap) {
3823                 u16 ctl;
3824
3825                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3826                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3827                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3828         }
3829 }
3830
3831 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3832 {
3833         u32 csi;
3834
3835         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3836         rtl_csi_write(ioaddr, 0x070c, csi | bits);
3837 }
3838
3839 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3840 {
3841         rtl_csi_access_enable(ioaddr, 0x17000000);
3842 }
3843
3844 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3845 {
3846         rtl_csi_access_enable(ioaddr, 0x27000000);
3847 }
3848
3849 struct ephy_info {
3850         unsigned int offset;
3851         u16 mask;
3852         u16 bits;
3853 };
3854
3855 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3856 {
3857         u16 w;
3858
3859         while (len-- > 0) {
3860                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3861                 rtl_ephy_write(ioaddr, e->offset, w);
3862                 e++;
3863         }
3864 }
3865
3866 static void rtl_disable_clock_request(struct pci_dev *pdev)
3867 {
3868         struct net_device *dev = pci_get_drvdata(pdev);
3869         struct rtl8169_private *tp = netdev_priv(dev);
3870         int cap = tp->pcie_cap;
3871
3872         if (cap) {
3873                 u16 ctl;
3874
3875                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3876                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3877                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3878         }
3879 }
3880
3881 static void rtl_enable_clock_request(struct pci_dev *pdev)
3882 {
3883         struct net_device *dev = pci_get_drvdata(pdev);
3884         struct rtl8169_private *tp = netdev_priv(dev);
3885         int cap = tp->pcie_cap;
3886
3887         if (cap) {
3888                 u16 ctl;
3889
3890                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3891                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3892                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3893         }
3894 }
3895
3896 #define R8168_CPCMD_QUIRK_MASK (\
3897         EnableBist | \
3898         Mac_dbgo_oe | \
3899         Force_half_dup | \
3900         Force_rxflow_en | \
3901         Force_txflow_en | \
3902         Cxpl_dbg_sel | \
3903         ASF | \
3904         PktCntrDisable | \
3905         Mac_dbgo_sel)
3906
3907 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3908 {
3909         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3910
3911         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3912
3913         rtl_tx_performance_tweak(pdev,
3914                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3915 }
3916
3917 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3918 {
3919         rtl_hw_start_8168bb(ioaddr, pdev);
3920
3921         RTL_W8(MaxTxPacketSize, TxPacketMax);
3922
3923         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3924 }
3925
3926 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3927 {
3928         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3929
3930         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3931
3932         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3933
3934         rtl_disable_clock_request(pdev);
3935
3936         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3937 }
3938
3939 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3940 {
3941         static const struct ephy_info e_info_8168cp[] = {
3942                 { 0x01, 0,      0x0001 },
3943                 { 0x02, 0x0800, 0x1000 },
3944                 { 0x03, 0,      0x0042 },
3945                 { 0x06, 0x0080, 0x0000 },
3946                 { 0x07, 0,      0x2000 }
3947         };
3948
3949         rtl_csi_access_enable_2(ioaddr);
3950
3951         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3952
3953         __rtl_hw_start_8168cp(ioaddr, pdev);
3954 }
3955
3956 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3957 {
3958         rtl_csi_access_enable_2(ioaddr);
3959
3960         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3961
3962         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3963
3964         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3965 }
3966
3967 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3968 {
3969         rtl_csi_access_enable_2(ioaddr);
3970
3971         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3972
3973         /* Magic. */
3974         RTL_W8(DBG_REG, 0x20);
3975
3976         RTL_W8(MaxTxPacketSize, TxPacketMax);
3977
3978         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3979
3980         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3981 }
3982
3983 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3984 {
3985         static const struct ephy_info e_info_8168c_1[] = {
3986                 { 0x02, 0x0800, 0x1000 },
3987                 { 0x03, 0,      0x0002 },
3988                 { 0x06, 0x0080, 0x0000 }
3989         };
3990
3991         rtl_csi_access_enable_2(ioaddr);
3992
3993         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3994
3995         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3996
3997         __rtl_hw_start_8168cp(ioaddr, pdev);
3998 }
3999
4000 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4001 {
4002         static const struct ephy_info e_info_8168c_2[] = {
4003                 { 0x01, 0,      0x0001 },
4004                 { 0x03, 0x0400, 0x0220 }
4005         };
4006
4007         rtl_csi_access_enable_2(ioaddr);
4008
4009         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4010
4011         __rtl_hw_start_8168cp(ioaddr, pdev);
4012 }
4013
4014 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4015 {
4016         rtl_hw_start_8168c_2(ioaddr, pdev);
4017 }
4018
4019 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4020 {
4021         rtl_csi_access_enable_2(ioaddr);
4022
4023         __rtl_hw_start_8168cp(ioaddr, pdev);
4024 }
4025
4026 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4027 {
4028         rtl_csi_access_enable_2(ioaddr);
4029
4030         rtl_disable_clock_request(pdev);
4031
4032         RTL_W8(MaxTxPacketSize, TxPacketMax);
4033
4034         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4035
4036         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4037 }
4038
4039 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4040 {
4041         rtl_csi_access_enable_1(ioaddr);
4042
4043         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4044
4045         RTL_W8(MaxTxPacketSize, TxPacketMax);
4046
4047         rtl_disable_clock_request(pdev);
4048 }
4049
4050 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4051 {
4052         static const struct ephy_info e_info_8168d_4[] = {
4053                 { 0x0b, ~0,     0x48 },
4054                 { 0x19, 0x20,   0x50 },
4055                 { 0x0c, ~0,     0x20 }
4056         };
4057         int i;
4058
4059         rtl_csi_access_enable_1(ioaddr);
4060
4061         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4062
4063         RTL_W8(MaxTxPacketSize, TxPacketMax);
4064
4065         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4066                 const struct ephy_info *e = e_info_8168d_4 + i;
4067                 u16 w;
4068
4069                 w = rtl_ephy_read(ioaddr, e->offset);
4070                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4071         }
4072
4073         rtl_enable_clock_request(pdev);
4074 }
4075
4076 static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4077 {
4078         static const struct ephy_info e_info_8168e[] = {
4079                 { 0x00, 0x0200, 0x0100 },
4080                 { 0x00, 0x0000, 0x0004 },
4081                 { 0x06, 0x0002, 0x0001 },
4082                 { 0x06, 0x0000, 0x0030 },
4083                 { 0x07, 0x0000, 0x2000 },
4084                 { 0x00, 0x0000, 0x0020 },
4085                 { 0x03, 0x5800, 0x2000 },
4086                 { 0x03, 0x0000, 0x0001 },
4087                 { 0x01, 0x0800, 0x1000 },
4088                 { 0x07, 0x0000, 0x4000 },
4089                 { 0x1e, 0x0000, 0x2000 },
4090                 { 0x19, 0xffff, 0xfe6c },
4091                 { 0x0a, 0x0000, 0x0040 }
4092         };
4093
4094         rtl_csi_access_enable_2(ioaddr);
4095
4096         rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4097
4098         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4099
4100         RTL_W8(MaxTxPacketSize, TxPacketMax);
4101
4102         rtl_disable_clock_request(pdev);
4103
4104         /* Reset tx FIFO pointer */
4105         RTL_W32(MISC, RTL_R32(MISC) | txpla_rst);
4106         RTL_W32(MISC, RTL_R32(MISC) & ~txpla_rst);
4107
4108         RTL_W8(Config5, RTL_R8(Config5) & ~spi_en);
4109 }
4110
4111 static void rtl_hw_start_8168(struct net_device *dev)
4112 {
4113         struct rtl8169_private *tp = netdev_priv(dev);
4114         void __iomem *ioaddr = tp->mmio_addr;
4115         struct pci_dev *pdev = tp->pci_dev;
4116
4117         RTL_W8(Cfg9346, Cfg9346_Unlock);
4118
4119         RTL_W8(MaxTxPacketSize, TxPacketMax);
4120
4121         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4122
4123         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4124
4125         RTL_W16(CPlusCmd, tp->cp_cmd);
4126
4127         RTL_W16(IntrMitigate, 0x5151);
4128
4129         /* Work around for RxFIFO overflow. */
4130         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4131             tp->mac_version == RTL_GIGA_MAC_VER_22) {
4132                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4133                 tp->intr_event &= ~RxOverflow;
4134         }
4135
4136         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4137
4138         rtl_set_rx_mode(dev);
4139
4140         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4141                 (InterFrameGap << TxInterFrameGapShift));
4142
4143         RTL_R8(IntrMask);
4144
4145         switch (tp->mac_version) {
4146         case RTL_GIGA_MAC_VER_11:
4147                 rtl_hw_start_8168bb(ioaddr, pdev);
4148                 break;
4149
4150         case RTL_GIGA_MAC_VER_12:
4151         case RTL_GIGA_MAC_VER_17:
4152                 rtl_hw_start_8168bef(ioaddr, pdev);
4153                 break;
4154
4155         case RTL_GIGA_MAC_VER_18:
4156                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4157                 break;
4158
4159         case RTL_GIGA_MAC_VER_19:
4160                 rtl_hw_start_8168c_1(ioaddr, pdev);
4161                 break;
4162
4163         case RTL_GIGA_MAC_VER_20:
4164                 rtl_hw_start_8168c_2(ioaddr, pdev);
4165                 break;
4166
4167         case RTL_GIGA_MAC_VER_21:
4168                 rtl_hw_start_8168c_3(ioaddr, pdev);
4169                 break;
4170
4171         case RTL_GIGA_MAC_VER_22:
4172                 rtl_hw_start_8168c_4(ioaddr, pdev);
4173                 break;
4174
4175         case RTL_GIGA_MAC_VER_23:
4176                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4177                 break;
4178
4179         case RTL_GIGA_MAC_VER_24:
4180                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4181                 break;
4182
4183         case RTL_GIGA_MAC_VER_25:
4184         case RTL_GIGA_MAC_VER_26:
4185         case RTL_GIGA_MAC_VER_27:
4186                 rtl_hw_start_8168d(ioaddr, pdev);
4187                 break;
4188
4189         case RTL_GIGA_MAC_VER_28:
4190                 rtl_hw_start_8168d_4(ioaddr, pdev);
4191                 break;
4192         case RTL_GIGA_MAC_VER_31:
4193                 rtl_hw_start_8168dp(ioaddr, pdev);
4194                 break;
4195
4196         case RTL_GIGA_MAC_VER_32:
4197         case RTL_GIGA_MAC_VER_33:
4198                 rtl_hw_start_8168e(ioaddr, pdev);
4199                 break;
4200
4201         default:
4202                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4203                         dev->name, tp->mac_version);
4204                 break;
4205         }
4206
4207         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4208
4209         RTL_W8(Cfg9346, Cfg9346_Lock);
4210
4211         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4212
4213         RTL_W16(IntrMask, tp->intr_event);
4214 }
4215
4216 #define R810X_CPCMD_QUIRK_MASK (\
4217         EnableBist | \
4218         Mac_dbgo_oe | \
4219         Force_half_dup | \
4220         Force_rxflow_en | \
4221         Force_txflow_en | \
4222         Cxpl_dbg_sel | \
4223         ASF | \
4224         PktCntrDisable | \
4225         Mac_dbgo_sel)
4226
4227 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4228 {
4229         static const struct ephy_info e_info_8102e_1[] = {
4230                 { 0x01, 0, 0x6e65 },
4231                 { 0x02, 0, 0x091f },
4232                 { 0x03, 0, 0xc2f9 },
4233                 { 0x06, 0, 0xafb5 },
4234                 { 0x07, 0, 0x0e00 },
4235                 { 0x19, 0, 0xec80 },
4236                 { 0x01, 0, 0x2e65 },
4237                 { 0x01, 0, 0x6e65 }
4238         };
4239         u8 cfg1;
4240
4241         rtl_csi_access_enable_2(ioaddr);
4242
4243         RTL_W8(DBG_REG, FIX_NAK_1);
4244
4245         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4246
4247         RTL_W8(Config1,
4248                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4249         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4250
4251         cfg1 = RTL_R8(Config1);
4252         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4253                 RTL_W8(Config1, cfg1 & ~LEDS0);
4254
4255         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4256 }
4257
4258 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4259 {
4260         rtl_csi_access_enable_2(ioaddr);
4261
4262         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4263
4264         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4265         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4266 }
4267
4268 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4269 {
4270         rtl_hw_start_8102e_2(ioaddr, pdev);
4271
4272         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4273 }
4274
4275 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4276 {
4277         static const struct ephy_info e_info_8105e_1[] = {
4278                 { 0x07, 0, 0x4000 },
4279                 { 0x19, 0, 0x0200 },
4280                 { 0x19, 0, 0x0020 },
4281                 { 0x1e, 0, 0x2000 },
4282                 { 0x03, 0, 0x0001 },
4283                 { 0x19, 0, 0x0100 },
4284                 { 0x19, 0, 0x0004 },
4285                 { 0x0a, 0, 0x0020 }
4286         };
4287
4288         /* Force LAN exit from ASPM if Rx/Tx are not idel */
4289         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4290
4291         /* disable Early Tally Counter */
4292         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4293
4294         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4295         RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4296
4297         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4298 }
4299
4300 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4301 {
4302         rtl_hw_start_8105e_1(ioaddr, pdev);
4303         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4304 }
4305
4306 static void rtl_hw_start_8101(struct net_device *dev)
4307 {
4308         struct rtl8169_private *tp = netdev_priv(dev);
4309         void __iomem *ioaddr = tp->mmio_addr;
4310         struct pci_dev *pdev = tp->pci_dev;
4311
4312         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
4313             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
4314                 int cap = tp->pcie_cap;
4315
4316                 if (cap) {
4317                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4318                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4319                 }
4320         }
4321
4322         RTL_W8(Cfg9346, Cfg9346_Unlock);
4323
4324         switch (tp->mac_version) {
4325         case RTL_GIGA_MAC_VER_07:
4326                 rtl_hw_start_8102e_1(ioaddr, pdev);
4327                 break;
4328
4329         case RTL_GIGA_MAC_VER_08:
4330                 rtl_hw_start_8102e_3(ioaddr, pdev);
4331                 break;
4332
4333         case RTL_GIGA_MAC_VER_09:
4334                 rtl_hw_start_8102e_2(ioaddr, pdev);
4335                 break;
4336
4337         case RTL_GIGA_MAC_VER_29:
4338                 rtl_hw_start_8105e_1(ioaddr, pdev);
4339                 break;
4340         case RTL_GIGA_MAC_VER_30:
4341                 rtl_hw_start_8105e_2(ioaddr, pdev);
4342                 break;
4343         }
4344
4345         RTL_W8(Cfg9346, Cfg9346_Lock);
4346
4347         RTL_W8(MaxTxPacketSize, TxPacketMax);
4348
4349         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4350
4351         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4352         RTL_W16(CPlusCmd, tp->cp_cmd);
4353
4354         RTL_W16(IntrMitigate, 0x0000);
4355
4356         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4357
4358         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4359         rtl_set_rx_tx_config_registers(tp);
4360
4361         RTL_R8(IntrMask);
4362
4363         rtl_set_rx_mode(dev);
4364
4365         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4366
4367         RTL_W16(IntrMask, tp->intr_event);
4368 }
4369
4370 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4371 {
4372         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4373                 return -EINVAL;
4374
4375         dev->mtu = new_mtu;
4376         netdev_update_features(dev);
4377
4378         return 0;
4379 }
4380
4381 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4382 {
4383         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4384         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4385 }
4386
4387 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4388                                      void **data_buff, struct RxDesc *desc)
4389 {
4390         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4391                          DMA_FROM_DEVICE);
4392
4393         kfree(*data_buff);
4394         *data_buff = NULL;
4395         rtl8169_make_unusable_by_asic(desc);
4396 }
4397
4398 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4399 {
4400         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4401
4402         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4403 }
4404
4405 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4406                                        u32 rx_buf_sz)
4407 {
4408         desc->addr = cpu_to_le64(mapping);
4409         wmb();
4410         rtl8169_mark_to_asic(desc, rx_buf_sz);
4411 }
4412
4413 static inline void *rtl8169_align(void *data)
4414 {
4415         return (void *)ALIGN((long)data, 16);
4416 }
4417
4418 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4419                                              struct RxDesc *desc)
4420 {
4421         void *data;
4422         dma_addr_t mapping;
4423         struct device *d = &tp->pci_dev->dev;
4424         struct net_device *dev = tp->dev;
4425         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4426
4427         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4428         if (!data)
4429                 return NULL;
4430
4431         if (rtl8169_align(data) != data) {
4432                 kfree(data);
4433                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4434                 if (!data)
4435                         return NULL;
4436         }
4437
4438         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4439                                  DMA_FROM_DEVICE);
4440         if (unlikely(dma_mapping_error(d, mapping))) {
4441                 if (net_ratelimit())
4442                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4443                 goto err_out;
4444         }
4445
4446         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4447         return data;
4448
4449 err_out:
4450         kfree(data);
4451         return NULL;
4452 }
4453
4454 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4455 {
4456         unsigned int i;
4457
4458         for (i = 0; i < NUM_RX_DESC; i++) {
4459                 if (tp->Rx_databuff[i]) {
4460                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4461                                             tp->RxDescArray + i);
4462                 }
4463         }
4464 }
4465
4466 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4467 {
4468         desc->opts1 |= cpu_to_le32(RingEnd);
4469 }
4470
4471 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4472 {
4473         unsigned int i;
4474
4475         for (i = 0; i < NUM_RX_DESC; i++) {
4476                 void *data;
4477
4478                 if (tp->Rx_databuff[i])
4479                         continue;
4480
4481                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4482                 if (!data) {
4483                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4484                         goto err_out;
4485                 }
4486                 tp->Rx_databuff[i] = data;
4487         }
4488
4489         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4490         return 0;
4491
4492 err_out:
4493         rtl8169_rx_clear(tp);
4494         return -ENOMEM;
4495 }
4496
4497 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4498 {
4499         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4500 }
4501
4502 static int rtl8169_init_ring(struct net_device *dev)
4503 {
4504         struct rtl8169_private *tp = netdev_priv(dev);
4505
4506         rtl8169_init_ring_indexes(tp);
4507
4508         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4509         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4510
4511         return rtl8169_rx_fill(tp);
4512 }
4513
4514 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4515                                  struct TxDesc *desc)
4516 {
4517         unsigned int len = tx_skb->len;
4518
4519         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4520
4521         desc->opts1 = 0x00;
4522         desc->opts2 = 0x00;
4523         desc->addr = 0x00;
4524         tx_skb->len = 0;
4525 }
4526
4527 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4528                                    unsigned int n)
4529 {
4530         unsigned int i;
4531
4532         for (i = 0; i < n; i++) {
4533                 unsigned int entry = (start + i) % NUM_TX_DESC;
4534                 struct ring_info *tx_skb = tp->tx_skb + entry;
4535                 unsigned int len = tx_skb->len;
4536
4537                 if (len) {
4538                         struct sk_buff *skb = tx_skb->skb;
4539
4540                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4541                                              tp->TxDescArray + entry);
4542                         if (skb) {
4543                                 tp->dev->stats.tx_dropped++;
4544                                 dev_kfree_skb(skb);
4545                                 tx_skb->skb = NULL;
4546                         }
4547                 }
4548         }
4549 }
4550
4551 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4552 {
4553         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4554         tp->cur_tx = tp->dirty_tx = 0;
4555 }
4556
4557 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4558 {
4559         struct rtl8169_private *tp = netdev_priv(dev);
4560
4561         PREPARE_DELAYED_WORK(&tp->task, task);
4562         schedule_delayed_work(&tp->task, 4);
4563 }
4564
4565 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4566 {
4567         struct rtl8169_private *tp = netdev_priv(dev);
4568         void __iomem *ioaddr = tp->mmio_addr;
4569
4570         synchronize_irq(dev->irq);
4571
4572         /* Wait for any pending NAPI task to complete */
4573         napi_disable(&tp->napi);
4574
4575         rtl8169_irq_mask_and_ack(ioaddr);
4576
4577         tp->intr_mask = 0xffff;
4578         RTL_W16(IntrMask, tp->intr_event);
4579         napi_enable(&tp->napi);
4580 }
4581
4582 static void rtl8169_reinit_task(struct work_struct *work)
4583 {
4584         struct rtl8169_private *tp =
4585                 container_of(work, struct rtl8169_private, task.work);
4586         struct net_device *dev = tp->dev;
4587         int ret;
4588
4589         rtnl_lock();
4590
4591         if (!netif_running(dev))
4592                 goto out_unlock;
4593
4594         rtl8169_wait_for_quiescence(dev);
4595         rtl8169_close(dev);
4596
4597         ret = rtl8169_open(dev);
4598         if (unlikely(ret < 0)) {
4599                 if (net_ratelimit())
4600                         netif_err(tp, drv, dev,
4601                                   "reinit failure (status = %d). Rescheduling\n",
4602                                   ret);
4603                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4604         }
4605
4606 out_unlock:
4607         rtnl_unlock();
4608 }
4609
4610 static void rtl8169_reset_task(struct work_struct *work)
4611 {
4612         struct rtl8169_private *tp =
4613                 container_of(work, struct rtl8169_private, task.work);
4614         struct net_device *dev = tp->dev;
4615
4616         rtnl_lock();
4617
4618         if (!netif_running(dev))
4619                 goto out_unlock;
4620
4621         rtl8169_wait_for_quiescence(dev);
4622
4623         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4624         rtl8169_tx_clear(tp);
4625
4626         if (tp->dirty_rx == tp->cur_rx) {
4627                 rtl8169_init_ring_indexes(tp);
4628                 rtl_hw_start(dev);
4629                 netif_wake_queue(dev);
4630                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4631         } else {
4632                 if (net_ratelimit())
4633                         netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4634                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4635         }
4636
4637 out_unlock:
4638         rtnl_unlock();
4639 }
4640
4641 static void rtl8169_tx_timeout(struct net_device *dev)
4642 {
4643         struct rtl8169_private *tp = netdev_priv(dev);
4644
4645         rtl8169_hw_reset(tp);
4646
4647         /* Let's wait a bit while any (async) irq lands on */
4648         rtl8169_schedule_work(dev, rtl8169_reset_task);
4649 }
4650
4651 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4652                               u32 *opts)
4653 {
4654         struct skb_shared_info *info = skb_shinfo(skb);
4655         unsigned int cur_frag, entry;
4656         struct TxDesc * uninitialized_var(txd);
4657         struct device *d = &tp->pci_dev->dev;
4658
4659         entry = tp->cur_tx;
4660         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4661                 skb_frag_t *frag = info->frags + cur_frag;
4662                 dma_addr_t mapping;
4663                 u32 status, len;
4664                 void *addr;
4665
4666                 entry = (entry + 1) % NUM_TX_DESC;
4667
4668                 txd = tp->TxDescArray + entry;
4669                 len = frag->size;
4670                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4671                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4672                 if (unlikely(dma_mapping_error(d, mapping))) {
4673                         if (net_ratelimit())
4674                                 netif_err(tp, drv, tp->dev,
4675                                           "Failed to map TX fragments DMA!\n");
4676                         goto err_out;
4677                 }
4678
4679                 /* anti gcc 2.95.3 bugware (sic) */
4680                 status = opts[0] | len |
4681                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
4682
4683                 txd->opts1 = cpu_to_le32(status);
4684                 txd->opts2 = cpu_to_le32(opts[1]);
4685                 txd->addr = cpu_to_le64(mapping);
4686
4687                 tp->tx_skb[entry].len = len;
4688         }
4689
4690         if (cur_frag) {
4691                 tp->tx_skb[entry].skb = skb;
4692                 txd->opts1 |= cpu_to_le32(LastFrag);
4693         }
4694
4695         return cur_frag;
4696
4697 err_out:
4698         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4699         return -EIO;
4700 }
4701
4702 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4703                                     struct sk_buff *skb, u32 *opts)
4704 {
4705         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
4706         u32 mss = skb_shinfo(skb)->gso_size;
4707         int offset = info->opts_offset;
4708
4709         if (mss) {
4710                 opts[0] |= TD_LSO;
4711                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4712         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4713                 const struct iphdr *ip = ip_hdr(skb);
4714
4715                 if (ip->protocol == IPPROTO_TCP)
4716                         opts[offset] |= info->checksum.tcp;
4717                 else if (ip->protocol == IPPROTO_UDP)
4718                         opts[offset] |= info->checksum.udp;
4719                 else
4720                         WARN_ON_ONCE(1);
4721         }
4722 }
4723
4724 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4725                                       struct net_device *dev)
4726 {
4727         struct rtl8169_private *tp = netdev_priv(dev);
4728         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4729         struct TxDesc *txd = tp->TxDescArray + entry;
4730         void __iomem *ioaddr = tp->mmio_addr;
4731         struct device *d = &tp->pci_dev->dev;
4732         dma_addr_t mapping;
4733         u32 status, len;
4734         u32 opts[2];
4735         int frags;
4736
4737         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4738                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4739                 goto err_stop_0;
4740         }
4741
4742         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4743                 goto err_stop_0;
4744
4745         len = skb_headlen(skb);
4746         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4747         if (unlikely(dma_mapping_error(d, mapping))) {
4748                 if (net_ratelimit())
4749                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4750                 goto err_dma_0;
4751         }
4752
4753         tp->tx_skb[entry].len = len;
4754         txd->addr = cpu_to_le64(mapping);
4755
4756         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4757         opts[0] = DescOwn;
4758
4759         rtl8169_tso_csum(tp, skb, opts);
4760
4761         frags = rtl8169_xmit_frags(tp, skb, opts);
4762         if (frags < 0)
4763                 goto err_dma_1;
4764         else if (frags)
4765                 opts[0] |= FirstFrag;
4766         else {
4767                 opts[0] |= FirstFrag | LastFrag;
4768                 tp->tx_skb[entry].skb = skb;
4769         }
4770
4771         txd->opts2 = cpu_to_le32(opts[1]);
4772
4773         wmb();
4774
4775         /* anti gcc 2.95.3 bugware (sic) */
4776         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4777         txd->opts1 = cpu_to_le32(status);
4778
4779         tp->cur_tx += frags + 1;
4780
4781         wmb();
4782
4783         RTL_W8(TxPoll, NPQ);    /* set polling bit */
4784
4785         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4786                 netif_stop_queue(dev);
4787                 smp_rmb();
4788                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4789                         netif_wake_queue(dev);
4790         }
4791
4792         return NETDEV_TX_OK;
4793
4794 err_dma_1:
4795         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4796 err_dma_0:
4797         dev_kfree_skb(skb);
4798         dev->stats.tx_dropped++;
4799         return NETDEV_TX_OK;
4800
4801 err_stop_0:
4802         netif_stop_queue(dev);
4803         dev->stats.tx_dropped++;
4804         return NETDEV_TX_BUSY;
4805 }
4806
4807 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4808 {
4809         struct rtl8169_private *tp = netdev_priv(dev);
4810         struct pci_dev *pdev = tp->pci_dev;
4811         u16 pci_status, pci_cmd;
4812
4813         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4814         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4815
4816         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4817                   pci_cmd, pci_status);
4818
4819         /*
4820          * The recovery sequence below admits a very elaborated explanation:
4821          * - it seems to work;
4822          * - I did not see what else could be done;
4823          * - it makes iop3xx happy.
4824          *
4825          * Feel free to adjust to your needs.
4826          */
4827         if (pdev->broken_parity_status)
4828                 pci_cmd &= ~PCI_COMMAND_PARITY;
4829         else
4830                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4831
4832         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4833
4834         pci_write_config_word(pdev, PCI_STATUS,
4835                 pci_status & (PCI_STATUS_DETECTED_PARITY |
4836                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4837                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4838
4839         /* The infamous DAC f*ckup only happens at boot time */
4840         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4841                 void __iomem *ioaddr = tp->mmio_addr;
4842
4843                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4844                 tp->cp_cmd &= ~PCIDAC;
4845                 RTL_W16(CPlusCmd, tp->cp_cmd);
4846                 dev->features &= ~NETIF_F_HIGHDMA;
4847         }
4848
4849         rtl8169_hw_reset(tp);
4850
4851         rtl8169_schedule_work(dev, rtl8169_reinit_task);
4852 }
4853
4854 static void rtl8169_tx_interrupt(struct net_device *dev,
4855                                  struct rtl8169_private *tp,
4856                                  void __iomem *ioaddr)
4857 {
4858         unsigned int dirty_tx, tx_left;
4859
4860         dirty_tx = tp->dirty_tx;
4861         smp_rmb();
4862         tx_left = tp->cur_tx - dirty_tx;
4863
4864         while (tx_left > 0) {
4865                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4866                 struct ring_info *tx_skb = tp->tx_skb + entry;
4867                 u32 status;
4868
4869                 rmb();
4870                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4871                 if (status & DescOwn)
4872                         break;
4873
4874                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4875                                      tp->TxDescArray + entry);
4876                 if (status & LastFrag) {
4877                         dev->stats.tx_packets++;
4878                         dev->stats.tx_bytes += tx_skb->skb->len;
4879                         dev_kfree_skb(tx_skb->skb);
4880                         tx_skb->skb = NULL;
4881                 }
4882                 dirty_tx++;
4883                 tx_left--;
4884         }
4885
4886         if (tp->dirty_tx != dirty_tx) {
4887                 tp->dirty_tx = dirty_tx;
4888                 smp_wmb();
4889                 if (netif_queue_stopped(dev) &&
4890                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4891                         netif_wake_queue(dev);
4892                 }
4893                 /*
4894                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4895                  * too close. Let's kick an extra TxPoll request when a burst
4896                  * of start_xmit activity is detected (if it is not detected,
4897                  * it is slow enough). -- FR
4898                  */
4899                 smp_rmb();
4900                 if (tp->cur_tx != dirty_tx)
4901                         RTL_W8(TxPoll, NPQ);
4902         }
4903 }
4904
4905 static inline int rtl8169_fragmented_frame(u32 status)
4906 {
4907         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4908 }
4909
4910 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4911 {
4912         u32 status = opts1 & RxProtoMask;
4913
4914         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4915             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4916                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4917         else
4918                 skb_checksum_none_assert(skb);
4919 }
4920
4921 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4922                                            struct rtl8169_private *tp,
4923                                            int pkt_size,
4924                                            dma_addr_t addr)
4925 {
4926         struct sk_buff *skb;
4927         struct device *d = &tp->pci_dev->dev;
4928
4929         data = rtl8169_align(data);
4930         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4931         prefetch(data);
4932         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4933         if (skb)
4934                 memcpy(skb->data, data, pkt_size);
4935         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4936
4937         return skb;
4938 }
4939
4940 /*
4941  * Warning : rtl8169_rx_interrupt() might be called :
4942  * 1) from NAPI (softirq) context
4943  *      (polling = 1 : we should call netif_receive_skb())
4944  * 2) from process context (rtl8169_reset_task())
4945  *      (polling = 0 : we must call netif_rx() instead)
4946  */
4947 static int rtl8169_rx_interrupt(struct net_device *dev,
4948                                 struct rtl8169_private *tp,
4949                                 void __iomem *ioaddr, u32 budget)
4950 {
4951         unsigned int cur_rx, rx_left;
4952         unsigned int count;
4953         int polling = (budget != ~(u32)0) ? 1 : 0;
4954
4955         cur_rx = tp->cur_rx;
4956         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4957         rx_left = min(rx_left, budget);
4958
4959         for (; rx_left > 0; rx_left--, cur_rx++) {
4960                 unsigned int entry = cur_rx % NUM_RX_DESC;
4961                 struct RxDesc *desc = tp->RxDescArray + entry;
4962                 u32 status;
4963
4964                 rmb();
4965                 status = le32_to_cpu(desc->opts1);
4966
4967                 if (status & DescOwn)
4968                         break;
4969                 if (unlikely(status & RxRES)) {
4970                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4971                                    status);
4972                         dev->stats.rx_errors++;
4973                         if (status & (RxRWT | RxRUNT))
4974                                 dev->stats.rx_length_errors++;
4975                         if (status & RxCRC)
4976                                 dev->stats.rx_crc_errors++;
4977                         if (status & RxFOVF) {
4978                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4979                                 dev->stats.rx_fifo_errors++;
4980                         }
4981                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4982                 } else {
4983                         struct sk_buff *skb;
4984                         dma_addr_t addr = le64_to_cpu(desc->addr);
4985                         int pkt_size = (status & 0x00001FFF) - 4;
4986
4987                         /*
4988                          * The driver does not support incoming fragmented
4989                          * frames. They are seen as a symptom of over-mtu
4990                          * sized frames.
4991                          */
4992                         if (unlikely(rtl8169_fragmented_frame(status))) {
4993                                 dev->stats.rx_dropped++;
4994                                 dev->stats.rx_length_errors++;
4995                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
4996                                 continue;
4997                         }
4998
4999                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5000                                                   tp, pkt_size, addr);
5001                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5002                         if (!skb) {
5003                                 dev->stats.rx_dropped++;
5004                                 continue;
5005                         }
5006
5007                         rtl8169_rx_csum(skb, status);
5008                         skb_put(skb, pkt_size);
5009                         skb->protocol = eth_type_trans(skb, dev);
5010
5011                         rtl8169_rx_vlan_tag(desc, skb);
5012
5013                         if (likely(polling))
5014                                 napi_gro_receive(&tp->napi, skb);
5015                         else
5016                                 netif_rx(skb);
5017
5018                         dev->stats.rx_bytes += pkt_size;
5019                         dev->stats.rx_packets++;
5020                 }
5021
5022                 /* Work around for AMD plateform. */
5023                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5024                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5025                         desc->opts2 = 0;
5026                         cur_rx++;
5027                 }
5028         }
5029
5030         count = cur_rx - tp->cur_rx;
5031         tp->cur_rx = cur_rx;
5032
5033         tp->dirty_rx += count;
5034
5035         return count;
5036 }
5037
5038 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5039 {
5040         struct net_device *dev = dev_instance;
5041         struct rtl8169_private *tp = netdev_priv(dev);
5042         void __iomem *ioaddr = tp->mmio_addr;
5043         int handled = 0;
5044         int status;
5045
5046         /* loop handling interrupts until we have no new ones or
5047          * we hit a invalid/hotplug case.
5048          */
5049         status = RTL_R16(IntrStatus);
5050         while (status && status != 0xffff) {
5051                 handled = 1;
5052
5053                 /* Handle all of the error cases first. These will reset
5054                  * the chip, so just exit the loop.
5055                  */
5056                 if (unlikely(!netif_running(dev))) {
5057                         rtl8169_asic_down(ioaddr);
5058                         break;
5059                 }
5060
5061                 if (unlikely(status & RxFIFOOver)) {
5062                         switch (tp->mac_version) {
5063                         /* Work around for rx fifo overflow */
5064                         case RTL_GIGA_MAC_VER_11:
5065                         case RTL_GIGA_MAC_VER_22:
5066                         case RTL_GIGA_MAC_VER_26:
5067                                 netif_stop_queue(dev);
5068                                 rtl8169_tx_timeout(dev);
5069                                 goto done;
5070                         /* Testers needed. */
5071                         case RTL_GIGA_MAC_VER_17:
5072                         case RTL_GIGA_MAC_VER_19:
5073                         case RTL_GIGA_MAC_VER_20:
5074                         case RTL_GIGA_MAC_VER_21:
5075                         case RTL_GIGA_MAC_VER_23:
5076                         case RTL_GIGA_MAC_VER_24:
5077                         case RTL_GIGA_MAC_VER_27:
5078                         case RTL_GIGA_MAC_VER_28:
5079                         case RTL_GIGA_MAC_VER_31:
5080                         /* Experimental science. Pktgen proof. */
5081                         case RTL_GIGA_MAC_VER_12:
5082                         case RTL_GIGA_MAC_VER_25:
5083                                 if (status == RxFIFOOver)
5084                                         goto done;
5085                                 break;
5086                         default:
5087                                 break;
5088                         }
5089                 }
5090
5091                 if (unlikely(status & SYSErr)) {
5092                         rtl8169_pcierr_interrupt(dev);
5093                         break;
5094                 }
5095
5096                 if (status & LinkChg)
5097                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5098
5099                 /* We need to see the lastest version of tp->intr_mask to
5100                  * avoid ignoring an MSI interrupt and having to wait for
5101                  * another event which may never come.
5102                  */
5103                 smp_rmb();
5104                 if (status & tp->intr_mask & tp->napi_event) {
5105                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5106                         tp->intr_mask = ~tp->napi_event;
5107
5108                         if (likely(napi_schedule_prep(&tp->napi)))
5109                                 __napi_schedule(&tp->napi);
5110                         else
5111                                 netif_info(tp, intr, dev,
5112                                            "interrupt %04x in poll\n", status);
5113                 }
5114
5115                 /* We only get a new MSI interrupt when all active irq
5116                  * sources on the chip have been acknowledged. So, ack
5117                  * everything we've seen and check if new sources have become
5118                  * active to avoid blocking all interrupts from the chip.
5119                  */
5120                 RTL_W16(IntrStatus,
5121                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5122                 status = RTL_R16(IntrStatus);
5123         }
5124 done:
5125         return IRQ_RETVAL(handled);
5126 }
5127
5128 static int rtl8169_poll(struct napi_struct *napi, int budget)
5129 {
5130         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5131         struct net_device *dev = tp->dev;
5132         void __iomem *ioaddr = tp->mmio_addr;
5133         int work_done;
5134
5135         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5136         rtl8169_tx_interrupt(dev, tp, ioaddr);
5137
5138         if (work_done < budget) {
5139                 napi_complete(napi);
5140
5141                 /* We need for force the visibility of tp->intr_mask
5142                  * for other CPUs, as we can loose an MSI interrupt
5143                  * and potentially wait for a retransmit timeout if we don't.
5144                  * The posted write to IntrMask is safe, as it will
5145                  * eventually make it to the chip and we won't loose anything
5146                  * until it does.
5147                  */
5148                 tp->intr_mask = 0xffff;
5149                 wmb();
5150                 RTL_W16(IntrMask, tp->intr_event);
5151         }
5152
5153         return work_done;
5154 }
5155
5156 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5157 {
5158         struct rtl8169_private *tp = netdev_priv(dev);
5159
5160         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5161                 return;
5162
5163         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5164         RTL_W32(RxMissed, 0);
5165 }
5166
5167 static void rtl8169_down(struct net_device *dev)
5168 {
5169         struct rtl8169_private *tp = netdev_priv(dev);
5170         void __iomem *ioaddr = tp->mmio_addr;
5171
5172         rtl8169_delete_timer(dev);
5173
5174         netif_stop_queue(dev);
5175
5176         napi_disable(&tp->napi);
5177
5178         spin_lock_irq(&tp->lock);
5179
5180         rtl8169_asic_down(ioaddr);
5181         /*
5182          * At this point device interrupts can not be enabled in any function,
5183          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5184          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5185          */
5186         rtl8169_rx_missed(dev, ioaddr);
5187
5188         spin_unlock_irq(&tp->lock);
5189
5190         synchronize_irq(dev->irq);
5191
5192         /* Give a racing hard_start_xmit a few cycles to complete. */
5193         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5194
5195         rtl8169_tx_clear(tp);
5196
5197         rtl8169_rx_clear(tp);
5198
5199         rtl_pll_power_down(tp);
5200 }
5201
5202 static int rtl8169_close(struct net_device *dev)
5203 {
5204         struct rtl8169_private *tp = netdev_priv(dev);
5205         struct pci_dev *pdev = tp->pci_dev;
5206
5207         pm_runtime_get_sync(&pdev->dev);
5208
5209         /* update counters before going down */
5210         rtl8169_update_counters(dev);
5211
5212         rtl8169_down(dev);
5213
5214         free_irq(dev->irq, dev);
5215
5216         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5217                           tp->RxPhyAddr);
5218         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5219                           tp->TxPhyAddr);
5220         tp->TxDescArray = NULL;
5221         tp->RxDescArray = NULL;
5222
5223         pm_runtime_put_sync(&pdev->dev);
5224
5225         return 0;
5226 }
5227
5228 static void rtl_set_rx_mode(struct net_device *dev)
5229 {
5230         struct rtl8169_private *tp = netdev_priv(dev);
5231         void __iomem *ioaddr = tp->mmio_addr;
5232         unsigned long flags;
5233         u32 mc_filter[2];       /* Multicast hash filter */
5234         int rx_mode;
5235         u32 tmp = 0;
5236
5237         if (dev->flags & IFF_PROMISC) {
5238                 /* Unconditionally log net taps. */
5239                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5240                 rx_mode =
5241                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5242                     AcceptAllPhys;
5243                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5244         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5245                    (dev->flags & IFF_ALLMULTI)) {
5246                 /* Too many to filter perfectly -- accept all multicasts. */
5247                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5248                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5249         } else {
5250                 struct netdev_hw_addr *ha;
5251
5252                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5253                 mc_filter[1] = mc_filter[0] = 0;
5254                 netdev_for_each_mc_addr(ha, dev) {
5255                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5256                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5257                         rx_mode |= AcceptMulticast;
5258                 }
5259         }
5260
5261         spin_lock_irqsave(&tp->lock, flags);
5262
5263         tmp = rtl8169_rx_config | rx_mode |
5264               (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
5265
5266         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5267                 u32 data = mc_filter[0];
5268
5269                 mc_filter[0] = swab32(mc_filter[1]);
5270                 mc_filter[1] = swab32(data);
5271         }
5272
5273         RTL_W32(MAR0 + 4, mc_filter[1]);
5274         RTL_W32(MAR0 + 0, mc_filter[0]);
5275
5276         RTL_W32(RxConfig, tmp);
5277
5278         spin_unlock_irqrestore(&tp->lock, flags);
5279 }
5280
5281 /**
5282  *  rtl8169_get_stats - Get rtl8169 read/write statistics
5283  *  @dev: The Ethernet Device to get statistics for
5284  *
5285  *  Get TX/RX statistics for rtl8169
5286  */
5287 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5288 {
5289         struct rtl8169_private *tp = netdev_priv(dev);
5290         void __iomem *ioaddr = tp->mmio_addr;
5291         unsigned long flags;
5292
5293         if (netif_running(dev)) {
5294                 spin_lock_irqsave(&tp->lock, flags);
5295                 rtl8169_rx_missed(dev, ioaddr);
5296                 spin_unlock_irqrestore(&tp->lock, flags);
5297         }
5298
5299         return &dev->stats;
5300 }
5301
5302 static void rtl8169_net_suspend(struct net_device *dev)
5303 {
5304         struct rtl8169_private *tp = netdev_priv(dev);
5305
5306         if (!netif_running(dev))
5307                 return;
5308
5309         rtl_pll_power_down(tp);
5310
5311         netif_device_detach(dev);
5312         netif_stop_queue(dev);
5313 }
5314
5315 #ifdef CONFIG_PM
5316
5317 static int rtl8169_suspend(struct device *device)
5318 {
5319         struct pci_dev *pdev = to_pci_dev(device);
5320         struct net_device *dev = pci_get_drvdata(pdev);
5321
5322         rtl8169_net_suspend(dev);
5323
5324         return 0;
5325 }
5326
5327 static void __rtl8169_resume(struct net_device *dev)
5328 {
5329         struct rtl8169_private *tp = netdev_priv(dev);
5330
5331         netif_device_attach(dev);
5332
5333         rtl_pll_power_up(tp);
5334
5335         rtl8169_schedule_work(dev, rtl8169_reset_task);
5336 }
5337
5338 static int rtl8169_resume(struct device *device)
5339 {
5340         struct pci_dev *pdev = to_pci_dev(device);
5341         struct net_device *dev = pci_get_drvdata(pdev);
5342         struct rtl8169_private *tp = netdev_priv(dev);
5343
5344         rtl8169_init_phy(dev, tp);
5345
5346         if (netif_running(dev))
5347                 __rtl8169_resume(dev);
5348
5349         return 0;
5350 }
5351
5352 static int rtl8169_runtime_suspend(struct device *device)
5353 {
5354         struct pci_dev *pdev = to_pci_dev(device);
5355         struct net_device *dev = pci_get_drvdata(pdev);
5356         struct rtl8169_private *tp = netdev_priv(dev);
5357
5358         if (!tp->TxDescArray)
5359                 return 0;
5360
5361         spin_lock_irq(&tp->lock);
5362         tp->saved_wolopts = __rtl8169_get_wol(tp);
5363         __rtl8169_set_wol(tp, WAKE_ANY);
5364         spin_unlock_irq(&tp->lock);
5365
5366         rtl8169_net_suspend(dev);
5367
5368         return 0;
5369 }
5370
5371 static int rtl8169_runtime_resume(struct device *device)
5372 {
5373         struct pci_dev *pdev = to_pci_dev(device);
5374         struct net_device *dev = pci_get_drvdata(pdev);
5375         struct rtl8169_private *tp = netdev_priv(dev);
5376
5377         if (!tp->TxDescArray)
5378                 return 0;
5379
5380         spin_lock_irq(&tp->lock);
5381         __rtl8169_set_wol(tp, tp->saved_wolopts);
5382         tp->saved_wolopts = 0;
5383         spin_unlock_irq(&tp->lock);
5384
5385         rtl8169_init_phy(dev, tp);
5386
5387         __rtl8169_resume(dev);
5388
5389         return 0;
5390 }
5391
5392 static int rtl8169_runtime_idle(struct device *device)
5393 {
5394         struct pci_dev *pdev = to_pci_dev(device);
5395         struct net_device *dev = pci_get_drvdata(pdev);
5396         struct rtl8169_private *tp = netdev_priv(dev);
5397
5398         return tp->TxDescArray ? -EBUSY : 0;
5399 }
5400
5401 static const struct dev_pm_ops rtl8169_pm_ops = {
5402         .suspend = rtl8169_suspend,
5403         .resume = rtl8169_resume,
5404         .freeze = rtl8169_suspend,
5405         .thaw = rtl8169_resume,
5406         .poweroff = rtl8169_suspend,
5407         .restore = rtl8169_resume,
5408         .runtime_suspend = rtl8169_runtime_suspend,
5409         .runtime_resume = rtl8169_runtime_resume,
5410         .runtime_idle = rtl8169_runtime_idle,
5411 };
5412
5413 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5414
5415 #else /* !CONFIG_PM */
5416
5417 #define RTL8169_PM_OPS  NULL
5418
5419 #endif /* !CONFIG_PM */
5420
5421 static void rtl_shutdown(struct pci_dev *pdev)
5422 {
5423         struct net_device *dev = pci_get_drvdata(pdev);
5424         struct rtl8169_private *tp = netdev_priv(dev);
5425         void __iomem *ioaddr = tp->mmio_addr;
5426
5427         rtl8169_net_suspend(dev);
5428
5429         /* restore original MAC address */
5430         rtl_rar_set(tp, dev->perm_addr);
5431
5432         spin_lock_irq(&tp->lock);
5433
5434         rtl8169_asic_down(ioaddr);
5435
5436         spin_unlock_irq(&tp->lock);
5437
5438         if (system_state == SYSTEM_POWER_OFF) {
5439                 /* WoL fails with some 8168 when the receiver is disabled. */
5440                 if (tp->features & RTL_FEATURE_WOL) {
5441                         pci_clear_master(pdev);
5442
5443                         RTL_W8(ChipCmd, CmdRxEnb);
5444                         /* PCI commit */
5445                         RTL_R8(ChipCmd);
5446                 }
5447
5448                 pci_wake_from_d3(pdev, true);
5449                 pci_set_power_state(pdev, PCI_D3hot);
5450         }
5451 }
5452
5453 static struct pci_driver rtl8169_pci_driver = {
5454         .name           = MODULENAME,
5455         .id_table       = rtl8169_pci_tbl,
5456         .probe          = rtl8169_init_one,
5457         .remove         = __devexit_p(rtl8169_remove_one),
5458         .shutdown       = rtl_shutdown,
5459         .driver.pm      = RTL8169_PM_OPS,
5460 };
5461
5462 static int __init rtl8169_init_module(void)
5463 {
5464         return pci_register_driver(&rtl8169_pci_driver);
5465 }
5466
5467 static void __exit rtl8169_cleanup_module(void)
5468 {
5469         pci_unregister_driver(&rtl8169_pci_driver);
5470 }
5471
5472 module_init(rtl8169_init_module);
5473 module_exit(rtl8169_cleanup_module);