c1bb24cf07938e6541eddeed9ba4273854b09ab8
[linux-2.6.git] / drivers / net / r8169.c
1 /*
2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3  *
4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6  * Copyright (c) a lot of people too. Please respect their work.
7  *
8  * See MAINTAINERS file for support contact information.
9  */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26
27 #include <asm/system.h>
28 #include <asm/io.h>
29 #include <asm/irq.h>
30
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
34
35 #ifdef RTL8169_DEBUG
36 #define assert(expr) \
37         if (!(expr)) {                                  \
38                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39                 #expr,__FILE__,__func__,__LINE__);              \
40         }
41 #define dprintk(fmt, args...) \
42         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
43 #else
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...)   do {} while (0)
46 #endif /* RTL8169_DEBUG */
47
48 #define R8169_MSG_DEFAULT \
49         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
50
51 #define TX_BUFFS_AVAIL(tp) \
52         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
54 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
55    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
56 static const int multicast_filter_limit = 32;
57
58 /* MAC address length */
59 #define MAC_ADDR_LEN    6
60
61 #define MAX_READ_REQUEST_SHIFT  12
62 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
63 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
64 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
65 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
66 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
67 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
68
69 #define R8169_REGS_SIZE         256
70 #define R8169_NAPI_WEIGHT       64
71 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
72 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
73 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
74 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
75 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
76
77 #define RTL8169_TX_TIMEOUT      (6*HZ)
78 #define RTL8169_PHY_TIMEOUT     (10*HZ)
79
80 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
81 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
82 #define RTL_EEPROM_SIG_ADDR     0x0000
83
84 /* write/read MMIO register */
85 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
86 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
87 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
88 #define RTL_R8(reg)             readb (ioaddr + (reg))
89 #define RTL_R16(reg)            readw (ioaddr + (reg))
90 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
91
92 enum mac_version {
93         RTL_GIGA_MAC_NONE   = 0x00,
94         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
95         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
96         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
97         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
98         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
99         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
100         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
101         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
102         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
103         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
104         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
105         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
106         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
107         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
108         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
109         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
110         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
111         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
112         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
113         RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
114         RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
115         RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
116         RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
117         RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
118         RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
119         RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
120         RTL_GIGA_MAC_VER_27 = 0x1b  // 8168DP
121 };
122
123 #define _R(NAME,MAC,MASK) \
124         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
125
126 static const struct {
127         const char *name;
128         u8 mac_version;
129         u32 RxConfigMask;       /* Clears the bits supported by this chip */
130 } rtl_chip_info[] = {
131         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
132         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
133         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
134         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
135         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
136         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
137         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
138         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
139         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
140         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
141         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
142         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
143         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
144         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
145         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
146         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
147         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
148         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
149         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
150         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
151         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
152         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
153         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
154         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
155         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
156         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
157         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_27, 0xff7e1880)  // PCI-E
158 };
159 #undef _R
160
161 enum cfg_version {
162         RTL_CFG_0 = 0x00,
163         RTL_CFG_1,
164         RTL_CFG_2
165 };
166
167 static void rtl_hw_start_8169(struct net_device *);
168 static void rtl_hw_start_8168(struct net_device *);
169 static void rtl_hw_start_8101(struct net_device *);
170
171 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
172         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
173         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
174         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
175         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
176         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
177         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
178         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
179         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
180         { PCI_VENDOR_ID_LINKSYS,                0x1032,
181                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
182         { 0x0001,                               0x8168,
183                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
184         {0,},
185 };
186
187 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
188
189 static int rx_copybreak = 200;
190 static int use_dac;
191 static struct {
192         u32 msg_enable;
193 } debug = { -1 };
194
195 enum rtl_registers {
196         MAC0            = 0,    /* Ethernet hardware address. */
197         MAC4            = 4,
198         MAR0            = 8,    /* Multicast filter. */
199         CounterAddrLow          = 0x10,
200         CounterAddrHigh         = 0x14,
201         TxDescStartAddrLow      = 0x20,
202         TxDescStartAddrHigh     = 0x24,
203         TxHDescStartAddrLow     = 0x28,
204         TxHDescStartAddrHigh    = 0x2c,
205         FLASH           = 0x30,
206         ERSR            = 0x36,
207         ChipCmd         = 0x37,
208         TxPoll          = 0x38,
209         IntrMask        = 0x3c,
210         IntrStatus      = 0x3e,
211         TxConfig        = 0x40,
212         RxConfig        = 0x44,
213         RxMissed        = 0x4c,
214         Cfg9346         = 0x50,
215         Config0         = 0x51,
216         Config1         = 0x52,
217         Config2         = 0x53,
218         Config3         = 0x54,
219         Config4         = 0x55,
220         Config5         = 0x56,
221         MultiIntr       = 0x5c,
222         PHYAR           = 0x60,
223         PHYstatus       = 0x6c,
224         RxMaxSize       = 0xda,
225         CPlusCmd        = 0xe0,
226         IntrMitigate    = 0xe2,
227         RxDescAddrLow   = 0xe4,
228         RxDescAddrHigh  = 0xe8,
229         EarlyTxThres    = 0xec,
230         FuncEvent       = 0xf0,
231         FuncEventMask   = 0xf4,
232         FuncPresetState = 0xf8,
233         FuncForceEvent  = 0xfc,
234 };
235
236 enum rtl8110_registers {
237         TBICSR                  = 0x64,
238         TBI_ANAR                = 0x68,
239         TBI_LPAR                = 0x6a,
240 };
241
242 enum rtl8168_8101_registers {
243         CSIDR                   = 0x64,
244         CSIAR                   = 0x68,
245 #define CSIAR_FLAG                      0x80000000
246 #define CSIAR_WRITE_CMD                 0x80000000
247 #define CSIAR_BYTE_ENABLE               0x0f
248 #define CSIAR_BYTE_ENABLE_SHIFT         12
249 #define CSIAR_ADDR_MASK                 0x0fff
250
251         EPHYAR                  = 0x80,
252 #define EPHYAR_FLAG                     0x80000000
253 #define EPHYAR_WRITE_CMD                0x80000000
254 #define EPHYAR_REG_MASK                 0x1f
255 #define EPHYAR_REG_SHIFT                16
256 #define EPHYAR_DATA_MASK                0xffff
257         DBG_REG                 = 0xd1,
258 #define FIX_NAK_1                       (1 << 4)
259 #define FIX_NAK_2                       (1 << 3)
260         EFUSEAR                 = 0xdc,
261 #define EFUSEAR_FLAG                    0x80000000
262 #define EFUSEAR_WRITE_CMD               0x80000000
263 #define EFUSEAR_READ_CMD                0x00000000
264 #define EFUSEAR_REG_MASK                0x03ff
265 #define EFUSEAR_REG_SHIFT               8
266 #define EFUSEAR_DATA_MASK               0xff
267 };
268
269 enum rtl_register_content {
270         /* InterruptStatusBits */
271         SYSErr          = 0x8000,
272         PCSTimeout      = 0x4000,
273         SWInt           = 0x0100,
274         TxDescUnavail   = 0x0080,
275         RxFIFOOver      = 0x0040,
276         LinkChg         = 0x0020,
277         RxOverflow      = 0x0010,
278         TxErr           = 0x0008,
279         TxOK            = 0x0004,
280         RxErr           = 0x0002,
281         RxOK            = 0x0001,
282
283         /* RxStatusDesc */
284         RxFOVF  = (1 << 23),
285         RxRWT   = (1 << 22),
286         RxRES   = (1 << 21),
287         RxRUNT  = (1 << 20),
288         RxCRC   = (1 << 19),
289
290         /* ChipCmdBits */
291         CmdReset        = 0x10,
292         CmdRxEnb        = 0x08,
293         CmdTxEnb        = 0x04,
294         RxBufEmpty      = 0x01,
295
296         /* TXPoll register p.5 */
297         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
298         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
299         FSWInt          = 0x01,         /* Forced software interrupt */
300
301         /* Cfg9346Bits */
302         Cfg9346_Lock    = 0x00,
303         Cfg9346_Unlock  = 0xc0,
304
305         /* rx_mode_bits */
306         AcceptErr       = 0x20,
307         AcceptRunt      = 0x10,
308         AcceptBroadcast = 0x08,
309         AcceptMulticast = 0x04,
310         AcceptMyPhys    = 0x02,
311         AcceptAllPhys   = 0x01,
312
313         /* RxConfigBits */
314         RxCfgFIFOShift  = 13,
315         RxCfgDMAShift   =  8,
316
317         /* TxConfigBits */
318         TxInterFrameGapShift = 24,
319         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
320
321         /* Config1 register p.24 */
322         LEDS1           = (1 << 7),
323         LEDS0           = (1 << 6),
324         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
325         Speed_down      = (1 << 4),
326         MEMMAP          = (1 << 3),
327         IOMAP           = (1 << 2),
328         VPD             = (1 << 1),
329         PMEnable        = (1 << 0),     /* Power Management Enable */
330
331         /* Config2 register p. 25 */
332         PCI_Clock_66MHz = 0x01,
333         PCI_Clock_33MHz = 0x00,
334
335         /* Config3 register p.25 */
336         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
337         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
338         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
339
340         /* Config5 register p.27 */
341         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
342         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
343         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
344         LanWake         = (1 << 1),     /* LanWake enable/disable */
345         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
346
347         /* TBICSR p.28 */
348         TBIReset        = 0x80000000,
349         TBILoopback     = 0x40000000,
350         TBINwEnable     = 0x20000000,
351         TBINwRestart    = 0x10000000,
352         TBILinkOk       = 0x02000000,
353         TBINwComplete   = 0x01000000,
354
355         /* CPlusCmd p.31 */
356         EnableBist      = (1 << 15),    // 8168 8101
357         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
358         Normal_mode     = (1 << 13),    // unused
359         Force_half_dup  = (1 << 12),    // 8168 8101
360         Force_rxflow_en = (1 << 11),    // 8168 8101
361         Force_txflow_en = (1 << 10),    // 8168 8101
362         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
363         ASF             = (1 << 8),     // 8168 8101
364         PktCntrDisable  = (1 << 7),     // 8168 8101
365         Mac_dbgo_sel    = 0x001c,       // 8168
366         RxVlan          = (1 << 6),
367         RxChkSum        = (1 << 5),
368         PCIDAC          = (1 << 4),
369         PCIMulRW        = (1 << 3),
370         INTT_0          = 0x0000,       // 8168
371         INTT_1          = 0x0001,       // 8168
372         INTT_2          = 0x0002,       // 8168
373         INTT_3          = 0x0003,       // 8168
374
375         /* rtl8169_PHYstatus */
376         TBI_Enable      = 0x80,
377         TxFlowCtrl      = 0x40,
378         RxFlowCtrl      = 0x20,
379         _1000bpsF       = 0x10,
380         _100bps         = 0x08,
381         _10bps          = 0x04,
382         LinkStatus      = 0x02,
383         FullDup         = 0x01,
384
385         /* _TBICSRBit */
386         TBILinkOK       = 0x02000000,
387
388         /* DumpCounterCommand */
389         CounterDump     = 0x8,
390 };
391
392 enum desc_status_bit {
393         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
394         RingEnd         = (1 << 30), /* End of descriptor ring */
395         FirstFrag       = (1 << 29), /* First segment of a packet */
396         LastFrag        = (1 << 28), /* Final segment of a packet */
397
398         /* Tx private */
399         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
400         MSSShift        = 16,        /* MSS value position */
401         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
402         IPCS            = (1 << 18), /* Calculate IP checksum */
403         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
404         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
405         TxVlanTag       = (1 << 17), /* Add VLAN tag */
406
407         /* Rx private */
408         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
409         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
410
411 #define RxProtoUDP      (PID1)
412 #define RxProtoTCP      (PID0)
413 #define RxProtoIP       (PID1 | PID0)
414 #define RxProtoMask     RxProtoIP
415
416         IPFail          = (1 << 16), /* IP checksum failed */
417         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
418         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
419         RxVlanTag       = (1 << 16), /* VLAN tag available */
420 };
421
422 #define RsvdMask        0x3fffc000
423
424 struct TxDesc {
425         __le32 opts1;
426         __le32 opts2;
427         __le64 addr;
428 };
429
430 struct RxDesc {
431         __le32 opts1;
432         __le32 opts2;
433         __le64 addr;
434 };
435
436 struct ring_info {
437         struct sk_buff  *skb;
438         u32             len;
439         u8              __pad[sizeof(void *) - sizeof(u32)];
440 };
441
442 enum features {
443         RTL_FEATURE_WOL         = (1 << 0),
444         RTL_FEATURE_MSI         = (1 << 1),
445         RTL_FEATURE_GMII        = (1 << 2),
446 };
447
448 struct rtl8169_counters {
449         __le64  tx_packets;
450         __le64  rx_packets;
451         __le64  tx_errors;
452         __le32  rx_errors;
453         __le16  rx_missed;
454         __le16  align_errors;
455         __le32  tx_one_collision;
456         __le32  tx_multi_collision;
457         __le64  rx_unicast;
458         __le64  rx_broadcast;
459         __le32  rx_multicast;
460         __le16  tx_aborted;
461         __le16  tx_underun;
462 };
463
464 struct rtl8169_private {
465         void __iomem *mmio_addr;        /* memory map physical address */
466         struct pci_dev *pci_dev;        /* Index of PCI device */
467         struct net_device *dev;
468         struct napi_struct napi;
469         spinlock_t lock;                /* spin lock flag */
470         u32 msg_enable;
471         int chipset;
472         int mac_version;
473         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
474         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
475         u32 dirty_rx;
476         u32 dirty_tx;
477         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
478         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
479         dma_addr_t TxPhyAddr;
480         dma_addr_t RxPhyAddr;
481         struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
482         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
483         unsigned align;
484         unsigned rx_buf_sz;
485         struct timer_list timer;
486         u16 cp_cmd;
487         u16 intr_event;
488         u16 napi_event;
489         u16 intr_mask;
490         int phy_1000_ctrl_reg;
491 #ifdef CONFIG_R8169_VLAN
492         struct vlan_group *vlgrp;
493 #endif
494         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
495         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
496         void (*phy_reset_enable)(void __iomem *);
497         void (*hw_start)(struct net_device *);
498         unsigned int (*phy_reset_pending)(void __iomem *);
499         unsigned int (*link_ok)(void __iomem *);
500         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
501         int pcie_cap;
502         struct delayed_work task;
503         unsigned features;
504
505         struct mii_if_info mii;
506         struct rtl8169_counters counters;
507 };
508
509 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
510 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
511 module_param(rx_copybreak, int, 0);
512 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
513 module_param(use_dac, int, 0);
514 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
515 module_param_named(debug, debug.msg_enable, int, 0);
516 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
517 MODULE_LICENSE("GPL");
518 MODULE_VERSION(RTL8169_VERSION);
519
520 static int rtl8169_open(struct net_device *dev);
521 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
522                                       struct net_device *dev);
523 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
524 static int rtl8169_init_ring(struct net_device *dev);
525 static void rtl_hw_start(struct net_device *dev);
526 static int rtl8169_close(struct net_device *dev);
527 static void rtl_set_rx_mode(struct net_device *dev);
528 static void rtl8169_tx_timeout(struct net_device *dev);
529 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
530 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
531                                 void __iomem *, u32 budget);
532 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
533 static void rtl8169_down(struct net_device *dev);
534 static void rtl8169_rx_clear(struct rtl8169_private *tp);
535 static int rtl8169_poll(struct napi_struct *napi, int budget);
536
537 static const unsigned int rtl8169_rx_config =
538         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
539
540 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
541 {
542         int i;
543
544         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
545
546         for (i = 20; i > 0; i--) {
547                 /*
548                  * Check if the RTL8169 has completed writing to the specified
549                  * MII register.
550                  */
551                 if (!(RTL_R32(PHYAR) & 0x80000000))
552                         break;
553                 udelay(25);
554         }
555 }
556
557 static int mdio_read(void __iomem *ioaddr, int reg_addr)
558 {
559         int i, value = -1;
560
561         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
562
563         for (i = 20; i > 0; i--) {
564                 /*
565                  * Check if the RTL8169 has completed retrieving data from
566                  * the specified MII register.
567                  */
568                 if (RTL_R32(PHYAR) & 0x80000000) {
569                         value = RTL_R32(PHYAR) & 0xffff;
570                         break;
571                 }
572                 udelay(25);
573         }
574         return value;
575 }
576
577 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
578 {
579         mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
580 }
581
582 static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
583 {
584         int val;
585
586         val = mdio_read(ioaddr, reg_addr);
587         mdio_write(ioaddr, reg_addr, (val | p) & ~m);
588 }
589
590 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
591                            int val)
592 {
593         struct rtl8169_private *tp = netdev_priv(dev);
594         void __iomem *ioaddr = tp->mmio_addr;
595
596         mdio_write(ioaddr, location, val);
597 }
598
599 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
600 {
601         struct rtl8169_private *tp = netdev_priv(dev);
602         void __iomem *ioaddr = tp->mmio_addr;
603
604         return mdio_read(ioaddr, location);
605 }
606
607 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
608 {
609         unsigned int i;
610
611         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
612                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
613
614         for (i = 0; i < 100; i++) {
615                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
616                         break;
617                 udelay(10);
618         }
619 }
620
621 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
622 {
623         u16 value = 0xffff;
624         unsigned int i;
625
626         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
627
628         for (i = 0; i < 100; i++) {
629                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
630                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
631                         break;
632                 }
633                 udelay(10);
634         }
635
636         return value;
637 }
638
639 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
640 {
641         unsigned int i;
642
643         RTL_W32(CSIDR, value);
644         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
645                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
646
647         for (i = 0; i < 100; i++) {
648                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
649                         break;
650                 udelay(10);
651         }
652 }
653
654 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
655 {
656         u32 value = ~0x00;
657         unsigned int i;
658
659         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
660                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
661
662         for (i = 0; i < 100; i++) {
663                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
664                         value = RTL_R32(CSIDR);
665                         break;
666                 }
667                 udelay(10);
668         }
669
670         return value;
671 }
672
673 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
674 {
675         u8 value = 0xff;
676         unsigned int i;
677
678         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
679
680         for (i = 0; i < 300; i++) {
681                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
682                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
683                         break;
684                 }
685                 udelay(100);
686         }
687
688         return value;
689 }
690
691 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
692 {
693         RTL_W16(IntrMask, 0x0000);
694
695         RTL_W16(IntrStatus, 0xffff);
696 }
697
698 static void rtl8169_asic_down(void __iomem *ioaddr)
699 {
700         RTL_W8(ChipCmd, 0x00);
701         rtl8169_irq_mask_and_ack(ioaddr);
702         RTL_R16(CPlusCmd);
703 }
704
705 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
706 {
707         return RTL_R32(TBICSR) & TBIReset;
708 }
709
710 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
711 {
712         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
713 }
714
715 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
716 {
717         return RTL_R32(TBICSR) & TBILinkOk;
718 }
719
720 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
721 {
722         return RTL_R8(PHYstatus) & LinkStatus;
723 }
724
725 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
726 {
727         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
728 }
729
730 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
731 {
732         unsigned int val;
733
734         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
735         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
736 }
737
738 static void rtl8169_check_link_status(struct net_device *dev,
739                                       struct rtl8169_private *tp,
740                                       void __iomem *ioaddr)
741 {
742         unsigned long flags;
743
744         spin_lock_irqsave(&tp->lock, flags);
745         if (tp->link_ok(ioaddr)) {
746                 netif_carrier_on(dev);
747                 if (netif_msg_ifup(tp))
748                         printk(KERN_INFO PFX "%s: link up\n", dev->name);
749         } else {
750                 if (netif_msg_ifdown(tp))
751                         printk(KERN_INFO PFX "%s: link down\n", dev->name);
752                 netif_carrier_off(dev);
753         }
754         spin_unlock_irqrestore(&tp->lock, flags);
755 }
756
757 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
758 {
759         struct rtl8169_private *tp = netdev_priv(dev);
760         void __iomem *ioaddr = tp->mmio_addr;
761         u8 options;
762
763         wol->wolopts = 0;
764
765 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
766         wol->supported = WAKE_ANY;
767
768         spin_lock_irq(&tp->lock);
769
770         options = RTL_R8(Config1);
771         if (!(options & PMEnable))
772                 goto out_unlock;
773
774         options = RTL_R8(Config3);
775         if (options & LinkUp)
776                 wol->wolopts |= WAKE_PHY;
777         if (options & MagicPacket)
778                 wol->wolopts |= WAKE_MAGIC;
779
780         options = RTL_R8(Config5);
781         if (options & UWF)
782                 wol->wolopts |= WAKE_UCAST;
783         if (options & BWF)
784                 wol->wolopts |= WAKE_BCAST;
785         if (options & MWF)
786                 wol->wolopts |= WAKE_MCAST;
787
788 out_unlock:
789         spin_unlock_irq(&tp->lock);
790 }
791
792 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
793 {
794         struct rtl8169_private *tp = netdev_priv(dev);
795         void __iomem *ioaddr = tp->mmio_addr;
796         unsigned int i;
797         static const struct {
798                 u32 opt;
799                 u16 reg;
800                 u8  mask;
801         } cfg[] = {
802                 { WAKE_ANY,   Config1, PMEnable },
803                 { WAKE_PHY,   Config3, LinkUp },
804                 { WAKE_MAGIC, Config3, MagicPacket },
805                 { WAKE_UCAST, Config5, UWF },
806                 { WAKE_BCAST, Config5, BWF },
807                 { WAKE_MCAST, Config5, MWF },
808                 { WAKE_ANY,   Config5, LanWake }
809         };
810
811         spin_lock_irq(&tp->lock);
812
813         RTL_W8(Cfg9346, Cfg9346_Unlock);
814
815         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
816                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
817                 if (wol->wolopts & cfg[i].opt)
818                         options |= cfg[i].mask;
819                 RTL_W8(cfg[i].reg, options);
820         }
821
822         RTL_W8(Cfg9346, Cfg9346_Lock);
823
824         if (wol->wolopts)
825                 tp->features |= RTL_FEATURE_WOL;
826         else
827                 tp->features &= ~RTL_FEATURE_WOL;
828         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
829
830         spin_unlock_irq(&tp->lock);
831
832         return 0;
833 }
834
835 static void rtl8169_get_drvinfo(struct net_device *dev,
836                                 struct ethtool_drvinfo *info)
837 {
838         struct rtl8169_private *tp = netdev_priv(dev);
839
840         strcpy(info->driver, MODULENAME);
841         strcpy(info->version, RTL8169_VERSION);
842         strcpy(info->bus_info, pci_name(tp->pci_dev));
843 }
844
845 static int rtl8169_get_regs_len(struct net_device *dev)
846 {
847         return R8169_REGS_SIZE;
848 }
849
850 static int rtl8169_set_speed_tbi(struct net_device *dev,
851                                  u8 autoneg, u16 speed, u8 duplex)
852 {
853         struct rtl8169_private *tp = netdev_priv(dev);
854         void __iomem *ioaddr = tp->mmio_addr;
855         int ret = 0;
856         u32 reg;
857
858         reg = RTL_R32(TBICSR);
859         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
860             (duplex == DUPLEX_FULL)) {
861                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
862         } else if (autoneg == AUTONEG_ENABLE)
863                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
864         else {
865                 if (netif_msg_link(tp)) {
866                         printk(KERN_WARNING "%s: "
867                                "incorrect speed setting refused in TBI mode\n",
868                                dev->name);
869                 }
870                 ret = -EOPNOTSUPP;
871         }
872
873         return ret;
874 }
875
876 static int rtl8169_set_speed_xmii(struct net_device *dev,
877                                   u8 autoneg, u16 speed, u8 duplex)
878 {
879         struct rtl8169_private *tp = netdev_priv(dev);
880         void __iomem *ioaddr = tp->mmio_addr;
881         int giga_ctrl, bmcr;
882
883         if (autoneg == AUTONEG_ENABLE) {
884                 int auto_nego;
885
886                 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
887                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
888                               ADVERTISE_100HALF | ADVERTISE_100FULL);
889                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
890
891                 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
892                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
893
894                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
895                 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
896                     (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
897                     (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
898                     (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
899                     (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
900                     (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
901                     (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
902                     (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
903                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
904                 } else if (netif_msg_link(tp)) {
905                         printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
906                                dev->name);
907                 }
908
909                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
910
911                 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
912                     (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
913                     (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
914                         /*
915                          * Wake up the PHY.
916                          * Vendor specific (0x1f) and reserved (0x0e) MII
917                          * registers.
918                          */
919                         mdio_write(ioaddr, 0x1f, 0x0000);
920                         mdio_write(ioaddr, 0x0e, 0x0000);
921                 }
922
923                 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
924                 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
925         } else {
926                 giga_ctrl = 0;
927
928                 if (speed == SPEED_10)
929                         bmcr = 0;
930                 else if (speed == SPEED_100)
931                         bmcr = BMCR_SPEED100;
932                 else
933                         return -EINVAL;
934
935                 if (duplex == DUPLEX_FULL)
936                         bmcr |= BMCR_FULLDPLX;
937
938                 mdio_write(ioaddr, 0x1f, 0x0000);
939         }
940
941         tp->phy_1000_ctrl_reg = giga_ctrl;
942
943         mdio_write(ioaddr, MII_BMCR, bmcr);
944
945         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
946             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
947                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
948                         mdio_write(ioaddr, 0x17, 0x2138);
949                         mdio_write(ioaddr, 0x0e, 0x0260);
950                 } else {
951                         mdio_write(ioaddr, 0x17, 0x2108);
952                         mdio_write(ioaddr, 0x0e, 0x0000);
953                 }
954         }
955
956         return 0;
957 }
958
959 static int rtl8169_set_speed(struct net_device *dev,
960                              u8 autoneg, u16 speed, u8 duplex)
961 {
962         struct rtl8169_private *tp = netdev_priv(dev);
963         int ret;
964
965         ret = tp->set_speed(dev, autoneg, speed, duplex);
966
967         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
968                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
969
970         return ret;
971 }
972
973 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
974 {
975         struct rtl8169_private *tp = netdev_priv(dev);
976         unsigned long flags;
977         int ret;
978
979         spin_lock_irqsave(&tp->lock, flags);
980         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
981         spin_unlock_irqrestore(&tp->lock, flags);
982
983         return ret;
984 }
985
986 static u32 rtl8169_get_rx_csum(struct net_device *dev)
987 {
988         struct rtl8169_private *tp = netdev_priv(dev);
989
990         return tp->cp_cmd & RxChkSum;
991 }
992
993 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
994 {
995         struct rtl8169_private *tp = netdev_priv(dev);
996         void __iomem *ioaddr = tp->mmio_addr;
997         unsigned long flags;
998
999         spin_lock_irqsave(&tp->lock, flags);
1000
1001         if (data)
1002                 tp->cp_cmd |= RxChkSum;
1003         else
1004                 tp->cp_cmd &= ~RxChkSum;
1005
1006         RTL_W16(CPlusCmd, tp->cp_cmd);
1007         RTL_R16(CPlusCmd);
1008
1009         spin_unlock_irqrestore(&tp->lock, flags);
1010
1011         return 0;
1012 }
1013
1014 #ifdef CONFIG_R8169_VLAN
1015
1016 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1017                                       struct sk_buff *skb)
1018 {
1019         return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
1020                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1021 }
1022
1023 static void rtl8169_vlan_rx_register(struct net_device *dev,
1024                                      struct vlan_group *grp)
1025 {
1026         struct rtl8169_private *tp = netdev_priv(dev);
1027         void __iomem *ioaddr = tp->mmio_addr;
1028         unsigned long flags;
1029
1030         spin_lock_irqsave(&tp->lock, flags);
1031         tp->vlgrp = grp;
1032         /*
1033          * Do not disable RxVlan on 8110SCd.
1034          */
1035         if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1036                 tp->cp_cmd |= RxVlan;
1037         else
1038                 tp->cp_cmd &= ~RxVlan;
1039         RTL_W16(CPlusCmd, tp->cp_cmd);
1040         RTL_R16(CPlusCmd);
1041         spin_unlock_irqrestore(&tp->lock, flags);
1042 }
1043
1044 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1045                                struct sk_buff *skb)
1046 {
1047         u32 opts2 = le32_to_cpu(desc->opts2);
1048         struct vlan_group *vlgrp = tp->vlgrp;
1049         int ret;
1050
1051         if (vlgrp && (opts2 & RxVlanTag)) {
1052                 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1053                 ret = 0;
1054         } else
1055                 ret = -1;
1056         desc->opts2 = 0;
1057         return ret;
1058 }
1059
1060 #else /* !CONFIG_R8169_VLAN */
1061
1062 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1063                                       struct sk_buff *skb)
1064 {
1065         return 0;
1066 }
1067
1068 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1069                                struct sk_buff *skb)
1070 {
1071         return -1;
1072 }
1073
1074 #endif
1075
1076 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1077 {
1078         struct rtl8169_private *tp = netdev_priv(dev);
1079         void __iomem *ioaddr = tp->mmio_addr;
1080         u32 status;
1081
1082         cmd->supported =
1083                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1084         cmd->port = PORT_FIBRE;
1085         cmd->transceiver = XCVR_INTERNAL;
1086
1087         status = RTL_R32(TBICSR);
1088         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1089         cmd->autoneg = !!(status & TBINwEnable);
1090
1091         cmd->speed = SPEED_1000;
1092         cmd->duplex = DUPLEX_FULL; /* Always set */
1093
1094         return 0;
1095 }
1096
1097 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1098 {
1099         struct rtl8169_private *tp = netdev_priv(dev);
1100
1101         return mii_ethtool_gset(&tp->mii, cmd);
1102 }
1103
1104 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1105 {
1106         struct rtl8169_private *tp = netdev_priv(dev);
1107         unsigned long flags;
1108         int rc;
1109
1110         spin_lock_irqsave(&tp->lock, flags);
1111
1112         rc = tp->get_settings(dev, cmd);
1113
1114         spin_unlock_irqrestore(&tp->lock, flags);
1115         return rc;
1116 }
1117
1118 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1119                              void *p)
1120 {
1121         struct rtl8169_private *tp = netdev_priv(dev);
1122         unsigned long flags;
1123
1124         if (regs->len > R8169_REGS_SIZE)
1125                 regs->len = R8169_REGS_SIZE;
1126
1127         spin_lock_irqsave(&tp->lock, flags);
1128         memcpy_fromio(p, tp->mmio_addr, regs->len);
1129         spin_unlock_irqrestore(&tp->lock, flags);
1130 }
1131
1132 static u32 rtl8169_get_msglevel(struct net_device *dev)
1133 {
1134         struct rtl8169_private *tp = netdev_priv(dev);
1135
1136         return tp->msg_enable;
1137 }
1138
1139 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1140 {
1141         struct rtl8169_private *tp = netdev_priv(dev);
1142
1143         tp->msg_enable = value;
1144 }
1145
1146 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1147         "tx_packets",
1148         "rx_packets",
1149         "tx_errors",
1150         "rx_errors",
1151         "rx_missed",
1152         "align_errors",
1153         "tx_single_collisions",
1154         "tx_multi_collisions",
1155         "unicast",
1156         "broadcast",
1157         "multicast",
1158         "tx_aborted",
1159         "tx_underrun",
1160 };
1161
1162 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1163 {
1164         switch (sset) {
1165         case ETH_SS_STATS:
1166                 return ARRAY_SIZE(rtl8169_gstrings);
1167         default:
1168                 return -EOPNOTSUPP;
1169         }
1170 }
1171
1172 static void rtl8169_update_counters(struct net_device *dev)
1173 {
1174         struct rtl8169_private *tp = netdev_priv(dev);
1175         void __iomem *ioaddr = tp->mmio_addr;
1176         struct rtl8169_counters *counters;
1177         dma_addr_t paddr;
1178         u32 cmd;
1179         int wait = 1000;
1180
1181         /*
1182          * Some chips are unable to dump tally counters when the receiver
1183          * is disabled.
1184          */
1185         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1186                 return;
1187
1188         counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1189         if (!counters)
1190                 return;
1191
1192         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1193         cmd = (u64)paddr & DMA_BIT_MASK(32);
1194         RTL_W32(CounterAddrLow, cmd);
1195         RTL_W32(CounterAddrLow, cmd | CounterDump);
1196
1197         while (wait--) {
1198                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1199                         /* copy updated counters */
1200                         memcpy(&tp->counters, counters, sizeof(*counters));
1201                         break;
1202                 }
1203                 udelay(10);
1204         }
1205
1206         RTL_W32(CounterAddrLow, 0);
1207         RTL_W32(CounterAddrHigh, 0);
1208
1209         pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1210 }
1211
1212 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1213                                       struct ethtool_stats *stats, u64 *data)
1214 {
1215         struct rtl8169_private *tp = netdev_priv(dev);
1216
1217         ASSERT_RTNL();
1218
1219         rtl8169_update_counters(dev);
1220
1221         data[0] = le64_to_cpu(tp->counters.tx_packets);
1222         data[1] = le64_to_cpu(tp->counters.rx_packets);
1223         data[2] = le64_to_cpu(tp->counters.tx_errors);
1224         data[3] = le32_to_cpu(tp->counters.rx_errors);
1225         data[4] = le16_to_cpu(tp->counters.rx_missed);
1226         data[5] = le16_to_cpu(tp->counters.align_errors);
1227         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1228         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1229         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1230         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1231         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1232         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1233         data[12] = le16_to_cpu(tp->counters.tx_underun);
1234 }
1235
1236 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1237 {
1238         switch(stringset) {
1239         case ETH_SS_STATS:
1240                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1241                 break;
1242         }
1243 }
1244
1245 static const struct ethtool_ops rtl8169_ethtool_ops = {
1246         .get_drvinfo            = rtl8169_get_drvinfo,
1247         .get_regs_len           = rtl8169_get_regs_len,
1248         .get_link               = ethtool_op_get_link,
1249         .get_settings           = rtl8169_get_settings,
1250         .set_settings           = rtl8169_set_settings,
1251         .get_msglevel           = rtl8169_get_msglevel,
1252         .set_msglevel           = rtl8169_set_msglevel,
1253         .get_rx_csum            = rtl8169_get_rx_csum,
1254         .set_rx_csum            = rtl8169_set_rx_csum,
1255         .set_tx_csum            = ethtool_op_set_tx_csum,
1256         .set_sg                 = ethtool_op_set_sg,
1257         .set_tso                = ethtool_op_set_tso,
1258         .get_regs               = rtl8169_get_regs,
1259         .get_wol                = rtl8169_get_wol,
1260         .set_wol                = rtl8169_set_wol,
1261         .get_strings            = rtl8169_get_strings,
1262         .get_sset_count         = rtl8169_get_sset_count,
1263         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1264 };
1265
1266 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1267                                     void __iomem *ioaddr)
1268 {
1269         /*
1270          * The driver currently handles the 8168Bf and the 8168Be identically
1271          * but they can be identified more specifically through the test below
1272          * if needed:
1273          *
1274          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1275          *
1276          * Same thing for the 8101Eb and the 8101Ec:
1277          *
1278          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1279          */
1280         static const struct {
1281                 u32 mask;
1282                 u32 val;
1283                 int mac_version;
1284         } mac_info[] = {
1285                 /* 8168D family. */
1286                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1287                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1288                 { 0x7c800000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1289                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1290
1291                 /* 8168C family. */
1292                 { 0x7cf00000, 0x3ca00000,       RTL_GIGA_MAC_VER_24 },
1293                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1294                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1295                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1296                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1297                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1298                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1299                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1300                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1301
1302                 /* 8168B family. */
1303                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1304                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1305                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1306                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1307
1308                 /* 8101 family. */
1309                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1310                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1311                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1312                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1313                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1314                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1315                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1316                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1317                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1318                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1319                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1320                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1321                 /* FIXME: where did these entries come from ? -- FR */
1322                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1323                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1324
1325                 /* 8110 family. */
1326                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1327                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1328                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1329                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1330                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1331                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1332
1333                 /* Catch-all */
1334                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1335         }, *p = mac_info;
1336         u32 reg;
1337
1338         reg = RTL_R32(TxConfig);
1339         while ((reg & p->mask) != p->val)
1340                 p++;
1341         tp->mac_version = p->mac_version;
1342 }
1343
1344 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1345 {
1346         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1347 }
1348
1349 struct phy_reg {
1350         u16 reg;
1351         u16 val;
1352 };
1353
1354 static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len)
1355 {
1356         while (len-- > 0) {
1357                 mdio_write(ioaddr, regs->reg, regs->val);
1358                 regs++;
1359         }
1360 }
1361
1362 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1363 {
1364         static const struct phy_reg phy_reg_init[] = {
1365                 { 0x1f, 0x0001 },
1366                 { 0x06, 0x006e },
1367                 { 0x08, 0x0708 },
1368                 { 0x15, 0x4000 },
1369                 { 0x18, 0x65c7 },
1370
1371                 { 0x1f, 0x0001 },
1372                 { 0x03, 0x00a1 },
1373                 { 0x02, 0x0008 },
1374                 { 0x01, 0x0120 },
1375                 { 0x00, 0x1000 },
1376                 { 0x04, 0x0800 },
1377                 { 0x04, 0x0000 },
1378
1379                 { 0x03, 0xff41 },
1380                 { 0x02, 0xdf60 },
1381                 { 0x01, 0x0140 },
1382                 { 0x00, 0x0077 },
1383                 { 0x04, 0x7800 },
1384                 { 0x04, 0x7000 },
1385
1386                 { 0x03, 0x802f },
1387                 { 0x02, 0x4f02 },
1388                 { 0x01, 0x0409 },
1389                 { 0x00, 0xf0f9 },
1390                 { 0x04, 0x9800 },
1391                 { 0x04, 0x9000 },
1392
1393                 { 0x03, 0xdf01 },
1394                 { 0x02, 0xdf20 },
1395                 { 0x01, 0xff95 },
1396                 { 0x00, 0xba00 },
1397                 { 0x04, 0xa800 },
1398                 { 0x04, 0xa000 },
1399
1400                 { 0x03, 0xff41 },
1401                 { 0x02, 0xdf20 },
1402                 { 0x01, 0x0140 },
1403                 { 0x00, 0x00bb },
1404                 { 0x04, 0xb800 },
1405                 { 0x04, 0xb000 },
1406
1407                 { 0x03, 0xdf41 },
1408                 { 0x02, 0xdc60 },
1409                 { 0x01, 0x6340 },
1410                 { 0x00, 0x007d },
1411                 { 0x04, 0xd800 },
1412                 { 0x04, 0xd000 },
1413
1414                 { 0x03, 0xdf01 },
1415                 { 0x02, 0xdf20 },
1416                 { 0x01, 0x100a },
1417                 { 0x00, 0xa0ff },
1418                 { 0x04, 0xf800 },
1419                 { 0x04, 0xf000 },
1420
1421                 { 0x1f, 0x0000 },
1422                 { 0x0b, 0x0000 },
1423                 { 0x00, 0x9200 }
1424         };
1425
1426         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1427 }
1428
1429 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1430 {
1431         static const struct phy_reg phy_reg_init[] = {
1432                 { 0x1f, 0x0002 },
1433                 { 0x01, 0x90d0 },
1434                 { 0x1f, 0x0000 }
1435         };
1436
1437         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1438 }
1439
1440 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1441                                            void __iomem *ioaddr)
1442 {
1443         struct pci_dev *pdev = tp->pci_dev;
1444         u16 vendor_id, device_id;
1445
1446         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1447         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1448
1449         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1450                 return;
1451
1452         mdio_write(ioaddr, 0x1f, 0x0001);
1453         mdio_write(ioaddr, 0x10, 0xf01b);
1454         mdio_write(ioaddr, 0x1f, 0x0000);
1455 }
1456
1457 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1458                                      void __iomem *ioaddr)
1459 {
1460         static const struct phy_reg phy_reg_init[] = {
1461                 { 0x1f, 0x0001 },
1462                 { 0x04, 0x0000 },
1463                 { 0x03, 0x00a1 },
1464                 { 0x02, 0x0008 },
1465                 { 0x01, 0x0120 },
1466                 { 0x00, 0x1000 },
1467                 { 0x04, 0x0800 },
1468                 { 0x04, 0x9000 },
1469                 { 0x03, 0x802f },
1470                 { 0x02, 0x4f02 },
1471                 { 0x01, 0x0409 },
1472                 { 0x00, 0xf099 },
1473                 { 0x04, 0x9800 },
1474                 { 0x04, 0xa000 },
1475                 { 0x03, 0xdf01 },
1476                 { 0x02, 0xdf20 },
1477                 { 0x01, 0xff95 },
1478                 { 0x00, 0xba00 },
1479                 { 0x04, 0xa800 },
1480                 { 0x04, 0xf000 },
1481                 { 0x03, 0xdf01 },
1482                 { 0x02, 0xdf20 },
1483                 { 0x01, 0x101a },
1484                 { 0x00, 0xa0ff },
1485                 { 0x04, 0xf800 },
1486                 { 0x04, 0x0000 },
1487                 { 0x1f, 0x0000 },
1488
1489                 { 0x1f, 0x0001 },
1490                 { 0x10, 0xf41b },
1491                 { 0x14, 0xfb54 },
1492                 { 0x18, 0xf5c7 },
1493                 { 0x1f, 0x0000 },
1494
1495                 { 0x1f, 0x0001 },
1496                 { 0x17, 0x0cc0 },
1497                 { 0x1f, 0x0000 }
1498         };
1499
1500         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1501
1502         rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1503 }
1504
1505 static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1506 {
1507         static const struct phy_reg phy_reg_init[] = {
1508                 { 0x1f, 0x0001 },
1509                 { 0x04, 0x0000 },
1510                 { 0x03, 0x00a1 },
1511                 { 0x02, 0x0008 },
1512                 { 0x01, 0x0120 },
1513                 { 0x00, 0x1000 },
1514                 { 0x04, 0x0800 },
1515                 { 0x04, 0x9000 },
1516                 { 0x03, 0x802f },
1517                 { 0x02, 0x4f02 },
1518                 { 0x01, 0x0409 },
1519                 { 0x00, 0xf099 },
1520                 { 0x04, 0x9800 },
1521                 { 0x04, 0xa000 },
1522                 { 0x03, 0xdf01 },
1523                 { 0x02, 0xdf20 },
1524                 { 0x01, 0xff95 },
1525                 { 0x00, 0xba00 },
1526                 { 0x04, 0xa800 },
1527                 { 0x04, 0xf000 },
1528                 { 0x03, 0xdf01 },
1529                 { 0x02, 0xdf20 },
1530                 { 0x01, 0x101a },
1531                 { 0x00, 0xa0ff },
1532                 { 0x04, 0xf800 },
1533                 { 0x04, 0x0000 },
1534                 { 0x1f, 0x0000 },
1535
1536                 { 0x1f, 0x0001 },
1537                 { 0x0b, 0x8480 },
1538                 { 0x1f, 0x0000 },
1539
1540                 { 0x1f, 0x0001 },
1541                 { 0x18, 0x67c7 },
1542                 { 0x04, 0x2000 },
1543                 { 0x03, 0x002f },
1544                 { 0x02, 0x4360 },
1545                 { 0x01, 0x0109 },
1546                 { 0x00, 0x3022 },
1547                 { 0x04, 0x2800 },
1548                 { 0x1f, 0x0000 },
1549
1550                 { 0x1f, 0x0001 },
1551                 { 0x17, 0x0cc0 },
1552                 { 0x1f, 0x0000 }
1553         };
1554
1555         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1556 }
1557
1558 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1559 {
1560         static const struct phy_reg phy_reg_init[] = {
1561                 { 0x10, 0xf41b },
1562                 { 0x1f, 0x0000 }
1563         };
1564
1565         mdio_write(ioaddr, 0x1f, 0x0001);
1566         mdio_patch(ioaddr, 0x16, 1 << 0);
1567
1568         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1569 }
1570
1571 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1572 {
1573         static const struct phy_reg phy_reg_init[] = {
1574                 { 0x1f, 0x0001 },
1575                 { 0x10, 0xf41b },
1576                 { 0x1f, 0x0000 }
1577         };
1578
1579         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1580 }
1581
1582 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1583 {
1584         static const struct phy_reg phy_reg_init[] = {
1585                 { 0x1f, 0x0000 },
1586                 { 0x1d, 0x0f00 },
1587                 { 0x1f, 0x0002 },
1588                 { 0x0c, 0x1ec8 },
1589                 { 0x1f, 0x0000 }
1590         };
1591
1592         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1593 }
1594
1595 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1596 {
1597         static const struct phy_reg phy_reg_init[] = {
1598                 { 0x1f, 0x0001 },
1599                 { 0x1d, 0x3d98 },
1600                 { 0x1f, 0x0000 }
1601         };
1602
1603         mdio_write(ioaddr, 0x1f, 0x0000);
1604         mdio_patch(ioaddr, 0x14, 1 << 5);
1605         mdio_patch(ioaddr, 0x0d, 1 << 5);
1606
1607         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1608 }
1609
1610 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1611 {
1612         static const struct phy_reg phy_reg_init[] = {
1613                 { 0x1f, 0x0001 },
1614                 { 0x12, 0x2300 },
1615                 { 0x1f, 0x0002 },
1616                 { 0x00, 0x88d4 },
1617                 { 0x01, 0x82b1 },
1618                 { 0x03, 0x7002 },
1619                 { 0x08, 0x9e30 },
1620                 { 0x09, 0x01f0 },
1621                 { 0x0a, 0x5500 },
1622                 { 0x0c, 0x00c8 },
1623                 { 0x1f, 0x0003 },
1624                 { 0x12, 0xc096 },
1625                 { 0x16, 0x000a },
1626                 { 0x1f, 0x0000 },
1627                 { 0x1f, 0x0000 },
1628                 { 0x09, 0x2000 },
1629                 { 0x09, 0x0000 }
1630         };
1631
1632         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1633
1634         mdio_patch(ioaddr, 0x14, 1 << 5);
1635         mdio_patch(ioaddr, 0x0d, 1 << 5);
1636         mdio_write(ioaddr, 0x1f, 0x0000);
1637 }
1638
1639 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1640 {
1641         static const struct phy_reg phy_reg_init[] = {
1642                 { 0x1f, 0x0001 },
1643                 { 0x12, 0x2300 },
1644                 { 0x03, 0x802f },
1645                 { 0x02, 0x4f02 },
1646                 { 0x01, 0x0409 },
1647                 { 0x00, 0xf099 },
1648                 { 0x04, 0x9800 },
1649                 { 0x04, 0x9000 },
1650                 { 0x1d, 0x3d98 },
1651                 { 0x1f, 0x0002 },
1652                 { 0x0c, 0x7eb8 },
1653                 { 0x06, 0x0761 },
1654                 { 0x1f, 0x0003 },
1655                 { 0x16, 0x0f0a },
1656                 { 0x1f, 0x0000 }
1657         };
1658
1659         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1660
1661         mdio_patch(ioaddr, 0x16, 1 << 0);
1662         mdio_patch(ioaddr, 0x14, 1 << 5);
1663         mdio_patch(ioaddr, 0x0d, 1 << 5);
1664         mdio_write(ioaddr, 0x1f, 0x0000);
1665 }
1666
1667 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1668 {
1669         static const struct phy_reg phy_reg_init[] = {
1670                 { 0x1f, 0x0001 },
1671                 { 0x12, 0x2300 },
1672                 { 0x1d, 0x3d98 },
1673                 { 0x1f, 0x0002 },
1674                 { 0x0c, 0x7eb8 },
1675                 { 0x06, 0x5461 },
1676                 { 0x1f, 0x0003 },
1677                 { 0x16, 0x0f0a },
1678                 { 0x1f, 0x0000 }
1679         };
1680
1681         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1682
1683         mdio_patch(ioaddr, 0x16, 1 << 0);
1684         mdio_patch(ioaddr, 0x14, 1 << 5);
1685         mdio_patch(ioaddr, 0x0d, 1 << 5);
1686         mdio_write(ioaddr, 0x1f, 0x0000);
1687 }
1688
1689 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1690 {
1691         rtl8168c_3_hw_phy_config(ioaddr);
1692 }
1693
1694 static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
1695 {
1696         static const struct phy_reg phy_reg_init_0[] = {
1697                 { 0x1f, 0x0001 },
1698                 { 0x06, 0x4064 },
1699                 { 0x07, 0x2863 },
1700                 { 0x08, 0x059c },
1701                 { 0x09, 0x26b4 },
1702                 { 0x0a, 0x6a19 },
1703                 { 0x0b, 0xdcc8 },
1704                 { 0x10, 0xf06d },
1705                 { 0x14, 0x7f68 },
1706                 { 0x18, 0x7fd9 },
1707                 { 0x1c, 0xf0ff },
1708                 { 0x1d, 0x3d9c },
1709                 { 0x1f, 0x0003 },
1710                 { 0x12, 0xf49f },
1711                 { 0x13, 0x070b },
1712                 { 0x1a, 0x05ad },
1713                 { 0x14, 0x94c0 }
1714         };
1715         static const struct phy_reg phy_reg_init_1[] = {
1716                 { 0x1f, 0x0002 },
1717                 { 0x06, 0x5561 },
1718                 { 0x1f, 0x0005 },
1719                 { 0x05, 0x8332 },
1720                 { 0x06, 0x5561 }
1721         };
1722         static const struct phy_reg phy_reg_init_2[] = {
1723                 { 0x1f, 0x0005 },
1724                 { 0x05, 0xffc2 },
1725                 { 0x1f, 0x0005 },
1726                 { 0x05, 0x8000 },
1727                 { 0x06, 0xf8f9 },
1728                 { 0x06, 0xfaef },
1729                 { 0x06, 0x59ee },
1730                 { 0x06, 0xf8ea },
1731                 { 0x06, 0x00ee },
1732                 { 0x06, 0xf8eb },
1733                 { 0x06, 0x00e0 },
1734                 { 0x06, 0xf87c },
1735                 { 0x06, 0xe1f8 },
1736                 { 0x06, 0x7d59 },
1737                 { 0x06, 0x0fef },
1738                 { 0x06, 0x0139 },
1739                 { 0x06, 0x029e },
1740                 { 0x06, 0x06ef },
1741                 { 0x06, 0x1039 },
1742                 { 0x06, 0x089f },
1743                 { 0x06, 0x2aee },
1744                 { 0x06, 0xf8ea },
1745                 { 0x06, 0x00ee },
1746                 { 0x06, 0xf8eb },
1747                 { 0x06, 0x01e0 },
1748                 { 0x06, 0xf87c },
1749                 { 0x06, 0xe1f8 },
1750                 { 0x06, 0x7d58 },
1751                 { 0x06, 0x409e },
1752                 { 0x06, 0x0f39 },
1753                 { 0x06, 0x46aa },
1754                 { 0x06, 0x0bbf },
1755                 { 0x06, 0x8290 },
1756                 { 0x06, 0xd682 },
1757                 { 0x06, 0x9802 },
1758                 { 0x06, 0x014f },
1759                 { 0x06, 0xae09 },
1760                 { 0x06, 0xbf82 },
1761                 { 0x06, 0x98d6 },
1762                 { 0x06, 0x82a0 },
1763                 { 0x06, 0x0201 },
1764                 { 0x06, 0x4fef },
1765                 { 0x06, 0x95fe },
1766                 { 0x06, 0xfdfc },
1767                 { 0x06, 0x05f8 },
1768                 { 0x06, 0xf9fa },
1769                 { 0x06, 0xeef8 },
1770                 { 0x06, 0xea00 },
1771                 { 0x06, 0xeef8 },
1772                 { 0x06, 0xeb00 },
1773                 { 0x06, 0xe2f8 },
1774                 { 0x06, 0x7ce3 },
1775                 { 0x06, 0xf87d },
1776                 { 0x06, 0xa511 },
1777                 { 0x06, 0x1112 },
1778                 { 0x06, 0xd240 },
1779                 { 0x06, 0xd644 },
1780                 { 0x06, 0x4402 },
1781                 { 0x06, 0x8217 },
1782                 { 0x06, 0xd2a0 },
1783                 { 0x06, 0xd6aa },
1784                 { 0x06, 0xaa02 },
1785                 { 0x06, 0x8217 },
1786                 { 0x06, 0xae0f },
1787                 { 0x06, 0xa544 },
1788                 { 0x06, 0x4402 },
1789                 { 0x06, 0xae4d },
1790                 { 0x06, 0xa5aa },
1791                 { 0x06, 0xaa02 },
1792                 { 0x06, 0xae47 },
1793                 { 0x06, 0xaf82 },
1794                 { 0x06, 0x13ee },
1795                 { 0x06, 0x834e },
1796                 { 0x06, 0x00ee },
1797                 { 0x06, 0x834d },
1798                 { 0x06, 0x0fee },
1799                 { 0x06, 0x834c },
1800                 { 0x06, 0x0fee },
1801                 { 0x06, 0x834f },
1802                 { 0x06, 0x00ee },
1803                 { 0x06, 0x8351 },
1804                 { 0x06, 0x00ee },
1805                 { 0x06, 0x834a },
1806                 { 0x06, 0xffee },
1807                 { 0x06, 0x834b },
1808                 { 0x06, 0xffe0 },
1809                 { 0x06, 0x8330 },
1810                 { 0x06, 0xe183 },
1811                 { 0x06, 0x3158 },
1812                 { 0x06, 0xfee4 },
1813                 { 0x06, 0xf88a },
1814                 { 0x06, 0xe5f8 },
1815                 { 0x06, 0x8be0 },
1816                 { 0x06, 0x8332 },
1817                 { 0x06, 0xe183 },
1818                 { 0x06, 0x3359 },
1819                 { 0x06, 0x0fe2 },
1820                 { 0x06, 0x834d },
1821                 { 0x06, 0x0c24 },
1822                 { 0x06, 0x5af0 },
1823                 { 0x06, 0x1e12 },
1824                 { 0x06, 0xe4f8 },
1825                 { 0x06, 0x8ce5 },
1826                 { 0x06, 0xf88d },
1827                 { 0x06, 0xaf82 },
1828                 { 0x06, 0x13e0 },
1829                 { 0x06, 0x834f },
1830                 { 0x06, 0x10e4 },
1831                 { 0x06, 0x834f },
1832                 { 0x06, 0xe083 },
1833                 { 0x06, 0x4e78 },
1834                 { 0x06, 0x009f },
1835                 { 0x06, 0x0ae0 },
1836                 { 0x06, 0x834f },
1837                 { 0x06, 0xa010 },
1838                 { 0x06, 0xa5ee },
1839                 { 0x06, 0x834e },
1840                 { 0x06, 0x01e0 },
1841                 { 0x06, 0x834e },
1842                 { 0x06, 0x7805 },
1843                 { 0x06, 0x9e9a },
1844                 { 0x06, 0xe083 },
1845                 { 0x06, 0x4e78 },
1846                 { 0x06, 0x049e },
1847                 { 0x06, 0x10e0 },
1848                 { 0x06, 0x834e },
1849                 { 0x06, 0x7803 },
1850                 { 0x06, 0x9e0f },
1851                 { 0x06, 0xe083 },
1852                 { 0x06, 0x4e78 },
1853                 { 0x06, 0x019e },
1854                 { 0x06, 0x05ae },
1855                 { 0x06, 0x0caf },
1856                 { 0x06, 0x81f8 },
1857                 { 0x06, 0xaf81 },
1858                 { 0x06, 0xa3af },
1859                 { 0x06, 0x81dc },
1860                 { 0x06, 0xaf82 },
1861                 { 0x06, 0x13ee },
1862                 { 0x06, 0x8348 },
1863                 { 0x06, 0x00ee },
1864                 { 0x06, 0x8349 },
1865                 { 0x06, 0x00e0 },
1866                 { 0x06, 0x8351 },
1867                 { 0x06, 0x10e4 },
1868                 { 0x06, 0x8351 },
1869                 { 0x06, 0x5801 },
1870                 { 0x06, 0x9fea },
1871                 { 0x06, 0xd000 },
1872                 { 0x06, 0xd180 },
1873                 { 0x06, 0x1f66 },
1874                 { 0x06, 0xe2f8 },
1875                 { 0x06, 0xeae3 },
1876                 { 0x06, 0xf8eb },
1877                 { 0x06, 0x5af8 },
1878                 { 0x06, 0x1e20 },
1879                 { 0x06, 0xe6f8 },
1880                 { 0x06, 0xeae5 },
1881                 { 0x06, 0xf8eb },
1882                 { 0x06, 0xd302 },
1883                 { 0x06, 0xb3fe },
1884                 { 0x06, 0xe2f8 },
1885                 { 0x06, 0x7cef },
1886                 { 0x06, 0x325b },
1887                 { 0x06, 0x80e3 },
1888                 { 0x06, 0xf87d },
1889                 { 0x06, 0x9e03 },
1890                 { 0x06, 0x7dff },
1891                 { 0x06, 0xff0d },
1892                 { 0x06, 0x581c },
1893                 { 0x06, 0x551a },
1894                 { 0x06, 0x6511 },
1895                 { 0x06, 0xa190 },
1896                 { 0x06, 0xd3e2 },
1897                 { 0x06, 0x8348 },
1898                 { 0x06, 0xe383 },
1899                 { 0x06, 0x491b },
1900                 { 0x06, 0x56ab },
1901                 { 0x06, 0x08ef },
1902                 { 0x06, 0x56e6 },
1903                 { 0x06, 0x8348 },
1904                 { 0x06, 0xe783 },
1905                 { 0x06, 0x4910 },
1906                 { 0x06, 0xd180 },
1907                 { 0x06, 0x1f66 },
1908                 { 0x06, 0xa004 },
1909                 { 0x06, 0xb9e2 },
1910                 { 0x06, 0x8348 },
1911                 { 0x06, 0xe383 },
1912                 { 0x06, 0x49ef },
1913                 { 0x06, 0x65e2 },
1914                 { 0x06, 0x834a },
1915                 { 0x06, 0xe383 },
1916                 { 0x06, 0x4b1b },
1917                 { 0x06, 0x56aa },
1918                 { 0x06, 0x0eef },
1919                 { 0x06, 0x56e6 },
1920                 { 0x06, 0x834a },
1921                 { 0x06, 0xe783 },
1922                 { 0x06, 0x4be2 },
1923                 { 0x06, 0x834d },
1924                 { 0x06, 0xe683 },
1925                 { 0x06, 0x4ce0 },
1926                 { 0x06, 0x834d },
1927                 { 0x06, 0xa000 },
1928                 { 0x06, 0x0caf },
1929                 { 0x06, 0x81dc },
1930                 { 0x06, 0xe083 },
1931                 { 0x06, 0x4d10 },
1932                 { 0x06, 0xe483 },
1933                 { 0x06, 0x4dae },
1934                 { 0x06, 0x0480 },
1935                 { 0x06, 0xe483 },
1936                 { 0x06, 0x4de0 },
1937                 { 0x06, 0x834e },
1938                 { 0x06, 0x7803 },
1939                 { 0x06, 0x9e0b },
1940                 { 0x06, 0xe083 },
1941                 { 0x06, 0x4e78 },
1942                 { 0x06, 0x049e },
1943                 { 0x06, 0x04ee },
1944                 { 0x06, 0x834e },
1945                 { 0x06, 0x02e0 },
1946                 { 0x06, 0x8332 },
1947                 { 0x06, 0xe183 },
1948                 { 0x06, 0x3359 },
1949                 { 0x06, 0x0fe2 },
1950                 { 0x06, 0x834d },
1951                 { 0x06, 0x0c24 },
1952                 { 0x06, 0x5af0 },
1953                 { 0x06, 0x1e12 },
1954                 { 0x06, 0xe4f8 },
1955                 { 0x06, 0x8ce5 },
1956                 { 0x06, 0xf88d },
1957                 { 0x06, 0xe083 },
1958                 { 0x06, 0x30e1 },
1959                 { 0x06, 0x8331 },
1960                 { 0x06, 0x6801 },
1961                 { 0x06, 0xe4f8 },
1962                 { 0x06, 0x8ae5 },
1963                 { 0x06, 0xf88b },
1964                 { 0x06, 0xae37 },
1965                 { 0x06, 0xee83 },
1966                 { 0x06, 0x4e03 },
1967                 { 0x06, 0xe083 },
1968                 { 0x06, 0x4ce1 },
1969                 { 0x06, 0x834d },
1970                 { 0x06, 0x1b01 },
1971                 { 0x06, 0x9e04 },
1972                 { 0x06, 0xaaa1 },
1973                 { 0x06, 0xaea8 },
1974                 { 0x06, 0xee83 },
1975                 { 0x06, 0x4e04 },
1976                 { 0x06, 0xee83 },
1977                 { 0x06, 0x4f00 },
1978                 { 0x06, 0xaeab },
1979                 { 0x06, 0xe083 },
1980                 { 0x06, 0x4f78 },
1981                 { 0x06, 0x039f },
1982                 { 0x06, 0x14ee },
1983                 { 0x06, 0x834e },
1984                 { 0x06, 0x05d2 },
1985                 { 0x06, 0x40d6 },
1986                 { 0x06, 0x5554 },
1987                 { 0x06, 0x0282 },
1988                 { 0x06, 0x17d2 },
1989                 { 0x06, 0xa0d6 },
1990                 { 0x06, 0xba00 },
1991                 { 0x06, 0x0282 },
1992                 { 0x06, 0x17fe },
1993                 { 0x06, 0xfdfc },
1994                 { 0x06, 0x05f8 },
1995                 { 0x06, 0xe0f8 },
1996                 { 0x06, 0x60e1 },
1997                 { 0x06, 0xf861 },
1998                 { 0x06, 0x6802 },
1999                 { 0x06, 0xe4f8 },
2000                 { 0x06, 0x60e5 },
2001                 { 0x06, 0xf861 },
2002                 { 0x06, 0xe0f8 },
2003                 { 0x06, 0x48e1 },
2004                 { 0x06, 0xf849 },
2005                 { 0x06, 0x580f },
2006                 { 0x06, 0x1e02 },
2007                 { 0x06, 0xe4f8 },
2008                 { 0x06, 0x48e5 },
2009                 { 0x06, 0xf849 },
2010                 { 0x06, 0xd000 },
2011                 { 0x06, 0x0282 },
2012                 { 0x06, 0x5bbf },
2013                 { 0x06, 0x8350 },
2014                 { 0x06, 0xef46 },
2015                 { 0x06, 0xdc19 },
2016                 { 0x06, 0xddd0 },
2017                 { 0x06, 0x0102 },
2018                 { 0x06, 0x825b },
2019                 { 0x06, 0x0282 },
2020                 { 0x06, 0x77e0 },
2021                 { 0x06, 0xf860 },
2022                 { 0x06, 0xe1f8 },
2023                 { 0x06, 0x6158 },
2024                 { 0x06, 0xfde4 },
2025                 { 0x06, 0xf860 },
2026                 { 0x06, 0xe5f8 },
2027                 { 0x06, 0x61fc },
2028                 { 0x06, 0x04f9 },
2029                 { 0x06, 0xfafb },
2030                 { 0x06, 0xc6bf },
2031                 { 0x06, 0xf840 },
2032                 { 0x06, 0xbe83 },
2033                 { 0x06, 0x50a0 },
2034                 { 0x06, 0x0101 },
2035                 { 0x06, 0x071b },
2036                 { 0x06, 0x89cf },
2037                 { 0x06, 0xd208 },
2038                 { 0x06, 0xebdb },
2039                 { 0x06, 0x19b2 },
2040                 { 0x06, 0xfbff },
2041                 { 0x06, 0xfefd },
2042                 { 0x06, 0x04f8 },
2043                 { 0x06, 0xe0f8 },
2044                 { 0x06, 0x48e1 },
2045                 { 0x06, 0xf849 },
2046                 { 0x06, 0x6808 },
2047                 { 0x06, 0xe4f8 },
2048                 { 0x06, 0x48e5 },
2049                 { 0x06, 0xf849 },
2050                 { 0x06, 0x58f7 },
2051                 { 0x06, 0xe4f8 },
2052                 { 0x06, 0x48e5 },
2053                 { 0x06, 0xf849 },
2054                 { 0x06, 0xfc04 },
2055                 { 0x06, 0x4d20 },
2056                 { 0x06, 0x0002 },
2057                 { 0x06, 0x4e22 },
2058                 { 0x06, 0x0002 },
2059                 { 0x06, 0x4ddf },
2060                 { 0x06, 0xff01 },
2061                 { 0x06, 0x4edd },
2062                 { 0x06, 0xff01 },
2063                 { 0x05, 0x83d4 },
2064                 { 0x06, 0x8000 },
2065                 { 0x05, 0x83d8 },
2066                 { 0x06, 0x8051 },
2067                 { 0x02, 0x6010 },
2068                 { 0x03, 0xdc00 },
2069                 { 0x05, 0xfff6 },
2070                 { 0x06, 0x00fc },
2071                 { 0x1f, 0x0000 },
2072
2073                 { 0x1f, 0x0000 },
2074                 { 0x0d, 0xf880 },
2075                 { 0x1f, 0x0000 }
2076         };
2077
2078         rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2079
2080         mdio_write(ioaddr, 0x1f, 0x0002);
2081         mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
2082         mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
2083
2084         rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2085
2086         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2087                 static const struct phy_reg phy_reg_init[] = {
2088                         { 0x1f, 0x0002 },
2089                         { 0x05, 0x669a },
2090                         { 0x1f, 0x0005 },
2091                         { 0x05, 0x8330 },
2092                         { 0x06, 0x669a },
2093                         { 0x1f, 0x0002 }
2094                 };
2095                 int val;
2096
2097                 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2098
2099                 val = mdio_read(ioaddr, 0x0d);
2100
2101                 if ((val & 0x00ff) != 0x006c) {
2102                         static const u32 set[] = {
2103                                 0x0065, 0x0066, 0x0067, 0x0068,
2104                                 0x0069, 0x006a, 0x006b, 0x006c
2105                         };
2106                         int i;
2107
2108                         mdio_write(ioaddr, 0x1f, 0x0002);
2109
2110                         val &= 0xff00;
2111                         for (i = 0; i < ARRAY_SIZE(set); i++)
2112                                 mdio_write(ioaddr, 0x0d, val | set[i]);
2113                 }
2114         } else {
2115                 static const struct phy_reg phy_reg_init[] = {
2116                         { 0x1f, 0x0002 },
2117                         { 0x05, 0x6662 },
2118                         { 0x1f, 0x0005 },
2119                         { 0x05, 0x8330 },
2120                         { 0x06, 0x6662 }
2121                 };
2122
2123                 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2124         }
2125
2126         mdio_write(ioaddr, 0x1f, 0x0002);
2127         mdio_patch(ioaddr, 0x0d, 0x0300);
2128         mdio_patch(ioaddr, 0x0f, 0x0010);
2129
2130         mdio_write(ioaddr, 0x1f, 0x0002);
2131         mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2132         mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2133
2134         rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
2135 }
2136
2137 static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2138 {
2139         static const struct phy_reg phy_reg_init_0[] = {
2140                 { 0x1f, 0x0001 },
2141                 { 0x06, 0x4064 },
2142                 { 0x07, 0x2863 },
2143                 { 0x08, 0x059c },
2144                 { 0x09, 0x26b4 },
2145                 { 0x0a, 0x6a19 },
2146                 { 0x0b, 0xdcc8 },
2147                 { 0x10, 0xf06d },
2148                 { 0x14, 0x7f68 },
2149                 { 0x18, 0x7fd9 },
2150                 { 0x1c, 0xf0ff },
2151                 { 0x1d, 0x3d9c },
2152                 { 0x1f, 0x0003 },
2153                 { 0x12, 0xf49f },
2154                 { 0x13, 0x070b },
2155                 { 0x1a, 0x05ad },
2156                 { 0x14, 0x94c0 },
2157
2158                 { 0x1f, 0x0002 },
2159                 { 0x06, 0x5561 },
2160                 { 0x1f, 0x0005 },
2161                 { 0x05, 0x8332 },
2162                 { 0x06, 0x5561 }
2163         };
2164         static const struct phy_reg phy_reg_init_1[] = {
2165                 { 0x1f, 0x0005 },
2166                 { 0x05, 0xffc2 },
2167                 { 0x1f, 0x0005 },
2168                 { 0x05, 0x8000 },
2169                 { 0x06, 0xf8f9 },
2170                 { 0x06, 0xfaee },
2171                 { 0x06, 0xf8ea },
2172                 { 0x06, 0x00ee },
2173                 { 0x06, 0xf8eb },
2174                 { 0x06, 0x00e2 },
2175                 { 0x06, 0xf87c },
2176                 { 0x06, 0xe3f8 },
2177                 { 0x06, 0x7da5 },
2178                 { 0x06, 0x1111 },
2179                 { 0x06, 0x12d2 },
2180                 { 0x06, 0x40d6 },
2181                 { 0x06, 0x4444 },
2182                 { 0x06, 0x0281 },
2183                 { 0x06, 0xc6d2 },
2184                 { 0x06, 0xa0d6 },
2185                 { 0x06, 0xaaaa },
2186                 { 0x06, 0x0281 },
2187                 { 0x06, 0xc6ae },
2188                 { 0x06, 0x0fa5 },
2189                 { 0x06, 0x4444 },
2190                 { 0x06, 0x02ae },
2191                 { 0x06, 0x4da5 },
2192                 { 0x06, 0xaaaa },
2193                 { 0x06, 0x02ae },
2194                 { 0x06, 0x47af },
2195                 { 0x06, 0x81c2 },
2196                 { 0x06, 0xee83 },
2197                 { 0x06, 0x4e00 },
2198                 { 0x06, 0xee83 },
2199                 { 0x06, 0x4d0f },
2200                 { 0x06, 0xee83 },
2201                 { 0x06, 0x4c0f },
2202                 { 0x06, 0xee83 },
2203                 { 0x06, 0x4f00 },
2204                 { 0x06, 0xee83 },
2205                 { 0x06, 0x5100 },
2206                 { 0x06, 0xee83 },
2207                 { 0x06, 0x4aff },
2208                 { 0x06, 0xee83 },
2209                 { 0x06, 0x4bff },
2210                 { 0x06, 0xe083 },
2211                 { 0x06, 0x30e1 },
2212                 { 0x06, 0x8331 },
2213                 { 0x06, 0x58fe },
2214                 { 0x06, 0xe4f8 },
2215                 { 0x06, 0x8ae5 },
2216                 { 0x06, 0xf88b },
2217                 { 0x06, 0xe083 },
2218                 { 0x06, 0x32e1 },
2219                 { 0x06, 0x8333 },
2220                 { 0x06, 0x590f },
2221                 { 0x06, 0xe283 },
2222                 { 0x06, 0x4d0c },
2223                 { 0x06, 0x245a },
2224                 { 0x06, 0xf01e },
2225                 { 0x06, 0x12e4 },
2226                 { 0x06, 0xf88c },
2227                 { 0x06, 0xe5f8 },
2228                 { 0x06, 0x8daf },
2229                 { 0x06, 0x81c2 },
2230                 { 0x06, 0xe083 },
2231                 { 0x06, 0x4f10 },
2232                 { 0x06, 0xe483 },
2233                 { 0x06, 0x4fe0 },
2234                 { 0x06, 0x834e },
2235                 { 0x06, 0x7800 },
2236                 { 0x06, 0x9f0a },
2237                 { 0x06, 0xe083 },
2238                 { 0x06, 0x4fa0 },
2239                 { 0x06, 0x10a5 },
2240                 { 0x06, 0xee83 },
2241                 { 0x06, 0x4e01 },
2242                 { 0x06, 0xe083 },
2243                 { 0x06, 0x4e78 },
2244                 { 0x06, 0x059e },
2245                 { 0x06, 0x9ae0 },
2246                 { 0x06, 0x834e },
2247                 { 0x06, 0x7804 },
2248                 { 0x06, 0x9e10 },
2249                 { 0x06, 0xe083 },
2250                 { 0x06, 0x4e78 },
2251                 { 0x06, 0x039e },
2252                 { 0x06, 0x0fe0 },
2253                 { 0x06, 0x834e },
2254                 { 0x06, 0x7801 },
2255                 { 0x06, 0x9e05 },
2256                 { 0x06, 0xae0c },
2257                 { 0x06, 0xaf81 },
2258                 { 0x06, 0xa7af },
2259                 { 0x06, 0x8152 },
2260                 { 0x06, 0xaf81 },
2261                 { 0x06, 0x8baf },
2262                 { 0x06, 0x81c2 },
2263                 { 0x06, 0xee83 },
2264                 { 0x06, 0x4800 },
2265                 { 0x06, 0xee83 },
2266                 { 0x06, 0x4900 },
2267                 { 0x06, 0xe083 },
2268                 { 0x06, 0x5110 },
2269                 { 0x06, 0xe483 },
2270                 { 0x06, 0x5158 },
2271                 { 0x06, 0x019f },
2272                 { 0x06, 0xead0 },
2273                 { 0x06, 0x00d1 },
2274                 { 0x06, 0x801f },
2275                 { 0x06, 0x66e2 },
2276                 { 0x06, 0xf8ea },
2277                 { 0x06, 0xe3f8 },
2278                 { 0x06, 0xeb5a },
2279                 { 0x06, 0xf81e },
2280                 { 0x06, 0x20e6 },
2281                 { 0x06, 0xf8ea },
2282                 { 0x06, 0xe5f8 },
2283                 { 0x06, 0xebd3 },
2284                 { 0x06, 0x02b3 },
2285                 { 0x06, 0xfee2 },
2286                 { 0x06, 0xf87c },
2287                 { 0x06, 0xef32 },
2288                 { 0x06, 0x5b80 },
2289                 { 0x06, 0xe3f8 },
2290                 { 0x06, 0x7d9e },
2291                 { 0x06, 0x037d },
2292                 { 0x06, 0xffff },
2293                 { 0x06, 0x0d58 },
2294                 { 0x06, 0x1c55 },
2295                 { 0x06, 0x1a65 },
2296                 { 0x06, 0x11a1 },
2297                 { 0x06, 0x90d3 },
2298                 { 0x06, 0xe283 },
2299                 { 0x06, 0x48e3 },
2300                 { 0x06, 0x8349 },
2301                 { 0x06, 0x1b56 },
2302                 { 0x06, 0xab08 },
2303                 { 0x06, 0xef56 },
2304                 { 0x06, 0xe683 },
2305                 { 0x06, 0x48e7 },
2306                 { 0x06, 0x8349 },
2307                 { 0x06, 0x10d1 },
2308                 { 0x06, 0x801f },
2309                 { 0x06, 0x66a0 },
2310                 { 0x06, 0x04b9 },
2311                 { 0x06, 0xe283 },
2312                 { 0x06, 0x48e3 },
2313                 { 0x06, 0x8349 },
2314                 { 0x06, 0xef65 },
2315                 { 0x06, 0xe283 },
2316                 { 0x06, 0x4ae3 },
2317                 { 0x06, 0x834b },
2318                 { 0x06, 0x1b56 },
2319                 { 0x06, 0xaa0e },
2320                 { 0x06, 0xef56 },
2321                 { 0x06, 0xe683 },
2322                 { 0x06, 0x4ae7 },
2323                 { 0x06, 0x834b },
2324                 { 0x06, 0xe283 },
2325                 { 0x06, 0x4de6 },
2326                 { 0x06, 0x834c },
2327                 { 0x06, 0xe083 },
2328                 { 0x06, 0x4da0 },
2329                 { 0x06, 0x000c },
2330                 { 0x06, 0xaf81 },
2331                 { 0x06, 0x8be0 },
2332                 { 0x06, 0x834d },
2333                 { 0x06, 0x10e4 },
2334                 { 0x06, 0x834d },
2335                 { 0x06, 0xae04 },
2336                 { 0x06, 0x80e4 },
2337                 { 0x06, 0x834d },
2338                 { 0x06, 0xe083 },
2339                 { 0x06, 0x4e78 },
2340                 { 0x06, 0x039e },
2341                 { 0x06, 0x0be0 },
2342                 { 0x06, 0x834e },
2343                 { 0x06, 0x7804 },
2344                 { 0x06, 0x9e04 },
2345                 { 0x06, 0xee83 },
2346                 { 0x06, 0x4e02 },
2347                 { 0x06, 0xe083 },
2348                 { 0x06, 0x32e1 },
2349                 { 0x06, 0x8333 },
2350                 { 0x06, 0x590f },
2351                 { 0x06, 0xe283 },
2352                 { 0x06, 0x4d0c },
2353                 { 0x06, 0x245a },
2354                 { 0x06, 0xf01e },
2355                 { 0x06, 0x12e4 },
2356                 { 0x06, 0xf88c },
2357                 { 0x06, 0xe5f8 },
2358                 { 0x06, 0x8de0 },
2359                 { 0x06, 0x8330 },
2360                 { 0x06, 0xe183 },
2361                 { 0x06, 0x3168 },
2362                 { 0x06, 0x01e4 },
2363                 { 0x06, 0xf88a },
2364                 { 0x06, 0xe5f8 },
2365                 { 0x06, 0x8bae },
2366                 { 0x06, 0x37ee },
2367                 { 0x06, 0x834e },
2368                 { 0x06, 0x03e0 },
2369                 { 0x06, 0x834c },
2370                 { 0x06, 0xe183 },
2371                 { 0x06, 0x4d1b },
2372                 { 0x06, 0x019e },
2373                 { 0x06, 0x04aa },
2374                 { 0x06, 0xa1ae },
2375                 { 0x06, 0xa8ee },
2376                 { 0x06, 0x834e },
2377                 { 0x06, 0x04ee },
2378                 { 0x06, 0x834f },
2379                 { 0x06, 0x00ae },
2380                 { 0x06, 0xabe0 },
2381                 { 0x06, 0x834f },
2382                 { 0x06, 0x7803 },
2383                 { 0x06, 0x9f14 },
2384                 { 0x06, 0xee83 },
2385                 { 0x06, 0x4e05 },
2386                 { 0x06, 0xd240 },
2387                 { 0x06, 0xd655 },
2388                 { 0x06, 0x5402 },
2389                 { 0x06, 0x81c6 },
2390                 { 0x06, 0xd2a0 },
2391                 { 0x06, 0xd6ba },
2392                 { 0x06, 0x0002 },
2393                 { 0x06, 0x81c6 },
2394                 { 0x06, 0xfefd },
2395                 { 0x06, 0xfc05 },
2396                 { 0x06, 0xf8e0 },
2397                 { 0x06, 0xf860 },
2398                 { 0x06, 0xe1f8 },
2399                 { 0x06, 0x6168 },
2400                 { 0x06, 0x02e4 },
2401                 { 0x06, 0xf860 },
2402                 { 0x06, 0xe5f8 },
2403                 { 0x06, 0x61e0 },
2404                 { 0x06, 0xf848 },
2405                 { 0x06, 0xe1f8 },
2406                 { 0x06, 0x4958 },
2407                 { 0x06, 0x0f1e },
2408                 { 0x06, 0x02e4 },
2409                 { 0x06, 0xf848 },
2410                 { 0x06, 0xe5f8 },
2411                 { 0x06, 0x49d0 },
2412                 { 0x06, 0x0002 },
2413                 { 0x06, 0x820a },
2414                 { 0x06, 0xbf83 },
2415                 { 0x06, 0x50ef },
2416                 { 0x06, 0x46dc },
2417                 { 0x06, 0x19dd },
2418                 { 0x06, 0xd001 },
2419                 { 0x06, 0x0282 },
2420                 { 0x06, 0x0a02 },
2421                 { 0x06, 0x8226 },
2422                 { 0x06, 0xe0f8 },
2423                 { 0x06, 0x60e1 },
2424                 { 0x06, 0xf861 },
2425                 { 0x06, 0x58fd },
2426                 { 0x06, 0xe4f8 },
2427                 { 0x06, 0x60e5 },
2428                 { 0x06, 0xf861 },
2429                 { 0x06, 0xfc04 },
2430                 { 0x06, 0xf9fa },
2431                 { 0x06, 0xfbc6 },
2432                 { 0x06, 0xbff8 },
2433                 { 0x06, 0x40be },
2434                 { 0x06, 0x8350 },
2435                 { 0x06, 0xa001 },
2436                 { 0x06, 0x0107 },
2437                 { 0x06, 0x1b89 },
2438                 { 0x06, 0xcfd2 },
2439                 { 0x06, 0x08eb },
2440                 { 0x06, 0xdb19 },
2441                 { 0x06, 0xb2fb },
2442                 { 0x06, 0xfffe },
2443                 { 0x06, 0xfd04 },
2444                 { 0x06, 0xf8e0 },
2445                 { 0x06, 0xf848 },
2446                 { 0x06, 0xe1f8 },
2447                 { 0x06, 0x4968 },
2448                 { 0x06, 0x08e4 },
2449                 { 0x06, 0xf848 },
2450                 { 0x06, 0xe5f8 },
2451                 { 0x06, 0x4958 },
2452                 { 0x06, 0xf7e4 },
2453                 { 0x06, 0xf848 },
2454                 { 0x06, 0xe5f8 },
2455                 { 0x06, 0x49fc },
2456                 { 0x06, 0x044d },
2457                 { 0x06, 0x2000 },
2458                 { 0x06, 0x024e },
2459                 { 0x06, 0x2200 },
2460                 { 0x06, 0x024d },
2461                 { 0x06, 0xdfff },
2462                 { 0x06, 0x014e },
2463                 { 0x06, 0xddff },
2464                 { 0x06, 0x0100 },
2465                 { 0x05, 0x83d8 },
2466                 { 0x06, 0x8000 },
2467                 { 0x03, 0xdc00 },
2468                 { 0x05, 0xfff6 },
2469                 { 0x06, 0x00fc },
2470                 { 0x1f, 0x0000 },
2471
2472                 { 0x1f, 0x0000 },
2473                 { 0x0d, 0xf880 },
2474                 { 0x1f, 0x0000 }
2475         };
2476
2477         rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2478
2479         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2480                 static const struct phy_reg phy_reg_init[] = {
2481                         { 0x1f, 0x0002 },
2482                         { 0x05, 0x669a },
2483                         { 0x1f, 0x0005 },
2484                         { 0x05, 0x8330 },
2485                         { 0x06, 0x669a },
2486
2487                         { 0x1f, 0x0002 }
2488                 };
2489                 int val;
2490
2491                 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2492
2493                 val = mdio_read(ioaddr, 0x0d);
2494                 if ((val & 0x00ff) != 0x006c) {
2495                         u32 set[] = {
2496                                 0x0065, 0x0066, 0x0067, 0x0068,
2497                                 0x0069, 0x006a, 0x006b, 0x006c
2498                         };
2499                         int i;
2500
2501                         mdio_write(ioaddr, 0x1f, 0x0002);
2502
2503                         val &= 0xff00;
2504                         for (i = 0; i < ARRAY_SIZE(set); i++)
2505                                 mdio_write(ioaddr, 0x0d, val | set[i]);
2506                 }
2507         } else {
2508                 static const struct phy_reg phy_reg_init[] = {
2509                         { 0x1f, 0x0002 },
2510                         { 0x05, 0x2642 },
2511                         { 0x1f, 0x0005 },
2512                         { 0x05, 0x8330 },
2513                         { 0x06, 0x2642 }
2514                 };
2515
2516                 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2517         }
2518
2519         mdio_write(ioaddr, 0x1f, 0x0002);
2520         mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2521         mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2522
2523         mdio_write(ioaddr, 0x1f, 0x0001);
2524         mdio_write(ioaddr, 0x17, 0x0cc0);
2525
2526         mdio_write(ioaddr, 0x1f, 0x0002);
2527         mdio_patch(ioaddr, 0x0f, 0x0017);
2528
2529         rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2530 }
2531
2532 static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2533 {
2534         static const struct phy_reg phy_reg_init[] = {
2535                 { 0x1f, 0x0002 },
2536                 { 0x10, 0x0008 },
2537                 { 0x0d, 0x006c },
2538
2539                 { 0x1f, 0x0000 },
2540                 { 0x0d, 0xf880 },
2541
2542                 { 0x1f, 0x0001 },
2543                 { 0x17, 0x0cc0 },
2544
2545                 { 0x1f, 0x0001 },
2546                 { 0x0b, 0xa4d8 },
2547                 { 0x09, 0x281c },
2548                 { 0x07, 0x2883 },
2549                 { 0x0a, 0x6b35 },
2550                 { 0x1d, 0x3da4 },
2551                 { 0x1c, 0xeffd },
2552                 { 0x14, 0x7f52 },
2553                 { 0x18, 0x7fc6 },
2554                 { 0x08, 0x0601 },
2555                 { 0x06, 0x4063 },
2556                 { 0x10, 0xf074 },
2557                 { 0x1f, 0x0003 },
2558                 { 0x13, 0x0789 },
2559                 { 0x12, 0xf4bd },
2560                 { 0x1a, 0x04fd },
2561                 { 0x14, 0x84b0 },
2562                 { 0x1f, 0x0000 },
2563                 { 0x00, 0x9200 },
2564
2565                 { 0x1f, 0x0005 },
2566                 { 0x01, 0x0340 },
2567                 { 0x1f, 0x0001 },
2568                 { 0x04, 0x4000 },
2569                 { 0x03, 0x1d21 },
2570                 { 0x02, 0x0c32 },
2571                 { 0x01, 0x0200 },
2572                 { 0x00, 0x5554 },
2573                 { 0x04, 0x4800 },
2574                 { 0x04, 0x4000 },
2575                 { 0x04, 0xf000 },
2576                 { 0x03, 0xdf01 },
2577                 { 0x02, 0xdf20 },
2578                 { 0x01, 0x101a },
2579                 { 0x00, 0xa0ff },
2580                 { 0x04, 0xf800 },
2581                 { 0x04, 0xf000 },
2582                 { 0x1f, 0x0000 },
2583
2584                 { 0x1f, 0x0007 },
2585                 { 0x1e, 0x0023 },
2586                 { 0x16, 0x0000 },
2587                 { 0x1f, 0x0000 }
2588         };
2589
2590         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2591 }
2592
2593 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2594 {
2595         static const struct phy_reg phy_reg_init[] = {
2596                 { 0x1f, 0x0003 },
2597                 { 0x08, 0x441d },
2598                 { 0x01, 0x9100 },
2599                 { 0x1f, 0x0000 }
2600         };
2601
2602         mdio_write(ioaddr, 0x1f, 0x0000);
2603         mdio_patch(ioaddr, 0x11, 1 << 12);
2604         mdio_patch(ioaddr, 0x19, 1 << 13);
2605         mdio_patch(ioaddr, 0x10, 1 << 15);
2606
2607         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2608 }
2609
2610 static void rtl_hw_phy_config(struct net_device *dev)
2611 {
2612         struct rtl8169_private *tp = netdev_priv(dev);
2613         void __iomem *ioaddr = tp->mmio_addr;
2614
2615         rtl8169_print_mac_version(tp);
2616
2617         switch (tp->mac_version) {
2618         case RTL_GIGA_MAC_VER_01:
2619                 break;
2620         case RTL_GIGA_MAC_VER_02:
2621         case RTL_GIGA_MAC_VER_03:
2622                 rtl8169s_hw_phy_config(ioaddr);
2623                 break;
2624         case RTL_GIGA_MAC_VER_04:
2625                 rtl8169sb_hw_phy_config(ioaddr);
2626                 break;
2627         case RTL_GIGA_MAC_VER_05:
2628                 rtl8169scd_hw_phy_config(tp, ioaddr);
2629                 break;
2630         case RTL_GIGA_MAC_VER_06:
2631                 rtl8169sce_hw_phy_config(ioaddr);
2632                 break;
2633         case RTL_GIGA_MAC_VER_07:
2634         case RTL_GIGA_MAC_VER_08:
2635         case RTL_GIGA_MAC_VER_09:
2636                 rtl8102e_hw_phy_config(ioaddr);
2637                 break;
2638         case RTL_GIGA_MAC_VER_11:
2639                 rtl8168bb_hw_phy_config(ioaddr);
2640                 break;
2641         case RTL_GIGA_MAC_VER_12:
2642                 rtl8168bef_hw_phy_config(ioaddr);
2643                 break;
2644         case RTL_GIGA_MAC_VER_17:
2645                 rtl8168bef_hw_phy_config(ioaddr);
2646                 break;
2647         case RTL_GIGA_MAC_VER_18:
2648                 rtl8168cp_1_hw_phy_config(ioaddr);
2649                 break;
2650         case RTL_GIGA_MAC_VER_19:
2651                 rtl8168c_1_hw_phy_config(ioaddr);
2652                 break;
2653         case RTL_GIGA_MAC_VER_20:
2654                 rtl8168c_2_hw_phy_config(ioaddr);
2655                 break;
2656         case RTL_GIGA_MAC_VER_21:
2657                 rtl8168c_3_hw_phy_config(ioaddr);
2658                 break;
2659         case RTL_GIGA_MAC_VER_22:
2660                 rtl8168c_4_hw_phy_config(ioaddr);
2661                 break;
2662         case RTL_GIGA_MAC_VER_23:
2663         case RTL_GIGA_MAC_VER_24:
2664                 rtl8168cp_2_hw_phy_config(ioaddr);
2665                 break;
2666         case RTL_GIGA_MAC_VER_25:
2667                 rtl8168d_1_hw_phy_config(ioaddr);
2668                 break;
2669         case RTL_GIGA_MAC_VER_26:
2670                 rtl8168d_2_hw_phy_config(ioaddr);
2671                 break;
2672         case RTL_GIGA_MAC_VER_27:
2673                 rtl8168d_3_hw_phy_config(ioaddr);
2674                 break;
2675
2676         default:
2677                 break;
2678         }
2679 }
2680
2681 static void rtl8169_phy_timer(unsigned long __opaque)
2682 {
2683         struct net_device *dev = (struct net_device *)__opaque;
2684         struct rtl8169_private *tp = netdev_priv(dev);
2685         struct timer_list *timer = &tp->timer;
2686         void __iomem *ioaddr = tp->mmio_addr;
2687         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2688
2689         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2690
2691         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2692                 return;
2693
2694         spin_lock_irq(&tp->lock);
2695
2696         if (tp->phy_reset_pending(ioaddr)) {
2697                 /*
2698                  * A busy loop could burn quite a few cycles on nowadays CPU.
2699                  * Let's delay the execution of the timer for a few ticks.
2700                  */
2701                 timeout = HZ/10;
2702                 goto out_mod_timer;
2703         }
2704
2705         if (tp->link_ok(ioaddr))
2706                 goto out_unlock;
2707
2708         if (netif_msg_link(tp))
2709                 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
2710
2711         tp->phy_reset_enable(ioaddr);
2712
2713 out_mod_timer:
2714         mod_timer(timer, jiffies + timeout);
2715 out_unlock:
2716         spin_unlock_irq(&tp->lock);
2717 }
2718
2719 static inline void rtl8169_delete_timer(struct net_device *dev)
2720 {
2721         struct rtl8169_private *tp = netdev_priv(dev);
2722         struct timer_list *timer = &tp->timer;
2723
2724         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2725                 return;
2726
2727         del_timer_sync(timer);
2728 }
2729
2730 static inline void rtl8169_request_timer(struct net_device *dev)
2731 {
2732         struct rtl8169_private *tp = netdev_priv(dev);
2733         struct timer_list *timer = &tp->timer;
2734
2735         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2736                 return;
2737
2738         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2739 }
2740
2741 #ifdef CONFIG_NET_POLL_CONTROLLER
2742 /*
2743  * Polling 'interrupt' - used by things like netconsole to send skbs
2744  * without having to re-enable interrupts. It's not called while
2745  * the interrupt routine is executing.
2746  */
2747 static void rtl8169_netpoll(struct net_device *dev)
2748 {
2749         struct rtl8169_private *tp = netdev_priv(dev);
2750         struct pci_dev *pdev = tp->pci_dev;
2751
2752         disable_irq(pdev->irq);
2753         rtl8169_interrupt(pdev->irq, dev);
2754         enable_irq(pdev->irq);
2755 }
2756 #endif
2757
2758 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2759                                   void __iomem *ioaddr)
2760 {
2761         iounmap(ioaddr);
2762         pci_release_regions(pdev);
2763         pci_disable_device(pdev);
2764         free_netdev(dev);
2765 }
2766
2767 static void rtl8169_phy_reset(struct net_device *dev,
2768                               struct rtl8169_private *tp)
2769 {
2770         void __iomem *ioaddr = tp->mmio_addr;
2771         unsigned int i;
2772
2773         tp->phy_reset_enable(ioaddr);
2774         for (i = 0; i < 100; i++) {
2775                 if (!tp->phy_reset_pending(ioaddr))
2776                         return;
2777                 msleep(1);
2778         }
2779         if (netif_msg_link(tp))
2780                 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
2781 }
2782
2783 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2784 {
2785         void __iomem *ioaddr = tp->mmio_addr;
2786
2787         rtl_hw_phy_config(dev);
2788
2789         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2790                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2791                 RTL_W8(0x82, 0x01);
2792         }
2793
2794         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2795
2796         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2797                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2798
2799         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2800                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2801                 RTL_W8(0x82, 0x01);
2802                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2803                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
2804         }
2805
2806         rtl8169_phy_reset(dev, tp);
2807
2808         /*
2809          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2810          * only 8101. Don't panic.
2811          */
2812         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2813
2814         if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
2815                 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
2816 }
2817
2818 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2819 {
2820         void __iomem *ioaddr = tp->mmio_addr;
2821         u32 high;
2822         u32 low;
2823
2824         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2825         high = addr[4] | (addr[5] << 8);
2826
2827         spin_lock_irq(&tp->lock);
2828
2829         RTL_W8(Cfg9346, Cfg9346_Unlock);
2830         RTL_W32(MAC0, low);
2831         RTL_W32(MAC4, high);
2832         RTL_W8(Cfg9346, Cfg9346_Lock);
2833
2834         spin_unlock_irq(&tp->lock);
2835 }
2836
2837 static int rtl_set_mac_address(struct net_device *dev, void *p)
2838 {
2839         struct rtl8169_private *tp = netdev_priv(dev);
2840         struct sockaddr *addr = p;
2841
2842         if (!is_valid_ether_addr(addr->sa_data))
2843                 return -EADDRNOTAVAIL;
2844
2845         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2846
2847         rtl_rar_set(tp, dev->dev_addr);
2848
2849         return 0;
2850 }
2851
2852 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2853 {
2854         struct rtl8169_private *tp = netdev_priv(dev);
2855         struct mii_ioctl_data *data = if_mii(ifr);
2856
2857         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2858 }
2859
2860 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2861 {
2862         switch (cmd) {
2863         case SIOCGMIIPHY:
2864                 data->phy_id = 32; /* Internal PHY */
2865                 return 0;
2866
2867         case SIOCGMIIREG:
2868                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
2869                 return 0;
2870
2871         case SIOCSMIIREG:
2872                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
2873                 return 0;
2874         }
2875         return -EOPNOTSUPP;
2876 }
2877
2878 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2879 {
2880         return -EOPNOTSUPP;
2881 }
2882
2883 static const struct rtl_cfg_info {
2884         void (*hw_start)(struct net_device *);
2885         unsigned int region;
2886         unsigned int align;
2887         u16 intr_event;
2888         u16 napi_event;
2889         unsigned features;
2890         u8 default_ver;
2891 } rtl_cfg_infos [] = {
2892         [RTL_CFG_0] = {
2893                 .hw_start       = rtl_hw_start_8169,
2894                 .region         = 1,
2895                 .align          = 0,
2896                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2897                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2898                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2899                 .features       = RTL_FEATURE_GMII,
2900                 .default_ver    = RTL_GIGA_MAC_VER_01,
2901         },
2902         [RTL_CFG_1] = {
2903                 .hw_start       = rtl_hw_start_8168,
2904                 .region         = 2,
2905                 .align          = 8,
2906                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2907                                   TxErr | TxOK | RxOK | RxErr,
2908                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
2909                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2910                 .default_ver    = RTL_GIGA_MAC_VER_11,
2911         },
2912         [RTL_CFG_2] = {
2913                 .hw_start       = rtl_hw_start_8101,
2914                 .region         = 2,
2915                 .align          = 8,
2916                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2917                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2918                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2919                 .features       = RTL_FEATURE_MSI,
2920                 .default_ver    = RTL_GIGA_MAC_VER_13,
2921         }
2922 };
2923
2924 /* Cfg9346_Unlock assumed. */
2925 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2926                             const struct rtl_cfg_info *cfg)
2927 {
2928         unsigned msi = 0;
2929         u8 cfg2;
2930
2931         cfg2 = RTL_R8(Config2) & ~MSIEnable;
2932         if (cfg->features & RTL_FEATURE_MSI) {
2933                 if (pci_enable_msi(pdev)) {
2934                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2935                 } else {
2936                         cfg2 |= MSIEnable;
2937                         msi = RTL_FEATURE_MSI;
2938                 }
2939         }
2940         RTL_W8(Config2, cfg2);
2941         return msi;
2942 }
2943
2944 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2945 {
2946         if (tp->features & RTL_FEATURE_MSI) {
2947                 pci_disable_msi(pdev);
2948                 tp->features &= ~RTL_FEATURE_MSI;
2949         }
2950 }
2951
2952 static const struct net_device_ops rtl8169_netdev_ops = {
2953         .ndo_open               = rtl8169_open,
2954         .ndo_stop               = rtl8169_close,
2955         .ndo_get_stats          = rtl8169_get_stats,
2956         .ndo_start_xmit         = rtl8169_start_xmit,
2957         .ndo_tx_timeout         = rtl8169_tx_timeout,
2958         .ndo_validate_addr      = eth_validate_addr,
2959         .ndo_change_mtu         = rtl8169_change_mtu,
2960         .ndo_set_mac_address    = rtl_set_mac_address,
2961         .ndo_do_ioctl           = rtl8169_ioctl,
2962         .ndo_set_multicast_list = rtl_set_rx_mode,
2963 #ifdef CONFIG_R8169_VLAN
2964         .ndo_vlan_rx_register   = rtl8169_vlan_rx_register,
2965 #endif
2966 #ifdef CONFIG_NET_POLL_CONTROLLER
2967         .ndo_poll_controller    = rtl8169_netpoll,
2968 #endif
2969
2970 };
2971
2972 static int __devinit
2973 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2974 {
2975         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2976         const unsigned int region = cfg->region;
2977         struct rtl8169_private *tp;
2978         struct mii_if_info *mii;
2979         struct net_device *dev;
2980         void __iomem *ioaddr;
2981         unsigned int i;
2982         int rc;
2983
2984         if (netif_msg_drv(&debug)) {
2985                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2986                        MODULENAME, RTL8169_VERSION);
2987         }
2988
2989         dev = alloc_etherdev(sizeof (*tp));
2990         if (!dev) {
2991                 if (netif_msg_drv(&debug))
2992                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
2993                 rc = -ENOMEM;
2994                 goto out;
2995         }
2996
2997         SET_NETDEV_DEV(dev, &pdev->dev);
2998         dev->netdev_ops = &rtl8169_netdev_ops;
2999         tp = netdev_priv(dev);
3000         tp->dev = dev;
3001         tp->pci_dev = pdev;
3002         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3003
3004         mii = &tp->mii;
3005         mii->dev = dev;
3006         mii->mdio_read = rtl_mdio_read;
3007         mii->mdio_write = rtl_mdio_write;
3008         mii->phy_id_mask = 0x1f;
3009         mii->reg_num_mask = 0x1f;
3010         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3011
3012         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3013         rc = pci_enable_device(pdev);
3014         if (rc < 0) {
3015                 if (netif_msg_probe(tp))
3016                         dev_err(&pdev->dev, "enable failure\n");
3017                 goto err_out_free_dev_1;
3018         }
3019
3020         rc = pci_set_mwi(pdev);
3021         if (rc < 0)
3022                 goto err_out_disable_2;
3023
3024         /* make sure PCI base addr 1 is MMIO */
3025         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3026                 if (netif_msg_probe(tp)) {
3027                         dev_err(&pdev->dev,
3028                                 "region #%d not an MMIO resource, aborting\n",
3029                                 region);
3030                 }
3031                 rc = -ENODEV;
3032                 goto err_out_mwi_3;
3033         }
3034
3035         /* check for weird/broken PCI region reporting */
3036         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3037                 if (netif_msg_probe(tp)) {
3038                         dev_err(&pdev->dev,
3039                                 "Invalid PCI region size(s), aborting\n");
3040                 }
3041                 rc = -ENODEV;
3042                 goto err_out_mwi_3;
3043         }
3044
3045         rc = pci_request_regions(pdev, MODULENAME);
3046         if (rc < 0) {
3047                 if (netif_msg_probe(tp))
3048                         dev_err(&pdev->dev, "could not request regions.\n");
3049                 goto err_out_mwi_3;
3050         }
3051
3052         tp->cp_cmd = PCIMulRW | RxChkSum;
3053
3054         if ((sizeof(dma_addr_t) > 4) &&
3055             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3056                 tp->cp_cmd |= PCIDAC;
3057                 dev->features |= NETIF_F_HIGHDMA;
3058         } else {
3059                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3060                 if (rc < 0) {
3061                         if (netif_msg_probe(tp)) {
3062                                 dev_err(&pdev->dev,
3063                                         "DMA configuration failed.\n");
3064                         }
3065                         goto err_out_free_res_4;
3066                 }
3067         }
3068
3069         /* ioremap MMIO region */
3070         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3071         if (!ioaddr) {
3072                 if (netif_msg_probe(tp))
3073                         dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
3074                 rc = -EIO;
3075                 goto err_out_free_res_4;
3076         }
3077
3078         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3079         if (!tp->pcie_cap && netif_msg_probe(tp))
3080                 dev_info(&pdev->dev, "no PCI Express capability\n");
3081
3082         RTL_W16(IntrMask, 0x0000);
3083
3084         /* Soft reset the chip. */
3085         RTL_W8(ChipCmd, CmdReset);
3086
3087         /* Check that the chip has finished the reset. */
3088         for (i = 0; i < 100; i++) {
3089                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3090                         break;
3091                 msleep_interruptible(1);
3092         }
3093
3094         RTL_W16(IntrStatus, 0xffff);
3095
3096         pci_set_master(pdev);
3097
3098         /* Identify chip attached to board */
3099         rtl8169_get_mac_version(tp, ioaddr);
3100
3101         /* Use appropriate default if unknown */
3102         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3103                 if (netif_msg_probe(tp)) {
3104                         dev_notice(&pdev->dev,
3105                                    "unknown MAC, using family default\n");
3106                 }
3107                 tp->mac_version = cfg->default_ver;
3108         }
3109
3110         rtl8169_print_mac_version(tp);
3111
3112         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3113                 if (tp->mac_version == rtl_chip_info[i].mac_version)
3114                         break;
3115         }
3116         if (i == ARRAY_SIZE(rtl_chip_info)) {
3117                 dev_err(&pdev->dev,
3118                         "driver bug, MAC version not found in rtl_chip_info\n");
3119                 goto err_out_msi_5;
3120         }
3121         tp->chipset = i;
3122
3123         RTL_W8(Cfg9346, Cfg9346_Unlock);
3124         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3125         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3126         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3127                 tp->features |= RTL_FEATURE_WOL;
3128         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3129                 tp->features |= RTL_FEATURE_WOL;
3130         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3131         RTL_W8(Cfg9346, Cfg9346_Lock);
3132
3133         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3134             (RTL_R8(PHYstatus) & TBI_Enable)) {
3135                 tp->set_speed = rtl8169_set_speed_tbi;
3136                 tp->get_settings = rtl8169_gset_tbi;
3137                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3138                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3139                 tp->link_ok = rtl8169_tbi_link_ok;
3140                 tp->do_ioctl = rtl_tbi_ioctl;
3141
3142                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3143         } else {
3144                 tp->set_speed = rtl8169_set_speed_xmii;
3145                 tp->get_settings = rtl8169_gset_xmii;
3146                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3147                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3148                 tp->link_ok = rtl8169_xmii_link_ok;
3149                 tp->do_ioctl = rtl_xmii_ioctl;
3150         }
3151
3152         spin_lock_init(&tp->lock);
3153
3154         tp->mmio_addr = ioaddr;
3155
3156         /* Get MAC address */
3157         for (i = 0; i < MAC_ADDR_LEN; i++)
3158                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3159         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3160
3161         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3162         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3163         dev->irq = pdev->irq;
3164         dev->base_addr = (unsigned long) ioaddr;
3165
3166         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3167
3168 #ifdef CONFIG_R8169_VLAN
3169         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3170 #endif
3171
3172         tp->intr_mask = 0xffff;
3173         tp->align = cfg->align;
3174         tp->hw_start = cfg->hw_start;
3175         tp->intr_event = cfg->intr_event;
3176         tp->napi_event = cfg->napi_event;
3177
3178         init_timer(&tp->timer);
3179         tp->timer.data = (unsigned long) dev;
3180         tp->timer.function = rtl8169_phy_timer;
3181
3182         rc = register_netdev(dev);
3183         if (rc < 0)
3184                 goto err_out_msi_5;
3185
3186         pci_set_drvdata(pdev, dev);
3187
3188         if (netif_msg_probe(tp)) {
3189                 u32 xid = RTL_R32(TxConfig) & 0x9cf0f8ff;
3190
3191                 printk(KERN_INFO "%s: %s at 0x%lx, %pM, XID %08x IRQ %d\n",
3192                        dev->name,
3193                        rtl_chip_info[tp->chipset].name,
3194                        dev->base_addr, dev->dev_addr, xid, dev->irq);
3195         }
3196
3197         rtl8169_init_phy(dev, tp);
3198
3199         /*
3200          * Pretend we are using VLANs; This bypasses a nasty bug where
3201          * Interrupts stop flowing on high load on 8110SCd controllers.
3202          */
3203         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3204                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3205
3206         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3207
3208 out:
3209         return rc;
3210
3211 err_out_msi_5:
3212         rtl_disable_msi(pdev, tp);
3213         iounmap(ioaddr);
3214 err_out_free_res_4:
3215         pci_release_regions(pdev);
3216 err_out_mwi_3:
3217         pci_clear_mwi(pdev);
3218 err_out_disable_2:
3219         pci_disable_device(pdev);
3220 err_out_free_dev_1:
3221         free_netdev(dev);
3222         goto out;
3223 }
3224
3225 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3226 {
3227         struct net_device *dev = pci_get_drvdata(pdev);
3228         struct rtl8169_private *tp = netdev_priv(dev);
3229
3230         flush_scheduled_work();
3231
3232         unregister_netdev(dev);
3233
3234         /* restore original MAC address */
3235         rtl_rar_set(tp, dev->perm_addr);
3236
3237         rtl_disable_msi(pdev, tp);
3238         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3239         pci_set_drvdata(pdev, NULL);
3240 }
3241
3242 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
3243                                   struct net_device *dev)
3244 {
3245         unsigned int max_frame = dev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3246
3247         tp->rx_buf_sz = (max_frame > RX_BUF_SIZE) ? max_frame : RX_BUF_SIZE;
3248 }
3249
3250 static int rtl8169_open(struct net_device *dev)
3251 {
3252         struct rtl8169_private *tp = netdev_priv(dev);
3253         struct pci_dev *pdev = tp->pci_dev;
3254         int retval = -ENOMEM;
3255
3256
3257         rtl8169_set_rxbufsize(tp, dev);
3258
3259         /*
3260          * Rx and Tx desscriptors needs 256 bytes alignment.
3261          * pci_alloc_consistent provides more.
3262          */
3263         tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
3264                                                &tp->TxPhyAddr);
3265         if (!tp->TxDescArray)
3266                 goto out;
3267
3268         tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
3269                                                &tp->RxPhyAddr);
3270         if (!tp->RxDescArray)
3271                 goto err_free_tx_0;
3272
3273         retval = rtl8169_init_ring(dev);
3274         if (retval < 0)
3275                 goto err_free_rx_1;
3276
3277         INIT_DELAYED_WORK(&tp->task, NULL);
3278
3279         smp_mb();
3280
3281         retval = request_irq(dev->irq, rtl8169_interrupt,
3282                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3283                              dev->name, dev);
3284         if (retval < 0)
3285                 goto err_release_ring_2;
3286
3287         napi_enable(&tp->napi);
3288
3289         rtl_hw_start(dev);
3290
3291         rtl8169_request_timer(dev);
3292
3293         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3294 out:
3295         return retval;
3296
3297 err_release_ring_2:
3298         rtl8169_rx_clear(tp);
3299 err_free_rx_1:
3300         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3301                             tp->RxPhyAddr);
3302 err_free_tx_0:
3303         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3304                             tp->TxPhyAddr);
3305         goto out;
3306 }
3307
3308 static void rtl8169_hw_reset(void __iomem *ioaddr)
3309 {
3310         /* Disable interrupts */
3311         rtl8169_irq_mask_and_ack(ioaddr);
3312
3313         /* Reset the chipset */
3314         RTL_W8(ChipCmd, CmdReset);
3315
3316         /* PCI commit */
3317         RTL_R8(ChipCmd);
3318 }
3319
3320 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3321 {
3322         void __iomem *ioaddr = tp->mmio_addr;
3323         u32 cfg = rtl8169_rx_config;
3324
3325         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3326         RTL_W32(RxConfig, cfg);
3327
3328         /* Set DMA burst size and Interframe Gap Time */
3329         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3330                 (InterFrameGap << TxInterFrameGapShift));
3331 }
3332
3333 static void rtl_hw_start(struct net_device *dev)
3334 {
3335         struct rtl8169_private *tp = netdev_priv(dev);
3336         void __iomem *ioaddr = tp->mmio_addr;
3337         unsigned int i;
3338
3339         /* Soft reset the chip. */
3340         RTL_W8(ChipCmd, CmdReset);
3341
3342         /* Check that the chip has finished the reset. */
3343         for (i = 0; i < 100; i++) {
3344                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3345                         break;
3346                 msleep_interruptible(1);
3347         }
3348
3349         tp->hw_start(dev);
3350
3351         netif_start_queue(dev);
3352 }
3353
3354
3355 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3356                                          void __iomem *ioaddr)
3357 {
3358         /*
3359          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3360          * register to be written before TxDescAddrLow to work.
3361          * Switching from MMIO to I/O access fixes the issue as well.
3362          */
3363         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3364         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3365         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3366         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3367 }
3368
3369 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3370 {
3371         u16 cmd;
3372
3373         cmd = RTL_R16(CPlusCmd);
3374         RTL_W16(CPlusCmd, cmd);
3375         return cmd;
3376 }
3377
3378 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3379 {
3380         /* Low hurts. Let's disable the filtering. */
3381         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3382 }
3383
3384 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3385 {
3386         static const struct {
3387                 u32 mac_version;
3388                 u32 clk;
3389                 u32 val;
3390         } cfg2_info [] = {
3391                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3392                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3393                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3394                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3395         }, *p = cfg2_info;
3396         unsigned int i;
3397         u32 clk;
3398
3399         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3400         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3401                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3402                         RTL_W32(0x7c, p->val);
3403                         break;
3404                 }
3405         }
3406 }
3407
3408 static void rtl_hw_start_8169(struct net_device *dev)
3409 {
3410         struct rtl8169_private *tp = netdev_priv(dev);
3411         void __iomem *ioaddr = tp->mmio_addr;
3412         struct pci_dev *pdev = tp->pci_dev;
3413
3414         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3415                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3416                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3417         }
3418
3419         RTL_W8(Cfg9346, Cfg9346_Unlock);
3420         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3421             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3422             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3423             (tp->mac_version == RTL_GIGA_MAC_VER_04))
3424                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3425
3426         RTL_W8(EarlyTxThres, EarlyTxThld);
3427
3428         rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3429
3430         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3431             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3432             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3433             (tp->mac_version == RTL_GIGA_MAC_VER_04))
3434                 rtl_set_rx_tx_config_registers(tp);
3435
3436         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3437
3438         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3439             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3440                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3441                         "Bit-3 and bit-14 MUST be 1\n");
3442                 tp->cp_cmd |= (1 << 14);
3443         }
3444
3445         RTL_W16(CPlusCmd, tp->cp_cmd);
3446
3447         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3448
3449         /*
3450          * Undocumented corner. Supposedly:
3451          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3452          */
3453         RTL_W16(IntrMitigate, 0x0000);
3454
3455         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3456
3457         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3458             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3459             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3460             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3461                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3462                 rtl_set_rx_tx_config_registers(tp);
3463         }
3464
3465         RTL_W8(Cfg9346, Cfg9346_Lock);
3466
3467         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3468         RTL_R8(IntrMask);
3469
3470         RTL_W32(RxMissed, 0);
3471
3472         rtl_set_rx_mode(dev);
3473
3474         /* no early-rx interrupts */
3475         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3476
3477         /* Enable all known interrupts by setting the interrupt mask. */
3478         RTL_W16(IntrMask, tp->intr_event);
3479 }
3480
3481 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3482 {
3483         struct net_device *dev = pci_get_drvdata(pdev);
3484         struct rtl8169_private *tp = netdev_priv(dev);
3485         int cap = tp->pcie_cap;
3486
3487         if (cap) {
3488                 u16 ctl;
3489
3490                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3491                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3492                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3493         }
3494 }
3495
3496 static void rtl_csi_access_enable(void __iomem *ioaddr)
3497 {
3498         u32 csi;
3499
3500         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3501         rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3502 }
3503
3504 struct ephy_info {
3505         unsigned int offset;
3506         u16 mask;
3507         u16 bits;
3508 };
3509
3510 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3511 {
3512         u16 w;
3513
3514         while (len-- > 0) {
3515                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3516                 rtl_ephy_write(ioaddr, e->offset, w);
3517                 e++;
3518         }
3519 }
3520
3521 static void rtl_disable_clock_request(struct pci_dev *pdev)
3522 {
3523         struct net_device *dev = pci_get_drvdata(pdev);
3524         struct rtl8169_private *tp = netdev_priv(dev);
3525         int cap = tp->pcie_cap;
3526
3527         if (cap) {
3528                 u16 ctl;
3529
3530                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3531                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3532                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3533         }
3534 }
3535
3536 #define R8168_CPCMD_QUIRK_MASK (\
3537         EnableBist | \
3538         Mac_dbgo_oe | \
3539         Force_half_dup | \
3540         Force_rxflow_en | \
3541         Force_txflow_en | \
3542         Cxpl_dbg_sel | \
3543         ASF | \
3544         PktCntrDisable | \
3545         Mac_dbgo_sel)
3546
3547 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3548 {
3549         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3550
3551         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3552
3553         rtl_tx_performance_tweak(pdev,
3554                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3555 }
3556
3557 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3558 {
3559         rtl_hw_start_8168bb(ioaddr, pdev);
3560
3561         RTL_W8(EarlyTxThres, EarlyTxThld);
3562
3563         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3564 }
3565
3566 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3567 {
3568         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3569
3570         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3571
3572         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3573
3574         rtl_disable_clock_request(pdev);
3575
3576         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3577 }
3578
3579 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3580 {
3581         static const struct ephy_info e_info_8168cp[] = {
3582                 { 0x01, 0,      0x0001 },
3583                 { 0x02, 0x0800, 0x1000 },
3584                 { 0x03, 0,      0x0042 },
3585                 { 0x06, 0x0080, 0x0000 },
3586                 { 0x07, 0,      0x2000 }
3587         };
3588
3589         rtl_csi_access_enable(ioaddr);
3590
3591         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3592
3593         __rtl_hw_start_8168cp(ioaddr, pdev);
3594 }
3595
3596 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3597 {
3598         rtl_csi_access_enable(ioaddr);
3599
3600         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3601
3602         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3603
3604         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3605 }
3606
3607 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3608 {
3609         rtl_csi_access_enable(ioaddr);
3610
3611         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3612
3613         /* Magic. */
3614         RTL_W8(DBG_REG, 0x20);
3615
3616         RTL_W8(EarlyTxThres, EarlyTxThld);
3617
3618         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3619
3620         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3621 }
3622
3623 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3624 {
3625         static const struct ephy_info e_info_8168c_1[] = {
3626                 { 0x02, 0x0800, 0x1000 },
3627                 { 0x03, 0,      0x0002 },
3628                 { 0x06, 0x0080, 0x0000 }
3629         };
3630
3631         rtl_csi_access_enable(ioaddr);
3632
3633         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3634
3635         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3636
3637         __rtl_hw_start_8168cp(ioaddr, pdev);
3638 }
3639
3640 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3641 {
3642         static const struct ephy_info e_info_8168c_2[] = {
3643                 { 0x01, 0,      0x0001 },
3644                 { 0x03, 0x0400, 0x0220 }
3645         };
3646
3647         rtl_csi_access_enable(ioaddr);
3648
3649         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3650
3651         __rtl_hw_start_8168cp(ioaddr, pdev);
3652 }
3653
3654 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3655 {
3656         rtl_hw_start_8168c_2(ioaddr, pdev);
3657 }
3658
3659 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3660 {
3661         rtl_csi_access_enable(ioaddr);
3662
3663         __rtl_hw_start_8168cp(ioaddr, pdev);
3664 }
3665
3666 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3667 {
3668         rtl_csi_access_enable(ioaddr);
3669
3670         rtl_disable_clock_request(pdev);
3671
3672         RTL_W8(EarlyTxThres, EarlyTxThld);
3673
3674         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3675
3676         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3677 }
3678
3679 static void rtl_hw_start_8168(struct net_device *dev)
3680 {
3681         struct rtl8169_private *tp = netdev_priv(dev);
3682         void __iomem *ioaddr = tp->mmio_addr;
3683         struct pci_dev *pdev = tp->pci_dev;
3684
3685         RTL_W8(Cfg9346, Cfg9346_Unlock);
3686
3687         RTL_W8(EarlyTxThres, EarlyTxThld);
3688
3689         rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3690
3691         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3692
3693         RTL_W16(CPlusCmd, tp->cp_cmd);
3694
3695         RTL_W16(IntrMitigate, 0x5151);
3696
3697         /* Work around for RxFIFO overflow. */
3698         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3699                 tp->intr_event |= RxFIFOOver | PCSTimeout;
3700                 tp->intr_event &= ~RxOverflow;
3701         }
3702
3703         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3704
3705         rtl_set_rx_mode(dev);
3706
3707         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3708                 (InterFrameGap << TxInterFrameGapShift));
3709
3710         RTL_R8(IntrMask);
3711
3712         switch (tp->mac_version) {
3713         case RTL_GIGA_MAC_VER_11:
3714                 rtl_hw_start_8168bb(ioaddr, pdev);
3715         break;
3716
3717         case RTL_GIGA_MAC_VER_12:
3718         case RTL_GIGA_MAC_VER_17:
3719                 rtl_hw_start_8168bef(ioaddr, pdev);
3720         break;
3721
3722         case RTL_GIGA_MAC_VER_18:
3723                 rtl_hw_start_8168cp_1(ioaddr, pdev);
3724         break;
3725
3726         case RTL_GIGA_MAC_VER_19:
3727                 rtl_hw_start_8168c_1(ioaddr, pdev);
3728         break;
3729
3730         case RTL_GIGA_MAC_VER_20:
3731                 rtl_hw_start_8168c_2(ioaddr, pdev);
3732         break;
3733
3734         case RTL_GIGA_MAC_VER_21:
3735                 rtl_hw_start_8168c_3(ioaddr, pdev);
3736         break;
3737
3738         case RTL_GIGA_MAC_VER_22:
3739                 rtl_hw_start_8168c_4(ioaddr, pdev);
3740         break;
3741
3742         case RTL_GIGA_MAC_VER_23:
3743                 rtl_hw_start_8168cp_2(ioaddr, pdev);
3744         break;
3745
3746         case RTL_GIGA_MAC_VER_24:
3747                 rtl_hw_start_8168cp_3(ioaddr, pdev);
3748         break;
3749
3750         case RTL_GIGA_MAC_VER_25:
3751         case RTL_GIGA_MAC_VER_26:
3752         case RTL_GIGA_MAC_VER_27:
3753                 rtl_hw_start_8168d(ioaddr, pdev);
3754         break;
3755
3756         default:
3757                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3758                         dev->name, tp->mac_version);
3759         break;
3760         }
3761
3762         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3763
3764         RTL_W8(Cfg9346, Cfg9346_Lock);
3765
3766         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3767
3768         RTL_W16(IntrMask, tp->intr_event);
3769 }
3770
3771 #define R810X_CPCMD_QUIRK_MASK (\
3772         EnableBist | \
3773         Mac_dbgo_oe | \
3774         Force_half_dup | \
3775         Force_rxflow_en | \
3776         Force_txflow_en | \
3777         Cxpl_dbg_sel | \
3778         ASF | \
3779         PktCntrDisable | \
3780         PCIDAC | \
3781         PCIMulRW)
3782
3783 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3784 {
3785         static const struct ephy_info e_info_8102e_1[] = {
3786                 { 0x01, 0, 0x6e65 },
3787                 { 0x02, 0, 0x091f },
3788                 { 0x03, 0, 0xc2f9 },
3789                 { 0x06, 0, 0xafb5 },
3790                 { 0x07, 0, 0x0e00 },
3791                 { 0x19, 0, 0xec80 },
3792                 { 0x01, 0, 0x2e65 },
3793                 { 0x01, 0, 0x6e65 }
3794         };
3795         u8 cfg1;
3796
3797         rtl_csi_access_enable(ioaddr);
3798
3799         RTL_W8(DBG_REG, FIX_NAK_1);
3800
3801         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3802
3803         RTL_W8(Config1,
3804                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3805         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3806
3807         cfg1 = RTL_R8(Config1);
3808         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3809                 RTL_W8(Config1, cfg1 & ~LEDS0);
3810
3811         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3812
3813         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3814 }
3815
3816 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3817 {
3818         rtl_csi_access_enable(ioaddr);
3819
3820         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3821
3822         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3823         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3824
3825         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3826 }
3827
3828 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3829 {
3830         rtl_hw_start_8102e_2(ioaddr, pdev);
3831
3832         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3833 }
3834
3835 static void rtl_hw_start_8101(struct net_device *dev)
3836 {
3837         struct rtl8169_private *tp = netdev_priv(dev);
3838         void __iomem *ioaddr = tp->mmio_addr;
3839         struct pci_dev *pdev = tp->pci_dev;
3840
3841         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3842             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3843                 int cap = tp->pcie_cap;
3844
3845                 if (cap) {
3846                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3847                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
3848                 }
3849         }
3850
3851         switch (tp->mac_version) {
3852         case RTL_GIGA_MAC_VER_07:
3853                 rtl_hw_start_8102e_1(ioaddr, pdev);
3854                 break;
3855
3856         case RTL_GIGA_MAC_VER_08:
3857                 rtl_hw_start_8102e_3(ioaddr, pdev);
3858                 break;
3859
3860         case RTL_GIGA_MAC_VER_09:
3861                 rtl_hw_start_8102e_2(ioaddr, pdev);
3862                 break;
3863         }
3864
3865         RTL_W8(Cfg9346, Cfg9346_Unlock);
3866
3867         RTL_W8(EarlyTxThres, EarlyTxThld);
3868
3869         rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3870
3871         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3872
3873         RTL_W16(CPlusCmd, tp->cp_cmd);
3874
3875         RTL_W16(IntrMitigate, 0x0000);
3876
3877         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3878
3879         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3880         rtl_set_rx_tx_config_registers(tp);
3881
3882         RTL_W8(Cfg9346, Cfg9346_Lock);
3883
3884         RTL_R8(IntrMask);
3885
3886         rtl_set_rx_mode(dev);
3887
3888         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3889
3890         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3891
3892         RTL_W16(IntrMask, tp->intr_event);
3893 }
3894
3895 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3896 {
3897         struct rtl8169_private *tp = netdev_priv(dev);
3898         int ret = 0;
3899
3900         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3901                 return -EINVAL;
3902
3903         dev->mtu = new_mtu;
3904
3905         if (!netif_running(dev))
3906                 goto out;
3907
3908         rtl8169_down(dev);
3909
3910         rtl8169_set_rxbufsize(tp, dev);
3911
3912         ret = rtl8169_init_ring(dev);
3913         if (ret < 0)
3914                 goto out;
3915
3916         napi_enable(&tp->napi);
3917
3918         rtl_hw_start(dev);
3919
3920         rtl8169_request_timer(dev);
3921
3922 out:
3923         return ret;
3924 }
3925
3926 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3927 {
3928         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3929         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3930 }
3931
3932 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
3933                                 struct sk_buff **sk_buff, struct RxDesc *desc)
3934 {
3935         struct pci_dev *pdev = tp->pci_dev;
3936
3937         pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
3938                          PCI_DMA_FROMDEVICE);
3939         dev_kfree_skb(*sk_buff);
3940         *sk_buff = NULL;
3941         rtl8169_make_unusable_by_asic(desc);
3942 }
3943
3944 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3945 {
3946         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3947
3948         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3949 }
3950
3951 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3952                                        u32 rx_buf_sz)
3953 {
3954         desc->addr = cpu_to_le64(mapping);
3955         wmb();
3956         rtl8169_mark_to_asic(desc, rx_buf_sz);
3957 }
3958
3959 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
3960                                             struct net_device *dev,
3961                                             struct RxDesc *desc, int rx_buf_sz,
3962                                             unsigned int align)
3963 {
3964         struct sk_buff *skb;
3965         dma_addr_t mapping;
3966         unsigned int pad;
3967
3968         pad = align ? align : NET_IP_ALIGN;
3969
3970         skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
3971         if (!skb)
3972                 goto err_out;
3973
3974         skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
3975
3976         mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
3977                                  PCI_DMA_FROMDEVICE);
3978
3979         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
3980 out:
3981         return skb;
3982
3983 err_out:
3984         rtl8169_make_unusable_by_asic(desc);
3985         goto out;
3986 }
3987
3988 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3989 {
3990         unsigned int i;
3991
3992         for (i = 0; i < NUM_RX_DESC; i++) {
3993                 if (tp->Rx_skbuff[i]) {
3994                         rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
3995                                             tp->RxDescArray + i);
3996                 }
3997         }
3998 }
3999
4000 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
4001                            u32 start, u32 end)
4002 {
4003         u32 cur;
4004
4005         for (cur = start; end - cur != 0; cur++) {
4006                 struct sk_buff *skb;
4007                 unsigned int i = cur % NUM_RX_DESC;
4008
4009                 WARN_ON((s32)(end - cur) < 0);
4010
4011                 if (tp->Rx_skbuff[i])
4012                         continue;
4013
4014                 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
4015                                            tp->RxDescArray + i,
4016                                            tp->rx_buf_sz, tp->align);
4017                 if (!skb)
4018                         break;
4019
4020                 tp->Rx_skbuff[i] = skb;
4021         }
4022         return cur - start;
4023 }
4024
4025 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4026 {
4027         desc->opts1 |= cpu_to_le32(RingEnd);
4028 }
4029
4030 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4031 {
4032         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4033 }
4034
4035 static int rtl8169_init_ring(struct net_device *dev)
4036 {
4037         struct rtl8169_private *tp = netdev_priv(dev);
4038
4039         rtl8169_init_ring_indexes(tp);
4040
4041         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4042         memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
4043
4044         if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
4045                 goto err_out;
4046
4047         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4048
4049         return 0;
4050
4051 err_out:
4052         rtl8169_rx_clear(tp);
4053         return -ENOMEM;
4054 }
4055
4056 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
4057                                  struct TxDesc *desc)
4058 {
4059         unsigned int len = tx_skb->len;
4060
4061         pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
4062         desc->opts1 = 0x00;
4063         desc->opts2 = 0x00;
4064         desc->addr = 0x00;
4065         tx_skb->len = 0;
4066 }
4067
4068 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4069 {
4070         unsigned int i;
4071
4072         for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
4073                 unsigned int entry = i % NUM_TX_DESC;
4074                 struct ring_info *tx_skb = tp->tx_skb + entry;
4075                 unsigned int len = tx_skb->len;
4076
4077                 if (len) {
4078                         struct sk_buff *skb = tx_skb->skb;
4079
4080                         rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
4081                                              tp->TxDescArray + entry);
4082                         if (skb) {
4083                                 dev_kfree_skb(skb);
4084                                 tx_skb->skb = NULL;
4085                         }
4086                         tp->dev->stats.tx_dropped++;
4087                 }
4088         }
4089         tp->cur_tx = tp->dirty_tx = 0;
4090 }
4091
4092 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4093 {
4094         struct rtl8169_private *tp = netdev_priv(dev);
4095
4096         PREPARE_DELAYED_WORK(&tp->task, task);
4097         schedule_delayed_work(&tp->task, 4);
4098 }
4099
4100 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4101 {
4102         struct rtl8169_private *tp = netdev_priv(dev);
4103         void __iomem *ioaddr = tp->mmio_addr;
4104
4105         synchronize_irq(dev->irq);
4106
4107         /* Wait for any pending NAPI task to complete */
4108         napi_disable(&tp->napi);
4109
4110         rtl8169_irq_mask_and_ack(ioaddr);
4111
4112         tp->intr_mask = 0xffff;
4113         RTL_W16(IntrMask, tp->intr_event);
4114         napi_enable(&tp->napi);
4115 }
4116
4117 static void rtl8169_reinit_task(struct work_struct *work)
4118 {
4119         struct rtl8169_private *tp =
4120                 container_of(work, struct rtl8169_private, task.work);
4121         struct net_device *dev = tp->dev;
4122         int ret;
4123
4124         rtnl_lock();
4125
4126         if (!netif_running(dev))
4127                 goto out_unlock;
4128
4129         rtl8169_wait_for_quiescence(dev);
4130         rtl8169_close(dev);
4131
4132         ret = rtl8169_open(dev);
4133         if (unlikely(ret < 0)) {
4134                 if (net_ratelimit() && netif_msg_drv(tp)) {
4135                         printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
4136                                " Rescheduling.\n", dev->name, ret);
4137                 }
4138                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4139         }
4140
4141 out_unlock:
4142         rtnl_unlock();
4143 }
4144
4145 static void rtl8169_reset_task(struct work_struct *work)
4146 {
4147         struct rtl8169_private *tp =
4148                 container_of(work, struct rtl8169_private, task.work);
4149         struct net_device *dev = tp->dev;
4150
4151         rtnl_lock();
4152
4153         if (!netif_running(dev))
4154                 goto out_unlock;
4155
4156         rtl8169_wait_for_quiescence(dev);
4157
4158         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4159         rtl8169_tx_clear(tp);
4160
4161         if (tp->dirty_rx == tp->cur_rx) {
4162                 rtl8169_init_ring_indexes(tp);
4163                 rtl_hw_start(dev);
4164                 netif_wake_queue(dev);
4165                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4166         } else {
4167                 if (net_ratelimit() && netif_msg_intr(tp)) {
4168                         printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
4169                                dev->name);
4170                 }
4171                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4172         }
4173
4174 out_unlock:
4175         rtnl_unlock();
4176 }
4177
4178 static void rtl8169_tx_timeout(struct net_device *dev)
4179 {
4180         struct rtl8169_private *tp = netdev_priv(dev);
4181
4182         rtl8169_hw_reset(tp->mmio_addr);
4183
4184         /* Let's wait a bit while any (async) irq lands on */
4185         rtl8169_schedule_work(dev, rtl8169_reset_task);
4186 }
4187
4188 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4189                               u32 opts1)
4190 {
4191         struct skb_shared_info *info = skb_shinfo(skb);
4192         unsigned int cur_frag, entry;
4193         struct TxDesc * uninitialized_var(txd);
4194
4195         entry = tp->cur_tx;
4196         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4197                 skb_frag_t *frag = info->frags + cur_frag;
4198                 dma_addr_t mapping;
4199                 u32 status, len;
4200                 void *addr;
4201
4202                 entry = (entry + 1) % NUM_TX_DESC;
4203
4204                 txd = tp->TxDescArray + entry;
4205                 len = frag->size;
4206                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4207                 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
4208
4209                 /* anti gcc 2.95.3 bugware (sic) */
4210                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4211
4212                 txd->opts1 = cpu_to_le32(status);
4213                 txd->addr = cpu_to_le64(mapping);
4214
4215                 tp->tx_skb[entry].len = len;
4216         }
4217
4218         if (cur_frag) {
4219                 tp->tx_skb[entry].skb = skb;
4220                 txd->opts1 |= cpu_to_le32(LastFrag);
4221         }
4222
4223         return cur_frag;
4224 }
4225
4226 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4227 {
4228         if (dev->features & NETIF_F_TSO) {
4229                 u32 mss = skb_shinfo(skb)->gso_size;
4230
4231                 if (mss)
4232                         return LargeSend | ((mss & MSSMask) << MSSShift);
4233         }
4234         if (skb->ip_summed == CHECKSUM_PARTIAL) {
4235                 const struct iphdr *ip = ip_hdr(skb);
4236
4237                 if (ip->protocol == IPPROTO_TCP)
4238                         return IPCS | TCPCS;
4239                 else if (ip->protocol == IPPROTO_UDP)
4240                         return IPCS | UDPCS;
4241                 WARN_ON(1);     /* we need a WARN() */
4242         }
4243         return 0;
4244 }
4245
4246 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4247                                       struct net_device *dev)
4248 {
4249         struct rtl8169_private *tp = netdev_priv(dev);
4250         unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
4251         struct TxDesc *txd = tp->TxDescArray + entry;
4252         void __iomem *ioaddr = tp->mmio_addr;
4253         dma_addr_t mapping;
4254         u32 status, len;
4255         u32 opts1;
4256
4257         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4258                 if (netif_msg_drv(tp)) {
4259                         printk(KERN_ERR
4260                                "%s: BUG! Tx Ring full when queue awake!\n",
4261                                dev->name);
4262                 }
4263                 goto err_stop;
4264         }
4265
4266         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4267                 goto err_stop;
4268
4269         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4270
4271         frags = rtl8169_xmit_frags(tp, skb, opts1);
4272         if (frags) {
4273                 len = skb_headlen(skb);
4274                 opts1 |= FirstFrag;
4275         } else {
4276                 len = skb->len;
4277                 opts1 |= FirstFrag | LastFrag;
4278                 tp->tx_skb[entry].skb = skb;
4279         }
4280
4281         mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
4282
4283         tp->tx_skb[entry].len = len;
4284         txd->addr = cpu_to_le64(mapping);
4285         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4286
4287         wmb();
4288
4289         /* anti gcc 2.95.3 bugware (sic) */
4290         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4291         txd->opts1 = cpu_to_le32(status);
4292
4293         tp->cur_tx += frags + 1;
4294
4295         smp_wmb();
4296
4297         RTL_W8(TxPoll, NPQ);    /* set polling bit */
4298
4299         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4300                 netif_stop_queue(dev);
4301                 smp_rmb();
4302                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4303                         netif_wake_queue(dev);
4304         }
4305
4306         return NETDEV_TX_OK;
4307
4308 err_stop:
4309         netif_stop_queue(dev);
4310         dev->stats.tx_dropped++;
4311         return NETDEV_TX_BUSY;
4312 }
4313
4314 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4315 {
4316         struct rtl8169_private *tp = netdev_priv(dev);
4317         struct pci_dev *pdev = tp->pci_dev;
4318         void __iomem *ioaddr = tp->mmio_addr;
4319         u16 pci_status, pci_cmd;
4320
4321         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4322         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4323
4324         if (netif_msg_intr(tp)) {
4325                 printk(KERN_ERR
4326                        "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
4327                        dev->name, pci_cmd, pci_status);
4328         }
4329
4330         /*
4331          * The recovery sequence below admits a very elaborated explanation:
4332          * - it seems to work;
4333          * - I did not see what else could be done;
4334          * - it makes iop3xx happy.
4335          *
4336          * Feel free to adjust to your needs.
4337          */
4338         if (pdev->broken_parity_status)
4339                 pci_cmd &= ~PCI_COMMAND_PARITY;
4340         else
4341                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4342
4343         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4344
4345         pci_write_config_word(pdev, PCI_STATUS,
4346                 pci_status & (PCI_STATUS_DETECTED_PARITY |
4347                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4348                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4349
4350         /* The infamous DAC f*ckup only happens at boot time */
4351         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4352                 if (netif_msg_intr(tp))
4353                         printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
4354                 tp->cp_cmd &= ~PCIDAC;
4355                 RTL_W16(CPlusCmd, tp->cp_cmd);
4356                 dev->features &= ~NETIF_F_HIGHDMA;
4357         }
4358
4359         rtl8169_hw_reset(ioaddr);
4360
4361         rtl8169_schedule_work(dev, rtl8169_reinit_task);
4362 }
4363
4364 static void rtl8169_tx_interrupt(struct net_device *dev,
4365                                  struct rtl8169_private *tp,
4366                                  void __iomem *ioaddr)
4367 {
4368         unsigned int dirty_tx, tx_left;
4369
4370         dirty_tx = tp->dirty_tx;
4371         smp_rmb();
4372         tx_left = tp->cur_tx - dirty_tx;
4373
4374         while (tx_left > 0) {
4375                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4376                 struct ring_info *tx_skb = tp->tx_skb + entry;
4377                 u32 len = tx_skb->len;
4378                 u32 status;
4379
4380                 rmb();
4381                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4382                 if (status & DescOwn)
4383                         break;
4384
4385                 dev->stats.tx_bytes += len;
4386                 dev->stats.tx_packets++;
4387
4388                 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
4389
4390                 if (status & LastFrag) {
4391                         dev_kfree_skb(tx_skb->skb);
4392                         tx_skb->skb = NULL;
4393                 }
4394                 dirty_tx++;
4395                 tx_left--;
4396         }
4397
4398         if (tp->dirty_tx != dirty_tx) {
4399                 tp->dirty_tx = dirty_tx;
4400                 smp_wmb();
4401                 if (netif_queue_stopped(dev) &&
4402                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4403                         netif_wake_queue(dev);
4404                 }
4405                 /*
4406                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4407                  * too close. Let's kick an extra TxPoll request when a burst
4408                  * of start_xmit activity is detected (if it is not detected,
4409                  * it is slow enough). -- FR
4410                  */
4411                 smp_rmb();
4412                 if (tp->cur_tx != dirty_tx)
4413                         RTL_W8(TxPoll, NPQ);
4414         }
4415 }
4416
4417 static inline int rtl8169_fragmented_frame(u32 status)
4418 {
4419         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4420 }
4421
4422 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
4423 {
4424         u32 opts1 = le32_to_cpu(desc->opts1);
4425         u32 status = opts1 & RxProtoMask;
4426
4427         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4428             ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
4429             ((status == RxProtoIP) && !(opts1 & IPFail)))
4430                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4431         else
4432                 skb->ip_summed = CHECKSUM_NONE;
4433 }
4434
4435 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
4436                                        struct rtl8169_private *tp, int pkt_size,
4437                                        dma_addr_t addr)
4438 {
4439         struct sk_buff *skb;
4440         bool done = false;
4441
4442         if (pkt_size >= rx_copybreak)
4443                 goto out;
4444
4445         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4446         if (!skb)
4447                 goto out;
4448
4449         pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
4450                                     PCI_DMA_FROMDEVICE);
4451         skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
4452         *sk_buff = skb;
4453         done = true;
4454 out:
4455         return done;
4456 }
4457
4458 static int rtl8169_rx_interrupt(struct net_device *dev,
4459                                 struct rtl8169_private *tp,
4460                                 void __iomem *ioaddr, u32 budget)
4461 {
4462         unsigned int cur_rx, rx_left;
4463         unsigned int delta, count;
4464
4465         cur_rx = tp->cur_rx;
4466         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4467         rx_left = min(rx_left, budget);
4468
4469         for (; rx_left > 0; rx_left--, cur_rx++) {
4470                 unsigned int entry = cur_rx % NUM_RX_DESC;
4471                 struct RxDesc *desc = tp->RxDescArray + entry;
4472                 u32 status;
4473
4474                 rmb();
4475                 status = le32_to_cpu(desc->opts1);
4476
4477                 if (status & DescOwn)
4478                         break;
4479                 if (unlikely(status & RxRES)) {
4480                         if (netif_msg_rx_err(tp)) {
4481                                 printk(KERN_INFO
4482                                        "%s: Rx ERROR. status = %08x\n",
4483                                        dev->name, status);
4484                         }
4485                         dev->stats.rx_errors++;
4486                         if (status & (RxRWT | RxRUNT))
4487                                 dev->stats.rx_length_errors++;
4488                         if (status & RxCRC)
4489                                 dev->stats.rx_crc_errors++;
4490                         if (status & RxFOVF) {
4491                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4492                                 dev->stats.rx_fifo_errors++;
4493                         }
4494                         rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4495                 } else {
4496                         struct sk_buff *skb = tp->Rx_skbuff[entry];
4497                         dma_addr_t addr = le64_to_cpu(desc->addr);
4498                         int pkt_size = (status & 0x00001FFF) - 4;
4499                         struct pci_dev *pdev = tp->pci_dev;
4500
4501                         /*
4502                          * The driver does not support incoming fragmented
4503                          * frames. They are seen as a symptom of over-mtu
4504                          * sized frames.
4505                          */
4506                         if (unlikely(rtl8169_fragmented_frame(status))) {
4507                                 dev->stats.rx_dropped++;
4508                                 dev->stats.rx_length_errors++;
4509                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4510                                 continue;
4511                         }
4512
4513                         rtl8169_rx_csum(skb, desc);
4514
4515                         if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
4516                                 pci_dma_sync_single_for_device(pdev, addr,
4517                                         pkt_size, PCI_DMA_FROMDEVICE);
4518                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4519                         } else {
4520                                 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
4521                                                  PCI_DMA_FROMDEVICE);
4522                                 tp->Rx_skbuff[entry] = NULL;
4523                         }
4524
4525                         skb_put(skb, pkt_size);
4526                         skb->protocol = eth_type_trans(skb, dev);
4527
4528                         if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
4529                                 netif_receive_skb(skb);
4530
4531                         dev->stats.rx_bytes += pkt_size;
4532                         dev->stats.rx_packets++;
4533                 }
4534
4535                 /* Work around for AMD plateform. */
4536                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4537                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4538                         desc->opts2 = 0;
4539                         cur_rx++;
4540                 }
4541         }
4542
4543         count = cur_rx - tp->cur_rx;
4544         tp->cur_rx = cur_rx;
4545
4546         delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
4547         if (!delta && count && netif_msg_intr(tp))
4548                 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
4549         tp->dirty_rx += delta;
4550
4551         /*
4552          * FIXME: until there is periodic timer to try and refill the ring,
4553          * a temporary shortage may definitely kill the Rx process.
4554          * - disable the asic to try and avoid an overflow and kick it again
4555          *   after refill ?
4556          * - how do others driver handle this condition (Uh oh...).
4557          */
4558         if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
4559                 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
4560
4561         return count;
4562 }
4563
4564 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4565 {
4566         struct net_device *dev = dev_instance;
4567         struct rtl8169_private *tp = netdev_priv(dev);
4568         void __iomem *ioaddr = tp->mmio_addr;
4569         int handled = 0;
4570         int status;
4571
4572         /* loop handling interrupts until we have no new ones or
4573          * we hit a invalid/hotplug case.
4574          */
4575         status = RTL_R16(IntrStatus);
4576         while (status && status != 0xffff) {
4577                 handled = 1;
4578
4579                 /* Handle all of the error cases first. These will reset
4580                  * the chip, so just exit the loop.
4581                  */
4582                 if (unlikely(!netif_running(dev))) {
4583                         rtl8169_asic_down(ioaddr);
4584                         break;
4585                 }
4586
4587                 /* Work around for rx fifo overflow */
4588                 if (unlikely(status & RxFIFOOver) &&
4589                 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4590                         netif_stop_queue(dev);
4591                         rtl8169_tx_timeout(dev);
4592                         break;
4593                 }
4594
4595                 if (unlikely(status & SYSErr)) {
4596                         rtl8169_pcierr_interrupt(dev);
4597                         break;
4598                 }
4599
4600                 if (status & LinkChg)
4601                         rtl8169_check_link_status(dev, tp, ioaddr);
4602
4603                 /* We need to see the lastest version of tp->intr_mask to
4604                  * avoid ignoring an MSI interrupt and having to wait for
4605                  * another event which may never come.
4606                  */
4607                 smp_rmb();
4608                 if (status & tp->intr_mask & tp->napi_event) {
4609                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4610                         tp->intr_mask = ~tp->napi_event;
4611
4612                         if (likely(napi_schedule_prep(&tp->napi)))
4613                                 __napi_schedule(&tp->napi);
4614                         else if (netif_msg_intr(tp)) {
4615                                 printk(KERN_INFO "%s: interrupt %04x in poll\n",
4616                                 dev->name, status);
4617                         }
4618                 }
4619
4620                 /* We only get a new MSI interrupt when all active irq
4621                  * sources on the chip have been acknowledged. So, ack
4622                  * everything we've seen and check if new sources have become
4623                  * active to avoid blocking all interrupts from the chip.
4624                  */
4625                 RTL_W16(IntrStatus,
4626                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
4627                 status = RTL_R16(IntrStatus);
4628         }
4629
4630         return IRQ_RETVAL(handled);
4631 }
4632
4633 static int rtl8169_poll(struct napi_struct *napi, int budget)
4634 {
4635         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4636         struct net_device *dev = tp->dev;
4637         void __iomem *ioaddr = tp->mmio_addr;
4638         int work_done;
4639
4640         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4641         rtl8169_tx_interrupt(dev, tp, ioaddr);
4642
4643         if (work_done < budget) {
4644                 napi_complete(napi);
4645
4646                 /* We need for force the visibility of tp->intr_mask
4647                  * for other CPUs, as we can loose an MSI interrupt
4648                  * and potentially wait for a retransmit timeout if we don't.
4649                  * The posted write to IntrMask is safe, as it will
4650                  * eventually make it to the chip and we won't loose anything
4651                  * until it does.
4652                  */
4653                 tp->intr_mask = 0xffff;
4654                 smp_wmb();
4655                 RTL_W16(IntrMask, tp->intr_event);
4656         }
4657
4658         return work_done;
4659 }
4660
4661 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4662 {
4663         struct rtl8169_private *tp = netdev_priv(dev);
4664
4665         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4666                 return;
4667
4668         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4669         RTL_W32(RxMissed, 0);
4670 }
4671
4672 static void rtl8169_down(struct net_device *dev)
4673 {
4674         struct rtl8169_private *tp = netdev_priv(dev);
4675         void __iomem *ioaddr = tp->mmio_addr;
4676         unsigned int intrmask;
4677
4678         rtl8169_delete_timer(dev);
4679
4680         netif_stop_queue(dev);
4681
4682         napi_disable(&tp->napi);
4683
4684 core_down:
4685         spin_lock_irq(&tp->lock);
4686
4687         rtl8169_asic_down(ioaddr);
4688
4689         rtl8169_rx_missed(dev, ioaddr);
4690
4691         spin_unlock_irq(&tp->lock);
4692
4693         synchronize_irq(dev->irq);
4694
4695         /* Give a racing hard_start_xmit a few cycles to complete. */
4696         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
4697
4698         /*
4699          * And now for the 50k$ question: are IRQ disabled or not ?
4700          *
4701          * Two paths lead here:
4702          * 1) dev->close
4703          *    -> netif_running() is available to sync the current code and the
4704          *       IRQ handler. See rtl8169_interrupt for details.
4705          * 2) dev->change_mtu
4706          *    -> rtl8169_poll can not be issued again and re-enable the
4707          *       interruptions. Let's simply issue the IRQ down sequence again.
4708          *
4709          * No loop if hotpluged or major error (0xffff).
4710          */
4711         intrmask = RTL_R16(IntrMask);
4712         if (intrmask && (intrmask != 0xffff))
4713                 goto core_down;
4714
4715         rtl8169_tx_clear(tp);
4716
4717         rtl8169_rx_clear(tp);
4718 }
4719
4720 static int rtl8169_close(struct net_device *dev)
4721 {
4722         struct rtl8169_private *tp = netdev_priv(dev);
4723         struct pci_dev *pdev = tp->pci_dev;
4724
4725         /* update counters before going down */
4726         rtl8169_update_counters(dev);
4727
4728         rtl8169_down(dev);
4729
4730         free_irq(dev->irq, dev);
4731
4732         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
4733                             tp->RxPhyAddr);
4734         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
4735                             tp->TxPhyAddr);
4736         tp->TxDescArray = NULL;
4737         tp->RxDescArray = NULL;
4738
4739         return 0;
4740 }
4741
4742 static void rtl_set_rx_mode(struct net_device *dev)
4743 {
4744         struct rtl8169_private *tp = netdev_priv(dev);
4745         void __iomem *ioaddr = tp->mmio_addr;
4746         unsigned long flags;
4747         u32 mc_filter[2];       /* Multicast hash filter */
4748         int rx_mode;
4749         u32 tmp = 0;
4750
4751         if (dev->flags & IFF_PROMISC) {
4752                 /* Unconditionally log net taps. */
4753                 if (netif_msg_link(tp)) {
4754                         printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
4755                                dev->name);
4756                 }
4757                 rx_mode =
4758                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4759                     AcceptAllPhys;
4760                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4761         } else if ((dev->mc_count > multicast_filter_limit) ||
4762                    (dev->flags & IFF_ALLMULTI)) {
4763                 /* Too many to filter perfectly -- accept all multicasts. */
4764                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4765                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4766         } else {
4767                 struct dev_mc_list *mclist;
4768                 unsigned int i;
4769
4770                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4771                 mc_filter[1] = mc_filter[0] = 0;
4772                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
4773                      i++, mclist = mclist->next) {
4774                         int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
4775                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4776                         rx_mode |= AcceptMulticast;
4777                 }
4778         }
4779
4780         spin_lock_irqsave(&tp->lock, flags);
4781
4782         tmp = rtl8169_rx_config | rx_mode |
4783               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4784
4785         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4786                 u32 data = mc_filter[0];
4787
4788                 mc_filter[0] = swab32(mc_filter[1]);
4789                 mc_filter[1] = swab32(data);
4790         }
4791
4792         RTL_W32(MAR0 + 0, mc_filter[0]);
4793         RTL_W32(MAR0 + 4, mc_filter[1]);
4794
4795         RTL_W32(RxConfig, tmp);
4796
4797         spin_unlock_irqrestore(&tp->lock, flags);
4798 }
4799
4800 /**
4801  *  rtl8169_get_stats - Get rtl8169 read/write statistics
4802  *  @dev: The Ethernet Device to get statistics for
4803  *
4804  *  Get TX/RX statistics for rtl8169
4805  */
4806 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4807 {
4808         struct rtl8169_private *tp = netdev_priv(dev);
4809         void __iomem *ioaddr = tp->mmio_addr;
4810         unsigned long flags;
4811
4812         if (netif_running(dev)) {
4813                 spin_lock_irqsave(&tp->lock, flags);
4814                 rtl8169_rx_missed(dev, ioaddr);
4815                 spin_unlock_irqrestore(&tp->lock, flags);
4816         }
4817
4818         return &dev->stats;
4819 }
4820
4821 static void rtl8169_net_suspend(struct net_device *dev)
4822 {
4823         if (!netif_running(dev))
4824                 return;
4825
4826         netif_device_detach(dev);
4827         netif_stop_queue(dev);
4828 }
4829
4830 #ifdef CONFIG_PM
4831
4832 static int rtl8169_suspend(struct device *device)
4833 {
4834         struct pci_dev *pdev = to_pci_dev(device);
4835         struct net_device *dev = pci_get_drvdata(pdev);
4836
4837         rtl8169_net_suspend(dev);
4838
4839         return 0;
4840 }
4841
4842 static int rtl8169_resume(struct device *device)
4843 {
4844         struct pci_dev *pdev = to_pci_dev(device);
4845         struct net_device *dev = pci_get_drvdata(pdev);
4846
4847         if (!netif_running(dev))
4848                 goto out;
4849
4850         netif_device_attach(dev);
4851
4852         rtl8169_schedule_work(dev, rtl8169_reset_task);
4853 out:
4854         return 0;
4855 }
4856
4857 static const struct dev_pm_ops rtl8169_pm_ops = {
4858         .suspend = rtl8169_suspend,
4859         .resume = rtl8169_resume,
4860         .freeze = rtl8169_suspend,
4861         .thaw = rtl8169_resume,
4862         .poweroff = rtl8169_suspend,
4863         .restore = rtl8169_resume,
4864 };
4865
4866 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
4867
4868 #else /* !CONFIG_PM */
4869
4870 #define RTL8169_PM_OPS  NULL
4871
4872 #endif /* !CONFIG_PM */
4873
4874 static void rtl_shutdown(struct pci_dev *pdev)
4875 {
4876         struct net_device *dev = pci_get_drvdata(pdev);
4877         struct rtl8169_private *tp = netdev_priv(dev);
4878         void __iomem *ioaddr = tp->mmio_addr;
4879
4880         rtl8169_net_suspend(dev);
4881
4882         /* restore original MAC address */
4883         rtl_rar_set(tp, dev->perm_addr);
4884
4885         spin_lock_irq(&tp->lock);
4886
4887         rtl8169_asic_down(ioaddr);
4888
4889         spin_unlock_irq(&tp->lock);
4890
4891         if (system_state == SYSTEM_POWER_OFF) {
4892                 /* WoL fails with some 8168 when the receiver is disabled. */
4893                 if (tp->features & RTL_FEATURE_WOL) {
4894                         pci_clear_master(pdev);
4895
4896                         RTL_W8(ChipCmd, CmdRxEnb);
4897                         /* PCI commit */
4898                         RTL_R8(ChipCmd);
4899                 }
4900
4901                 pci_wake_from_d3(pdev, true);
4902                 pci_set_power_state(pdev, PCI_D3hot);
4903         }
4904 }
4905
4906 static struct pci_driver rtl8169_pci_driver = {
4907         .name           = MODULENAME,
4908         .id_table       = rtl8169_pci_tbl,
4909         .probe          = rtl8169_init_one,
4910         .remove         = __devexit_p(rtl8169_remove_one),
4911         .shutdown       = rtl_shutdown,
4912         .driver.pm      = RTL8169_PM_OPS,
4913 };
4914
4915 static int __init rtl8169_init_module(void)
4916 {
4917         return pci_register_driver(&rtl8169_pci_driver);
4918 }
4919
4920 static void __exit rtl8169_cleanup_module(void)
4921 {
4922         pci_unregister_driver(&rtl8169_pci_driver);
4923 }
4924
4925 module_init(rtl8169_init_module);
4926 module_exit(rtl8169_cleanup_module);