r8169: additional 8101 and 8102 support
[linux-2.6.git] / drivers / net / r8169.c
1 /*
2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3  *
4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6  * Copyright (c) a lot of people too. Please respect their work.
7  *
8  * See MAINTAINERS file for support contact information.
9  */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26
27 #include <asm/system.h>
28 #include <asm/io.h>
29 #include <asm/irq.h>
30
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
34
35 #ifdef RTL8169_DEBUG
36 #define assert(expr) \
37         if (!(expr)) {                                  \
38                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39                 #expr,__FILE__,__FUNCTION__,__LINE__);          \
40         }
41 #define dprintk(fmt, args...) \
42         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
43 #else
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...)   do {} while (0)
46 #endif /* RTL8169_DEBUG */
47
48 #define R8169_MSG_DEFAULT \
49         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
50
51 #define TX_BUFFS_AVAIL(tp) \
52         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static const int max_interrupt_work = 20;
56
57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
59 static const int multicast_filter_limit = 32;
60
61 /* MAC address length */
62 #define MAC_ADDR_LEN    6
63
64 #define MAX_READ_REQUEST_SHIFT  12
65 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
67 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
68 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
69 #define RxPacketMaxSize 0x3FE8  /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
72
73 #define R8169_REGS_SIZE         256
74 #define R8169_NAPI_WEIGHT       64
75 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
80
81 #define RTL8169_TX_TIMEOUT      (6*HZ)
82 #define RTL8169_PHY_TIMEOUT     (10*HZ)
83
84 /* write/read MMIO register */
85 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
86 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
87 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
88 #define RTL_R8(reg)             readb (ioaddr + (reg))
89 #define RTL_R16(reg)            readw (ioaddr + (reg))
90 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
91
92 enum mac_version {
93         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
94         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
95         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
96         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
97         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
98         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
99         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
100         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
101         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
102         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
103         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
104         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
105         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
106         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
107         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
108         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
109         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
110         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
111         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
112         RTL_GIGA_MAC_VER_20 = 0x14  // 8168C
113 };
114
115 #define _R(NAME,MAC,MASK) \
116         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
117
118 static const struct {
119         const char *name;
120         u8 mac_version;
121         u32 RxConfigMask;       /* Clears the bits supported by this chip */
122 } rtl_chip_info[] = {
123         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
124         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
125         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
126         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
127         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
128         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
129         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
130         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
131         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
132         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
133         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
134         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
135         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
136         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
137         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
138         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
139         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
140         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
141         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
142         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880)  // PCI-E
143 };
144 #undef _R
145
146 enum cfg_version {
147         RTL_CFG_0 = 0x00,
148         RTL_CFG_1,
149         RTL_CFG_2
150 };
151
152 static void rtl_hw_start_8169(struct net_device *);
153 static void rtl_hw_start_8168(struct net_device *);
154 static void rtl_hw_start_8101(struct net_device *);
155
156 static struct pci_device_id rtl8169_pci_tbl[] = {
157         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
158         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
159         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
160         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
161         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
162         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
163         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
164         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
165         { PCI_VENDOR_ID_LINKSYS,                0x1032,
166                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
167         { 0x0001,                               0x8168,
168                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
169         {0,},
170 };
171
172 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
173
174 static int rx_copybreak = 200;
175 static int use_dac;
176 static struct {
177         u32 msg_enable;
178 } debug = { -1 };
179
180 enum rtl_registers {
181         MAC0            = 0,    /* Ethernet hardware address. */
182         MAC4            = 4,
183         MAR0            = 8,    /* Multicast filter. */
184         CounterAddrLow          = 0x10,
185         CounterAddrHigh         = 0x14,
186         TxDescStartAddrLow      = 0x20,
187         TxDescStartAddrHigh     = 0x24,
188         TxHDescStartAddrLow     = 0x28,
189         TxHDescStartAddrHigh    = 0x2c,
190         FLASH           = 0x30,
191         ERSR            = 0x36,
192         ChipCmd         = 0x37,
193         TxPoll          = 0x38,
194         IntrMask        = 0x3c,
195         IntrStatus      = 0x3e,
196         TxConfig        = 0x40,
197         RxConfig        = 0x44,
198         RxMissed        = 0x4c,
199         Cfg9346         = 0x50,
200         Config0         = 0x51,
201         Config1         = 0x52,
202         Config2         = 0x53,
203         Config3         = 0x54,
204         Config4         = 0x55,
205         Config5         = 0x56,
206         MultiIntr       = 0x5c,
207         PHYAR           = 0x60,
208         PHYstatus       = 0x6c,
209         RxMaxSize       = 0xda,
210         CPlusCmd        = 0xe0,
211         IntrMitigate    = 0xe2,
212         RxDescAddrLow   = 0xe4,
213         RxDescAddrHigh  = 0xe8,
214         EarlyTxThres    = 0xec,
215         FuncEvent       = 0xf0,
216         FuncEventMask   = 0xf4,
217         FuncPresetState = 0xf8,
218         FuncForceEvent  = 0xfc,
219 };
220
221 enum rtl8110_registers {
222         TBICSR                  = 0x64,
223         TBI_ANAR                = 0x68,
224         TBI_LPAR                = 0x6a,
225 };
226
227 enum rtl8168_8101_registers {
228         CSIDR                   = 0x64,
229         CSIAR                   = 0x68,
230 #define CSIAR_FLAG                      0x80000000
231 #define CSIAR_WRITE_CMD                 0x80000000
232 #define CSIAR_BYTE_ENABLE               0x0f
233 #define CSIAR_BYTE_ENABLE_SHIFT         12
234 #define CSIAR_ADDR_MASK                 0x0fff
235
236         EPHYAR                  = 0x80,
237 #define EPHYAR_FLAG                     0x80000000
238 #define EPHYAR_WRITE_CMD                0x80000000
239 #define EPHYAR_REG_MASK                 0x1f
240 #define EPHYAR_REG_SHIFT                16
241 #define EPHYAR_DATA_MASK                0xffff
242         DBG_REG                 = 0xd1,
243 #define FIX_NAK_1                       (1 << 4)
244 #define FIX_NAK_2                       (1 << 3)
245 };
246
247 enum rtl_register_content {
248         /* InterruptStatusBits */
249         SYSErr          = 0x8000,
250         PCSTimeout      = 0x4000,
251         SWInt           = 0x0100,
252         TxDescUnavail   = 0x0080,
253         RxFIFOOver      = 0x0040,
254         LinkChg         = 0x0020,
255         RxOverflow      = 0x0010,
256         TxErr           = 0x0008,
257         TxOK            = 0x0004,
258         RxErr           = 0x0002,
259         RxOK            = 0x0001,
260
261         /* RxStatusDesc */
262         RxFOVF  = (1 << 23),
263         RxRWT   = (1 << 22),
264         RxRES   = (1 << 21),
265         RxRUNT  = (1 << 20),
266         RxCRC   = (1 << 19),
267
268         /* ChipCmdBits */
269         CmdReset        = 0x10,
270         CmdRxEnb        = 0x08,
271         CmdTxEnb        = 0x04,
272         RxBufEmpty      = 0x01,
273
274         /* TXPoll register p.5 */
275         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
276         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
277         FSWInt          = 0x01,         /* Forced software interrupt */
278
279         /* Cfg9346Bits */
280         Cfg9346_Lock    = 0x00,
281         Cfg9346_Unlock  = 0xc0,
282
283         /* rx_mode_bits */
284         AcceptErr       = 0x20,
285         AcceptRunt      = 0x10,
286         AcceptBroadcast = 0x08,
287         AcceptMulticast = 0x04,
288         AcceptMyPhys    = 0x02,
289         AcceptAllPhys   = 0x01,
290
291         /* RxConfigBits */
292         RxCfgFIFOShift  = 13,
293         RxCfgDMAShift   =  8,
294
295         /* TxConfigBits */
296         TxInterFrameGapShift = 24,
297         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
298
299         /* Config1 register p.24 */
300         LEDS1           = (1 << 7),
301         LEDS0           = (1 << 6),
302         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
303         Speed_down      = (1 << 4),
304         MEMMAP          = (1 << 3),
305         IOMAP           = (1 << 2),
306         VPD             = (1 << 1),
307         PMEnable        = (1 << 0),     /* Power Management Enable */
308
309         /* Config2 register p. 25 */
310         PCI_Clock_66MHz = 0x01,
311         PCI_Clock_33MHz = 0x00,
312
313         /* Config3 register p.25 */
314         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
315         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
316         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
317
318         /* Config5 register p.27 */
319         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
320         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
321         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
322         LanWake         = (1 << 1),     /* LanWake enable/disable */
323         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
324
325         /* TBICSR p.28 */
326         TBIReset        = 0x80000000,
327         TBILoopback     = 0x40000000,
328         TBINwEnable     = 0x20000000,
329         TBINwRestart    = 0x10000000,
330         TBILinkOk       = 0x02000000,
331         TBINwComplete   = 0x01000000,
332
333         /* CPlusCmd p.31 */
334         EnableBist      = (1 << 15),    // 8168 8101
335         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
336         Normal_mode     = (1 << 13),    // unused
337         Force_half_dup  = (1 << 12),    // 8168 8101
338         Force_rxflow_en = (1 << 11),    // 8168 8101
339         Force_txflow_en = (1 << 10),    // 8168 8101
340         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
341         ASF             = (1 << 8),     // 8168 8101
342         PktCntrDisable  = (1 << 7),     // 8168 8101
343         Mac_dbgo_sel    = 0x001c,       // 8168
344         RxVlan          = (1 << 6),
345         RxChkSum        = (1 << 5),
346         PCIDAC          = (1 << 4),
347         PCIMulRW        = (1 << 3),
348         INTT_0          = 0x0000,       // 8168
349         INTT_1          = 0x0001,       // 8168
350         INTT_2          = 0x0002,       // 8168
351         INTT_3          = 0x0003,       // 8168
352
353         /* rtl8169_PHYstatus */
354         TBI_Enable      = 0x80,
355         TxFlowCtrl      = 0x40,
356         RxFlowCtrl      = 0x20,
357         _1000bpsF       = 0x10,
358         _100bps         = 0x08,
359         _10bps          = 0x04,
360         LinkStatus      = 0x02,
361         FullDup         = 0x01,
362
363         /* _TBICSRBit */
364         TBILinkOK       = 0x02000000,
365
366         /* DumpCounterCommand */
367         CounterDump     = 0x8,
368 };
369
370 enum desc_status_bit {
371         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
372         RingEnd         = (1 << 30), /* End of descriptor ring */
373         FirstFrag       = (1 << 29), /* First segment of a packet */
374         LastFrag        = (1 << 28), /* Final segment of a packet */
375
376         /* Tx private */
377         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
378         MSSShift        = 16,        /* MSS value position */
379         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
380         IPCS            = (1 << 18), /* Calculate IP checksum */
381         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
382         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
383         TxVlanTag       = (1 << 17), /* Add VLAN tag */
384
385         /* Rx private */
386         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
387         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
388
389 #define RxProtoUDP      (PID1)
390 #define RxProtoTCP      (PID0)
391 #define RxProtoIP       (PID1 | PID0)
392 #define RxProtoMask     RxProtoIP
393
394         IPFail          = (1 << 16), /* IP checksum failed */
395         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
396         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
397         RxVlanTag       = (1 << 16), /* VLAN tag available */
398 };
399
400 #define RsvdMask        0x3fffc000
401
402 struct TxDesc {
403         __le32 opts1;
404         __le32 opts2;
405         __le64 addr;
406 };
407
408 struct RxDesc {
409         __le32 opts1;
410         __le32 opts2;
411         __le64 addr;
412 };
413
414 struct ring_info {
415         struct sk_buff  *skb;
416         u32             len;
417         u8              __pad[sizeof(void *) - sizeof(u32)];
418 };
419
420 enum features {
421         RTL_FEATURE_WOL         = (1 << 0),
422         RTL_FEATURE_MSI         = (1 << 1),
423         RTL_FEATURE_GMII        = (1 << 2),
424 };
425
426 struct rtl8169_private {
427         void __iomem *mmio_addr;        /* memory map physical address */
428         struct pci_dev *pci_dev;        /* Index of PCI device */
429         struct net_device *dev;
430         struct napi_struct napi;
431         spinlock_t lock;                /* spin lock flag */
432         u32 msg_enable;
433         int chipset;
434         int mac_version;
435         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
436         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
437         u32 dirty_rx;
438         u32 dirty_tx;
439         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
440         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
441         dma_addr_t TxPhyAddr;
442         dma_addr_t RxPhyAddr;
443         struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
444         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
445         unsigned align;
446         unsigned rx_buf_sz;
447         struct timer_list timer;
448         u16 cp_cmd;
449         u16 intr_event;
450         u16 napi_event;
451         u16 intr_mask;
452         int phy_auto_nego_reg;
453         int phy_1000_ctrl_reg;
454 #ifdef CONFIG_R8169_VLAN
455         struct vlan_group *vlgrp;
456 #endif
457         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
458         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
459         void (*phy_reset_enable)(void __iomem *);
460         void (*hw_start)(struct net_device *);
461         unsigned int (*phy_reset_pending)(void __iomem *);
462         unsigned int (*link_ok)(void __iomem *);
463         int pcie_cap;
464         struct delayed_work task;
465         unsigned features;
466
467         struct mii_if_info mii;
468 };
469
470 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
471 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
472 module_param(rx_copybreak, int, 0);
473 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
474 module_param(use_dac, int, 0);
475 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
476 module_param_named(debug, debug.msg_enable, int, 0);
477 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
478 MODULE_LICENSE("GPL");
479 MODULE_VERSION(RTL8169_VERSION);
480
481 static int rtl8169_open(struct net_device *dev);
482 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
483 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
484 static int rtl8169_init_ring(struct net_device *dev);
485 static void rtl_hw_start(struct net_device *dev);
486 static int rtl8169_close(struct net_device *dev);
487 static void rtl_set_rx_mode(struct net_device *dev);
488 static void rtl8169_tx_timeout(struct net_device *dev);
489 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
490 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
491                                 void __iomem *, u32 budget);
492 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
493 static void rtl8169_down(struct net_device *dev);
494 static void rtl8169_rx_clear(struct rtl8169_private *tp);
495 static int rtl8169_poll(struct napi_struct *napi, int budget);
496
497 static const unsigned int rtl8169_rx_config =
498         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
499
500 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
501 {
502         int i;
503
504         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
505
506         for (i = 20; i > 0; i--) {
507                 /*
508                  * Check if the RTL8169 has completed writing to the specified
509                  * MII register.
510                  */
511                 if (!(RTL_R32(PHYAR) & 0x80000000))
512                         break;
513                 udelay(25);
514         }
515 }
516
517 static int mdio_read(void __iomem *ioaddr, int reg_addr)
518 {
519         int i, value = -1;
520
521         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
522
523         for (i = 20; i > 0; i--) {
524                 /*
525                  * Check if the RTL8169 has completed retrieving data from
526                  * the specified MII register.
527                  */
528                 if (RTL_R32(PHYAR) & 0x80000000) {
529                         value = RTL_R32(PHYAR) & 0xffff;
530                         break;
531                 }
532                 udelay(25);
533         }
534         return value;
535 }
536
537 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
538 {
539         mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
540 }
541
542 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
543                            int val)
544 {
545         struct rtl8169_private *tp = netdev_priv(dev);
546         void __iomem *ioaddr = tp->mmio_addr;
547
548         mdio_write(ioaddr, location, val);
549 }
550
551 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
552 {
553         struct rtl8169_private *tp = netdev_priv(dev);
554         void __iomem *ioaddr = tp->mmio_addr;
555
556         return mdio_read(ioaddr, location);
557 }
558
559 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
560 {
561         unsigned int i;
562
563         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
564                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
565
566         for (i = 0; i < 100; i++) {
567                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
568                         break;
569                 udelay(10);
570         }
571 }
572
573 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
574 {
575         u16 value = 0xffff;
576         unsigned int i;
577
578         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
579
580         for (i = 0; i < 100; i++) {
581                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
582                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
583                         break;
584                 }
585                 udelay(10);
586         }
587
588         return value;
589 }
590
591 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
592 {
593         unsigned int i;
594
595         RTL_W32(CSIDR, value);
596         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
597                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
598
599         for (i = 0; i < 100; i++) {
600                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
601                         break;
602                 udelay(10);
603         }
604 }
605
606 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
607 {
608         u32 value = ~0x00;
609         unsigned int i;
610
611         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
612                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
613
614         for (i = 0; i < 100; i++) {
615                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
616                         value = RTL_R32(CSIDR);
617                         break;
618                 }
619                 udelay(10);
620         }
621
622         return value;
623 }
624
625 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
626 {
627         RTL_W16(IntrMask, 0x0000);
628
629         RTL_W16(IntrStatus, 0xffff);
630 }
631
632 static void rtl8169_asic_down(void __iomem *ioaddr)
633 {
634         RTL_W8(ChipCmd, 0x00);
635         rtl8169_irq_mask_and_ack(ioaddr);
636         RTL_R16(CPlusCmd);
637 }
638
639 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
640 {
641         return RTL_R32(TBICSR) & TBIReset;
642 }
643
644 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
645 {
646         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
647 }
648
649 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
650 {
651         return RTL_R32(TBICSR) & TBILinkOk;
652 }
653
654 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
655 {
656         return RTL_R8(PHYstatus) & LinkStatus;
657 }
658
659 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
660 {
661         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
662 }
663
664 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
665 {
666         unsigned int val;
667
668         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
669         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
670 }
671
672 static void rtl8169_check_link_status(struct net_device *dev,
673                                       struct rtl8169_private *tp,
674                                       void __iomem *ioaddr)
675 {
676         unsigned long flags;
677
678         spin_lock_irqsave(&tp->lock, flags);
679         if (tp->link_ok(ioaddr)) {
680                 netif_carrier_on(dev);
681                 if (netif_msg_ifup(tp))
682                         printk(KERN_INFO PFX "%s: link up\n", dev->name);
683         } else {
684                 if (netif_msg_ifdown(tp))
685                         printk(KERN_INFO PFX "%s: link down\n", dev->name);
686                 netif_carrier_off(dev);
687         }
688         spin_unlock_irqrestore(&tp->lock, flags);
689 }
690
691 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
692 {
693         struct rtl8169_private *tp = netdev_priv(dev);
694         void __iomem *ioaddr = tp->mmio_addr;
695         u8 options;
696
697         wol->wolopts = 0;
698
699 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
700         wol->supported = WAKE_ANY;
701
702         spin_lock_irq(&tp->lock);
703
704         options = RTL_R8(Config1);
705         if (!(options & PMEnable))
706                 goto out_unlock;
707
708         options = RTL_R8(Config3);
709         if (options & LinkUp)
710                 wol->wolopts |= WAKE_PHY;
711         if (options & MagicPacket)
712                 wol->wolopts |= WAKE_MAGIC;
713
714         options = RTL_R8(Config5);
715         if (options & UWF)
716                 wol->wolopts |= WAKE_UCAST;
717         if (options & BWF)
718                 wol->wolopts |= WAKE_BCAST;
719         if (options & MWF)
720                 wol->wolopts |= WAKE_MCAST;
721
722 out_unlock:
723         spin_unlock_irq(&tp->lock);
724 }
725
726 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
727 {
728         struct rtl8169_private *tp = netdev_priv(dev);
729         void __iomem *ioaddr = tp->mmio_addr;
730         unsigned int i;
731         static struct {
732                 u32 opt;
733                 u16 reg;
734                 u8  mask;
735         } cfg[] = {
736                 { WAKE_ANY,   Config1, PMEnable },
737                 { WAKE_PHY,   Config3, LinkUp },
738                 { WAKE_MAGIC, Config3, MagicPacket },
739                 { WAKE_UCAST, Config5, UWF },
740                 { WAKE_BCAST, Config5, BWF },
741                 { WAKE_MCAST, Config5, MWF },
742                 { WAKE_ANY,   Config5, LanWake }
743         };
744
745         spin_lock_irq(&tp->lock);
746
747         RTL_W8(Cfg9346, Cfg9346_Unlock);
748
749         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
750                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
751                 if (wol->wolopts & cfg[i].opt)
752                         options |= cfg[i].mask;
753                 RTL_W8(cfg[i].reg, options);
754         }
755
756         RTL_W8(Cfg9346, Cfg9346_Lock);
757
758         if (wol->wolopts)
759                 tp->features |= RTL_FEATURE_WOL;
760         else
761                 tp->features &= ~RTL_FEATURE_WOL;
762
763         spin_unlock_irq(&tp->lock);
764
765         return 0;
766 }
767
768 static void rtl8169_get_drvinfo(struct net_device *dev,
769                                 struct ethtool_drvinfo *info)
770 {
771         struct rtl8169_private *tp = netdev_priv(dev);
772
773         strcpy(info->driver, MODULENAME);
774         strcpy(info->version, RTL8169_VERSION);
775         strcpy(info->bus_info, pci_name(tp->pci_dev));
776 }
777
778 static int rtl8169_get_regs_len(struct net_device *dev)
779 {
780         return R8169_REGS_SIZE;
781 }
782
783 static int rtl8169_set_speed_tbi(struct net_device *dev,
784                                  u8 autoneg, u16 speed, u8 duplex)
785 {
786         struct rtl8169_private *tp = netdev_priv(dev);
787         void __iomem *ioaddr = tp->mmio_addr;
788         int ret = 0;
789         u32 reg;
790
791         reg = RTL_R32(TBICSR);
792         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
793             (duplex == DUPLEX_FULL)) {
794                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
795         } else if (autoneg == AUTONEG_ENABLE)
796                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
797         else {
798                 if (netif_msg_link(tp)) {
799                         printk(KERN_WARNING "%s: "
800                                "incorrect speed setting refused in TBI mode\n",
801                                dev->name);
802                 }
803                 ret = -EOPNOTSUPP;
804         }
805
806         return ret;
807 }
808
809 static int rtl8169_set_speed_xmii(struct net_device *dev,
810                                   u8 autoneg, u16 speed, u8 duplex)
811 {
812         struct rtl8169_private *tp = netdev_priv(dev);
813         void __iomem *ioaddr = tp->mmio_addr;
814         int auto_nego, giga_ctrl;
815
816         auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
817         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
818                        ADVERTISE_100HALF | ADVERTISE_100FULL);
819         giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
820         giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
821
822         if (autoneg == AUTONEG_ENABLE) {
823                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
824                               ADVERTISE_100HALF | ADVERTISE_100FULL);
825                 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
826         } else {
827                 if (speed == SPEED_10)
828                         auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
829                 else if (speed == SPEED_100)
830                         auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
831                 else if (speed == SPEED_1000)
832                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
833
834                 if (duplex == DUPLEX_HALF)
835                         auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
836
837                 if (duplex == DUPLEX_FULL)
838                         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
839
840                 /* This tweak comes straight from Realtek's driver. */
841                 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
842                     ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
843                      (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
844                         auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
845                 }
846         }
847
848         /* The 8100e/8101e/8102e do Fast Ethernet only. */
849         if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
850             (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
851             (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
852             (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
853             (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
854             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
855             (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
856             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
857                 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
858                     netif_msg_link(tp)) {
859                         printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
860                                dev->name);
861                 }
862                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
863         }
864
865         auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
866
867         if ((tp->mac_version == RTL_GIGA_MAC_VER_12) ||
868             (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
869                 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
870                 mdio_write(ioaddr, 0x1f, 0x0000);
871                 mdio_write(ioaddr, 0x0e, 0x0000);
872         }
873
874         tp->phy_auto_nego_reg = auto_nego;
875         tp->phy_1000_ctrl_reg = giga_ctrl;
876
877         mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
878         mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
879         mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
880         return 0;
881 }
882
883 static int rtl8169_set_speed(struct net_device *dev,
884                              u8 autoneg, u16 speed, u8 duplex)
885 {
886         struct rtl8169_private *tp = netdev_priv(dev);
887         int ret;
888
889         ret = tp->set_speed(dev, autoneg, speed, duplex);
890
891         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
892                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
893
894         return ret;
895 }
896
897 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
898 {
899         struct rtl8169_private *tp = netdev_priv(dev);
900         unsigned long flags;
901         int ret;
902
903         spin_lock_irqsave(&tp->lock, flags);
904         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
905         spin_unlock_irqrestore(&tp->lock, flags);
906
907         return ret;
908 }
909
910 static u32 rtl8169_get_rx_csum(struct net_device *dev)
911 {
912         struct rtl8169_private *tp = netdev_priv(dev);
913
914         return tp->cp_cmd & RxChkSum;
915 }
916
917 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
918 {
919         struct rtl8169_private *tp = netdev_priv(dev);
920         void __iomem *ioaddr = tp->mmio_addr;
921         unsigned long flags;
922
923         spin_lock_irqsave(&tp->lock, flags);
924
925         if (data)
926                 tp->cp_cmd |= RxChkSum;
927         else
928                 tp->cp_cmd &= ~RxChkSum;
929
930         RTL_W16(CPlusCmd, tp->cp_cmd);
931         RTL_R16(CPlusCmd);
932
933         spin_unlock_irqrestore(&tp->lock, flags);
934
935         return 0;
936 }
937
938 #ifdef CONFIG_R8169_VLAN
939
940 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
941                                       struct sk_buff *skb)
942 {
943         return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
944                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
945 }
946
947 static void rtl8169_vlan_rx_register(struct net_device *dev,
948                                      struct vlan_group *grp)
949 {
950         struct rtl8169_private *tp = netdev_priv(dev);
951         void __iomem *ioaddr = tp->mmio_addr;
952         unsigned long flags;
953
954         spin_lock_irqsave(&tp->lock, flags);
955         tp->vlgrp = grp;
956         if (tp->vlgrp)
957                 tp->cp_cmd |= RxVlan;
958         else
959                 tp->cp_cmd &= ~RxVlan;
960         RTL_W16(CPlusCmd, tp->cp_cmd);
961         RTL_R16(CPlusCmd);
962         spin_unlock_irqrestore(&tp->lock, flags);
963 }
964
965 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
966                                struct sk_buff *skb)
967 {
968         u32 opts2 = le32_to_cpu(desc->opts2);
969         struct vlan_group *vlgrp = tp->vlgrp;
970         int ret;
971
972         if (vlgrp && (opts2 & RxVlanTag)) {
973                 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
974                 ret = 0;
975         } else
976                 ret = -1;
977         desc->opts2 = 0;
978         return ret;
979 }
980
981 #else /* !CONFIG_R8169_VLAN */
982
983 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
984                                       struct sk_buff *skb)
985 {
986         return 0;
987 }
988
989 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
990                                struct sk_buff *skb)
991 {
992         return -1;
993 }
994
995 #endif
996
997 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
998 {
999         struct rtl8169_private *tp = netdev_priv(dev);
1000         void __iomem *ioaddr = tp->mmio_addr;
1001         u32 status;
1002
1003         cmd->supported =
1004                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1005         cmd->port = PORT_FIBRE;
1006         cmd->transceiver = XCVR_INTERNAL;
1007
1008         status = RTL_R32(TBICSR);
1009         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1010         cmd->autoneg = !!(status & TBINwEnable);
1011
1012         cmd->speed = SPEED_1000;
1013         cmd->duplex = DUPLEX_FULL; /* Always set */
1014
1015         return 0;
1016 }
1017
1018 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1019 {
1020         struct rtl8169_private *tp = netdev_priv(dev);
1021
1022         return mii_ethtool_gset(&tp->mii, cmd);
1023 }
1024
1025 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1026 {
1027         struct rtl8169_private *tp = netdev_priv(dev);
1028         unsigned long flags;
1029         int rc;
1030
1031         spin_lock_irqsave(&tp->lock, flags);
1032
1033         rc = tp->get_settings(dev, cmd);
1034
1035         spin_unlock_irqrestore(&tp->lock, flags);
1036         return rc;
1037 }
1038
1039 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1040                              void *p)
1041 {
1042         struct rtl8169_private *tp = netdev_priv(dev);
1043         unsigned long flags;
1044
1045         if (regs->len > R8169_REGS_SIZE)
1046                 regs->len = R8169_REGS_SIZE;
1047
1048         spin_lock_irqsave(&tp->lock, flags);
1049         memcpy_fromio(p, tp->mmio_addr, regs->len);
1050         spin_unlock_irqrestore(&tp->lock, flags);
1051 }
1052
1053 static u32 rtl8169_get_msglevel(struct net_device *dev)
1054 {
1055         struct rtl8169_private *tp = netdev_priv(dev);
1056
1057         return tp->msg_enable;
1058 }
1059
1060 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1061 {
1062         struct rtl8169_private *tp = netdev_priv(dev);
1063
1064         tp->msg_enable = value;
1065 }
1066
1067 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1068         "tx_packets",
1069         "rx_packets",
1070         "tx_errors",
1071         "rx_errors",
1072         "rx_missed",
1073         "align_errors",
1074         "tx_single_collisions",
1075         "tx_multi_collisions",
1076         "unicast",
1077         "broadcast",
1078         "multicast",
1079         "tx_aborted",
1080         "tx_underrun",
1081 };
1082
1083 struct rtl8169_counters {
1084         __le64  tx_packets;
1085         __le64  rx_packets;
1086         __le64  tx_errors;
1087         __le32  rx_errors;
1088         __le16  rx_missed;
1089         __le16  align_errors;
1090         __le32  tx_one_collision;
1091         __le32  tx_multi_collision;
1092         __le64  rx_unicast;
1093         __le64  rx_broadcast;
1094         __le32  rx_multicast;
1095         __le16  tx_aborted;
1096         __le16  tx_underun;
1097 };
1098
1099 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1100 {
1101         switch (sset) {
1102         case ETH_SS_STATS:
1103                 return ARRAY_SIZE(rtl8169_gstrings);
1104         default:
1105                 return -EOPNOTSUPP;
1106         }
1107 }
1108
1109 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1110                                       struct ethtool_stats *stats, u64 *data)
1111 {
1112         struct rtl8169_private *tp = netdev_priv(dev);
1113         void __iomem *ioaddr = tp->mmio_addr;
1114         struct rtl8169_counters *counters;
1115         dma_addr_t paddr;
1116         u32 cmd;
1117
1118         ASSERT_RTNL();
1119
1120         counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1121         if (!counters)
1122                 return;
1123
1124         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1125         cmd = (u64)paddr & DMA_32BIT_MASK;
1126         RTL_W32(CounterAddrLow, cmd);
1127         RTL_W32(CounterAddrLow, cmd | CounterDump);
1128
1129         while (RTL_R32(CounterAddrLow) & CounterDump) {
1130                 if (msleep_interruptible(1))
1131                         break;
1132         }
1133
1134         RTL_W32(CounterAddrLow, 0);
1135         RTL_W32(CounterAddrHigh, 0);
1136
1137         data[0] = le64_to_cpu(counters->tx_packets);
1138         data[1] = le64_to_cpu(counters->rx_packets);
1139         data[2] = le64_to_cpu(counters->tx_errors);
1140         data[3] = le32_to_cpu(counters->rx_errors);
1141         data[4] = le16_to_cpu(counters->rx_missed);
1142         data[5] = le16_to_cpu(counters->align_errors);
1143         data[6] = le32_to_cpu(counters->tx_one_collision);
1144         data[7] = le32_to_cpu(counters->tx_multi_collision);
1145         data[8] = le64_to_cpu(counters->rx_unicast);
1146         data[9] = le64_to_cpu(counters->rx_broadcast);
1147         data[10] = le32_to_cpu(counters->rx_multicast);
1148         data[11] = le16_to_cpu(counters->tx_aborted);
1149         data[12] = le16_to_cpu(counters->tx_underun);
1150
1151         pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1152 }
1153
1154 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1155 {
1156         switch(stringset) {
1157         case ETH_SS_STATS:
1158                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1159                 break;
1160         }
1161 }
1162
1163 static const struct ethtool_ops rtl8169_ethtool_ops = {
1164         .get_drvinfo            = rtl8169_get_drvinfo,
1165         .get_regs_len           = rtl8169_get_regs_len,
1166         .get_link               = ethtool_op_get_link,
1167         .get_settings           = rtl8169_get_settings,
1168         .set_settings           = rtl8169_set_settings,
1169         .get_msglevel           = rtl8169_get_msglevel,
1170         .set_msglevel           = rtl8169_set_msglevel,
1171         .get_rx_csum            = rtl8169_get_rx_csum,
1172         .set_rx_csum            = rtl8169_set_rx_csum,
1173         .set_tx_csum            = ethtool_op_set_tx_csum,
1174         .set_sg                 = ethtool_op_set_sg,
1175         .set_tso                = ethtool_op_set_tso,
1176         .get_regs               = rtl8169_get_regs,
1177         .get_wol                = rtl8169_get_wol,
1178         .set_wol                = rtl8169_set_wol,
1179         .get_strings            = rtl8169_get_strings,
1180         .get_sset_count         = rtl8169_get_sset_count,
1181         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1182 };
1183
1184 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1185                                        int bitnum, int bitval)
1186 {
1187         int val;
1188
1189         val = mdio_read(ioaddr, reg);
1190         val = (bitval == 1) ?
1191                 val | (bitval << bitnum) :  val & ~(0x0001 << bitnum);
1192         mdio_write(ioaddr, reg, val & 0xffff);
1193 }
1194
1195 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1196                                     void __iomem *ioaddr)
1197 {
1198         /*
1199          * The driver currently handles the 8168Bf and the 8168Be identically
1200          * but they can be identified more specifically through the test below
1201          * if needed:
1202          *
1203          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1204          *
1205          * Same thing for the 8101Eb and the 8101Ec:
1206          *
1207          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1208          */
1209         const struct {
1210                 u32 mask;
1211                 u32 val;
1212                 int mac_version;
1213         } mac_info[] = {
1214                 /* 8168B family. */
1215                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1216                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1217                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1218                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_20 },
1219
1220                 /* 8168B family. */
1221                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1222                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1223                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1224                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1225
1226                 /* 8101 family. */
1227                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1228                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1229                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1230                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1231                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1232                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1233                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1234                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1235                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1236                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1237                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1238                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1239                 /* FIXME: where did these entries come from ? -- FR */
1240                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1241                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1242
1243                 /* 8110 family. */
1244                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1245                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1246                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1247                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1248                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1249                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1250
1251                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_VER_01 }   /* Catch-all */
1252         }, *p = mac_info;
1253         u32 reg;
1254
1255         reg = RTL_R32(TxConfig);
1256         while ((reg & p->mask) != p->val)
1257                 p++;
1258         tp->mac_version = p->mac_version;
1259
1260         if (p->mask == 0x00000000) {
1261                 struct pci_dev *pdev = tp->pci_dev;
1262
1263                 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1264         }
1265 }
1266
1267 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1268 {
1269         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1270 }
1271
1272 struct phy_reg {
1273         u16 reg;
1274         u16 val;
1275 };
1276
1277 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1278 {
1279         while (len-- > 0) {
1280                 mdio_write(ioaddr, regs->reg, regs->val);
1281                 regs++;
1282         }
1283 }
1284
1285 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1286 {
1287         struct {
1288                 u16 regs[5]; /* Beware of bit-sign propagation */
1289         } phy_magic[5] = { {
1290                 { 0x0000,       //w 4 15 12 0
1291                   0x00a1,       //w 3 15 0 00a1
1292                   0x0008,       //w 2 15 0 0008
1293                   0x1020,       //w 1 15 0 1020
1294                   0x1000 } },{  //w 0 15 0 1000
1295                 { 0x7000,       //w 4 15 12 7
1296                   0xff41,       //w 3 15 0 ff41
1297                   0xde60,       //w 2 15 0 de60
1298                   0x0140,       //w 1 15 0 0140
1299                   0x0077 } },{  //w 0 15 0 0077
1300                 { 0xa000,       //w 4 15 12 a
1301                   0xdf01,       //w 3 15 0 df01
1302                   0xdf20,       //w 2 15 0 df20
1303                   0xff95,       //w 1 15 0 ff95
1304                   0xfa00 } },{  //w 0 15 0 fa00
1305                 { 0xb000,       //w 4 15 12 b
1306                   0xff41,       //w 3 15 0 ff41
1307                   0xde20,       //w 2 15 0 de20
1308                   0x0140,       //w 1 15 0 0140
1309                   0x00bb } },{  //w 0 15 0 00bb
1310                 { 0xf000,       //w 4 15 12 f
1311                   0xdf01,       //w 3 15 0 df01
1312                   0xdf20,       //w 2 15 0 df20
1313                   0xff95,       //w 1 15 0 ff95
1314                   0xbf00 }      //w 0 15 0 bf00
1315                 }
1316         }, *p = phy_magic;
1317         unsigned int i;
1318
1319         mdio_write(ioaddr, 0x1f, 0x0001);               //w 31 2 0 1
1320         mdio_write(ioaddr, 0x15, 0x1000);               //w 21 15 0 1000
1321         mdio_write(ioaddr, 0x18, 0x65c7);               //w 24 15 0 65c7
1322         rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
1323
1324         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1325                 int val, pos = 4;
1326
1327                 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1328                 mdio_write(ioaddr, pos, val);
1329                 while (--pos >= 0)
1330                         mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1331                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1332                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1333         }
1334         mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1335 }
1336
1337 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1338 {
1339         struct phy_reg phy_reg_init[] = {
1340                 { 0x1f, 0x0002 },
1341                 { 0x01, 0x90d0 },
1342                 { 0x1f, 0x0000 }
1343         };
1344
1345         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1346 }
1347
1348 static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1349 {
1350         struct phy_reg phy_reg_init[] = {
1351                 { 0x1f, 0x0000 },
1352                 { 0x1d, 0x0f00 },
1353                 { 0x1f, 0x0002 },
1354                 { 0x0c, 0x1ec8 },
1355                 { 0x1f, 0x0000 }
1356         };
1357
1358         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1359 }
1360
1361 static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
1362 {
1363         struct phy_reg phy_reg_init[] = {
1364                 { 0x1f, 0x0001 },
1365                 { 0x12, 0x2300 },
1366                 { 0x1f, 0x0002 },
1367                 { 0x00, 0x88d4 },
1368                 { 0x01, 0x82b1 },
1369                 { 0x03, 0x7002 },
1370                 { 0x08, 0x9e30 },
1371                 { 0x09, 0x01f0 },
1372                 { 0x0a, 0x5500 },
1373                 { 0x0c, 0x00c8 },
1374                 { 0x1f, 0x0003 },
1375                 { 0x12, 0xc096 },
1376                 { 0x16, 0x000a },
1377                 { 0x1f, 0x0000 }
1378         };
1379
1380         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1381 }
1382
1383 static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
1384 {
1385         struct phy_reg phy_reg_init[] = {
1386                 { 0x1f, 0x0000 },
1387                 { 0x12, 0x2300 },
1388                 { 0x1f, 0x0003 },
1389                 { 0x16, 0x0f0a },
1390                 { 0x1f, 0x0000 },
1391                 { 0x1f, 0x0002 },
1392                 { 0x0c, 0x7eb8 },
1393                 { 0x1f, 0x0000 }
1394         };
1395
1396         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1397 }
1398
1399 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1400 {
1401         struct phy_reg phy_reg_init[] = {
1402                 { 0x1f, 0x0003 },
1403                 { 0x08, 0x441d },
1404                 { 0x01, 0x9100 },
1405                 { 0x1f, 0x0000 }
1406         };
1407
1408         mdio_write(ioaddr, 0x1f, 0x0000);
1409         mdio_patch(ioaddr, 0x11, 1 << 12);
1410         mdio_patch(ioaddr, 0x19, 1 << 13);
1411
1412         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1413 }
1414
1415 static void rtl_hw_phy_config(struct net_device *dev)
1416 {
1417         struct rtl8169_private *tp = netdev_priv(dev);
1418         void __iomem *ioaddr = tp->mmio_addr;
1419
1420         rtl8169_print_mac_version(tp);
1421
1422         switch (tp->mac_version) {
1423         case RTL_GIGA_MAC_VER_01:
1424                 break;
1425         case RTL_GIGA_MAC_VER_02:
1426         case RTL_GIGA_MAC_VER_03:
1427                 rtl8169s_hw_phy_config(ioaddr);
1428                 break;
1429         case RTL_GIGA_MAC_VER_04:
1430                 rtl8169sb_hw_phy_config(ioaddr);
1431                 break;
1432         case RTL_GIGA_MAC_VER_07:
1433         case RTL_GIGA_MAC_VER_08:
1434         case RTL_GIGA_MAC_VER_09:
1435                 rtl8102e_hw_phy_config(ioaddr);
1436                 break;
1437         case RTL_GIGA_MAC_VER_18:
1438                 rtl8168cp_hw_phy_config(ioaddr);
1439                 break;
1440         case RTL_GIGA_MAC_VER_19:
1441                 rtl8168c_hw_phy_config(ioaddr);
1442                 break;
1443         case RTL_GIGA_MAC_VER_20:
1444                 rtl8168cx_hw_phy_config(ioaddr);
1445                 break;
1446         default:
1447                 break;
1448         }
1449 }
1450
1451 static void rtl8169_phy_timer(unsigned long __opaque)
1452 {
1453         struct net_device *dev = (struct net_device *)__opaque;
1454         struct rtl8169_private *tp = netdev_priv(dev);
1455         struct timer_list *timer = &tp->timer;
1456         void __iomem *ioaddr = tp->mmio_addr;
1457         unsigned long timeout = RTL8169_PHY_TIMEOUT;
1458
1459         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1460
1461         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1462                 return;
1463
1464         spin_lock_irq(&tp->lock);
1465
1466         if (tp->phy_reset_pending(ioaddr)) {
1467                 /*
1468                  * A busy loop could burn quite a few cycles on nowadays CPU.
1469                  * Let's delay the execution of the timer for a few ticks.
1470                  */
1471                 timeout = HZ/10;
1472                 goto out_mod_timer;
1473         }
1474
1475         if (tp->link_ok(ioaddr))
1476                 goto out_unlock;
1477
1478         if (netif_msg_link(tp))
1479                 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1480
1481         tp->phy_reset_enable(ioaddr);
1482
1483 out_mod_timer:
1484         mod_timer(timer, jiffies + timeout);
1485 out_unlock:
1486         spin_unlock_irq(&tp->lock);
1487 }
1488
1489 static inline void rtl8169_delete_timer(struct net_device *dev)
1490 {
1491         struct rtl8169_private *tp = netdev_priv(dev);
1492         struct timer_list *timer = &tp->timer;
1493
1494         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1495                 return;
1496
1497         del_timer_sync(timer);
1498 }
1499
1500 static inline void rtl8169_request_timer(struct net_device *dev)
1501 {
1502         struct rtl8169_private *tp = netdev_priv(dev);
1503         struct timer_list *timer = &tp->timer;
1504
1505         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1506                 return;
1507
1508         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1509 }
1510
1511 #ifdef CONFIG_NET_POLL_CONTROLLER
1512 /*
1513  * Polling 'interrupt' - used by things like netconsole to send skbs
1514  * without having to re-enable interrupts. It's not called while
1515  * the interrupt routine is executing.
1516  */
1517 static void rtl8169_netpoll(struct net_device *dev)
1518 {
1519         struct rtl8169_private *tp = netdev_priv(dev);
1520         struct pci_dev *pdev = tp->pci_dev;
1521
1522         disable_irq(pdev->irq);
1523         rtl8169_interrupt(pdev->irq, dev);
1524         enable_irq(pdev->irq);
1525 }
1526 #endif
1527
1528 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1529                                   void __iomem *ioaddr)
1530 {
1531         iounmap(ioaddr);
1532         pci_release_regions(pdev);
1533         pci_disable_device(pdev);
1534         free_netdev(dev);
1535 }
1536
1537 static void rtl8169_phy_reset(struct net_device *dev,
1538                               struct rtl8169_private *tp)
1539 {
1540         void __iomem *ioaddr = tp->mmio_addr;
1541         unsigned int i;
1542
1543         tp->phy_reset_enable(ioaddr);
1544         for (i = 0; i < 100; i++) {
1545                 if (!tp->phy_reset_pending(ioaddr))
1546                         return;
1547                 msleep(1);
1548         }
1549         if (netif_msg_link(tp))
1550                 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1551 }
1552
1553 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1554 {
1555         void __iomem *ioaddr = tp->mmio_addr;
1556
1557         rtl_hw_phy_config(dev);
1558
1559         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1560                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1561                 RTL_W8(0x82, 0x01);
1562         }
1563
1564         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1565
1566         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1567                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1568
1569         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1570                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1571                 RTL_W8(0x82, 0x01);
1572                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1573                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1574         }
1575
1576         rtl8169_phy_reset(dev, tp);
1577
1578         /*
1579          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1580          * only 8101. Don't panic.
1581          */
1582         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1583
1584         if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1585                 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1586 }
1587
1588 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1589 {
1590         void __iomem *ioaddr = tp->mmio_addr;
1591         u32 high;
1592         u32 low;
1593
1594         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1595         high = addr[4] | (addr[5] << 8);
1596
1597         spin_lock_irq(&tp->lock);
1598
1599         RTL_W8(Cfg9346, Cfg9346_Unlock);
1600         RTL_W32(MAC0, low);
1601         RTL_W32(MAC4, high);
1602         RTL_W8(Cfg9346, Cfg9346_Lock);
1603
1604         spin_unlock_irq(&tp->lock);
1605 }
1606
1607 static int rtl_set_mac_address(struct net_device *dev, void *p)
1608 {
1609         struct rtl8169_private *tp = netdev_priv(dev);
1610         struct sockaddr *addr = p;
1611
1612         if (!is_valid_ether_addr(addr->sa_data))
1613                 return -EADDRNOTAVAIL;
1614
1615         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1616
1617         rtl_rar_set(tp, dev->dev_addr);
1618
1619         return 0;
1620 }
1621
1622 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1623 {
1624         struct rtl8169_private *tp = netdev_priv(dev);
1625         struct mii_ioctl_data *data = if_mii(ifr);
1626
1627         if (!netif_running(dev))
1628                 return -ENODEV;
1629
1630         switch (cmd) {
1631         case SIOCGMIIPHY:
1632                 data->phy_id = 32; /* Internal PHY */
1633                 return 0;
1634
1635         case SIOCGMIIREG:
1636                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1637                 return 0;
1638
1639         case SIOCSMIIREG:
1640                 if (!capable(CAP_NET_ADMIN))
1641                         return -EPERM;
1642                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1643                 return 0;
1644         }
1645         return -EOPNOTSUPP;
1646 }
1647
1648 static const struct rtl_cfg_info {
1649         void (*hw_start)(struct net_device *);
1650         unsigned int region;
1651         unsigned int align;
1652         u16 intr_event;
1653         u16 napi_event;
1654         unsigned features;
1655 } rtl_cfg_infos [] = {
1656         [RTL_CFG_0] = {
1657                 .hw_start       = rtl_hw_start_8169,
1658                 .region         = 1,
1659                 .align          = 0,
1660                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1661                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1662                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1663                 .features       = RTL_FEATURE_GMII
1664         },
1665         [RTL_CFG_1] = {
1666                 .hw_start       = rtl_hw_start_8168,
1667                 .region         = 2,
1668                 .align          = 8,
1669                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1670                                   TxErr | TxOK | RxOK | RxErr,
1671                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
1672                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI
1673         },
1674         [RTL_CFG_2] = {
1675                 .hw_start       = rtl_hw_start_8101,
1676                 .region         = 2,
1677                 .align          = 8,
1678                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1679                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1680                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1681                 .features       = RTL_FEATURE_MSI
1682         }
1683 };
1684
1685 /* Cfg9346_Unlock assumed. */
1686 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1687                             const struct rtl_cfg_info *cfg)
1688 {
1689         unsigned msi = 0;
1690         u8 cfg2;
1691
1692         cfg2 = RTL_R8(Config2) & ~MSIEnable;
1693         if (cfg->features & RTL_FEATURE_MSI) {
1694                 if (pci_enable_msi(pdev)) {
1695                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1696                 } else {
1697                         cfg2 |= MSIEnable;
1698                         msi = RTL_FEATURE_MSI;
1699                 }
1700         }
1701         RTL_W8(Config2, cfg2);
1702         return msi;
1703 }
1704
1705 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1706 {
1707         if (tp->features & RTL_FEATURE_MSI) {
1708                 pci_disable_msi(pdev);
1709                 tp->features &= ~RTL_FEATURE_MSI;
1710         }
1711 }
1712
1713 static int __devinit
1714 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1715 {
1716         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1717         const unsigned int region = cfg->region;
1718         struct rtl8169_private *tp;
1719         struct mii_if_info *mii;
1720         struct net_device *dev;
1721         void __iomem *ioaddr;
1722         unsigned int i;
1723         int rc;
1724
1725         if (netif_msg_drv(&debug)) {
1726                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1727                        MODULENAME, RTL8169_VERSION);
1728         }
1729
1730         dev = alloc_etherdev(sizeof (*tp));
1731         if (!dev) {
1732                 if (netif_msg_drv(&debug))
1733                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1734                 rc = -ENOMEM;
1735                 goto out;
1736         }
1737
1738         SET_NETDEV_DEV(dev, &pdev->dev);
1739         tp = netdev_priv(dev);
1740         tp->dev = dev;
1741         tp->pci_dev = pdev;
1742         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1743
1744         mii = &tp->mii;
1745         mii->dev = dev;
1746         mii->mdio_read = rtl_mdio_read;
1747         mii->mdio_write = rtl_mdio_write;
1748         mii->phy_id_mask = 0x1f;
1749         mii->reg_num_mask = 0x1f;
1750         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1751
1752         /* enable device (incl. PCI PM wakeup and hotplug setup) */
1753         rc = pci_enable_device(pdev);
1754         if (rc < 0) {
1755                 if (netif_msg_probe(tp))
1756                         dev_err(&pdev->dev, "enable failure\n");
1757                 goto err_out_free_dev_1;
1758         }
1759
1760         rc = pci_set_mwi(pdev);
1761         if (rc < 0)
1762                 goto err_out_disable_2;
1763
1764         /* make sure PCI base addr 1 is MMIO */
1765         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1766                 if (netif_msg_probe(tp)) {
1767                         dev_err(&pdev->dev,
1768                                 "region #%d not an MMIO resource, aborting\n",
1769                                 region);
1770                 }
1771                 rc = -ENODEV;
1772                 goto err_out_mwi_3;
1773         }
1774
1775         /* check for weird/broken PCI region reporting */
1776         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1777                 if (netif_msg_probe(tp)) {
1778                         dev_err(&pdev->dev,
1779                                 "Invalid PCI region size(s), aborting\n");
1780                 }
1781                 rc = -ENODEV;
1782                 goto err_out_mwi_3;
1783         }
1784
1785         rc = pci_request_regions(pdev, MODULENAME);
1786         if (rc < 0) {
1787                 if (netif_msg_probe(tp))
1788                         dev_err(&pdev->dev, "could not request regions.\n");
1789                 goto err_out_mwi_3;
1790         }
1791
1792         tp->cp_cmd = PCIMulRW | RxChkSum;
1793
1794         if ((sizeof(dma_addr_t) > 4) &&
1795             !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1796                 tp->cp_cmd |= PCIDAC;
1797                 dev->features |= NETIF_F_HIGHDMA;
1798         } else {
1799                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1800                 if (rc < 0) {
1801                         if (netif_msg_probe(tp)) {
1802                                 dev_err(&pdev->dev,
1803                                         "DMA configuration failed.\n");
1804                         }
1805                         goto err_out_free_res_4;
1806                 }
1807         }
1808
1809         pci_set_master(pdev);
1810
1811         /* ioremap MMIO region */
1812         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1813         if (!ioaddr) {
1814                 if (netif_msg_probe(tp))
1815                         dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1816                 rc = -EIO;
1817                 goto err_out_free_res_4;
1818         }
1819
1820         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1821         if (!tp->pcie_cap && netif_msg_probe(tp))
1822                 dev_info(&pdev->dev, "no PCI Express capability\n");
1823
1824         /* Unneeded ? Don't mess with Mrs. Murphy. */
1825         rtl8169_irq_mask_and_ack(ioaddr);
1826
1827         /* Soft reset the chip. */
1828         RTL_W8(ChipCmd, CmdReset);
1829
1830         /* Check that the chip has finished the reset. */
1831         for (i = 0; i < 100; i++) {
1832                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1833                         break;
1834                 msleep_interruptible(1);
1835         }
1836
1837         /* Identify chip attached to board */
1838         rtl8169_get_mac_version(tp, ioaddr);
1839
1840         rtl8169_print_mac_version(tp);
1841
1842         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1843                 if (tp->mac_version == rtl_chip_info[i].mac_version)
1844                         break;
1845         }
1846         if (i == ARRAY_SIZE(rtl_chip_info)) {
1847                 /* Unknown chip: assume array element #0, original RTL-8169 */
1848                 if (netif_msg_probe(tp)) {
1849                         dev_printk(KERN_DEBUG, &pdev->dev,
1850                                 "unknown chip version, assuming %s\n",
1851                                 rtl_chip_info[0].name);
1852                 }
1853                 i = 0;
1854         }
1855         tp->chipset = i;
1856
1857         RTL_W8(Cfg9346, Cfg9346_Unlock);
1858         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1859         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1860         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
1861         RTL_W8(Cfg9346, Cfg9346_Lock);
1862
1863         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
1864             (RTL_R8(PHYstatus) & TBI_Enable)) {
1865                 tp->set_speed = rtl8169_set_speed_tbi;
1866                 tp->get_settings = rtl8169_gset_tbi;
1867                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1868                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1869                 tp->link_ok = rtl8169_tbi_link_ok;
1870
1871                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1872         } else {
1873                 tp->set_speed = rtl8169_set_speed_xmii;
1874                 tp->get_settings = rtl8169_gset_xmii;
1875                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1876                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1877                 tp->link_ok = rtl8169_xmii_link_ok;
1878
1879                 dev->do_ioctl = rtl8169_ioctl;
1880         }
1881
1882         /* Get MAC address.  FIXME: read EEPROM */
1883         for (i = 0; i < MAC_ADDR_LEN; i++)
1884                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1885         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1886
1887         dev->open = rtl8169_open;
1888         dev->hard_start_xmit = rtl8169_start_xmit;
1889         dev->get_stats = rtl8169_get_stats;
1890         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1891         dev->stop = rtl8169_close;
1892         dev->tx_timeout = rtl8169_tx_timeout;
1893         dev->set_multicast_list = rtl_set_rx_mode;
1894         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1895         dev->irq = pdev->irq;
1896         dev->base_addr = (unsigned long) ioaddr;
1897         dev->change_mtu = rtl8169_change_mtu;
1898         dev->set_mac_address = rtl_set_mac_address;
1899
1900         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1901
1902 #ifdef CONFIG_R8169_VLAN
1903         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1904         dev->vlan_rx_register = rtl8169_vlan_rx_register;
1905 #endif
1906
1907 #ifdef CONFIG_NET_POLL_CONTROLLER
1908         dev->poll_controller = rtl8169_netpoll;
1909 #endif
1910
1911         tp->intr_mask = 0xffff;
1912         tp->mmio_addr = ioaddr;
1913         tp->align = cfg->align;
1914         tp->hw_start = cfg->hw_start;
1915         tp->intr_event = cfg->intr_event;
1916         tp->napi_event = cfg->napi_event;
1917
1918         init_timer(&tp->timer);
1919         tp->timer.data = (unsigned long) dev;
1920         tp->timer.function = rtl8169_phy_timer;
1921
1922         spin_lock_init(&tp->lock);
1923
1924         rc = register_netdev(dev);
1925         if (rc < 0)
1926                 goto err_out_msi_5;
1927
1928         pci_set_drvdata(pdev, dev);
1929
1930         if (netif_msg_probe(tp)) {
1931                 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1932
1933                 printk(KERN_INFO "%s: %s at 0x%lx, "
1934                        "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1935                        "XID %08x IRQ %d\n",
1936                        dev->name,
1937                        rtl_chip_info[tp->chipset].name,
1938                        dev->base_addr,
1939                        dev->dev_addr[0], dev->dev_addr[1],
1940                        dev->dev_addr[2], dev->dev_addr[3],
1941                        dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
1942         }
1943
1944         rtl8169_init_phy(dev, tp);
1945
1946 out:
1947         return rc;
1948
1949 err_out_msi_5:
1950         rtl_disable_msi(pdev, tp);
1951         iounmap(ioaddr);
1952 err_out_free_res_4:
1953         pci_release_regions(pdev);
1954 err_out_mwi_3:
1955         pci_clear_mwi(pdev);
1956 err_out_disable_2:
1957         pci_disable_device(pdev);
1958 err_out_free_dev_1:
1959         free_netdev(dev);
1960         goto out;
1961 }
1962
1963 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1964 {
1965         struct net_device *dev = pci_get_drvdata(pdev);
1966         struct rtl8169_private *tp = netdev_priv(dev);
1967
1968         flush_scheduled_work();
1969
1970         unregister_netdev(dev);
1971         rtl_disable_msi(pdev, tp);
1972         rtl8169_release_board(pdev, dev, tp->mmio_addr);
1973         pci_set_drvdata(pdev, NULL);
1974 }
1975
1976 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1977                                   struct net_device *dev)
1978 {
1979         unsigned int mtu = dev->mtu;
1980
1981         tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1982 }
1983
1984 static int rtl8169_open(struct net_device *dev)
1985 {
1986         struct rtl8169_private *tp = netdev_priv(dev);
1987         struct pci_dev *pdev = tp->pci_dev;
1988         int retval = -ENOMEM;
1989
1990
1991         rtl8169_set_rxbufsize(tp, dev);
1992
1993         /*
1994          * Rx and Tx desscriptors needs 256 bytes alignment.
1995          * pci_alloc_consistent provides more.
1996          */
1997         tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1998                                                &tp->TxPhyAddr);
1999         if (!tp->TxDescArray)
2000                 goto out;
2001
2002         tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2003                                                &tp->RxPhyAddr);
2004         if (!tp->RxDescArray)
2005                 goto err_free_tx_0;
2006
2007         retval = rtl8169_init_ring(dev);
2008         if (retval < 0)
2009                 goto err_free_rx_1;
2010
2011         INIT_DELAYED_WORK(&tp->task, NULL);
2012
2013         smp_mb();
2014
2015         retval = request_irq(dev->irq, rtl8169_interrupt,
2016                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2017                              dev->name, dev);
2018         if (retval < 0)
2019                 goto err_release_ring_2;
2020
2021         napi_enable(&tp->napi);
2022
2023         rtl_hw_start(dev);
2024
2025         rtl8169_request_timer(dev);
2026
2027         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2028 out:
2029         return retval;
2030
2031 err_release_ring_2:
2032         rtl8169_rx_clear(tp);
2033 err_free_rx_1:
2034         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2035                             tp->RxPhyAddr);
2036 err_free_tx_0:
2037         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2038                             tp->TxPhyAddr);
2039         goto out;
2040 }
2041
2042 static void rtl8169_hw_reset(void __iomem *ioaddr)
2043 {
2044         /* Disable interrupts */
2045         rtl8169_irq_mask_and_ack(ioaddr);
2046
2047         /* Reset the chipset */
2048         RTL_W8(ChipCmd, CmdReset);
2049
2050         /* PCI commit */
2051         RTL_R8(ChipCmd);
2052 }
2053
2054 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
2055 {
2056         void __iomem *ioaddr = tp->mmio_addr;
2057         u32 cfg = rtl8169_rx_config;
2058
2059         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2060         RTL_W32(RxConfig, cfg);
2061
2062         /* Set DMA burst size and Interframe Gap Time */
2063         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2064                 (InterFrameGap << TxInterFrameGapShift));
2065 }
2066
2067 static void rtl_hw_start(struct net_device *dev)
2068 {
2069         struct rtl8169_private *tp = netdev_priv(dev);
2070         void __iomem *ioaddr = tp->mmio_addr;
2071         unsigned int i;
2072
2073         /* Soft reset the chip. */
2074         RTL_W8(ChipCmd, CmdReset);
2075
2076         /* Check that the chip has finished the reset. */
2077         for (i = 0; i < 100; i++) {
2078                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2079                         break;
2080                 msleep_interruptible(1);
2081         }
2082
2083         tp->hw_start(dev);
2084
2085         netif_start_queue(dev);
2086 }
2087
2088
2089 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2090                                          void __iomem *ioaddr)
2091 {
2092         /*
2093          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2094          * register to be written before TxDescAddrLow to work.
2095          * Switching from MMIO to I/O access fixes the issue as well.
2096          */
2097         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2098         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
2099         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2100         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
2101 }
2102
2103 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2104 {
2105         u16 cmd;
2106
2107         cmd = RTL_R16(CPlusCmd);
2108         RTL_W16(CPlusCmd, cmd);
2109         return cmd;
2110 }
2111
2112 static void rtl_set_rx_max_size(void __iomem *ioaddr)
2113 {
2114         /* Low hurts. Let's disable the filtering. */
2115         RTL_W16(RxMaxSize, 16383);
2116 }
2117
2118 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2119 {
2120         struct {
2121                 u32 mac_version;
2122                 u32 clk;
2123                 u32 val;
2124         } cfg2_info [] = {
2125                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2126                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2127                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2128                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2129         }, *p = cfg2_info;
2130         unsigned int i;
2131         u32 clk;
2132
2133         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2134         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2135                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2136                         RTL_W32(0x7c, p->val);
2137                         break;
2138                 }
2139         }
2140 }
2141
2142 static void rtl_hw_start_8169(struct net_device *dev)
2143 {
2144         struct rtl8169_private *tp = netdev_priv(dev);
2145         void __iomem *ioaddr = tp->mmio_addr;
2146         struct pci_dev *pdev = tp->pci_dev;
2147
2148         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2149                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2150                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2151         }
2152
2153         RTL_W8(Cfg9346, Cfg9346_Unlock);
2154         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2155             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2156             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2157             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2158                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2159
2160         RTL_W8(EarlyTxThres, EarlyTxThld);
2161
2162         rtl_set_rx_max_size(ioaddr);
2163
2164         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2165             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2166             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2167             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2168                 rtl_set_rx_tx_config_registers(tp);
2169
2170         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2171
2172         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2173             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2174                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2175                         "Bit-3 and bit-14 MUST be 1\n");
2176                 tp->cp_cmd |= (1 << 14);
2177         }
2178
2179         RTL_W16(CPlusCmd, tp->cp_cmd);
2180
2181         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2182
2183         /*
2184          * Undocumented corner. Supposedly:
2185          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2186          */
2187         RTL_W16(IntrMitigate, 0x0000);
2188
2189         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2190
2191         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2192             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2193             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2194             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2195                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2196                 rtl_set_rx_tx_config_registers(tp);
2197         }
2198
2199         RTL_W8(Cfg9346, Cfg9346_Lock);
2200
2201         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2202         RTL_R8(IntrMask);
2203
2204         RTL_W32(RxMissed, 0);
2205
2206         rtl_set_rx_mode(dev);
2207
2208         /* no early-rx interrupts */
2209         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2210
2211         /* Enable all known interrupts by setting the interrupt mask. */
2212         RTL_W16(IntrMask, tp->intr_event);
2213 }
2214
2215 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2216 {
2217         struct net_device *dev = pci_get_drvdata(pdev);
2218         struct rtl8169_private *tp = netdev_priv(dev);
2219         int cap = tp->pcie_cap;
2220
2221         if (cap) {
2222                 u16 ctl;
2223
2224                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2225                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2226                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2227         }
2228 }
2229
2230 static void rtl_csi_access_enable(void __iomem *ioaddr)
2231 {
2232         u32 csi;
2233
2234         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2235         rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2236 }
2237
2238 struct ephy_info {
2239         unsigned int offset;
2240         u16 mask;
2241         u16 bits;
2242 };
2243
2244 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2245 {
2246         u16 w;
2247
2248         while (len-- > 0) {
2249                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2250                 rtl_ephy_write(ioaddr, e->offset, w);
2251                 e++;
2252         }
2253 }
2254
2255 static void rtl_hw_start_8168(struct net_device *dev)
2256 {
2257         struct rtl8169_private *tp = netdev_priv(dev);
2258         void __iomem *ioaddr = tp->mmio_addr;
2259         struct pci_dev *pdev = tp->pci_dev;
2260
2261         RTL_W8(Cfg9346, Cfg9346_Unlock);
2262
2263         RTL_W8(EarlyTxThres, EarlyTxThld);
2264
2265         rtl_set_rx_max_size(ioaddr);
2266
2267         rtl_set_rx_tx_config_registers(tp);
2268
2269         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2270
2271         RTL_W16(CPlusCmd, tp->cp_cmd);
2272
2273         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2274
2275         RTL_W16(IntrMitigate, 0x5151);
2276
2277         /* Work around for RxFIFO overflow. */
2278         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2279                 tp->intr_event |= RxFIFOOver | PCSTimeout;
2280                 tp->intr_event &= ~RxOverflow;
2281         }
2282
2283         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2284
2285         RTL_W8(Cfg9346, Cfg9346_Lock);
2286
2287         RTL_R8(IntrMask);
2288
2289         RTL_W32(RxMissed, 0);
2290
2291         rtl_set_rx_mode(dev);
2292
2293         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2294
2295         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2296
2297         RTL_W16(IntrMask, tp->intr_event);
2298 }
2299
2300 #define R810X_CPCMD_QUIRK_MASK (\
2301         EnableBist | \
2302         Mac_dbgo_oe | \
2303         Force_half_dup | \
2304         Force_half_dup | \
2305         Force_txflow_en | \
2306         Cxpl_dbg_sel | \
2307         ASF | \
2308         PktCntrDisable | \
2309         PCIDAC | \
2310         PCIMulRW)
2311
2312 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2313 {
2314         static struct ephy_info e_info_8102e_1[] = {
2315                 { 0x01, 0, 0x6e65 },
2316                 { 0x02, 0, 0x091f },
2317                 { 0x03, 0, 0xc2f9 },
2318                 { 0x06, 0, 0xafb5 },
2319                 { 0x07, 0, 0x0e00 },
2320                 { 0x19, 0, 0xec80 },
2321                 { 0x01, 0, 0x2e65 },
2322                 { 0x01, 0, 0x6e65 }
2323         };
2324         u8 cfg1;
2325
2326         rtl_csi_access_enable(ioaddr);
2327
2328         RTL_W8(DBG_REG, FIX_NAK_1);
2329
2330         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2331
2332         RTL_W8(Config1,
2333                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2334         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2335
2336         cfg1 = RTL_R8(Config1);
2337         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2338                 RTL_W8(Config1, cfg1 & ~LEDS0);
2339
2340         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2341
2342         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2343 }
2344
2345 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2346 {
2347         rtl_csi_access_enable(ioaddr);
2348
2349         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2350
2351         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2352         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2353
2354         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2355 }
2356
2357 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2358 {
2359         rtl_hw_start_8102e_2(ioaddr, pdev);
2360
2361         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2362 }
2363
2364 static void rtl_hw_start_8101(struct net_device *dev)
2365 {
2366         struct rtl8169_private *tp = netdev_priv(dev);
2367         void __iomem *ioaddr = tp->mmio_addr;
2368         struct pci_dev *pdev = tp->pci_dev;
2369
2370         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2371             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2372                 int cap = tp->pcie_cap;
2373
2374                 if (cap) {
2375                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2376                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
2377                 }
2378         }
2379
2380         switch (tp->mac_version) {
2381         case RTL_GIGA_MAC_VER_07:
2382                 rtl_hw_start_8102e_1(ioaddr, pdev);
2383                 break;
2384
2385         case RTL_GIGA_MAC_VER_08:
2386                 rtl_hw_start_8102e_3(ioaddr, pdev);
2387                 break;
2388
2389         case RTL_GIGA_MAC_VER_09:
2390                 rtl_hw_start_8102e_2(ioaddr, pdev);
2391                 break;
2392         }
2393
2394         RTL_W8(Cfg9346, Cfg9346_Unlock);
2395
2396         RTL_W8(EarlyTxThres, EarlyTxThld);
2397
2398         rtl_set_rx_max_size(ioaddr);
2399
2400         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2401
2402         RTL_W16(CPlusCmd, tp->cp_cmd);
2403
2404         RTL_W16(IntrMitigate, 0x0000);
2405
2406         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2407
2408         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2409         rtl_set_rx_tx_config_registers(tp);
2410
2411         RTL_W8(Cfg9346, Cfg9346_Lock);
2412
2413         RTL_R8(IntrMask);
2414
2415         RTL_W32(RxMissed, 0);
2416
2417         rtl_set_rx_mode(dev);
2418
2419         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2420
2421         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2422
2423         RTL_W16(IntrMask, tp->intr_event);
2424 }
2425
2426 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2427 {
2428         struct rtl8169_private *tp = netdev_priv(dev);
2429         int ret = 0;
2430
2431         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2432                 return -EINVAL;
2433
2434         dev->mtu = new_mtu;
2435
2436         if (!netif_running(dev))
2437                 goto out;
2438
2439         rtl8169_down(dev);
2440
2441         rtl8169_set_rxbufsize(tp, dev);
2442
2443         ret = rtl8169_init_ring(dev);
2444         if (ret < 0)
2445                 goto out;
2446
2447         napi_enable(&tp->napi);
2448
2449         rtl_hw_start(dev);
2450
2451         rtl8169_request_timer(dev);
2452
2453 out:
2454         return ret;
2455 }
2456
2457 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2458 {
2459         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2460         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2461 }
2462
2463 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2464                                 struct sk_buff **sk_buff, struct RxDesc *desc)
2465 {
2466         struct pci_dev *pdev = tp->pci_dev;
2467
2468         pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2469                          PCI_DMA_FROMDEVICE);
2470         dev_kfree_skb(*sk_buff);
2471         *sk_buff = NULL;
2472         rtl8169_make_unusable_by_asic(desc);
2473 }
2474
2475 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2476 {
2477         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2478
2479         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2480 }
2481
2482 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2483                                        u32 rx_buf_sz)
2484 {
2485         desc->addr = cpu_to_le64(mapping);
2486         wmb();
2487         rtl8169_mark_to_asic(desc, rx_buf_sz);
2488 }
2489
2490 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2491                                             struct net_device *dev,
2492                                             struct RxDesc *desc, int rx_buf_sz,
2493                                             unsigned int align)
2494 {
2495         struct sk_buff *skb;
2496         dma_addr_t mapping;
2497         unsigned int pad;
2498
2499         pad = align ? align : NET_IP_ALIGN;
2500
2501         skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2502         if (!skb)
2503                 goto err_out;
2504
2505         skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2506
2507         mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2508                                  PCI_DMA_FROMDEVICE);
2509
2510         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2511 out:
2512         return skb;
2513
2514 err_out:
2515         rtl8169_make_unusable_by_asic(desc);
2516         goto out;
2517 }
2518
2519 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2520 {
2521         unsigned int i;
2522
2523         for (i = 0; i < NUM_RX_DESC; i++) {
2524                 if (tp->Rx_skbuff[i]) {
2525                         rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2526                                             tp->RxDescArray + i);
2527                 }
2528         }
2529 }
2530
2531 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2532                            u32 start, u32 end)
2533 {
2534         u32 cur;
2535
2536         for (cur = start; end - cur != 0; cur++) {
2537                 struct sk_buff *skb;
2538                 unsigned int i = cur % NUM_RX_DESC;
2539
2540                 WARN_ON((s32)(end - cur) < 0);
2541
2542                 if (tp->Rx_skbuff[i])
2543                         continue;
2544
2545                 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2546                                            tp->RxDescArray + i,
2547                                            tp->rx_buf_sz, tp->align);
2548                 if (!skb)
2549                         break;
2550
2551                 tp->Rx_skbuff[i] = skb;
2552         }
2553         return cur - start;
2554 }
2555
2556 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2557 {
2558         desc->opts1 |= cpu_to_le32(RingEnd);
2559 }
2560
2561 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2562 {
2563         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2564 }
2565
2566 static int rtl8169_init_ring(struct net_device *dev)
2567 {
2568         struct rtl8169_private *tp = netdev_priv(dev);
2569
2570         rtl8169_init_ring_indexes(tp);
2571
2572         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2573         memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2574
2575         if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2576                 goto err_out;
2577
2578         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2579
2580         return 0;
2581
2582 err_out:
2583         rtl8169_rx_clear(tp);
2584         return -ENOMEM;
2585 }
2586
2587 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2588                                  struct TxDesc *desc)
2589 {
2590         unsigned int len = tx_skb->len;
2591
2592         pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2593         desc->opts1 = 0x00;
2594         desc->opts2 = 0x00;
2595         desc->addr = 0x00;
2596         tx_skb->len = 0;
2597 }
2598
2599 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2600 {
2601         unsigned int i;
2602
2603         for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2604                 unsigned int entry = i % NUM_TX_DESC;
2605                 struct ring_info *tx_skb = tp->tx_skb + entry;
2606                 unsigned int len = tx_skb->len;
2607
2608                 if (len) {
2609                         struct sk_buff *skb = tx_skb->skb;
2610
2611                         rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2612                                              tp->TxDescArray + entry);
2613                         if (skb) {
2614                                 dev_kfree_skb(skb);
2615                                 tx_skb->skb = NULL;
2616                         }
2617                         tp->dev->stats.tx_dropped++;
2618                 }
2619         }
2620         tp->cur_tx = tp->dirty_tx = 0;
2621 }
2622
2623 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2624 {
2625         struct rtl8169_private *tp = netdev_priv(dev);
2626
2627         PREPARE_DELAYED_WORK(&tp->task, task);
2628         schedule_delayed_work(&tp->task, 4);
2629 }
2630
2631 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2632 {
2633         struct rtl8169_private *tp = netdev_priv(dev);
2634         void __iomem *ioaddr = tp->mmio_addr;
2635
2636         synchronize_irq(dev->irq);
2637
2638         /* Wait for any pending NAPI task to complete */
2639         napi_disable(&tp->napi);
2640
2641         rtl8169_irq_mask_and_ack(ioaddr);
2642
2643         tp->intr_mask = 0xffff;
2644         RTL_W16(IntrMask, tp->intr_event);
2645         napi_enable(&tp->napi);
2646 }
2647
2648 static void rtl8169_reinit_task(struct work_struct *work)
2649 {
2650         struct rtl8169_private *tp =
2651                 container_of(work, struct rtl8169_private, task.work);
2652         struct net_device *dev = tp->dev;
2653         int ret;
2654
2655         rtnl_lock();
2656
2657         if (!netif_running(dev))
2658                 goto out_unlock;
2659
2660         rtl8169_wait_for_quiescence(dev);
2661         rtl8169_close(dev);
2662
2663         ret = rtl8169_open(dev);
2664         if (unlikely(ret < 0)) {
2665                 if (net_ratelimit() && netif_msg_drv(tp)) {
2666                         printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
2667                                " Rescheduling.\n", dev->name, ret);
2668                 }
2669                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2670         }
2671
2672 out_unlock:
2673         rtnl_unlock();
2674 }
2675
2676 static void rtl8169_reset_task(struct work_struct *work)
2677 {
2678         struct rtl8169_private *tp =
2679                 container_of(work, struct rtl8169_private, task.work);
2680         struct net_device *dev = tp->dev;
2681
2682         rtnl_lock();
2683
2684         if (!netif_running(dev))
2685                 goto out_unlock;
2686
2687         rtl8169_wait_for_quiescence(dev);
2688
2689         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
2690         rtl8169_tx_clear(tp);
2691
2692         if (tp->dirty_rx == tp->cur_rx) {
2693                 rtl8169_init_ring_indexes(tp);
2694                 rtl_hw_start(dev);
2695                 netif_wake_queue(dev);
2696                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2697         } else {
2698                 if (net_ratelimit() && netif_msg_intr(tp)) {
2699                         printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
2700                                dev->name);
2701                 }
2702                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2703         }
2704
2705 out_unlock:
2706         rtnl_unlock();
2707 }
2708
2709 static void rtl8169_tx_timeout(struct net_device *dev)
2710 {
2711         struct rtl8169_private *tp = netdev_priv(dev);
2712
2713         rtl8169_hw_reset(tp->mmio_addr);
2714
2715         /* Let's wait a bit while any (async) irq lands on */
2716         rtl8169_schedule_work(dev, rtl8169_reset_task);
2717 }
2718
2719 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2720                               u32 opts1)
2721 {
2722         struct skb_shared_info *info = skb_shinfo(skb);
2723         unsigned int cur_frag, entry;
2724         struct TxDesc * uninitialized_var(txd);
2725
2726         entry = tp->cur_tx;
2727         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2728                 skb_frag_t *frag = info->frags + cur_frag;
2729                 dma_addr_t mapping;
2730                 u32 status, len;
2731                 void *addr;
2732
2733                 entry = (entry + 1) % NUM_TX_DESC;
2734
2735                 txd = tp->TxDescArray + entry;
2736                 len = frag->size;
2737                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2738                 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2739
2740                 /* anti gcc 2.95.3 bugware (sic) */
2741                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2742
2743                 txd->opts1 = cpu_to_le32(status);
2744                 txd->addr = cpu_to_le64(mapping);
2745
2746                 tp->tx_skb[entry].len = len;
2747         }
2748
2749         if (cur_frag) {
2750                 tp->tx_skb[entry].skb = skb;
2751                 txd->opts1 |= cpu_to_le32(LastFrag);
2752         }
2753
2754         return cur_frag;
2755 }
2756
2757 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2758 {
2759         if (dev->features & NETIF_F_TSO) {
2760                 u32 mss = skb_shinfo(skb)->gso_size;
2761
2762                 if (mss)
2763                         return LargeSend | ((mss & MSSMask) << MSSShift);
2764         }
2765         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2766                 const struct iphdr *ip = ip_hdr(skb);
2767
2768                 if (ip->protocol == IPPROTO_TCP)
2769                         return IPCS | TCPCS;
2770                 else if (ip->protocol == IPPROTO_UDP)
2771                         return IPCS | UDPCS;
2772                 WARN_ON(1);     /* we need a WARN() */
2773         }
2774         return 0;
2775 }
2776
2777 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2778 {
2779         struct rtl8169_private *tp = netdev_priv(dev);
2780         unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2781         struct TxDesc *txd = tp->TxDescArray + entry;
2782         void __iomem *ioaddr = tp->mmio_addr;
2783         dma_addr_t mapping;
2784         u32 status, len;
2785         u32 opts1;
2786         int ret = NETDEV_TX_OK;
2787
2788         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2789                 if (netif_msg_drv(tp)) {
2790                         printk(KERN_ERR
2791                                "%s: BUG! Tx Ring full when queue awake!\n",
2792                                dev->name);
2793                 }
2794                 goto err_stop;
2795         }
2796
2797         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2798                 goto err_stop;
2799
2800         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2801
2802         frags = rtl8169_xmit_frags(tp, skb, opts1);
2803         if (frags) {
2804                 len = skb_headlen(skb);
2805                 opts1 |= FirstFrag;
2806         } else {
2807                 len = skb->len;
2808
2809                 if (unlikely(len < ETH_ZLEN)) {
2810                         if (skb_padto(skb, ETH_ZLEN))
2811                                 goto err_update_stats;
2812                         len = ETH_ZLEN;
2813                 }
2814
2815                 opts1 |= FirstFrag | LastFrag;
2816                 tp->tx_skb[entry].skb = skb;
2817         }
2818
2819         mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2820
2821         tp->tx_skb[entry].len = len;
2822         txd->addr = cpu_to_le64(mapping);
2823         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2824
2825         wmb();
2826
2827         /* anti gcc 2.95.3 bugware (sic) */
2828         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2829         txd->opts1 = cpu_to_le32(status);
2830
2831         dev->trans_start = jiffies;
2832
2833         tp->cur_tx += frags + 1;
2834
2835         smp_wmb();
2836
2837         RTL_W8(TxPoll, NPQ);    /* set polling bit */
2838
2839         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2840                 netif_stop_queue(dev);
2841                 smp_rmb();
2842                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2843                         netif_wake_queue(dev);
2844         }
2845
2846 out:
2847         return ret;
2848
2849 err_stop:
2850         netif_stop_queue(dev);
2851         ret = NETDEV_TX_BUSY;
2852 err_update_stats:
2853         dev->stats.tx_dropped++;
2854         goto out;
2855 }
2856
2857 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2858 {
2859         struct rtl8169_private *tp = netdev_priv(dev);
2860         struct pci_dev *pdev = tp->pci_dev;
2861         void __iomem *ioaddr = tp->mmio_addr;
2862         u16 pci_status, pci_cmd;
2863
2864         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2865         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2866
2867         if (netif_msg_intr(tp)) {
2868                 printk(KERN_ERR
2869                        "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2870                        dev->name, pci_cmd, pci_status);
2871         }
2872
2873         /*
2874          * The recovery sequence below admits a very elaborated explanation:
2875          * - it seems to work;
2876          * - I did not see what else could be done;
2877          * - it makes iop3xx happy.
2878          *
2879          * Feel free to adjust to your needs.
2880          */
2881         if (pdev->broken_parity_status)
2882                 pci_cmd &= ~PCI_COMMAND_PARITY;
2883         else
2884                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2885
2886         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2887
2888         pci_write_config_word(pdev, PCI_STATUS,
2889                 pci_status & (PCI_STATUS_DETECTED_PARITY |
2890                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2891                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2892
2893         /* The infamous DAC f*ckup only happens at boot time */
2894         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2895                 if (netif_msg_intr(tp))
2896                         printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2897                 tp->cp_cmd &= ~PCIDAC;
2898                 RTL_W16(CPlusCmd, tp->cp_cmd);
2899                 dev->features &= ~NETIF_F_HIGHDMA;
2900         }
2901
2902         rtl8169_hw_reset(ioaddr);
2903
2904         rtl8169_schedule_work(dev, rtl8169_reinit_task);
2905 }
2906
2907 static void rtl8169_tx_interrupt(struct net_device *dev,
2908                                  struct rtl8169_private *tp,
2909                                  void __iomem *ioaddr)
2910 {
2911         unsigned int dirty_tx, tx_left;
2912
2913         dirty_tx = tp->dirty_tx;
2914         smp_rmb();
2915         tx_left = tp->cur_tx - dirty_tx;
2916
2917         while (tx_left > 0) {
2918                 unsigned int entry = dirty_tx % NUM_TX_DESC;
2919                 struct ring_info *tx_skb = tp->tx_skb + entry;
2920                 u32 len = tx_skb->len;
2921                 u32 status;
2922
2923                 rmb();
2924                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2925                 if (status & DescOwn)
2926                         break;
2927
2928                 dev->stats.tx_bytes += len;
2929                 dev->stats.tx_packets++;
2930
2931                 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2932
2933                 if (status & LastFrag) {
2934                         dev_kfree_skb_irq(tx_skb->skb);
2935                         tx_skb->skb = NULL;
2936                 }
2937                 dirty_tx++;
2938                 tx_left--;
2939         }
2940
2941         if (tp->dirty_tx != dirty_tx) {
2942                 tp->dirty_tx = dirty_tx;
2943                 smp_wmb();
2944                 if (netif_queue_stopped(dev) &&
2945                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2946                         netif_wake_queue(dev);
2947                 }
2948                 /*
2949                  * 8168 hack: TxPoll requests are lost when the Tx packets are
2950                  * too close. Let's kick an extra TxPoll request when a burst
2951                  * of start_xmit activity is detected (if it is not detected,
2952                  * it is slow enough). -- FR
2953                  */
2954                 smp_rmb();
2955                 if (tp->cur_tx != dirty_tx)
2956                         RTL_W8(TxPoll, NPQ);
2957         }
2958 }
2959
2960 static inline int rtl8169_fragmented_frame(u32 status)
2961 {
2962         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2963 }
2964
2965 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2966 {
2967         u32 opts1 = le32_to_cpu(desc->opts1);
2968         u32 status = opts1 & RxProtoMask;
2969
2970         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2971             ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2972             ((status == RxProtoIP) && !(opts1 & IPFail)))
2973                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2974         else
2975                 skb->ip_summed = CHECKSUM_NONE;
2976 }
2977
2978 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2979                                        struct rtl8169_private *tp, int pkt_size,
2980                                        dma_addr_t addr)
2981 {
2982         struct sk_buff *skb;
2983         bool done = false;
2984
2985         if (pkt_size >= rx_copybreak)
2986                 goto out;
2987
2988         skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
2989         if (!skb)
2990                 goto out;
2991
2992         pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2993                                     PCI_DMA_FROMDEVICE);
2994         skb_reserve(skb, NET_IP_ALIGN);
2995         skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2996         *sk_buff = skb;
2997         done = true;
2998 out:
2999         return done;
3000 }
3001
3002 static int rtl8169_rx_interrupt(struct net_device *dev,
3003                                 struct rtl8169_private *tp,
3004                                 void __iomem *ioaddr, u32 budget)
3005 {
3006         unsigned int cur_rx, rx_left;
3007         unsigned int delta, count;
3008
3009         cur_rx = tp->cur_rx;
3010         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3011         rx_left = min(rx_left, budget);
3012
3013         for (; rx_left > 0; rx_left--, cur_rx++) {
3014                 unsigned int entry = cur_rx % NUM_RX_DESC;
3015                 struct RxDesc *desc = tp->RxDescArray + entry;
3016                 u32 status;
3017
3018                 rmb();
3019                 status = le32_to_cpu(desc->opts1);
3020
3021                 if (status & DescOwn)
3022                         break;
3023                 if (unlikely(status & RxRES)) {
3024                         if (netif_msg_rx_err(tp)) {
3025                                 printk(KERN_INFO
3026                                        "%s: Rx ERROR. status = %08x\n",
3027                                        dev->name, status);
3028                         }
3029                         dev->stats.rx_errors++;
3030                         if (status & (RxRWT | RxRUNT))
3031                                 dev->stats.rx_length_errors++;
3032                         if (status & RxCRC)
3033                                 dev->stats.rx_crc_errors++;
3034                         if (status & RxFOVF) {
3035                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
3036                                 dev->stats.rx_fifo_errors++;
3037                         }
3038                         rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3039                 } else {
3040                         struct sk_buff *skb = tp->Rx_skbuff[entry];
3041                         dma_addr_t addr = le64_to_cpu(desc->addr);
3042                         int pkt_size = (status & 0x00001FFF) - 4;
3043                         struct pci_dev *pdev = tp->pci_dev;
3044
3045                         /*
3046                          * The driver does not support incoming fragmented
3047                          * frames. They are seen as a symptom of over-mtu
3048                          * sized frames.
3049                          */
3050                         if (unlikely(rtl8169_fragmented_frame(status))) {
3051                                 dev->stats.rx_dropped++;
3052                                 dev->stats.rx_length_errors++;
3053                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3054                                 continue;
3055                         }
3056
3057                         rtl8169_rx_csum(skb, desc);
3058
3059                         if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
3060                                 pci_dma_sync_single_for_device(pdev, addr,
3061                                         pkt_size, PCI_DMA_FROMDEVICE);
3062                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3063                         } else {
3064                                 pci_unmap_single(pdev, addr, pkt_size,
3065                                                  PCI_DMA_FROMDEVICE);
3066                                 tp->Rx_skbuff[entry] = NULL;
3067                         }
3068
3069                         skb_put(skb, pkt_size);
3070                         skb->protocol = eth_type_trans(skb, dev);
3071
3072                         if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
3073                                 netif_receive_skb(skb);
3074
3075                         dev->last_rx = jiffies;
3076                         dev->stats.rx_bytes += pkt_size;
3077                         dev->stats.rx_packets++;
3078                 }
3079
3080                 /* Work around for AMD plateform. */
3081                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
3082                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3083                         desc->opts2 = 0;
3084                         cur_rx++;
3085                 }
3086         }
3087
3088         count = cur_rx - tp->cur_rx;
3089         tp->cur_rx = cur_rx;
3090
3091         delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
3092         if (!delta && count && netif_msg_intr(tp))
3093                 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3094         tp->dirty_rx += delta;
3095
3096         /*
3097          * FIXME: until there is periodic timer to try and refill the ring,
3098          * a temporary shortage may definitely kill the Rx process.
3099          * - disable the asic to try and avoid an overflow and kick it again
3100          *   after refill ?
3101          * - how do others driver handle this condition (Uh oh...).
3102          */
3103         if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
3104                 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3105
3106         return count;
3107 }
3108
3109 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
3110 {
3111         struct net_device *dev = dev_instance;
3112         struct rtl8169_private *tp = netdev_priv(dev);
3113         void __iomem *ioaddr = tp->mmio_addr;
3114         int handled = 0;
3115         int status;
3116
3117         status = RTL_R16(IntrStatus);
3118
3119         /* hotplug/major error/no more work/shared irq */
3120         if ((status == 0xffff) || !status)
3121                 goto out;
3122
3123         handled = 1;
3124
3125         if (unlikely(!netif_running(dev))) {
3126                 rtl8169_asic_down(ioaddr);
3127                 goto out;
3128         }
3129
3130         status &= tp->intr_mask;
3131         RTL_W16(IntrStatus,
3132                 (status & RxFIFOOver) ? (status | RxOverflow) : status);
3133
3134         if (!(status & tp->intr_event))
3135                 goto out;
3136
3137         /* Work around for rx fifo overflow */
3138         if (unlikely(status & RxFIFOOver) &&
3139             (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3140                 netif_stop_queue(dev);
3141                 rtl8169_tx_timeout(dev);
3142                 goto out;
3143         }
3144
3145         if (unlikely(status & SYSErr)) {
3146                 rtl8169_pcierr_interrupt(dev);
3147                 goto out;
3148         }
3149
3150         if (status & LinkChg)
3151                 rtl8169_check_link_status(dev, tp, ioaddr);
3152
3153         if (status & tp->napi_event) {
3154                 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3155                 tp->intr_mask = ~tp->napi_event;
3156
3157                 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
3158                         __netif_rx_schedule(dev, &tp->napi);
3159                 else if (netif_msg_intr(tp)) {
3160                         printk(KERN_INFO "%s: interrupt %04x in poll\n",
3161                                dev->name, status);
3162                 }
3163         }
3164 out:
3165         return IRQ_RETVAL(handled);
3166 }
3167
3168 static int rtl8169_poll(struct napi_struct *napi, int budget)
3169 {
3170         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3171         struct net_device *dev = tp->dev;
3172         void __iomem *ioaddr = tp->mmio_addr;
3173         int work_done;
3174
3175         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
3176         rtl8169_tx_interrupt(dev, tp, ioaddr);
3177
3178         if (work_done < budget) {
3179                 netif_rx_complete(dev, napi);
3180                 tp->intr_mask = 0xffff;
3181                 /*
3182                  * 20040426: the barrier is not strictly required but the
3183                  * behavior of the irq handler could be less predictable
3184                  * without it. Btw, the lack of flush for the posted pci
3185                  * write is safe - FR
3186                  */
3187                 smp_wmb();
3188                 RTL_W16(IntrMask, tp->intr_event);
3189         }
3190
3191         return work_done;
3192 }
3193
3194 static void rtl8169_down(struct net_device *dev)
3195 {
3196         struct rtl8169_private *tp = netdev_priv(dev);
3197         void __iomem *ioaddr = tp->mmio_addr;
3198         unsigned int intrmask;
3199
3200         rtl8169_delete_timer(dev);
3201
3202         netif_stop_queue(dev);
3203
3204         napi_disable(&tp->napi);
3205
3206 core_down:
3207         spin_lock_irq(&tp->lock);
3208
3209         rtl8169_asic_down(ioaddr);
3210
3211         /* Update the error counts. */
3212         dev->stats.rx_missed_errors += RTL_R32(RxMissed);
3213         RTL_W32(RxMissed, 0);
3214
3215         spin_unlock_irq(&tp->lock);
3216
3217         synchronize_irq(dev->irq);
3218
3219         /* Give a racing hard_start_xmit a few cycles to complete. */
3220         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
3221
3222         /*
3223          * And now for the 50k$ question: are IRQ disabled or not ?
3224          *
3225          * Two paths lead here:
3226          * 1) dev->close
3227          *    -> netif_running() is available to sync the current code and the
3228          *       IRQ handler. See rtl8169_interrupt for details.
3229          * 2) dev->change_mtu
3230          *    -> rtl8169_poll can not be issued again and re-enable the
3231          *       interruptions. Let's simply issue the IRQ down sequence again.
3232          *
3233          * No loop if hotpluged or major error (0xffff).
3234          */
3235         intrmask = RTL_R16(IntrMask);
3236         if (intrmask && (intrmask != 0xffff))
3237                 goto core_down;
3238
3239         rtl8169_tx_clear(tp);
3240
3241         rtl8169_rx_clear(tp);
3242 }
3243
3244 static int rtl8169_close(struct net_device *dev)
3245 {
3246         struct rtl8169_private *tp = netdev_priv(dev);
3247         struct pci_dev *pdev = tp->pci_dev;
3248
3249         rtl8169_down(dev);
3250
3251         free_irq(dev->irq, dev);
3252
3253         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3254                             tp->RxPhyAddr);
3255         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3256                             tp->TxPhyAddr);
3257         tp->TxDescArray = NULL;
3258         tp->RxDescArray = NULL;
3259
3260         return 0;
3261 }
3262
3263 static void rtl_set_rx_mode(struct net_device *dev)
3264 {
3265         struct rtl8169_private *tp = netdev_priv(dev);
3266         void __iomem *ioaddr = tp->mmio_addr;
3267         unsigned long flags;
3268         u32 mc_filter[2];       /* Multicast hash filter */
3269         int rx_mode;
3270         u32 tmp = 0;
3271
3272         if (dev->flags & IFF_PROMISC) {
3273                 /* Unconditionally log net taps. */
3274                 if (netif_msg_link(tp)) {
3275                         printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3276                                dev->name);
3277                 }
3278                 rx_mode =
3279                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3280                     AcceptAllPhys;
3281                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3282         } else if ((dev->mc_count > multicast_filter_limit)
3283                    || (dev->flags & IFF_ALLMULTI)) {
3284                 /* Too many to filter perfectly -- accept all multicasts. */
3285                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3286                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3287         } else {
3288                 struct dev_mc_list *mclist;
3289                 unsigned int i;
3290
3291                 rx_mode = AcceptBroadcast | AcceptMyPhys;
3292                 mc_filter[1] = mc_filter[0] = 0;
3293                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3294                      i++, mclist = mclist->next) {
3295                         int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3296                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3297                         rx_mode |= AcceptMulticast;
3298                 }
3299         }
3300
3301         spin_lock_irqsave(&tp->lock, flags);
3302
3303         tmp = rtl8169_rx_config | rx_mode |
3304               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3305
3306         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3307                 u32 data = mc_filter[0];
3308
3309                 mc_filter[0] = swab32(mc_filter[1]);
3310                 mc_filter[1] = swab32(data);
3311         }
3312
3313         RTL_W32(MAR0 + 0, mc_filter[0]);
3314         RTL_W32(MAR0 + 4, mc_filter[1]);
3315
3316         RTL_W32(RxConfig, tmp);
3317
3318         spin_unlock_irqrestore(&tp->lock, flags);
3319 }
3320
3321 /**
3322  *  rtl8169_get_stats - Get rtl8169 read/write statistics
3323  *  @dev: The Ethernet Device to get statistics for
3324  *
3325  *  Get TX/RX statistics for rtl8169
3326  */
3327 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3328 {
3329         struct rtl8169_private *tp = netdev_priv(dev);
3330         void __iomem *ioaddr = tp->mmio_addr;
3331         unsigned long flags;
3332
3333         if (netif_running(dev)) {
3334                 spin_lock_irqsave(&tp->lock, flags);
3335                 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
3336                 RTL_W32(RxMissed, 0);
3337                 spin_unlock_irqrestore(&tp->lock, flags);
3338         }
3339
3340         return &dev->stats;
3341 }
3342
3343 #ifdef CONFIG_PM
3344
3345 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3346 {
3347         struct net_device *dev = pci_get_drvdata(pdev);
3348         struct rtl8169_private *tp = netdev_priv(dev);
3349         void __iomem *ioaddr = tp->mmio_addr;
3350
3351         if (!netif_running(dev))
3352                 goto out_pci_suspend;
3353
3354         netif_device_detach(dev);
3355         netif_stop_queue(dev);
3356
3357         spin_lock_irq(&tp->lock);
3358
3359         rtl8169_asic_down(ioaddr);
3360
3361         dev->stats.rx_missed_errors += RTL_R32(RxMissed);
3362         RTL_W32(RxMissed, 0);
3363
3364         spin_unlock_irq(&tp->lock);
3365
3366 out_pci_suspend:
3367         pci_save_state(pdev);
3368         pci_enable_wake(pdev, pci_choose_state(pdev, state),
3369                 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3370         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3371
3372         return 0;
3373 }
3374
3375 static int rtl8169_resume(struct pci_dev *pdev)
3376 {
3377         struct net_device *dev = pci_get_drvdata(pdev);
3378
3379         pci_set_power_state(pdev, PCI_D0);
3380         pci_restore_state(pdev);
3381         pci_enable_wake(pdev, PCI_D0, 0);
3382
3383         if (!netif_running(dev))
3384                 goto out;
3385
3386         netif_device_attach(dev);
3387
3388         rtl8169_schedule_work(dev, rtl8169_reset_task);
3389 out:
3390         return 0;
3391 }
3392
3393 #endif /* CONFIG_PM */
3394
3395 static struct pci_driver rtl8169_pci_driver = {
3396         .name           = MODULENAME,
3397         .id_table       = rtl8169_pci_tbl,
3398         .probe          = rtl8169_init_one,
3399         .remove         = __devexit_p(rtl8169_remove_one),
3400 #ifdef CONFIG_PM
3401         .suspend        = rtl8169_suspend,
3402         .resume         = rtl8169_resume,
3403 #endif
3404 };
3405
3406 static int __init rtl8169_init_module(void)
3407 {
3408         return pci_register_driver(&rtl8169_pci_driver);
3409 }
3410
3411 static void __exit rtl8169_cleanup_module(void)
3412 {
3413         pci_unregister_driver(&rtl8169_pci_driver);
3414 }
3415
3416 module_init(rtl8169_init_module);
3417 module_exit(rtl8169_cleanup_module);