b3cf1d20ba2c46c60072fbcc3c133fa588122b5d
[linux-2.6.git] / drivers / net / r8169.c
1 /*
2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3  *
4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6  * Copyright (c) a lot of people too. Please respect their work.
7  *
8  * See MAINTAINERS file for support contact information.
9  */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29
30 #include <asm/system.h>
31 #include <asm/io.h>
32 #include <asm/irq.h>
33
34 #define RTL8169_VERSION "2.3LK-NAPI"
35 #define MODULENAME "r8169"
36 #define PFX MODULENAME ": "
37
38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
43
44 #ifdef RTL8169_DEBUG
45 #define assert(expr) \
46         if (!(expr)) {                                  \
47                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
48                 #expr,__FILE__,__func__,__LINE__);              \
49         }
50 #define dprintk(fmt, args...) \
51         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
52 #else
53 #define assert(expr) do {} while (0)
54 #define dprintk(fmt, args...)   do {} while (0)
55 #endif /* RTL8169_DEBUG */
56
57 #define R8169_MSG_DEFAULT \
58         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
59
60 #define TX_BUFFS_AVAIL(tp) \
61         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
62
63 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
64    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
65 static const int multicast_filter_limit = 32;
66
67 /* MAC address length */
68 #define MAC_ADDR_LEN    6
69
70 #define MAX_READ_REQUEST_SHIFT  12
71 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
72 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
73 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
74 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
75 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
76
77 #define R8169_REGS_SIZE         256
78 #define R8169_NAPI_WEIGHT       64
79 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
80 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
81 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
82 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
83 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
84
85 #define RTL8169_TX_TIMEOUT      (6*HZ)
86 #define RTL8169_PHY_TIMEOUT     (10*HZ)
87
88 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
89 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
90 #define RTL_EEPROM_SIG_ADDR     0x0000
91
92 /* write/read MMIO register */
93 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
94 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
95 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
96 #define RTL_R8(reg)             readb (ioaddr + (reg))
97 #define RTL_R16(reg)            readw (ioaddr + (reg))
98 #define RTL_R32(reg)            readl (ioaddr + (reg))
99
100 enum mac_version {
101         RTL_GIGA_MAC_NONE   = 0x00,
102         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
103         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
104         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
105         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
106         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
107         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
108         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
109         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
110         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
111         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
112         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
113         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
114         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
115         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
116         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
117         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
118         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
119         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
120         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
121         RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
122         RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
123         RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
124         RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
125         RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
126         RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
127         RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
128         RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
129         RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
130         RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E
131         RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E
132         RTL_GIGA_MAC_VER_31 = 0x1f, // 8168DP
133         RTL_GIGA_MAC_VER_32 = 0x20, // 8168E
134         RTL_GIGA_MAC_VER_33 = 0x21, // 8168E
135 };
136
137 enum rtl_tx_desc_version {
138         RTL_TD_0        = 0,
139         RTL_TD_1        = 1,
140 };
141
142 #define _R(NAME,MAC,TD) \
143         { .name = NAME, .mac_version = MAC, .txd_version = TD }
144
145 static const struct {
146         const char *name;
147         u8 mac_version;
148         enum rtl_tx_desc_version txd_version;
149 } rtl_chip_info[] = {
150         _R("RTL8169",           RTL_GIGA_MAC_VER_01, RTL_TD_0), // 8169
151         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, RTL_TD_0), // 8169S
152         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, RTL_TD_0), // 8110S
153         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, RTL_TD_0), // 8169SB
154         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, RTL_TD_0), // 8110SCd
155         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, RTL_TD_0), // 8110SCe
156         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, RTL_TD_1), // PCI-E
157         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, RTL_TD_1), // PCI-E
158         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, RTL_TD_1), // PCI-E
159         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, RTL_TD_0), // PCI-E
160         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, RTL_TD_0), // PCI-E
161         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, RTL_TD_0), // PCI-E
162         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, RTL_TD_0), // PCI-E 8139
163         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, RTL_TD_0), // PCI-E 8139
164         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, RTL_TD_0), // PCI-E 8139
165         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, RTL_TD_0), // PCI-E
166         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, RTL_TD_0), // PCI-E
167         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, RTL_TD_1), // PCI-E
168         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, RTL_TD_1), // PCI-E
169         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, RTL_TD_1), // PCI-E
170         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_21, RTL_TD_1), // PCI-E
171         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_22, RTL_TD_1), // PCI-E
172         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_23, RTL_TD_1), // PCI-E
173         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_24, RTL_TD_1), // PCI-E
174         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_25, RTL_TD_1), // PCI-E
175         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_26, RTL_TD_1), // PCI-E
176         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_27, RTL_TD_1), // PCI-E
177         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_28, RTL_TD_1), // PCI-E
178         _R("RTL8105e",          RTL_GIGA_MAC_VER_29, RTL_TD_1), // PCI-E
179         _R("RTL8105e",          RTL_GIGA_MAC_VER_30, RTL_TD_1), // PCI-E
180         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_31, RTL_TD_1), // PCI-E
181         _R("RTL8168e/8111e",    RTL_GIGA_MAC_VER_32, RTL_TD_1), // PCI-E
182         _R("RTL8168e/8111e",    RTL_GIGA_MAC_VER_33, RTL_TD_1)  // PCI-E
183 };
184 #undef _R
185
186 static const struct rtl_firmware_info {
187         int mac_version;
188         const char *fw_name;
189 } rtl_firmware_infos[] = {
190         { .mac_version = RTL_GIGA_MAC_VER_25, .fw_name = FIRMWARE_8168D_1 },
191         { .mac_version = RTL_GIGA_MAC_VER_26, .fw_name = FIRMWARE_8168D_2 },
192         { .mac_version = RTL_GIGA_MAC_VER_29, .fw_name = FIRMWARE_8105E_1 },
193         { .mac_version = RTL_GIGA_MAC_VER_30, .fw_name = FIRMWARE_8105E_1 },
194         { .mac_version = RTL_GIGA_MAC_VER_32, .fw_name = FIRMWARE_8168E_1 },
195         { .mac_version = RTL_GIGA_MAC_VER_33, .fw_name = FIRMWARE_8168E_2 }
196 };
197
198 enum cfg_version {
199         RTL_CFG_0 = 0x00,
200         RTL_CFG_1,
201         RTL_CFG_2
202 };
203
204 static void rtl_hw_start_8169(struct net_device *);
205 static void rtl_hw_start_8168(struct net_device *);
206 static void rtl_hw_start_8101(struct net_device *);
207
208 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
209         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
210         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
211         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
212         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
213         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
214         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
215         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
216         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
217         { PCI_VENDOR_ID_LINKSYS,                0x1032,
218                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
219         { 0x0001,                               0x8168,
220                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
221         {0,},
222 };
223
224 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
225
226 static int rx_buf_sz = 16383;
227 static int use_dac;
228 static struct {
229         u32 msg_enable;
230 } debug = { -1 };
231
232 enum rtl_registers {
233         MAC0            = 0,    /* Ethernet hardware address. */
234         MAC4            = 4,
235         MAR0            = 8,    /* Multicast filter. */
236         CounterAddrLow          = 0x10,
237         CounterAddrHigh         = 0x14,
238         TxDescStartAddrLow      = 0x20,
239         TxDescStartAddrHigh     = 0x24,
240         TxHDescStartAddrLow     = 0x28,
241         TxHDescStartAddrHigh    = 0x2c,
242         FLASH           = 0x30,
243         ERSR            = 0x36,
244         ChipCmd         = 0x37,
245         TxPoll          = 0x38,
246         IntrMask        = 0x3c,
247         IntrStatus      = 0x3e,
248         TxConfig        = 0x40,
249         RxConfig        = 0x44,
250
251 #define RTL_RX_CONFIG_MASK              0xff7e1880u
252
253         RxMissed        = 0x4c,
254         Cfg9346         = 0x50,
255         Config0         = 0x51,
256         Config1         = 0x52,
257         Config2         = 0x53,
258         Config3         = 0x54,
259         Config4         = 0x55,
260         Config5         = 0x56,
261         MultiIntr       = 0x5c,
262         PHYAR           = 0x60,
263         PHYstatus       = 0x6c,
264         RxMaxSize       = 0xda,
265         CPlusCmd        = 0xe0,
266         IntrMitigate    = 0xe2,
267         RxDescAddrLow   = 0xe4,
268         RxDescAddrHigh  = 0xe8,
269         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
270
271 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
272
273         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
274
275 #define TxPacketMax     (8064 >> 7)
276
277         FuncEvent       = 0xf0,
278         FuncEventMask   = 0xf4,
279         FuncPresetState = 0xf8,
280         FuncForceEvent  = 0xfc,
281 };
282
283 enum rtl8110_registers {
284         TBICSR                  = 0x64,
285         TBI_ANAR                = 0x68,
286         TBI_LPAR                = 0x6a,
287 };
288
289 enum rtl8168_8101_registers {
290         CSIDR                   = 0x64,
291         CSIAR                   = 0x68,
292 #define CSIAR_FLAG                      0x80000000
293 #define CSIAR_WRITE_CMD                 0x80000000
294 #define CSIAR_BYTE_ENABLE               0x0f
295 #define CSIAR_BYTE_ENABLE_SHIFT         12
296 #define CSIAR_ADDR_MASK                 0x0fff
297         PMCH                    = 0x6f,
298         EPHYAR                  = 0x80,
299 #define EPHYAR_FLAG                     0x80000000
300 #define EPHYAR_WRITE_CMD                0x80000000
301 #define EPHYAR_REG_MASK                 0x1f
302 #define EPHYAR_REG_SHIFT                16
303 #define EPHYAR_DATA_MASK                0xffff
304         DLLPR                   = 0xd0,
305 #define PM_SWITCH                       (1 << 6)
306         DBG_REG                 = 0xd1,
307 #define FIX_NAK_1                       (1 << 4)
308 #define FIX_NAK_2                       (1 << 3)
309         TWSI                    = 0xd2,
310         MCU                     = 0xd3,
311 #define EN_NDP                          (1 << 3)
312 #define EN_OOB_RESET                    (1 << 2)
313         EFUSEAR                 = 0xdc,
314 #define EFUSEAR_FLAG                    0x80000000
315 #define EFUSEAR_WRITE_CMD               0x80000000
316 #define EFUSEAR_READ_CMD                0x00000000
317 #define EFUSEAR_REG_MASK                0x03ff
318 #define EFUSEAR_REG_SHIFT               8
319 #define EFUSEAR_DATA_MASK               0xff
320 };
321
322 enum rtl8168_registers {
323         ERIDR                   = 0x70,
324         ERIAR                   = 0x74,
325 #define ERIAR_FLAG                      0x80000000
326 #define ERIAR_WRITE_CMD                 0x80000000
327 #define ERIAR_READ_CMD                  0x00000000
328 #define ERIAR_ADDR_BYTE_ALIGN           4
329 #define ERIAR_EXGMAC                    0
330 #define ERIAR_MSIX                      1
331 #define ERIAR_ASF                       2
332 #define ERIAR_TYPE_SHIFT                16
333 #define ERIAR_BYTEEN                    0x0f
334 #define ERIAR_BYTEEN_SHIFT              12
335         EPHY_RXER_NUM           = 0x7c,
336         OCPDR                   = 0xb0, /* OCP GPHY access */
337 #define OCPDR_WRITE_CMD                 0x80000000
338 #define OCPDR_READ_CMD                  0x00000000
339 #define OCPDR_REG_MASK                  0x7f
340 #define OCPDR_GPHY_REG_SHIFT            16
341 #define OCPDR_DATA_MASK                 0xffff
342         OCPAR                   = 0xb4,
343 #define OCPAR_FLAG                      0x80000000
344 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
345 #define OCPAR_GPHY_READ_CMD             0x0000f060
346         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
347         MISC                    = 0xf0, /* 8168e only. */
348 #define TXPLA_RST                       (1 << 29)
349 };
350
351 enum rtl_register_content {
352         /* InterruptStatusBits */
353         SYSErr          = 0x8000,
354         PCSTimeout      = 0x4000,
355         SWInt           = 0x0100,
356         TxDescUnavail   = 0x0080,
357         RxFIFOOver      = 0x0040,
358         LinkChg         = 0x0020,
359         RxOverflow      = 0x0010,
360         TxErr           = 0x0008,
361         TxOK            = 0x0004,
362         RxErr           = 0x0002,
363         RxOK            = 0x0001,
364
365         /* RxStatusDesc */
366         RxFOVF  = (1 << 23),
367         RxRWT   = (1 << 22),
368         RxRES   = (1 << 21),
369         RxRUNT  = (1 << 20),
370         RxCRC   = (1 << 19),
371
372         /* ChipCmdBits */
373         CmdReset        = 0x10,
374         CmdRxEnb        = 0x08,
375         CmdTxEnb        = 0x04,
376         RxBufEmpty      = 0x01,
377
378         /* TXPoll register p.5 */
379         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
380         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
381         FSWInt          = 0x01,         /* Forced software interrupt */
382
383         /* Cfg9346Bits */
384         Cfg9346_Lock    = 0x00,
385         Cfg9346_Unlock  = 0xc0,
386
387         /* rx_mode_bits */
388         AcceptErr       = 0x20,
389         AcceptRunt      = 0x10,
390         AcceptBroadcast = 0x08,
391         AcceptMulticast = 0x04,
392         AcceptMyPhys    = 0x02,
393         AcceptAllPhys   = 0x01,
394
395         /* RxConfigBits */
396         RxCfgFIFOShift  = 13,
397         RxCfgDMAShift   =  8,
398
399         /* TxConfigBits */
400         TxInterFrameGapShift = 24,
401         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
402
403         /* Config1 register p.24 */
404         LEDS1           = (1 << 7),
405         LEDS0           = (1 << 6),
406         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
407         Speed_down      = (1 << 4),
408         MEMMAP          = (1 << 3),
409         IOMAP           = (1 << 2),
410         VPD             = (1 << 1),
411         PMEnable        = (1 << 0),     /* Power Management Enable */
412
413         /* Config2 register p. 25 */
414         PCI_Clock_66MHz = 0x01,
415         PCI_Clock_33MHz = 0x00,
416
417         /* Config3 register p.25 */
418         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
419         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
420         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
421
422         /* Config5 register p.27 */
423         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
424         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
425         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
426         Spi_en          = (1 << 3),
427         LanWake         = (1 << 1),     /* LanWake enable/disable */
428         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
429
430         /* TBICSR p.28 */
431         TBIReset        = 0x80000000,
432         TBILoopback     = 0x40000000,
433         TBINwEnable     = 0x20000000,
434         TBINwRestart    = 0x10000000,
435         TBILinkOk       = 0x02000000,
436         TBINwComplete   = 0x01000000,
437
438         /* CPlusCmd p.31 */
439         EnableBist      = (1 << 15),    // 8168 8101
440         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
441         Normal_mode     = (1 << 13),    // unused
442         Force_half_dup  = (1 << 12),    // 8168 8101
443         Force_rxflow_en = (1 << 11),    // 8168 8101
444         Force_txflow_en = (1 << 10),    // 8168 8101
445         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
446         ASF             = (1 << 8),     // 8168 8101
447         PktCntrDisable  = (1 << 7),     // 8168 8101
448         Mac_dbgo_sel    = 0x001c,       // 8168
449         RxVlan          = (1 << 6),
450         RxChkSum        = (1 << 5),
451         PCIDAC          = (1 << 4),
452         PCIMulRW        = (1 << 3),
453         INTT_0          = 0x0000,       // 8168
454         INTT_1          = 0x0001,       // 8168
455         INTT_2          = 0x0002,       // 8168
456         INTT_3          = 0x0003,       // 8168
457
458         /* rtl8169_PHYstatus */
459         TBI_Enable      = 0x80,
460         TxFlowCtrl      = 0x40,
461         RxFlowCtrl      = 0x20,
462         _1000bpsF       = 0x10,
463         _100bps         = 0x08,
464         _10bps          = 0x04,
465         LinkStatus      = 0x02,
466         FullDup         = 0x01,
467
468         /* _TBICSRBit */
469         TBILinkOK       = 0x02000000,
470
471         /* DumpCounterCommand */
472         CounterDump     = 0x8,
473 };
474
475 enum rtl_desc_bit {
476         /* First doubleword. */
477         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
478         RingEnd         = (1 << 30), /* End of descriptor ring */
479         FirstFrag       = (1 << 29), /* First segment of a packet */
480         LastFrag        = (1 << 28), /* Final segment of a packet */
481 };
482
483 /* Generic case. */
484 enum rtl_tx_desc_bit {
485         /* First doubleword. */
486         TD_LSO          = (1 << 27),            /* Large Send Offload */
487 #define TD_MSS_MAX                      0x07ffu /* MSS value */
488
489         /* Second doubleword. */
490         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
491 };
492
493 /* 8169, 8168b and 810x except 8102e. */
494 enum rtl_tx_desc_bit_0 {
495         /* First doubleword. */
496 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
497         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
498         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
499         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
500 };
501
502 /* 8102e, 8168c and beyond. */
503 enum rtl_tx_desc_bit_1 {
504         /* Second doubleword. */
505 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
506         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
507         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
508         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
509 };
510
511 static const struct rtl_tx_desc_info {
512         struct {
513                 u32 udp;
514                 u32 tcp;
515         } checksum;
516         u16 mss_shift;
517         u16 opts_offset;
518 } tx_desc_info [] = {
519         [RTL_TD_0] = {
520                 .checksum = {
521                         .udp    = TD0_IP_CS | TD0_UDP_CS,
522                         .tcp    = TD0_IP_CS | TD0_TCP_CS
523                 },
524                 .mss_shift      = TD0_MSS_SHIFT,
525                 .opts_offset    = 0
526         },
527         [RTL_TD_1] = {
528                 .checksum = {
529                         .udp    = TD1_IP_CS | TD1_UDP_CS,
530                         .tcp    = TD1_IP_CS | TD1_TCP_CS
531                 },
532                 .mss_shift      = TD1_MSS_SHIFT,
533                 .opts_offset    = 1
534         }
535 };
536
537 enum rtl_rx_desc_bit {
538         /* Rx private */
539         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
540         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
541
542 #define RxProtoUDP      (PID1)
543 #define RxProtoTCP      (PID0)
544 #define RxProtoIP       (PID1 | PID0)
545 #define RxProtoMask     RxProtoIP
546
547         IPFail          = (1 << 16), /* IP checksum failed */
548         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
549         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
550         RxVlanTag       = (1 << 16), /* VLAN tag available */
551 };
552
553 #define RsvdMask        0x3fffc000
554
555 struct TxDesc {
556         __le32 opts1;
557         __le32 opts2;
558         __le64 addr;
559 };
560
561 struct RxDesc {
562         __le32 opts1;
563         __le32 opts2;
564         __le64 addr;
565 };
566
567 struct ring_info {
568         struct sk_buff  *skb;
569         u32             len;
570         u8              __pad[sizeof(void *) - sizeof(u32)];
571 };
572
573 enum features {
574         RTL_FEATURE_WOL         = (1 << 0),
575         RTL_FEATURE_MSI         = (1 << 1),
576         RTL_FEATURE_GMII        = (1 << 2),
577 };
578
579 struct rtl8169_counters {
580         __le64  tx_packets;
581         __le64  rx_packets;
582         __le64  tx_errors;
583         __le32  rx_errors;
584         __le16  rx_missed;
585         __le16  align_errors;
586         __le32  tx_one_collision;
587         __le32  tx_multi_collision;
588         __le64  rx_unicast;
589         __le64  rx_broadcast;
590         __le32  rx_multicast;
591         __le16  tx_aborted;
592         __le16  tx_underun;
593 };
594
595 struct rtl8169_private {
596         void __iomem *mmio_addr;        /* memory map physical address */
597         struct pci_dev *pci_dev;
598         struct net_device *dev;
599         struct napi_struct napi;
600         spinlock_t lock;
601         u32 msg_enable;
602         u16 txd_version;
603         u16 mac_version;
604         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
605         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
606         u32 dirty_rx;
607         u32 dirty_tx;
608         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
609         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
610         dma_addr_t TxPhyAddr;
611         dma_addr_t RxPhyAddr;
612         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
613         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
614         struct timer_list timer;
615         u16 cp_cmd;
616         u16 intr_event;
617         u16 napi_event;
618         u16 intr_mask;
619
620         struct mdio_ops {
621                 void (*write)(void __iomem *, int, int);
622                 int (*read)(void __iomem *, int);
623         } mdio_ops;
624
625         struct pll_power_ops {
626                 void (*down)(struct rtl8169_private *);
627                 void (*up)(struct rtl8169_private *);
628         } pll_power_ops;
629
630         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
631         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
632         void (*phy_reset_enable)(struct rtl8169_private *tp);
633         void (*hw_start)(struct net_device *);
634         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
635         unsigned int (*link_ok)(void __iomem *);
636         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
637         int pcie_cap;
638         struct delayed_work task;
639         unsigned features;
640
641         struct mii_if_info mii;
642         struct rtl8169_counters counters;
643         u32 saved_wolopts;
644
645         const struct firmware *fw;
646 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN);
647 };
648
649 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
650 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
651 module_param(use_dac, int, 0);
652 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
653 module_param_named(debug, debug.msg_enable, int, 0);
654 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
655 MODULE_LICENSE("GPL");
656 MODULE_VERSION(RTL8169_VERSION);
657 MODULE_FIRMWARE(FIRMWARE_8168D_1);
658 MODULE_FIRMWARE(FIRMWARE_8168D_2);
659 MODULE_FIRMWARE(FIRMWARE_8168E_1);
660 MODULE_FIRMWARE(FIRMWARE_8168E_2);
661 MODULE_FIRMWARE(FIRMWARE_8105E_1);
662
663 static int rtl8169_open(struct net_device *dev);
664 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
665                                       struct net_device *dev);
666 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
667 static int rtl8169_init_ring(struct net_device *dev);
668 static void rtl_hw_start(struct net_device *dev);
669 static int rtl8169_close(struct net_device *dev);
670 static void rtl_set_rx_mode(struct net_device *dev);
671 static void rtl8169_tx_timeout(struct net_device *dev);
672 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
673 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
674                                 void __iomem *, u32 budget);
675 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
676 static void rtl8169_down(struct net_device *dev);
677 static void rtl8169_rx_clear(struct rtl8169_private *tp);
678 static int rtl8169_poll(struct napi_struct *napi, int budget);
679
680 static const unsigned int rtl8169_rx_config =
681         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
682
683 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
684 {
685         void __iomem *ioaddr = tp->mmio_addr;
686         int i;
687
688         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
689         for (i = 0; i < 20; i++) {
690                 udelay(100);
691                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
692                         break;
693         }
694         return RTL_R32(OCPDR);
695 }
696
697 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
698 {
699         void __iomem *ioaddr = tp->mmio_addr;
700         int i;
701
702         RTL_W32(OCPDR, data);
703         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
704         for (i = 0; i < 20; i++) {
705                 udelay(100);
706                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
707                         break;
708         }
709 }
710
711 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
712 {
713         void __iomem *ioaddr = tp->mmio_addr;
714         int i;
715
716         RTL_W8(ERIDR, cmd);
717         RTL_W32(ERIAR, 0x800010e8);
718         msleep(2);
719         for (i = 0; i < 5; i++) {
720                 udelay(100);
721                 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
722                         break;
723         }
724
725         ocp_write(tp, 0x1, 0x30, 0x00000001);
726 }
727
728 #define OOB_CMD_RESET           0x00
729 #define OOB_CMD_DRIVER_START    0x05
730 #define OOB_CMD_DRIVER_STOP     0x06
731
732 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
733 {
734         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
735 }
736
737 static void rtl8168_driver_start(struct rtl8169_private *tp)
738 {
739         u16 reg;
740         int i;
741
742         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
743
744         reg = rtl8168_get_ocp_reg(tp);
745
746         for (i = 0; i < 10; i++) {
747                 msleep(10);
748                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
749                         break;
750         }
751 }
752
753 static void rtl8168_driver_stop(struct rtl8169_private *tp)
754 {
755         u16 reg;
756         int i;
757
758         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
759
760         reg = rtl8168_get_ocp_reg(tp);
761
762         for (i = 0; i < 10; i++) {
763                 msleep(10);
764                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
765                         break;
766         }
767 }
768
769 static int r8168dp_check_dash(struct rtl8169_private *tp)
770 {
771         u16 reg = rtl8168_get_ocp_reg(tp);
772
773         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
774 }
775
776 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
777 {
778         int i;
779
780         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
781
782         for (i = 20; i > 0; i--) {
783                 /*
784                  * Check if the RTL8169 has completed writing to the specified
785                  * MII register.
786                  */
787                 if (!(RTL_R32(PHYAR) & 0x80000000))
788                         break;
789                 udelay(25);
790         }
791         /*
792          * According to hardware specs a 20us delay is required after write
793          * complete indication, but before sending next command.
794          */
795         udelay(20);
796 }
797
798 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
799 {
800         int i, value = -1;
801
802         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
803
804         for (i = 20; i > 0; i--) {
805                 /*
806                  * Check if the RTL8169 has completed retrieving data from
807                  * the specified MII register.
808                  */
809                 if (RTL_R32(PHYAR) & 0x80000000) {
810                         value = RTL_R32(PHYAR) & 0xffff;
811                         break;
812                 }
813                 udelay(25);
814         }
815         /*
816          * According to hardware specs a 20us delay is required after read
817          * complete indication, but before sending next command.
818          */
819         udelay(20);
820
821         return value;
822 }
823
824 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
825 {
826         int i;
827
828         RTL_W32(OCPDR, data |
829                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
830         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
831         RTL_W32(EPHY_RXER_NUM, 0);
832
833         for (i = 0; i < 100; i++) {
834                 mdelay(1);
835                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
836                         break;
837         }
838 }
839
840 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
841 {
842         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
843                 (value & OCPDR_DATA_MASK));
844 }
845
846 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
847 {
848         int i;
849
850         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
851
852         mdelay(1);
853         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
854         RTL_W32(EPHY_RXER_NUM, 0);
855
856         for (i = 0; i < 100; i++) {
857                 mdelay(1);
858                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
859                         break;
860         }
861
862         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
863 }
864
865 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
866
867 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
868 {
869         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
870 }
871
872 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
873 {
874         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
875 }
876
877 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
878 {
879         r8168dp_2_mdio_start(ioaddr);
880
881         r8169_mdio_write(ioaddr, reg_addr, value);
882
883         r8168dp_2_mdio_stop(ioaddr);
884 }
885
886 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
887 {
888         int value;
889
890         r8168dp_2_mdio_start(ioaddr);
891
892         value = r8169_mdio_read(ioaddr, reg_addr);
893
894         r8168dp_2_mdio_stop(ioaddr);
895
896         return value;
897 }
898
899 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
900 {
901         tp->mdio_ops.write(tp->mmio_addr, location, val);
902 }
903
904 static int rtl_readphy(struct rtl8169_private *tp, int location)
905 {
906         return tp->mdio_ops.read(tp->mmio_addr, location);
907 }
908
909 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
910 {
911         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
912 }
913
914 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
915 {
916         int val;
917
918         val = rtl_readphy(tp, reg_addr);
919         rtl_writephy(tp, reg_addr, (val | p) & ~m);
920 }
921
922 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
923                            int val)
924 {
925         struct rtl8169_private *tp = netdev_priv(dev);
926
927         rtl_writephy(tp, location, val);
928 }
929
930 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
931 {
932         struct rtl8169_private *tp = netdev_priv(dev);
933
934         return rtl_readphy(tp, location);
935 }
936
937 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
938 {
939         unsigned int i;
940
941         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
942                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
943
944         for (i = 0; i < 100; i++) {
945                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
946                         break;
947                 udelay(10);
948         }
949 }
950
951 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
952 {
953         u16 value = 0xffff;
954         unsigned int i;
955
956         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
957
958         for (i = 0; i < 100; i++) {
959                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
960                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
961                         break;
962                 }
963                 udelay(10);
964         }
965
966         return value;
967 }
968
969 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
970 {
971         unsigned int i;
972
973         RTL_W32(CSIDR, value);
974         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
975                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
976
977         for (i = 0; i < 100; i++) {
978                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
979                         break;
980                 udelay(10);
981         }
982 }
983
984 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
985 {
986         u32 value = ~0x00;
987         unsigned int i;
988
989         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
990                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
991
992         for (i = 0; i < 100; i++) {
993                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
994                         value = RTL_R32(CSIDR);
995                         break;
996                 }
997                 udelay(10);
998         }
999
1000         return value;
1001 }
1002
1003 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1004 {
1005         u8 value = 0xff;
1006         unsigned int i;
1007
1008         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1009
1010         for (i = 0; i < 300; i++) {
1011                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1012                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1013                         break;
1014                 }
1015                 udelay(100);
1016         }
1017
1018         return value;
1019 }
1020
1021 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1022 {
1023         RTL_W16(IntrMask, 0x0000);
1024
1025         RTL_W16(IntrStatus, 0xffff);
1026 }
1027
1028 static void rtl8169_asic_down(void __iomem *ioaddr)
1029 {
1030         RTL_W8(ChipCmd, 0x00);
1031         rtl8169_irq_mask_and_ack(ioaddr);
1032         RTL_R16(CPlusCmd);
1033 }
1034
1035 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1036 {
1037         void __iomem *ioaddr = tp->mmio_addr;
1038
1039         return RTL_R32(TBICSR) & TBIReset;
1040 }
1041
1042 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1043 {
1044         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1045 }
1046
1047 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1048 {
1049         return RTL_R32(TBICSR) & TBILinkOk;
1050 }
1051
1052 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1053 {
1054         return RTL_R8(PHYstatus) & LinkStatus;
1055 }
1056
1057 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1058 {
1059         void __iomem *ioaddr = tp->mmio_addr;
1060
1061         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1062 }
1063
1064 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1065 {
1066         unsigned int val;
1067
1068         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1069         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1070 }
1071
1072 static void __rtl8169_check_link_status(struct net_device *dev,
1073                                         struct rtl8169_private *tp,
1074                                         void __iomem *ioaddr, bool pm)
1075 {
1076         unsigned long flags;
1077
1078         spin_lock_irqsave(&tp->lock, flags);
1079         if (tp->link_ok(ioaddr)) {
1080                 /* This is to cancel a scheduled suspend if there's one. */
1081                 if (pm)
1082                         pm_request_resume(&tp->pci_dev->dev);
1083                 netif_carrier_on(dev);
1084                 if (net_ratelimit())
1085                         netif_info(tp, ifup, dev, "link up\n");
1086         } else {
1087                 netif_carrier_off(dev);
1088                 netif_info(tp, ifdown, dev, "link down\n");
1089                 if (pm)
1090                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
1091         }
1092         spin_unlock_irqrestore(&tp->lock, flags);
1093 }
1094
1095 static void rtl8169_check_link_status(struct net_device *dev,
1096                                       struct rtl8169_private *tp,
1097                                       void __iomem *ioaddr)
1098 {
1099         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1100 }
1101
1102 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1103
1104 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1105 {
1106         void __iomem *ioaddr = tp->mmio_addr;
1107         u8 options;
1108         u32 wolopts = 0;
1109
1110         options = RTL_R8(Config1);
1111         if (!(options & PMEnable))
1112                 return 0;
1113
1114         options = RTL_R8(Config3);
1115         if (options & LinkUp)
1116                 wolopts |= WAKE_PHY;
1117         if (options & MagicPacket)
1118                 wolopts |= WAKE_MAGIC;
1119
1120         options = RTL_R8(Config5);
1121         if (options & UWF)
1122                 wolopts |= WAKE_UCAST;
1123         if (options & BWF)
1124                 wolopts |= WAKE_BCAST;
1125         if (options & MWF)
1126                 wolopts |= WAKE_MCAST;
1127
1128         return wolopts;
1129 }
1130
1131 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1132 {
1133         struct rtl8169_private *tp = netdev_priv(dev);
1134
1135         spin_lock_irq(&tp->lock);
1136
1137         wol->supported = WAKE_ANY;
1138         wol->wolopts = __rtl8169_get_wol(tp);
1139
1140         spin_unlock_irq(&tp->lock);
1141 }
1142
1143 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1144 {
1145         void __iomem *ioaddr = tp->mmio_addr;
1146         unsigned int i;
1147         static const struct {
1148                 u32 opt;
1149                 u16 reg;
1150                 u8  mask;
1151         } cfg[] = {
1152                 { WAKE_ANY,   Config1, PMEnable },
1153                 { WAKE_PHY,   Config3, LinkUp },
1154                 { WAKE_MAGIC, Config3, MagicPacket },
1155                 { WAKE_UCAST, Config5, UWF },
1156                 { WAKE_BCAST, Config5, BWF },
1157                 { WAKE_MCAST, Config5, MWF },
1158                 { WAKE_ANY,   Config5, LanWake }
1159         };
1160
1161         RTL_W8(Cfg9346, Cfg9346_Unlock);
1162
1163         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1164                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1165                 if (wolopts & cfg[i].opt)
1166                         options |= cfg[i].mask;
1167                 RTL_W8(cfg[i].reg, options);
1168         }
1169
1170         RTL_W8(Cfg9346, Cfg9346_Lock);
1171 }
1172
1173 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1174 {
1175         struct rtl8169_private *tp = netdev_priv(dev);
1176
1177         spin_lock_irq(&tp->lock);
1178
1179         if (wol->wolopts)
1180                 tp->features |= RTL_FEATURE_WOL;
1181         else
1182                 tp->features &= ~RTL_FEATURE_WOL;
1183         __rtl8169_set_wol(tp, wol->wolopts);
1184         spin_unlock_irq(&tp->lock);
1185
1186         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1187
1188         return 0;
1189 }
1190
1191 static void rtl8169_get_drvinfo(struct net_device *dev,
1192                                 struct ethtool_drvinfo *info)
1193 {
1194         struct rtl8169_private *tp = netdev_priv(dev);
1195
1196         strcpy(info->driver, MODULENAME);
1197         strcpy(info->version, RTL8169_VERSION);
1198         strcpy(info->bus_info, pci_name(tp->pci_dev));
1199 }
1200
1201 static int rtl8169_get_regs_len(struct net_device *dev)
1202 {
1203         return R8169_REGS_SIZE;
1204 }
1205
1206 static int rtl8169_set_speed_tbi(struct net_device *dev,
1207                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1208 {
1209         struct rtl8169_private *tp = netdev_priv(dev);
1210         void __iomem *ioaddr = tp->mmio_addr;
1211         int ret = 0;
1212         u32 reg;
1213
1214         reg = RTL_R32(TBICSR);
1215         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1216             (duplex == DUPLEX_FULL)) {
1217                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1218         } else if (autoneg == AUTONEG_ENABLE)
1219                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1220         else {
1221                 netif_warn(tp, link, dev,
1222                            "incorrect speed setting refused in TBI mode\n");
1223                 ret = -EOPNOTSUPP;
1224         }
1225
1226         return ret;
1227 }
1228
1229 static int rtl8169_set_speed_xmii(struct net_device *dev,
1230                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1231 {
1232         struct rtl8169_private *tp = netdev_priv(dev);
1233         int giga_ctrl, bmcr;
1234         int rc = -EINVAL;
1235
1236         rtl_writephy(tp, 0x1f, 0x0000);
1237
1238         if (autoneg == AUTONEG_ENABLE) {
1239                 int auto_nego;
1240
1241                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1242                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1243                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1244
1245                 if (adv & ADVERTISED_10baseT_Half)
1246                         auto_nego |= ADVERTISE_10HALF;
1247                 if (adv & ADVERTISED_10baseT_Full)
1248                         auto_nego |= ADVERTISE_10FULL;
1249                 if (adv & ADVERTISED_100baseT_Half)
1250                         auto_nego |= ADVERTISE_100HALF;
1251                 if (adv & ADVERTISED_100baseT_Full)
1252                         auto_nego |= ADVERTISE_100FULL;
1253
1254                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1255
1256                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1257                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1258
1259                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1260                 if (tp->mii.supports_gmii) {
1261                         if (adv & ADVERTISED_1000baseT_Half)
1262                                 giga_ctrl |= ADVERTISE_1000HALF;
1263                         if (adv & ADVERTISED_1000baseT_Full)
1264                                 giga_ctrl |= ADVERTISE_1000FULL;
1265                 } else if (adv & (ADVERTISED_1000baseT_Half |
1266                                   ADVERTISED_1000baseT_Full)) {
1267                         netif_info(tp, link, dev,
1268                                    "PHY does not support 1000Mbps\n");
1269                         goto out;
1270                 }
1271
1272                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1273
1274                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1275                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1276         } else {
1277                 giga_ctrl = 0;
1278
1279                 if (speed == SPEED_10)
1280                         bmcr = 0;
1281                 else if (speed == SPEED_100)
1282                         bmcr = BMCR_SPEED100;
1283                 else
1284                         goto out;
1285
1286                 if (duplex == DUPLEX_FULL)
1287                         bmcr |= BMCR_FULLDPLX;
1288         }
1289
1290         rtl_writephy(tp, MII_BMCR, bmcr);
1291
1292         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1293             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1294                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1295                         rtl_writephy(tp, 0x17, 0x2138);
1296                         rtl_writephy(tp, 0x0e, 0x0260);
1297                 } else {
1298                         rtl_writephy(tp, 0x17, 0x2108);
1299                         rtl_writephy(tp, 0x0e, 0x0000);
1300                 }
1301         }
1302
1303         rc = 0;
1304 out:
1305         return rc;
1306 }
1307
1308 static int rtl8169_set_speed(struct net_device *dev,
1309                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1310 {
1311         struct rtl8169_private *tp = netdev_priv(dev);
1312         int ret;
1313
1314         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1315         if (ret < 0)
1316                 goto out;
1317
1318         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1319             (advertising & ADVERTISED_1000baseT_Full)) {
1320                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1321         }
1322 out:
1323         return ret;
1324 }
1325
1326 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1327 {
1328         struct rtl8169_private *tp = netdev_priv(dev);
1329         unsigned long flags;
1330         int ret;
1331
1332         del_timer_sync(&tp->timer);
1333
1334         spin_lock_irqsave(&tp->lock, flags);
1335         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1336                                 cmd->duplex, cmd->advertising);
1337         spin_unlock_irqrestore(&tp->lock, flags);
1338
1339         return ret;
1340 }
1341
1342 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1343 {
1344         if (dev->mtu > TD_MSS_MAX)
1345                 features &= ~NETIF_F_ALL_TSO;
1346
1347         return features;
1348 }
1349
1350 static int rtl8169_set_features(struct net_device *dev, u32 features)
1351 {
1352         struct rtl8169_private *tp = netdev_priv(dev);
1353         void __iomem *ioaddr = tp->mmio_addr;
1354         unsigned long flags;
1355
1356         spin_lock_irqsave(&tp->lock, flags);
1357
1358         if (features & NETIF_F_RXCSUM)
1359                 tp->cp_cmd |= RxChkSum;
1360         else
1361                 tp->cp_cmd &= ~RxChkSum;
1362
1363         if (dev->features & NETIF_F_HW_VLAN_RX)
1364                 tp->cp_cmd |= RxVlan;
1365         else
1366                 tp->cp_cmd &= ~RxVlan;
1367
1368         RTL_W16(CPlusCmd, tp->cp_cmd);
1369         RTL_R16(CPlusCmd);
1370
1371         spin_unlock_irqrestore(&tp->lock, flags);
1372
1373         return 0;
1374 }
1375
1376 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1377                                       struct sk_buff *skb)
1378 {
1379         return (vlan_tx_tag_present(skb)) ?
1380                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1381 }
1382
1383 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1384 {
1385         u32 opts2 = le32_to_cpu(desc->opts2);
1386
1387         if (opts2 & RxVlanTag)
1388                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1389
1390         desc->opts2 = 0;
1391 }
1392
1393 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1394 {
1395         struct rtl8169_private *tp = netdev_priv(dev);
1396         void __iomem *ioaddr = tp->mmio_addr;
1397         u32 status;
1398
1399         cmd->supported =
1400                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1401         cmd->port = PORT_FIBRE;
1402         cmd->transceiver = XCVR_INTERNAL;
1403
1404         status = RTL_R32(TBICSR);
1405         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1406         cmd->autoneg = !!(status & TBINwEnable);
1407
1408         ethtool_cmd_speed_set(cmd, SPEED_1000);
1409         cmd->duplex = DUPLEX_FULL; /* Always set */
1410
1411         return 0;
1412 }
1413
1414 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1415 {
1416         struct rtl8169_private *tp = netdev_priv(dev);
1417
1418         return mii_ethtool_gset(&tp->mii, cmd);
1419 }
1420
1421 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1422 {
1423         struct rtl8169_private *tp = netdev_priv(dev);
1424         unsigned long flags;
1425         int rc;
1426
1427         spin_lock_irqsave(&tp->lock, flags);
1428
1429         rc = tp->get_settings(dev, cmd);
1430
1431         spin_unlock_irqrestore(&tp->lock, flags);
1432         return rc;
1433 }
1434
1435 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1436                              void *p)
1437 {
1438         struct rtl8169_private *tp = netdev_priv(dev);
1439         unsigned long flags;
1440
1441         if (regs->len > R8169_REGS_SIZE)
1442                 regs->len = R8169_REGS_SIZE;
1443
1444         spin_lock_irqsave(&tp->lock, flags);
1445         memcpy_fromio(p, tp->mmio_addr, regs->len);
1446         spin_unlock_irqrestore(&tp->lock, flags);
1447 }
1448
1449 static u32 rtl8169_get_msglevel(struct net_device *dev)
1450 {
1451         struct rtl8169_private *tp = netdev_priv(dev);
1452
1453         return tp->msg_enable;
1454 }
1455
1456 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1457 {
1458         struct rtl8169_private *tp = netdev_priv(dev);
1459
1460         tp->msg_enable = value;
1461 }
1462
1463 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1464         "tx_packets",
1465         "rx_packets",
1466         "tx_errors",
1467         "rx_errors",
1468         "rx_missed",
1469         "align_errors",
1470         "tx_single_collisions",
1471         "tx_multi_collisions",
1472         "unicast",
1473         "broadcast",
1474         "multicast",
1475         "tx_aborted",
1476         "tx_underrun",
1477 };
1478
1479 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1480 {
1481         switch (sset) {
1482         case ETH_SS_STATS:
1483                 return ARRAY_SIZE(rtl8169_gstrings);
1484         default:
1485                 return -EOPNOTSUPP;
1486         }
1487 }
1488
1489 static void rtl8169_update_counters(struct net_device *dev)
1490 {
1491         struct rtl8169_private *tp = netdev_priv(dev);
1492         void __iomem *ioaddr = tp->mmio_addr;
1493         struct device *d = &tp->pci_dev->dev;
1494         struct rtl8169_counters *counters;
1495         dma_addr_t paddr;
1496         u32 cmd;
1497         int wait = 1000;
1498
1499         /*
1500          * Some chips are unable to dump tally counters when the receiver
1501          * is disabled.
1502          */
1503         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1504                 return;
1505
1506         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1507         if (!counters)
1508                 return;
1509
1510         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1511         cmd = (u64)paddr & DMA_BIT_MASK(32);
1512         RTL_W32(CounterAddrLow, cmd);
1513         RTL_W32(CounterAddrLow, cmd | CounterDump);
1514
1515         while (wait--) {
1516                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1517                         memcpy(&tp->counters, counters, sizeof(*counters));
1518                         break;
1519                 }
1520                 udelay(10);
1521         }
1522
1523         RTL_W32(CounterAddrLow, 0);
1524         RTL_W32(CounterAddrHigh, 0);
1525
1526         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1527 }
1528
1529 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1530                                       struct ethtool_stats *stats, u64 *data)
1531 {
1532         struct rtl8169_private *tp = netdev_priv(dev);
1533
1534         ASSERT_RTNL();
1535
1536         rtl8169_update_counters(dev);
1537
1538         data[0] = le64_to_cpu(tp->counters.tx_packets);
1539         data[1] = le64_to_cpu(tp->counters.rx_packets);
1540         data[2] = le64_to_cpu(tp->counters.tx_errors);
1541         data[3] = le32_to_cpu(tp->counters.rx_errors);
1542         data[4] = le16_to_cpu(tp->counters.rx_missed);
1543         data[5] = le16_to_cpu(tp->counters.align_errors);
1544         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1545         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1546         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1547         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1548         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1549         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1550         data[12] = le16_to_cpu(tp->counters.tx_underun);
1551 }
1552
1553 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1554 {
1555         switch(stringset) {
1556         case ETH_SS_STATS:
1557                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1558                 break;
1559         }
1560 }
1561
1562 static const struct ethtool_ops rtl8169_ethtool_ops = {
1563         .get_drvinfo            = rtl8169_get_drvinfo,
1564         .get_regs_len           = rtl8169_get_regs_len,
1565         .get_link               = ethtool_op_get_link,
1566         .get_settings           = rtl8169_get_settings,
1567         .set_settings           = rtl8169_set_settings,
1568         .get_msglevel           = rtl8169_get_msglevel,
1569         .set_msglevel           = rtl8169_set_msglevel,
1570         .get_regs               = rtl8169_get_regs,
1571         .get_wol                = rtl8169_get_wol,
1572         .set_wol                = rtl8169_set_wol,
1573         .get_strings            = rtl8169_get_strings,
1574         .get_sset_count         = rtl8169_get_sset_count,
1575         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1576 };
1577
1578 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1579                                     void __iomem *ioaddr)
1580 {
1581         /*
1582          * The driver currently handles the 8168Bf and the 8168Be identically
1583          * but they can be identified more specifically through the test below
1584          * if needed:
1585          *
1586          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1587          *
1588          * Same thing for the 8101Eb and the 8101Ec:
1589          *
1590          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1591          */
1592         static const struct {
1593                 u32 mask;
1594                 u32 val;
1595                 int mac_version;
1596         } mac_info[] = {
1597                 /* 8168E family. */
1598                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1599                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1600                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1601
1602                 /* 8168D family. */
1603                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1604                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1605                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1606
1607                 /* 8168DP family. */
1608                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1609                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1610                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1611
1612                 /* 8168C family. */
1613                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1614                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1615                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1616                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1617                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1618                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1619                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1620                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1621                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1622
1623                 /* 8168B family. */
1624                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1625                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1626                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1627                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1628
1629                 /* 8101 family. */
1630                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1631                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1632                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1633                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1634                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1635                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1636                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1637                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1638                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1639                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1640                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1641                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1642                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1643                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1644                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1645                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1646                 /* FIXME: where did these entries come from ? -- FR */
1647                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1648                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1649
1650                 /* 8110 family. */
1651                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1652                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1653                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1654                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1655                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1656                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1657
1658                 /* Catch-all */
1659                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1660         }, *p = mac_info;
1661         u32 reg;
1662
1663         reg = RTL_R32(TxConfig);
1664         while ((reg & p->mask) != p->val)
1665                 p++;
1666         tp->mac_version = p->mac_version;
1667 }
1668
1669 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1670 {
1671         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1672 }
1673
1674 struct phy_reg {
1675         u16 reg;
1676         u16 val;
1677 };
1678
1679 static void rtl_writephy_batch(struct rtl8169_private *tp,
1680                                const struct phy_reg *regs, int len)
1681 {
1682         while (len-- > 0) {
1683                 rtl_writephy(tp, regs->reg, regs->val);
1684                 regs++;
1685         }
1686 }
1687
1688 #define PHY_READ                0x00000000
1689 #define PHY_DATA_OR             0x10000000
1690 #define PHY_DATA_AND            0x20000000
1691 #define PHY_BJMPN               0x30000000
1692 #define PHY_READ_EFUSE          0x40000000
1693 #define PHY_READ_MAC_BYTE       0x50000000
1694 #define PHY_WRITE_MAC_BYTE      0x60000000
1695 #define PHY_CLEAR_READCOUNT     0x70000000
1696 #define PHY_WRITE               0x80000000
1697 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1698 #define PHY_COMP_EQ_SKIPN       0xa0000000
1699 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1700 #define PHY_WRITE_PREVIOUS      0xc0000000
1701 #define PHY_SKIPN               0xd0000000
1702 #define PHY_DELAY_MS            0xe0000000
1703 #define PHY_WRITE_ERI_WORD      0xf0000000
1704
1705 static void
1706 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1707 {
1708         __le32 *phytable = (__le32 *)fw->data;
1709         struct net_device *dev = tp->dev;
1710         size_t index, fw_size = fw->size / sizeof(*phytable);
1711         u32 predata, count;
1712
1713         if (fw->size % sizeof(*phytable)) {
1714                 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1715                 return;
1716         }
1717
1718         for (index = 0; index < fw_size; index++) {
1719                 u32 action = le32_to_cpu(phytable[index]);
1720                 u32 regno = (action & 0x0fff0000) >> 16;
1721
1722                 switch(action & 0xf0000000) {
1723                 case PHY_READ:
1724                 case PHY_DATA_OR:
1725                 case PHY_DATA_AND:
1726                 case PHY_READ_EFUSE:
1727                 case PHY_CLEAR_READCOUNT:
1728                 case PHY_WRITE:
1729                 case PHY_WRITE_PREVIOUS:
1730                 case PHY_DELAY_MS:
1731                         break;
1732
1733                 case PHY_BJMPN:
1734                         if (regno > index) {
1735                                 netif_err(tp, probe, tp->dev,
1736                                           "Out of range of firmware\n");
1737                                 return;
1738                         }
1739                         break;
1740                 case PHY_READCOUNT_EQ_SKIP:
1741                         if (index + 2 >= fw_size) {
1742                                 netif_err(tp, probe, tp->dev,
1743                                           "Out of range of firmware\n");
1744                                 return;
1745                         }
1746                         break;
1747                 case PHY_COMP_EQ_SKIPN:
1748                 case PHY_COMP_NEQ_SKIPN:
1749                 case PHY_SKIPN:
1750                         if (index + 1 + regno >= fw_size) {
1751                                 netif_err(tp, probe, tp->dev,
1752                                           "Out of range of firmware\n");
1753                                 return;
1754                         }
1755                         break;
1756
1757                 case PHY_READ_MAC_BYTE:
1758                 case PHY_WRITE_MAC_BYTE:
1759                 case PHY_WRITE_ERI_WORD:
1760                 default:
1761                         netif_err(tp, probe, tp->dev,
1762                                   "Invalid action 0x%08x\n", action);
1763                         return;
1764                 }
1765         }
1766
1767         predata = 0;
1768         count = 0;
1769
1770         for (index = 0; index < fw_size; ) {
1771                 u32 action = le32_to_cpu(phytable[index]);
1772                 u32 data = action & 0x0000ffff;
1773                 u32 regno = (action & 0x0fff0000) >> 16;
1774
1775                 if (!action)
1776                         break;
1777
1778                 switch(action & 0xf0000000) {
1779                 case PHY_READ:
1780                         predata = rtl_readphy(tp, regno);
1781                         count++;
1782                         index++;
1783                         break;
1784                 case PHY_DATA_OR:
1785                         predata |= data;
1786                         index++;
1787                         break;
1788                 case PHY_DATA_AND:
1789                         predata &= data;
1790                         index++;
1791                         break;
1792                 case PHY_BJMPN:
1793                         index -= regno;
1794                         break;
1795                 case PHY_READ_EFUSE:
1796                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1797                         index++;
1798                         break;
1799                 case PHY_CLEAR_READCOUNT:
1800                         count = 0;
1801                         index++;
1802                         break;
1803                 case PHY_WRITE:
1804                         rtl_writephy(tp, regno, data);
1805                         index++;
1806                         break;
1807                 case PHY_READCOUNT_EQ_SKIP:
1808                         index += (count == data) ? 2 : 1;
1809                         break;
1810                 case PHY_COMP_EQ_SKIPN:
1811                         if (predata == data)
1812                                 index += regno;
1813                         index++;
1814                         break;
1815                 case PHY_COMP_NEQ_SKIPN:
1816                         if (predata != data)
1817                                 index += regno;
1818                         index++;
1819                         break;
1820                 case PHY_WRITE_PREVIOUS:
1821                         rtl_writephy(tp, regno, predata);
1822                         index++;
1823                         break;
1824                 case PHY_SKIPN:
1825                         index += regno + 1;
1826                         break;
1827                 case PHY_DELAY_MS:
1828                         mdelay(data);
1829                         index++;
1830                         break;
1831
1832                 case PHY_READ_MAC_BYTE:
1833                 case PHY_WRITE_MAC_BYTE:
1834                 case PHY_WRITE_ERI_WORD:
1835                 default:
1836                         BUG();
1837                 }
1838         }
1839 }
1840
1841 static void rtl_release_firmware(struct rtl8169_private *tp)
1842 {
1843         if (!IS_ERR_OR_NULL(tp->fw))
1844                 release_firmware(tp->fw);
1845         tp->fw = RTL_FIRMWARE_UNKNOWN;
1846 }
1847
1848 static void rtl_apply_firmware(struct rtl8169_private *tp)
1849 {
1850         const struct firmware *fw = tp->fw;
1851
1852         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1853         if (!IS_ERR_OR_NULL(fw))
1854                 rtl_phy_write_fw(tp, fw);
1855 }
1856
1857 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1858 {
1859         if (rtl_readphy(tp, reg) != val)
1860                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1861         else
1862                 rtl_apply_firmware(tp);
1863 }
1864
1865 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1866 {
1867         static const struct phy_reg phy_reg_init[] = {
1868                 { 0x1f, 0x0001 },
1869                 { 0x06, 0x006e },
1870                 { 0x08, 0x0708 },
1871                 { 0x15, 0x4000 },
1872                 { 0x18, 0x65c7 },
1873
1874                 { 0x1f, 0x0001 },
1875                 { 0x03, 0x00a1 },
1876                 { 0x02, 0x0008 },
1877                 { 0x01, 0x0120 },
1878                 { 0x00, 0x1000 },
1879                 { 0x04, 0x0800 },
1880                 { 0x04, 0x0000 },
1881
1882                 { 0x03, 0xff41 },
1883                 { 0x02, 0xdf60 },
1884                 { 0x01, 0x0140 },
1885                 { 0x00, 0x0077 },
1886                 { 0x04, 0x7800 },
1887                 { 0x04, 0x7000 },
1888
1889                 { 0x03, 0x802f },
1890                 { 0x02, 0x4f02 },
1891                 { 0x01, 0x0409 },
1892                 { 0x00, 0xf0f9 },
1893                 { 0x04, 0x9800 },
1894                 { 0x04, 0x9000 },
1895
1896                 { 0x03, 0xdf01 },
1897                 { 0x02, 0xdf20 },
1898                 { 0x01, 0xff95 },
1899                 { 0x00, 0xba00 },
1900                 { 0x04, 0xa800 },
1901                 { 0x04, 0xa000 },
1902
1903                 { 0x03, 0xff41 },
1904                 { 0x02, 0xdf20 },
1905                 { 0x01, 0x0140 },
1906                 { 0x00, 0x00bb },
1907                 { 0x04, 0xb800 },
1908                 { 0x04, 0xb000 },
1909
1910                 { 0x03, 0xdf41 },
1911                 { 0x02, 0xdc60 },
1912                 { 0x01, 0x6340 },
1913                 { 0x00, 0x007d },
1914                 { 0x04, 0xd800 },
1915                 { 0x04, 0xd000 },
1916
1917                 { 0x03, 0xdf01 },
1918                 { 0x02, 0xdf20 },
1919                 { 0x01, 0x100a },
1920                 { 0x00, 0xa0ff },
1921                 { 0x04, 0xf800 },
1922                 { 0x04, 0xf000 },
1923
1924                 { 0x1f, 0x0000 },
1925                 { 0x0b, 0x0000 },
1926                 { 0x00, 0x9200 }
1927         };
1928
1929         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1930 }
1931
1932 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1933 {
1934         static const struct phy_reg phy_reg_init[] = {
1935                 { 0x1f, 0x0002 },
1936                 { 0x01, 0x90d0 },
1937                 { 0x1f, 0x0000 }
1938         };
1939
1940         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1941 }
1942
1943 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1944 {
1945         struct pci_dev *pdev = tp->pci_dev;
1946         u16 vendor_id, device_id;
1947
1948         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1949         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1950
1951         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1952                 return;
1953
1954         rtl_writephy(tp, 0x1f, 0x0001);
1955         rtl_writephy(tp, 0x10, 0xf01b);
1956         rtl_writephy(tp, 0x1f, 0x0000);
1957 }
1958
1959 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
1960 {
1961         static const struct phy_reg phy_reg_init[] = {
1962                 { 0x1f, 0x0001 },
1963                 { 0x04, 0x0000 },
1964                 { 0x03, 0x00a1 },
1965                 { 0x02, 0x0008 },
1966                 { 0x01, 0x0120 },
1967                 { 0x00, 0x1000 },
1968                 { 0x04, 0x0800 },
1969                 { 0x04, 0x9000 },
1970                 { 0x03, 0x802f },
1971                 { 0x02, 0x4f02 },
1972                 { 0x01, 0x0409 },
1973                 { 0x00, 0xf099 },
1974                 { 0x04, 0x9800 },
1975                 { 0x04, 0xa000 },
1976                 { 0x03, 0xdf01 },
1977                 { 0x02, 0xdf20 },
1978                 { 0x01, 0xff95 },
1979                 { 0x00, 0xba00 },
1980                 { 0x04, 0xa800 },
1981                 { 0x04, 0xf000 },
1982                 { 0x03, 0xdf01 },
1983                 { 0x02, 0xdf20 },
1984                 { 0x01, 0x101a },
1985                 { 0x00, 0xa0ff },
1986                 { 0x04, 0xf800 },
1987                 { 0x04, 0x0000 },
1988                 { 0x1f, 0x0000 },
1989
1990                 { 0x1f, 0x0001 },
1991                 { 0x10, 0xf41b },
1992                 { 0x14, 0xfb54 },
1993                 { 0x18, 0xf5c7 },
1994                 { 0x1f, 0x0000 },
1995
1996                 { 0x1f, 0x0001 },
1997                 { 0x17, 0x0cc0 },
1998                 { 0x1f, 0x0000 }
1999         };
2000
2001         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2002
2003         rtl8169scd_hw_phy_config_quirk(tp);
2004 }
2005
2006 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2007 {
2008         static const struct phy_reg phy_reg_init[] = {
2009                 { 0x1f, 0x0001 },
2010                 { 0x04, 0x0000 },
2011                 { 0x03, 0x00a1 },
2012                 { 0x02, 0x0008 },
2013                 { 0x01, 0x0120 },
2014                 { 0x00, 0x1000 },
2015                 { 0x04, 0x0800 },
2016                 { 0x04, 0x9000 },
2017                 { 0x03, 0x802f },
2018                 { 0x02, 0x4f02 },
2019                 { 0x01, 0x0409 },
2020                 { 0x00, 0xf099 },
2021                 { 0x04, 0x9800 },
2022                 { 0x04, 0xa000 },
2023                 { 0x03, 0xdf01 },
2024                 { 0x02, 0xdf20 },
2025                 { 0x01, 0xff95 },
2026                 { 0x00, 0xba00 },
2027                 { 0x04, 0xa800 },
2028                 { 0x04, 0xf000 },
2029                 { 0x03, 0xdf01 },
2030                 { 0x02, 0xdf20 },
2031                 { 0x01, 0x101a },
2032                 { 0x00, 0xa0ff },
2033                 { 0x04, 0xf800 },
2034                 { 0x04, 0x0000 },
2035                 { 0x1f, 0x0000 },
2036
2037                 { 0x1f, 0x0001 },
2038                 { 0x0b, 0x8480 },
2039                 { 0x1f, 0x0000 },
2040
2041                 { 0x1f, 0x0001 },
2042                 { 0x18, 0x67c7 },
2043                 { 0x04, 0x2000 },
2044                 { 0x03, 0x002f },
2045                 { 0x02, 0x4360 },
2046                 { 0x01, 0x0109 },
2047                 { 0x00, 0x3022 },
2048                 { 0x04, 0x2800 },
2049                 { 0x1f, 0x0000 },
2050
2051                 { 0x1f, 0x0001 },
2052                 { 0x17, 0x0cc0 },
2053                 { 0x1f, 0x0000 }
2054         };
2055
2056         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2057 }
2058
2059 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2060 {
2061         static const struct phy_reg phy_reg_init[] = {
2062                 { 0x10, 0xf41b },
2063                 { 0x1f, 0x0000 }
2064         };
2065
2066         rtl_writephy(tp, 0x1f, 0x0001);
2067         rtl_patchphy(tp, 0x16, 1 << 0);
2068
2069         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2070 }
2071
2072 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2073 {
2074         static const struct phy_reg phy_reg_init[] = {
2075                 { 0x1f, 0x0001 },
2076                 { 0x10, 0xf41b },
2077                 { 0x1f, 0x0000 }
2078         };
2079
2080         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2081 }
2082
2083 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2084 {
2085         static const struct phy_reg phy_reg_init[] = {
2086                 { 0x1f, 0x0000 },
2087                 { 0x1d, 0x0f00 },
2088                 { 0x1f, 0x0002 },
2089                 { 0x0c, 0x1ec8 },
2090                 { 0x1f, 0x0000 }
2091         };
2092
2093         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2094 }
2095
2096 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2097 {
2098         static const struct phy_reg phy_reg_init[] = {
2099                 { 0x1f, 0x0001 },
2100                 { 0x1d, 0x3d98 },
2101                 { 0x1f, 0x0000 }
2102         };
2103
2104         rtl_writephy(tp, 0x1f, 0x0000);
2105         rtl_patchphy(tp, 0x14, 1 << 5);
2106         rtl_patchphy(tp, 0x0d, 1 << 5);
2107
2108         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2109 }
2110
2111 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2112 {
2113         static const struct phy_reg phy_reg_init[] = {
2114                 { 0x1f, 0x0001 },
2115                 { 0x12, 0x2300 },
2116                 { 0x1f, 0x0002 },
2117                 { 0x00, 0x88d4 },
2118                 { 0x01, 0x82b1 },
2119                 { 0x03, 0x7002 },
2120                 { 0x08, 0x9e30 },
2121                 { 0x09, 0x01f0 },
2122                 { 0x0a, 0x5500 },
2123                 { 0x0c, 0x00c8 },
2124                 { 0x1f, 0x0003 },
2125                 { 0x12, 0xc096 },
2126                 { 0x16, 0x000a },
2127                 { 0x1f, 0x0000 },
2128                 { 0x1f, 0x0000 },
2129                 { 0x09, 0x2000 },
2130                 { 0x09, 0x0000 }
2131         };
2132
2133         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2134
2135         rtl_patchphy(tp, 0x14, 1 << 5);
2136         rtl_patchphy(tp, 0x0d, 1 << 5);
2137         rtl_writephy(tp, 0x1f, 0x0000);
2138 }
2139
2140 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2141 {
2142         static const struct phy_reg phy_reg_init[] = {
2143                 { 0x1f, 0x0001 },
2144                 { 0x12, 0x2300 },
2145                 { 0x03, 0x802f },
2146                 { 0x02, 0x4f02 },
2147                 { 0x01, 0x0409 },
2148                 { 0x00, 0xf099 },
2149                 { 0x04, 0x9800 },
2150                 { 0x04, 0x9000 },
2151                 { 0x1d, 0x3d98 },
2152                 { 0x1f, 0x0002 },
2153                 { 0x0c, 0x7eb8 },
2154                 { 0x06, 0x0761 },
2155                 { 0x1f, 0x0003 },
2156                 { 0x16, 0x0f0a },
2157                 { 0x1f, 0x0000 }
2158         };
2159
2160         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2161
2162         rtl_patchphy(tp, 0x16, 1 << 0);
2163         rtl_patchphy(tp, 0x14, 1 << 5);
2164         rtl_patchphy(tp, 0x0d, 1 << 5);
2165         rtl_writephy(tp, 0x1f, 0x0000);
2166 }
2167
2168 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2169 {
2170         static const struct phy_reg phy_reg_init[] = {
2171                 { 0x1f, 0x0001 },
2172                 { 0x12, 0x2300 },
2173                 { 0x1d, 0x3d98 },
2174                 { 0x1f, 0x0002 },
2175                 { 0x0c, 0x7eb8 },
2176                 { 0x06, 0x5461 },
2177                 { 0x1f, 0x0003 },
2178                 { 0x16, 0x0f0a },
2179                 { 0x1f, 0x0000 }
2180         };
2181
2182         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2183
2184         rtl_patchphy(tp, 0x16, 1 << 0);
2185         rtl_patchphy(tp, 0x14, 1 << 5);
2186         rtl_patchphy(tp, 0x0d, 1 << 5);
2187         rtl_writephy(tp, 0x1f, 0x0000);
2188 }
2189
2190 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2191 {
2192         rtl8168c_3_hw_phy_config(tp);
2193 }
2194
2195 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2196 {
2197         static const struct phy_reg phy_reg_init_0[] = {
2198                 /* Channel Estimation */
2199                 { 0x1f, 0x0001 },
2200                 { 0x06, 0x4064 },
2201                 { 0x07, 0x2863 },
2202                 { 0x08, 0x059c },
2203                 { 0x09, 0x26b4 },
2204                 { 0x0a, 0x6a19 },
2205                 { 0x0b, 0xdcc8 },
2206                 { 0x10, 0xf06d },
2207                 { 0x14, 0x7f68 },
2208                 { 0x18, 0x7fd9 },
2209                 { 0x1c, 0xf0ff },
2210                 { 0x1d, 0x3d9c },
2211                 { 0x1f, 0x0003 },
2212                 { 0x12, 0xf49f },
2213                 { 0x13, 0x070b },
2214                 { 0x1a, 0x05ad },
2215                 { 0x14, 0x94c0 },
2216
2217                 /*
2218                  * Tx Error Issue
2219                  * Enhance line driver power
2220                  */
2221                 { 0x1f, 0x0002 },
2222                 { 0x06, 0x5561 },
2223                 { 0x1f, 0x0005 },
2224                 { 0x05, 0x8332 },
2225                 { 0x06, 0x5561 },
2226
2227                 /*
2228                  * Can not link to 1Gbps with bad cable
2229                  * Decrease SNR threshold form 21.07dB to 19.04dB
2230                  */
2231                 { 0x1f, 0x0001 },
2232                 { 0x17, 0x0cc0 },
2233
2234                 { 0x1f, 0x0000 },
2235                 { 0x0d, 0xf880 }
2236         };
2237         void __iomem *ioaddr = tp->mmio_addr;
2238
2239         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2240
2241         /*
2242          * Rx Error Issue
2243          * Fine Tune Switching regulator parameter
2244          */
2245         rtl_writephy(tp, 0x1f, 0x0002);
2246         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2247         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2248
2249         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2250                 static const struct phy_reg phy_reg_init[] = {
2251                         { 0x1f, 0x0002 },
2252                         { 0x05, 0x669a },
2253                         { 0x1f, 0x0005 },
2254                         { 0x05, 0x8330 },
2255                         { 0x06, 0x669a },
2256                         { 0x1f, 0x0002 }
2257                 };
2258                 int val;
2259
2260                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2261
2262                 val = rtl_readphy(tp, 0x0d);
2263
2264                 if ((val & 0x00ff) != 0x006c) {
2265                         static const u32 set[] = {
2266                                 0x0065, 0x0066, 0x0067, 0x0068,
2267                                 0x0069, 0x006a, 0x006b, 0x006c
2268                         };
2269                         int i;
2270
2271                         rtl_writephy(tp, 0x1f, 0x0002);
2272
2273                         val &= 0xff00;
2274                         for (i = 0; i < ARRAY_SIZE(set); i++)
2275                                 rtl_writephy(tp, 0x0d, val | set[i]);
2276                 }
2277         } else {
2278                 static const struct phy_reg phy_reg_init[] = {
2279                         { 0x1f, 0x0002 },
2280                         { 0x05, 0x6662 },
2281                         { 0x1f, 0x0005 },
2282                         { 0x05, 0x8330 },
2283                         { 0x06, 0x6662 }
2284                 };
2285
2286                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2287         }
2288
2289         /* RSET couple improve */
2290         rtl_writephy(tp, 0x1f, 0x0002);
2291         rtl_patchphy(tp, 0x0d, 0x0300);
2292         rtl_patchphy(tp, 0x0f, 0x0010);
2293
2294         /* Fine tune PLL performance */
2295         rtl_writephy(tp, 0x1f, 0x0002);
2296         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2297         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2298
2299         rtl_writephy(tp, 0x1f, 0x0005);
2300         rtl_writephy(tp, 0x05, 0x001b);
2301
2302         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2303
2304         rtl_writephy(tp, 0x1f, 0x0000);
2305 }
2306
2307 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2308 {
2309         static const struct phy_reg phy_reg_init_0[] = {
2310                 /* Channel Estimation */
2311                 { 0x1f, 0x0001 },
2312                 { 0x06, 0x4064 },
2313                 { 0x07, 0x2863 },
2314                 { 0x08, 0x059c },
2315                 { 0x09, 0x26b4 },
2316                 { 0x0a, 0x6a19 },
2317                 { 0x0b, 0xdcc8 },
2318                 { 0x10, 0xf06d },
2319                 { 0x14, 0x7f68 },
2320                 { 0x18, 0x7fd9 },
2321                 { 0x1c, 0xf0ff },
2322                 { 0x1d, 0x3d9c },
2323                 { 0x1f, 0x0003 },
2324                 { 0x12, 0xf49f },
2325                 { 0x13, 0x070b },
2326                 { 0x1a, 0x05ad },
2327                 { 0x14, 0x94c0 },
2328
2329                 /*
2330                  * Tx Error Issue
2331                  * Enhance line driver power
2332                  */
2333                 { 0x1f, 0x0002 },
2334                 { 0x06, 0x5561 },
2335                 { 0x1f, 0x0005 },
2336                 { 0x05, 0x8332 },
2337                 { 0x06, 0x5561 },
2338
2339                 /*
2340                  * Can not link to 1Gbps with bad cable
2341                  * Decrease SNR threshold form 21.07dB to 19.04dB
2342                  */
2343                 { 0x1f, 0x0001 },
2344                 { 0x17, 0x0cc0 },
2345
2346                 { 0x1f, 0x0000 },
2347                 { 0x0d, 0xf880 }
2348         };
2349         void __iomem *ioaddr = tp->mmio_addr;
2350
2351         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2352
2353         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2354                 static const struct phy_reg phy_reg_init[] = {
2355                         { 0x1f, 0x0002 },
2356                         { 0x05, 0x669a },
2357                         { 0x1f, 0x0005 },
2358                         { 0x05, 0x8330 },
2359                         { 0x06, 0x669a },
2360
2361                         { 0x1f, 0x0002 }
2362                 };
2363                 int val;
2364
2365                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2366
2367                 val = rtl_readphy(tp, 0x0d);
2368                 if ((val & 0x00ff) != 0x006c) {
2369                         static const u32 set[] = {
2370                                 0x0065, 0x0066, 0x0067, 0x0068,
2371                                 0x0069, 0x006a, 0x006b, 0x006c
2372                         };
2373                         int i;
2374
2375                         rtl_writephy(tp, 0x1f, 0x0002);
2376
2377                         val &= 0xff00;
2378                         for (i = 0; i < ARRAY_SIZE(set); i++)
2379                                 rtl_writephy(tp, 0x0d, val | set[i]);
2380                 }
2381         } else {
2382                 static const struct phy_reg phy_reg_init[] = {
2383                         { 0x1f, 0x0002 },
2384                         { 0x05, 0x2642 },
2385                         { 0x1f, 0x0005 },
2386                         { 0x05, 0x8330 },
2387                         { 0x06, 0x2642 }
2388                 };
2389
2390                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2391         }
2392
2393         /* Fine tune PLL performance */
2394         rtl_writephy(tp, 0x1f, 0x0002);
2395         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2396         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2397
2398         /* Switching regulator Slew rate */
2399         rtl_writephy(tp, 0x1f, 0x0002);
2400         rtl_patchphy(tp, 0x0f, 0x0017);
2401
2402         rtl_writephy(tp, 0x1f, 0x0005);
2403         rtl_writephy(tp, 0x05, 0x001b);
2404
2405         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2406
2407         rtl_writephy(tp, 0x1f, 0x0000);
2408 }
2409
2410 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2411 {
2412         static const struct phy_reg phy_reg_init[] = {
2413                 { 0x1f, 0x0002 },
2414                 { 0x10, 0x0008 },
2415                 { 0x0d, 0x006c },
2416
2417                 { 0x1f, 0x0000 },
2418                 { 0x0d, 0xf880 },
2419
2420                 { 0x1f, 0x0001 },
2421                 { 0x17, 0x0cc0 },
2422
2423                 { 0x1f, 0x0001 },
2424                 { 0x0b, 0xa4d8 },
2425                 { 0x09, 0x281c },
2426                 { 0x07, 0x2883 },
2427                 { 0x0a, 0x6b35 },
2428                 { 0x1d, 0x3da4 },
2429                 { 0x1c, 0xeffd },
2430                 { 0x14, 0x7f52 },
2431                 { 0x18, 0x7fc6 },
2432                 { 0x08, 0x0601 },
2433                 { 0x06, 0x4063 },
2434                 { 0x10, 0xf074 },
2435                 { 0x1f, 0x0003 },
2436                 { 0x13, 0x0789 },
2437                 { 0x12, 0xf4bd },
2438                 { 0x1a, 0x04fd },
2439                 { 0x14, 0x84b0 },
2440                 { 0x1f, 0x0000 },
2441                 { 0x00, 0x9200 },
2442
2443                 { 0x1f, 0x0005 },
2444                 { 0x01, 0x0340 },
2445                 { 0x1f, 0x0001 },
2446                 { 0x04, 0x4000 },
2447                 { 0x03, 0x1d21 },
2448                 { 0x02, 0x0c32 },
2449                 { 0x01, 0x0200 },
2450                 { 0x00, 0x5554 },
2451                 { 0x04, 0x4800 },
2452                 { 0x04, 0x4000 },
2453                 { 0x04, 0xf000 },
2454                 { 0x03, 0xdf01 },
2455                 { 0x02, 0xdf20 },
2456                 { 0x01, 0x101a },
2457                 { 0x00, 0xa0ff },
2458                 { 0x04, 0xf800 },
2459                 { 0x04, 0xf000 },
2460                 { 0x1f, 0x0000 },
2461
2462                 { 0x1f, 0x0007 },
2463                 { 0x1e, 0x0023 },
2464                 { 0x16, 0x0000 },
2465                 { 0x1f, 0x0000 }
2466         };
2467
2468         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2469 }
2470
2471 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2472 {
2473         static const struct phy_reg phy_reg_init[] = {
2474                 { 0x1f, 0x0001 },
2475                 { 0x17, 0x0cc0 },
2476
2477                 { 0x1f, 0x0007 },
2478                 { 0x1e, 0x002d },
2479                 { 0x18, 0x0040 },
2480                 { 0x1f, 0x0000 }
2481         };
2482
2483         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2484         rtl_patchphy(tp, 0x0d, 1 << 5);
2485 }
2486
2487 static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2488 {
2489         static const struct phy_reg phy_reg_init[] = {
2490                 /* Enable Delay cap */
2491                 { 0x1f, 0x0005 },
2492                 { 0x05, 0x8b80 },
2493                 { 0x06, 0xc896 },
2494                 { 0x1f, 0x0000 },
2495
2496                 /* Channel estimation fine tune */
2497                 { 0x1f, 0x0001 },
2498                 { 0x0b, 0x6c20 },
2499                 { 0x07, 0x2872 },
2500                 { 0x1c, 0xefff },
2501                 { 0x1f, 0x0003 },
2502                 { 0x14, 0x6420 },
2503                 { 0x1f, 0x0000 },
2504
2505                 /* Update PFM & 10M TX idle timer */
2506                 { 0x1f, 0x0007 },
2507                 { 0x1e, 0x002f },
2508                 { 0x15, 0x1919 },
2509                 { 0x1f, 0x0000 },
2510
2511                 { 0x1f, 0x0007 },
2512                 { 0x1e, 0x00ac },
2513                 { 0x18, 0x0006 },
2514                 { 0x1f, 0x0000 }
2515         };
2516
2517         rtl_apply_firmware(tp);
2518
2519         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2520
2521         /* DCO enable for 10M IDLE Power */
2522         rtl_writephy(tp, 0x1f, 0x0007);
2523         rtl_writephy(tp, 0x1e, 0x0023);
2524         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2525         rtl_writephy(tp, 0x1f, 0x0000);
2526
2527         /* For impedance matching */
2528         rtl_writephy(tp, 0x1f, 0x0002);
2529         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2530         rtl_writephy(tp, 0x1f, 0x0000);
2531
2532         /* PHY auto speed down */
2533         rtl_writephy(tp, 0x1f, 0x0007);
2534         rtl_writephy(tp, 0x1e, 0x002d);
2535         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2536         rtl_writephy(tp, 0x1f, 0x0000);
2537         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2538
2539         rtl_writephy(tp, 0x1f, 0x0005);
2540         rtl_writephy(tp, 0x05, 0x8b86);
2541         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2542         rtl_writephy(tp, 0x1f, 0x0000);
2543
2544         rtl_writephy(tp, 0x1f, 0x0005);
2545         rtl_writephy(tp, 0x05, 0x8b85);
2546         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2547         rtl_writephy(tp, 0x1f, 0x0007);
2548         rtl_writephy(tp, 0x1e, 0x0020);
2549         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2550         rtl_writephy(tp, 0x1f, 0x0006);
2551         rtl_writephy(tp, 0x00, 0x5a00);
2552         rtl_writephy(tp, 0x1f, 0x0000);
2553         rtl_writephy(tp, 0x0d, 0x0007);
2554         rtl_writephy(tp, 0x0e, 0x003c);
2555         rtl_writephy(tp, 0x0d, 0x4007);
2556         rtl_writephy(tp, 0x0e, 0x0000);
2557         rtl_writephy(tp, 0x0d, 0x0000);
2558 }
2559
2560 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2561 {
2562         static const struct phy_reg phy_reg_init[] = {
2563                 { 0x1f, 0x0003 },
2564                 { 0x08, 0x441d },
2565                 { 0x01, 0x9100 },
2566                 { 0x1f, 0x0000 }
2567         };
2568
2569         rtl_writephy(tp, 0x1f, 0x0000);
2570         rtl_patchphy(tp, 0x11, 1 << 12);
2571         rtl_patchphy(tp, 0x19, 1 << 13);
2572         rtl_patchphy(tp, 0x10, 1 << 15);
2573
2574         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2575 }
2576
2577 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2578 {
2579         static const struct phy_reg phy_reg_init[] = {
2580                 { 0x1f, 0x0005 },
2581                 { 0x1a, 0x0000 },
2582                 { 0x1f, 0x0000 },
2583
2584                 { 0x1f, 0x0004 },
2585                 { 0x1c, 0x0000 },
2586                 { 0x1f, 0x0000 },
2587
2588                 { 0x1f, 0x0001 },
2589                 { 0x15, 0x7701 },
2590                 { 0x1f, 0x0000 }
2591         };
2592
2593         /* Disable ALDPS before ram code */
2594         rtl_writephy(tp, 0x1f, 0x0000);
2595         rtl_writephy(tp, 0x18, 0x0310);
2596         msleep(100);
2597
2598         rtl_apply_firmware(tp);
2599
2600         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2601 }
2602
2603 static void rtl_hw_phy_config(struct net_device *dev)
2604 {
2605         struct rtl8169_private *tp = netdev_priv(dev);
2606
2607         rtl8169_print_mac_version(tp);
2608
2609         switch (tp->mac_version) {
2610         case RTL_GIGA_MAC_VER_01:
2611                 break;
2612         case RTL_GIGA_MAC_VER_02:
2613         case RTL_GIGA_MAC_VER_03:
2614                 rtl8169s_hw_phy_config(tp);
2615                 break;
2616         case RTL_GIGA_MAC_VER_04:
2617                 rtl8169sb_hw_phy_config(tp);
2618                 break;
2619         case RTL_GIGA_MAC_VER_05:
2620                 rtl8169scd_hw_phy_config(tp);
2621                 break;
2622         case RTL_GIGA_MAC_VER_06:
2623                 rtl8169sce_hw_phy_config(tp);
2624                 break;
2625         case RTL_GIGA_MAC_VER_07:
2626         case RTL_GIGA_MAC_VER_08:
2627         case RTL_GIGA_MAC_VER_09:
2628                 rtl8102e_hw_phy_config(tp);
2629                 break;
2630         case RTL_GIGA_MAC_VER_11:
2631                 rtl8168bb_hw_phy_config(tp);
2632                 break;
2633         case RTL_GIGA_MAC_VER_12:
2634                 rtl8168bef_hw_phy_config(tp);
2635                 break;
2636         case RTL_GIGA_MAC_VER_17:
2637                 rtl8168bef_hw_phy_config(tp);
2638                 break;
2639         case RTL_GIGA_MAC_VER_18:
2640                 rtl8168cp_1_hw_phy_config(tp);
2641                 break;
2642         case RTL_GIGA_MAC_VER_19:
2643                 rtl8168c_1_hw_phy_config(tp);
2644                 break;
2645         case RTL_GIGA_MAC_VER_20:
2646                 rtl8168c_2_hw_phy_config(tp);
2647                 break;
2648         case RTL_GIGA_MAC_VER_21:
2649                 rtl8168c_3_hw_phy_config(tp);
2650                 break;
2651         case RTL_GIGA_MAC_VER_22:
2652                 rtl8168c_4_hw_phy_config(tp);
2653                 break;
2654         case RTL_GIGA_MAC_VER_23:
2655         case RTL_GIGA_MAC_VER_24:
2656                 rtl8168cp_2_hw_phy_config(tp);
2657                 break;
2658         case RTL_GIGA_MAC_VER_25:
2659                 rtl8168d_1_hw_phy_config(tp);
2660                 break;
2661         case RTL_GIGA_MAC_VER_26:
2662                 rtl8168d_2_hw_phy_config(tp);
2663                 break;
2664         case RTL_GIGA_MAC_VER_27:
2665                 rtl8168d_3_hw_phy_config(tp);
2666                 break;
2667         case RTL_GIGA_MAC_VER_28:
2668                 rtl8168d_4_hw_phy_config(tp);
2669                 break;
2670         case RTL_GIGA_MAC_VER_29:
2671         case RTL_GIGA_MAC_VER_30:
2672                 rtl8105e_hw_phy_config(tp);
2673                 break;
2674         case RTL_GIGA_MAC_VER_31:
2675                 /* None. */
2676                 break;
2677         case RTL_GIGA_MAC_VER_32:
2678         case RTL_GIGA_MAC_VER_33:
2679                 rtl8168e_hw_phy_config(tp);
2680                 break;
2681
2682         default:
2683                 break;
2684         }
2685 }
2686
2687 static void rtl8169_phy_timer(unsigned long __opaque)
2688 {
2689         struct net_device *dev = (struct net_device *)__opaque;
2690         struct rtl8169_private *tp = netdev_priv(dev);
2691         struct timer_list *timer = &tp->timer;
2692         void __iomem *ioaddr = tp->mmio_addr;
2693         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2694
2695         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2696
2697         spin_lock_irq(&tp->lock);
2698
2699         if (tp->phy_reset_pending(tp)) {
2700                 /*
2701                  * A busy loop could burn quite a few cycles on nowadays CPU.
2702                  * Let's delay the execution of the timer for a few ticks.
2703                  */
2704                 timeout = HZ/10;
2705                 goto out_mod_timer;
2706         }
2707
2708         if (tp->link_ok(ioaddr))
2709                 goto out_unlock;
2710
2711         netif_warn(tp, link, dev, "PHY reset until link up\n");
2712
2713         tp->phy_reset_enable(tp);
2714
2715 out_mod_timer:
2716         mod_timer(timer, jiffies + timeout);
2717 out_unlock:
2718         spin_unlock_irq(&tp->lock);
2719 }
2720
2721 #ifdef CONFIG_NET_POLL_CONTROLLER
2722 /*
2723  * Polling 'interrupt' - used by things like netconsole to send skbs
2724  * without having to re-enable interrupts. It's not called while
2725  * the interrupt routine is executing.
2726  */
2727 static void rtl8169_netpoll(struct net_device *dev)
2728 {
2729         struct rtl8169_private *tp = netdev_priv(dev);
2730         struct pci_dev *pdev = tp->pci_dev;
2731
2732         disable_irq(pdev->irq);
2733         rtl8169_interrupt(pdev->irq, dev);
2734         enable_irq(pdev->irq);
2735 }
2736 #endif
2737
2738 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2739                                   void __iomem *ioaddr)
2740 {
2741         iounmap(ioaddr);
2742         pci_release_regions(pdev);
2743         pci_clear_mwi(pdev);
2744         pci_disable_device(pdev);
2745         free_netdev(dev);
2746 }
2747
2748 static void rtl8169_phy_reset(struct net_device *dev,
2749                               struct rtl8169_private *tp)
2750 {
2751         unsigned int i;
2752
2753         tp->phy_reset_enable(tp);
2754         for (i = 0; i < 100; i++) {
2755                 if (!tp->phy_reset_pending(tp))
2756                         return;
2757                 msleep(1);
2758         }
2759         netif_err(tp, link, dev, "PHY reset failed\n");
2760 }
2761
2762 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2763 {
2764         void __iomem *ioaddr = tp->mmio_addr;
2765
2766         rtl_hw_phy_config(dev);
2767
2768         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2769                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2770                 RTL_W8(0x82, 0x01);
2771         }
2772
2773         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2774
2775         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2776                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2777
2778         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2779                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2780                 RTL_W8(0x82, 0x01);
2781                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2782                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2783         }
2784
2785         rtl8169_phy_reset(dev, tp);
2786
2787         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2788                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2789                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2790                           (tp->mii.supports_gmii ?
2791                            ADVERTISED_1000baseT_Half |
2792                            ADVERTISED_1000baseT_Full : 0));
2793
2794         if (RTL_R8(PHYstatus) & TBI_Enable)
2795                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2796 }
2797
2798 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2799 {
2800         void __iomem *ioaddr = tp->mmio_addr;
2801         u32 high;
2802         u32 low;
2803
2804         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2805         high = addr[4] | (addr[5] << 8);
2806
2807         spin_lock_irq(&tp->lock);
2808
2809         RTL_W8(Cfg9346, Cfg9346_Unlock);
2810
2811         RTL_W32(MAC4, high);
2812         RTL_R32(MAC4);
2813
2814         RTL_W32(MAC0, low);
2815         RTL_R32(MAC0);
2816
2817         RTL_W8(Cfg9346, Cfg9346_Lock);
2818
2819         spin_unlock_irq(&tp->lock);
2820 }
2821
2822 static int rtl_set_mac_address(struct net_device *dev, void *p)
2823 {
2824         struct rtl8169_private *tp = netdev_priv(dev);
2825         struct sockaddr *addr = p;
2826
2827         if (!is_valid_ether_addr(addr->sa_data))
2828                 return -EADDRNOTAVAIL;
2829
2830         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2831
2832         rtl_rar_set(tp, dev->dev_addr);
2833
2834         return 0;
2835 }
2836
2837 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2838 {
2839         struct rtl8169_private *tp = netdev_priv(dev);
2840         struct mii_ioctl_data *data = if_mii(ifr);
2841
2842         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2843 }
2844
2845 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2846                           struct mii_ioctl_data *data, int cmd)
2847 {
2848         switch (cmd) {
2849         case SIOCGMIIPHY:
2850                 data->phy_id = 32; /* Internal PHY */
2851                 return 0;
2852
2853         case SIOCGMIIREG:
2854                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2855                 return 0;
2856
2857         case SIOCSMIIREG:
2858                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2859                 return 0;
2860         }
2861         return -EOPNOTSUPP;
2862 }
2863
2864 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2865 {
2866         return -EOPNOTSUPP;
2867 }
2868
2869 static const struct rtl_cfg_info {
2870         void (*hw_start)(struct net_device *);
2871         unsigned int region;
2872         unsigned int align;
2873         u16 intr_event;
2874         u16 napi_event;
2875         unsigned features;
2876         u8 default_ver;
2877 } rtl_cfg_infos [] = {
2878         [RTL_CFG_0] = {
2879                 .hw_start       = rtl_hw_start_8169,
2880                 .region         = 1,
2881                 .align          = 0,
2882                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2883                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2884                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2885                 .features       = RTL_FEATURE_GMII,
2886                 .default_ver    = RTL_GIGA_MAC_VER_01,
2887         },
2888         [RTL_CFG_1] = {
2889                 .hw_start       = rtl_hw_start_8168,
2890                 .region         = 2,
2891                 .align          = 8,
2892                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2893                                   TxErr | TxOK | RxOK | RxErr,
2894                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
2895                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2896                 .default_ver    = RTL_GIGA_MAC_VER_11,
2897         },
2898         [RTL_CFG_2] = {
2899                 .hw_start       = rtl_hw_start_8101,
2900                 .region         = 2,
2901                 .align          = 8,
2902                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2903                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2904                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2905                 .features       = RTL_FEATURE_MSI,
2906                 .default_ver    = RTL_GIGA_MAC_VER_13,
2907         }
2908 };
2909
2910 /* Cfg9346_Unlock assumed. */
2911 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2912                             const struct rtl_cfg_info *cfg)
2913 {
2914         unsigned msi = 0;
2915         u8 cfg2;
2916
2917         cfg2 = RTL_R8(Config2) & ~MSIEnable;
2918         if (cfg->features & RTL_FEATURE_MSI) {
2919                 if (pci_enable_msi(pdev)) {
2920                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2921                 } else {
2922                         cfg2 |= MSIEnable;
2923                         msi = RTL_FEATURE_MSI;
2924                 }
2925         }
2926         RTL_W8(Config2, cfg2);
2927         return msi;
2928 }
2929
2930 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2931 {
2932         if (tp->features & RTL_FEATURE_MSI) {
2933                 pci_disable_msi(pdev);
2934                 tp->features &= ~RTL_FEATURE_MSI;
2935         }
2936 }
2937
2938 static const struct net_device_ops rtl8169_netdev_ops = {
2939         .ndo_open               = rtl8169_open,
2940         .ndo_stop               = rtl8169_close,
2941         .ndo_get_stats          = rtl8169_get_stats,
2942         .ndo_start_xmit         = rtl8169_start_xmit,
2943         .ndo_tx_timeout         = rtl8169_tx_timeout,
2944         .ndo_validate_addr      = eth_validate_addr,
2945         .ndo_change_mtu         = rtl8169_change_mtu,
2946         .ndo_fix_features       = rtl8169_fix_features,
2947         .ndo_set_features       = rtl8169_set_features,
2948         .ndo_set_mac_address    = rtl_set_mac_address,
2949         .ndo_do_ioctl           = rtl8169_ioctl,
2950         .ndo_set_multicast_list = rtl_set_rx_mode,
2951 #ifdef CONFIG_NET_POLL_CONTROLLER
2952         .ndo_poll_controller    = rtl8169_netpoll,
2953 #endif
2954
2955 };
2956
2957 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2958 {
2959         struct mdio_ops *ops = &tp->mdio_ops;
2960
2961         switch (tp->mac_version) {
2962         case RTL_GIGA_MAC_VER_27:
2963                 ops->write      = r8168dp_1_mdio_write;
2964                 ops->read       = r8168dp_1_mdio_read;
2965                 break;
2966         case RTL_GIGA_MAC_VER_28:
2967         case RTL_GIGA_MAC_VER_31:
2968                 ops->write      = r8168dp_2_mdio_write;
2969                 ops->read       = r8168dp_2_mdio_read;
2970                 break;
2971         default:
2972                 ops->write      = r8169_mdio_write;
2973                 ops->read       = r8169_mdio_read;
2974                 break;
2975         }
2976 }
2977
2978 static void r810x_phy_power_down(struct rtl8169_private *tp)
2979 {
2980         rtl_writephy(tp, 0x1f, 0x0000);
2981         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2982 }
2983
2984 static void r810x_phy_power_up(struct rtl8169_private *tp)
2985 {
2986         rtl_writephy(tp, 0x1f, 0x0000);
2987         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2988 }
2989
2990 static void r810x_pll_power_down(struct rtl8169_private *tp)
2991 {
2992         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2993                 rtl_writephy(tp, 0x1f, 0x0000);
2994                 rtl_writephy(tp, MII_BMCR, 0x0000);
2995                 return;
2996         }
2997
2998         r810x_phy_power_down(tp);
2999 }
3000
3001 static void r810x_pll_power_up(struct rtl8169_private *tp)
3002 {
3003         r810x_phy_power_up(tp);
3004 }
3005
3006 static void r8168_phy_power_up(struct rtl8169_private *tp)
3007 {
3008         rtl_writephy(tp, 0x1f, 0x0000);
3009         switch (tp->mac_version) {
3010         case RTL_GIGA_MAC_VER_11:
3011         case RTL_GIGA_MAC_VER_12:
3012         case RTL_GIGA_MAC_VER_17:
3013         case RTL_GIGA_MAC_VER_18:
3014         case RTL_GIGA_MAC_VER_19:
3015         case RTL_GIGA_MAC_VER_20:
3016         case RTL_GIGA_MAC_VER_21:
3017         case RTL_GIGA_MAC_VER_22:
3018         case RTL_GIGA_MAC_VER_23:
3019         case RTL_GIGA_MAC_VER_24:
3020         case RTL_GIGA_MAC_VER_25:
3021         case RTL_GIGA_MAC_VER_26:
3022         case RTL_GIGA_MAC_VER_27:
3023         case RTL_GIGA_MAC_VER_28:
3024         case RTL_GIGA_MAC_VER_31:
3025                 rtl_writephy(tp, 0x0e, 0x0000);
3026                 break;
3027         default:
3028                 break;
3029         }
3030         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3031 }
3032
3033 static void r8168_phy_power_down(struct rtl8169_private *tp)
3034 {
3035         rtl_writephy(tp, 0x1f, 0x0000);
3036         switch (tp->mac_version) {
3037         case RTL_GIGA_MAC_VER_32:
3038         case RTL_GIGA_MAC_VER_33:
3039                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3040                 break;
3041
3042         case RTL_GIGA_MAC_VER_11:
3043         case RTL_GIGA_MAC_VER_12:
3044         case RTL_GIGA_MAC_VER_17:
3045         case RTL_GIGA_MAC_VER_18:
3046         case RTL_GIGA_MAC_VER_19:
3047         case RTL_GIGA_MAC_VER_20:
3048         case RTL_GIGA_MAC_VER_21:
3049         case RTL_GIGA_MAC_VER_22:
3050         case RTL_GIGA_MAC_VER_23:
3051         case RTL_GIGA_MAC_VER_24:
3052         case RTL_GIGA_MAC_VER_25:
3053         case RTL_GIGA_MAC_VER_26:
3054         case RTL_GIGA_MAC_VER_27:
3055         case RTL_GIGA_MAC_VER_28:
3056         case RTL_GIGA_MAC_VER_31:
3057                 rtl_writephy(tp, 0x0e, 0x0200);
3058         default:
3059                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3060                 break;
3061         }
3062 }
3063
3064 static void r8168_pll_power_down(struct rtl8169_private *tp)
3065 {
3066         void __iomem *ioaddr = tp->mmio_addr;
3067
3068         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3069              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3070              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3071             r8168dp_check_dash(tp)) {
3072                 return;
3073         }
3074
3075         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3076              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3077             (RTL_R16(CPlusCmd) & ASF)) {
3078                 return;
3079         }
3080
3081         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3082             tp->mac_version == RTL_GIGA_MAC_VER_33)
3083                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3084
3085         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3086                 rtl_writephy(tp, 0x1f, 0x0000);
3087                 rtl_writephy(tp, MII_BMCR, 0x0000);
3088
3089                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3090                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3091                 return;
3092         }
3093
3094         r8168_phy_power_down(tp);
3095
3096         switch (tp->mac_version) {
3097         case RTL_GIGA_MAC_VER_25:
3098         case RTL_GIGA_MAC_VER_26:
3099         case RTL_GIGA_MAC_VER_27:
3100         case RTL_GIGA_MAC_VER_28:
3101         case RTL_GIGA_MAC_VER_31:
3102         case RTL_GIGA_MAC_VER_32:
3103         case RTL_GIGA_MAC_VER_33:
3104                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3105                 break;
3106         }
3107 }
3108
3109 static void r8168_pll_power_up(struct rtl8169_private *tp)
3110 {
3111         void __iomem *ioaddr = tp->mmio_addr;
3112
3113         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3114              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3115              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3116             r8168dp_check_dash(tp)) {
3117                 return;
3118         }
3119
3120         switch (tp->mac_version) {
3121         case RTL_GIGA_MAC_VER_25:
3122         case RTL_GIGA_MAC_VER_26:
3123         case RTL_GIGA_MAC_VER_27:
3124         case RTL_GIGA_MAC_VER_28:
3125         case RTL_GIGA_MAC_VER_31:
3126         case RTL_GIGA_MAC_VER_32:
3127         case RTL_GIGA_MAC_VER_33:
3128                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3129                 break;
3130         }
3131
3132         r8168_phy_power_up(tp);
3133 }
3134
3135 static void rtl_pll_power_op(struct rtl8169_private *tp,
3136                              void (*op)(struct rtl8169_private *))
3137 {
3138         if (op)
3139                 op(tp);
3140 }
3141
3142 static void rtl_pll_power_down(struct rtl8169_private *tp)
3143 {
3144         rtl_pll_power_op(tp, tp->pll_power_ops.down);
3145 }
3146
3147 static void rtl_pll_power_up(struct rtl8169_private *tp)
3148 {
3149         rtl_pll_power_op(tp, tp->pll_power_ops.up);
3150 }
3151
3152 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3153 {
3154         struct pll_power_ops *ops = &tp->pll_power_ops;
3155
3156         switch (tp->mac_version) {
3157         case RTL_GIGA_MAC_VER_07:
3158         case RTL_GIGA_MAC_VER_08:
3159         case RTL_GIGA_MAC_VER_09:
3160         case RTL_GIGA_MAC_VER_10:
3161         case RTL_GIGA_MAC_VER_16:
3162         case RTL_GIGA_MAC_VER_29:
3163         case RTL_GIGA_MAC_VER_30:
3164                 ops->down       = r810x_pll_power_down;
3165                 ops->up         = r810x_pll_power_up;
3166                 break;
3167
3168         case RTL_GIGA_MAC_VER_11:
3169         case RTL_GIGA_MAC_VER_12:
3170         case RTL_GIGA_MAC_VER_17:
3171         case RTL_GIGA_MAC_VER_18:
3172         case RTL_GIGA_MAC_VER_19:
3173         case RTL_GIGA_MAC_VER_20:
3174         case RTL_GIGA_MAC_VER_21:
3175         case RTL_GIGA_MAC_VER_22:
3176         case RTL_GIGA_MAC_VER_23:
3177         case RTL_GIGA_MAC_VER_24:
3178         case RTL_GIGA_MAC_VER_25:
3179         case RTL_GIGA_MAC_VER_26:
3180         case RTL_GIGA_MAC_VER_27:
3181         case RTL_GIGA_MAC_VER_28:
3182         case RTL_GIGA_MAC_VER_31:
3183         case RTL_GIGA_MAC_VER_32:
3184         case RTL_GIGA_MAC_VER_33:
3185                 ops->down       = r8168_pll_power_down;
3186                 ops->up         = r8168_pll_power_up;
3187                 break;
3188
3189         default:
3190                 ops->down       = NULL;
3191                 ops->up         = NULL;
3192                 break;
3193         }
3194 }
3195
3196 static void rtl_hw_reset(struct rtl8169_private *tp)
3197 {
3198         void __iomem *ioaddr = tp->mmio_addr;
3199         int i;
3200
3201         /* Soft reset the chip. */
3202         RTL_W8(ChipCmd, CmdReset);
3203
3204         /* Check that the chip has finished the reset. */
3205         for (i = 0; i < 100; i++) {
3206                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3207                         break;
3208                 msleep_interruptible(1);
3209         }
3210 }
3211
3212 static int __devinit
3213 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3214 {
3215         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3216         const unsigned int region = cfg->region;
3217         struct rtl8169_private *tp;
3218         struct mii_if_info *mii;
3219         struct net_device *dev;
3220         void __iomem *ioaddr;
3221         int chipset, i;
3222         int rc;
3223
3224         if (netif_msg_drv(&debug)) {
3225                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3226                        MODULENAME, RTL8169_VERSION);
3227         }
3228
3229         dev = alloc_etherdev(sizeof (*tp));
3230         if (!dev) {
3231                 if (netif_msg_drv(&debug))
3232                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3233                 rc = -ENOMEM;
3234                 goto out;
3235         }
3236
3237         SET_NETDEV_DEV(dev, &pdev->dev);
3238         dev->netdev_ops = &rtl8169_netdev_ops;
3239         tp = netdev_priv(dev);
3240         tp->dev = dev;
3241         tp->pci_dev = pdev;
3242         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3243
3244         mii = &tp->mii;
3245         mii->dev = dev;
3246         mii->mdio_read = rtl_mdio_read;
3247         mii->mdio_write = rtl_mdio_write;
3248         mii->phy_id_mask = 0x1f;
3249         mii->reg_num_mask = 0x1f;
3250         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3251
3252         /* disable ASPM completely as that cause random device stop working
3253          * problems as well as full system hangs for some PCIe devices users */
3254         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3255                                      PCIE_LINK_STATE_CLKPM);
3256
3257         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3258         rc = pci_enable_device(pdev);
3259         if (rc < 0) {
3260                 netif_err(tp, probe, dev, "enable failure\n");
3261                 goto err_out_free_dev_1;
3262         }
3263
3264         if (pci_set_mwi(pdev) < 0)
3265                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3266
3267         /* make sure PCI base addr 1 is MMIO */
3268         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3269                 netif_err(tp, probe, dev,
3270                           "region #%d not an MMIO resource, aborting\n",
3271                           region);
3272                 rc = -ENODEV;
3273                 goto err_out_mwi_2;
3274         }
3275
3276         /* check for weird/broken PCI region reporting */
3277         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3278                 netif_err(tp, probe, dev,
3279                           "Invalid PCI region size(s), aborting\n");
3280                 rc = -ENODEV;
3281                 goto err_out_mwi_2;
3282         }
3283
3284         rc = pci_request_regions(pdev, MODULENAME);
3285         if (rc < 0) {
3286                 netif_err(tp, probe, dev, "could not request regions\n");
3287                 goto err_out_mwi_2;
3288         }
3289
3290         tp->cp_cmd = RxChkSum;
3291
3292         if ((sizeof(dma_addr_t) > 4) &&
3293             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3294                 tp->cp_cmd |= PCIDAC;
3295                 dev->features |= NETIF_F_HIGHDMA;
3296         } else {
3297                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3298                 if (rc < 0) {
3299                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3300                         goto err_out_free_res_3;
3301                 }
3302         }
3303
3304         /* ioremap MMIO region */
3305         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3306         if (!ioaddr) {
3307                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3308                 rc = -EIO;
3309                 goto err_out_free_res_3;
3310         }
3311         tp->mmio_addr = ioaddr;
3312
3313         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3314         if (!tp->pcie_cap)
3315                 netif_info(tp, probe, dev, "no PCI Express capability\n");
3316
3317         RTL_W16(IntrMask, 0x0000);
3318
3319         rtl_hw_reset(tp);
3320
3321         RTL_W16(IntrStatus, 0xffff);
3322
3323         pci_set_master(pdev);
3324
3325         /* Identify chip attached to board */
3326         rtl8169_get_mac_version(tp, ioaddr);
3327
3328         /*
3329          * Pretend we are using VLANs; This bypasses a nasty bug where
3330          * Interrupts stop flowing on high load on 8110SCd controllers.
3331          */
3332         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3333                 tp->cp_cmd |= RxVlan;
3334
3335         rtl_init_mdio_ops(tp);
3336         rtl_init_pll_power_ops(tp);
3337
3338         /* Use appropriate default if unknown */
3339         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3340                 netif_notice(tp, probe, dev,
3341                              "unknown MAC, using family default\n");
3342                 tp->mac_version = cfg->default_ver;
3343         }
3344
3345         rtl8169_print_mac_version(tp);
3346
3347         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3348                 if (tp->mac_version == rtl_chip_info[i].mac_version)
3349                         break;
3350         }
3351         if (i == ARRAY_SIZE(rtl_chip_info)) {
3352                 dev_err(&pdev->dev,
3353                         "driver bug, MAC version not found in rtl_chip_info\n");
3354                 goto err_out_msi_4;
3355         }
3356         chipset = i;
3357         tp->txd_version = rtl_chip_info[chipset].txd_version;
3358
3359         RTL_W8(Cfg9346, Cfg9346_Unlock);
3360         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3361         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3362         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3363                 tp->features |= RTL_FEATURE_WOL;
3364         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3365                 tp->features |= RTL_FEATURE_WOL;
3366         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3367         RTL_W8(Cfg9346, Cfg9346_Lock);
3368
3369         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3370             (RTL_R8(PHYstatus) & TBI_Enable)) {
3371                 tp->set_speed = rtl8169_set_speed_tbi;
3372                 tp->get_settings = rtl8169_gset_tbi;
3373                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3374                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3375                 tp->link_ok = rtl8169_tbi_link_ok;
3376                 tp->do_ioctl = rtl_tbi_ioctl;
3377         } else {
3378                 tp->set_speed = rtl8169_set_speed_xmii;
3379                 tp->get_settings = rtl8169_gset_xmii;
3380                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3381                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3382                 tp->link_ok = rtl8169_xmii_link_ok;
3383                 tp->do_ioctl = rtl_xmii_ioctl;
3384         }
3385
3386         spin_lock_init(&tp->lock);
3387
3388         /* Get MAC address */
3389         for (i = 0; i < MAC_ADDR_LEN; i++)
3390                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3391         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3392
3393         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3394         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3395         dev->irq = pdev->irq;
3396         dev->base_addr = (unsigned long) ioaddr;
3397
3398         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3399
3400         /* don't enable SG, IP_CSUM and TSO by default - it might not work
3401          * properly for all devices */
3402         dev->features |= NETIF_F_RXCSUM |
3403                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3404
3405         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3406                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3407         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3408                 NETIF_F_HIGHDMA;
3409
3410         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3411                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3412                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3413
3414         tp->intr_mask = 0xffff;
3415         tp->hw_start = cfg->hw_start;
3416         tp->intr_event = cfg->intr_event;
3417         tp->napi_event = cfg->napi_event;
3418
3419         init_timer(&tp->timer);
3420         tp->timer.data = (unsigned long) dev;
3421         tp->timer.function = rtl8169_phy_timer;
3422
3423         tp->fw = RTL_FIRMWARE_UNKNOWN;
3424
3425         rc = register_netdev(dev);
3426         if (rc < 0)
3427                 goto err_out_msi_4;
3428
3429         pci_set_drvdata(pdev, dev);
3430
3431         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3432                    rtl_chip_info[chipset].name, dev->base_addr, dev->dev_addr,
3433                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3434
3435         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3436             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3437             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3438                 rtl8168_driver_start(tp);
3439         }
3440
3441         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3442
3443         if (pci_dev_run_wake(pdev))
3444                 pm_runtime_put_noidle(&pdev->dev);
3445
3446         netif_carrier_off(dev);
3447
3448 out:
3449         return rc;
3450
3451 err_out_msi_4:
3452         rtl_disable_msi(pdev, tp);
3453         iounmap(ioaddr);
3454 err_out_free_res_3:
3455         pci_release_regions(pdev);
3456 err_out_mwi_2:
3457         pci_clear_mwi(pdev);
3458         pci_disable_device(pdev);
3459 err_out_free_dev_1:
3460         free_netdev(dev);
3461         goto out;
3462 }
3463
3464 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3465 {
3466         struct net_device *dev = pci_get_drvdata(pdev);
3467         struct rtl8169_private *tp = netdev_priv(dev);
3468
3469         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3470             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3471             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3472                 rtl8168_driver_stop(tp);
3473         }
3474
3475         cancel_delayed_work_sync(&tp->task);
3476
3477         unregister_netdev(dev);
3478
3479         rtl_release_firmware(tp);
3480
3481         if (pci_dev_run_wake(pdev))
3482                 pm_runtime_get_noresume(&pdev->dev);
3483
3484         /* restore original MAC address */
3485         rtl_rar_set(tp, dev->perm_addr);
3486
3487         rtl_disable_msi(pdev, tp);
3488         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3489         pci_set_drvdata(pdev, NULL);
3490 }
3491
3492 static void rtl_request_firmware(struct rtl8169_private *tp)
3493 {
3494         int i;
3495
3496         /* Return early if the firmware is already loaded / cached. */
3497         if (!IS_ERR(tp->fw))
3498                 goto out;
3499
3500         for (i = 0; i < ARRAY_SIZE(rtl_firmware_infos); i++) {
3501                 const struct rtl_firmware_info *info = rtl_firmware_infos + i;
3502
3503                 if (info->mac_version == tp->mac_version) {
3504                         const char *name = info->fw_name;
3505                         int rc;
3506
3507                         rc = request_firmware(&tp->fw, name, &tp->pci_dev->dev);
3508                         if (rc < 0) {
3509                                 netif_warn(tp, ifup, tp->dev, "unable to load "
3510                                         "firmware patch %s (%d)\n", name, rc);
3511                                 goto out_disable_request_firmware;
3512                         }
3513                         goto out;
3514                 }
3515         }
3516
3517 out_disable_request_firmware:
3518         tp->fw = NULL;
3519 out:
3520         return;
3521 }
3522
3523 static int rtl8169_open(struct net_device *dev)
3524 {
3525         struct rtl8169_private *tp = netdev_priv(dev);
3526         void __iomem *ioaddr = tp->mmio_addr;
3527         struct pci_dev *pdev = tp->pci_dev;
3528         int retval = -ENOMEM;
3529
3530         pm_runtime_get_sync(&pdev->dev);
3531
3532         /*
3533          * Rx and Tx desscriptors needs 256 bytes alignment.
3534          * dma_alloc_coherent provides more.
3535          */
3536         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3537                                              &tp->TxPhyAddr, GFP_KERNEL);
3538         if (!tp->TxDescArray)
3539                 goto err_pm_runtime_put;
3540
3541         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3542                                              &tp->RxPhyAddr, GFP_KERNEL);
3543         if (!tp->RxDescArray)
3544                 goto err_free_tx_0;
3545
3546         retval = rtl8169_init_ring(dev);
3547         if (retval < 0)
3548                 goto err_free_rx_1;
3549
3550         INIT_DELAYED_WORK(&tp->task, NULL);
3551
3552         smp_mb();
3553
3554         rtl_request_firmware(tp);
3555
3556         retval = request_irq(dev->irq, rtl8169_interrupt,
3557                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3558                              dev->name, dev);
3559         if (retval < 0)
3560                 goto err_release_fw_2;
3561
3562         napi_enable(&tp->napi);
3563
3564         rtl8169_init_phy(dev, tp);
3565
3566         rtl8169_set_features(dev, dev->features);
3567
3568         rtl_pll_power_up(tp);
3569
3570         rtl_hw_start(dev);
3571
3572         tp->saved_wolopts = 0;
3573         pm_runtime_put_noidle(&pdev->dev);
3574
3575         rtl8169_check_link_status(dev, tp, ioaddr);
3576 out:
3577         return retval;
3578
3579 err_release_fw_2:
3580         rtl_release_firmware(tp);
3581         rtl8169_rx_clear(tp);
3582 err_free_rx_1:
3583         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3584                           tp->RxPhyAddr);
3585         tp->RxDescArray = NULL;
3586 err_free_tx_0:
3587         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3588                           tp->TxPhyAddr);
3589         tp->TxDescArray = NULL;
3590 err_pm_runtime_put:
3591         pm_runtime_put_noidle(&pdev->dev);
3592         goto out;
3593 }
3594
3595 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3596 {
3597         void __iomem *ioaddr = tp->mmio_addr;
3598
3599         /* Disable interrupts */
3600         rtl8169_irq_mask_and_ack(ioaddr);
3601
3602         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3603             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3604             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3605                 while (RTL_R8(TxPoll) & NPQ)
3606                         udelay(20);
3607
3608         }
3609
3610         /* Reset the chipset */
3611         RTL_W8(ChipCmd, CmdReset);
3612
3613         /* PCI commit */
3614         RTL_R8(ChipCmd);
3615 }
3616
3617 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3618 {
3619         void __iomem *ioaddr = tp->mmio_addr;
3620         u32 cfg = rtl8169_rx_config;
3621
3622         cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
3623         RTL_W32(RxConfig, cfg);
3624
3625         /* Set DMA burst size and Interframe Gap Time */
3626         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3627                 (InterFrameGap << TxInterFrameGapShift));
3628 }
3629
3630 static void rtl_hw_start(struct net_device *dev)
3631 {
3632         struct rtl8169_private *tp = netdev_priv(dev);
3633
3634         rtl_hw_reset(tp);
3635
3636         tp->hw_start(dev);
3637
3638         netif_start_queue(dev);
3639 }
3640
3641 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3642                                          void __iomem *ioaddr)
3643 {
3644         /*
3645          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3646          * register to be written before TxDescAddrLow to work.
3647          * Switching from MMIO to I/O access fixes the issue as well.
3648          */
3649         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3650         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3651         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3652         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3653 }
3654
3655 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3656 {
3657         u16 cmd;
3658
3659         cmd = RTL_R16(CPlusCmd);
3660         RTL_W16(CPlusCmd, cmd);
3661         return cmd;
3662 }
3663
3664 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3665 {
3666         /* Low hurts. Let's disable the filtering. */
3667         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3668 }
3669
3670 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3671 {
3672         static const struct {
3673                 u32 mac_version;
3674                 u32 clk;
3675                 u32 val;
3676         } cfg2_info [] = {
3677                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3678                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3679                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3680                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3681         }, *p = cfg2_info;
3682         unsigned int i;
3683         u32 clk;
3684
3685         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3686         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3687                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3688                         RTL_W32(0x7c, p->val);
3689                         break;
3690                 }
3691         }
3692 }
3693
3694 static void rtl_hw_start_8169(struct net_device *dev)
3695 {
3696         struct rtl8169_private *tp = netdev_priv(dev);
3697         void __iomem *ioaddr = tp->mmio_addr;
3698         struct pci_dev *pdev = tp->pci_dev;
3699
3700         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3701                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3702                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3703         }
3704
3705         RTL_W8(Cfg9346, Cfg9346_Unlock);
3706         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3707             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3708             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3709             tp->mac_version == RTL_GIGA_MAC_VER_04)
3710                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3711
3712         RTL_W8(EarlyTxThres, NoEarlyTx);
3713
3714         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3715
3716         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3717             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3718             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3719             tp->mac_version == RTL_GIGA_MAC_VER_04)
3720                 rtl_set_rx_tx_config_registers(tp);
3721
3722         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3723
3724         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3725             tp->mac_version == RTL_GIGA_MAC_VER_03) {
3726                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3727                         "Bit-3 and bit-14 MUST be 1\n");
3728                 tp->cp_cmd |= (1 << 14);
3729         }
3730
3731         RTL_W16(CPlusCmd, tp->cp_cmd);
3732
3733         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3734
3735         /*
3736          * Undocumented corner. Supposedly:
3737          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3738          */
3739         RTL_W16(IntrMitigate, 0x0000);
3740
3741         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3742
3743         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3744             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3745             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3746             tp->mac_version != RTL_GIGA_MAC_VER_04) {
3747                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3748                 rtl_set_rx_tx_config_registers(tp);
3749         }
3750
3751         RTL_W8(Cfg9346, Cfg9346_Lock);
3752
3753         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3754         RTL_R8(IntrMask);
3755
3756         RTL_W32(RxMissed, 0);
3757
3758         rtl_set_rx_mode(dev);
3759
3760         /* no early-rx interrupts */
3761         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3762
3763         /* Enable all known interrupts by setting the interrupt mask. */
3764         RTL_W16(IntrMask, tp->intr_event);
3765 }
3766
3767 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3768 {
3769         struct net_device *dev = pci_get_drvdata(pdev);
3770         struct rtl8169_private *tp = netdev_priv(dev);
3771         int cap = tp->pcie_cap;
3772
3773         if (cap) {
3774                 u16 ctl;
3775
3776                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3777                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3778                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3779         }
3780 }
3781
3782 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3783 {
3784         u32 csi;
3785
3786         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3787         rtl_csi_write(ioaddr, 0x070c, csi | bits);
3788 }
3789
3790 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3791 {
3792         rtl_csi_access_enable(ioaddr, 0x17000000);
3793 }
3794
3795 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3796 {
3797         rtl_csi_access_enable(ioaddr, 0x27000000);
3798 }
3799
3800 struct ephy_info {
3801         unsigned int offset;
3802         u16 mask;
3803         u16 bits;
3804 };
3805
3806 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3807 {
3808         u16 w;
3809
3810         while (len-- > 0) {
3811                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3812                 rtl_ephy_write(ioaddr, e->offset, w);
3813                 e++;
3814         }
3815 }
3816
3817 static void rtl_disable_clock_request(struct pci_dev *pdev)
3818 {
3819         struct net_device *dev = pci_get_drvdata(pdev);
3820         struct rtl8169_private *tp = netdev_priv(dev);
3821         int cap = tp->pcie_cap;
3822
3823         if (cap) {
3824                 u16 ctl;
3825
3826                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3827                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3828                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3829         }
3830 }
3831
3832 static void rtl_enable_clock_request(struct pci_dev *pdev)
3833 {
3834         struct net_device *dev = pci_get_drvdata(pdev);
3835         struct rtl8169_private *tp = netdev_priv(dev);
3836         int cap = tp->pcie_cap;
3837
3838         if (cap) {
3839                 u16 ctl;
3840
3841                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3842                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3843                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3844         }
3845 }
3846
3847 #define R8168_CPCMD_QUIRK_MASK (\
3848         EnableBist | \
3849         Mac_dbgo_oe | \
3850         Force_half_dup | \
3851         Force_rxflow_en | \
3852         Force_txflow_en | \
3853         Cxpl_dbg_sel | \
3854         ASF | \
3855         PktCntrDisable | \
3856         Mac_dbgo_sel)
3857
3858 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3859 {
3860         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3861
3862         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3863
3864         rtl_tx_performance_tweak(pdev,
3865                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3866 }
3867
3868 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3869 {
3870         rtl_hw_start_8168bb(ioaddr, pdev);
3871
3872         RTL_W8(MaxTxPacketSize, TxPacketMax);
3873
3874         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3875 }
3876
3877 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3878 {
3879         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3880
3881         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3882
3883         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3884
3885         rtl_disable_clock_request(pdev);
3886
3887         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3888 }
3889
3890 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3891 {
3892         static const struct ephy_info e_info_8168cp[] = {
3893                 { 0x01, 0,      0x0001 },
3894                 { 0x02, 0x0800, 0x1000 },
3895                 { 0x03, 0,      0x0042 },
3896                 { 0x06, 0x0080, 0x0000 },
3897                 { 0x07, 0,      0x2000 }
3898         };
3899
3900         rtl_csi_access_enable_2(ioaddr);
3901
3902         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3903
3904         __rtl_hw_start_8168cp(ioaddr, pdev);
3905 }
3906
3907 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3908 {
3909         rtl_csi_access_enable_2(ioaddr);
3910
3911         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3912
3913         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3914
3915         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3916 }
3917
3918 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3919 {
3920         rtl_csi_access_enable_2(ioaddr);
3921
3922         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3923
3924         /* Magic. */
3925         RTL_W8(DBG_REG, 0x20);
3926
3927         RTL_W8(MaxTxPacketSize, TxPacketMax);
3928
3929         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3930
3931         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3932 }
3933
3934 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3935 {
3936         static const struct ephy_info e_info_8168c_1[] = {
3937                 { 0x02, 0x0800, 0x1000 },
3938                 { 0x03, 0,      0x0002 },
3939                 { 0x06, 0x0080, 0x0000 }
3940         };
3941
3942         rtl_csi_access_enable_2(ioaddr);
3943
3944         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3945
3946         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3947
3948         __rtl_hw_start_8168cp(ioaddr, pdev);
3949 }
3950
3951 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3952 {
3953         static const struct ephy_info e_info_8168c_2[] = {
3954                 { 0x01, 0,      0x0001 },
3955                 { 0x03, 0x0400, 0x0220 }
3956         };
3957
3958         rtl_csi_access_enable_2(ioaddr);
3959
3960         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3961
3962         __rtl_hw_start_8168cp(ioaddr, pdev);
3963 }
3964
3965 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3966 {
3967         rtl_hw_start_8168c_2(ioaddr, pdev);
3968 }
3969
3970 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3971 {
3972         rtl_csi_access_enable_2(ioaddr);
3973
3974         __rtl_hw_start_8168cp(ioaddr, pdev);
3975 }
3976
3977 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3978 {
3979         rtl_csi_access_enable_2(ioaddr);
3980
3981         rtl_disable_clock_request(pdev);
3982
3983         RTL_W8(MaxTxPacketSize, TxPacketMax);
3984
3985         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3986
3987         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3988 }
3989
3990 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
3991 {
3992         rtl_csi_access_enable_1(ioaddr);
3993
3994         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3995
3996         RTL_W8(MaxTxPacketSize, TxPacketMax);
3997
3998         rtl_disable_clock_request(pdev);
3999 }
4000
4001 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4002 {
4003         static const struct ephy_info e_info_8168d_4[] = {
4004                 { 0x0b, ~0,     0x48 },
4005                 { 0x19, 0x20,   0x50 },
4006                 { 0x0c, ~0,     0x20 }
4007         };
4008         int i;
4009
4010         rtl_csi_access_enable_1(ioaddr);
4011
4012         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4013
4014         RTL_W8(MaxTxPacketSize, TxPacketMax);
4015
4016         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4017                 const struct ephy_info *e = e_info_8168d_4 + i;
4018                 u16 w;
4019
4020                 w = rtl_ephy_read(ioaddr, e->offset);
4021                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4022         }
4023
4024         rtl_enable_clock_request(pdev);
4025 }
4026
4027 static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4028 {
4029         static const struct ephy_info e_info_8168e[] = {
4030                 { 0x00, 0x0200, 0x0100 },
4031                 { 0x00, 0x0000, 0x0004 },
4032                 { 0x06, 0x0002, 0x0001 },
4033                 { 0x06, 0x0000, 0x0030 },
4034                 { 0x07, 0x0000, 0x2000 },
4035                 { 0x00, 0x0000, 0x0020 },
4036                 { 0x03, 0x5800, 0x2000 },
4037                 { 0x03, 0x0000, 0x0001 },
4038                 { 0x01, 0x0800, 0x1000 },
4039                 { 0x07, 0x0000, 0x4000 },
4040                 { 0x1e, 0x0000, 0x2000 },
4041                 { 0x19, 0xffff, 0xfe6c },
4042                 { 0x0a, 0x0000, 0x0040 }
4043         };
4044
4045         rtl_csi_access_enable_2(ioaddr);
4046
4047         rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4048
4049         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4050
4051         RTL_W8(MaxTxPacketSize, TxPacketMax);
4052
4053         rtl_disable_clock_request(pdev);
4054
4055         /* Reset tx FIFO pointer */
4056         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4057         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4058
4059         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4060 }
4061
4062 static void rtl_hw_start_8168(struct net_device *dev)
4063 {
4064         struct rtl8169_private *tp = netdev_priv(dev);
4065         void __iomem *ioaddr = tp->mmio_addr;
4066         struct pci_dev *pdev = tp->pci_dev;
4067
4068         RTL_W8(Cfg9346, Cfg9346_Unlock);
4069
4070         RTL_W8(MaxTxPacketSize, TxPacketMax);
4071
4072         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4073
4074         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4075
4076         RTL_W16(CPlusCmd, tp->cp_cmd);
4077
4078         RTL_W16(IntrMitigate, 0x5151);
4079
4080         /* Work around for RxFIFO overflow. */
4081         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4082             tp->mac_version == RTL_GIGA_MAC_VER_22) {
4083                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4084                 tp->intr_event &= ~RxOverflow;
4085         }
4086
4087         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4088
4089         rtl_set_rx_mode(dev);
4090
4091         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4092                 (InterFrameGap << TxInterFrameGapShift));
4093
4094         RTL_R8(IntrMask);
4095
4096         switch (tp->mac_version) {
4097         case RTL_GIGA_MAC_VER_11:
4098                 rtl_hw_start_8168bb(ioaddr, pdev);
4099                 break;
4100
4101         case RTL_GIGA_MAC_VER_12:
4102         case RTL_GIGA_MAC_VER_17:
4103                 rtl_hw_start_8168bef(ioaddr, pdev);
4104                 break;
4105
4106         case RTL_GIGA_MAC_VER_18:
4107                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4108                 break;
4109
4110         case RTL_GIGA_MAC_VER_19:
4111                 rtl_hw_start_8168c_1(ioaddr, pdev);
4112                 break;
4113
4114         case RTL_GIGA_MAC_VER_20:
4115                 rtl_hw_start_8168c_2(ioaddr, pdev);
4116                 break;
4117
4118         case RTL_GIGA_MAC_VER_21:
4119                 rtl_hw_start_8168c_3(ioaddr, pdev);
4120                 break;
4121
4122         case RTL_GIGA_MAC_VER_22:
4123                 rtl_hw_start_8168c_4(ioaddr, pdev);
4124                 break;
4125
4126         case RTL_GIGA_MAC_VER_23:
4127                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4128                 break;
4129
4130         case RTL_GIGA_MAC_VER_24:
4131                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4132                 break;
4133
4134         case RTL_GIGA_MAC_VER_25:
4135         case RTL_GIGA_MAC_VER_26:
4136         case RTL_GIGA_MAC_VER_27:
4137                 rtl_hw_start_8168d(ioaddr, pdev);
4138                 break;
4139
4140         case RTL_GIGA_MAC_VER_28:
4141                 rtl_hw_start_8168d_4(ioaddr, pdev);
4142                 break;
4143
4144         case RTL_GIGA_MAC_VER_31:
4145                 rtl_hw_start_8168dp(ioaddr, pdev);
4146                 break;
4147
4148         case RTL_GIGA_MAC_VER_32:
4149         case RTL_GIGA_MAC_VER_33:
4150                 rtl_hw_start_8168e(ioaddr, pdev);
4151                 break;
4152
4153         default:
4154                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4155                         dev->name, tp->mac_version);
4156                 break;
4157         }
4158
4159         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4160
4161         RTL_W8(Cfg9346, Cfg9346_Lock);
4162
4163         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4164
4165         RTL_W16(IntrMask, tp->intr_event);
4166 }
4167
4168 #define R810X_CPCMD_QUIRK_MASK (\
4169         EnableBist | \
4170         Mac_dbgo_oe | \
4171         Force_half_dup | \
4172         Force_rxflow_en | \
4173         Force_txflow_en | \
4174         Cxpl_dbg_sel | \
4175         ASF | \
4176         PktCntrDisable | \
4177         Mac_dbgo_sel)
4178
4179 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4180 {
4181         static const struct ephy_info e_info_8102e_1[] = {
4182                 { 0x01, 0, 0x6e65 },
4183                 { 0x02, 0, 0x091f },
4184                 { 0x03, 0, 0xc2f9 },
4185                 { 0x06, 0, 0xafb5 },
4186                 { 0x07, 0, 0x0e00 },
4187                 { 0x19, 0, 0xec80 },
4188                 { 0x01, 0, 0x2e65 },
4189                 { 0x01, 0, 0x6e65 }
4190         };
4191         u8 cfg1;
4192
4193         rtl_csi_access_enable_2(ioaddr);
4194
4195         RTL_W8(DBG_REG, FIX_NAK_1);
4196
4197         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4198
4199         RTL_W8(Config1,
4200                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4201         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4202
4203         cfg1 = RTL_R8(Config1);
4204         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4205                 RTL_W8(Config1, cfg1 & ~LEDS0);
4206
4207         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4208 }
4209
4210 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4211 {
4212         rtl_csi_access_enable_2(ioaddr);
4213
4214         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4215
4216         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4217         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4218 }
4219
4220 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4221 {
4222         rtl_hw_start_8102e_2(ioaddr, pdev);
4223
4224         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4225 }
4226
4227 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4228 {
4229         static const struct ephy_info e_info_8105e_1[] = {
4230                 { 0x07, 0, 0x4000 },
4231                 { 0x19, 0, 0x0200 },
4232                 { 0x19, 0, 0x0020 },
4233                 { 0x1e, 0, 0x2000 },
4234                 { 0x03, 0, 0x0001 },
4235                 { 0x19, 0, 0x0100 },
4236                 { 0x19, 0, 0x0004 },
4237                 { 0x0a, 0, 0x0020 }
4238         };
4239
4240         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4241         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4242
4243         /* Disable Early Tally Counter */
4244         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4245
4246         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4247         RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4248
4249         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4250 }
4251
4252 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4253 {
4254         rtl_hw_start_8105e_1(ioaddr, pdev);
4255         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4256 }
4257
4258 static void rtl_hw_start_8101(struct net_device *dev)
4259 {
4260         struct rtl8169_private *tp = netdev_priv(dev);
4261         void __iomem *ioaddr = tp->mmio_addr;
4262         struct pci_dev *pdev = tp->pci_dev;
4263
4264         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4265             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4266                 int cap = tp->pcie_cap;
4267
4268                 if (cap) {
4269                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4270                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4271                 }
4272         }
4273
4274         RTL_W8(Cfg9346, Cfg9346_Unlock);
4275
4276         switch (tp->mac_version) {
4277         case RTL_GIGA_MAC_VER_07:
4278                 rtl_hw_start_8102e_1(ioaddr, pdev);
4279                 break;
4280
4281         case RTL_GIGA_MAC_VER_08:
4282                 rtl_hw_start_8102e_3(ioaddr, pdev);
4283                 break;
4284
4285         case RTL_GIGA_MAC_VER_09:
4286                 rtl_hw_start_8102e_2(ioaddr, pdev);
4287                 break;
4288
4289         case RTL_GIGA_MAC_VER_29:
4290                 rtl_hw_start_8105e_1(ioaddr, pdev);
4291                 break;
4292         case RTL_GIGA_MAC_VER_30:
4293                 rtl_hw_start_8105e_2(ioaddr, pdev);
4294                 break;
4295         }
4296
4297         RTL_W8(Cfg9346, Cfg9346_Lock);
4298
4299         RTL_W8(MaxTxPacketSize, TxPacketMax);
4300
4301         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4302
4303         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4304         RTL_W16(CPlusCmd, tp->cp_cmd);
4305
4306         RTL_W16(IntrMitigate, 0x0000);
4307
4308         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4309
4310         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4311         rtl_set_rx_tx_config_registers(tp);
4312
4313         RTL_R8(IntrMask);
4314
4315         rtl_set_rx_mode(dev);
4316
4317         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4318
4319         RTL_W16(IntrMask, tp->intr_event);
4320 }
4321
4322 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4323 {
4324         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4325                 return -EINVAL;
4326
4327         dev->mtu = new_mtu;
4328         netdev_update_features(dev);
4329
4330         return 0;
4331 }
4332
4333 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4334 {
4335         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4336         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4337 }
4338
4339 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4340                                      void **data_buff, struct RxDesc *desc)
4341 {
4342         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4343                          DMA_FROM_DEVICE);
4344
4345         kfree(*data_buff);
4346         *data_buff = NULL;
4347         rtl8169_make_unusable_by_asic(desc);
4348 }
4349
4350 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4351 {
4352         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4353
4354         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4355 }
4356
4357 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4358                                        u32 rx_buf_sz)
4359 {
4360         desc->addr = cpu_to_le64(mapping);
4361         wmb();
4362         rtl8169_mark_to_asic(desc, rx_buf_sz);
4363 }
4364
4365 static inline void *rtl8169_align(void *data)
4366 {
4367         return (void *)ALIGN((long)data, 16);
4368 }
4369
4370 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4371                                              struct RxDesc *desc)
4372 {
4373         void *data;
4374         dma_addr_t mapping;
4375         struct device *d = &tp->pci_dev->dev;
4376         struct net_device *dev = tp->dev;
4377         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4378
4379         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4380         if (!data)
4381                 return NULL;
4382
4383         if (rtl8169_align(data) != data) {
4384                 kfree(data);
4385                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4386                 if (!data)
4387                         return NULL;
4388         }
4389
4390         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4391                                  DMA_FROM_DEVICE);
4392         if (unlikely(dma_mapping_error(d, mapping))) {
4393                 if (net_ratelimit())
4394                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4395                 goto err_out;
4396         }
4397
4398         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4399         return data;
4400
4401 err_out:
4402         kfree(data);
4403         return NULL;
4404 }
4405
4406 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4407 {
4408         unsigned int i;
4409
4410         for (i = 0; i < NUM_RX_DESC; i++) {
4411                 if (tp->Rx_databuff[i]) {
4412                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4413                                             tp->RxDescArray + i);
4414                 }
4415         }
4416 }
4417
4418 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4419 {
4420         desc->opts1 |= cpu_to_le32(RingEnd);
4421 }
4422
4423 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4424 {
4425         unsigned int i;
4426
4427         for (i = 0; i < NUM_RX_DESC; i++) {
4428                 void *data;
4429
4430                 if (tp->Rx_databuff[i])
4431                         continue;
4432
4433                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4434                 if (!data) {
4435                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4436                         goto err_out;
4437                 }
4438                 tp->Rx_databuff[i] = data;
4439         }
4440
4441         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4442         return 0;
4443
4444 err_out:
4445         rtl8169_rx_clear(tp);
4446         return -ENOMEM;
4447 }
4448
4449 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4450 {
4451         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4452 }
4453
4454 static int rtl8169_init_ring(struct net_device *dev)
4455 {
4456         struct rtl8169_private *tp = netdev_priv(dev);
4457
4458         rtl8169_init_ring_indexes(tp);
4459
4460         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4461         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4462
4463         return rtl8169_rx_fill(tp);
4464 }
4465
4466 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4467                                  struct TxDesc *desc)
4468 {
4469         unsigned int len = tx_skb->len;
4470
4471         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4472
4473         desc->opts1 = 0x00;
4474         desc->opts2 = 0x00;
4475         desc->addr = 0x00;
4476         tx_skb->len = 0;
4477 }
4478
4479 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4480                                    unsigned int n)
4481 {
4482         unsigned int i;
4483
4484         for (i = 0; i < n; i++) {
4485                 unsigned int entry = (start + i) % NUM_TX_DESC;
4486                 struct ring_info *tx_skb = tp->tx_skb + entry;
4487                 unsigned int len = tx_skb->len;
4488
4489                 if (len) {
4490                         struct sk_buff *skb = tx_skb->skb;
4491
4492                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4493                                              tp->TxDescArray + entry);
4494                         if (skb) {
4495                                 tp->dev->stats.tx_dropped++;
4496                                 dev_kfree_skb(skb);
4497                                 tx_skb->skb = NULL;
4498                         }
4499                 }
4500         }
4501 }
4502
4503 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4504 {
4505         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4506         tp->cur_tx = tp->dirty_tx = 0;
4507 }
4508
4509 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4510 {
4511         struct rtl8169_private *tp = netdev_priv(dev);
4512
4513         PREPARE_DELAYED_WORK(&tp->task, task);
4514         schedule_delayed_work(&tp->task, 4);
4515 }
4516
4517 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4518 {
4519         struct rtl8169_private *tp = netdev_priv(dev);
4520         void __iomem *ioaddr = tp->mmio_addr;
4521
4522         synchronize_irq(dev->irq);
4523
4524         /* Wait for any pending NAPI task to complete */
4525         napi_disable(&tp->napi);
4526
4527         rtl8169_irq_mask_and_ack(ioaddr);
4528
4529         tp->intr_mask = 0xffff;
4530         RTL_W16(IntrMask, tp->intr_event);
4531         napi_enable(&tp->napi);
4532 }
4533
4534 static void rtl8169_reinit_task(struct work_struct *work)
4535 {
4536         struct rtl8169_private *tp =
4537                 container_of(work, struct rtl8169_private, task.work);
4538         struct net_device *dev = tp->dev;
4539         int ret;
4540
4541         rtnl_lock();
4542
4543         if (!netif_running(dev))
4544                 goto out_unlock;
4545
4546         rtl8169_wait_for_quiescence(dev);
4547         rtl8169_close(dev);
4548
4549         ret = rtl8169_open(dev);
4550         if (unlikely(ret < 0)) {
4551                 if (net_ratelimit())
4552                         netif_err(tp, drv, dev,
4553                                   "reinit failure (status = %d). Rescheduling\n",
4554                                   ret);
4555                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4556         }
4557
4558 out_unlock:
4559         rtnl_unlock();
4560 }
4561
4562 static void rtl8169_reset_task(struct work_struct *work)
4563 {
4564         struct rtl8169_private *tp =
4565                 container_of(work, struct rtl8169_private, task.work);
4566         struct net_device *dev = tp->dev;
4567
4568         rtnl_lock();
4569
4570         if (!netif_running(dev))
4571                 goto out_unlock;
4572
4573         rtl8169_wait_for_quiescence(dev);
4574
4575         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4576         rtl8169_tx_clear(tp);
4577
4578         if (tp->dirty_rx == tp->cur_rx) {
4579                 rtl8169_init_ring_indexes(tp);
4580                 rtl_hw_start(dev);
4581                 netif_wake_queue(dev);
4582                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4583         } else {
4584                 if (net_ratelimit())
4585                         netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4586                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4587         }
4588
4589 out_unlock:
4590         rtnl_unlock();
4591 }
4592
4593 static void rtl8169_tx_timeout(struct net_device *dev)
4594 {
4595         struct rtl8169_private *tp = netdev_priv(dev);
4596
4597         rtl8169_hw_reset(tp);
4598
4599         /* Let's wait a bit while any (async) irq lands on */
4600         rtl8169_schedule_work(dev, rtl8169_reset_task);
4601 }
4602
4603 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4604                               u32 *opts)
4605 {
4606         struct skb_shared_info *info = skb_shinfo(skb);
4607         unsigned int cur_frag, entry;
4608         struct TxDesc * uninitialized_var(txd);
4609         struct device *d = &tp->pci_dev->dev;
4610
4611         entry = tp->cur_tx;
4612         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4613                 skb_frag_t *frag = info->frags + cur_frag;
4614                 dma_addr_t mapping;
4615                 u32 status, len;
4616                 void *addr;
4617
4618                 entry = (entry + 1) % NUM_TX_DESC;
4619
4620                 txd = tp->TxDescArray + entry;
4621                 len = frag->size;
4622                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4623                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4624                 if (unlikely(dma_mapping_error(d, mapping))) {
4625                         if (net_ratelimit())
4626                                 netif_err(tp, drv, tp->dev,
4627                                           "Failed to map TX fragments DMA!\n");
4628                         goto err_out;
4629                 }
4630
4631                 /* Anti gcc 2.95.3 bugware (sic) */
4632                 status = opts[0] | len |
4633                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
4634
4635                 txd->opts1 = cpu_to_le32(status);
4636                 txd->opts2 = cpu_to_le32(opts[1]);
4637                 txd->addr = cpu_to_le64(mapping);
4638
4639                 tp->tx_skb[entry].len = len;
4640         }
4641
4642         if (cur_frag) {
4643                 tp->tx_skb[entry].skb = skb;
4644                 txd->opts1 |= cpu_to_le32(LastFrag);
4645         }
4646
4647         return cur_frag;
4648
4649 err_out:
4650         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4651         return -EIO;
4652 }
4653
4654 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4655                                     struct sk_buff *skb, u32 *opts)
4656 {
4657         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
4658         u32 mss = skb_shinfo(skb)->gso_size;
4659         int offset = info->opts_offset;
4660
4661         if (mss) {
4662                 opts[0] |= TD_LSO;
4663                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4664         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4665                 const struct iphdr *ip = ip_hdr(skb);
4666
4667                 if (ip->protocol == IPPROTO_TCP)
4668                         opts[offset] |= info->checksum.tcp;
4669                 else if (ip->protocol == IPPROTO_UDP)
4670                         opts[offset] |= info->checksum.udp;
4671                 else
4672                         WARN_ON_ONCE(1);
4673         }
4674 }
4675
4676 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4677                                       struct net_device *dev)
4678 {
4679         struct rtl8169_private *tp = netdev_priv(dev);
4680         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4681         struct TxDesc *txd = tp->TxDescArray + entry;
4682         void __iomem *ioaddr = tp->mmio_addr;
4683         struct device *d = &tp->pci_dev->dev;
4684         dma_addr_t mapping;
4685         u32 status, len;
4686         u32 opts[2];
4687         int frags;
4688
4689         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4690                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4691                 goto err_stop_0;
4692         }
4693
4694         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4695                 goto err_stop_0;
4696
4697         len = skb_headlen(skb);
4698         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4699         if (unlikely(dma_mapping_error(d, mapping))) {
4700                 if (net_ratelimit())
4701                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4702                 goto err_dma_0;
4703         }
4704
4705         tp->tx_skb[entry].len = len;
4706         txd->addr = cpu_to_le64(mapping);
4707
4708         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4709         opts[0] = DescOwn;
4710
4711         rtl8169_tso_csum(tp, skb, opts);
4712
4713         frags = rtl8169_xmit_frags(tp, skb, opts);
4714         if (frags < 0)
4715                 goto err_dma_1;
4716         else if (frags)
4717                 opts[0] |= FirstFrag;
4718         else {
4719                 opts[0] |= FirstFrag | LastFrag;
4720                 tp->tx_skb[entry].skb = skb;
4721         }
4722
4723         txd->opts2 = cpu_to_le32(opts[1]);
4724
4725         wmb();
4726
4727         /* Anti gcc 2.95.3 bugware (sic) */
4728         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4729         txd->opts1 = cpu_to_le32(status);
4730
4731         tp->cur_tx += frags + 1;
4732
4733         wmb();
4734
4735         RTL_W8(TxPoll, NPQ);
4736
4737         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4738                 netif_stop_queue(dev);
4739                 smp_rmb();
4740                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4741                         netif_wake_queue(dev);
4742         }
4743
4744         return NETDEV_TX_OK;
4745
4746 err_dma_1:
4747         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4748 err_dma_0:
4749         dev_kfree_skb(skb);
4750         dev->stats.tx_dropped++;
4751         return NETDEV_TX_OK;
4752
4753 err_stop_0:
4754         netif_stop_queue(dev);
4755         dev->stats.tx_dropped++;
4756         return NETDEV_TX_BUSY;
4757 }
4758
4759 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4760 {
4761         struct rtl8169_private *tp = netdev_priv(dev);
4762         struct pci_dev *pdev = tp->pci_dev;
4763         u16 pci_status, pci_cmd;
4764
4765         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4766         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4767
4768         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4769                   pci_cmd, pci_status);
4770
4771         /*
4772          * The recovery sequence below admits a very elaborated explanation:
4773          * - it seems to work;
4774          * - I did not see what else could be done;
4775          * - it makes iop3xx happy.
4776          *
4777          * Feel free to adjust to your needs.
4778          */
4779         if (pdev->broken_parity_status)
4780                 pci_cmd &= ~PCI_COMMAND_PARITY;
4781         else
4782                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4783
4784         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4785
4786         pci_write_config_word(pdev, PCI_STATUS,
4787                 pci_status & (PCI_STATUS_DETECTED_PARITY |
4788                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4789                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4790
4791         /* The infamous DAC f*ckup only happens at boot time */
4792         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4793                 void __iomem *ioaddr = tp->mmio_addr;
4794
4795                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4796                 tp->cp_cmd &= ~PCIDAC;
4797                 RTL_W16(CPlusCmd, tp->cp_cmd);
4798                 dev->features &= ~NETIF_F_HIGHDMA;
4799         }
4800
4801         rtl8169_hw_reset(tp);
4802
4803         rtl8169_schedule_work(dev, rtl8169_reinit_task);
4804 }
4805
4806 static void rtl8169_tx_interrupt(struct net_device *dev,
4807                                  struct rtl8169_private *tp,
4808                                  void __iomem *ioaddr)
4809 {
4810         unsigned int dirty_tx, tx_left;
4811
4812         dirty_tx = tp->dirty_tx;
4813         smp_rmb();
4814         tx_left = tp->cur_tx - dirty_tx;
4815
4816         while (tx_left > 0) {
4817                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4818                 struct ring_info *tx_skb = tp->tx_skb + entry;
4819                 u32 status;
4820
4821                 rmb();
4822                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4823                 if (status & DescOwn)
4824                         break;
4825
4826                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4827                                      tp->TxDescArray + entry);
4828                 if (status & LastFrag) {
4829                         dev->stats.tx_packets++;
4830                         dev->stats.tx_bytes += tx_skb->skb->len;
4831                         dev_kfree_skb(tx_skb->skb);
4832                         tx_skb->skb = NULL;
4833                 }
4834                 dirty_tx++;
4835                 tx_left--;
4836         }
4837
4838         if (tp->dirty_tx != dirty_tx) {
4839                 tp->dirty_tx = dirty_tx;
4840                 smp_wmb();
4841                 if (netif_queue_stopped(dev) &&
4842                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4843                         netif_wake_queue(dev);
4844                 }
4845                 /*
4846                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4847                  * too close. Let's kick an extra TxPoll request when a burst
4848                  * of start_xmit activity is detected (if it is not detected,
4849                  * it is slow enough). -- FR
4850                  */
4851                 smp_rmb();
4852                 if (tp->cur_tx != dirty_tx)
4853                         RTL_W8(TxPoll, NPQ);
4854         }
4855 }
4856
4857 static inline int rtl8169_fragmented_frame(u32 status)
4858 {
4859         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4860 }
4861
4862 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4863 {
4864         u32 status = opts1 & RxProtoMask;
4865
4866         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4867             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4868                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4869         else
4870                 skb_checksum_none_assert(skb);
4871 }
4872
4873 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4874                                            struct rtl8169_private *tp,
4875                                            int pkt_size,
4876                                            dma_addr_t addr)
4877 {
4878         struct sk_buff *skb;
4879         struct device *d = &tp->pci_dev->dev;
4880
4881         data = rtl8169_align(data);
4882         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4883         prefetch(data);
4884         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4885         if (skb)
4886                 memcpy(skb->data, data, pkt_size);
4887         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4888
4889         return skb;
4890 }
4891
4892 /*
4893  * Warning : rtl8169_rx_interrupt() might be called :
4894  * 1) from NAPI (softirq) context
4895  *      (polling = 1 : we should call netif_receive_skb())
4896  * 2) from process context (rtl8169_reset_task())
4897  *      (polling = 0 : we must call netif_rx() instead)
4898  */
4899 static int rtl8169_rx_interrupt(struct net_device *dev,
4900                                 struct rtl8169_private *tp,
4901                                 void __iomem *ioaddr, u32 budget)
4902 {
4903         unsigned int cur_rx, rx_left;
4904         unsigned int count;
4905         int polling = (budget != ~(u32)0) ? 1 : 0;
4906
4907         cur_rx = tp->cur_rx;
4908         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4909         rx_left = min(rx_left, budget);
4910
4911         for (; rx_left > 0; rx_left--, cur_rx++) {
4912                 unsigned int entry = cur_rx % NUM_RX_DESC;
4913                 struct RxDesc *desc = tp->RxDescArray + entry;
4914                 u32 status;
4915
4916                 rmb();
4917                 status = le32_to_cpu(desc->opts1);
4918
4919                 if (status & DescOwn)
4920                         break;
4921                 if (unlikely(status & RxRES)) {
4922                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4923                                    status);
4924                         dev->stats.rx_errors++;
4925                         if (status & (RxRWT | RxRUNT))
4926                                 dev->stats.rx_length_errors++;
4927                         if (status & RxCRC)
4928                                 dev->stats.rx_crc_errors++;
4929                         if (status & RxFOVF) {
4930                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4931                                 dev->stats.rx_fifo_errors++;
4932                         }
4933                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4934                 } else {
4935                         struct sk_buff *skb;
4936                         dma_addr_t addr = le64_to_cpu(desc->addr);
4937                         int pkt_size = (status & 0x00001FFF) - 4;
4938
4939                         /*
4940                          * The driver does not support incoming fragmented
4941                          * frames. They are seen as a symptom of over-mtu
4942                          * sized frames.
4943                          */
4944                         if (unlikely(rtl8169_fragmented_frame(status))) {
4945                                 dev->stats.rx_dropped++;
4946                                 dev->stats.rx_length_errors++;
4947                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
4948                                 continue;
4949                         }
4950
4951                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4952                                                   tp, pkt_size, addr);
4953                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4954                         if (!skb) {
4955                                 dev->stats.rx_dropped++;
4956                                 continue;
4957                         }
4958
4959                         rtl8169_rx_csum(skb, status);
4960                         skb_put(skb, pkt_size);
4961                         skb->protocol = eth_type_trans(skb, dev);
4962
4963                         rtl8169_rx_vlan_tag(desc, skb);
4964
4965                         if (likely(polling))
4966                                 napi_gro_receive(&tp->napi, skb);
4967                         else
4968                                 netif_rx(skb);
4969
4970                         dev->stats.rx_bytes += pkt_size;
4971                         dev->stats.rx_packets++;
4972                 }
4973
4974                 /* Work around for AMD plateform. */
4975                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4976                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4977                         desc->opts2 = 0;
4978                         cur_rx++;
4979                 }
4980         }
4981
4982         count = cur_rx - tp->cur_rx;
4983         tp->cur_rx = cur_rx;
4984
4985         tp->dirty_rx += count;
4986
4987         return count;
4988 }
4989
4990 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4991 {
4992         struct net_device *dev = dev_instance;
4993         struct rtl8169_private *tp = netdev_priv(dev);
4994         void __iomem *ioaddr = tp->mmio_addr;
4995         int handled = 0;
4996         int status;
4997
4998         /* loop handling interrupts until we have no new ones or
4999          * we hit a invalid/hotplug case.
5000          */
5001         status = RTL_R16(IntrStatus);
5002         while (status && status != 0xffff) {
5003                 handled = 1;
5004
5005                 /* Handle all of the error cases first. These will reset
5006                  * the chip, so just exit the loop.
5007                  */
5008                 if (unlikely(!netif_running(dev))) {
5009                         rtl8169_asic_down(ioaddr);
5010                         break;
5011                 }
5012
5013                 if (unlikely(status & RxFIFOOver)) {
5014                         switch (tp->mac_version) {
5015                         /* Work around for rx fifo overflow */
5016                         case RTL_GIGA_MAC_VER_11:
5017                         case RTL_GIGA_MAC_VER_22:
5018                         case RTL_GIGA_MAC_VER_26:
5019                                 netif_stop_queue(dev);
5020                                 rtl8169_tx_timeout(dev);
5021                                 goto done;
5022                         /* Testers needed. */
5023                         case RTL_GIGA_MAC_VER_17:
5024                         case RTL_GIGA_MAC_VER_19:
5025                         case RTL_GIGA_MAC_VER_20:
5026                         case RTL_GIGA_MAC_VER_21:
5027                         case RTL_GIGA_MAC_VER_23:
5028                         case RTL_GIGA_MAC_VER_24:
5029                         case RTL_GIGA_MAC_VER_27:
5030                         case RTL_GIGA_MAC_VER_28:
5031                         case RTL_GIGA_MAC_VER_31:
5032                         /* Experimental science. Pktgen proof. */
5033                         case RTL_GIGA_MAC_VER_12:
5034                         case RTL_GIGA_MAC_VER_25:
5035                                 if (status == RxFIFOOver)
5036                                         goto done;
5037                                 break;
5038                         default:
5039                                 break;
5040                         }
5041                 }
5042
5043                 if (unlikely(status & SYSErr)) {
5044                         rtl8169_pcierr_interrupt(dev);
5045                         break;
5046                 }
5047
5048                 if (status & LinkChg)
5049                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5050
5051                 /* We need to see the lastest version of tp->intr_mask to
5052                  * avoid ignoring an MSI interrupt and having to wait for
5053                  * another event which may never come.
5054                  */
5055                 smp_rmb();
5056                 if (status & tp->intr_mask & tp->napi_event) {
5057                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5058                         tp->intr_mask = ~tp->napi_event;
5059
5060                         if (likely(napi_schedule_prep(&tp->napi)))
5061                                 __napi_schedule(&tp->napi);
5062                         else
5063                                 netif_info(tp, intr, dev,
5064                                            "interrupt %04x in poll\n", status);
5065                 }
5066
5067                 /* We only get a new MSI interrupt when all active irq
5068                  * sources on the chip have been acknowledged. So, ack
5069                  * everything we've seen and check if new sources have become
5070                  * active to avoid blocking all interrupts from the chip.
5071                  */
5072                 RTL_W16(IntrStatus,
5073                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5074                 status = RTL_R16(IntrStatus);
5075         }
5076 done:
5077         return IRQ_RETVAL(handled);
5078 }
5079
5080 static int rtl8169_poll(struct napi_struct *napi, int budget)
5081 {
5082         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5083         struct net_device *dev = tp->dev;
5084         void __iomem *ioaddr = tp->mmio_addr;
5085         int work_done;
5086
5087         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5088         rtl8169_tx_interrupt(dev, tp, ioaddr);
5089
5090         if (work_done < budget) {
5091                 napi_complete(napi);
5092
5093                 /* We need for force the visibility of tp->intr_mask
5094                  * for other CPUs, as we can loose an MSI interrupt
5095                  * and potentially wait for a retransmit timeout if we don't.
5096                  * The posted write to IntrMask is safe, as it will
5097                  * eventually make it to the chip and we won't loose anything
5098                  * until it does.
5099                  */
5100                 tp->intr_mask = 0xffff;
5101                 wmb();
5102                 RTL_W16(IntrMask, tp->intr_event);
5103         }
5104
5105         return work_done;
5106 }
5107
5108 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5109 {
5110         struct rtl8169_private *tp = netdev_priv(dev);
5111
5112         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5113                 return;
5114
5115         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5116         RTL_W32(RxMissed, 0);
5117 }
5118
5119 static void rtl8169_down(struct net_device *dev)
5120 {
5121         struct rtl8169_private *tp = netdev_priv(dev);
5122         void __iomem *ioaddr = tp->mmio_addr;
5123
5124         del_timer_sync(&tp->timer);
5125
5126         netif_stop_queue(dev);
5127
5128         napi_disable(&tp->napi);
5129
5130         spin_lock_irq(&tp->lock);
5131
5132         rtl8169_asic_down(ioaddr);
5133         /*
5134          * At this point device interrupts can not be enabled in any function,
5135          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5136          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5137          */
5138         rtl8169_rx_missed(dev, ioaddr);
5139
5140         spin_unlock_irq(&tp->lock);
5141
5142         synchronize_irq(dev->irq);
5143
5144         /* Give a racing hard_start_xmit a few cycles to complete. */
5145         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5146
5147         rtl8169_tx_clear(tp);
5148
5149         rtl8169_rx_clear(tp);
5150
5151         rtl_pll_power_down(tp);
5152 }
5153
5154 static int rtl8169_close(struct net_device *dev)
5155 {
5156         struct rtl8169_private *tp = netdev_priv(dev);
5157         struct pci_dev *pdev = tp->pci_dev;
5158
5159         pm_runtime_get_sync(&pdev->dev);
5160
5161         /* Update counters before going down */
5162         rtl8169_update_counters(dev);
5163
5164         rtl8169_down(dev);
5165
5166         free_irq(dev->irq, dev);
5167
5168         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5169                           tp->RxPhyAddr);
5170         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5171                           tp->TxPhyAddr);
5172         tp->TxDescArray = NULL;
5173         tp->RxDescArray = NULL;
5174
5175         pm_runtime_put_sync(&pdev->dev);
5176
5177         return 0;
5178 }
5179
5180 static void rtl_set_rx_mode(struct net_device *dev)
5181 {
5182         struct rtl8169_private *tp = netdev_priv(dev);
5183         void __iomem *ioaddr = tp->mmio_addr;
5184         unsigned long flags;
5185         u32 mc_filter[2];       /* Multicast hash filter */
5186         int rx_mode;
5187         u32 tmp = 0;
5188
5189         if (dev->flags & IFF_PROMISC) {
5190                 /* Unconditionally log net taps. */
5191                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5192                 rx_mode =
5193                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5194                     AcceptAllPhys;
5195                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5196         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5197                    (dev->flags & IFF_ALLMULTI)) {
5198                 /* Too many to filter perfectly -- accept all multicasts. */
5199                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5200                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5201         } else {
5202                 struct netdev_hw_addr *ha;
5203
5204                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5205                 mc_filter[1] = mc_filter[0] = 0;
5206                 netdev_for_each_mc_addr(ha, dev) {
5207                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5208                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5209                         rx_mode |= AcceptMulticast;
5210                 }
5211         }
5212
5213         spin_lock_irqsave(&tp->lock, flags);
5214
5215         tmp = rtl8169_rx_config | rx_mode |
5216               (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
5217
5218         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5219                 u32 data = mc_filter[0];
5220
5221                 mc_filter[0] = swab32(mc_filter[1]);
5222                 mc_filter[1] = swab32(data);
5223         }
5224
5225         RTL_W32(MAR0 + 4, mc_filter[1]);
5226         RTL_W32(MAR0 + 0, mc_filter[0]);
5227
5228         RTL_W32(RxConfig, tmp);
5229
5230         spin_unlock_irqrestore(&tp->lock, flags);
5231 }
5232
5233 /**
5234  *  rtl8169_get_stats - Get rtl8169 read/write statistics
5235  *  @dev: The Ethernet Device to get statistics for
5236  *
5237  *  Get TX/RX statistics for rtl8169
5238  */
5239 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5240 {
5241         struct rtl8169_private *tp = netdev_priv(dev);
5242         void __iomem *ioaddr = tp->mmio_addr;
5243         unsigned long flags;
5244
5245         if (netif_running(dev)) {
5246                 spin_lock_irqsave(&tp->lock, flags);
5247                 rtl8169_rx_missed(dev, ioaddr);
5248                 spin_unlock_irqrestore(&tp->lock, flags);
5249         }
5250
5251         return &dev->stats;
5252 }
5253
5254 static void rtl8169_net_suspend(struct net_device *dev)
5255 {
5256         struct rtl8169_private *tp = netdev_priv(dev);
5257
5258         if (!netif_running(dev))
5259                 return;
5260
5261         rtl_pll_power_down(tp);
5262
5263         netif_device_detach(dev);
5264         netif_stop_queue(dev);
5265 }
5266
5267 #ifdef CONFIG_PM
5268
5269 static int rtl8169_suspend(struct device *device)
5270 {
5271         struct pci_dev *pdev = to_pci_dev(device);
5272         struct net_device *dev = pci_get_drvdata(pdev);
5273
5274         rtl8169_net_suspend(dev);
5275
5276         return 0;
5277 }
5278
5279 static void __rtl8169_resume(struct net_device *dev)
5280 {
5281         struct rtl8169_private *tp = netdev_priv(dev);
5282
5283         netif_device_attach(dev);
5284
5285         rtl_pll_power_up(tp);
5286
5287         rtl8169_schedule_work(dev, rtl8169_reset_task);
5288 }
5289
5290 static int rtl8169_resume(struct device *device)
5291 {
5292         struct pci_dev *pdev = to_pci_dev(device);
5293         struct net_device *dev = pci_get_drvdata(pdev);
5294         struct rtl8169_private *tp = netdev_priv(dev);
5295
5296         rtl8169_init_phy(dev, tp);
5297
5298         if (netif_running(dev))
5299                 __rtl8169_resume(dev);
5300
5301         return 0;
5302 }
5303
5304 static int rtl8169_runtime_suspend(struct device *device)
5305 {
5306         struct pci_dev *pdev = to_pci_dev(device);
5307         struct net_device *dev = pci_get_drvdata(pdev);
5308         struct rtl8169_private *tp = netdev_priv(dev);
5309
5310         if (!tp->TxDescArray)
5311                 return 0;
5312
5313         spin_lock_irq(&tp->lock);
5314         tp->saved_wolopts = __rtl8169_get_wol(tp);
5315         __rtl8169_set_wol(tp, WAKE_ANY);
5316         spin_unlock_irq(&tp->lock);
5317
5318         rtl8169_net_suspend(dev);
5319
5320         return 0;
5321 }
5322
5323 static int rtl8169_runtime_resume(struct device *device)
5324 {
5325         struct pci_dev *pdev = to_pci_dev(device);
5326         struct net_device *dev = pci_get_drvdata(pdev);
5327         struct rtl8169_private *tp = netdev_priv(dev);
5328
5329         if (!tp->TxDescArray)
5330                 return 0;
5331
5332         spin_lock_irq(&tp->lock);
5333         __rtl8169_set_wol(tp, tp->saved_wolopts);
5334         tp->saved_wolopts = 0;
5335         spin_unlock_irq(&tp->lock);
5336
5337         rtl8169_init_phy(dev, tp);
5338
5339         __rtl8169_resume(dev);
5340
5341         return 0;
5342 }
5343
5344 static int rtl8169_runtime_idle(struct device *device)
5345 {
5346         struct pci_dev *pdev = to_pci_dev(device);
5347         struct net_device *dev = pci_get_drvdata(pdev);
5348         struct rtl8169_private *tp = netdev_priv(dev);
5349
5350         return tp->TxDescArray ? -EBUSY : 0;
5351 }
5352
5353 static const struct dev_pm_ops rtl8169_pm_ops = {
5354         .suspend                = rtl8169_suspend,
5355         .resume                 = rtl8169_resume,
5356         .freeze                 = rtl8169_suspend,
5357         .thaw                   = rtl8169_resume,
5358         .poweroff               = rtl8169_suspend,
5359         .restore                = rtl8169_resume,
5360         .runtime_suspend        = rtl8169_runtime_suspend,
5361         .runtime_resume         = rtl8169_runtime_resume,
5362         .runtime_idle           = rtl8169_runtime_idle,
5363 };
5364
5365 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5366
5367 #else /* !CONFIG_PM */
5368
5369 #define RTL8169_PM_OPS  NULL
5370
5371 #endif /* !CONFIG_PM */
5372
5373 static void rtl_shutdown(struct pci_dev *pdev)
5374 {
5375         struct net_device *dev = pci_get_drvdata(pdev);
5376         struct rtl8169_private *tp = netdev_priv(dev);
5377         void __iomem *ioaddr = tp->mmio_addr;
5378
5379         rtl8169_net_suspend(dev);
5380
5381         /* Restore original MAC address */
5382         rtl_rar_set(tp, dev->perm_addr);
5383
5384         spin_lock_irq(&tp->lock);
5385
5386         rtl8169_asic_down(ioaddr);
5387
5388         spin_unlock_irq(&tp->lock);
5389
5390         if (system_state == SYSTEM_POWER_OFF) {
5391                 /* WoL fails with some 8168 when the receiver is disabled. */
5392                 if (tp->features & RTL_FEATURE_WOL) {
5393                         pci_clear_master(pdev);
5394
5395                         RTL_W8(ChipCmd, CmdRxEnb);
5396                         /* PCI commit */
5397                         RTL_R8(ChipCmd);
5398                 }
5399
5400                 pci_wake_from_d3(pdev, true);
5401                 pci_set_power_state(pdev, PCI_D3hot);
5402         }
5403 }
5404
5405 static struct pci_driver rtl8169_pci_driver = {
5406         .name           = MODULENAME,
5407         .id_table       = rtl8169_pci_tbl,
5408         .probe          = rtl8169_init_one,
5409         .remove         = __devexit_p(rtl8169_remove_one),
5410         .shutdown       = rtl_shutdown,
5411         .driver.pm      = RTL8169_PM_OPS,
5412 };
5413
5414 static int __init rtl8169_init_module(void)
5415 {
5416         return pci_register_driver(&rtl8169_pci_driver);
5417 }
5418
5419 static void __exit rtl8169_cleanup_module(void)
5420 {
5421         pci_unregister_driver(&rtl8169_pci_driver);
5422 }
5423
5424 module_init(rtl8169_init_module);
5425 module_exit(rtl8169_cleanup_module);