qlge: Add support for device ID 8000.
[linux-2.6.git] / drivers / net / qlge / qlge_main.c
1 /*
2  * QLogic qlge NIC HBA Driver
3  * Copyright (c)  2003-2008 QLogic Corporation
4  * See LICENSE.qlge for copyright and licensing details.
5  * Author:     Linux qlge network device driver by
6  *                      Ron Mercer <ron.mercer@qlogic.com>
7  */
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/pagemap.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/dmapool.h>
19 #include <linux/mempool.h>
20 #include <linux/spinlock.h>
21 #include <linux/kthread.h>
22 #include <linux/interrupt.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/in.h>
26 #include <linux/ip.h>
27 #include <linux/ipv6.h>
28 #include <net/ipv6.h>
29 #include <linux/tcp.h>
30 #include <linux/udp.h>
31 #include <linux/if_arp.h>
32 #include <linux/if_ether.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/skbuff.h>
37 #include <linux/rtnetlink.h>
38 #include <linux/if_vlan.h>
39 #include <linux/delay.h>
40 #include <linux/mm.h>
41 #include <linux/vmalloc.h>
42 #include <net/ip6_checksum.h>
43
44 #include "qlge.h"
45
46 char qlge_driver_name[] = DRV_NAME;
47 const char qlge_driver_version[] = DRV_VERSION;
48
49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
50 MODULE_DESCRIPTION(DRV_STRING " ");
51 MODULE_LICENSE("GPL");
52 MODULE_VERSION(DRV_VERSION);
53
54 static const u32 default_msg =
55     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
56 /* NETIF_MSG_TIMER |    */
57     NETIF_MSG_IFDOWN |
58     NETIF_MSG_IFUP |
59     NETIF_MSG_RX_ERR |
60     NETIF_MSG_TX_ERR |
61 /*  NETIF_MSG_TX_QUEUED | */
62 /*  NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS | */
63 /* NETIF_MSG_PKTDATA | */
64     NETIF_MSG_HW | NETIF_MSG_WOL | 0;
65
66 static int debug = 0x00007fff;  /* defaults above */
67 module_param(debug, int, 0);
68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
69
70 #define MSIX_IRQ 0
71 #define MSI_IRQ 1
72 #define LEG_IRQ 2
73 static int irq_type = MSIX_IRQ;
74 module_param(irq_type, int, MSIX_IRQ);
75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
76
77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
78         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8012)},
79         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8000)},
80         /* required last entry */
81         {0,}
82 };
83
84 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
85
86 /* This hardware semaphore causes exclusive access to
87  * resources shared between the NIC driver, MPI firmware,
88  * FCOE firmware and the FC driver.
89  */
90 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
91 {
92         u32 sem_bits = 0;
93
94         switch (sem_mask) {
95         case SEM_XGMAC0_MASK:
96                 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
97                 break;
98         case SEM_XGMAC1_MASK:
99                 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
100                 break;
101         case SEM_ICB_MASK:
102                 sem_bits = SEM_SET << SEM_ICB_SHIFT;
103                 break;
104         case SEM_MAC_ADDR_MASK:
105                 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
106                 break;
107         case SEM_FLASH_MASK:
108                 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
109                 break;
110         case SEM_PROBE_MASK:
111                 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
112                 break;
113         case SEM_RT_IDX_MASK:
114                 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
115                 break;
116         case SEM_PROC_REG_MASK:
117                 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
118                 break;
119         default:
120                 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
121                 return -EINVAL;
122         }
123
124         ql_write32(qdev, SEM, sem_bits | sem_mask);
125         return !(ql_read32(qdev, SEM) & sem_bits);
126 }
127
128 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
129 {
130         unsigned int wait_count = 30;
131         do {
132                 if (!ql_sem_trylock(qdev, sem_mask))
133                         return 0;
134                 udelay(100);
135         } while (--wait_count);
136         return -ETIMEDOUT;
137 }
138
139 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
140 {
141         ql_write32(qdev, SEM, sem_mask);
142         ql_read32(qdev, SEM);   /* flush */
143 }
144
145 /* This function waits for a specific bit to come ready
146  * in a given register.  It is used mostly by the initialize
147  * process, but is also used in kernel thread API such as
148  * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
149  */
150 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
151 {
152         u32 temp;
153         int count = UDELAY_COUNT;
154
155         while (count) {
156                 temp = ql_read32(qdev, reg);
157
158                 /* check for errors */
159                 if (temp & err_bit) {
160                         QPRINTK(qdev, PROBE, ALERT,
161                                 "register 0x%.08x access error, value = 0x%.08x!.\n",
162                                 reg, temp);
163                         return -EIO;
164                 } else if (temp & bit)
165                         return 0;
166                 udelay(UDELAY_DELAY);
167                 count--;
168         }
169         QPRINTK(qdev, PROBE, ALERT,
170                 "Timed out waiting for reg %x to come ready.\n", reg);
171         return -ETIMEDOUT;
172 }
173
174 /* The CFG register is used to download TX and RX control blocks
175  * to the chip. This function waits for an operation to complete.
176  */
177 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
178 {
179         int count = UDELAY_COUNT;
180         u32 temp;
181
182         while (count) {
183                 temp = ql_read32(qdev, CFG);
184                 if (temp & CFG_LE)
185                         return -EIO;
186                 if (!(temp & bit))
187                         return 0;
188                 udelay(UDELAY_DELAY);
189                 count--;
190         }
191         return -ETIMEDOUT;
192 }
193
194
195 /* Used to issue init control blocks to hw. Maps control block,
196  * sets address, triggers download, waits for completion.
197  */
198 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
199                  u16 q_id)
200 {
201         u64 map;
202         int status = 0;
203         int direction;
204         u32 mask;
205         u32 value;
206
207         direction =
208             (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
209             PCI_DMA_FROMDEVICE;
210
211         map = pci_map_single(qdev->pdev, ptr, size, direction);
212         if (pci_dma_mapping_error(qdev->pdev, map)) {
213                 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
214                 return -ENOMEM;
215         }
216
217         status = ql_wait_cfg(qdev, bit);
218         if (status) {
219                 QPRINTK(qdev, IFUP, ERR,
220                         "Timed out waiting for CFG to come ready.\n");
221                 goto exit;
222         }
223
224         status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
225         if (status)
226                 goto exit;
227         ql_write32(qdev, ICB_L, (u32) map);
228         ql_write32(qdev, ICB_H, (u32) (map >> 32));
229         ql_sem_unlock(qdev, SEM_ICB_MASK);      /* does flush too */
230
231         mask = CFG_Q_MASK | (bit << 16);
232         value = bit | (q_id << CFG_Q_SHIFT);
233         ql_write32(qdev, CFG, (mask | value));
234
235         /*
236          * Wait for the bit to clear after signaling hw.
237          */
238         status = ql_wait_cfg(qdev, bit);
239 exit:
240         pci_unmap_single(qdev->pdev, map, size, direction);
241         return status;
242 }
243
244 /* Get a specific MAC address from the CAM.  Used for debug and reg dump. */
245 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
246                         u32 *value)
247 {
248         u32 offset = 0;
249         int status;
250
251         switch (type) {
252         case MAC_ADDR_TYPE_MULTI_MAC:
253         case MAC_ADDR_TYPE_CAM_MAC:
254                 {
255                         status =
256                             ql_wait_reg_rdy(qdev,
257                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
258                         if (status)
259                                 goto exit;
260                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
261                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
262                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
263                         status =
264                             ql_wait_reg_rdy(qdev,
265                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
266                         if (status)
267                                 goto exit;
268                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
269                         status =
270                             ql_wait_reg_rdy(qdev,
271                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
272                         if (status)
273                                 goto exit;
274                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
275                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
276                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
277                         status =
278                             ql_wait_reg_rdy(qdev,
279                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
280                         if (status)
281                                 goto exit;
282                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
283                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
284                                 status =
285                                     ql_wait_reg_rdy(qdev,
286                                         MAC_ADDR_IDX, MAC_ADDR_MW, 0);
287                                 if (status)
288                                         goto exit;
289                                 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
290                                            (index << MAC_ADDR_IDX_SHIFT) | /* index */
291                                            MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
292                                 status =
293                                     ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
294                                                     MAC_ADDR_MR, 0);
295                                 if (status)
296                                         goto exit;
297                                 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
298                         }
299                         break;
300                 }
301         case MAC_ADDR_TYPE_VLAN:
302         case MAC_ADDR_TYPE_MULTI_FLTR:
303         default:
304                 QPRINTK(qdev, IFUP, CRIT,
305                         "Address type %d not yet supported.\n", type);
306                 status = -EPERM;
307         }
308 exit:
309         return status;
310 }
311
312 /* Set up a MAC, multicast or VLAN address for the
313  * inbound frame matching.
314  */
315 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
316                                u16 index)
317 {
318         u32 offset = 0;
319         int status = 0;
320
321         switch (type) {
322         case MAC_ADDR_TYPE_MULTI_MAC:
323         case MAC_ADDR_TYPE_CAM_MAC:
324                 {
325                         u32 cam_output;
326                         u32 upper = (addr[0] << 8) | addr[1];
327                         u32 lower =
328                             (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
329                             (addr[5]);
330
331                         QPRINTK(qdev, IFUP, DEBUG,
332                                 "Adding %s address %pM"
333                                 " at index %d in the CAM.\n",
334                                 ((type ==
335                                   MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
336                                  "UNICAST"), addr, index);
337
338                         status =
339                             ql_wait_reg_rdy(qdev,
340                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
341                         if (status)
342                                 goto exit;
343                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
344                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
345                                    type);       /* type */
346                         ql_write32(qdev, MAC_ADDR_DATA, lower);
347                         status =
348                             ql_wait_reg_rdy(qdev,
349                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
350                         if (status)
351                                 goto exit;
352                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
353                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
354                                    type);       /* type */
355                         ql_write32(qdev, MAC_ADDR_DATA, upper);
356                         status =
357                             ql_wait_reg_rdy(qdev,
358                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
359                         if (status)
360                                 goto exit;
361                         ql_write32(qdev, MAC_ADDR_IDX, (offset) |       /* offset */
362                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
363                                    type);       /* type */
364                         /* This field should also include the queue id
365                            and possibly the function id.  Right now we hardcode
366                            the route field to NIC core.
367                          */
368                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
369                                 cam_output = (CAM_OUT_ROUTE_NIC |
370                                               (qdev->
371                                                func << CAM_OUT_FUNC_SHIFT) |
372                                               (qdev->
373                                                rss_ring_first_cq_id <<
374                                                CAM_OUT_CQ_ID_SHIFT));
375                                 if (qdev->vlgrp)
376                                         cam_output |= CAM_OUT_RV;
377                                 /* route to NIC core */
378                                 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
379                         }
380                         break;
381                 }
382         case MAC_ADDR_TYPE_VLAN:
383                 {
384                         u32 enable_bit = *((u32 *) &addr[0]);
385                         /* For VLAN, the addr actually holds a bit that
386                          * either enables or disables the vlan id we are
387                          * addressing. It's either MAC_ADDR_E on or off.
388                          * That's bit-27 we're talking about.
389                          */
390                         QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
391                                 (enable_bit ? "Adding" : "Removing"),
392                                 index, (enable_bit ? "to" : "from"));
393
394                         status =
395                             ql_wait_reg_rdy(qdev,
396                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
397                         if (status)
398                                 goto exit;
399                         ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
400                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
401                                    type |       /* type */
402                                    enable_bit); /* enable/disable */
403                         break;
404                 }
405         case MAC_ADDR_TYPE_MULTI_FLTR:
406         default:
407                 QPRINTK(qdev, IFUP, CRIT,
408                         "Address type %d not yet supported.\n", type);
409                 status = -EPERM;
410         }
411 exit:
412         return status;
413 }
414
415 /* Get a specific frame routing value from the CAM.
416  * Used for debug and reg dump.
417  */
418 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
419 {
420         int status = 0;
421
422         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
423         if (status)
424                 goto exit;
425
426         ql_write32(qdev, RT_IDX,
427                    RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
428         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
429         if (status)
430                 goto exit;
431         *value = ql_read32(qdev, RT_DATA);
432 exit:
433         return status;
434 }
435
436 /* The NIC function for this chip has 16 routing indexes.  Each one can be used
437  * to route different frame types to various inbound queues.  We send broadcast/
438  * multicast/error frames to the default queue for slow handling,
439  * and CAM hit/RSS frames to the fast handling queues.
440  */
441 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
442                               int enable)
443 {
444         int status = -EINVAL; /* Return error if no mask match. */
445         u32 value = 0;
446
447         QPRINTK(qdev, IFUP, DEBUG,
448                 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
449                 (enable ? "Adding" : "Removing"),
450                 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
451                 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
452                 ((index ==
453                   RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
454                 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
455                 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
456                 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
457                 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
458                 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
459                 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
460                 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
461                 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
462                 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
463                 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
464                 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
465                 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
466                 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
467                 (enable ? "to" : "from"));
468
469         switch (mask) {
470         case RT_IDX_CAM_HIT:
471                 {
472                         value = RT_IDX_DST_CAM_Q |      /* dest */
473                             RT_IDX_TYPE_NICQ |  /* type */
474                             (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
475                         break;
476                 }
477         case RT_IDX_VALID:      /* Promiscuous Mode frames. */
478                 {
479                         value = RT_IDX_DST_DFLT_Q |     /* dest */
480                             RT_IDX_TYPE_NICQ |  /* type */
481                             (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
482                         break;
483                 }
484         case RT_IDX_ERR:        /* Pass up MAC,IP,TCP/UDP error frames. */
485                 {
486                         value = RT_IDX_DST_DFLT_Q |     /* dest */
487                             RT_IDX_TYPE_NICQ |  /* type */
488                             (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
489                         break;
490                 }
491         case RT_IDX_BCAST:      /* Pass up Broadcast frames to default Q. */
492                 {
493                         value = RT_IDX_DST_DFLT_Q |     /* dest */
494                             RT_IDX_TYPE_NICQ |  /* type */
495                             (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
496                         break;
497                 }
498         case RT_IDX_MCAST:      /* Pass up All Multicast frames. */
499                 {
500                         value = RT_IDX_DST_CAM_Q |      /* dest */
501                             RT_IDX_TYPE_NICQ |  /* type */
502                             (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
503                         break;
504                 }
505         case RT_IDX_MCAST_MATCH:        /* Pass up matched Multicast frames. */
506                 {
507                         value = RT_IDX_DST_CAM_Q |      /* dest */
508                             RT_IDX_TYPE_NICQ |  /* type */
509                             (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
510                         break;
511                 }
512         case RT_IDX_RSS_MATCH:  /* Pass up matched RSS frames. */
513                 {
514                         value = RT_IDX_DST_RSS |        /* dest */
515                             RT_IDX_TYPE_NICQ |  /* type */
516                             (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
517                         break;
518                 }
519         case 0:         /* Clear the E-bit on an entry. */
520                 {
521                         value = RT_IDX_DST_DFLT_Q |     /* dest */
522                             RT_IDX_TYPE_NICQ |  /* type */
523                             (index << RT_IDX_IDX_SHIFT);/* index */
524                         break;
525                 }
526         default:
527                 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
528                         mask);
529                 status = -EPERM;
530                 goto exit;
531         }
532
533         if (value) {
534                 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
535                 if (status)
536                         goto exit;
537                 value |= (enable ? RT_IDX_E : 0);
538                 ql_write32(qdev, RT_IDX, value);
539                 ql_write32(qdev, RT_DATA, enable ? mask : 0);
540         }
541 exit:
542         return status;
543 }
544
545 static void ql_enable_interrupts(struct ql_adapter *qdev)
546 {
547         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
548 }
549
550 static void ql_disable_interrupts(struct ql_adapter *qdev)
551 {
552         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
553 }
554
555 /* If we're running with multiple MSI-X vectors then we enable on the fly.
556  * Otherwise, we may have multiple outstanding workers and don't want to
557  * enable until the last one finishes. In this case, the irq_cnt gets
558  * incremented everytime we queue a worker and decremented everytime
559  * a worker finishes.  Once it hits zero we enable the interrupt.
560  */
561 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
562 {
563         u32 var = 0;
564         unsigned long hw_flags = 0;
565         struct intr_context *ctx = qdev->intr_context + intr;
566
567         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
568                 /* Always enable if we're MSIX multi interrupts and
569                  * it's not the default (zeroeth) interrupt.
570                  */
571                 ql_write32(qdev, INTR_EN,
572                            ctx->intr_en_mask);
573                 var = ql_read32(qdev, STS);
574                 return var;
575         }
576
577         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
578         if (atomic_dec_and_test(&ctx->irq_cnt)) {
579                 ql_write32(qdev, INTR_EN,
580                            ctx->intr_en_mask);
581                 var = ql_read32(qdev, STS);
582         }
583         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
584         return var;
585 }
586
587 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
588 {
589         u32 var = 0;
590         unsigned long hw_flags;
591         struct intr_context *ctx;
592
593         /* HW disables for us if we're MSIX multi interrupts and
594          * it's not the default (zeroeth) interrupt.
595          */
596         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
597                 return 0;
598
599         ctx = qdev->intr_context + intr;
600         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
601         if (!atomic_read(&ctx->irq_cnt)) {
602                 ql_write32(qdev, INTR_EN,
603                 ctx->intr_dis_mask);
604                 var = ql_read32(qdev, STS);
605         }
606         atomic_inc(&ctx->irq_cnt);
607         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
608         return var;
609 }
610
611 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
612 {
613         int i;
614         for (i = 0; i < qdev->intr_count; i++) {
615                 /* The enable call does a atomic_dec_and_test
616                  * and enables only if the result is zero.
617                  * So we precharge it here.
618                  */
619                 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
620                         i == 0))
621                         atomic_set(&qdev->intr_context[i].irq_cnt, 1);
622                 ql_enable_completion_interrupt(qdev, i);
623         }
624
625 }
626
627 static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str)
628 {
629         int status, i;
630         u16 csum = 0;
631         __le16 *flash = (__le16 *)&qdev->flash;
632
633         status = strncmp((char *)&qdev->flash, str, 4);
634         if (status) {
635                 QPRINTK(qdev, IFUP, ERR, "Invalid flash signature.\n");
636                 return  status;
637         }
638
639         for (i = 0; i < size; i++)
640                 csum += le16_to_cpu(*flash++);
641
642         if (csum)
643                 QPRINTK(qdev, IFUP, ERR,
644                         "Invalid flash checksum, csum = 0x%.04x.\n", csum);
645
646         return csum;
647 }
648
649 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
650 {
651         int status = 0;
652         /* wait for reg to come ready */
653         status = ql_wait_reg_rdy(qdev,
654                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
655         if (status)
656                 goto exit;
657         /* set up for reg read */
658         ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
659         /* wait for reg to come ready */
660         status = ql_wait_reg_rdy(qdev,
661                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
662         if (status)
663                 goto exit;
664          /* This data is stored on flash as an array of
665          * __le32.  Since ql_read32() returns cpu endian
666          * we need to swap it back.
667          */
668         *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
669 exit:
670         return status;
671 }
672
673 static int ql_get_8000_flash_params(struct ql_adapter *qdev)
674 {
675         u32 i, size;
676         int status;
677         __le32 *p = (__le32 *)&qdev->flash;
678         u32 offset;
679
680         /* Get flash offset for function and adjust
681          * for dword access.
682          */
683         if (!qdev->func)
684                 offset = FUNC0_FLASH_OFFSET / sizeof(u32);
685         else
686                 offset = FUNC1_FLASH_OFFSET / sizeof(u32);
687
688         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
689                 return -ETIMEDOUT;
690
691         size = sizeof(struct flash_params_8000) / sizeof(u32);
692         for (i = 0; i < size; i++, p++) {
693                 status = ql_read_flash_word(qdev, i+offset, p);
694                 if (status) {
695                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
696                         goto exit;
697                 }
698         }
699
700         status = ql_validate_flash(qdev,
701                         sizeof(struct flash_params_8000) / sizeof(u16),
702                         "8000");
703         if (status) {
704                 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
705                 status = -EINVAL;
706                 goto exit;
707         }
708
709         if (!is_valid_ether_addr(qdev->flash.flash_params_8000.mac_addr)) {
710                 QPRINTK(qdev, IFUP, ERR, "Invalid MAC address.\n");
711                 status = -EINVAL;
712                 goto exit;
713         }
714
715         memcpy(qdev->ndev->dev_addr,
716                 qdev->flash.flash_params_8000.mac_addr,
717                 qdev->ndev->addr_len);
718
719 exit:
720         ql_sem_unlock(qdev, SEM_FLASH_MASK);
721         return status;
722 }
723
724 static int ql_get_8012_flash_params(struct ql_adapter *qdev)
725 {
726         int i;
727         int status;
728         __le32 *p = (__le32 *)&qdev->flash;
729         u32 offset = 0;
730         u32 size = sizeof(struct flash_params_8012) / sizeof(u32);
731
732         /* Second function's parameters follow the first
733          * function's.
734          */
735         if (qdev->func)
736                 offset = size;
737
738         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
739                 return -ETIMEDOUT;
740
741         for (i = 0; i < size; i++, p++) {
742                 status = ql_read_flash_word(qdev, i+offset, p);
743                 if (status) {
744                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
745                         goto exit;
746                 }
747
748         }
749
750         status = ql_validate_flash(qdev,
751                         sizeof(struct flash_params_8012) / sizeof(u16),
752                         "8012");
753         if (status) {
754                 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
755                 status = -EINVAL;
756                 goto exit;
757         }
758
759         if (!is_valid_ether_addr(qdev->flash.flash_params_8012.mac_addr)) {
760                 status = -EINVAL;
761                 goto exit;
762         }
763
764         memcpy(qdev->ndev->dev_addr,
765                 qdev->flash.flash_params_8012.mac_addr,
766                 qdev->ndev->addr_len);
767
768 exit:
769         ql_sem_unlock(qdev, SEM_FLASH_MASK);
770         return status;
771 }
772
773 /* xgmac register are located behind the xgmac_addr and xgmac_data
774  * register pair.  Each read/write requires us to wait for the ready
775  * bit before reading/writing the data.
776  */
777 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
778 {
779         int status;
780         /* wait for reg to come ready */
781         status = ql_wait_reg_rdy(qdev,
782                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
783         if (status)
784                 return status;
785         /* write the data to the data reg */
786         ql_write32(qdev, XGMAC_DATA, data);
787         /* trigger the write */
788         ql_write32(qdev, XGMAC_ADDR, reg);
789         return status;
790 }
791
792 /* xgmac register are located behind the xgmac_addr and xgmac_data
793  * register pair.  Each read/write requires us to wait for the ready
794  * bit before reading/writing the data.
795  */
796 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
797 {
798         int status = 0;
799         /* wait for reg to come ready */
800         status = ql_wait_reg_rdy(qdev,
801                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
802         if (status)
803                 goto exit;
804         /* set up for reg read */
805         ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
806         /* wait for reg to come ready */
807         status = ql_wait_reg_rdy(qdev,
808                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
809         if (status)
810                 goto exit;
811         /* get the data */
812         *data = ql_read32(qdev, XGMAC_DATA);
813 exit:
814         return status;
815 }
816
817 /* This is used for reading the 64-bit statistics regs. */
818 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
819 {
820         int status = 0;
821         u32 hi = 0;
822         u32 lo = 0;
823
824         status = ql_read_xgmac_reg(qdev, reg, &lo);
825         if (status)
826                 goto exit;
827
828         status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
829         if (status)
830                 goto exit;
831
832         *data = (u64) lo | ((u64) hi << 32);
833
834 exit:
835         return status;
836 }
837
838 static int ql_8000_port_initialize(struct ql_adapter *qdev)
839 {
840         return ql_mb_get_fw_state(qdev);
841 }
842
843 /* Take the MAC Core out of reset.
844  * Enable statistics counting.
845  * Take the transmitter/receiver out of reset.
846  * This functionality may be done in the MPI firmware at a
847  * later date.
848  */
849 static int ql_8012_port_initialize(struct ql_adapter *qdev)
850 {
851         int status = 0;
852         u32 data;
853
854         if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
855                 /* Another function has the semaphore, so
856                  * wait for the port init bit to come ready.
857                  */
858                 QPRINTK(qdev, LINK, INFO,
859                         "Another function has the semaphore, so wait for the port init bit to come ready.\n");
860                 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
861                 if (status) {
862                         QPRINTK(qdev, LINK, CRIT,
863                                 "Port initialize timed out.\n");
864                 }
865                 return status;
866         }
867
868         QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
869         /* Set the core reset. */
870         status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
871         if (status)
872                 goto end;
873         data |= GLOBAL_CFG_RESET;
874         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
875         if (status)
876                 goto end;
877
878         /* Clear the core reset and turn on jumbo for receiver. */
879         data &= ~GLOBAL_CFG_RESET;      /* Clear core reset. */
880         data |= GLOBAL_CFG_JUMBO;       /* Turn on jumbo. */
881         data |= GLOBAL_CFG_TX_STAT_EN;
882         data |= GLOBAL_CFG_RX_STAT_EN;
883         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
884         if (status)
885                 goto end;
886
887         /* Enable transmitter, and clear it's reset. */
888         status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
889         if (status)
890                 goto end;
891         data &= ~TX_CFG_RESET;  /* Clear the TX MAC reset. */
892         data |= TX_CFG_EN;      /* Enable the transmitter. */
893         status = ql_write_xgmac_reg(qdev, TX_CFG, data);
894         if (status)
895                 goto end;
896
897         /* Enable receiver and clear it's reset. */
898         status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
899         if (status)
900                 goto end;
901         data &= ~RX_CFG_RESET;  /* Clear the RX MAC reset. */
902         data |= RX_CFG_EN;      /* Enable the receiver. */
903         status = ql_write_xgmac_reg(qdev, RX_CFG, data);
904         if (status)
905                 goto end;
906
907         /* Turn on jumbo. */
908         status =
909             ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
910         if (status)
911                 goto end;
912         status =
913             ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
914         if (status)
915                 goto end;
916
917         /* Signal to the world that the port is enabled.        */
918         ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
919 end:
920         ql_sem_unlock(qdev, qdev->xg_sem_mask);
921         return status;
922 }
923
924 /* Get the next large buffer. */
925 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
926 {
927         struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
928         rx_ring->lbq_curr_idx++;
929         if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
930                 rx_ring->lbq_curr_idx = 0;
931         rx_ring->lbq_free_cnt++;
932         return lbq_desc;
933 }
934
935 /* Get the next small buffer. */
936 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
937 {
938         struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
939         rx_ring->sbq_curr_idx++;
940         if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
941                 rx_ring->sbq_curr_idx = 0;
942         rx_ring->sbq_free_cnt++;
943         return sbq_desc;
944 }
945
946 /* Update an rx ring index. */
947 static void ql_update_cq(struct rx_ring *rx_ring)
948 {
949         rx_ring->cnsmr_idx++;
950         rx_ring->curr_entry++;
951         if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
952                 rx_ring->cnsmr_idx = 0;
953                 rx_ring->curr_entry = rx_ring->cq_base;
954         }
955 }
956
957 static void ql_write_cq_idx(struct rx_ring *rx_ring)
958 {
959         ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
960 }
961
962 /* Process (refill) a large buffer queue. */
963 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
964 {
965         u32 clean_idx = rx_ring->lbq_clean_idx;
966         u32 start_idx = clean_idx;
967         struct bq_desc *lbq_desc;
968         u64 map;
969         int i;
970
971         while (rx_ring->lbq_free_cnt > 16) {
972                 for (i = 0; i < 16; i++) {
973                         QPRINTK(qdev, RX_STATUS, DEBUG,
974                                 "lbq: try cleaning clean_idx = %d.\n",
975                                 clean_idx);
976                         lbq_desc = &rx_ring->lbq[clean_idx];
977                         if (lbq_desc->p.lbq_page == NULL) {
978                                 QPRINTK(qdev, RX_STATUS, DEBUG,
979                                         "lbq: getting new page for index %d.\n",
980                                         lbq_desc->index);
981                                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
982                                 if (lbq_desc->p.lbq_page == NULL) {
983                                         rx_ring->lbq_clean_idx = clean_idx;
984                                         QPRINTK(qdev, RX_STATUS, ERR,
985                                                 "Couldn't get a page.\n");
986                                         return;
987                                 }
988                                 map = pci_map_page(qdev->pdev,
989                                                    lbq_desc->p.lbq_page,
990                                                    0, PAGE_SIZE,
991                                                    PCI_DMA_FROMDEVICE);
992                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
993                                         rx_ring->lbq_clean_idx = clean_idx;
994                                         put_page(lbq_desc->p.lbq_page);
995                                         lbq_desc->p.lbq_page = NULL;
996                                         QPRINTK(qdev, RX_STATUS, ERR,
997                                                 "PCI mapping failed.\n");
998                                         return;
999                                 }
1000                                 pci_unmap_addr_set(lbq_desc, mapaddr, map);
1001                                 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
1002                                 *lbq_desc->addr = cpu_to_le64(map);
1003                         }
1004                         clean_idx++;
1005                         if (clean_idx == rx_ring->lbq_len)
1006                                 clean_idx = 0;
1007                 }
1008
1009                 rx_ring->lbq_clean_idx = clean_idx;
1010                 rx_ring->lbq_prod_idx += 16;
1011                 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
1012                         rx_ring->lbq_prod_idx = 0;
1013                 rx_ring->lbq_free_cnt -= 16;
1014         }
1015
1016         if (start_idx != clean_idx) {
1017                 QPRINTK(qdev, RX_STATUS, DEBUG,
1018                         "lbq: updating prod idx = %d.\n",
1019                         rx_ring->lbq_prod_idx);
1020                 ql_write_db_reg(rx_ring->lbq_prod_idx,
1021                                 rx_ring->lbq_prod_idx_db_reg);
1022         }
1023 }
1024
1025 /* Process (refill) a small buffer queue. */
1026 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1027 {
1028         u32 clean_idx = rx_ring->sbq_clean_idx;
1029         u32 start_idx = clean_idx;
1030         struct bq_desc *sbq_desc;
1031         u64 map;
1032         int i;
1033
1034         while (rx_ring->sbq_free_cnt > 16) {
1035                 for (i = 0; i < 16; i++) {
1036                         sbq_desc = &rx_ring->sbq[clean_idx];
1037                         QPRINTK(qdev, RX_STATUS, DEBUG,
1038                                 "sbq: try cleaning clean_idx = %d.\n",
1039                                 clean_idx);
1040                         if (sbq_desc->p.skb == NULL) {
1041                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1042                                         "sbq: getting new skb for index %d.\n",
1043                                         sbq_desc->index);
1044                                 sbq_desc->p.skb =
1045                                     netdev_alloc_skb(qdev->ndev,
1046                                                      rx_ring->sbq_buf_size);
1047                                 if (sbq_desc->p.skb == NULL) {
1048                                         QPRINTK(qdev, PROBE, ERR,
1049                                                 "Couldn't get an skb.\n");
1050                                         rx_ring->sbq_clean_idx = clean_idx;
1051                                         return;
1052                                 }
1053                                 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
1054                                 map = pci_map_single(qdev->pdev,
1055                                                      sbq_desc->p.skb->data,
1056                                                      rx_ring->sbq_buf_size /
1057                                                      2, PCI_DMA_FROMDEVICE);
1058                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
1059                                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
1060                                         rx_ring->sbq_clean_idx = clean_idx;
1061                                         dev_kfree_skb_any(sbq_desc->p.skb);
1062                                         sbq_desc->p.skb = NULL;
1063                                         return;
1064                                 }
1065                                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
1066                                 pci_unmap_len_set(sbq_desc, maplen,
1067                                                   rx_ring->sbq_buf_size / 2);
1068                                 *sbq_desc->addr = cpu_to_le64(map);
1069                         }
1070
1071                         clean_idx++;
1072                         if (clean_idx == rx_ring->sbq_len)
1073                                 clean_idx = 0;
1074                 }
1075                 rx_ring->sbq_clean_idx = clean_idx;
1076                 rx_ring->sbq_prod_idx += 16;
1077                 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
1078                         rx_ring->sbq_prod_idx = 0;
1079                 rx_ring->sbq_free_cnt -= 16;
1080         }
1081
1082         if (start_idx != clean_idx) {
1083                 QPRINTK(qdev, RX_STATUS, DEBUG,
1084                         "sbq: updating prod idx = %d.\n",
1085                         rx_ring->sbq_prod_idx);
1086                 ql_write_db_reg(rx_ring->sbq_prod_idx,
1087                                 rx_ring->sbq_prod_idx_db_reg);
1088         }
1089 }
1090
1091 static void ql_update_buffer_queues(struct ql_adapter *qdev,
1092                                     struct rx_ring *rx_ring)
1093 {
1094         ql_update_sbq(qdev, rx_ring);
1095         ql_update_lbq(qdev, rx_ring);
1096 }
1097
1098 /* Unmaps tx buffers.  Can be called from send() if a pci mapping
1099  * fails at some stage, or from the interrupt when a tx completes.
1100  */
1101 static void ql_unmap_send(struct ql_adapter *qdev,
1102                           struct tx_ring_desc *tx_ring_desc, int mapped)
1103 {
1104         int i;
1105         for (i = 0; i < mapped; i++) {
1106                 if (i == 0 || (i == 7 && mapped > 7)) {
1107                         /*
1108                          * Unmap the skb->data area, or the
1109                          * external sglist (AKA the Outbound
1110                          * Address List (OAL)).
1111                          * If its the zeroeth element, then it's
1112                          * the skb->data area.  If it's the 7th
1113                          * element and there is more than 6 frags,
1114                          * then its an OAL.
1115                          */
1116                         if (i == 7) {
1117                                 QPRINTK(qdev, TX_DONE, DEBUG,
1118                                         "unmapping OAL area.\n");
1119                         }
1120                         pci_unmap_single(qdev->pdev,
1121                                          pci_unmap_addr(&tx_ring_desc->map[i],
1122                                                         mapaddr),
1123                                          pci_unmap_len(&tx_ring_desc->map[i],
1124                                                        maplen),
1125                                          PCI_DMA_TODEVICE);
1126                 } else {
1127                         QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1128                                 i);
1129                         pci_unmap_page(qdev->pdev,
1130                                        pci_unmap_addr(&tx_ring_desc->map[i],
1131                                                       mapaddr),
1132                                        pci_unmap_len(&tx_ring_desc->map[i],
1133                                                      maplen), PCI_DMA_TODEVICE);
1134                 }
1135         }
1136
1137 }
1138
1139 /* Map the buffers for this transmit.  This will return
1140  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1141  */
1142 static int ql_map_send(struct ql_adapter *qdev,
1143                        struct ob_mac_iocb_req *mac_iocb_ptr,
1144                        struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1145 {
1146         int len = skb_headlen(skb);
1147         dma_addr_t map;
1148         int frag_idx, err, map_idx = 0;
1149         struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1150         int frag_cnt = skb_shinfo(skb)->nr_frags;
1151
1152         if (frag_cnt) {
1153                 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1154         }
1155         /*
1156          * Map the skb buffer first.
1157          */
1158         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1159
1160         err = pci_dma_mapping_error(qdev->pdev, map);
1161         if (err) {
1162                 QPRINTK(qdev, TX_QUEUED, ERR,
1163                         "PCI mapping failed with error: %d\n", err);
1164
1165                 return NETDEV_TX_BUSY;
1166         }
1167
1168         tbd->len = cpu_to_le32(len);
1169         tbd->addr = cpu_to_le64(map);
1170         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1171         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1172         map_idx++;
1173
1174         /*
1175          * This loop fills the remainder of the 8 address descriptors
1176          * in the IOCB.  If there are more than 7 fragments, then the
1177          * eighth address desc will point to an external list (OAL).
1178          * When this happens, the remainder of the frags will be stored
1179          * in this list.
1180          */
1181         for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1182                 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1183                 tbd++;
1184                 if (frag_idx == 6 && frag_cnt > 7) {
1185                         /* Let's tack on an sglist.
1186                          * Our control block will now
1187                          * look like this:
1188                          * iocb->seg[0] = skb->data
1189                          * iocb->seg[1] = frag[0]
1190                          * iocb->seg[2] = frag[1]
1191                          * iocb->seg[3] = frag[2]
1192                          * iocb->seg[4] = frag[3]
1193                          * iocb->seg[5] = frag[4]
1194                          * iocb->seg[6] = frag[5]
1195                          * iocb->seg[7] = ptr to OAL (external sglist)
1196                          * oal->seg[0] = frag[6]
1197                          * oal->seg[1] = frag[7]
1198                          * oal->seg[2] = frag[8]
1199                          * oal->seg[3] = frag[9]
1200                          * oal->seg[4] = frag[10]
1201                          *      etc...
1202                          */
1203                         /* Tack on the OAL in the eighth segment of IOCB. */
1204                         map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1205                                              sizeof(struct oal),
1206                                              PCI_DMA_TODEVICE);
1207                         err = pci_dma_mapping_error(qdev->pdev, map);
1208                         if (err) {
1209                                 QPRINTK(qdev, TX_QUEUED, ERR,
1210                                         "PCI mapping outbound address list with error: %d\n",
1211                                         err);
1212                                 goto map_error;
1213                         }
1214
1215                         tbd->addr = cpu_to_le64(map);
1216                         /*
1217                          * The length is the number of fragments
1218                          * that remain to be mapped times the length
1219                          * of our sglist (OAL).
1220                          */
1221                         tbd->len =
1222                             cpu_to_le32((sizeof(struct tx_buf_desc) *
1223                                          (frag_cnt - frag_idx)) | TX_DESC_C);
1224                         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1225                                            map);
1226                         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1227                                           sizeof(struct oal));
1228                         tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1229                         map_idx++;
1230                 }
1231
1232                 map =
1233                     pci_map_page(qdev->pdev, frag->page,
1234                                  frag->page_offset, frag->size,
1235                                  PCI_DMA_TODEVICE);
1236
1237                 err = pci_dma_mapping_error(qdev->pdev, map);
1238                 if (err) {
1239                         QPRINTK(qdev, TX_QUEUED, ERR,
1240                                 "PCI mapping frags failed with error: %d.\n",
1241                                 err);
1242                         goto map_error;
1243                 }
1244
1245                 tbd->addr = cpu_to_le64(map);
1246                 tbd->len = cpu_to_le32(frag->size);
1247                 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1248                 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1249                                   frag->size);
1250
1251         }
1252         /* Save the number of segments we've mapped. */
1253         tx_ring_desc->map_cnt = map_idx;
1254         /* Terminate the last segment. */
1255         tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1256         return NETDEV_TX_OK;
1257
1258 map_error:
1259         /*
1260          * If the first frag mapping failed, then i will be zero.
1261          * This causes the unmap of the skb->data area.  Otherwise
1262          * we pass in the number of frags that mapped successfully
1263          * so they can be umapped.
1264          */
1265         ql_unmap_send(qdev, tx_ring_desc, map_idx);
1266         return NETDEV_TX_BUSY;
1267 }
1268
1269 static void ql_realign_skb(struct sk_buff *skb, int len)
1270 {
1271         void *temp_addr = skb->data;
1272
1273         /* Undo the skb_reserve(skb,32) we did before
1274          * giving to hardware, and realign data on
1275          * a 2-byte boundary.
1276          */
1277         skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1278         skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1279         skb_copy_to_linear_data(skb, temp_addr,
1280                 (unsigned int)len);
1281 }
1282
1283 /*
1284  * This function builds an skb for the given inbound
1285  * completion.  It will be rewritten for readability in the near
1286  * future, but for not it works well.
1287  */
1288 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1289                                        struct rx_ring *rx_ring,
1290                                        struct ib_mac_iocb_rsp *ib_mac_rsp)
1291 {
1292         struct bq_desc *lbq_desc;
1293         struct bq_desc *sbq_desc;
1294         struct sk_buff *skb = NULL;
1295         u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1296        u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1297
1298         /*
1299          * Handle the header buffer if present.
1300          */
1301         if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1302             ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1303                 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1304                 /*
1305                  * Headers fit nicely into a small buffer.
1306                  */
1307                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1308                 pci_unmap_single(qdev->pdev,
1309                                 pci_unmap_addr(sbq_desc, mapaddr),
1310                                 pci_unmap_len(sbq_desc, maplen),
1311                                 PCI_DMA_FROMDEVICE);
1312                 skb = sbq_desc->p.skb;
1313                 ql_realign_skb(skb, hdr_len);
1314                 skb_put(skb, hdr_len);
1315                 sbq_desc->p.skb = NULL;
1316         }
1317
1318         /*
1319          * Handle the data buffer(s).
1320          */
1321         if (unlikely(!length)) {        /* Is there data too? */
1322                 QPRINTK(qdev, RX_STATUS, DEBUG,
1323                         "No Data buffer in this packet.\n");
1324                 return skb;
1325         }
1326
1327         if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1328                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1329                         QPRINTK(qdev, RX_STATUS, DEBUG,
1330                                 "Headers in small, data of %d bytes in small, combine them.\n", length);
1331                         /*
1332                          * Data is less than small buffer size so it's
1333                          * stuffed in a small buffer.
1334                          * For this case we append the data
1335                          * from the "data" small buffer to the "header" small
1336                          * buffer.
1337                          */
1338                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1339                         pci_dma_sync_single_for_cpu(qdev->pdev,
1340                                                     pci_unmap_addr
1341                                                     (sbq_desc, mapaddr),
1342                                                     pci_unmap_len
1343                                                     (sbq_desc, maplen),
1344                                                     PCI_DMA_FROMDEVICE);
1345                         memcpy(skb_put(skb, length),
1346                                sbq_desc->p.skb->data, length);
1347                         pci_dma_sync_single_for_device(qdev->pdev,
1348                                                        pci_unmap_addr
1349                                                        (sbq_desc,
1350                                                         mapaddr),
1351                                                        pci_unmap_len
1352                                                        (sbq_desc,
1353                                                         maplen),
1354                                                        PCI_DMA_FROMDEVICE);
1355                 } else {
1356                         QPRINTK(qdev, RX_STATUS, DEBUG,
1357                                 "%d bytes in a single small buffer.\n", length);
1358                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1359                         skb = sbq_desc->p.skb;
1360                         ql_realign_skb(skb, length);
1361                         skb_put(skb, length);
1362                         pci_unmap_single(qdev->pdev,
1363                                          pci_unmap_addr(sbq_desc,
1364                                                         mapaddr),
1365                                          pci_unmap_len(sbq_desc,
1366                                                        maplen),
1367                                          PCI_DMA_FROMDEVICE);
1368                         sbq_desc->p.skb = NULL;
1369                 }
1370         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1371                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1372                         QPRINTK(qdev, RX_STATUS, DEBUG,
1373                                 "Header in small, %d bytes in large. Chain large to small!\n", length);
1374                         /*
1375                          * The data is in a single large buffer.  We
1376                          * chain it to the header buffer's skb and let
1377                          * it rip.
1378                          */
1379                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1380                         pci_unmap_page(qdev->pdev,
1381                                        pci_unmap_addr(lbq_desc,
1382                                                       mapaddr),
1383                                        pci_unmap_len(lbq_desc, maplen),
1384                                        PCI_DMA_FROMDEVICE);
1385                         QPRINTK(qdev, RX_STATUS, DEBUG,
1386                                 "Chaining page to skb.\n");
1387                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1388                                            0, length);
1389                         skb->len += length;
1390                         skb->data_len += length;
1391                         skb->truesize += length;
1392                         lbq_desc->p.lbq_page = NULL;
1393                 } else {
1394                         /*
1395                          * The headers and data are in a single large buffer. We
1396                          * copy it to a new skb and let it go. This can happen with
1397                          * jumbo mtu on a non-TCP/UDP frame.
1398                          */
1399                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1400                         skb = netdev_alloc_skb(qdev->ndev, length);
1401                         if (skb == NULL) {
1402                                 QPRINTK(qdev, PROBE, DEBUG,
1403                                         "No skb available, drop the packet.\n");
1404                                 return NULL;
1405                         }
1406                         pci_unmap_page(qdev->pdev,
1407                                        pci_unmap_addr(lbq_desc,
1408                                                       mapaddr),
1409                                        pci_unmap_len(lbq_desc, maplen),
1410                                        PCI_DMA_FROMDEVICE);
1411                         skb_reserve(skb, NET_IP_ALIGN);
1412                         QPRINTK(qdev, RX_STATUS, DEBUG,
1413                                 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1414                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1415                                            0, length);
1416                         skb->len += length;
1417                         skb->data_len += length;
1418                         skb->truesize += length;
1419                         length -= length;
1420                         lbq_desc->p.lbq_page = NULL;
1421                         __pskb_pull_tail(skb,
1422                                 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1423                                 VLAN_ETH_HLEN : ETH_HLEN);
1424                 }
1425         } else {
1426                 /*
1427                  * The data is in a chain of large buffers
1428                  * pointed to by a small buffer.  We loop
1429                  * thru and chain them to the our small header
1430                  * buffer's skb.
1431                  * frags:  There are 18 max frags and our small
1432                  *         buffer will hold 32 of them. The thing is,
1433                  *         we'll use 3 max for our 9000 byte jumbo
1434                  *         frames.  If the MTU goes up we could
1435                  *          eventually be in trouble.
1436                  */
1437                 int size, offset, i = 0;
1438                 __le64 *bq, bq_array[8];
1439                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1440                 pci_unmap_single(qdev->pdev,
1441                                  pci_unmap_addr(sbq_desc, mapaddr),
1442                                  pci_unmap_len(sbq_desc, maplen),
1443                                  PCI_DMA_FROMDEVICE);
1444                 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1445                         /*
1446                          * This is an non TCP/UDP IP frame, so
1447                          * the headers aren't split into a small
1448                          * buffer.  We have to use the small buffer
1449                          * that contains our sg list as our skb to
1450                          * send upstairs. Copy the sg list here to
1451                          * a local buffer and use it to find the
1452                          * pages to chain.
1453                          */
1454                         QPRINTK(qdev, RX_STATUS, DEBUG,
1455                                 "%d bytes of headers & data in chain of large.\n", length);
1456                         skb = sbq_desc->p.skb;
1457                         bq = &bq_array[0];
1458                         memcpy(bq, skb->data, sizeof(bq_array));
1459                         sbq_desc->p.skb = NULL;
1460                         skb_reserve(skb, NET_IP_ALIGN);
1461                 } else {
1462                         QPRINTK(qdev, RX_STATUS, DEBUG,
1463                                 "Headers in small, %d bytes of data in chain of large.\n", length);
1464                         bq = (__le64 *)sbq_desc->p.skb->data;
1465                 }
1466                 while (length > 0) {
1467                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1468                         pci_unmap_page(qdev->pdev,
1469                                        pci_unmap_addr(lbq_desc,
1470                                                       mapaddr),
1471                                        pci_unmap_len(lbq_desc,
1472                                                      maplen),
1473                                        PCI_DMA_FROMDEVICE);
1474                         size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1475                         offset = 0;
1476
1477                         QPRINTK(qdev, RX_STATUS, DEBUG,
1478                                 "Adding page %d to skb for %d bytes.\n",
1479                                 i, size);
1480                         skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1481                                            offset, size);
1482                         skb->len += size;
1483                         skb->data_len += size;
1484                         skb->truesize += size;
1485                         length -= size;
1486                         lbq_desc->p.lbq_page = NULL;
1487                         bq++;
1488                         i++;
1489                 }
1490                 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1491                                 VLAN_ETH_HLEN : ETH_HLEN);
1492         }
1493         return skb;
1494 }
1495
1496 /* Process an inbound completion from an rx ring. */
1497 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1498                                    struct rx_ring *rx_ring,
1499                                    struct ib_mac_iocb_rsp *ib_mac_rsp)
1500 {
1501         struct net_device *ndev = qdev->ndev;
1502         struct sk_buff *skb = NULL;
1503
1504         QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1505
1506         skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1507         if (unlikely(!skb)) {
1508                 QPRINTK(qdev, RX_STATUS, DEBUG,
1509                         "No skb available, drop packet.\n");
1510                 return;
1511         }
1512
1513         prefetch(skb->data);
1514         skb->dev = ndev;
1515         if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1516                 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1517                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1518                         IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1519                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1520                         IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1521                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1522                         IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1523         }
1524         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1525                 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1526         }
1527         if (ib_mac_rsp->flags1 & (IB_MAC_IOCB_RSP_IE | IB_MAC_IOCB_RSP_TE)) {
1528                 QPRINTK(qdev, RX_STATUS, ERR,
1529                         "Bad checksum for this %s packet.\n",
1530                         ((ib_mac_rsp->
1531                           flags2 & IB_MAC_IOCB_RSP_T) ? "TCP" : "UDP"));
1532                 skb->ip_summed = CHECKSUM_NONE;
1533         } else if (qdev->rx_csum &&
1534                    ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ||
1535                     ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1536                      !(ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU)))) {
1537                 QPRINTK(qdev, RX_STATUS, DEBUG, "RX checksum done!\n");
1538                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1539         }
1540         qdev->stats.rx_packets++;
1541         qdev->stats.rx_bytes += skb->len;
1542         skb->protocol = eth_type_trans(skb, ndev);
1543         skb_record_rx_queue(skb, rx_ring - &qdev->rx_ring[0]);
1544         if (qdev->vlgrp && (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)) {
1545                 QPRINTK(qdev, RX_STATUS, DEBUG,
1546                         "Passing a VLAN packet upstream.\n");
1547                 vlan_hwaccel_receive_skb(skb, qdev->vlgrp,
1548                                 le16_to_cpu(ib_mac_rsp->vlan_id));
1549         } else {
1550                 QPRINTK(qdev, RX_STATUS, DEBUG,
1551                         "Passing a normal packet upstream.\n");
1552                 netif_receive_skb(skb);
1553         }
1554 }
1555
1556 /* Process an outbound completion from an rx ring. */
1557 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1558                                    struct ob_mac_iocb_rsp *mac_rsp)
1559 {
1560         struct tx_ring *tx_ring;
1561         struct tx_ring_desc *tx_ring_desc;
1562
1563         QL_DUMP_OB_MAC_RSP(mac_rsp);
1564         tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1565         tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1566         ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1567         qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1568         qdev->stats.tx_packets++;
1569         dev_kfree_skb(tx_ring_desc->skb);
1570         tx_ring_desc->skb = NULL;
1571
1572         if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1573                                         OB_MAC_IOCB_RSP_S |
1574                                         OB_MAC_IOCB_RSP_L |
1575                                         OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1576                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1577                         QPRINTK(qdev, TX_DONE, WARNING,
1578                                 "Total descriptor length did not match transfer length.\n");
1579                 }
1580                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1581                         QPRINTK(qdev, TX_DONE, WARNING,
1582                                 "Frame too short to be legal, not sent.\n");
1583                 }
1584                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1585                         QPRINTK(qdev, TX_DONE, WARNING,
1586                                 "Frame too long, but sent anyway.\n");
1587                 }
1588                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1589                         QPRINTK(qdev, TX_DONE, WARNING,
1590                                 "PCI backplane error. Frame not sent.\n");
1591                 }
1592         }
1593         atomic_inc(&tx_ring->tx_count);
1594 }
1595
1596 /* Fire up a handler to reset the MPI processor. */
1597 void ql_queue_fw_error(struct ql_adapter *qdev)
1598 {
1599         netif_stop_queue(qdev->ndev);
1600         netif_carrier_off(qdev->ndev);
1601         queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1602 }
1603
1604 void ql_queue_asic_error(struct ql_adapter *qdev)
1605 {
1606         netif_stop_queue(qdev->ndev);
1607         netif_carrier_off(qdev->ndev);
1608         ql_disable_interrupts(qdev);
1609         /* Clear adapter up bit to signal the recovery
1610          * process that it shouldn't kill the reset worker
1611          * thread
1612          */
1613         clear_bit(QL_ADAPTER_UP, &qdev->flags);
1614         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1615 }
1616
1617 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1618                                     struct ib_ae_iocb_rsp *ib_ae_rsp)
1619 {
1620         switch (ib_ae_rsp->event) {
1621         case MGMT_ERR_EVENT:
1622                 QPRINTK(qdev, RX_ERR, ERR,
1623                         "Management Processor Fatal Error.\n");
1624                 ql_queue_fw_error(qdev);
1625                 return;
1626
1627         case CAM_LOOKUP_ERR_EVENT:
1628                 QPRINTK(qdev, LINK, ERR,
1629                         "Multiple CAM hits lookup occurred.\n");
1630                 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1631                 ql_queue_asic_error(qdev);
1632                 return;
1633
1634         case SOFT_ECC_ERROR_EVENT:
1635                 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1636                 ql_queue_asic_error(qdev);
1637                 break;
1638
1639         case PCI_ERR_ANON_BUF_RD:
1640                 QPRINTK(qdev, RX_ERR, ERR,
1641                         "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1642                         ib_ae_rsp->q_id);
1643                 ql_queue_asic_error(qdev);
1644                 break;
1645
1646         default:
1647                 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1648                         ib_ae_rsp->event);
1649                 ql_queue_asic_error(qdev);
1650                 break;
1651         }
1652 }
1653
1654 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1655 {
1656         struct ql_adapter *qdev = rx_ring->qdev;
1657         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1658         struct ob_mac_iocb_rsp *net_rsp = NULL;
1659         int count = 0;
1660
1661         /* While there are entries in the completion queue. */
1662         while (prod != rx_ring->cnsmr_idx) {
1663
1664                 QPRINTK(qdev, RX_STATUS, DEBUG,
1665                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1666                         prod, rx_ring->cnsmr_idx);
1667
1668                 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1669                 rmb();
1670                 switch (net_rsp->opcode) {
1671
1672                 case OPCODE_OB_MAC_TSO_IOCB:
1673                 case OPCODE_OB_MAC_IOCB:
1674                         ql_process_mac_tx_intr(qdev, net_rsp);
1675                         break;
1676                 default:
1677                         QPRINTK(qdev, RX_STATUS, DEBUG,
1678                                 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1679                                 net_rsp->opcode);
1680                 }
1681                 count++;
1682                 ql_update_cq(rx_ring);
1683                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1684         }
1685         ql_write_cq_idx(rx_ring);
1686         if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) {
1687                 struct tx_ring *tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1688                 if (atomic_read(&tx_ring->queue_stopped) &&
1689                     (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1690                         /*
1691                          * The queue got stopped because the tx_ring was full.
1692                          * Wake it up, because it's now at least 25% empty.
1693                          */
1694                         netif_wake_queue(qdev->ndev);
1695         }
1696
1697         return count;
1698 }
1699
1700 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1701 {
1702         struct ql_adapter *qdev = rx_ring->qdev;
1703         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1704         struct ql_net_rsp_iocb *net_rsp;
1705         int count = 0;
1706
1707         /* While there are entries in the completion queue. */
1708         while (prod != rx_ring->cnsmr_idx) {
1709
1710                 QPRINTK(qdev, RX_STATUS, DEBUG,
1711                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1712                         prod, rx_ring->cnsmr_idx);
1713
1714                 net_rsp = rx_ring->curr_entry;
1715                 rmb();
1716                 switch (net_rsp->opcode) {
1717                 case OPCODE_IB_MAC_IOCB:
1718                         ql_process_mac_rx_intr(qdev, rx_ring,
1719                                                (struct ib_mac_iocb_rsp *)
1720                                                net_rsp);
1721                         break;
1722
1723                 case OPCODE_IB_AE_IOCB:
1724                         ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1725                                                 net_rsp);
1726                         break;
1727                 default:
1728                         {
1729                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1730                                         "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1731                                         net_rsp->opcode);
1732                         }
1733                 }
1734                 count++;
1735                 ql_update_cq(rx_ring);
1736                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1737                 if (count == budget)
1738                         break;
1739         }
1740         ql_update_buffer_queues(qdev, rx_ring);
1741         ql_write_cq_idx(rx_ring);
1742         return count;
1743 }
1744
1745 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1746 {
1747         struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1748         struct ql_adapter *qdev = rx_ring->qdev;
1749         int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1750
1751         QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1752                 rx_ring->cq_id);
1753
1754         if (work_done < budget) {
1755                 __napi_complete(napi);
1756                 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1757         }
1758         return work_done;
1759 }
1760
1761 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1762 {
1763         struct ql_adapter *qdev = netdev_priv(ndev);
1764
1765         qdev->vlgrp = grp;
1766         if (grp) {
1767                 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1768                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1769                            NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1770         } else {
1771                 QPRINTK(qdev, IFUP, DEBUG,
1772                         "Turning off VLAN in NIC_RCV_CFG.\n");
1773                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1774         }
1775 }
1776
1777 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1778 {
1779         struct ql_adapter *qdev = netdev_priv(ndev);
1780         u32 enable_bit = MAC_ADDR_E;
1781         int status;
1782
1783         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1784         if (status)
1785                 return;
1786         spin_lock(&qdev->hw_lock);
1787         if (ql_set_mac_addr_reg
1788             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1789                 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1790         }
1791         spin_unlock(&qdev->hw_lock);
1792         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1793 }
1794
1795 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1796 {
1797         struct ql_adapter *qdev = netdev_priv(ndev);
1798         u32 enable_bit = 0;
1799         int status;
1800
1801         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1802         if (status)
1803                 return;
1804
1805         spin_lock(&qdev->hw_lock);
1806         if (ql_set_mac_addr_reg
1807             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1808                 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1809         }
1810         spin_unlock(&qdev->hw_lock);
1811         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1812
1813 }
1814
1815 /* Worker thread to process a given rx_ring that is dedicated
1816  * to outbound completions.
1817  */
1818 static void ql_tx_clean(struct work_struct *work)
1819 {
1820         struct rx_ring *rx_ring =
1821             container_of(work, struct rx_ring, rx_work.work);
1822         ql_clean_outbound_rx_ring(rx_ring);
1823         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1824
1825 }
1826
1827 /* Worker thread to process a given rx_ring that is dedicated
1828  * to inbound completions.
1829  */
1830 static void ql_rx_clean(struct work_struct *work)
1831 {
1832         struct rx_ring *rx_ring =
1833             container_of(work, struct rx_ring, rx_work.work);
1834         ql_clean_inbound_rx_ring(rx_ring, 64);
1835         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1836 }
1837
1838 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1839 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1840 {
1841         struct rx_ring *rx_ring = dev_id;
1842         queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1843                               &rx_ring->rx_work, 0);
1844         return IRQ_HANDLED;
1845 }
1846
1847 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1848 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1849 {
1850         struct rx_ring *rx_ring = dev_id;
1851         napi_schedule(&rx_ring->napi);
1852         return IRQ_HANDLED;
1853 }
1854
1855 /* This handles a fatal error, MPI activity, and the default
1856  * rx_ring in an MSI-X multiple vector environment.
1857  * In MSI/Legacy environment it also process the rest of
1858  * the rx_rings.
1859  */
1860 static irqreturn_t qlge_isr(int irq, void *dev_id)
1861 {
1862         struct rx_ring *rx_ring = dev_id;
1863         struct ql_adapter *qdev = rx_ring->qdev;
1864         struct intr_context *intr_context = &qdev->intr_context[0];
1865         u32 var;
1866         int i;
1867         int work_done = 0;
1868
1869         spin_lock(&qdev->hw_lock);
1870         if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1871                 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1872                 spin_unlock(&qdev->hw_lock);
1873                 return IRQ_NONE;
1874         }
1875         spin_unlock(&qdev->hw_lock);
1876
1877         var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1878
1879         /*
1880          * Check for fatal error.
1881          */
1882         if (var & STS_FE) {
1883                 ql_queue_asic_error(qdev);
1884                 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1885                 var = ql_read32(qdev, ERR_STS);
1886                 QPRINTK(qdev, INTR, ERR,
1887                         "Resetting chip. Error Status Register = 0x%x\n", var);
1888                 return IRQ_HANDLED;
1889         }
1890
1891         /*
1892          * Check MPI processor activity.
1893          */
1894         if (var & STS_PI) {
1895                 /*
1896                  * We've got an async event or mailbox completion.
1897                  * Handle it and clear the source of the interrupt.
1898                  */
1899                 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1900                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1901                 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1902                                       &qdev->mpi_work, 0);
1903                 work_done++;
1904         }
1905
1906         /*
1907          * Check the default queue and wake handler if active.
1908          */
1909         rx_ring = &qdev->rx_ring[0];
1910         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1911                 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1912                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1913                 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1914                                       &rx_ring->rx_work, 0);
1915                 work_done++;
1916         }
1917
1918         if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1919                 /*
1920                  * Start the DPC for each active queue.
1921                  */
1922                 for (i = 1; i < qdev->rx_ring_count; i++) {
1923                         rx_ring = &qdev->rx_ring[i];
1924                         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1925                             rx_ring->cnsmr_idx) {
1926                                 QPRINTK(qdev, INTR, INFO,
1927                                         "Waking handler for rx_ring[%d].\n", i);
1928                                 ql_disable_completion_interrupt(qdev,
1929                                                                 intr_context->
1930                                                                 intr);
1931                                 if (i < qdev->rss_ring_first_cq_id)
1932                                         queue_delayed_work_on(rx_ring->cpu,
1933                                                               qdev->q_workqueue,
1934                                                               &rx_ring->rx_work,
1935                                                               0);
1936                                 else
1937                                         napi_schedule(&rx_ring->napi);
1938                                 work_done++;
1939                         }
1940                 }
1941         }
1942         ql_enable_completion_interrupt(qdev, intr_context->intr);
1943         return work_done ? IRQ_HANDLED : IRQ_NONE;
1944 }
1945
1946 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1947 {
1948
1949         if (skb_is_gso(skb)) {
1950                 int err;
1951                 if (skb_header_cloned(skb)) {
1952                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1953                         if (err)
1954                                 return err;
1955                 }
1956
1957                 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1958                 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1959                 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1960                 mac_iocb_ptr->total_hdrs_len =
1961                     cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1962                 mac_iocb_ptr->net_trans_offset =
1963                     cpu_to_le16(skb_network_offset(skb) |
1964                                 skb_transport_offset(skb)
1965                                 << OB_MAC_TRANSPORT_HDR_SHIFT);
1966                 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1967                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1968                 if (likely(skb->protocol == htons(ETH_P_IP))) {
1969                         struct iphdr *iph = ip_hdr(skb);
1970                         iph->check = 0;
1971                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1972                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1973                                                                  iph->daddr, 0,
1974                                                                  IPPROTO_TCP,
1975                                                                  0);
1976                 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1977                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
1978                         tcp_hdr(skb)->check =
1979                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1980                                              &ipv6_hdr(skb)->daddr,
1981                                              0, IPPROTO_TCP, 0);
1982                 }
1983                 return 1;
1984         }
1985         return 0;
1986 }
1987
1988 static void ql_hw_csum_setup(struct sk_buff *skb,
1989                              struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1990 {
1991         int len;
1992         struct iphdr *iph = ip_hdr(skb);
1993         __sum16 *check;
1994         mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1995         mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1996         mac_iocb_ptr->net_trans_offset =
1997                 cpu_to_le16(skb_network_offset(skb) |
1998                 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
1999
2000         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2001         len = (ntohs(iph->tot_len) - (iph->ihl << 2));
2002         if (likely(iph->protocol == IPPROTO_TCP)) {
2003                 check = &(tcp_hdr(skb)->check);
2004                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
2005                 mac_iocb_ptr->total_hdrs_len =
2006                     cpu_to_le16(skb_transport_offset(skb) +
2007                                 (tcp_hdr(skb)->doff << 2));
2008         } else {
2009                 check = &(udp_hdr(skb)->check);
2010                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
2011                 mac_iocb_ptr->total_hdrs_len =
2012                     cpu_to_le16(skb_transport_offset(skb) +
2013                                 sizeof(struct udphdr));
2014         }
2015         *check = ~csum_tcpudp_magic(iph->saddr,
2016                                     iph->daddr, len, iph->protocol, 0);
2017 }
2018
2019 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
2020 {
2021         struct tx_ring_desc *tx_ring_desc;
2022         struct ob_mac_iocb_req *mac_iocb_ptr;
2023         struct ql_adapter *qdev = netdev_priv(ndev);
2024         int tso;
2025         struct tx_ring *tx_ring;
2026         u32 tx_ring_idx = (u32) QL_TXQ_IDX(qdev, skb);
2027
2028         tx_ring = &qdev->tx_ring[tx_ring_idx];
2029
2030         if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
2031                 QPRINTK(qdev, TX_QUEUED, INFO,
2032                         "%s: shutting down tx queue %d du to lack of resources.\n",
2033                         __func__, tx_ring_idx);
2034                 netif_stop_queue(ndev);
2035                 atomic_inc(&tx_ring->queue_stopped);
2036                 return NETDEV_TX_BUSY;
2037         }
2038         tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
2039         mac_iocb_ptr = tx_ring_desc->queue_entry;
2040         memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
2041
2042         mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
2043         mac_iocb_ptr->tid = tx_ring_desc->index;
2044         /* We use the upper 32-bits to store the tx queue for this IO.
2045          * When we get the completion we can use it to establish the context.
2046          */
2047         mac_iocb_ptr->txq_idx = tx_ring_idx;
2048         tx_ring_desc->skb = skb;
2049
2050         mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
2051
2052         if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
2053                 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
2054                         vlan_tx_tag_get(skb));
2055                 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
2056                 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
2057         }
2058         tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2059         if (tso < 0) {
2060                 dev_kfree_skb_any(skb);
2061                 return NETDEV_TX_OK;
2062         } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
2063                 ql_hw_csum_setup(skb,
2064                                  (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2065         }
2066         if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
2067                         NETDEV_TX_OK) {
2068                 QPRINTK(qdev, TX_QUEUED, ERR,
2069                                 "Could not map the segments.\n");
2070                 return NETDEV_TX_BUSY;
2071         }
2072         QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
2073         tx_ring->prod_idx++;
2074         if (tx_ring->prod_idx == tx_ring->wq_len)
2075                 tx_ring->prod_idx = 0;
2076         wmb();
2077
2078         ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
2079         ndev->trans_start = jiffies;
2080         QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
2081                 tx_ring->prod_idx, skb->len);
2082
2083         atomic_dec(&tx_ring->tx_count);
2084         return NETDEV_TX_OK;
2085 }
2086
2087 static void ql_free_shadow_space(struct ql_adapter *qdev)
2088 {
2089         if (qdev->rx_ring_shadow_reg_area) {
2090                 pci_free_consistent(qdev->pdev,
2091                                     PAGE_SIZE,
2092                                     qdev->rx_ring_shadow_reg_area,
2093                                     qdev->rx_ring_shadow_reg_dma);
2094                 qdev->rx_ring_shadow_reg_area = NULL;
2095         }
2096         if (qdev->tx_ring_shadow_reg_area) {
2097                 pci_free_consistent(qdev->pdev,
2098                                     PAGE_SIZE,
2099                                     qdev->tx_ring_shadow_reg_area,
2100                                     qdev->tx_ring_shadow_reg_dma);
2101                 qdev->tx_ring_shadow_reg_area = NULL;
2102         }
2103 }
2104
2105 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2106 {
2107         qdev->rx_ring_shadow_reg_area =
2108             pci_alloc_consistent(qdev->pdev,
2109                                  PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2110         if (qdev->rx_ring_shadow_reg_area == NULL) {
2111                 QPRINTK(qdev, IFUP, ERR,
2112                         "Allocation of RX shadow space failed.\n");
2113                 return -ENOMEM;
2114         }
2115         qdev->tx_ring_shadow_reg_area =
2116             pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2117                                  &qdev->tx_ring_shadow_reg_dma);
2118         if (qdev->tx_ring_shadow_reg_area == NULL) {
2119                 QPRINTK(qdev, IFUP, ERR,
2120                         "Allocation of TX shadow space failed.\n");
2121                 goto err_wqp_sh_area;
2122         }
2123         return 0;
2124
2125 err_wqp_sh_area:
2126         pci_free_consistent(qdev->pdev,
2127                             PAGE_SIZE,
2128                             qdev->rx_ring_shadow_reg_area,
2129                             qdev->rx_ring_shadow_reg_dma);
2130         return -ENOMEM;
2131 }
2132
2133 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2134 {
2135         struct tx_ring_desc *tx_ring_desc;
2136         int i;
2137         struct ob_mac_iocb_req *mac_iocb_ptr;
2138
2139         mac_iocb_ptr = tx_ring->wq_base;
2140         tx_ring_desc = tx_ring->q;
2141         for (i = 0; i < tx_ring->wq_len; i++) {
2142                 tx_ring_desc->index = i;
2143                 tx_ring_desc->skb = NULL;
2144                 tx_ring_desc->queue_entry = mac_iocb_ptr;
2145                 mac_iocb_ptr++;
2146                 tx_ring_desc++;
2147         }
2148         atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2149         atomic_set(&tx_ring->queue_stopped, 0);
2150 }
2151
2152 static void ql_free_tx_resources(struct ql_adapter *qdev,
2153                                  struct tx_ring *tx_ring)
2154 {
2155         if (tx_ring->wq_base) {
2156                 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2157                                     tx_ring->wq_base, tx_ring->wq_base_dma);
2158                 tx_ring->wq_base = NULL;
2159         }
2160         kfree(tx_ring->q);
2161         tx_ring->q = NULL;
2162 }
2163
2164 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2165                                  struct tx_ring *tx_ring)
2166 {
2167         tx_ring->wq_base =
2168             pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2169                                  &tx_ring->wq_base_dma);
2170
2171         if ((tx_ring->wq_base == NULL)
2172             || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2173                 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2174                 return -ENOMEM;
2175         }
2176         tx_ring->q =
2177             kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2178         if (tx_ring->q == NULL)
2179                 goto err;
2180
2181         return 0;
2182 err:
2183         pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2184                             tx_ring->wq_base, tx_ring->wq_base_dma);
2185         return -ENOMEM;
2186 }
2187
2188 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2189 {
2190         int i;
2191         struct bq_desc *lbq_desc;
2192
2193         for (i = 0; i < rx_ring->lbq_len; i++) {
2194                 lbq_desc = &rx_ring->lbq[i];
2195                 if (lbq_desc->p.lbq_page) {
2196                         pci_unmap_page(qdev->pdev,
2197                                        pci_unmap_addr(lbq_desc, mapaddr),
2198                                        pci_unmap_len(lbq_desc, maplen),
2199                                        PCI_DMA_FROMDEVICE);
2200
2201                         put_page(lbq_desc->p.lbq_page);
2202                         lbq_desc->p.lbq_page = NULL;
2203                 }
2204         }
2205 }
2206
2207 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2208 {
2209         int i;
2210         struct bq_desc *sbq_desc;
2211
2212         for (i = 0; i < rx_ring->sbq_len; i++) {
2213                 sbq_desc = &rx_ring->sbq[i];
2214                 if (sbq_desc == NULL) {
2215                         QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2216                         return;
2217                 }
2218                 if (sbq_desc->p.skb) {
2219                         pci_unmap_single(qdev->pdev,
2220                                          pci_unmap_addr(sbq_desc, mapaddr),
2221                                          pci_unmap_len(sbq_desc, maplen),
2222                                          PCI_DMA_FROMDEVICE);
2223                         dev_kfree_skb(sbq_desc->p.skb);
2224                         sbq_desc->p.skb = NULL;
2225                 }
2226         }
2227 }
2228
2229 /* Free all large and small rx buffers associated
2230  * with the completion queues for this device.
2231  */
2232 static void ql_free_rx_buffers(struct ql_adapter *qdev)
2233 {
2234         int i;
2235         struct rx_ring *rx_ring;
2236
2237         for (i = 0; i < qdev->rx_ring_count; i++) {
2238                 rx_ring = &qdev->rx_ring[i];
2239                 if (rx_ring->lbq)
2240                         ql_free_lbq_buffers(qdev, rx_ring);
2241                 if (rx_ring->sbq)
2242                         ql_free_sbq_buffers(qdev, rx_ring);
2243         }
2244 }
2245
2246 static void ql_alloc_rx_buffers(struct ql_adapter *qdev)
2247 {
2248         struct rx_ring *rx_ring;
2249         int i;
2250
2251         for (i = 0; i < qdev->rx_ring_count; i++) {
2252                 rx_ring = &qdev->rx_ring[i];
2253                 if (rx_ring->type != TX_Q)
2254                         ql_update_buffer_queues(qdev, rx_ring);
2255         }
2256 }
2257
2258 static void ql_init_lbq_ring(struct ql_adapter *qdev,
2259                                 struct rx_ring *rx_ring)
2260 {
2261         int i;
2262         struct bq_desc *lbq_desc;
2263         __le64 *bq = rx_ring->lbq_base;
2264
2265         memset(rx_ring->lbq, 0, rx_ring->lbq_len * sizeof(struct bq_desc));
2266         for (i = 0; i < rx_ring->lbq_len; i++) {
2267                 lbq_desc = &rx_ring->lbq[i];
2268                 memset(lbq_desc, 0, sizeof(*lbq_desc));
2269                 lbq_desc->index = i;
2270                 lbq_desc->addr = bq;
2271                 bq++;
2272         }
2273 }
2274
2275 static void ql_init_sbq_ring(struct ql_adapter *qdev,
2276                                 struct rx_ring *rx_ring)
2277 {
2278         int i;
2279         struct bq_desc *sbq_desc;
2280         __le64 *bq = rx_ring->sbq_base;
2281
2282         memset(rx_ring->sbq, 0, rx_ring->sbq_len * sizeof(struct bq_desc));
2283         for (i = 0; i < rx_ring->sbq_len; i++) {
2284                 sbq_desc = &rx_ring->sbq[i];
2285                 memset(sbq_desc, 0, sizeof(*sbq_desc));
2286                 sbq_desc->index = i;
2287                 sbq_desc->addr = bq;
2288                 bq++;
2289         }
2290 }
2291
2292 static void ql_free_rx_resources(struct ql_adapter *qdev,
2293                                  struct rx_ring *rx_ring)
2294 {
2295         /* Free the small buffer queue. */
2296         if (rx_ring->sbq_base) {
2297                 pci_free_consistent(qdev->pdev,
2298                                     rx_ring->sbq_size,
2299                                     rx_ring->sbq_base, rx_ring->sbq_base_dma);
2300                 rx_ring->sbq_base = NULL;
2301         }
2302
2303         /* Free the small buffer queue control blocks. */
2304         kfree(rx_ring->sbq);
2305         rx_ring->sbq = NULL;
2306
2307         /* Free the large buffer queue. */
2308         if (rx_ring->lbq_base) {
2309                 pci_free_consistent(qdev->pdev,
2310                                     rx_ring->lbq_size,
2311                                     rx_ring->lbq_base, rx_ring->lbq_base_dma);
2312                 rx_ring->lbq_base = NULL;
2313         }
2314
2315         /* Free the large buffer queue control blocks. */
2316         kfree(rx_ring->lbq);
2317         rx_ring->lbq = NULL;
2318
2319         /* Free the rx queue. */
2320         if (rx_ring->cq_base) {
2321                 pci_free_consistent(qdev->pdev,
2322                                     rx_ring->cq_size,
2323                                     rx_ring->cq_base, rx_ring->cq_base_dma);
2324                 rx_ring->cq_base = NULL;
2325         }
2326 }
2327
2328 /* Allocate queues and buffers for this completions queue based
2329  * on the values in the parameter structure. */
2330 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2331                                  struct rx_ring *rx_ring)
2332 {
2333
2334         /*
2335          * Allocate the completion queue for this rx_ring.
2336          */
2337         rx_ring->cq_base =
2338             pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2339                                  &rx_ring->cq_base_dma);
2340
2341         if (rx_ring->cq_base == NULL) {
2342                 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2343                 return -ENOMEM;
2344         }
2345
2346         if (rx_ring->sbq_len) {
2347                 /*
2348                  * Allocate small buffer queue.
2349                  */
2350                 rx_ring->sbq_base =
2351                     pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2352                                          &rx_ring->sbq_base_dma);
2353
2354                 if (rx_ring->sbq_base == NULL) {
2355                         QPRINTK(qdev, IFUP, ERR,
2356                                 "Small buffer queue allocation failed.\n");
2357                         goto err_mem;
2358                 }
2359
2360                 /*
2361                  * Allocate small buffer queue control blocks.
2362                  */
2363                 rx_ring->sbq =
2364                     kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2365                             GFP_KERNEL);
2366                 if (rx_ring->sbq == NULL) {
2367                         QPRINTK(qdev, IFUP, ERR,
2368                                 "Small buffer queue control block allocation failed.\n");
2369                         goto err_mem;
2370                 }
2371
2372                 ql_init_sbq_ring(qdev, rx_ring);
2373         }
2374
2375         if (rx_ring->lbq_len) {
2376                 /*
2377                  * Allocate large buffer queue.
2378                  */
2379                 rx_ring->lbq_base =
2380                     pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2381                                          &rx_ring->lbq_base_dma);
2382
2383                 if (rx_ring->lbq_base == NULL) {
2384                         QPRINTK(qdev, IFUP, ERR,
2385                                 "Large buffer queue allocation failed.\n");
2386                         goto err_mem;
2387                 }
2388                 /*
2389                  * Allocate large buffer queue control blocks.
2390                  */
2391                 rx_ring->lbq =
2392                     kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2393                             GFP_KERNEL);
2394                 if (rx_ring->lbq == NULL) {
2395                         QPRINTK(qdev, IFUP, ERR,
2396                                 "Large buffer queue control block allocation failed.\n");
2397                         goto err_mem;
2398                 }
2399
2400                 ql_init_lbq_ring(qdev, rx_ring);
2401         }
2402
2403         return 0;
2404
2405 err_mem:
2406         ql_free_rx_resources(qdev, rx_ring);
2407         return -ENOMEM;
2408 }
2409
2410 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2411 {
2412         struct tx_ring *tx_ring;
2413         struct tx_ring_desc *tx_ring_desc;
2414         int i, j;
2415
2416         /*
2417          * Loop through all queues and free
2418          * any resources.
2419          */
2420         for (j = 0; j < qdev->tx_ring_count; j++) {
2421                 tx_ring = &qdev->tx_ring[j];
2422                 for (i = 0; i < tx_ring->wq_len; i++) {
2423                         tx_ring_desc = &tx_ring->q[i];
2424                         if (tx_ring_desc && tx_ring_desc->skb) {
2425                                 QPRINTK(qdev, IFDOWN, ERR,
2426                                 "Freeing lost SKB %p, from queue %d, index %d.\n",
2427                                         tx_ring_desc->skb, j,
2428                                         tx_ring_desc->index);
2429                                 ql_unmap_send(qdev, tx_ring_desc,
2430                                               tx_ring_desc->map_cnt);
2431                                 dev_kfree_skb(tx_ring_desc->skb);
2432                                 tx_ring_desc->skb = NULL;
2433                         }
2434                 }
2435         }
2436 }
2437
2438 static void ql_free_mem_resources(struct ql_adapter *qdev)
2439 {
2440         int i;
2441
2442         for (i = 0; i < qdev->tx_ring_count; i++)
2443                 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2444         for (i = 0; i < qdev->rx_ring_count; i++)
2445                 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2446         ql_free_shadow_space(qdev);
2447 }
2448
2449 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2450 {
2451         int i;
2452
2453         /* Allocate space for our shadow registers and such. */
2454         if (ql_alloc_shadow_space(qdev))
2455                 return -ENOMEM;
2456
2457         for (i = 0; i < qdev->rx_ring_count; i++) {
2458                 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2459                         QPRINTK(qdev, IFUP, ERR,
2460                                 "RX resource allocation failed.\n");
2461                         goto err_mem;
2462                 }
2463         }
2464         /* Allocate tx queue resources */
2465         for (i = 0; i < qdev->tx_ring_count; i++) {
2466                 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2467                         QPRINTK(qdev, IFUP, ERR,
2468                                 "TX resource allocation failed.\n");
2469                         goto err_mem;
2470                 }
2471         }
2472         return 0;
2473
2474 err_mem:
2475         ql_free_mem_resources(qdev);
2476         return -ENOMEM;
2477 }
2478
2479 /* Set up the rx ring control block and pass it to the chip.
2480  * The control block is defined as
2481  * "Completion Queue Initialization Control Block", or cqicb.
2482  */
2483 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2484 {
2485         struct cqicb *cqicb = &rx_ring->cqicb;
2486         void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2487             (rx_ring->cq_id * sizeof(u64) * 4);
2488         u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2489             (rx_ring->cq_id * sizeof(u64) * 4);
2490         void __iomem *doorbell_area =
2491             qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2492         int err = 0;
2493         u16 bq_len;
2494
2495         /* Set up the shadow registers for this ring. */
2496         rx_ring->prod_idx_sh_reg = shadow_reg;
2497         rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2498         shadow_reg += sizeof(u64);
2499         shadow_reg_dma += sizeof(u64);
2500         rx_ring->lbq_base_indirect = shadow_reg;
2501         rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2502         shadow_reg += sizeof(u64);
2503         shadow_reg_dma += sizeof(u64);
2504         rx_ring->sbq_base_indirect = shadow_reg;
2505         rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2506
2507         /* PCI doorbell mem area + 0x00 for consumer index register */
2508         rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2509         rx_ring->cnsmr_idx = 0;
2510         rx_ring->curr_entry = rx_ring->cq_base;
2511
2512         /* PCI doorbell mem area + 0x04 for valid register */
2513         rx_ring->valid_db_reg = doorbell_area + 0x04;
2514
2515         /* PCI doorbell mem area + 0x18 for large buffer consumer */
2516         rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2517
2518         /* PCI doorbell mem area + 0x1c */
2519         rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2520
2521         memset((void *)cqicb, 0, sizeof(struct cqicb));
2522         cqicb->msix_vect = rx_ring->irq;
2523
2524         bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2525         cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
2526
2527         cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
2528
2529         cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
2530
2531         /*
2532          * Set up the control block load flags.
2533          */
2534         cqicb->flags = FLAGS_LC |       /* Load queue base address */
2535             FLAGS_LV |          /* Load MSI-X vector */
2536             FLAGS_LI;           /* Load irq delay values */
2537         if (rx_ring->lbq_len) {
2538                 cqicb->flags |= FLAGS_LL;       /* Load lbq values */
2539                 *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma;
2540                 cqicb->lbq_addr =
2541                     cpu_to_le64(rx_ring->lbq_base_indirect_dma);
2542                 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2543                         (u16) rx_ring->lbq_buf_size;
2544                 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2545                 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2546                         (u16) rx_ring->lbq_len;
2547                 cqicb->lbq_len = cpu_to_le16(bq_len);
2548                 rx_ring->lbq_prod_idx = 0;
2549                 rx_ring->lbq_curr_idx = 0;
2550                 rx_ring->lbq_clean_idx = 0;
2551                 rx_ring->lbq_free_cnt = rx_ring->lbq_len;
2552         }
2553         if (rx_ring->sbq_len) {
2554                 cqicb->flags |= FLAGS_LS;       /* Load sbq values */
2555                 *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma;
2556                 cqicb->sbq_addr =
2557                     cpu_to_le64(rx_ring->sbq_base_indirect_dma);
2558                 cqicb->sbq_buf_size =
2559                     cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
2560                 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2561                         (u16) rx_ring->sbq_len;
2562                 cqicb->sbq_len = cpu_to_le16(bq_len);
2563                 rx_ring->sbq_prod_idx = 0;
2564                 rx_ring->sbq_curr_idx = 0;
2565                 rx_ring->sbq_clean_idx = 0;
2566                 rx_ring->sbq_free_cnt = rx_ring->sbq_len;
2567         }
2568         switch (rx_ring->type) {
2569         case TX_Q:
2570                 /* If there's only one interrupt, then we use
2571                  * worker threads to process the outbound
2572                  * completion handling rx_rings. We do this so
2573                  * they can be run on multiple CPUs. There is
2574                  * room to play with this more where we would only
2575                  * run in a worker if there are more than x number
2576                  * of outbound completions on the queue and more
2577                  * than one queue active.  Some threshold that
2578                  * would indicate a benefit in spite of the cost
2579                  * of a context switch.
2580                  * If there's more than one interrupt, then the
2581                  * outbound completions are processed in the ISR.
2582                  */
2583                 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2584                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2585                 else {
2586                         /* With all debug warnings on we see a WARN_ON message
2587                          * when we free the skb in the interrupt context.
2588                          */
2589                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2590                 }
2591                 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2592                 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2593                 break;
2594         case DEFAULT_Q:
2595                 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2596                 cqicb->irq_delay = 0;
2597                 cqicb->pkt_delay = 0;
2598                 break;
2599         case RX_Q:
2600                 /* Inbound completion handling rx_rings run in
2601                  * separate NAPI contexts.
2602                  */
2603                 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2604                                64);
2605                 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2606                 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2607                 break;
2608         default:
2609                 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2610                         rx_ring->type);
2611         }
2612         QPRINTK(qdev, IFUP, DEBUG, "Initializing rx work queue.\n");
2613         err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2614                            CFG_LCQ, rx_ring->cq_id);
2615         if (err) {
2616                 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2617                 return err;
2618         }
2619         return err;
2620 }
2621
2622 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2623 {
2624         struct wqicb *wqicb = (struct wqicb *)tx_ring;
2625         void __iomem *doorbell_area =
2626             qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2627         void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2628             (tx_ring->wq_id * sizeof(u64));
2629         u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2630             (tx_ring->wq_id * sizeof(u64));
2631         int err = 0;
2632
2633         /*
2634          * Assign doorbell registers for this tx_ring.
2635          */
2636         /* TX PCI doorbell mem area for tx producer index */
2637         tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2638         tx_ring->prod_idx = 0;
2639         /* TX PCI doorbell mem area + 0x04 */
2640         tx_ring->valid_db_reg = doorbell_area + 0x04;
2641
2642         /*
2643          * Assign shadow registers for this tx_ring.
2644          */
2645         tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2646         tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2647
2648         wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2649         wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2650                                    Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2651         wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2652         wqicb->rid = 0;
2653         wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
2654
2655         wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
2656
2657         ql_init_tx_ring(qdev, tx_ring);
2658
2659         err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2660                            (u16) tx_ring->wq_id);
2661         if (err) {
2662                 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2663                 return err;
2664         }
2665         QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded WQICB.\n");
2666         return err;
2667 }
2668
2669 static void ql_disable_msix(struct ql_adapter *qdev)
2670 {
2671         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2672                 pci_disable_msix(qdev->pdev);
2673                 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2674                 kfree(qdev->msi_x_entry);
2675                 qdev->msi_x_entry = NULL;
2676         } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2677                 pci_disable_msi(qdev->pdev);
2678                 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2679         }
2680 }
2681
2682 static void ql_enable_msix(struct ql_adapter *qdev)
2683 {
2684         int i;
2685
2686         qdev->intr_count = 1;
2687         /* Get the MSIX vectors. */
2688         if (irq_type == MSIX_IRQ) {
2689                 /* Try to alloc space for the msix struct,
2690                  * if it fails then go to MSI/legacy.
2691                  */
2692                 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2693                                             sizeof(struct msix_entry),
2694                                             GFP_KERNEL);
2695                 if (!qdev->msi_x_entry) {
2696                         irq_type = MSI_IRQ;
2697                         goto msi;
2698                 }
2699
2700                 for (i = 0; i < qdev->rx_ring_count; i++)
2701                         qdev->msi_x_entry[i].entry = i;
2702
2703                 if (!pci_enable_msix
2704                     (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2705                         set_bit(QL_MSIX_ENABLED, &qdev->flags);
2706                         qdev->intr_count = qdev->rx_ring_count;
2707                         QPRINTK(qdev, IFUP, DEBUG,
2708                                 "MSI-X Enabled, got %d vectors.\n",
2709                                 qdev->intr_count);
2710                         return;
2711                 } else {
2712                         kfree(qdev->msi_x_entry);
2713                         qdev->msi_x_entry = NULL;
2714                         QPRINTK(qdev, IFUP, WARNING,
2715                                 "MSI-X Enable failed, trying MSI.\n");
2716                         irq_type = MSI_IRQ;
2717                 }
2718         }
2719 msi:
2720         if (irq_type == MSI_IRQ) {
2721                 if (!pci_enable_msi(qdev->pdev)) {
2722                         set_bit(QL_MSI_ENABLED, &qdev->flags);
2723                         QPRINTK(qdev, IFUP, INFO,
2724                                 "Running with MSI interrupts.\n");
2725                         return;
2726                 }
2727         }
2728         irq_type = LEG_IRQ;
2729         QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2730 }
2731
2732 /*
2733  * Here we build the intr_context structures based on
2734  * our rx_ring count and intr vector count.
2735  * The intr_context structure is used to hook each vector
2736  * to possibly different handlers.
2737  */
2738 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2739 {
2740         int i = 0;
2741         struct intr_context *intr_context = &qdev->intr_context[0];
2742
2743         ql_enable_msix(qdev);
2744
2745         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2746                 /* Each rx_ring has it's
2747                  * own intr_context since we have separate
2748                  * vectors for each queue.
2749                  * This only true when MSI-X is enabled.
2750                  */
2751                 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2752                         qdev->rx_ring[i].irq = i;
2753                         intr_context->intr = i;
2754                         intr_context->qdev = qdev;
2755                         /*
2756                          * We set up each vectors enable/disable/read bits so
2757                          * there's no bit/mask calculations in the critical path.
2758                          */
2759                         intr_context->intr_en_mask =
2760                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2761                             INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2762                             | i;
2763                         intr_context->intr_dis_mask =
2764                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2765                             INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2766                             INTR_EN_IHD | i;
2767                         intr_context->intr_read_mask =
2768                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2769                             INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2770                             i;
2771
2772                         if (i == 0) {
2773                                 /*
2774                                  * Default queue handles bcast/mcast plus
2775                                  * async events.  Needs buffers.
2776                                  */
2777                                 intr_context->handler = qlge_isr;
2778                                 sprintf(intr_context->name, "%s-default-queue",
2779                                         qdev->ndev->name);
2780                         } else if (i < qdev->rss_ring_first_cq_id) {
2781                                 /*
2782                                  * Outbound queue is for outbound completions only.
2783                                  */
2784                                 intr_context->handler = qlge_msix_tx_isr;
2785                                 sprintf(intr_context->name, "%s-tx-%d",
2786                                         qdev->ndev->name, i);
2787                         } else {
2788                                 /*
2789                                  * Inbound queues handle unicast frames only.
2790                                  */
2791                                 intr_context->handler = qlge_msix_rx_isr;
2792                                 sprintf(intr_context->name, "%s-rx-%d",
2793                                         qdev->ndev->name, i);
2794                         }
2795                 }
2796         } else {
2797                 /*
2798                  * All rx_rings use the same intr_context since
2799                  * there is only one vector.
2800                  */
2801                 intr_context->intr = 0;
2802                 intr_context->qdev = qdev;
2803                 /*
2804                  * We set up each vectors enable/disable/read bits so
2805                  * there's no bit/mask calculations in the critical path.
2806                  */
2807                 intr_context->intr_en_mask =
2808                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2809                 intr_context->intr_dis_mask =
2810                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2811                     INTR_EN_TYPE_DISABLE;
2812                 intr_context->intr_read_mask =
2813                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2814                 /*
2815                  * Single interrupt means one handler for all rings.
2816                  */
2817                 intr_context->handler = qlge_isr;
2818                 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2819                 for (i = 0; i < qdev->rx_ring_count; i++)
2820                         qdev->rx_ring[i].irq = 0;
2821         }
2822 }
2823
2824 static void ql_free_irq(struct ql_adapter *qdev)
2825 {
2826         int i;
2827         struct intr_context *intr_context = &qdev->intr_context[0];
2828
2829         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2830                 if (intr_context->hooked) {
2831                         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2832                                 free_irq(qdev->msi_x_entry[i].vector,
2833                                          &qdev->rx_ring[i]);
2834                                 QPRINTK(qdev, IFDOWN, DEBUG,
2835                                         "freeing msix interrupt %d.\n", i);
2836                         } else {
2837                                 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2838                                 QPRINTK(qdev, IFDOWN, DEBUG,
2839                                         "freeing msi interrupt %d.\n", i);
2840                         }
2841                 }
2842         }
2843         ql_disable_msix(qdev);
2844 }
2845
2846 static int ql_request_irq(struct ql_adapter *qdev)
2847 {
2848         int i;
2849         int status = 0;
2850         struct pci_dev *pdev = qdev->pdev;
2851         struct intr_context *intr_context = &qdev->intr_context[0];
2852
2853         ql_resolve_queues_to_irqs(qdev);
2854
2855         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2856                 atomic_set(&intr_context->irq_cnt, 0);
2857                 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2858                         status = request_irq(qdev->msi_x_entry[i].vector,
2859                                              intr_context->handler,
2860                                              0,
2861                                              intr_context->name,
2862                                              &qdev->rx_ring[i]);
2863                         if (status) {
2864                                 QPRINTK(qdev, IFUP, ERR,
2865                                         "Failed request for MSIX interrupt %d.\n",
2866                                         i);
2867                                 goto err_irq;
2868                         } else {
2869                                 QPRINTK(qdev, IFUP, DEBUG,
2870                                         "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2871                                         i,
2872                                         qdev->rx_ring[i].type ==
2873                                         DEFAULT_Q ? "DEFAULT_Q" : "",
2874                                         qdev->rx_ring[i].type ==
2875                                         TX_Q ? "TX_Q" : "",
2876                                         qdev->rx_ring[i].type ==
2877                                         RX_Q ? "RX_Q" : "", intr_context->name);
2878                         }
2879                 } else {
2880                         QPRINTK(qdev, IFUP, DEBUG,
2881                                 "trying msi or legacy interrupts.\n");
2882                         QPRINTK(qdev, IFUP, DEBUG,
2883                                 "%s: irq = %d.\n", __func__, pdev->irq);
2884                         QPRINTK(qdev, IFUP, DEBUG,
2885                                 "%s: context->name = %s.\n", __func__,
2886                                intr_context->name);
2887                         QPRINTK(qdev, IFUP, DEBUG,
2888                                 "%s: dev_id = 0x%p.\n", __func__,
2889                                &qdev->rx_ring[0]);
2890                         status =
2891                             request_irq(pdev->irq, qlge_isr,
2892                                         test_bit(QL_MSI_ENABLED,
2893                                                  &qdev->
2894                                                  flags) ? 0 : IRQF_SHARED,
2895                                         intr_context->name, &qdev->rx_ring[0]);
2896                         if (status)
2897                                 goto err_irq;
2898
2899                         QPRINTK(qdev, IFUP, ERR,
2900                                 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2901                                 i,
2902                                 qdev->rx_ring[0].type ==
2903                                 DEFAULT_Q ? "DEFAULT_Q" : "",
2904                                 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2905                                 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2906                                 intr_context->name);
2907                 }
2908                 intr_context->hooked = 1;
2909         }
2910         return status;
2911 err_irq:
2912         QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2913         ql_free_irq(qdev);
2914         return status;
2915 }
2916
2917 static int ql_start_rss(struct ql_adapter *qdev)
2918 {
2919         struct ricb *ricb = &qdev->ricb;
2920         int status = 0;
2921         int i;
2922         u8 *hash_id = (u8 *) ricb->hash_cq_id;
2923
2924         memset((void *)ricb, 0, sizeof(ricb));
2925
2926         ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2927         ricb->flags =
2928             (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2929              RSS_RT6);
2930         ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2931
2932         /*
2933          * Fill out the Indirection Table.
2934          */
2935         for (i = 0; i < 256; i++)
2936                 hash_id[i] = i & (qdev->rss_ring_count - 1);
2937
2938         /*
2939          * Random values for the IPv6 and IPv4 Hash Keys.
2940          */
2941         get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2942         get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2943
2944         QPRINTK(qdev, IFUP, DEBUG, "Initializing RSS.\n");
2945
2946         status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2947         if (status) {
2948                 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2949                 return status;
2950         }
2951         QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded RICB.\n");
2952         return status;
2953 }
2954
2955 /* Initialize the frame-to-queue routing. */
2956 static int ql_route_initialize(struct ql_adapter *qdev)
2957 {
2958         int status = 0;
2959         int i;
2960
2961         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
2962         if (status)
2963                 return status;
2964
2965         /* Clear all the entries in the routing table. */
2966         for (i = 0; i < 16; i++) {
2967                 status = ql_set_routing_reg(qdev, i, 0, 0);
2968                 if (status) {
2969                         QPRINTK(qdev, IFUP, ERR,
2970                                 "Failed to init routing register for CAM packets.\n");
2971                         goto exit;
2972                 }
2973         }
2974
2975         status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
2976         if (status) {
2977                 QPRINTK(qdev, IFUP, ERR,
2978                         "Failed to init routing register for error packets.\n");
2979                 goto exit;
2980         }
2981         status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
2982         if (status) {
2983                 QPRINTK(qdev, IFUP, ERR,
2984                         "Failed to init routing register for broadcast packets.\n");
2985                 goto exit;
2986         }
2987         /* If we have more than one inbound queue, then turn on RSS in the
2988          * routing block.
2989          */
2990         if (qdev->rss_ring_count > 1) {
2991                 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
2992                                         RT_IDX_RSS_MATCH, 1);
2993                 if (status) {
2994                         QPRINTK(qdev, IFUP, ERR,
2995                                 "Failed to init routing register for MATCH RSS packets.\n");
2996                         goto exit;
2997                 }
2998         }
2999
3000         status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
3001                                     RT_IDX_CAM_HIT, 1);
3002         if (status)
3003                 QPRINTK(qdev, IFUP, ERR,
3004                         "Failed to init routing register for CAM packets.\n");
3005 exit:
3006         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3007         return status;
3008 }
3009
3010 static int ql_cam_route_initialize(struct ql_adapter *qdev)
3011 {
3012         int status;
3013
3014         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3015         if (status)
3016                 return status;
3017         status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3018                              MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3019         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3020         if (status) {
3021                 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3022                 return status;
3023         }
3024
3025         status = ql_route_initialize(qdev);
3026         if (status)
3027                 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3028
3029         return status;
3030 }
3031
3032 static int ql_adapter_initialize(struct ql_adapter *qdev)
3033 {
3034         u32 value, mask;
3035         int i;
3036         int status = 0;
3037
3038         /*
3039          * Set up the System register to halt on errors.
3040          */
3041         value = SYS_EFE | SYS_FAE;
3042         mask = value << 16;
3043         ql_write32(qdev, SYS, mask | value);
3044
3045         /* Set the default queue. */
3046         value = NIC_RCV_CFG_DFQ;
3047         mask = NIC_RCV_CFG_DFQ_MASK;
3048         ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3049
3050         /* Set the MPI interrupt to enabled. */
3051         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3052
3053         /* Enable the function, set pagesize, enable error checking. */
3054         value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3055             FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
3056
3057         /* Set/clear header splitting. */
3058         mask = FSC_VM_PAGESIZE_MASK |
3059             FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3060         ql_write32(qdev, FSC, mask | value);
3061
3062         ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3063                 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3064
3065         /* Start up the rx queues. */
3066         for (i = 0; i < qdev->rx_ring_count; i++) {
3067                 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3068                 if (status) {
3069                         QPRINTK(qdev, IFUP, ERR,
3070                                 "Failed to start rx ring[%d].\n", i);
3071                         return status;
3072                 }
3073         }
3074
3075         /* If there is more than one inbound completion queue
3076          * then download a RICB to configure RSS.
3077          */
3078         if (qdev->rss_ring_count > 1) {
3079                 status = ql_start_rss(qdev);
3080                 if (status) {
3081                         QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3082                         return status;
3083                 }
3084         }
3085
3086         /* Start up the tx queues. */
3087         for (i = 0; i < qdev->tx_ring_count; i++) {
3088                 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3089                 if (status) {
3090                         QPRINTK(qdev, IFUP, ERR,
3091                                 "Failed to start tx ring[%d].\n", i);
3092                         return status;
3093                 }
3094         }
3095
3096         /* Initialize the port and set the max framesize. */
3097         status = qdev->nic_ops->port_initialize(qdev);
3098        if (status) {
3099               QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3100               return status;
3101        }
3102
3103         /* Set up the MAC address and frame routing filter. */
3104         status = ql_cam_route_initialize(qdev);
3105         if (status) {
3106                 QPRINTK(qdev, IFUP, ERR,
3107                                 "Failed to init CAM/Routing tables.\n");
3108                 return status;
3109         }
3110
3111         /* Start NAPI for the RSS queues. */
3112         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3113                 QPRINTK(qdev, IFUP, DEBUG, "Enabling NAPI for rx_ring[%d].\n",
3114                         i);
3115                 napi_enable(&qdev->rx_ring[i].napi);
3116         }
3117
3118         return status;
3119 }
3120
3121 /* Issue soft reset to chip. */
3122 static int ql_adapter_reset(struct ql_adapter *qdev)
3123 {
3124         u32 value;
3125         int max_wait_time;
3126         int status = 0;
3127         int resetCnt = 0;
3128
3129 #define MAX_RESET_CNT   1
3130 issueReset:
3131         resetCnt++;
3132         QPRINTK(qdev, IFDOWN, DEBUG, "Issue soft reset to chip.\n");
3133         ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3134         /* Wait for reset to complete. */
3135         max_wait_time = 3;
3136         QPRINTK(qdev, IFDOWN, DEBUG, "Wait %d seconds for reset to complete.\n",
3137                 max_wait_time);
3138         do {
3139                 value = ql_read32(qdev, RST_FO);
3140                 if ((value & RST_FO_FR) == 0)
3141                         break;
3142
3143                 ssleep(1);
3144         } while ((--max_wait_time));
3145         if (value & RST_FO_FR) {
3146                 QPRINTK(qdev, IFDOWN, ERR,
3147                         "Stuck in SoftReset:  FSC_SR:0x%08x\n", value);
3148                 if (resetCnt < MAX_RESET_CNT)
3149                         goto issueReset;
3150         }
3151         if (max_wait_time == 0) {
3152                 status = -ETIMEDOUT;
3153                 QPRINTK(qdev, IFDOWN, ERR,
3154                         "ETIMEOUT!!! errored out of resetting the chip!\n");
3155         }
3156
3157         return status;
3158 }
3159
3160 static void ql_display_dev_info(struct net_device *ndev)
3161 {
3162         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3163
3164         QPRINTK(qdev, PROBE, INFO,
3165                 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3166                 "XG Roll = %d, XG Rev = %d.\n",
3167                 qdev->func,
3168                 qdev->chip_rev_id & 0x0000000f,
3169                 qdev->chip_rev_id >> 4 & 0x0000000f,
3170                 qdev->chip_rev_id >> 8 & 0x0000000f,
3171                 qdev->chip_rev_id >> 12 & 0x0000000f);
3172         QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3173 }
3174
3175 static int ql_adapter_down(struct ql_adapter *qdev)
3176 {
3177         struct net_device *ndev = qdev->ndev;
3178         int i, status = 0;
3179         struct rx_ring *rx_ring;
3180
3181         netif_stop_queue(ndev);
3182         netif_carrier_off(ndev);
3183
3184         /* Don't kill the reset worker thread if we
3185          * are in the process of recovery.
3186          */
3187         if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3188                 cancel_delayed_work_sync(&qdev->asic_reset_work);
3189         cancel_delayed_work_sync(&qdev->mpi_reset_work);
3190         cancel_delayed_work_sync(&qdev->mpi_work);
3191
3192         /* The default queue at index 0 is always processed in
3193          * a workqueue.
3194          */
3195         cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3196
3197         /* The rest of the rx_rings are processed in
3198          * a workqueue only if it's a single interrupt
3199          * environment (MSI/Legacy).
3200          */
3201         for (i = 1; i < qdev->rx_ring_count; i++) {
3202                 rx_ring = &qdev->rx_ring[i];
3203                 /* Only the RSS rings use NAPI on multi irq
3204                  * environment.  Outbound completion processing
3205                  * is done in interrupt context.
3206                  */
3207                 if (i >= qdev->rss_ring_first_cq_id) {
3208                         napi_disable(&rx_ring->napi);
3209                 } else {
3210                         cancel_delayed_work_sync(&rx_ring->rx_work);
3211                 }
3212         }
3213
3214         clear_bit(QL_ADAPTER_UP, &qdev->flags);
3215
3216         ql_disable_interrupts(qdev);
3217
3218         ql_tx_ring_clean(qdev);
3219
3220         ql_free_rx_buffers(qdev);
3221         spin_lock(&qdev->hw_lock);
3222         status = ql_adapter_reset(qdev);
3223         if (status)
3224                 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3225                         qdev->func);
3226         spin_unlock(&qdev->hw_lock);
3227         return status;
3228 }
3229
3230 static int ql_adapter_up(struct ql_adapter *qdev)
3231 {
3232         int err = 0;
3233
3234         spin_lock(&qdev->hw_lock);
3235         err = ql_adapter_initialize(qdev);
3236         if (err) {
3237                 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3238                 spin_unlock(&qdev->hw_lock);
3239                 goto err_init;
3240         }
3241         spin_unlock(&qdev->hw_lock);
3242         set_bit(QL_ADAPTER_UP, &qdev->flags);
3243         ql_alloc_rx_buffers(qdev);
3244         ql_enable_interrupts(qdev);
3245         ql_enable_all_completion_interrupts(qdev);
3246         if ((ql_read32(qdev, STS) & qdev->port_init)) {
3247                 netif_carrier_on(qdev->ndev);
3248                 netif_start_queue(qdev->ndev);
3249         }
3250
3251         return 0;
3252 err_init:
3253         ql_adapter_reset(qdev);
3254         return err;
3255 }
3256
3257 static int ql_cycle_adapter(struct ql_adapter *qdev)
3258 {
3259         int status;
3260
3261         status = ql_adapter_down(qdev);
3262         if (status)
3263                 goto error;
3264
3265         status = ql_adapter_up(qdev);
3266         if (status)
3267                 goto error;
3268
3269         return status;
3270 error:
3271         QPRINTK(qdev, IFUP, ALERT,
3272                 "Driver up/down cycle failed, closing device\n");
3273         rtnl_lock();
3274         dev_close(qdev->ndev);
3275         rtnl_unlock();
3276         return status;
3277 }
3278
3279 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3280 {
3281         ql_free_mem_resources(qdev);
3282         ql_free_irq(qdev);
3283 }
3284
3285 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3286 {
3287         int status = 0;
3288
3289         if (ql_alloc_mem_resources(qdev)) {
3290                 QPRINTK(qdev, IFUP, ERR, "Unable to  allocate memory.\n");
3291                 return -ENOMEM;
3292         }
3293         status = ql_request_irq(qdev);
3294         if (status)
3295                 goto err_irq;
3296         return status;
3297 err_irq:
3298         ql_free_mem_resources(qdev);
3299         return status;
3300 }
3301
3302 static int qlge_close(struct net_device *ndev)
3303 {
3304         struct ql_adapter *qdev = netdev_priv(ndev);
3305
3306         /*
3307          * Wait for device to recover from a reset.
3308          * (Rarely happens, but possible.)
3309          */
3310         while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3311                 msleep(1);
3312         ql_adapter_down(qdev);
3313         ql_release_adapter_resources(qdev);
3314         return 0;
3315 }
3316
3317 static int ql_configure_rings(struct ql_adapter *qdev)
3318 {
3319         int i;
3320         struct rx_ring *rx_ring;
3321         struct tx_ring *tx_ring;
3322         int cpu_cnt = num_online_cpus();
3323
3324         /*
3325          * For each processor present we allocate one
3326          * rx_ring for outbound completions, and one
3327          * rx_ring for inbound completions.  Plus there is
3328          * always the one default queue.  For the CPU
3329          * counts we end up with the following rx_rings:
3330          * rx_ring count =
3331          *  one default queue +
3332          *  (CPU count * outbound completion rx_ring) +
3333          *  (CPU count * inbound (RSS) completion rx_ring)
3334          * To keep it simple we limit the total number of
3335          * queues to < 32, so we truncate CPU to 8.
3336          * This limitation can be removed when requested.
3337          */
3338
3339         if (cpu_cnt > MAX_CPUS)
3340                 cpu_cnt = MAX_CPUS;
3341
3342         /*
3343          * rx_ring[0] is always the default queue.
3344          */
3345         /* Allocate outbound completion ring for each CPU. */
3346         qdev->tx_ring_count = cpu_cnt;
3347         /* Allocate inbound completion (RSS) ring for each CPU. */
3348         qdev->rss_ring_count = cpu_cnt;
3349         /* cq_id for the first inbound ring handler. */
3350         qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3351         /*
3352          * qdev->rx_ring_count:
3353          * Total number of rx_rings.  This includes the one
3354          * default queue, a number of outbound completion
3355          * handler rx_rings, and the number of inbound
3356          * completion handler rx_rings.
3357          */
3358         qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3359
3360         for (i = 0; i < qdev->tx_ring_count; i++) {
3361                 tx_ring = &qdev->tx_ring[i];
3362                 memset((void *)tx_ring, 0, sizeof(tx_ring));
3363                 tx_ring->qdev = qdev;
3364                 tx_ring->wq_id = i;
3365                 tx_ring->wq_len = qdev->tx_ring_size;
3366                 tx_ring->wq_size =
3367                     tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3368
3369                 /*
3370                  * The completion queue ID for the tx rings start
3371                  * immediately after the default Q ID, which is zero.
3372                  */
3373                 tx_ring->cq_id = i + 1;
3374         }
3375
3376         for (i = 0; i < qdev->rx_ring_count; i++) {
3377                 rx_ring = &qdev->rx_ring[i];
3378                 memset((void *)rx_ring, 0, sizeof(rx_ring));
3379                 rx_ring->qdev = qdev;
3380                 rx_ring->cq_id = i;
3381                 rx_ring->cpu = i % cpu_cnt;     /* CPU to run handler on. */
3382                 if (i == 0) {   /* Default queue at index 0. */
3383                         /*
3384                          * Default queue handles bcast/mcast plus
3385                          * async events.  Needs buffers.
3386                          */
3387                         rx_ring->cq_len = qdev->rx_ring_size;
3388                         rx_ring->cq_size =
3389                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3390                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3391                         rx_ring->lbq_size =
3392                             rx_ring->lbq_len * sizeof(__le64);
3393                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3394                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3395                         rx_ring->sbq_size =
3396                             rx_ring->sbq_len * sizeof(__le64);
3397                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3398                         rx_ring->type = DEFAULT_Q;
3399                 } else if (i < qdev->rss_ring_first_cq_id) {
3400                         /*
3401                          * Outbound queue handles outbound completions only.
3402                          */
3403                         /* outbound cq is same size as tx_ring it services. */
3404                         rx_ring->cq_len = qdev->tx_ring_size;
3405                         rx_ring->cq_size =
3406                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3407                         rx_ring->lbq_len = 0;
3408                         rx_ring->lbq_size = 0;
3409                         rx_ring->lbq_buf_size = 0;
3410                         rx_ring->sbq_len = 0;
3411                         rx_ring->sbq_size = 0;
3412                         rx_ring->sbq_buf_size = 0;
3413                         rx_ring->type = TX_Q;
3414                 } else {        /* Inbound completions (RSS) queues */
3415                         /*
3416                          * Inbound queues handle unicast frames only.
3417                          */
3418                         rx_ring->cq_len = qdev->rx_ring_size;
3419                         rx_ring->cq_size =
3420                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3421                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3422                         rx_ring->lbq_size =
3423                             rx_ring->lbq_len * sizeof(__le64);
3424                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3425                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3426                         rx_ring->sbq_size =
3427                             rx_ring->sbq_len * sizeof(__le64);
3428                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3429                         rx_ring->type = RX_Q;
3430                 }
3431         }
3432         return 0;
3433 }
3434
3435 static int qlge_open(struct net_device *ndev)
3436 {
3437         int err = 0;
3438         struct ql_adapter *qdev = netdev_priv(ndev);
3439
3440         err = ql_configure_rings(qdev);
3441         if (err)
3442                 return err;
3443
3444         err = ql_get_adapter_resources(qdev);
3445         if (err)
3446                 goto error_up;
3447
3448         err = ql_adapter_up(qdev);
3449         if (err)
3450                 goto error_up;
3451
3452         return err;
3453
3454 error_up:
3455         ql_release_adapter_resources(qdev);
3456         return err;
3457 }
3458
3459 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3460 {
3461         struct ql_adapter *qdev = netdev_priv(ndev);
3462
3463         if (ndev->mtu == 1500 && new_mtu == 9000) {
3464                 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3465         } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3466                 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3467         } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3468                    (ndev->mtu == 9000 && new_mtu == 9000)) {
3469                 return 0;
3470         } else
3471                 return -EINVAL;
3472         ndev->mtu = new_mtu;
3473         return 0;
3474 }
3475
3476 static struct net_device_stats *qlge_get_stats(struct net_device
3477                                                *ndev)
3478 {
3479         struct ql_adapter *qdev = netdev_priv(ndev);
3480         return &qdev->stats;
3481 }
3482
3483 static void qlge_set_multicast_list(struct net_device *ndev)
3484 {
3485         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3486         struct dev_mc_list *mc_ptr;
3487         int i, status;
3488
3489         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3490         if (status)
3491                 return;
3492         spin_lock(&qdev->hw_lock);
3493         /*
3494          * Set or clear promiscuous mode if a
3495          * transition is taking place.
3496          */
3497         if (ndev->flags & IFF_PROMISC) {
3498                 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3499                         if (ql_set_routing_reg
3500                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3501                                 QPRINTK(qdev, HW, ERR,
3502                                         "Failed to set promiscous mode.\n");
3503                         } else {
3504                                 set_bit(QL_PROMISCUOUS, &qdev->flags);
3505                         }
3506                 }
3507         } else {
3508                 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3509                         if (ql_set_routing_reg
3510                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3511                                 QPRINTK(qdev, HW, ERR,
3512                                         "Failed to clear promiscous mode.\n");
3513                         } else {
3514                                 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3515                         }
3516                 }
3517         }
3518
3519         /*
3520          * Set or clear all multicast mode if a
3521          * transition is taking place.
3522          */
3523         if ((ndev->flags & IFF_ALLMULTI) ||
3524             (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3525                 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3526                         if (ql_set_routing_reg
3527                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3528                                 QPRINTK(qdev, HW, ERR,
3529                                         "Failed to set all-multi mode.\n");
3530                         } else {
3531                                 set_bit(QL_ALLMULTI, &qdev->flags);
3532                         }
3533                 }
3534         } else {
3535                 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3536                         if (ql_set_routing_reg
3537                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3538                                 QPRINTK(qdev, HW, ERR,
3539                                         "Failed to clear all-multi mode.\n");
3540                         } else {
3541                                 clear_bit(QL_ALLMULTI, &qdev->flags);
3542                         }
3543                 }
3544         }
3545
3546         if (ndev->mc_count) {
3547                 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3548                 if (status)
3549                         goto exit;
3550                 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3551                      i++, mc_ptr = mc_ptr->next)
3552                         if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3553                                                 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3554                                 QPRINTK(qdev, HW, ERR,
3555                                         "Failed to loadmulticast address.\n");
3556                                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3557                                 goto exit;
3558                         }
3559                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3560                 if (ql_set_routing_reg
3561                     (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3562                         QPRINTK(qdev, HW, ERR,
3563                                 "Failed to set multicast match mode.\n");
3564                 } else {
3565                         set_bit(QL_ALLMULTI, &qdev->flags);
3566                 }
3567         }
3568 exit:
3569         spin_unlock(&qdev->hw_lock);
3570         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3571 }
3572
3573 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3574 {
3575         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3576         struct sockaddr *addr = p;
3577         int status;
3578
3579         if (netif_running(ndev))
3580                 return -EBUSY;
3581
3582         if (!is_valid_ether_addr(addr->sa_data))
3583                 return -EADDRNOTAVAIL;
3584         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3585
3586         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3587         if (status)
3588                 return status;
3589         spin_lock(&qdev->hw_lock);
3590         status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3591                         MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3592         spin_unlock(&qdev->hw_lock);
3593         if (status)
3594                 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3595         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3596         return status;
3597 }
3598
3599 static void qlge_tx_timeout(struct net_device *ndev)
3600 {
3601         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3602         ql_queue_asic_error(qdev);
3603 }
3604
3605 static void ql_asic_reset_work(struct work_struct *work)
3606 {
3607         struct ql_adapter *qdev =
3608             container_of(work, struct ql_adapter, asic_reset_work.work);
3609         ql_cycle_adapter(qdev);
3610 }
3611
3612 static struct nic_operations qla8012_nic_ops = {
3613         .get_flash              = ql_get_8012_flash_params,
3614         .port_initialize        = ql_8012_port_initialize,
3615 };
3616
3617 static struct nic_operations qla8000_nic_ops = {
3618         .get_flash              = ql_get_8000_flash_params,
3619         .port_initialize        = ql_8000_port_initialize,
3620 };
3621
3622
3623 static void ql_get_board_info(struct ql_adapter *qdev)
3624 {
3625         qdev->func =
3626             (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3627         if (qdev->func) {
3628                 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3629                 qdev->port_link_up = STS_PL1;
3630                 qdev->port_init = STS_PI1;
3631                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3632                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3633         } else {
3634                 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3635                 qdev->port_link_up = STS_PL0;
3636                 qdev->port_init = STS_PI0;
3637                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3638                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3639         }
3640         qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3641         qdev->device_id = qdev->pdev->device;
3642         if (qdev->device_id == QLGE_DEVICE_ID_8012)
3643                 qdev->nic_ops = &qla8012_nic_ops;
3644         else if (qdev->device_id == QLGE_DEVICE_ID_8000)
3645                 qdev->nic_ops = &qla8000_nic_ops;
3646 }
3647
3648 static void ql_release_all(struct pci_dev *pdev)
3649 {
3650         struct net_device *ndev = pci_get_drvdata(pdev);
3651         struct ql_adapter *qdev = netdev_priv(ndev);
3652
3653         if (qdev->workqueue) {
3654                 destroy_workqueue(qdev->workqueue);
3655                 qdev->workqueue = NULL;
3656         }
3657         if (qdev->q_workqueue) {
3658                 destroy_workqueue(qdev->q_workqueue);
3659                 qdev->q_workqueue = NULL;
3660         }
3661         if (qdev->reg_base)
3662                 iounmap(qdev->reg_base);
3663         if (qdev->doorbell_area)
3664                 iounmap(qdev->doorbell_area);
3665         pci_release_regions(pdev);
3666         pci_set_drvdata(pdev, NULL);
3667 }
3668
3669 static int __devinit ql_init_device(struct pci_dev *pdev,
3670                                     struct net_device *ndev, int cards_found)
3671 {
3672         struct ql_adapter *qdev = netdev_priv(ndev);
3673         int pos, err = 0;
3674         u16 val16;
3675
3676         memset((void *)qdev, 0, sizeof(qdev));
3677         err = pci_enable_device(pdev);
3678         if (err) {
3679                 dev_err(&pdev->dev, "PCI device enable failed.\n");
3680                 return err;
3681         }
3682
3683         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3684         if (pos <= 0) {
3685                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3686                         "aborting.\n");
3687                 goto err_out;
3688         } else {
3689                 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3690                 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3691                 val16 |= (PCI_EXP_DEVCTL_CERE |
3692                           PCI_EXP_DEVCTL_NFERE |
3693                           PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3694                 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3695         }
3696
3697         err = pci_request_regions(pdev, DRV_NAME);
3698         if (err) {
3699                 dev_err(&pdev->dev, "PCI region request failed.\n");
3700                 goto err_out;
3701         }
3702
3703         pci_set_master(pdev);
3704         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3705                 set_bit(QL_DMA64, &qdev->flags);
3706                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3707         } else {
3708                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3709                 if (!err)
3710                        err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3711         }
3712
3713         if (err) {
3714                 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3715                 goto err_out;
3716         }
3717
3718         pci_set_drvdata(pdev, ndev);
3719         qdev->reg_base =
3720             ioremap_nocache(pci_resource_start(pdev, 1),
3721                             pci_resource_len(pdev, 1));
3722         if (!qdev->reg_base) {
3723                 dev_err(&pdev->dev, "Register mapping failed.\n");
3724                 err = -ENOMEM;
3725                 goto err_out;
3726         }
3727
3728         qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3729         qdev->doorbell_area =
3730             ioremap_nocache(pci_resource_start(pdev, 3),
3731                             pci_resource_len(pdev, 3));
3732         if (!qdev->doorbell_area) {
3733                 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3734                 err = -ENOMEM;
3735                 goto err_out;
3736         }
3737
3738         qdev->ndev = ndev;
3739         qdev->pdev = pdev;
3740         ql_get_board_info(qdev);
3741         qdev->msg_enable = netif_msg_init(debug, default_msg);
3742         spin_lock_init(&qdev->hw_lock);
3743         spin_lock_init(&qdev->stats_lock);
3744
3745         /* make sure the EEPROM is good */
3746         err = qdev->nic_ops->get_flash(qdev);
3747         if (err) {
3748                 dev_err(&pdev->dev, "Invalid FLASH.\n");
3749                 goto err_out;
3750         }
3751
3752         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3753
3754         /* Set up the default ring sizes. */
3755         qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3756         qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3757
3758         /* Set up the coalescing parameters. */
3759         qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3760         qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3761         qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3762         qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3763
3764         /*
3765          * Set up the operating parameters.
3766          */
3767         qdev->rx_csum = 1;
3768
3769         qdev->q_workqueue = create_workqueue(ndev->name);
3770         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3771         INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3772         INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3773         INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3774         mutex_init(&qdev->mpi_mutex);
3775
3776         if (!cards_found) {
3777                 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3778                 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3779                          DRV_NAME, DRV_VERSION);
3780         }
3781         return 0;
3782 err_out:
3783         ql_release_all(pdev);
3784         pci_disable_device(pdev);
3785         return err;
3786 }
3787
3788
3789 static const struct net_device_ops qlge_netdev_ops = {
3790         .ndo_open               = qlge_open,
3791         .ndo_stop               = qlge_close,
3792         .ndo_start_xmit         = qlge_send,
3793         .ndo_change_mtu         = qlge_change_mtu,
3794         .ndo_get_stats          = qlge_get_stats,
3795         .ndo_set_multicast_list = qlge_set_multicast_list,
3796         .ndo_set_mac_address    = qlge_set_mac_address,
3797         .ndo_validate_addr      = eth_validate_addr,
3798         .ndo_tx_timeout         = qlge_tx_timeout,
3799         .ndo_vlan_rx_register   = ql_vlan_rx_register,
3800         .ndo_vlan_rx_add_vid    = ql_vlan_rx_add_vid,
3801         .ndo_vlan_rx_kill_vid   = ql_vlan_rx_kill_vid,
3802 };
3803
3804 static int __devinit qlge_probe(struct pci_dev *pdev,
3805                                 const struct pci_device_id *pci_entry)
3806 {
3807         struct net_device *ndev = NULL;
3808         struct ql_adapter *qdev = NULL;
3809         static int cards_found = 0;
3810         int err = 0;
3811
3812         ndev = alloc_etherdev(sizeof(struct ql_adapter));
3813         if (!ndev)
3814                 return -ENOMEM;
3815
3816         err = ql_init_device(pdev, ndev, cards_found);
3817         if (err < 0) {
3818                 free_netdev(ndev);
3819                 return err;
3820         }
3821
3822         qdev = netdev_priv(ndev);
3823         SET_NETDEV_DEV(ndev, &pdev->dev);
3824         ndev->features = (0
3825                           | NETIF_F_IP_CSUM
3826                           | NETIF_F_SG
3827                           | NETIF_F_TSO
3828                           | NETIF_F_TSO6
3829                           | NETIF_F_TSO_ECN
3830                           | NETIF_F_HW_VLAN_TX
3831                           | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3832
3833         if (test_bit(QL_DMA64, &qdev->flags))
3834                 ndev->features |= NETIF_F_HIGHDMA;
3835
3836         /*
3837          * Set up net_device structure.
3838          */
3839         ndev->tx_queue_len = qdev->tx_ring_size;
3840         ndev->irq = pdev->irq;
3841
3842         ndev->netdev_ops = &qlge_netdev_ops;
3843         SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
3844         ndev->watchdog_timeo = 10 * HZ;
3845
3846         err = register_netdev(ndev);
3847         if (err) {
3848                 dev_err(&pdev->dev, "net device registration failed.\n");
3849                 ql_release_all(pdev);
3850                 pci_disable_device(pdev);
3851                 return err;
3852         }
3853         netif_carrier_off(ndev);
3854         netif_stop_queue(ndev);
3855         ql_display_dev_info(ndev);
3856         cards_found++;
3857         return 0;
3858 }
3859
3860 static void __devexit qlge_remove(struct pci_dev *pdev)
3861 {
3862         struct net_device *ndev = pci_get_drvdata(pdev);
3863         unregister_netdev(ndev);
3864         ql_release_all(pdev);
3865         pci_disable_device(pdev);
3866         free_netdev(ndev);
3867 }
3868
3869 /*
3870  * This callback is called by the PCI subsystem whenever
3871  * a PCI bus error is detected.
3872  */
3873 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3874                                                enum pci_channel_state state)
3875 {
3876         struct net_device *ndev = pci_get_drvdata(pdev);
3877         struct ql_adapter *qdev = netdev_priv(ndev);
3878
3879         if (netif_running(ndev))
3880                 ql_adapter_down(qdev);
3881
3882         pci_disable_device(pdev);
3883
3884         /* Request a slot reset. */
3885         return PCI_ERS_RESULT_NEED_RESET;
3886 }
3887
3888 /*
3889  * This callback is called after the PCI buss has been reset.
3890  * Basically, this tries to restart the card from scratch.
3891  * This is a shortened version of the device probe/discovery code,
3892  * it resembles the first-half of the () routine.
3893  */
3894 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3895 {
3896         struct net_device *ndev = pci_get_drvdata(pdev);
3897         struct ql_adapter *qdev = netdev_priv(ndev);
3898
3899         if (pci_enable_device(pdev)) {
3900                 QPRINTK(qdev, IFUP, ERR,
3901                         "Cannot re-enable PCI device after reset.\n");
3902                 return PCI_ERS_RESULT_DISCONNECT;
3903         }
3904
3905         pci_set_master(pdev);
3906
3907         netif_carrier_off(ndev);
3908         netif_stop_queue(ndev);
3909         ql_adapter_reset(qdev);
3910
3911         /* Make sure the EEPROM is good */
3912         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3913
3914         if (!is_valid_ether_addr(ndev->perm_addr)) {
3915                 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3916                 return PCI_ERS_RESULT_DISCONNECT;
3917         }
3918
3919         return PCI_ERS_RESULT_RECOVERED;
3920 }
3921
3922 static void qlge_io_resume(struct pci_dev *pdev)
3923 {
3924         struct net_device *ndev = pci_get_drvdata(pdev);
3925         struct ql_adapter *qdev = netdev_priv(ndev);
3926
3927         pci_set_master(pdev);
3928
3929         if (netif_running(ndev)) {
3930                 if (ql_adapter_up(qdev)) {
3931                         QPRINTK(qdev, IFUP, ERR,
3932                                 "Device initialization failed after reset.\n");
3933                         return;
3934                 }
3935         }
3936
3937         netif_device_attach(ndev);
3938 }
3939
3940 static struct pci_error_handlers qlge_err_handler = {
3941         .error_detected = qlge_io_error_detected,
3942         .slot_reset = qlge_io_slot_reset,
3943         .resume = qlge_io_resume,
3944 };
3945
3946 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3947 {
3948         struct net_device *ndev = pci_get_drvdata(pdev);
3949         struct ql_adapter *qdev = netdev_priv(ndev);
3950         int err, i;
3951
3952         netif_device_detach(ndev);
3953
3954         if (netif_running(ndev)) {
3955                 err = ql_adapter_down(qdev);
3956                 if (!err)
3957                         return err;
3958         }
3959
3960         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++)
3961                 netif_napi_del(&qdev->rx_ring[i].napi);
3962
3963         err = pci_save_state(pdev);
3964         if (err)
3965                 return err;
3966
3967         pci_disable_device(pdev);
3968
3969         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3970
3971         return 0;
3972 }
3973
3974 #ifdef CONFIG_PM
3975 static int qlge_resume(struct pci_dev *pdev)
3976 {
3977         struct net_device *ndev = pci_get_drvdata(pdev);
3978         struct ql_adapter *qdev = netdev_priv(ndev);
3979         int err;
3980
3981         pci_set_power_state(pdev, PCI_D0);
3982         pci_restore_state(pdev);
3983         err = pci_enable_device(pdev);
3984         if (err) {
3985                 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
3986                 return err;
3987         }
3988         pci_set_master(pdev);
3989
3990         pci_enable_wake(pdev, PCI_D3hot, 0);
3991         pci_enable_wake(pdev, PCI_D3cold, 0);
3992
3993         if (netif_running(ndev)) {
3994                 err = ql_adapter_up(qdev);
3995                 if (err)
3996                         return err;
3997         }
3998
3999         netif_device_attach(ndev);
4000
4001         return 0;
4002 }
4003 #endif /* CONFIG_PM */
4004
4005 static void qlge_shutdown(struct pci_dev *pdev)
4006 {
4007         qlge_suspend(pdev, PMSG_SUSPEND);
4008 }
4009
4010 static struct pci_driver qlge_driver = {
4011         .name = DRV_NAME,
4012         .id_table = qlge_pci_tbl,
4013         .probe = qlge_probe,
4014         .remove = __devexit_p(qlge_remove),
4015 #ifdef CONFIG_PM
4016         .suspend = qlge_suspend,
4017         .resume = qlge_resume,
4018 #endif
4019         .shutdown = qlge_shutdown,
4020         .err_handler = &qlge_err_handler
4021 };
4022
4023 static int __init qlge_init_module(void)
4024 {
4025         return pci_register_driver(&qlge_driver);
4026 }
4027
4028 static void __exit qlge_exit(void)
4029 {
4030         pci_unregister_driver(&qlge_driver);
4031 }
4032
4033 module_init(qlge_init_module);
4034 module_exit(qlge_exit);