qlge: Increase MAC addr hw sem granularity.
[linux-2.6.git] / drivers / net / qlge / qlge_main.c
1 /*
2  * QLogic qlge NIC HBA Driver
3  * Copyright (c)  2003-2008 QLogic Corporation
4  * See LICENSE.qlge for copyright and licensing details.
5  * Author:     Linux qlge network device driver by
6  *                      Ron Mercer <ron.mercer@qlogic.com>
7  */
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/pagemap.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/dmapool.h>
19 #include <linux/mempool.h>
20 #include <linux/spinlock.h>
21 #include <linux/kthread.h>
22 #include <linux/interrupt.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/in.h>
26 #include <linux/ip.h>
27 #include <linux/ipv6.h>
28 #include <net/ipv6.h>
29 #include <linux/tcp.h>
30 #include <linux/udp.h>
31 #include <linux/if_arp.h>
32 #include <linux/if_ether.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/skbuff.h>
37 #include <linux/rtnetlink.h>
38 #include <linux/if_vlan.h>
39 #include <linux/delay.h>
40 #include <linux/mm.h>
41 #include <linux/vmalloc.h>
42 #include <net/ip6_checksum.h>
43
44 #include "qlge.h"
45
46 char qlge_driver_name[] = DRV_NAME;
47 const char qlge_driver_version[] = DRV_VERSION;
48
49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
50 MODULE_DESCRIPTION(DRV_STRING " ");
51 MODULE_LICENSE("GPL");
52 MODULE_VERSION(DRV_VERSION);
53
54 static const u32 default_msg =
55     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
56 /* NETIF_MSG_TIMER |    */
57     NETIF_MSG_IFDOWN |
58     NETIF_MSG_IFUP |
59     NETIF_MSG_RX_ERR |
60     NETIF_MSG_TX_ERR |
61     NETIF_MSG_TX_QUEUED |
62     NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS |
63 /* NETIF_MSG_PKTDATA | */
64     NETIF_MSG_HW | NETIF_MSG_WOL | 0;
65
66 static int debug = 0x00007fff;  /* defaults above */
67 module_param(debug, int, 0);
68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
69
70 #define MSIX_IRQ 0
71 #define MSI_IRQ 1
72 #define LEG_IRQ 2
73 static int irq_type = MSIX_IRQ;
74 module_param(irq_type, int, MSIX_IRQ);
75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
76
77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
78         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID)},
79         /* required last entry */
80         {0,}
81 };
82
83 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
84
85 /* This hardware semaphore causes exclusive access to
86  * resources shared between the NIC driver, MPI firmware,
87  * FCOE firmware and the FC driver.
88  */
89 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
90 {
91         u32 sem_bits = 0;
92
93         switch (sem_mask) {
94         case SEM_XGMAC0_MASK:
95                 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
96                 break;
97         case SEM_XGMAC1_MASK:
98                 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
99                 break;
100         case SEM_ICB_MASK:
101                 sem_bits = SEM_SET << SEM_ICB_SHIFT;
102                 break;
103         case SEM_MAC_ADDR_MASK:
104                 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
105                 break;
106         case SEM_FLASH_MASK:
107                 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
108                 break;
109         case SEM_PROBE_MASK:
110                 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
111                 break;
112         case SEM_RT_IDX_MASK:
113                 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
114                 break;
115         case SEM_PROC_REG_MASK:
116                 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
117                 break;
118         default:
119                 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
120                 return -EINVAL;
121         }
122
123         ql_write32(qdev, SEM, sem_bits | sem_mask);
124         return !(ql_read32(qdev, SEM) & sem_bits);
125 }
126
127 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
128 {
129         unsigned int wait_count = 30;
130         do {
131                 if (!ql_sem_trylock(qdev, sem_mask))
132                         return 0;
133                 udelay(100);
134         } while (--wait_count);
135         return -ETIMEDOUT;
136 }
137
138 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
139 {
140         ql_write32(qdev, SEM, sem_mask);
141         ql_read32(qdev, SEM);   /* flush */
142 }
143
144 /* This function waits for a specific bit to come ready
145  * in a given register.  It is used mostly by the initialize
146  * process, but is also used in kernel thread API such as
147  * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
148  */
149 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
150 {
151         u32 temp;
152         int count = UDELAY_COUNT;
153
154         while (count) {
155                 temp = ql_read32(qdev, reg);
156
157                 /* check for errors */
158                 if (temp & err_bit) {
159                         QPRINTK(qdev, PROBE, ALERT,
160                                 "register 0x%.08x access error, value = 0x%.08x!.\n",
161                                 reg, temp);
162                         return -EIO;
163                 } else if (temp & bit)
164                         return 0;
165                 udelay(UDELAY_DELAY);
166                 count--;
167         }
168         QPRINTK(qdev, PROBE, ALERT,
169                 "Timed out waiting for reg %x to come ready.\n", reg);
170         return -ETIMEDOUT;
171 }
172
173 /* The CFG register is used to download TX and RX control blocks
174  * to the chip. This function waits for an operation to complete.
175  */
176 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
177 {
178         int count = UDELAY_COUNT;
179         u32 temp;
180
181         while (count) {
182                 temp = ql_read32(qdev, CFG);
183                 if (temp & CFG_LE)
184                         return -EIO;
185                 if (!(temp & bit))
186                         return 0;
187                 udelay(UDELAY_DELAY);
188                 count--;
189         }
190         return -ETIMEDOUT;
191 }
192
193
194 /* Used to issue init control blocks to hw. Maps control block,
195  * sets address, triggers download, waits for completion.
196  */
197 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
198                  u16 q_id)
199 {
200         u64 map;
201         int status = 0;
202         int direction;
203         u32 mask;
204         u32 value;
205
206         direction =
207             (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
208             PCI_DMA_FROMDEVICE;
209
210         map = pci_map_single(qdev->pdev, ptr, size, direction);
211         if (pci_dma_mapping_error(qdev->pdev, map)) {
212                 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
213                 return -ENOMEM;
214         }
215
216         status = ql_wait_cfg(qdev, bit);
217         if (status) {
218                 QPRINTK(qdev, IFUP, ERR,
219                         "Timed out waiting for CFG to come ready.\n");
220                 goto exit;
221         }
222
223         status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
224         if (status)
225                 goto exit;
226         ql_write32(qdev, ICB_L, (u32) map);
227         ql_write32(qdev, ICB_H, (u32) (map >> 32));
228         ql_sem_unlock(qdev, SEM_ICB_MASK);      /* does flush too */
229
230         mask = CFG_Q_MASK | (bit << 16);
231         value = bit | (q_id << CFG_Q_SHIFT);
232         ql_write32(qdev, CFG, (mask | value));
233
234         /*
235          * Wait for the bit to clear after signaling hw.
236          */
237         status = ql_wait_cfg(qdev, bit);
238 exit:
239         pci_unmap_single(qdev->pdev, map, size, direction);
240         return status;
241 }
242
243 /* Get a specific MAC address from the CAM.  Used for debug and reg dump. */
244 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
245                         u32 *value)
246 {
247         u32 offset = 0;
248         int status;
249
250         switch (type) {
251         case MAC_ADDR_TYPE_MULTI_MAC:
252         case MAC_ADDR_TYPE_CAM_MAC:
253                 {
254                         status =
255                             ql_wait_reg_rdy(qdev,
256                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
257                         if (status)
258                                 goto exit;
259                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
260                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
261                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
262                         status =
263                             ql_wait_reg_rdy(qdev,
264                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
265                         if (status)
266                                 goto exit;
267                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
268                         status =
269                             ql_wait_reg_rdy(qdev,
270                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
271                         if (status)
272                                 goto exit;
273                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
274                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
275                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
276                         status =
277                             ql_wait_reg_rdy(qdev,
278                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
279                         if (status)
280                                 goto exit;
281                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
282                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
283                                 status =
284                                     ql_wait_reg_rdy(qdev,
285                                         MAC_ADDR_IDX, MAC_ADDR_MW, 0);
286                                 if (status)
287                                         goto exit;
288                                 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
289                                            (index << MAC_ADDR_IDX_SHIFT) | /* index */
290                                            MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
291                                 status =
292                                     ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
293                                                     MAC_ADDR_MR, 0);
294                                 if (status)
295                                         goto exit;
296                                 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
297                         }
298                         break;
299                 }
300         case MAC_ADDR_TYPE_VLAN:
301         case MAC_ADDR_TYPE_MULTI_FLTR:
302         default:
303                 QPRINTK(qdev, IFUP, CRIT,
304                         "Address type %d not yet supported.\n", type);
305                 status = -EPERM;
306         }
307 exit:
308         return status;
309 }
310
311 /* Set up a MAC, multicast or VLAN address for the
312  * inbound frame matching.
313  */
314 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
315                                u16 index)
316 {
317         u32 offset = 0;
318         int status = 0;
319
320         switch (type) {
321         case MAC_ADDR_TYPE_MULTI_MAC:
322         case MAC_ADDR_TYPE_CAM_MAC:
323                 {
324                         u32 cam_output;
325                         u32 upper = (addr[0] << 8) | addr[1];
326                         u32 lower =
327                             (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
328                             (addr[5]);
329
330                         QPRINTK(qdev, IFUP, INFO,
331                                 "Adding %s address %pM"
332                                 " at index %d in the CAM.\n",
333                                 ((type ==
334                                   MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
335                                  "UNICAST"), addr, index);
336
337                         status =
338                             ql_wait_reg_rdy(qdev,
339                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
340                         if (status)
341                                 goto exit;
342                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
343                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
344                                    type);       /* type */
345                         ql_write32(qdev, MAC_ADDR_DATA, lower);
346                         status =
347                             ql_wait_reg_rdy(qdev,
348                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
349                         if (status)
350                                 goto exit;
351                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
352                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
353                                    type);       /* type */
354                         ql_write32(qdev, MAC_ADDR_DATA, upper);
355                         status =
356                             ql_wait_reg_rdy(qdev,
357                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
358                         if (status)
359                                 goto exit;
360                         ql_write32(qdev, MAC_ADDR_IDX, (offset) |       /* offset */
361                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
362                                    type);       /* type */
363                         /* This field should also include the queue id
364                            and possibly the function id.  Right now we hardcode
365                            the route field to NIC core.
366                          */
367                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
368                                 cam_output = (CAM_OUT_ROUTE_NIC |
369                                               (qdev->
370                                                func << CAM_OUT_FUNC_SHIFT) |
371                                               (qdev->
372                                                rss_ring_first_cq_id <<
373                                                CAM_OUT_CQ_ID_SHIFT));
374                                 if (qdev->vlgrp)
375                                         cam_output |= CAM_OUT_RV;
376                                 /* route to NIC core */
377                                 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
378                         }
379                         break;
380                 }
381         case MAC_ADDR_TYPE_VLAN:
382                 {
383                         u32 enable_bit = *((u32 *) &addr[0]);
384                         /* For VLAN, the addr actually holds a bit that
385                          * either enables or disables the vlan id we are
386                          * addressing. It's either MAC_ADDR_E on or off.
387                          * That's bit-27 we're talking about.
388                          */
389                         QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
390                                 (enable_bit ? "Adding" : "Removing"),
391                                 index, (enable_bit ? "to" : "from"));
392
393                         status =
394                             ql_wait_reg_rdy(qdev,
395                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
396                         if (status)
397                                 goto exit;
398                         ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
399                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
400                                    type |       /* type */
401                                    enable_bit); /* enable/disable */
402                         break;
403                 }
404         case MAC_ADDR_TYPE_MULTI_FLTR:
405         default:
406                 QPRINTK(qdev, IFUP, CRIT,
407                         "Address type %d not yet supported.\n", type);
408                 status = -EPERM;
409         }
410 exit:
411         return status;
412 }
413
414 /* Get a specific frame routing value from the CAM.
415  * Used for debug and reg dump.
416  */
417 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
418 {
419         int status = 0;
420
421         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
422         if (status)
423                 goto exit;
424
425         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
426         if (status)
427                 goto exit;
428
429         ql_write32(qdev, RT_IDX,
430                    RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
431         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
432         if (status)
433                 goto exit;
434         *value = ql_read32(qdev, RT_DATA);
435 exit:
436         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
437         return status;
438 }
439
440 /* The NIC function for this chip has 16 routing indexes.  Each one can be used
441  * to route different frame types to various inbound queues.  We send broadcast/
442  * multicast/error frames to the default queue for slow handling,
443  * and CAM hit/RSS frames to the fast handling queues.
444  */
445 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
446                               int enable)
447 {
448         int status;
449         u32 value = 0;
450
451         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
452         if (status)
453                 return status;
454
455         QPRINTK(qdev, IFUP, DEBUG,
456                 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
457                 (enable ? "Adding" : "Removing"),
458                 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
459                 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
460                 ((index ==
461                   RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
462                 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
463                 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
464                 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
465                 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
466                 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
467                 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
468                 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
469                 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
470                 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
471                 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
472                 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
473                 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
474                 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
475                 (enable ? "to" : "from"));
476
477         switch (mask) {
478         case RT_IDX_CAM_HIT:
479                 {
480                         value = RT_IDX_DST_CAM_Q |      /* dest */
481                             RT_IDX_TYPE_NICQ |  /* type */
482                             (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
483                         break;
484                 }
485         case RT_IDX_VALID:      /* Promiscuous Mode frames. */
486                 {
487                         value = RT_IDX_DST_DFLT_Q |     /* dest */
488                             RT_IDX_TYPE_NICQ |  /* type */
489                             (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
490                         break;
491                 }
492         case RT_IDX_ERR:        /* Pass up MAC,IP,TCP/UDP error frames. */
493                 {
494                         value = RT_IDX_DST_DFLT_Q |     /* dest */
495                             RT_IDX_TYPE_NICQ |  /* type */
496                             (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
497                         break;
498                 }
499         case RT_IDX_BCAST:      /* Pass up Broadcast frames to default Q. */
500                 {
501                         value = RT_IDX_DST_DFLT_Q |     /* dest */
502                             RT_IDX_TYPE_NICQ |  /* type */
503                             (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
504                         break;
505                 }
506         case RT_IDX_MCAST:      /* Pass up All Multicast frames. */
507                 {
508                         value = RT_IDX_DST_CAM_Q |      /* dest */
509                             RT_IDX_TYPE_NICQ |  /* type */
510                             (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
511                         break;
512                 }
513         case RT_IDX_MCAST_MATCH:        /* Pass up matched Multicast frames. */
514                 {
515                         value = RT_IDX_DST_CAM_Q |      /* dest */
516                             RT_IDX_TYPE_NICQ |  /* type */
517                             (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
518                         break;
519                 }
520         case RT_IDX_RSS_MATCH:  /* Pass up matched RSS frames. */
521                 {
522                         value = RT_IDX_DST_RSS |        /* dest */
523                             RT_IDX_TYPE_NICQ |  /* type */
524                             (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
525                         break;
526                 }
527         case 0:         /* Clear the E-bit on an entry. */
528                 {
529                         value = RT_IDX_DST_DFLT_Q |     /* dest */
530                             RT_IDX_TYPE_NICQ |  /* type */
531                             (index << RT_IDX_IDX_SHIFT);/* index */
532                         break;
533                 }
534         default:
535                 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
536                         mask);
537                 status = -EPERM;
538                 goto exit;
539         }
540
541         if (value) {
542                 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
543                 if (status)
544                         goto exit;
545                 value |= (enable ? RT_IDX_E : 0);
546                 ql_write32(qdev, RT_IDX, value);
547                 ql_write32(qdev, RT_DATA, enable ? mask : 0);
548         }
549 exit:
550         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
551         return status;
552 }
553
554 static void ql_enable_interrupts(struct ql_adapter *qdev)
555 {
556         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
557 }
558
559 static void ql_disable_interrupts(struct ql_adapter *qdev)
560 {
561         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
562 }
563
564 /* If we're running with multiple MSI-X vectors then we enable on the fly.
565  * Otherwise, we may have multiple outstanding workers and don't want to
566  * enable until the last one finishes. In this case, the irq_cnt gets
567  * incremented everytime we queue a worker and decremented everytime
568  * a worker finishes.  Once it hits zero we enable the interrupt.
569  */
570 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
571 {
572         u32 var = 0;
573         unsigned long hw_flags = 0;
574         struct intr_context *ctx = qdev->intr_context + intr;
575
576         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
577                 /* Always enable if we're MSIX multi interrupts and
578                  * it's not the default (zeroeth) interrupt.
579                  */
580                 ql_write32(qdev, INTR_EN,
581                            ctx->intr_en_mask);
582                 var = ql_read32(qdev, STS);
583                 return var;
584         }
585
586         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
587         if (atomic_dec_and_test(&ctx->irq_cnt)) {
588                 ql_write32(qdev, INTR_EN,
589                            ctx->intr_en_mask);
590                 var = ql_read32(qdev, STS);
591         }
592         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
593         return var;
594 }
595
596 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
597 {
598         u32 var = 0;
599         unsigned long hw_flags;
600         struct intr_context *ctx;
601
602         /* HW disables for us if we're MSIX multi interrupts and
603          * it's not the default (zeroeth) interrupt.
604          */
605         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
606                 return 0;
607
608         ctx = qdev->intr_context + intr;
609         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
610         if (!atomic_read(&ctx->irq_cnt)) {
611                 ql_write32(qdev, INTR_EN,
612                 ctx->intr_dis_mask);
613                 var = ql_read32(qdev, STS);
614         }
615         atomic_inc(&ctx->irq_cnt);
616         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
617         return var;
618 }
619
620 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
621 {
622         int i;
623         for (i = 0; i < qdev->intr_count; i++) {
624                 /* The enable call does a atomic_dec_and_test
625                  * and enables only if the result is zero.
626                  * So we precharge it here.
627                  */
628                 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
629                         i == 0))
630                         atomic_set(&qdev->intr_context[i].irq_cnt, 1);
631                 ql_enable_completion_interrupt(qdev, i);
632         }
633
634 }
635
636 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
637 {
638         int status = 0;
639         /* wait for reg to come ready */
640         status = ql_wait_reg_rdy(qdev,
641                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
642         if (status)
643                 goto exit;
644         /* set up for reg read */
645         ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
646         /* wait for reg to come ready */
647         status = ql_wait_reg_rdy(qdev,
648                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
649         if (status)
650                 goto exit;
651          /* This data is stored on flash as an array of
652          * __le32.  Since ql_read32() returns cpu endian
653          * we need to swap it back.
654          */
655         *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
656 exit:
657         return status;
658 }
659
660 static int ql_get_flash_params(struct ql_adapter *qdev)
661 {
662         int i;
663         int status;
664         __le32 *p = (__le32 *)&qdev->flash;
665         u32 offset = 0;
666
667         /* Second function's parameters follow the first
668          * function's.
669          */
670         if (qdev->func)
671                 offset = sizeof(qdev->flash) / sizeof(u32);
672
673         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
674                 return -ETIMEDOUT;
675
676         for (i = 0; i < sizeof(qdev->flash) / sizeof(u32); i++, p++) {
677                 status = ql_read_flash_word(qdev, i+offset, p);
678                 if (status) {
679                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
680                         goto exit;
681                 }
682
683         }
684 exit:
685         ql_sem_unlock(qdev, SEM_FLASH_MASK);
686         return status;
687 }
688
689 /* xgmac register are located behind the xgmac_addr and xgmac_data
690  * register pair.  Each read/write requires us to wait for the ready
691  * bit before reading/writing the data.
692  */
693 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
694 {
695         int status;
696         /* wait for reg to come ready */
697         status = ql_wait_reg_rdy(qdev,
698                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
699         if (status)
700                 return status;
701         /* write the data to the data reg */
702         ql_write32(qdev, XGMAC_DATA, data);
703         /* trigger the write */
704         ql_write32(qdev, XGMAC_ADDR, reg);
705         return status;
706 }
707
708 /* xgmac register are located behind the xgmac_addr and xgmac_data
709  * register pair.  Each read/write requires us to wait for the ready
710  * bit before reading/writing the data.
711  */
712 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
713 {
714         int status = 0;
715         /* wait for reg to come ready */
716         status = ql_wait_reg_rdy(qdev,
717                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
718         if (status)
719                 goto exit;
720         /* set up for reg read */
721         ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
722         /* wait for reg to come ready */
723         status = ql_wait_reg_rdy(qdev,
724                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
725         if (status)
726                 goto exit;
727         /* get the data */
728         *data = ql_read32(qdev, XGMAC_DATA);
729 exit:
730         return status;
731 }
732
733 /* This is used for reading the 64-bit statistics regs. */
734 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
735 {
736         int status = 0;
737         u32 hi = 0;
738         u32 lo = 0;
739
740         status = ql_read_xgmac_reg(qdev, reg, &lo);
741         if (status)
742                 goto exit;
743
744         status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
745         if (status)
746                 goto exit;
747
748         *data = (u64) lo | ((u64) hi << 32);
749
750 exit:
751         return status;
752 }
753
754 /* Take the MAC Core out of reset.
755  * Enable statistics counting.
756  * Take the transmitter/receiver out of reset.
757  * This functionality may be done in the MPI firmware at a
758  * later date.
759  */
760 static int ql_port_initialize(struct ql_adapter *qdev)
761 {
762         int status = 0;
763         u32 data;
764
765         if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
766                 /* Another function has the semaphore, so
767                  * wait for the port init bit to come ready.
768                  */
769                 QPRINTK(qdev, LINK, INFO,
770                         "Another function has the semaphore, so wait for the port init bit to come ready.\n");
771                 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
772                 if (status) {
773                         QPRINTK(qdev, LINK, CRIT,
774                                 "Port initialize timed out.\n");
775                 }
776                 return status;
777         }
778
779         QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
780         /* Set the core reset. */
781         status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
782         if (status)
783                 goto end;
784         data |= GLOBAL_CFG_RESET;
785         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
786         if (status)
787                 goto end;
788
789         /* Clear the core reset and turn on jumbo for receiver. */
790         data &= ~GLOBAL_CFG_RESET;      /* Clear core reset. */
791         data |= GLOBAL_CFG_JUMBO;       /* Turn on jumbo. */
792         data |= GLOBAL_CFG_TX_STAT_EN;
793         data |= GLOBAL_CFG_RX_STAT_EN;
794         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
795         if (status)
796                 goto end;
797
798         /* Enable transmitter, and clear it's reset. */
799         status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
800         if (status)
801                 goto end;
802         data &= ~TX_CFG_RESET;  /* Clear the TX MAC reset. */
803         data |= TX_CFG_EN;      /* Enable the transmitter. */
804         status = ql_write_xgmac_reg(qdev, TX_CFG, data);
805         if (status)
806                 goto end;
807
808         /* Enable receiver and clear it's reset. */
809         status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
810         if (status)
811                 goto end;
812         data &= ~RX_CFG_RESET;  /* Clear the RX MAC reset. */
813         data |= RX_CFG_EN;      /* Enable the receiver. */
814         status = ql_write_xgmac_reg(qdev, RX_CFG, data);
815         if (status)
816                 goto end;
817
818         /* Turn on jumbo. */
819         status =
820             ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
821         if (status)
822                 goto end;
823         status =
824             ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
825         if (status)
826                 goto end;
827
828         /* Signal to the world that the port is enabled.        */
829         ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
830 end:
831         ql_sem_unlock(qdev, qdev->xg_sem_mask);
832         return status;
833 }
834
835 /* Get the next large buffer. */
836 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
837 {
838         struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
839         rx_ring->lbq_curr_idx++;
840         if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
841                 rx_ring->lbq_curr_idx = 0;
842         rx_ring->lbq_free_cnt++;
843         return lbq_desc;
844 }
845
846 /* Get the next small buffer. */
847 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
848 {
849         struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
850         rx_ring->sbq_curr_idx++;
851         if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
852                 rx_ring->sbq_curr_idx = 0;
853         rx_ring->sbq_free_cnt++;
854         return sbq_desc;
855 }
856
857 /* Update an rx ring index. */
858 static void ql_update_cq(struct rx_ring *rx_ring)
859 {
860         rx_ring->cnsmr_idx++;
861         rx_ring->curr_entry++;
862         if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
863                 rx_ring->cnsmr_idx = 0;
864                 rx_ring->curr_entry = rx_ring->cq_base;
865         }
866 }
867
868 static void ql_write_cq_idx(struct rx_ring *rx_ring)
869 {
870         ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
871 }
872
873 /* Process (refill) a large buffer queue. */
874 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
875 {
876         int clean_idx = rx_ring->lbq_clean_idx;
877         struct bq_desc *lbq_desc;
878         u64 map;
879         int i;
880
881         while (rx_ring->lbq_free_cnt > 16) {
882                 for (i = 0; i < 16; i++) {
883                         QPRINTK(qdev, RX_STATUS, DEBUG,
884                                 "lbq: try cleaning clean_idx = %d.\n",
885                                 clean_idx);
886                         lbq_desc = &rx_ring->lbq[clean_idx];
887                         if (lbq_desc->p.lbq_page == NULL) {
888                                 QPRINTK(qdev, RX_STATUS, DEBUG,
889                                         "lbq: getting new page for index %d.\n",
890                                         lbq_desc->index);
891                                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
892                                 if (lbq_desc->p.lbq_page == NULL) {
893                                         rx_ring->lbq_clean_idx = clean_idx;
894                                         QPRINTK(qdev, RX_STATUS, ERR,
895                                                 "Couldn't get a page.\n");
896                                         return;
897                                 }
898                                 map = pci_map_page(qdev->pdev,
899                                                    lbq_desc->p.lbq_page,
900                                                    0, PAGE_SIZE,
901                                                    PCI_DMA_FROMDEVICE);
902                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
903                                         rx_ring->lbq_clean_idx = clean_idx;
904                                         put_page(lbq_desc->p.lbq_page);
905                                         lbq_desc->p.lbq_page = NULL;
906                                         QPRINTK(qdev, RX_STATUS, ERR,
907                                                 "PCI mapping failed.\n");
908                                         return;
909                                 }
910                                 pci_unmap_addr_set(lbq_desc, mapaddr, map);
911                                 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
912                                 *lbq_desc->addr = cpu_to_le64(map);
913                         }
914                         clean_idx++;
915                         if (clean_idx == rx_ring->lbq_len)
916                                 clean_idx = 0;
917                 }
918
919                 rx_ring->lbq_clean_idx = clean_idx;
920                 rx_ring->lbq_prod_idx += 16;
921                 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
922                         rx_ring->lbq_prod_idx = 0;
923                 QPRINTK(qdev, RX_STATUS, DEBUG,
924                         "lbq: updating prod idx = %d.\n",
925                         rx_ring->lbq_prod_idx);
926                 ql_write_db_reg(rx_ring->lbq_prod_idx,
927                                 rx_ring->lbq_prod_idx_db_reg);
928                 rx_ring->lbq_free_cnt -= 16;
929         }
930 }
931
932 /* Process (refill) a small buffer queue. */
933 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
934 {
935         int clean_idx = rx_ring->sbq_clean_idx;
936         struct bq_desc *sbq_desc;
937         u64 map;
938         int i;
939
940         while (rx_ring->sbq_free_cnt > 16) {
941                 for (i = 0; i < 16; i++) {
942                         sbq_desc = &rx_ring->sbq[clean_idx];
943                         QPRINTK(qdev, RX_STATUS, DEBUG,
944                                 "sbq: try cleaning clean_idx = %d.\n",
945                                 clean_idx);
946                         if (sbq_desc->p.skb == NULL) {
947                                 QPRINTK(qdev, RX_STATUS, DEBUG,
948                                         "sbq: getting new skb for index %d.\n",
949                                         sbq_desc->index);
950                                 sbq_desc->p.skb =
951                                     netdev_alloc_skb(qdev->ndev,
952                                                      rx_ring->sbq_buf_size);
953                                 if (sbq_desc->p.skb == NULL) {
954                                         QPRINTK(qdev, PROBE, ERR,
955                                                 "Couldn't get an skb.\n");
956                                         rx_ring->sbq_clean_idx = clean_idx;
957                                         return;
958                                 }
959                                 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
960                                 map = pci_map_single(qdev->pdev,
961                                                      sbq_desc->p.skb->data,
962                                                      rx_ring->sbq_buf_size /
963                                                      2, PCI_DMA_FROMDEVICE);
964                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
965                                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
966                                         rx_ring->sbq_clean_idx = clean_idx;
967                                         dev_kfree_skb_any(sbq_desc->p.skb);
968                                         sbq_desc->p.skb = NULL;
969                                         return;
970                                 }
971                                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
972                                 pci_unmap_len_set(sbq_desc, maplen,
973                                                   rx_ring->sbq_buf_size / 2);
974                                 *sbq_desc->addr = cpu_to_le64(map);
975                         }
976
977                         clean_idx++;
978                         if (clean_idx == rx_ring->sbq_len)
979                                 clean_idx = 0;
980                 }
981                 rx_ring->sbq_clean_idx = clean_idx;
982                 rx_ring->sbq_prod_idx += 16;
983                 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
984                         rx_ring->sbq_prod_idx = 0;
985                 QPRINTK(qdev, RX_STATUS, DEBUG,
986                         "sbq: updating prod idx = %d.\n",
987                         rx_ring->sbq_prod_idx);
988                 ql_write_db_reg(rx_ring->sbq_prod_idx,
989                                 rx_ring->sbq_prod_idx_db_reg);
990
991                 rx_ring->sbq_free_cnt -= 16;
992         }
993 }
994
995 static void ql_update_buffer_queues(struct ql_adapter *qdev,
996                                     struct rx_ring *rx_ring)
997 {
998         ql_update_sbq(qdev, rx_ring);
999         ql_update_lbq(qdev, rx_ring);
1000 }
1001
1002 /* Unmaps tx buffers.  Can be called from send() if a pci mapping
1003  * fails at some stage, or from the interrupt when a tx completes.
1004  */
1005 static void ql_unmap_send(struct ql_adapter *qdev,
1006                           struct tx_ring_desc *tx_ring_desc, int mapped)
1007 {
1008         int i;
1009         for (i = 0; i < mapped; i++) {
1010                 if (i == 0 || (i == 7 && mapped > 7)) {
1011                         /*
1012                          * Unmap the skb->data area, or the
1013                          * external sglist (AKA the Outbound
1014                          * Address List (OAL)).
1015                          * If its the zeroeth element, then it's
1016                          * the skb->data area.  If it's the 7th
1017                          * element and there is more than 6 frags,
1018                          * then its an OAL.
1019                          */
1020                         if (i == 7) {
1021                                 QPRINTK(qdev, TX_DONE, DEBUG,
1022                                         "unmapping OAL area.\n");
1023                         }
1024                         pci_unmap_single(qdev->pdev,
1025                                          pci_unmap_addr(&tx_ring_desc->map[i],
1026                                                         mapaddr),
1027                                          pci_unmap_len(&tx_ring_desc->map[i],
1028                                                        maplen),
1029                                          PCI_DMA_TODEVICE);
1030                 } else {
1031                         QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1032                                 i);
1033                         pci_unmap_page(qdev->pdev,
1034                                        pci_unmap_addr(&tx_ring_desc->map[i],
1035                                                       mapaddr),
1036                                        pci_unmap_len(&tx_ring_desc->map[i],
1037                                                      maplen), PCI_DMA_TODEVICE);
1038                 }
1039         }
1040
1041 }
1042
1043 /* Map the buffers for this transmit.  This will return
1044  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1045  */
1046 static int ql_map_send(struct ql_adapter *qdev,
1047                        struct ob_mac_iocb_req *mac_iocb_ptr,
1048                        struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1049 {
1050         int len = skb_headlen(skb);
1051         dma_addr_t map;
1052         int frag_idx, err, map_idx = 0;
1053         struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1054         int frag_cnt = skb_shinfo(skb)->nr_frags;
1055
1056         if (frag_cnt) {
1057                 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1058         }
1059         /*
1060          * Map the skb buffer first.
1061          */
1062         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1063
1064         err = pci_dma_mapping_error(qdev->pdev, map);
1065         if (err) {
1066                 QPRINTK(qdev, TX_QUEUED, ERR,
1067                         "PCI mapping failed with error: %d\n", err);
1068
1069                 return NETDEV_TX_BUSY;
1070         }
1071
1072         tbd->len = cpu_to_le32(len);
1073         tbd->addr = cpu_to_le64(map);
1074         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1075         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1076         map_idx++;
1077
1078         /*
1079          * This loop fills the remainder of the 8 address descriptors
1080          * in the IOCB.  If there are more than 7 fragments, then the
1081          * eighth address desc will point to an external list (OAL).
1082          * When this happens, the remainder of the frags will be stored
1083          * in this list.
1084          */
1085         for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1086                 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1087                 tbd++;
1088                 if (frag_idx == 6 && frag_cnt > 7) {
1089                         /* Let's tack on an sglist.
1090                          * Our control block will now
1091                          * look like this:
1092                          * iocb->seg[0] = skb->data
1093                          * iocb->seg[1] = frag[0]
1094                          * iocb->seg[2] = frag[1]
1095                          * iocb->seg[3] = frag[2]
1096                          * iocb->seg[4] = frag[3]
1097                          * iocb->seg[5] = frag[4]
1098                          * iocb->seg[6] = frag[5]
1099                          * iocb->seg[7] = ptr to OAL (external sglist)
1100                          * oal->seg[0] = frag[6]
1101                          * oal->seg[1] = frag[7]
1102                          * oal->seg[2] = frag[8]
1103                          * oal->seg[3] = frag[9]
1104                          * oal->seg[4] = frag[10]
1105                          *      etc...
1106                          */
1107                         /* Tack on the OAL in the eighth segment of IOCB. */
1108                         map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1109                                              sizeof(struct oal),
1110                                              PCI_DMA_TODEVICE);
1111                         err = pci_dma_mapping_error(qdev->pdev, map);
1112                         if (err) {
1113                                 QPRINTK(qdev, TX_QUEUED, ERR,
1114                                         "PCI mapping outbound address list with error: %d\n",
1115                                         err);
1116                                 goto map_error;
1117                         }
1118
1119                         tbd->addr = cpu_to_le64(map);
1120                         /*
1121                          * The length is the number of fragments
1122                          * that remain to be mapped times the length
1123                          * of our sglist (OAL).
1124                          */
1125                         tbd->len =
1126                             cpu_to_le32((sizeof(struct tx_buf_desc) *
1127                                          (frag_cnt - frag_idx)) | TX_DESC_C);
1128                         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1129                                            map);
1130                         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1131                                           sizeof(struct oal));
1132                         tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1133                         map_idx++;
1134                 }
1135
1136                 map =
1137                     pci_map_page(qdev->pdev, frag->page,
1138                                  frag->page_offset, frag->size,
1139                                  PCI_DMA_TODEVICE);
1140
1141                 err = pci_dma_mapping_error(qdev->pdev, map);
1142                 if (err) {
1143                         QPRINTK(qdev, TX_QUEUED, ERR,
1144                                 "PCI mapping frags failed with error: %d.\n",
1145                                 err);
1146                         goto map_error;
1147                 }
1148
1149                 tbd->addr = cpu_to_le64(map);
1150                 tbd->len = cpu_to_le32(frag->size);
1151                 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1152                 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1153                                   frag->size);
1154
1155         }
1156         /* Save the number of segments we've mapped. */
1157         tx_ring_desc->map_cnt = map_idx;
1158         /* Terminate the last segment. */
1159         tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1160         return NETDEV_TX_OK;
1161
1162 map_error:
1163         /*
1164          * If the first frag mapping failed, then i will be zero.
1165          * This causes the unmap of the skb->data area.  Otherwise
1166          * we pass in the number of frags that mapped successfully
1167          * so they can be umapped.
1168          */
1169         ql_unmap_send(qdev, tx_ring_desc, map_idx);
1170         return NETDEV_TX_BUSY;
1171 }
1172
1173 static void ql_realign_skb(struct sk_buff *skb, int len)
1174 {
1175         void *temp_addr = skb->data;
1176
1177         /* Undo the skb_reserve(skb,32) we did before
1178          * giving to hardware, and realign data on
1179          * a 2-byte boundary.
1180          */
1181         skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1182         skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1183         skb_copy_to_linear_data(skb, temp_addr,
1184                 (unsigned int)len);
1185 }
1186
1187 /*
1188  * This function builds an skb for the given inbound
1189  * completion.  It will be rewritten for readability in the near
1190  * future, but for not it works well.
1191  */
1192 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1193                                        struct rx_ring *rx_ring,
1194                                        struct ib_mac_iocb_rsp *ib_mac_rsp)
1195 {
1196         struct bq_desc *lbq_desc;
1197         struct bq_desc *sbq_desc;
1198         struct sk_buff *skb = NULL;
1199         u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1200        u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1201
1202         /*
1203          * Handle the header buffer if present.
1204          */
1205         if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1206             ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1207                 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1208                 /*
1209                  * Headers fit nicely into a small buffer.
1210                  */
1211                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1212                 pci_unmap_single(qdev->pdev,
1213                                 pci_unmap_addr(sbq_desc, mapaddr),
1214                                 pci_unmap_len(sbq_desc, maplen),
1215                                 PCI_DMA_FROMDEVICE);
1216                 skb = sbq_desc->p.skb;
1217                 ql_realign_skb(skb, hdr_len);
1218                 skb_put(skb, hdr_len);
1219                 sbq_desc->p.skb = NULL;
1220         }
1221
1222         /*
1223          * Handle the data buffer(s).
1224          */
1225         if (unlikely(!length)) {        /* Is there data too? */
1226                 QPRINTK(qdev, RX_STATUS, DEBUG,
1227                         "No Data buffer in this packet.\n");
1228                 return skb;
1229         }
1230
1231         if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1232                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1233                         QPRINTK(qdev, RX_STATUS, DEBUG,
1234                                 "Headers in small, data of %d bytes in small, combine them.\n", length);
1235                         /*
1236                          * Data is less than small buffer size so it's
1237                          * stuffed in a small buffer.
1238                          * For this case we append the data
1239                          * from the "data" small buffer to the "header" small
1240                          * buffer.
1241                          */
1242                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1243                         pci_dma_sync_single_for_cpu(qdev->pdev,
1244                                                     pci_unmap_addr
1245                                                     (sbq_desc, mapaddr),
1246                                                     pci_unmap_len
1247                                                     (sbq_desc, maplen),
1248                                                     PCI_DMA_FROMDEVICE);
1249                         memcpy(skb_put(skb, length),
1250                                sbq_desc->p.skb->data, length);
1251                         pci_dma_sync_single_for_device(qdev->pdev,
1252                                                        pci_unmap_addr
1253                                                        (sbq_desc,
1254                                                         mapaddr),
1255                                                        pci_unmap_len
1256                                                        (sbq_desc,
1257                                                         maplen),
1258                                                        PCI_DMA_FROMDEVICE);
1259                 } else {
1260                         QPRINTK(qdev, RX_STATUS, DEBUG,
1261                                 "%d bytes in a single small buffer.\n", length);
1262                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1263                         skb = sbq_desc->p.skb;
1264                         ql_realign_skb(skb, length);
1265                         skb_put(skb, length);
1266                         pci_unmap_single(qdev->pdev,
1267                                          pci_unmap_addr(sbq_desc,
1268                                                         mapaddr),
1269                                          pci_unmap_len(sbq_desc,
1270                                                        maplen),
1271                                          PCI_DMA_FROMDEVICE);
1272                         sbq_desc->p.skb = NULL;
1273                 }
1274         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1275                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1276                         QPRINTK(qdev, RX_STATUS, DEBUG,
1277                                 "Header in small, %d bytes in large. Chain large to small!\n", length);
1278                         /*
1279                          * The data is in a single large buffer.  We
1280                          * chain it to the header buffer's skb and let
1281                          * it rip.
1282                          */
1283                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1284                         pci_unmap_page(qdev->pdev,
1285                                        pci_unmap_addr(lbq_desc,
1286                                                       mapaddr),
1287                                        pci_unmap_len(lbq_desc, maplen),
1288                                        PCI_DMA_FROMDEVICE);
1289                         QPRINTK(qdev, RX_STATUS, DEBUG,
1290                                 "Chaining page to skb.\n");
1291                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1292                                            0, length);
1293                         skb->len += length;
1294                         skb->data_len += length;
1295                         skb->truesize += length;
1296                         lbq_desc->p.lbq_page = NULL;
1297                 } else {
1298                         /*
1299                          * The headers and data are in a single large buffer. We
1300                          * copy it to a new skb and let it go. This can happen with
1301                          * jumbo mtu on a non-TCP/UDP frame.
1302                          */
1303                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1304                         skb = netdev_alloc_skb(qdev->ndev, length);
1305                         if (skb == NULL) {
1306                                 QPRINTK(qdev, PROBE, DEBUG,
1307                                         "No skb available, drop the packet.\n");
1308                                 return NULL;
1309                         }
1310                         pci_unmap_page(qdev->pdev,
1311                                        pci_unmap_addr(lbq_desc,
1312                                                       mapaddr),
1313                                        pci_unmap_len(lbq_desc, maplen),
1314                                        PCI_DMA_FROMDEVICE);
1315                         skb_reserve(skb, NET_IP_ALIGN);
1316                         QPRINTK(qdev, RX_STATUS, DEBUG,
1317                                 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1318                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1319                                            0, length);
1320                         skb->len += length;
1321                         skb->data_len += length;
1322                         skb->truesize += length;
1323                         length -= length;
1324                         lbq_desc->p.lbq_page = NULL;
1325                         __pskb_pull_tail(skb,
1326                                 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1327                                 VLAN_ETH_HLEN : ETH_HLEN);
1328                 }
1329         } else {
1330                 /*
1331                  * The data is in a chain of large buffers
1332                  * pointed to by a small buffer.  We loop
1333                  * thru and chain them to the our small header
1334                  * buffer's skb.
1335                  * frags:  There are 18 max frags and our small
1336                  *         buffer will hold 32 of them. The thing is,
1337                  *         we'll use 3 max for our 9000 byte jumbo
1338                  *         frames.  If the MTU goes up we could
1339                  *          eventually be in trouble.
1340                  */
1341                 int size, offset, i = 0;
1342                 __le64 *bq, bq_array[8];
1343                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1344                 pci_unmap_single(qdev->pdev,
1345                                  pci_unmap_addr(sbq_desc, mapaddr),
1346                                  pci_unmap_len(sbq_desc, maplen),
1347                                  PCI_DMA_FROMDEVICE);
1348                 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1349                         /*
1350                          * This is an non TCP/UDP IP frame, so
1351                          * the headers aren't split into a small
1352                          * buffer.  We have to use the small buffer
1353                          * that contains our sg list as our skb to
1354                          * send upstairs. Copy the sg list here to
1355                          * a local buffer and use it to find the
1356                          * pages to chain.
1357                          */
1358                         QPRINTK(qdev, RX_STATUS, DEBUG,
1359                                 "%d bytes of headers & data in chain of large.\n", length);
1360                         skb = sbq_desc->p.skb;
1361                         bq = &bq_array[0];
1362                         memcpy(bq, skb->data, sizeof(bq_array));
1363                         sbq_desc->p.skb = NULL;
1364                         skb_reserve(skb, NET_IP_ALIGN);
1365                 } else {
1366                         QPRINTK(qdev, RX_STATUS, DEBUG,
1367                                 "Headers in small, %d bytes of data in chain of large.\n", length);
1368                         bq = (__le64 *)sbq_desc->p.skb->data;
1369                 }
1370                 while (length > 0) {
1371                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1372                         pci_unmap_page(qdev->pdev,
1373                                        pci_unmap_addr(lbq_desc,
1374                                                       mapaddr),
1375                                        pci_unmap_len(lbq_desc,
1376                                                      maplen),
1377                                        PCI_DMA_FROMDEVICE);
1378                         size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1379                         offset = 0;
1380
1381                         QPRINTK(qdev, RX_STATUS, DEBUG,
1382                                 "Adding page %d to skb for %d bytes.\n",
1383                                 i, size);
1384                         skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1385                                            offset, size);
1386                         skb->len += size;
1387                         skb->data_len += size;
1388                         skb->truesize += size;
1389                         length -= size;
1390                         lbq_desc->p.lbq_page = NULL;
1391                         bq++;
1392                         i++;
1393                 }
1394                 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1395                                 VLAN_ETH_HLEN : ETH_HLEN);
1396         }
1397         return skb;
1398 }
1399
1400 /* Process an inbound completion from an rx ring. */
1401 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1402                                    struct rx_ring *rx_ring,
1403                                    struct ib_mac_iocb_rsp *ib_mac_rsp)
1404 {
1405         struct net_device *ndev = qdev->ndev;
1406         struct sk_buff *skb = NULL;
1407
1408         QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1409
1410         skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1411         if (unlikely(!skb)) {
1412                 QPRINTK(qdev, RX_STATUS, DEBUG,
1413                         "No skb available, drop packet.\n");
1414                 return;
1415         }
1416
1417         prefetch(skb->data);
1418         skb->dev = ndev;
1419         if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1420                 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1421                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1422                         IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1423                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1424                         IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1425                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1426                         IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1427         }
1428         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1429                 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1430         }
1431         if (ib_mac_rsp->flags1 & (IB_MAC_IOCB_RSP_IE | IB_MAC_IOCB_RSP_TE)) {
1432                 QPRINTK(qdev, RX_STATUS, ERR,
1433                         "Bad checksum for this %s packet.\n",
1434                         ((ib_mac_rsp->
1435                           flags2 & IB_MAC_IOCB_RSP_T) ? "TCP" : "UDP"));
1436                 skb->ip_summed = CHECKSUM_NONE;
1437         } else if (qdev->rx_csum &&
1438                    ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ||
1439                     ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1440                      !(ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU)))) {
1441                 QPRINTK(qdev, RX_STATUS, DEBUG, "RX checksum done!\n");
1442                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1443         }
1444         qdev->stats.rx_packets++;
1445         qdev->stats.rx_bytes += skb->len;
1446         skb->protocol = eth_type_trans(skb, ndev);
1447         skb_record_rx_queue(skb, rx_ring - &qdev->rx_ring[0]);
1448         if (qdev->vlgrp && (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)) {
1449                 QPRINTK(qdev, RX_STATUS, DEBUG,
1450                         "Passing a VLAN packet upstream.\n");
1451                 vlan_hwaccel_receive_skb(skb, qdev->vlgrp,
1452                                 le16_to_cpu(ib_mac_rsp->vlan_id));
1453         } else {
1454                 QPRINTK(qdev, RX_STATUS, DEBUG,
1455                         "Passing a normal packet upstream.\n");
1456                 netif_receive_skb(skb);
1457         }
1458 }
1459
1460 /* Process an outbound completion from an rx ring. */
1461 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1462                                    struct ob_mac_iocb_rsp *mac_rsp)
1463 {
1464         struct tx_ring *tx_ring;
1465         struct tx_ring_desc *tx_ring_desc;
1466
1467         QL_DUMP_OB_MAC_RSP(mac_rsp);
1468         tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1469         tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1470         ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1471         qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1472         qdev->stats.tx_packets++;
1473         dev_kfree_skb(tx_ring_desc->skb);
1474         tx_ring_desc->skb = NULL;
1475
1476         if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1477                                         OB_MAC_IOCB_RSP_S |
1478                                         OB_MAC_IOCB_RSP_L |
1479                                         OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1480                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1481                         QPRINTK(qdev, TX_DONE, WARNING,
1482                                 "Total descriptor length did not match transfer length.\n");
1483                 }
1484                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1485                         QPRINTK(qdev, TX_DONE, WARNING,
1486                                 "Frame too short to be legal, not sent.\n");
1487                 }
1488                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1489                         QPRINTK(qdev, TX_DONE, WARNING,
1490                                 "Frame too long, but sent anyway.\n");
1491                 }
1492                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1493                         QPRINTK(qdev, TX_DONE, WARNING,
1494                                 "PCI backplane error. Frame not sent.\n");
1495                 }
1496         }
1497         atomic_inc(&tx_ring->tx_count);
1498 }
1499
1500 /* Fire up a handler to reset the MPI processor. */
1501 void ql_queue_fw_error(struct ql_adapter *qdev)
1502 {
1503         netif_stop_queue(qdev->ndev);
1504         netif_carrier_off(qdev->ndev);
1505         queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1506 }
1507
1508 void ql_queue_asic_error(struct ql_adapter *qdev)
1509 {
1510         netif_stop_queue(qdev->ndev);
1511         netif_carrier_off(qdev->ndev);
1512         ql_disable_interrupts(qdev);
1513         /* Clear adapter up bit to signal the recovery
1514          * process that it shouldn't kill the reset worker
1515          * thread
1516          */
1517         clear_bit(QL_ADAPTER_UP, &qdev->flags);
1518         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1519 }
1520
1521 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1522                                     struct ib_ae_iocb_rsp *ib_ae_rsp)
1523 {
1524         switch (ib_ae_rsp->event) {
1525         case MGMT_ERR_EVENT:
1526                 QPRINTK(qdev, RX_ERR, ERR,
1527                         "Management Processor Fatal Error.\n");
1528                 ql_queue_fw_error(qdev);
1529                 return;
1530
1531         case CAM_LOOKUP_ERR_EVENT:
1532                 QPRINTK(qdev, LINK, ERR,
1533                         "Multiple CAM hits lookup occurred.\n");
1534                 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1535                 ql_queue_asic_error(qdev);
1536                 return;
1537
1538         case SOFT_ECC_ERROR_EVENT:
1539                 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1540                 ql_queue_asic_error(qdev);
1541                 break;
1542
1543         case PCI_ERR_ANON_BUF_RD:
1544                 QPRINTK(qdev, RX_ERR, ERR,
1545                         "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1546                         ib_ae_rsp->q_id);
1547                 ql_queue_asic_error(qdev);
1548                 break;
1549
1550         default:
1551                 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1552                         ib_ae_rsp->event);
1553                 ql_queue_asic_error(qdev);
1554                 break;
1555         }
1556 }
1557
1558 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1559 {
1560         struct ql_adapter *qdev = rx_ring->qdev;
1561         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1562         struct ob_mac_iocb_rsp *net_rsp = NULL;
1563         int count = 0;
1564
1565         /* While there are entries in the completion queue. */
1566         while (prod != rx_ring->cnsmr_idx) {
1567
1568                 QPRINTK(qdev, RX_STATUS, DEBUG,
1569                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1570                         prod, rx_ring->cnsmr_idx);
1571
1572                 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1573                 rmb();
1574                 switch (net_rsp->opcode) {
1575
1576                 case OPCODE_OB_MAC_TSO_IOCB:
1577                 case OPCODE_OB_MAC_IOCB:
1578                         ql_process_mac_tx_intr(qdev, net_rsp);
1579                         break;
1580                 default:
1581                         QPRINTK(qdev, RX_STATUS, DEBUG,
1582                                 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1583                                 net_rsp->opcode);
1584                 }
1585                 count++;
1586                 ql_update_cq(rx_ring);
1587                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1588         }
1589         ql_write_cq_idx(rx_ring);
1590         if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) {
1591                 struct tx_ring *tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1592                 if (atomic_read(&tx_ring->queue_stopped) &&
1593                     (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1594                         /*
1595                          * The queue got stopped because the tx_ring was full.
1596                          * Wake it up, because it's now at least 25% empty.
1597                          */
1598                         netif_wake_queue(qdev->ndev);
1599         }
1600
1601         return count;
1602 }
1603
1604 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1605 {
1606         struct ql_adapter *qdev = rx_ring->qdev;
1607         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1608         struct ql_net_rsp_iocb *net_rsp;
1609         int count = 0;
1610
1611         /* While there are entries in the completion queue. */
1612         while (prod != rx_ring->cnsmr_idx) {
1613
1614                 QPRINTK(qdev, RX_STATUS, DEBUG,
1615                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1616                         prod, rx_ring->cnsmr_idx);
1617
1618                 net_rsp = rx_ring->curr_entry;
1619                 rmb();
1620                 switch (net_rsp->opcode) {
1621                 case OPCODE_IB_MAC_IOCB:
1622                         ql_process_mac_rx_intr(qdev, rx_ring,
1623                                                (struct ib_mac_iocb_rsp *)
1624                                                net_rsp);
1625                         break;
1626
1627                 case OPCODE_IB_AE_IOCB:
1628                         ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1629                                                 net_rsp);
1630                         break;
1631                 default:
1632                         {
1633                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1634                                         "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1635                                         net_rsp->opcode);
1636                         }
1637                 }
1638                 count++;
1639                 ql_update_cq(rx_ring);
1640                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1641                 if (count == budget)
1642                         break;
1643         }
1644         ql_update_buffer_queues(qdev, rx_ring);
1645         ql_write_cq_idx(rx_ring);
1646         return count;
1647 }
1648
1649 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1650 {
1651         struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1652         struct ql_adapter *qdev = rx_ring->qdev;
1653         int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1654
1655         QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1656                 rx_ring->cq_id);
1657
1658         if (work_done < budget) {
1659                 __napi_complete(napi);
1660                 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1661         }
1662         return work_done;
1663 }
1664
1665 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1666 {
1667         struct ql_adapter *qdev = netdev_priv(ndev);
1668
1669         qdev->vlgrp = grp;
1670         if (grp) {
1671                 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1672                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1673                            NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1674         } else {
1675                 QPRINTK(qdev, IFUP, DEBUG,
1676                         "Turning off VLAN in NIC_RCV_CFG.\n");
1677                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1678         }
1679 }
1680
1681 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1682 {
1683         struct ql_adapter *qdev = netdev_priv(ndev);
1684         u32 enable_bit = MAC_ADDR_E;
1685         int status;
1686
1687         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1688         if (status)
1689                 return;
1690         spin_lock(&qdev->hw_lock);
1691         if (ql_set_mac_addr_reg
1692             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1693                 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1694         }
1695         spin_unlock(&qdev->hw_lock);
1696         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1697 }
1698
1699 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1700 {
1701         struct ql_adapter *qdev = netdev_priv(ndev);
1702         u32 enable_bit = 0;
1703         int status;
1704
1705         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1706         if (status)
1707                 return;
1708
1709         spin_lock(&qdev->hw_lock);
1710         if (ql_set_mac_addr_reg
1711             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1712                 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1713         }
1714         spin_unlock(&qdev->hw_lock);
1715         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1716
1717 }
1718
1719 /* Worker thread to process a given rx_ring that is dedicated
1720  * to outbound completions.
1721  */
1722 static void ql_tx_clean(struct work_struct *work)
1723 {
1724         struct rx_ring *rx_ring =
1725             container_of(work, struct rx_ring, rx_work.work);
1726         ql_clean_outbound_rx_ring(rx_ring);
1727         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1728
1729 }
1730
1731 /* Worker thread to process a given rx_ring that is dedicated
1732  * to inbound completions.
1733  */
1734 static void ql_rx_clean(struct work_struct *work)
1735 {
1736         struct rx_ring *rx_ring =
1737             container_of(work, struct rx_ring, rx_work.work);
1738         ql_clean_inbound_rx_ring(rx_ring, 64);
1739         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1740 }
1741
1742 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1743 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1744 {
1745         struct rx_ring *rx_ring = dev_id;
1746         queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1747                               &rx_ring->rx_work, 0);
1748         return IRQ_HANDLED;
1749 }
1750
1751 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1752 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1753 {
1754         struct rx_ring *rx_ring = dev_id;
1755         napi_schedule(&rx_ring->napi);
1756         return IRQ_HANDLED;
1757 }
1758
1759 /* This handles a fatal error, MPI activity, and the default
1760  * rx_ring in an MSI-X multiple vector environment.
1761  * In MSI/Legacy environment it also process the rest of
1762  * the rx_rings.
1763  */
1764 static irqreturn_t qlge_isr(int irq, void *dev_id)
1765 {
1766         struct rx_ring *rx_ring = dev_id;
1767         struct ql_adapter *qdev = rx_ring->qdev;
1768         struct intr_context *intr_context = &qdev->intr_context[0];
1769         u32 var;
1770         int i;
1771         int work_done = 0;
1772
1773         spin_lock(&qdev->hw_lock);
1774         if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1775                 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1776                 spin_unlock(&qdev->hw_lock);
1777                 return IRQ_NONE;
1778         }
1779         spin_unlock(&qdev->hw_lock);
1780
1781         var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1782
1783         /*
1784          * Check for fatal error.
1785          */
1786         if (var & STS_FE) {
1787                 ql_queue_asic_error(qdev);
1788                 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1789                 var = ql_read32(qdev, ERR_STS);
1790                 QPRINTK(qdev, INTR, ERR,
1791                         "Resetting chip. Error Status Register = 0x%x\n", var);
1792                 return IRQ_HANDLED;
1793         }
1794
1795         /*
1796          * Check MPI processor activity.
1797          */
1798         if (var & STS_PI) {
1799                 /*
1800                  * We've got an async event or mailbox completion.
1801                  * Handle it and clear the source of the interrupt.
1802                  */
1803                 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1804                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1805                 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1806                                       &qdev->mpi_work, 0);
1807                 work_done++;
1808         }
1809
1810         /*
1811          * Check the default queue and wake handler if active.
1812          */
1813         rx_ring = &qdev->rx_ring[0];
1814         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1815                 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1816                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1817                 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1818                                       &rx_ring->rx_work, 0);
1819                 work_done++;
1820         }
1821
1822         if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1823                 /*
1824                  * Start the DPC for each active queue.
1825                  */
1826                 for (i = 1; i < qdev->rx_ring_count; i++) {
1827                         rx_ring = &qdev->rx_ring[i];
1828                         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1829                             rx_ring->cnsmr_idx) {
1830                                 QPRINTK(qdev, INTR, INFO,
1831                                         "Waking handler for rx_ring[%d].\n", i);
1832                                 ql_disable_completion_interrupt(qdev,
1833                                                                 intr_context->
1834                                                                 intr);
1835                                 if (i < qdev->rss_ring_first_cq_id)
1836                                         queue_delayed_work_on(rx_ring->cpu,
1837                                                               qdev->q_workqueue,
1838                                                               &rx_ring->rx_work,
1839                                                               0);
1840                                 else
1841                                         napi_schedule(&rx_ring->napi);
1842                                 work_done++;
1843                         }
1844                 }
1845         }
1846         ql_enable_completion_interrupt(qdev, intr_context->intr);
1847         return work_done ? IRQ_HANDLED : IRQ_NONE;
1848 }
1849
1850 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1851 {
1852
1853         if (skb_is_gso(skb)) {
1854                 int err;
1855                 if (skb_header_cloned(skb)) {
1856                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1857                         if (err)
1858                                 return err;
1859                 }
1860
1861                 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1862                 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1863                 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1864                 mac_iocb_ptr->total_hdrs_len =
1865                     cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1866                 mac_iocb_ptr->net_trans_offset =
1867                     cpu_to_le16(skb_network_offset(skb) |
1868                                 skb_transport_offset(skb)
1869                                 << OB_MAC_TRANSPORT_HDR_SHIFT);
1870                 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1871                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1872                 if (likely(skb->protocol == htons(ETH_P_IP))) {
1873                         struct iphdr *iph = ip_hdr(skb);
1874                         iph->check = 0;
1875                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1876                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1877                                                                  iph->daddr, 0,
1878                                                                  IPPROTO_TCP,
1879                                                                  0);
1880                 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1881                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
1882                         tcp_hdr(skb)->check =
1883                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1884                                              &ipv6_hdr(skb)->daddr,
1885                                              0, IPPROTO_TCP, 0);
1886                 }
1887                 return 1;
1888         }
1889         return 0;
1890 }
1891
1892 static void ql_hw_csum_setup(struct sk_buff *skb,
1893                              struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1894 {
1895         int len;
1896         struct iphdr *iph = ip_hdr(skb);
1897         __sum16 *check;
1898         mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1899         mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1900         mac_iocb_ptr->net_trans_offset =
1901                 cpu_to_le16(skb_network_offset(skb) |
1902                 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
1903
1904         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1905         len = (ntohs(iph->tot_len) - (iph->ihl << 2));
1906         if (likely(iph->protocol == IPPROTO_TCP)) {
1907                 check = &(tcp_hdr(skb)->check);
1908                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
1909                 mac_iocb_ptr->total_hdrs_len =
1910                     cpu_to_le16(skb_transport_offset(skb) +
1911                                 (tcp_hdr(skb)->doff << 2));
1912         } else {
1913                 check = &(udp_hdr(skb)->check);
1914                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
1915                 mac_iocb_ptr->total_hdrs_len =
1916                     cpu_to_le16(skb_transport_offset(skb) +
1917                                 sizeof(struct udphdr));
1918         }
1919         *check = ~csum_tcpudp_magic(iph->saddr,
1920                                     iph->daddr, len, iph->protocol, 0);
1921 }
1922
1923 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
1924 {
1925         struct tx_ring_desc *tx_ring_desc;
1926         struct ob_mac_iocb_req *mac_iocb_ptr;
1927         struct ql_adapter *qdev = netdev_priv(ndev);
1928         int tso;
1929         struct tx_ring *tx_ring;
1930         u32 tx_ring_idx = (u32) QL_TXQ_IDX(qdev, skb);
1931
1932         tx_ring = &qdev->tx_ring[tx_ring_idx];
1933
1934         if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
1935                 QPRINTK(qdev, TX_QUEUED, INFO,
1936                         "%s: shutting down tx queue %d du to lack of resources.\n",
1937                         __func__, tx_ring_idx);
1938                 netif_stop_queue(ndev);
1939                 atomic_inc(&tx_ring->queue_stopped);
1940                 return NETDEV_TX_BUSY;
1941         }
1942         tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
1943         mac_iocb_ptr = tx_ring_desc->queue_entry;
1944         memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
1945
1946         mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
1947         mac_iocb_ptr->tid = tx_ring_desc->index;
1948         /* We use the upper 32-bits to store the tx queue for this IO.
1949          * When we get the completion we can use it to establish the context.
1950          */
1951         mac_iocb_ptr->txq_idx = tx_ring_idx;
1952         tx_ring_desc->skb = skb;
1953
1954         mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
1955
1956         if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
1957                 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
1958                         vlan_tx_tag_get(skb));
1959                 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
1960                 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
1961         }
1962         tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1963         if (tso < 0) {
1964                 dev_kfree_skb_any(skb);
1965                 return NETDEV_TX_OK;
1966         } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
1967                 ql_hw_csum_setup(skb,
1968                                  (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1969         }
1970         if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
1971                         NETDEV_TX_OK) {
1972                 QPRINTK(qdev, TX_QUEUED, ERR,
1973                                 "Could not map the segments.\n");
1974                 return NETDEV_TX_BUSY;
1975         }
1976         QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
1977         tx_ring->prod_idx++;
1978         if (tx_ring->prod_idx == tx_ring->wq_len)
1979                 tx_ring->prod_idx = 0;
1980         wmb();
1981
1982         ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
1983         ndev->trans_start = jiffies;
1984         QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
1985                 tx_ring->prod_idx, skb->len);
1986
1987         atomic_dec(&tx_ring->tx_count);
1988         return NETDEV_TX_OK;
1989 }
1990
1991 static void ql_free_shadow_space(struct ql_adapter *qdev)
1992 {
1993         if (qdev->rx_ring_shadow_reg_area) {
1994                 pci_free_consistent(qdev->pdev,
1995                                     PAGE_SIZE,
1996                                     qdev->rx_ring_shadow_reg_area,
1997                                     qdev->rx_ring_shadow_reg_dma);
1998                 qdev->rx_ring_shadow_reg_area = NULL;
1999         }
2000         if (qdev->tx_ring_shadow_reg_area) {
2001                 pci_free_consistent(qdev->pdev,
2002                                     PAGE_SIZE,
2003                                     qdev->tx_ring_shadow_reg_area,
2004                                     qdev->tx_ring_shadow_reg_dma);
2005                 qdev->tx_ring_shadow_reg_area = NULL;
2006         }
2007 }
2008
2009 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2010 {
2011         qdev->rx_ring_shadow_reg_area =
2012             pci_alloc_consistent(qdev->pdev,
2013                                  PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2014         if (qdev->rx_ring_shadow_reg_area == NULL) {
2015                 QPRINTK(qdev, IFUP, ERR,
2016                         "Allocation of RX shadow space failed.\n");
2017                 return -ENOMEM;
2018         }
2019         qdev->tx_ring_shadow_reg_area =
2020             pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2021                                  &qdev->tx_ring_shadow_reg_dma);
2022         if (qdev->tx_ring_shadow_reg_area == NULL) {
2023                 QPRINTK(qdev, IFUP, ERR,
2024                         "Allocation of TX shadow space failed.\n");
2025                 goto err_wqp_sh_area;
2026         }
2027         return 0;
2028
2029 err_wqp_sh_area:
2030         pci_free_consistent(qdev->pdev,
2031                             PAGE_SIZE,
2032                             qdev->rx_ring_shadow_reg_area,
2033                             qdev->rx_ring_shadow_reg_dma);
2034         return -ENOMEM;
2035 }
2036
2037 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2038 {
2039         struct tx_ring_desc *tx_ring_desc;
2040         int i;
2041         struct ob_mac_iocb_req *mac_iocb_ptr;
2042
2043         mac_iocb_ptr = tx_ring->wq_base;
2044         tx_ring_desc = tx_ring->q;
2045         for (i = 0; i < tx_ring->wq_len; i++) {
2046                 tx_ring_desc->index = i;
2047                 tx_ring_desc->skb = NULL;
2048                 tx_ring_desc->queue_entry = mac_iocb_ptr;
2049                 mac_iocb_ptr++;
2050                 tx_ring_desc++;
2051         }
2052         atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2053         atomic_set(&tx_ring->queue_stopped, 0);
2054 }
2055
2056 static void ql_free_tx_resources(struct ql_adapter *qdev,
2057                                  struct tx_ring *tx_ring)
2058 {
2059         if (tx_ring->wq_base) {
2060                 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2061                                     tx_ring->wq_base, tx_ring->wq_base_dma);
2062                 tx_ring->wq_base = NULL;
2063         }
2064         kfree(tx_ring->q);
2065         tx_ring->q = NULL;
2066 }
2067
2068 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2069                                  struct tx_ring *tx_ring)
2070 {
2071         tx_ring->wq_base =
2072             pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2073                                  &tx_ring->wq_base_dma);
2074
2075         if ((tx_ring->wq_base == NULL)
2076             || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2077                 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2078                 return -ENOMEM;
2079         }
2080         tx_ring->q =
2081             kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2082         if (tx_ring->q == NULL)
2083                 goto err;
2084
2085         return 0;
2086 err:
2087         pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2088                             tx_ring->wq_base, tx_ring->wq_base_dma);
2089         return -ENOMEM;
2090 }
2091
2092 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2093 {
2094         int i;
2095         struct bq_desc *lbq_desc;
2096
2097         for (i = 0; i < rx_ring->lbq_len; i++) {
2098                 lbq_desc = &rx_ring->lbq[i];
2099                 if (lbq_desc->p.lbq_page) {
2100                         pci_unmap_page(qdev->pdev,
2101                                        pci_unmap_addr(lbq_desc, mapaddr),
2102                                        pci_unmap_len(lbq_desc, maplen),
2103                                        PCI_DMA_FROMDEVICE);
2104
2105                         put_page(lbq_desc->p.lbq_page);
2106                         lbq_desc->p.lbq_page = NULL;
2107                 }
2108         }
2109 }
2110
2111 /*
2112  * Allocate and map a page for each element of the lbq.
2113  */
2114 static int ql_alloc_lbq_buffers(struct ql_adapter *qdev,
2115                                 struct rx_ring *rx_ring)
2116 {
2117         int i;
2118         struct bq_desc *lbq_desc;
2119         u64 map;
2120         __le64 *bq = rx_ring->lbq_base;
2121
2122         for (i = 0; i < rx_ring->lbq_len; i++) {
2123                 lbq_desc = &rx_ring->lbq[i];
2124                 memset(lbq_desc, 0, sizeof(lbq_desc));
2125                 lbq_desc->addr = bq;
2126                 lbq_desc->index = i;
2127                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
2128                 if (unlikely(!lbq_desc->p.lbq_page)) {
2129                         QPRINTK(qdev, IFUP, ERR, "failed alloc_page().\n");
2130                         goto mem_error;
2131                 } else {
2132                         map = pci_map_page(qdev->pdev,
2133                                            lbq_desc->p.lbq_page,
2134                                            0, PAGE_SIZE, PCI_DMA_FROMDEVICE);
2135                         if (pci_dma_mapping_error(qdev->pdev, map)) {
2136                                 QPRINTK(qdev, IFUP, ERR,
2137                                         "PCI mapping failed.\n");
2138                                 goto mem_error;
2139                         }
2140                         pci_unmap_addr_set(lbq_desc, mapaddr, map);
2141                         pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
2142                         *lbq_desc->addr = cpu_to_le64(map);
2143                 }
2144                 bq++;
2145         }
2146         return 0;
2147 mem_error:
2148         ql_free_lbq_buffers(qdev, rx_ring);
2149         return -ENOMEM;
2150 }
2151
2152 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2153 {
2154         int i;
2155         struct bq_desc *sbq_desc;
2156
2157         for (i = 0; i < rx_ring->sbq_len; i++) {
2158                 sbq_desc = &rx_ring->sbq[i];
2159                 if (sbq_desc == NULL) {
2160                         QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2161                         return;
2162                 }
2163                 if (sbq_desc->p.skb) {
2164                         pci_unmap_single(qdev->pdev,
2165                                          pci_unmap_addr(sbq_desc, mapaddr),
2166                                          pci_unmap_len(sbq_desc, maplen),
2167                                          PCI_DMA_FROMDEVICE);
2168                         dev_kfree_skb(sbq_desc->p.skb);
2169                         sbq_desc->p.skb = NULL;
2170                 }
2171         }
2172 }
2173
2174 /* Allocate and map an skb for each element of the sbq. */
2175 static int ql_alloc_sbq_buffers(struct ql_adapter *qdev,
2176                                 struct rx_ring *rx_ring)
2177 {
2178         int i;
2179         struct bq_desc *sbq_desc;
2180         struct sk_buff *skb;
2181         u64 map;
2182         __le64 *bq = rx_ring->sbq_base;
2183
2184         for (i = 0; i < rx_ring->sbq_len; i++) {
2185                 sbq_desc = &rx_ring->sbq[i];
2186                 memset(sbq_desc, 0, sizeof(sbq_desc));
2187                 sbq_desc->index = i;
2188                 sbq_desc->addr = bq;
2189                 skb = netdev_alloc_skb(qdev->ndev, rx_ring->sbq_buf_size);
2190                 if (unlikely(!skb)) {
2191                         /* Better luck next round */
2192                         QPRINTK(qdev, IFUP, ERR,
2193                                 "small buff alloc failed for %d bytes at index %d.\n",
2194                                 rx_ring->sbq_buf_size, i);
2195                         goto mem_err;
2196                 }
2197                 skb_reserve(skb, QLGE_SB_PAD);
2198                 sbq_desc->p.skb = skb;
2199                 /*
2200                  * Map only half the buffer. Because the
2201                  * other half may get some data copied to it
2202                  * when the completion arrives.
2203                  */
2204                 map = pci_map_single(qdev->pdev,
2205                                      skb->data,
2206                                      rx_ring->sbq_buf_size / 2,
2207                                      PCI_DMA_FROMDEVICE);
2208                 if (pci_dma_mapping_error(qdev->pdev, map)) {
2209                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
2210                         goto mem_err;
2211                 }
2212                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
2213                 pci_unmap_len_set(sbq_desc, maplen, rx_ring->sbq_buf_size / 2);
2214                 *sbq_desc->addr = cpu_to_le64(map);
2215                 bq++;
2216         }
2217         return 0;
2218 mem_err:
2219         ql_free_sbq_buffers(qdev, rx_ring);
2220         return -ENOMEM;
2221 }
2222
2223 static void ql_free_rx_resources(struct ql_adapter *qdev,
2224                                  struct rx_ring *rx_ring)
2225 {
2226         if (rx_ring->sbq_len)
2227                 ql_free_sbq_buffers(qdev, rx_ring);
2228         if (rx_ring->lbq_len)
2229                 ql_free_lbq_buffers(qdev, rx_ring);
2230
2231         /* Free the small buffer queue. */
2232         if (rx_ring->sbq_base) {
2233                 pci_free_consistent(qdev->pdev,
2234                                     rx_ring->sbq_size,
2235                                     rx_ring->sbq_base, rx_ring->sbq_base_dma);
2236                 rx_ring->sbq_base = NULL;
2237         }
2238
2239         /* Free the small buffer queue control blocks. */
2240         kfree(rx_ring->sbq);
2241         rx_ring->sbq = NULL;
2242
2243         /* Free the large buffer queue. */
2244         if (rx_ring->lbq_base) {
2245                 pci_free_consistent(qdev->pdev,
2246                                     rx_ring->lbq_size,
2247                                     rx_ring->lbq_base, rx_ring->lbq_base_dma);
2248                 rx_ring->lbq_base = NULL;
2249         }
2250
2251         /* Free the large buffer queue control blocks. */
2252         kfree(rx_ring->lbq);
2253         rx_ring->lbq = NULL;
2254
2255         /* Free the rx queue. */
2256         if (rx_ring->cq_base) {
2257                 pci_free_consistent(qdev->pdev,
2258                                     rx_ring->cq_size,
2259                                     rx_ring->cq_base, rx_ring->cq_base_dma);
2260                 rx_ring->cq_base = NULL;
2261         }
2262 }
2263
2264 /* Allocate queues and buffers for this completions queue based
2265  * on the values in the parameter structure. */
2266 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2267                                  struct rx_ring *rx_ring)
2268 {
2269
2270         /*
2271          * Allocate the completion queue for this rx_ring.
2272          */
2273         rx_ring->cq_base =
2274             pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2275                                  &rx_ring->cq_base_dma);
2276
2277         if (rx_ring->cq_base == NULL) {
2278                 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2279                 return -ENOMEM;
2280         }
2281
2282         if (rx_ring->sbq_len) {
2283                 /*
2284                  * Allocate small buffer queue.
2285                  */
2286                 rx_ring->sbq_base =
2287                     pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2288                                          &rx_ring->sbq_base_dma);
2289
2290                 if (rx_ring->sbq_base == NULL) {
2291                         QPRINTK(qdev, IFUP, ERR,
2292                                 "Small buffer queue allocation failed.\n");
2293                         goto err_mem;
2294                 }
2295
2296                 /*
2297                  * Allocate small buffer queue control blocks.
2298                  */
2299                 rx_ring->sbq =
2300                     kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2301                             GFP_KERNEL);
2302                 if (rx_ring->sbq == NULL) {
2303                         QPRINTK(qdev, IFUP, ERR,
2304                                 "Small buffer queue control block allocation failed.\n");
2305                         goto err_mem;
2306                 }
2307
2308                 if (ql_alloc_sbq_buffers(qdev, rx_ring)) {
2309                         QPRINTK(qdev, IFUP, ERR,
2310                                 "Small buffer allocation failed.\n");
2311                         goto err_mem;
2312                 }
2313         }
2314
2315         if (rx_ring->lbq_len) {
2316                 /*
2317                  * Allocate large buffer queue.
2318                  */
2319                 rx_ring->lbq_base =
2320                     pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2321                                          &rx_ring->lbq_base_dma);
2322
2323                 if (rx_ring->lbq_base == NULL) {
2324                         QPRINTK(qdev, IFUP, ERR,
2325                                 "Large buffer queue allocation failed.\n");
2326                         goto err_mem;
2327                 }
2328                 /*
2329                  * Allocate large buffer queue control blocks.
2330                  */
2331                 rx_ring->lbq =
2332                     kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2333                             GFP_KERNEL);
2334                 if (rx_ring->lbq == NULL) {
2335                         QPRINTK(qdev, IFUP, ERR,
2336                                 "Large buffer queue control block allocation failed.\n");
2337                         goto err_mem;
2338                 }
2339
2340                 /*
2341                  * Allocate the buffers.
2342                  */
2343                 if (ql_alloc_lbq_buffers(qdev, rx_ring)) {
2344                         QPRINTK(qdev, IFUP, ERR,
2345                                 "Large buffer allocation failed.\n");
2346                         goto err_mem;
2347                 }
2348         }
2349
2350         return 0;
2351
2352 err_mem:
2353         ql_free_rx_resources(qdev, rx_ring);
2354         return -ENOMEM;
2355 }
2356
2357 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2358 {
2359         struct tx_ring *tx_ring;
2360         struct tx_ring_desc *tx_ring_desc;
2361         int i, j;
2362
2363         /*
2364          * Loop through all queues and free
2365          * any resources.
2366          */
2367         for (j = 0; j < qdev->tx_ring_count; j++) {
2368                 tx_ring = &qdev->tx_ring[j];
2369                 for (i = 0; i < tx_ring->wq_len; i++) {
2370                         tx_ring_desc = &tx_ring->q[i];
2371                         if (tx_ring_desc && tx_ring_desc->skb) {
2372                                 QPRINTK(qdev, IFDOWN, ERR,
2373                                 "Freeing lost SKB %p, from queue %d, index %d.\n",
2374                                         tx_ring_desc->skb, j,
2375                                         tx_ring_desc->index);
2376                                 ql_unmap_send(qdev, tx_ring_desc,
2377                                               tx_ring_desc->map_cnt);
2378                                 dev_kfree_skb(tx_ring_desc->skb);
2379                                 tx_ring_desc->skb = NULL;
2380                         }
2381                 }
2382         }
2383 }
2384
2385 static void ql_free_mem_resources(struct ql_adapter *qdev)
2386 {
2387         int i;
2388
2389         for (i = 0; i < qdev->tx_ring_count; i++)
2390                 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2391         for (i = 0; i < qdev->rx_ring_count; i++)
2392                 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2393         ql_free_shadow_space(qdev);
2394 }
2395
2396 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2397 {
2398         int i;
2399
2400         /* Allocate space for our shadow registers and such. */
2401         if (ql_alloc_shadow_space(qdev))
2402                 return -ENOMEM;
2403
2404         for (i = 0; i < qdev->rx_ring_count; i++) {
2405                 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2406                         QPRINTK(qdev, IFUP, ERR,
2407                                 "RX resource allocation failed.\n");
2408                         goto err_mem;
2409                 }
2410         }
2411         /* Allocate tx queue resources */
2412         for (i = 0; i < qdev->tx_ring_count; i++) {
2413                 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2414                         QPRINTK(qdev, IFUP, ERR,
2415                                 "TX resource allocation failed.\n");
2416                         goto err_mem;
2417                 }
2418         }
2419         return 0;
2420
2421 err_mem:
2422         ql_free_mem_resources(qdev);
2423         return -ENOMEM;
2424 }
2425
2426 /* Set up the rx ring control block and pass it to the chip.
2427  * The control block is defined as
2428  * "Completion Queue Initialization Control Block", or cqicb.
2429  */
2430 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2431 {
2432         struct cqicb *cqicb = &rx_ring->cqicb;
2433         void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2434             (rx_ring->cq_id * sizeof(u64) * 4);
2435         u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2436             (rx_ring->cq_id * sizeof(u64) * 4);
2437         void __iomem *doorbell_area =
2438             qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2439         int err = 0;
2440         u16 bq_len;
2441
2442         /* Set up the shadow registers for this ring. */
2443         rx_ring->prod_idx_sh_reg = shadow_reg;
2444         rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2445         shadow_reg += sizeof(u64);
2446         shadow_reg_dma += sizeof(u64);
2447         rx_ring->lbq_base_indirect = shadow_reg;
2448         rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2449         shadow_reg += sizeof(u64);
2450         shadow_reg_dma += sizeof(u64);
2451         rx_ring->sbq_base_indirect = shadow_reg;
2452         rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2453
2454         /* PCI doorbell mem area + 0x00 for consumer index register */
2455         rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2456         rx_ring->cnsmr_idx = 0;
2457         rx_ring->curr_entry = rx_ring->cq_base;
2458
2459         /* PCI doorbell mem area + 0x04 for valid register */
2460         rx_ring->valid_db_reg = doorbell_area + 0x04;
2461
2462         /* PCI doorbell mem area + 0x18 for large buffer consumer */
2463         rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2464
2465         /* PCI doorbell mem area + 0x1c */
2466         rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2467
2468         memset((void *)cqicb, 0, sizeof(struct cqicb));
2469         cqicb->msix_vect = rx_ring->irq;
2470
2471         bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2472         cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
2473
2474         cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
2475
2476         cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
2477
2478         /*
2479          * Set up the control block load flags.
2480          */
2481         cqicb->flags = FLAGS_LC |       /* Load queue base address */
2482             FLAGS_LV |          /* Load MSI-X vector */
2483             FLAGS_LI;           /* Load irq delay values */
2484         if (rx_ring->lbq_len) {
2485                 cqicb->flags |= FLAGS_LL;       /* Load lbq values */
2486                 *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma;
2487                 cqicb->lbq_addr =
2488                     cpu_to_le64(rx_ring->lbq_base_indirect_dma);
2489                 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2490                         (u16) rx_ring->lbq_buf_size;
2491                 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2492                 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2493                         (u16) rx_ring->lbq_len;
2494                 cqicb->lbq_len = cpu_to_le16(bq_len);
2495                 rx_ring->lbq_prod_idx = rx_ring->lbq_len - 16;
2496                 rx_ring->lbq_curr_idx = 0;
2497                 rx_ring->lbq_clean_idx = rx_ring->lbq_prod_idx;
2498                 rx_ring->lbq_free_cnt = 16;
2499         }
2500         if (rx_ring->sbq_len) {
2501                 cqicb->flags |= FLAGS_LS;       /* Load sbq values */
2502                 *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma;
2503                 cqicb->sbq_addr =
2504                     cpu_to_le64(rx_ring->sbq_base_indirect_dma);
2505                 cqicb->sbq_buf_size =
2506                     cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
2507                 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2508                         (u16) rx_ring->sbq_len;
2509                 cqicb->sbq_len = cpu_to_le16(bq_len);
2510                 rx_ring->sbq_prod_idx = rx_ring->sbq_len - 16;
2511                 rx_ring->sbq_curr_idx = 0;
2512                 rx_ring->sbq_clean_idx = rx_ring->sbq_prod_idx;
2513                 rx_ring->sbq_free_cnt = 16;
2514         }
2515         switch (rx_ring->type) {
2516         case TX_Q:
2517                 /* If there's only one interrupt, then we use
2518                  * worker threads to process the outbound
2519                  * completion handling rx_rings. We do this so
2520                  * they can be run on multiple CPUs. There is
2521                  * room to play with this more where we would only
2522                  * run in a worker if there are more than x number
2523                  * of outbound completions on the queue and more
2524                  * than one queue active.  Some threshold that
2525                  * would indicate a benefit in spite of the cost
2526                  * of a context switch.
2527                  * If there's more than one interrupt, then the
2528                  * outbound completions are processed in the ISR.
2529                  */
2530                 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2531                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2532                 else {
2533                         /* With all debug warnings on we see a WARN_ON message
2534                          * when we free the skb in the interrupt context.
2535                          */
2536                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2537                 }
2538                 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2539                 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2540                 break;
2541         case DEFAULT_Q:
2542                 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2543                 cqicb->irq_delay = 0;
2544                 cqicb->pkt_delay = 0;
2545                 break;
2546         case RX_Q:
2547                 /* Inbound completion handling rx_rings run in
2548                  * separate NAPI contexts.
2549                  */
2550                 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2551                                64);
2552                 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2553                 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2554                 break;
2555         default:
2556                 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2557                         rx_ring->type);
2558         }
2559         QPRINTK(qdev, IFUP, INFO, "Initializing rx work queue.\n");
2560         err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2561                            CFG_LCQ, rx_ring->cq_id);
2562         if (err) {
2563                 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2564                 return err;
2565         }
2566         QPRINTK(qdev, IFUP, INFO, "Successfully loaded CQICB.\n");
2567         /*
2568          * Advance the producer index for the buffer queues.
2569          */
2570         wmb();
2571         if (rx_ring->lbq_len)
2572                 ql_write_db_reg(rx_ring->lbq_prod_idx,
2573                                 rx_ring->lbq_prod_idx_db_reg);
2574         if (rx_ring->sbq_len)
2575                 ql_write_db_reg(rx_ring->sbq_prod_idx,
2576                                 rx_ring->sbq_prod_idx_db_reg);
2577         return err;
2578 }
2579
2580 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2581 {
2582         struct wqicb *wqicb = (struct wqicb *)tx_ring;
2583         void __iomem *doorbell_area =
2584             qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2585         void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2586             (tx_ring->wq_id * sizeof(u64));
2587         u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2588             (tx_ring->wq_id * sizeof(u64));
2589         int err = 0;
2590
2591         /*
2592          * Assign doorbell registers for this tx_ring.
2593          */
2594         /* TX PCI doorbell mem area for tx producer index */
2595         tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2596         tx_ring->prod_idx = 0;
2597         /* TX PCI doorbell mem area + 0x04 */
2598         tx_ring->valid_db_reg = doorbell_area + 0x04;
2599
2600         /*
2601          * Assign shadow registers for this tx_ring.
2602          */
2603         tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2604         tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2605
2606         wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2607         wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2608                                    Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2609         wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2610         wqicb->rid = 0;
2611         wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
2612
2613         wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
2614
2615         ql_init_tx_ring(qdev, tx_ring);
2616
2617         err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2618                            (u16) tx_ring->wq_id);
2619         if (err) {
2620                 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2621                 return err;
2622         }
2623         QPRINTK(qdev, IFUP, INFO, "Successfully loaded WQICB.\n");
2624         return err;
2625 }
2626
2627 static void ql_disable_msix(struct ql_adapter *qdev)
2628 {
2629         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2630                 pci_disable_msix(qdev->pdev);
2631                 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2632                 kfree(qdev->msi_x_entry);
2633                 qdev->msi_x_entry = NULL;
2634         } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2635                 pci_disable_msi(qdev->pdev);
2636                 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2637         }
2638 }
2639
2640 static void ql_enable_msix(struct ql_adapter *qdev)
2641 {
2642         int i;
2643
2644         qdev->intr_count = 1;
2645         /* Get the MSIX vectors. */
2646         if (irq_type == MSIX_IRQ) {
2647                 /* Try to alloc space for the msix struct,
2648                  * if it fails then go to MSI/legacy.
2649                  */
2650                 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2651                                             sizeof(struct msix_entry),
2652                                             GFP_KERNEL);
2653                 if (!qdev->msi_x_entry) {
2654                         irq_type = MSI_IRQ;
2655                         goto msi;
2656                 }
2657
2658                 for (i = 0; i < qdev->rx_ring_count; i++)
2659                         qdev->msi_x_entry[i].entry = i;
2660
2661                 if (!pci_enable_msix
2662                     (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2663                         set_bit(QL_MSIX_ENABLED, &qdev->flags);
2664                         qdev->intr_count = qdev->rx_ring_count;
2665                         QPRINTK(qdev, IFUP, INFO,
2666                                 "MSI-X Enabled, got %d vectors.\n",
2667                                 qdev->intr_count);
2668                         return;
2669                 } else {
2670                         kfree(qdev->msi_x_entry);
2671                         qdev->msi_x_entry = NULL;
2672                         QPRINTK(qdev, IFUP, WARNING,
2673                                 "MSI-X Enable failed, trying MSI.\n");
2674                         irq_type = MSI_IRQ;
2675                 }
2676         }
2677 msi:
2678         if (irq_type == MSI_IRQ) {
2679                 if (!pci_enable_msi(qdev->pdev)) {
2680                         set_bit(QL_MSI_ENABLED, &qdev->flags);
2681                         QPRINTK(qdev, IFUP, INFO,
2682                                 "Running with MSI interrupts.\n");
2683                         return;
2684                 }
2685         }
2686         irq_type = LEG_IRQ;
2687         QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2688 }
2689
2690 /*
2691  * Here we build the intr_context structures based on
2692  * our rx_ring count and intr vector count.
2693  * The intr_context structure is used to hook each vector
2694  * to possibly different handlers.
2695  */
2696 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2697 {
2698         int i = 0;
2699         struct intr_context *intr_context = &qdev->intr_context[0];
2700
2701         ql_enable_msix(qdev);
2702
2703         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2704                 /* Each rx_ring has it's
2705                  * own intr_context since we have separate
2706                  * vectors for each queue.
2707                  * This only true when MSI-X is enabled.
2708                  */
2709                 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2710                         qdev->rx_ring[i].irq = i;
2711                         intr_context->intr = i;
2712                         intr_context->qdev = qdev;
2713                         /*
2714                          * We set up each vectors enable/disable/read bits so
2715                          * there's no bit/mask calculations in the critical path.
2716                          */
2717                         intr_context->intr_en_mask =
2718                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2719                             INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2720                             | i;
2721                         intr_context->intr_dis_mask =
2722                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2723                             INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2724                             INTR_EN_IHD | i;
2725                         intr_context->intr_read_mask =
2726                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2727                             INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2728                             i;
2729
2730                         if (i == 0) {
2731                                 /*
2732                                  * Default queue handles bcast/mcast plus
2733                                  * async events.  Needs buffers.
2734                                  */
2735                                 intr_context->handler = qlge_isr;
2736                                 sprintf(intr_context->name, "%s-default-queue",
2737                                         qdev->ndev->name);
2738                         } else if (i < qdev->rss_ring_first_cq_id) {
2739                                 /*
2740                                  * Outbound queue is for outbound completions only.
2741                                  */
2742                                 intr_context->handler = qlge_msix_tx_isr;
2743                                 sprintf(intr_context->name, "%s-tx-%d",
2744                                         qdev->ndev->name, i);
2745                         } else {
2746                                 /*
2747                                  * Inbound queues handle unicast frames only.
2748                                  */
2749                                 intr_context->handler = qlge_msix_rx_isr;
2750                                 sprintf(intr_context->name, "%s-rx-%d",
2751                                         qdev->ndev->name, i);
2752                         }
2753                 }
2754         } else {
2755                 /*
2756                  * All rx_rings use the same intr_context since
2757                  * there is only one vector.
2758                  */
2759                 intr_context->intr = 0;
2760                 intr_context->qdev = qdev;
2761                 /*
2762                  * We set up each vectors enable/disable/read bits so
2763                  * there's no bit/mask calculations in the critical path.
2764                  */
2765                 intr_context->intr_en_mask =
2766                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2767                 intr_context->intr_dis_mask =
2768                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2769                     INTR_EN_TYPE_DISABLE;
2770                 intr_context->intr_read_mask =
2771                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2772                 /*
2773                  * Single interrupt means one handler for all rings.
2774                  */
2775                 intr_context->handler = qlge_isr;
2776                 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2777                 for (i = 0; i < qdev->rx_ring_count; i++)
2778                         qdev->rx_ring[i].irq = 0;
2779         }
2780 }
2781
2782 static void ql_free_irq(struct ql_adapter *qdev)
2783 {
2784         int i;
2785         struct intr_context *intr_context = &qdev->intr_context[0];
2786
2787         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2788                 if (intr_context->hooked) {
2789                         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2790                                 free_irq(qdev->msi_x_entry[i].vector,
2791                                          &qdev->rx_ring[i]);
2792                                 QPRINTK(qdev, IFDOWN, ERR,
2793                                         "freeing msix interrupt %d.\n", i);
2794                         } else {
2795                                 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2796                                 QPRINTK(qdev, IFDOWN, ERR,
2797                                         "freeing msi interrupt %d.\n", i);
2798                         }
2799                 }
2800         }
2801         ql_disable_msix(qdev);
2802 }
2803
2804 static int ql_request_irq(struct ql_adapter *qdev)
2805 {
2806         int i;
2807         int status = 0;
2808         struct pci_dev *pdev = qdev->pdev;
2809         struct intr_context *intr_context = &qdev->intr_context[0];
2810
2811         ql_resolve_queues_to_irqs(qdev);
2812
2813         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2814                 atomic_set(&intr_context->irq_cnt, 0);
2815                 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2816                         status = request_irq(qdev->msi_x_entry[i].vector,
2817                                              intr_context->handler,
2818                                              0,
2819                                              intr_context->name,
2820                                              &qdev->rx_ring[i]);
2821                         if (status) {
2822                                 QPRINTK(qdev, IFUP, ERR,
2823                                         "Failed request for MSIX interrupt %d.\n",
2824                                         i);
2825                                 goto err_irq;
2826                         } else {
2827                                 QPRINTK(qdev, IFUP, INFO,
2828                                         "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2829                                         i,
2830                                         qdev->rx_ring[i].type ==
2831                                         DEFAULT_Q ? "DEFAULT_Q" : "",
2832                                         qdev->rx_ring[i].type ==
2833                                         TX_Q ? "TX_Q" : "",
2834                                         qdev->rx_ring[i].type ==
2835                                         RX_Q ? "RX_Q" : "", intr_context->name);
2836                         }
2837                 } else {
2838                         QPRINTK(qdev, IFUP, DEBUG,
2839                                 "trying msi or legacy interrupts.\n");
2840                         QPRINTK(qdev, IFUP, DEBUG,
2841                                 "%s: irq = %d.\n", __func__, pdev->irq);
2842                         QPRINTK(qdev, IFUP, DEBUG,
2843                                 "%s: context->name = %s.\n", __func__,
2844                                intr_context->name);
2845                         QPRINTK(qdev, IFUP, DEBUG,
2846                                 "%s: dev_id = 0x%p.\n", __func__,
2847                                &qdev->rx_ring[0]);
2848                         status =
2849                             request_irq(pdev->irq, qlge_isr,
2850                                         test_bit(QL_MSI_ENABLED,
2851                                                  &qdev->
2852                                                  flags) ? 0 : IRQF_SHARED,
2853                                         intr_context->name, &qdev->rx_ring[0]);
2854                         if (status)
2855                                 goto err_irq;
2856
2857                         QPRINTK(qdev, IFUP, ERR,
2858                                 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2859                                 i,
2860                                 qdev->rx_ring[0].type ==
2861                                 DEFAULT_Q ? "DEFAULT_Q" : "",
2862                                 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2863                                 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2864                                 intr_context->name);
2865                 }
2866                 intr_context->hooked = 1;
2867         }
2868         return status;
2869 err_irq:
2870         QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2871         ql_free_irq(qdev);
2872         return status;
2873 }
2874
2875 static int ql_start_rss(struct ql_adapter *qdev)
2876 {
2877         struct ricb *ricb = &qdev->ricb;
2878         int status = 0;
2879         int i;
2880         u8 *hash_id = (u8 *) ricb->hash_cq_id;
2881
2882         memset((void *)ricb, 0, sizeof(ricb));
2883
2884         ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2885         ricb->flags =
2886             (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2887              RSS_RT6);
2888         ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2889
2890         /*
2891          * Fill out the Indirection Table.
2892          */
2893         for (i = 0; i < 256; i++)
2894                 hash_id[i] = i & (qdev->rss_ring_count - 1);
2895
2896         /*
2897          * Random values for the IPv6 and IPv4 Hash Keys.
2898          */
2899         get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2900         get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2901
2902         QPRINTK(qdev, IFUP, INFO, "Initializing RSS.\n");
2903
2904         status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2905         if (status) {
2906                 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2907                 return status;
2908         }
2909         QPRINTK(qdev, IFUP, INFO, "Successfully loaded RICB.\n");
2910         return status;
2911 }
2912
2913 /* Initialize the frame-to-queue routing. */
2914 static int ql_route_initialize(struct ql_adapter *qdev)
2915 {
2916         int status = 0;
2917         int i;
2918
2919         /* Clear all the entries in the routing table. */
2920         for (i = 0; i < 16; i++) {
2921                 status = ql_set_routing_reg(qdev, i, 0, 0);
2922                 if (status) {
2923                         QPRINTK(qdev, IFUP, ERR,
2924                                 "Failed to init routing register for CAM packets.\n");
2925                         return status;
2926                 }
2927         }
2928
2929         status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
2930         if (status) {
2931                 QPRINTK(qdev, IFUP, ERR,
2932                         "Failed to init routing register for error packets.\n");
2933                 return status;
2934         }
2935         status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
2936         if (status) {
2937                 QPRINTK(qdev, IFUP, ERR,
2938                         "Failed to init routing register for broadcast packets.\n");
2939                 return status;
2940         }
2941         /* If we have more than one inbound queue, then turn on RSS in the
2942          * routing block.
2943          */
2944         if (qdev->rss_ring_count > 1) {
2945                 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
2946                                         RT_IDX_RSS_MATCH, 1);
2947                 if (status) {
2948                         QPRINTK(qdev, IFUP, ERR,
2949                                 "Failed to init routing register for MATCH RSS packets.\n");
2950                         return status;
2951                 }
2952         }
2953
2954         status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
2955                                     RT_IDX_CAM_HIT, 1);
2956         if (status) {
2957                 QPRINTK(qdev, IFUP, ERR,
2958                         "Failed to init routing register for CAM packets.\n");
2959                 return status;
2960         }
2961         return status;
2962 }
2963
2964 static int ql_cam_route_initialize(struct ql_adapter *qdev)
2965 {
2966         int status;
2967
2968         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
2969         if (status)
2970                 return status;
2971         status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
2972                              MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
2973         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
2974         if (status) {
2975                 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
2976                 return status;
2977         }
2978
2979         status = ql_route_initialize(qdev);
2980         if (status)
2981                 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
2982
2983         return status;
2984 }
2985
2986 static int ql_adapter_initialize(struct ql_adapter *qdev)
2987 {
2988         u32 value, mask;
2989         int i;
2990         int status = 0;
2991
2992         /*
2993          * Set up the System register to halt on errors.
2994          */
2995         value = SYS_EFE | SYS_FAE;
2996         mask = value << 16;
2997         ql_write32(qdev, SYS, mask | value);
2998
2999         /* Set the default queue. */
3000         value = NIC_RCV_CFG_DFQ;
3001         mask = NIC_RCV_CFG_DFQ_MASK;
3002         ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3003
3004         /* Set the MPI interrupt to enabled. */
3005         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3006
3007         /* Enable the function, set pagesize, enable error checking. */
3008         value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3009             FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
3010
3011         /* Set/clear header splitting. */
3012         mask = FSC_VM_PAGESIZE_MASK |
3013             FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3014         ql_write32(qdev, FSC, mask | value);
3015
3016         ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3017                 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3018
3019         /* Start up the rx queues. */
3020         for (i = 0; i < qdev->rx_ring_count; i++) {
3021                 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3022                 if (status) {
3023                         QPRINTK(qdev, IFUP, ERR,
3024                                 "Failed to start rx ring[%d].\n", i);
3025                         return status;
3026                 }
3027         }
3028
3029         /* If there is more than one inbound completion queue
3030          * then download a RICB to configure RSS.
3031          */
3032         if (qdev->rss_ring_count > 1) {
3033                 status = ql_start_rss(qdev);
3034                 if (status) {
3035                         QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3036                         return status;
3037                 }
3038         }
3039
3040         /* Start up the tx queues. */
3041         for (i = 0; i < qdev->tx_ring_count; i++) {
3042                 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3043                 if (status) {
3044                         QPRINTK(qdev, IFUP, ERR,
3045                                 "Failed to start tx ring[%d].\n", i);
3046                         return status;
3047                 }
3048         }
3049
3050         status = ql_port_initialize(qdev);
3051         if (status) {
3052                 QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3053                 return status;
3054         }
3055
3056         /* Set up the MAC address and frame routing filter. */
3057         status = ql_cam_route_initialize(qdev);
3058         if (status) {
3059                 QPRINTK(qdev, IFUP, ERR,
3060                                 "Failed to init CAM/Routing tables.\n");
3061                 return status;
3062         }
3063
3064         /* Start NAPI for the RSS queues. */
3065         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3066                 QPRINTK(qdev, IFUP, INFO, "Enabling NAPI for rx_ring[%d].\n",
3067                         i);
3068                 napi_enable(&qdev->rx_ring[i].napi);
3069         }
3070
3071         return status;
3072 }
3073
3074 /* Issue soft reset to chip. */
3075 static int ql_adapter_reset(struct ql_adapter *qdev)
3076 {
3077         u32 value;
3078         int max_wait_time;
3079         int status = 0;
3080         int resetCnt = 0;
3081
3082 #define MAX_RESET_CNT   1
3083 issueReset:
3084         resetCnt++;
3085         QPRINTK(qdev, IFDOWN, DEBUG, "Issue soft reset to chip.\n");
3086         ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3087         /* Wait for reset to complete. */
3088         max_wait_time = 3;
3089         QPRINTK(qdev, IFDOWN, DEBUG, "Wait %d seconds for reset to complete.\n",
3090                 max_wait_time);
3091         do {
3092                 value = ql_read32(qdev, RST_FO);
3093                 if ((value & RST_FO_FR) == 0)
3094                         break;
3095
3096                 ssleep(1);
3097         } while ((--max_wait_time));
3098         if (value & RST_FO_FR) {
3099                 QPRINTK(qdev, IFDOWN, ERR,
3100                         "Stuck in SoftReset:  FSC_SR:0x%08x\n", value);
3101                 if (resetCnt < MAX_RESET_CNT)
3102                         goto issueReset;
3103         }
3104         if (max_wait_time == 0) {
3105                 status = -ETIMEDOUT;
3106                 QPRINTK(qdev, IFDOWN, ERR,
3107                         "ETIMEOUT!!! errored out of resetting the chip!\n");
3108         }
3109
3110         return status;
3111 }
3112
3113 static void ql_display_dev_info(struct net_device *ndev)
3114 {
3115         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3116
3117         QPRINTK(qdev, PROBE, INFO,
3118                 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3119                 "XG Roll = %d, XG Rev = %d.\n",
3120                 qdev->func,
3121                 qdev->chip_rev_id & 0x0000000f,
3122                 qdev->chip_rev_id >> 4 & 0x0000000f,
3123                 qdev->chip_rev_id >> 8 & 0x0000000f,
3124                 qdev->chip_rev_id >> 12 & 0x0000000f);
3125         QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3126 }
3127
3128 static int ql_adapter_down(struct ql_adapter *qdev)
3129 {
3130         struct net_device *ndev = qdev->ndev;
3131         int i, status = 0;
3132         struct rx_ring *rx_ring;
3133
3134         netif_stop_queue(ndev);
3135         netif_carrier_off(ndev);
3136
3137         /* Don't kill the reset worker thread if we
3138          * are in the process of recovery.
3139          */
3140         if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3141                 cancel_delayed_work_sync(&qdev->asic_reset_work);
3142         cancel_delayed_work_sync(&qdev->mpi_reset_work);
3143         cancel_delayed_work_sync(&qdev->mpi_work);
3144
3145         /* The default queue at index 0 is always processed in
3146          * a workqueue.
3147          */
3148         cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3149
3150         /* The rest of the rx_rings are processed in
3151          * a workqueue only if it's a single interrupt
3152          * environment (MSI/Legacy).
3153          */
3154         for (i = 1; i < qdev->rx_ring_count; i++) {
3155                 rx_ring = &qdev->rx_ring[i];
3156                 /* Only the RSS rings use NAPI on multi irq
3157                  * environment.  Outbound completion processing
3158                  * is done in interrupt context.
3159                  */
3160                 if (i >= qdev->rss_ring_first_cq_id) {
3161                         napi_disable(&rx_ring->napi);
3162                 } else {
3163                         cancel_delayed_work_sync(&rx_ring->rx_work);
3164                 }
3165         }
3166
3167         clear_bit(QL_ADAPTER_UP, &qdev->flags);
3168
3169         ql_disable_interrupts(qdev);
3170
3171         ql_tx_ring_clean(qdev);
3172
3173         spin_lock(&qdev->hw_lock);
3174         status = ql_adapter_reset(qdev);
3175         if (status)
3176                 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3177                         qdev->func);
3178         spin_unlock(&qdev->hw_lock);
3179         return status;
3180 }
3181
3182 static int ql_adapter_up(struct ql_adapter *qdev)
3183 {
3184         int err = 0;
3185
3186         spin_lock(&qdev->hw_lock);
3187         err = ql_adapter_initialize(qdev);
3188         if (err) {
3189                 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3190                 spin_unlock(&qdev->hw_lock);
3191                 goto err_init;
3192         }
3193         spin_unlock(&qdev->hw_lock);
3194         set_bit(QL_ADAPTER_UP, &qdev->flags);
3195         ql_enable_interrupts(qdev);
3196         ql_enable_all_completion_interrupts(qdev);
3197         if ((ql_read32(qdev, STS) & qdev->port_init)) {
3198                 netif_carrier_on(qdev->ndev);
3199                 netif_start_queue(qdev->ndev);
3200         }
3201
3202         return 0;
3203 err_init:
3204         ql_adapter_reset(qdev);
3205         return err;
3206 }
3207
3208 static int ql_cycle_adapter(struct ql_adapter *qdev)
3209 {
3210         int status;
3211
3212         status = ql_adapter_down(qdev);
3213         if (status)
3214                 goto error;
3215
3216         status = ql_adapter_up(qdev);
3217         if (status)
3218                 goto error;
3219
3220         return status;
3221 error:
3222         QPRINTK(qdev, IFUP, ALERT,
3223                 "Driver up/down cycle failed, closing device\n");
3224         rtnl_lock();
3225         dev_close(qdev->ndev);
3226         rtnl_unlock();
3227         return status;
3228 }
3229
3230 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3231 {
3232         ql_free_mem_resources(qdev);
3233         ql_free_irq(qdev);
3234 }
3235
3236 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3237 {
3238         int status = 0;
3239
3240         if (ql_alloc_mem_resources(qdev)) {
3241                 QPRINTK(qdev, IFUP, ERR, "Unable to  allocate memory.\n");
3242                 return -ENOMEM;
3243         }
3244         status = ql_request_irq(qdev);
3245         if (status)
3246                 goto err_irq;
3247         return status;
3248 err_irq:
3249         ql_free_mem_resources(qdev);
3250         return status;
3251 }
3252
3253 static int qlge_close(struct net_device *ndev)
3254 {
3255         struct ql_adapter *qdev = netdev_priv(ndev);
3256
3257         /*
3258          * Wait for device to recover from a reset.
3259          * (Rarely happens, but possible.)
3260          */
3261         while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3262                 msleep(1);
3263         ql_adapter_down(qdev);
3264         ql_release_adapter_resources(qdev);
3265         return 0;
3266 }
3267
3268 static int ql_configure_rings(struct ql_adapter *qdev)
3269 {
3270         int i;
3271         struct rx_ring *rx_ring;
3272         struct tx_ring *tx_ring;
3273         int cpu_cnt = num_online_cpus();
3274
3275         /*
3276          * For each processor present we allocate one
3277          * rx_ring for outbound completions, and one
3278          * rx_ring for inbound completions.  Plus there is
3279          * always the one default queue.  For the CPU
3280          * counts we end up with the following rx_rings:
3281          * rx_ring count =
3282          *  one default queue +
3283          *  (CPU count * outbound completion rx_ring) +
3284          *  (CPU count * inbound (RSS) completion rx_ring)
3285          * To keep it simple we limit the total number of
3286          * queues to < 32, so we truncate CPU to 8.
3287          * This limitation can be removed when requested.
3288          */
3289
3290         if (cpu_cnt > MAX_CPUS)
3291                 cpu_cnt = MAX_CPUS;
3292
3293         /*
3294          * rx_ring[0] is always the default queue.
3295          */
3296         /* Allocate outbound completion ring for each CPU. */
3297         qdev->tx_ring_count = cpu_cnt;
3298         /* Allocate inbound completion (RSS) ring for each CPU. */
3299         qdev->rss_ring_count = cpu_cnt;
3300         /* cq_id for the first inbound ring handler. */
3301         qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3302         /*
3303          * qdev->rx_ring_count:
3304          * Total number of rx_rings.  This includes the one
3305          * default queue, a number of outbound completion
3306          * handler rx_rings, and the number of inbound
3307          * completion handler rx_rings.
3308          */
3309         qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3310
3311         for (i = 0; i < qdev->tx_ring_count; i++) {
3312                 tx_ring = &qdev->tx_ring[i];
3313                 memset((void *)tx_ring, 0, sizeof(tx_ring));
3314                 tx_ring->qdev = qdev;
3315                 tx_ring->wq_id = i;
3316                 tx_ring->wq_len = qdev->tx_ring_size;
3317                 tx_ring->wq_size =
3318                     tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3319
3320                 /*
3321                  * The completion queue ID for the tx rings start
3322                  * immediately after the default Q ID, which is zero.
3323                  */
3324                 tx_ring->cq_id = i + 1;
3325         }
3326
3327         for (i = 0; i < qdev->rx_ring_count; i++) {
3328                 rx_ring = &qdev->rx_ring[i];
3329                 memset((void *)rx_ring, 0, sizeof(rx_ring));
3330                 rx_ring->qdev = qdev;
3331                 rx_ring->cq_id = i;
3332                 rx_ring->cpu = i % cpu_cnt;     /* CPU to run handler on. */
3333                 if (i == 0) {   /* Default queue at index 0. */
3334                         /*
3335                          * Default queue handles bcast/mcast plus
3336                          * async events.  Needs buffers.
3337                          */
3338                         rx_ring->cq_len = qdev->rx_ring_size;
3339                         rx_ring->cq_size =
3340                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3341                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3342                         rx_ring->lbq_size =
3343                             rx_ring->lbq_len * sizeof(__le64);
3344                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3345                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3346                         rx_ring->sbq_size =
3347                             rx_ring->sbq_len * sizeof(__le64);
3348                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3349                         rx_ring->type = DEFAULT_Q;
3350                 } else if (i < qdev->rss_ring_first_cq_id) {
3351                         /*
3352                          * Outbound queue handles outbound completions only.
3353                          */
3354                         /* outbound cq is same size as tx_ring it services. */
3355                         rx_ring->cq_len = qdev->tx_ring_size;
3356                         rx_ring->cq_size =
3357                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3358                         rx_ring->lbq_len = 0;
3359                         rx_ring->lbq_size = 0;
3360                         rx_ring->lbq_buf_size = 0;
3361                         rx_ring->sbq_len = 0;
3362                         rx_ring->sbq_size = 0;
3363                         rx_ring->sbq_buf_size = 0;
3364                         rx_ring->type = TX_Q;
3365                 } else {        /* Inbound completions (RSS) queues */
3366                         /*
3367                          * Inbound queues handle unicast frames only.
3368                          */
3369                         rx_ring->cq_len = qdev->rx_ring_size;
3370                         rx_ring->cq_size =
3371                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3372                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3373                         rx_ring->lbq_size =
3374                             rx_ring->lbq_len * sizeof(__le64);
3375                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3376                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3377                         rx_ring->sbq_size =
3378                             rx_ring->sbq_len * sizeof(__le64);
3379                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3380                         rx_ring->type = RX_Q;
3381                 }
3382         }
3383         return 0;
3384 }
3385
3386 static int qlge_open(struct net_device *ndev)
3387 {
3388         int err = 0;
3389         struct ql_adapter *qdev = netdev_priv(ndev);
3390
3391         err = ql_configure_rings(qdev);
3392         if (err)
3393                 return err;
3394
3395         err = ql_get_adapter_resources(qdev);
3396         if (err)
3397                 goto error_up;
3398
3399         err = ql_adapter_up(qdev);
3400         if (err)
3401                 goto error_up;
3402
3403         return err;
3404
3405 error_up:
3406         ql_release_adapter_resources(qdev);
3407         return err;
3408 }
3409
3410 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3411 {
3412         struct ql_adapter *qdev = netdev_priv(ndev);
3413
3414         if (ndev->mtu == 1500 && new_mtu == 9000) {
3415                 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3416         } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3417                 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3418         } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3419                    (ndev->mtu == 9000 && new_mtu == 9000)) {
3420                 return 0;
3421         } else
3422                 return -EINVAL;
3423         ndev->mtu = new_mtu;
3424         return 0;
3425 }
3426
3427 static struct net_device_stats *qlge_get_stats(struct net_device
3428                                                *ndev)
3429 {
3430         struct ql_adapter *qdev = netdev_priv(ndev);
3431         return &qdev->stats;
3432 }
3433
3434 static void qlge_set_multicast_list(struct net_device *ndev)
3435 {
3436         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3437         struct dev_mc_list *mc_ptr;
3438         int i, status;
3439
3440         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3441         if (status)
3442                 return;
3443         spin_lock(&qdev->hw_lock);
3444         /*
3445          * Set or clear promiscuous mode if a
3446          * transition is taking place.
3447          */
3448         if (ndev->flags & IFF_PROMISC) {
3449                 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3450                         if (ql_set_routing_reg
3451                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3452                                 QPRINTK(qdev, HW, ERR,
3453                                         "Failed to set promiscous mode.\n");
3454                         } else {
3455                                 set_bit(QL_PROMISCUOUS, &qdev->flags);
3456                         }
3457                 }
3458         } else {
3459                 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3460                         if (ql_set_routing_reg
3461                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3462                                 QPRINTK(qdev, HW, ERR,
3463                                         "Failed to clear promiscous mode.\n");
3464                         } else {
3465                                 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3466                         }
3467                 }
3468         }
3469
3470         /*
3471          * Set or clear all multicast mode if a
3472          * transition is taking place.
3473          */
3474         if ((ndev->flags & IFF_ALLMULTI) ||
3475             (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3476                 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3477                         if (ql_set_routing_reg
3478                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3479                                 QPRINTK(qdev, HW, ERR,
3480                                         "Failed to set all-multi mode.\n");
3481                         } else {
3482                                 set_bit(QL_ALLMULTI, &qdev->flags);
3483                         }
3484                 }
3485         } else {
3486                 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3487                         if (ql_set_routing_reg
3488                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3489                                 QPRINTK(qdev, HW, ERR,
3490                                         "Failed to clear all-multi mode.\n");
3491                         } else {
3492                                 clear_bit(QL_ALLMULTI, &qdev->flags);
3493                         }
3494                 }
3495         }
3496
3497         if (ndev->mc_count) {
3498                 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3499                 if (status)
3500                         goto exit;
3501                 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3502                      i++, mc_ptr = mc_ptr->next)
3503                         if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3504                                                 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3505                                 QPRINTK(qdev, HW, ERR,
3506                                         "Failed to loadmulticast address.\n");
3507                                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3508                                 goto exit;
3509                         }
3510                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3511                 if (ql_set_routing_reg
3512                     (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3513                         QPRINTK(qdev, HW, ERR,
3514                                 "Failed to set multicast match mode.\n");
3515                 } else {
3516                         set_bit(QL_ALLMULTI, &qdev->flags);
3517                 }
3518         }
3519 exit:
3520         spin_unlock(&qdev->hw_lock);
3521 }
3522
3523 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3524 {
3525         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3526         struct sockaddr *addr = p;
3527         int status;
3528
3529         if (netif_running(ndev))
3530                 return -EBUSY;
3531
3532         if (!is_valid_ether_addr(addr->sa_data))
3533                 return -EADDRNOTAVAIL;
3534         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3535
3536         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3537         if (status)
3538                 return status;
3539         spin_lock(&qdev->hw_lock);
3540         status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3541                         MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3542         spin_unlock(&qdev->hw_lock);
3543         if (status)
3544                 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3545         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3546         return status;
3547 }
3548
3549 static void qlge_tx_timeout(struct net_device *ndev)
3550 {
3551         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3552         ql_queue_asic_error(qdev);
3553 }
3554
3555 static void ql_asic_reset_work(struct work_struct *work)
3556 {
3557         struct ql_adapter *qdev =
3558             container_of(work, struct ql_adapter, asic_reset_work.work);
3559         ql_cycle_adapter(qdev);
3560 }
3561
3562 static void ql_get_board_info(struct ql_adapter *qdev)
3563 {
3564         qdev->func =
3565             (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3566         if (qdev->func) {
3567                 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3568                 qdev->port_link_up = STS_PL1;
3569                 qdev->port_init = STS_PI1;
3570                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3571                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3572         } else {
3573                 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3574                 qdev->port_link_up = STS_PL0;
3575                 qdev->port_init = STS_PI0;
3576                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3577                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3578         }
3579         qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3580 }
3581
3582 static void ql_release_all(struct pci_dev *pdev)
3583 {
3584         struct net_device *ndev = pci_get_drvdata(pdev);
3585         struct ql_adapter *qdev = netdev_priv(ndev);
3586
3587         if (qdev->workqueue) {
3588                 destroy_workqueue(qdev->workqueue);
3589                 qdev->workqueue = NULL;
3590         }
3591         if (qdev->q_workqueue) {
3592                 destroy_workqueue(qdev->q_workqueue);
3593                 qdev->q_workqueue = NULL;
3594         }
3595         if (qdev->reg_base)
3596                 iounmap(qdev->reg_base);
3597         if (qdev->doorbell_area)
3598                 iounmap(qdev->doorbell_area);
3599         pci_release_regions(pdev);
3600         pci_set_drvdata(pdev, NULL);
3601 }
3602
3603 static int __devinit ql_init_device(struct pci_dev *pdev,
3604                                     struct net_device *ndev, int cards_found)
3605 {
3606         struct ql_adapter *qdev = netdev_priv(ndev);
3607         int pos, err = 0;
3608         u16 val16;
3609
3610         memset((void *)qdev, 0, sizeof(qdev));
3611         err = pci_enable_device(pdev);
3612         if (err) {
3613                 dev_err(&pdev->dev, "PCI device enable failed.\n");
3614                 return err;
3615         }
3616
3617         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3618         if (pos <= 0) {
3619                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3620                         "aborting.\n");
3621                 goto err_out;
3622         } else {
3623                 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3624                 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3625                 val16 |= (PCI_EXP_DEVCTL_CERE |
3626                           PCI_EXP_DEVCTL_NFERE |
3627                           PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3628                 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3629         }
3630
3631         err = pci_request_regions(pdev, DRV_NAME);
3632         if (err) {
3633                 dev_err(&pdev->dev, "PCI region request failed.\n");
3634                 goto err_out;
3635         }
3636
3637         pci_set_master(pdev);
3638         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3639                 set_bit(QL_DMA64, &qdev->flags);
3640                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3641         } else {
3642                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3643                 if (!err)
3644                        err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3645         }
3646
3647         if (err) {
3648                 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3649                 goto err_out;
3650         }
3651
3652         pci_set_drvdata(pdev, ndev);
3653         qdev->reg_base =
3654             ioremap_nocache(pci_resource_start(pdev, 1),
3655                             pci_resource_len(pdev, 1));
3656         if (!qdev->reg_base) {
3657                 dev_err(&pdev->dev, "Register mapping failed.\n");
3658                 err = -ENOMEM;
3659                 goto err_out;
3660         }
3661
3662         qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3663         qdev->doorbell_area =
3664             ioremap_nocache(pci_resource_start(pdev, 3),
3665                             pci_resource_len(pdev, 3));
3666         if (!qdev->doorbell_area) {
3667                 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3668                 err = -ENOMEM;
3669                 goto err_out;
3670         }
3671
3672         ql_get_board_info(qdev);
3673         qdev->ndev = ndev;
3674         qdev->pdev = pdev;
3675         qdev->msg_enable = netif_msg_init(debug, default_msg);
3676         spin_lock_init(&qdev->hw_lock);
3677         spin_lock_init(&qdev->stats_lock);
3678
3679         /* make sure the EEPROM is good */
3680         err = ql_get_flash_params(qdev);
3681         if (err) {
3682                 dev_err(&pdev->dev, "Invalid FLASH.\n");
3683                 goto err_out;
3684         }
3685
3686         if (!is_valid_ether_addr(qdev->flash.mac_addr))
3687                 goto err_out;
3688
3689         memcpy(ndev->dev_addr, qdev->flash.mac_addr, ndev->addr_len);
3690         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3691
3692         /* Set up the default ring sizes. */
3693         qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3694         qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3695
3696         /* Set up the coalescing parameters. */
3697         qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3698         qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3699         qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3700         qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3701
3702         /*
3703          * Set up the operating parameters.
3704          */
3705         qdev->rx_csum = 1;
3706
3707         qdev->q_workqueue = create_workqueue(ndev->name);
3708         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3709         INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3710         INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3711         INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3712
3713         if (!cards_found) {
3714                 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3715                 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3716                          DRV_NAME, DRV_VERSION);
3717         }
3718         return 0;
3719 err_out:
3720         ql_release_all(pdev);
3721         pci_disable_device(pdev);
3722         return err;
3723 }
3724
3725
3726 static const struct net_device_ops qlge_netdev_ops = {
3727         .ndo_open               = qlge_open,
3728         .ndo_stop               = qlge_close,
3729         .ndo_start_xmit         = qlge_send,
3730         .ndo_change_mtu         = qlge_change_mtu,
3731         .ndo_get_stats          = qlge_get_stats,
3732         .ndo_set_multicast_list = qlge_set_multicast_list,
3733         .ndo_set_mac_address    = qlge_set_mac_address,
3734         .ndo_validate_addr      = eth_validate_addr,
3735         .ndo_tx_timeout         = qlge_tx_timeout,
3736         .ndo_vlan_rx_register   = ql_vlan_rx_register,
3737         .ndo_vlan_rx_add_vid    = ql_vlan_rx_add_vid,
3738         .ndo_vlan_rx_kill_vid   = ql_vlan_rx_kill_vid,
3739 };
3740
3741 static int __devinit qlge_probe(struct pci_dev *pdev,
3742                                 const struct pci_device_id *pci_entry)
3743 {
3744         struct net_device *ndev = NULL;
3745         struct ql_adapter *qdev = NULL;
3746         static int cards_found = 0;
3747         int err = 0;
3748
3749         ndev = alloc_etherdev(sizeof(struct ql_adapter));
3750         if (!ndev)
3751                 return -ENOMEM;
3752
3753         err = ql_init_device(pdev, ndev, cards_found);
3754         if (err < 0) {
3755                 free_netdev(ndev);
3756                 return err;
3757         }
3758
3759         qdev = netdev_priv(ndev);
3760         SET_NETDEV_DEV(ndev, &pdev->dev);
3761         ndev->features = (0
3762                           | NETIF_F_IP_CSUM
3763                           | NETIF_F_SG
3764                           | NETIF_F_TSO
3765                           | NETIF_F_TSO6
3766                           | NETIF_F_TSO_ECN
3767                           | NETIF_F_HW_VLAN_TX
3768                           | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3769
3770         if (test_bit(QL_DMA64, &qdev->flags))
3771                 ndev->features |= NETIF_F_HIGHDMA;
3772
3773         /*
3774          * Set up net_device structure.
3775          */
3776         ndev->tx_queue_len = qdev->tx_ring_size;
3777         ndev->irq = pdev->irq;
3778
3779         ndev->netdev_ops = &qlge_netdev_ops;
3780         SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
3781         ndev->watchdog_timeo = 10 * HZ;
3782
3783         err = register_netdev(ndev);
3784         if (err) {
3785                 dev_err(&pdev->dev, "net device registration failed.\n");
3786                 ql_release_all(pdev);
3787                 pci_disable_device(pdev);
3788                 return err;
3789         }
3790         netif_carrier_off(ndev);
3791         netif_stop_queue(ndev);
3792         ql_display_dev_info(ndev);
3793         cards_found++;
3794         return 0;
3795 }
3796
3797 static void __devexit qlge_remove(struct pci_dev *pdev)
3798 {
3799         struct net_device *ndev = pci_get_drvdata(pdev);
3800         unregister_netdev(ndev);
3801         ql_release_all(pdev);
3802         pci_disable_device(pdev);
3803         free_netdev(ndev);
3804 }
3805
3806 /*
3807  * This callback is called by the PCI subsystem whenever
3808  * a PCI bus error is detected.
3809  */
3810 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3811                                                enum pci_channel_state state)
3812 {
3813         struct net_device *ndev = pci_get_drvdata(pdev);
3814         struct ql_adapter *qdev = netdev_priv(ndev);
3815
3816         if (netif_running(ndev))
3817                 ql_adapter_down(qdev);
3818
3819         pci_disable_device(pdev);
3820
3821         /* Request a slot reset. */
3822         return PCI_ERS_RESULT_NEED_RESET;
3823 }
3824
3825 /*
3826  * This callback is called after the PCI buss has been reset.
3827  * Basically, this tries to restart the card from scratch.
3828  * This is a shortened version of the device probe/discovery code,
3829  * it resembles the first-half of the () routine.
3830  */
3831 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3832 {
3833         struct net_device *ndev = pci_get_drvdata(pdev);
3834         struct ql_adapter *qdev = netdev_priv(ndev);
3835
3836         if (pci_enable_device(pdev)) {
3837                 QPRINTK(qdev, IFUP, ERR,
3838                         "Cannot re-enable PCI device after reset.\n");
3839                 return PCI_ERS_RESULT_DISCONNECT;
3840         }
3841
3842         pci_set_master(pdev);
3843
3844         netif_carrier_off(ndev);
3845         netif_stop_queue(ndev);
3846         ql_adapter_reset(qdev);
3847
3848         /* Make sure the EEPROM is good */
3849         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3850
3851         if (!is_valid_ether_addr(ndev->perm_addr)) {
3852                 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3853                 return PCI_ERS_RESULT_DISCONNECT;
3854         }
3855
3856         return PCI_ERS_RESULT_RECOVERED;
3857 }
3858
3859 static void qlge_io_resume(struct pci_dev *pdev)
3860 {
3861         struct net_device *ndev = pci_get_drvdata(pdev);
3862         struct ql_adapter *qdev = netdev_priv(ndev);
3863
3864         pci_set_master(pdev);
3865
3866         if (netif_running(ndev)) {
3867                 if (ql_adapter_up(qdev)) {
3868                         QPRINTK(qdev, IFUP, ERR,
3869                                 "Device initialization failed after reset.\n");
3870                         return;
3871                 }
3872         }
3873
3874         netif_device_attach(ndev);
3875 }
3876
3877 static struct pci_error_handlers qlge_err_handler = {
3878         .error_detected = qlge_io_error_detected,
3879         .slot_reset = qlge_io_slot_reset,
3880         .resume = qlge_io_resume,
3881 };
3882
3883 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3884 {
3885         struct net_device *ndev = pci_get_drvdata(pdev);
3886         struct ql_adapter *qdev = netdev_priv(ndev);
3887         int err, i;
3888
3889         netif_device_detach(ndev);
3890
3891         if (netif_running(ndev)) {
3892                 err = ql_adapter_down(qdev);
3893                 if (!err)
3894                         return err;
3895         }
3896
3897         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++)
3898                 netif_napi_del(&qdev->rx_ring[i].napi);
3899
3900         err = pci_save_state(pdev);
3901         if (err)
3902                 return err;
3903
3904         pci_disable_device(pdev);
3905
3906         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3907
3908         return 0;
3909 }
3910
3911 #ifdef CONFIG_PM
3912 static int qlge_resume(struct pci_dev *pdev)
3913 {
3914         struct net_device *ndev = pci_get_drvdata(pdev);
3915         struct ql_adapter *qdev = netdev_priv(ndev);
3916         int err;
3917
3918         pci_set_power_state(pdev, PCI_D0);
3919         pci_restore_state(pdev);
3920         err = pci_enable_device(pdev);
3921         if (err) {
3922                 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
3923                 return err;
3924         }
3925         pci_set_master(pdev);
3926
3927         pci_enable_wake(pdev, PCI_D3hot, 0);
3928         pci_enable_wake(pdev, PCI_D3cold, 0);
3929
3930         if (netif_running(ndev)) {
3931                 err = ql_adapter_up(qdev);
3932                 if (err)
3933                         return err;
3934         }
3935
3936         netif_device_attach(ndev);
3937
3938         return 0;
3939 }
3940 #endif /* CONFIG_PM */
3941
3942 static void qlge_shutdown(struct pci_dev *pdev)
3943 {
3944         qlge_suspend(pdev, PMSG_SUSPEND);
3945 }
3946
3947 static struct pci_driver qlge_driver = {
3948         .name = DRV_NAME,
3949         .id_table = qlge_pci_tbl,
3950         .probe = qlge_probe,
3951         .remove = __devexit_p(qlge_remove),
3952 #ifdef CONFIG_PM
3953         .suspend = qlge_suspend,
3954         .resume = qlge_resume,
3955 #endif
3956         .shutdown = qlge_shutdown,
3957         .err_handler = &qlge_err_handler
3958 };
3959
3960 static int __init qlge_init_module(void)
3961 {
3962         return pci_register_driver(&qlge_driver);
3963 }
3964
3965 static void __exit qlge_exit(void)
3966 {
3967         pci_unregister_driver(&qlge_driver);
3968 }
3969
3970 module_init(qlge_init_module);
3971 module_exit(qlge_exit);