qlge: Get rid of 'default' rx_ring type.
[linux-2.6.git] / drivers / net / qlge / qlge_main.c
1 /*
2  * QLogic qlge NIC HBA Driver
3  * Copyright (c)  2003-2008 QLogic Corporation
4  * See LICENSE.qlge for copyright and licensing details.
5  * Author:     Linux qlge network device driver by
6  *                      Ron Mercer <ron.mercer@qlogic.com>
7  */
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/pagemap.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/dmapool.h>
19 #include <linux/mempool.h>
20 #include <linux/spinlock.h>
21 #include <linux/kthread.h>
22 #include <linux/interrupt.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/in.h>
26 #include <linux/ip.h>
27 #include <linux/ipv6.h>
28 #include <net/ipv6.h>
29 #include <linux/tcp.h>
30 #include <linux/udp.h>
31 #include <linux/if_arp.h>
32 #include <linux/if_ether.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/skbuff.h>
37 #include <linux/rtnetlink.h>
38 #include <linux/if_vlan.h>
39 #include <linux/delay.h>
40 #include <linux/mm.h>
41 #include <linux/vmalloc.h>
42 #include <net/ip6_checksum.h>
43
44 #include "qlge.h"
45
46 char qlge_driver_name[] = DRV_NAME;
47 const char qlge_driver_version[] = DRV_VERSION;
48
49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
50 MODULE_DESCRIPTION(DRV_STRING " ");
51 MODULE_LICENSE("GPL");
52 MODULE_VERSION(DRV_VERSION);
53
54 static const u32 default_msg =
55     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
56 /* NETIF_MSG_TIMER |    */
57     NETIF_MSG_IFDOWN |
58     NETIF_MSG_IFUP |
59     NETIF_MSG_RX_ERR |
60     NETIF_MSG_TX_ERR |
61 /*  NETIF_MSG_TX_QUEUED | */
62 /*  NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS | */
63 /* NETIF_MSG_PKTDATA | */
64     NETIF_MSG_HW | NETIF_MSG_WOL | 0;
65
66 static int debug = 0x00007fff;  /* defaults above */
67 module_param(debug, int, 0);
68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
69
70 #define MSIX_IRQ 0
71 #define MSI_IRQ 1
72 #define LEG_IRQ 2
73 static int irq_type = MSIX_IRQ;
74 module_param(irq_type, int, MSIX_IRQ);
75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
76
77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
78         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8012)},
79         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8000)},
80         /* required last entry */
81         {0,}
82 };
83
84 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
85
86 /* This hardware semaphore causes exclusive access to
87  * resources shared between the NIC driver, MPI firmware,
88  * FCOE firmware and the FC driver.
89  */
90 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
91 {
92         u32 sem_bits = 0;
93
94         switch (sem_mask) {
95         case SEM_XGMAC0_MASK:
96                 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
97                 break;
98         case SEM_XGMAC1_MASK:
99                 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
100                 break;
101         case SEM_ICB_MASK:
102                 sem_bits = SEM_SET << SEM_ICB_SHIFT;
103                 break;
104         case SEM_MAC_ADDR_MASK:
105                 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
106                 break;
107         case SEM_FLASH_MASK:
108                 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
109                 break;
110         case SEM_PROBE_MASK:
111                 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
112                 break;
113         case SEM_RT_IDX_MASK:
114                 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
115                 break;
116         case SEM_PROC_REG_MASK:
117                 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
118                 break;
119         default:
120                 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
121                 return -EINVAL;
122         }
123
124         ql_write32(qdev, SEM, sem_bits | sem_mask);
125         return !(ql_read32(qdev, SEM) & sem_bits);
126 }
127
128 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
129 {
130         unsigned int wait_count = 30;
131         do {
132                 if (!ql_sem_trylock(qdev, sem_mask))
133                         return 0;
134                 udelay(100);
135         } while (--wait_count);
136         return -ETIMEDOUT;
137 }
138
139 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
140 {
141         ql_write32(qdev, SEM, sem_mask);
142         ql_read32(qdev, SEM);   /* flush */
143 }
144
145 /* This function waits for a specific bit to come ready
146  * in a given register.  It is used mostly by the initialize
147  * process, but is also used in kernel thread API such as
148  * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
149  */
150 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
151 {
152         u32 temp;
153         int count = UDELAY_COUNT;
154
155         while (count) {
156                 temp = ql_read32(qdev, reg);
157
158                 /* check for errors */
159                 if (temp & err_bit) {
160                         QPRINTK(qdev, PROBE, ALERT,
161                                 "register 0x%.08x access error, value = 0x%.08x!.\n",
162                                 reg, temp);
163                         return -EIO;
164                 } else if (temp & bit)
165                         return 0;
166                 udelay(UDELAY_DELAY);
167                 count--;
168         }
169         QPRINTK(qdev, PROBE, ALERT,
170                 "Timed out waiting for reg %x to come ready.\n", reg);
171         return -ETIMEDOUT;
172 }
173
174 /* The CFG register is used to download TX and RX control blocks
175  * to the chip. This function waits for an operation to complete.
176  */
177 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
178 {
179         int count = UDELAY_COUNT;
180         u32 temp;
181
182         while (count) {
183                 temp = ql_read32(qdev, CFG);
184                 if (temp & CFG_LE)
185                         return -EIO;
186                 if (!(temp & bit))
187                         return 0;
188                 udelay(UDELAY_DELAY);
189                 count--;
190         }
191         return -ETIMEDOUT;
192 }
193
194
195 /* Used to issue init control blocks to hw. Maps control block,
196  * sets address, triggers download, waits for completion.
197  */
198 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
199                  u16 q_id)
200 {
201         u64 map;
202         int status = 0;
203         int direction;
204         u32 mask;
205         u32 value;
206
207         direction =
208             (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
209             PCI_DMA_FROMDEVICE;
210
211         map = pci_map_single(qdev->pdev, ptr, size, direction);
212         if (pci_dma_mapping_error(qdev->pdev, map)) {
213                 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
214                 return -ENOMEM;
215         }
216
217         status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
218         if (status)
219                 return status;
220
221         status = ql_wait_cfg(qdev, bit);
222         if (status) {
223                 QPRINTK(qdev, IFUP, ERR,
224                         "Timed out waiting for CFG to come ready.\n");
225                 goto exit;
226         }
227
228         ql_write32(qdev, ICB_L, (u32) map);
229         ql_write32(qdev, ICB_H, (u32) (map >> 32));
230
231         mask = CFG_Q_MASK | (bit << 16);
232         value = bit | (q_id << CFG_Q_SHIFT);
233         ql_write32(qdev, CFG, (mask | value));
234
235         /*
236          * Wait for the bit to clear after signaling hw.
237          */
238         status = ql_wait_cfg(qdev, bit);
239 exit:
240         ql_sem_unlock(qdev, SEM_ICB_MASK);      /* does flush too */
241         pci_unmap_single(qdev->pdev, map, size, direction);
242         return status;
243 }
244
245 /* Get a specific MAC address from the CAM.  Used for debug and reg dump. */
246 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
247                         u32 *value)
248 {
249         u32 offset = 0;
250         int status;
251
252         switch (type) {
253         case MAC_ADDR_TYPE_MULTI_MAC:
254         case MAC_ADDR_TYPE_CAM_MAC:
255                 {
256                         status =
257                             ql_wait_reg_rdy(qdev,
258                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
259                         if (status)
260                                 goto exit;
261                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
262                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
263                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
264                         status =
265                             ql_wait_reg_rdy(qdev,
266                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
267                         if (status)
268                                 goto exit;
269                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
270                         status =
271                             ql_wait_reg_rdy(qdev,
272                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
273                         if (status)
274                                 goto exit;
275                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
276                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
277                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
278                         status =
279                             ql_wait_reg_rdy(qdev,
280                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
281                         if (status)
282                                 goto exit;
283                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
284                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
285                                 status =
286                                     ql_wait_reg_rdy(qdev,
287                                         MAC_ADDR_IDX, MAC_ADDR_MW, 0);
288                                 if (status)
289                                         goto exit;
290                                 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
291                                            (index << MAC_ADDR_IDX_SHIFT) | /* index */
292                                            MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
293                                 status =
294                                     ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
295                                                     MAC_ADDR_MR, 0);
296                                 if (status)
297                                         goto exit;
298                                 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
299                         }
300                         break;
301                 }
302         case MAC_ADDR_TYPE_VLAN:
303         case MAC_ADDR_TYPE_MULTI_FLTR:
304         default:
305                 QPRINTK(qdev, IFUP, CRIT,
306                         "Address type %d not yet supported.\n", type);
307                 status = -EPERM;
308         }
309 exit:
310         return status;
311 }
312
313 /* Set up a MAC, multicast or VLAN address for the
314  * inbound frame matching.
315  */
316 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
317                                u16 index)
318 {
319         u32 offset = 0;
320         int status = 0;
321
322         switch (type) {
323         case MAC_ADDR_TYPE_MULTI_MAC:
324         case MAC_ADDR_TYPE_CAM_MAC:
325                 {
326                         u32 cam_output;
327                         u32 upper = (addr[0] << 8) | addr[1];
328                         u32 lower =
329                             (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
330                             (addr[5]);
331
332                         QPRINTK(qdev, IFUP, DEBUG,
333                                 "Adding %s address %pM"
334                                 " at index %d in the CAM.\n",
335                                 ((type ==
336                                   MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
337                                  "UNICAST"), addr, index);
338
339                         status =
340                             ql_wait_reg_rdy(qdev,
341                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
342                         if (status)
343                                 goto exit;
344                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
345                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
346                                    type);       /* type */
347                         ql_write32(qdev, MAC_ADDR_DATA, lower);
348                         status =
349                             ql_wait_reg_rdy(qdev,
350                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
351                         if (status)
352                                 goto exit;
353                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
354                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
355                                    type);       /* type */
356                         ql_write32(qdev, MAC_ADDR_DATA, upper);
357                         status =
358                             ql_wait_reg_rdy(qdev,
359                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
360                         if (status)
361                                 goto exit;
362                         ql_write32(qdev, MAC_ADDR_IDX, (offset) |       /* offset */
363                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
364                                    type);       /* type */
365                         /* This field should also include the queue id
366                            and possibly the function id.  Right now we hardcode
367                            the route field to NIC core.
368                          */
369                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
370                                 cam_output = (CAM_OUT_ROUTE_NIC |
371                                               (qdev->
372                                                func << CAM_OUT_FUNC_SHIFT) |
373                                                 (0 << CAM_OUT_CQ_ID_SHIFT));
374                                 if (qdev->vlgrp)
375                                         cam_output |= CAM_OUT_RV;
376                                 /* route to NIC core */
377                                 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
378                         }
379                         break;
380                 }
381         case MAC_ADDR_TYPE_VLAN:
382                 {
383                         u32 enable_bit = *((u32 *) &addr[0]);
384                         /* For VLAN, the addr actually holds a bit that
385                          * either enables or disables the vlan id we are
386                          * addressing. It's either MAC_ADDR_E on or off.
387                          * That's bit-27 we're talking about.
388                          */
389                         QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
390                                 (enable_bit ? "Adding" : "Removing"),
391                                 index, (enable_bit ? "to" : "from"));
392
393                         status =
394                             ql_wait_reg_rdy(qdev,
395                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
396                         if (status)
397                                 goto exit;
398                         ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
399                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
400                                    type |       /* type */
401                                    enable_bit); /* enable/disable */
402                         break;
403                 }
404         case MAC_ADDR_TYPE_MULTI_FLTR:
405         default:
406                 QPRINTK(qdev, IFUP, CRIT,
407                         "Address type %d not yet supported.\n", type);
408                 status = -EPERM;
409         }
410 exit:
411         return status;
412 }
413
414 /* Set or clear MAC address in hardware. We sometimes
415  * have to clear it to prevent wrong frame routing
416  * especially in a bonding environment.
417  */
418 static int ql_set_mac_addr(struct ql_adapter *qdev, int set)
419 {
420         int status;
421         char zero_mac_addr[ETH_ALEN];
422         char *addr;
423
424         if (set) {
425                 addr = &qdev->ndev->dev_addr[0];
426                 QPRINTK(qdev, IFUP, DEBUG,
427                         "Set Mac addr %02x:%02x:%02x:%02x:%02x:%02x\n",
428                         addr[0], addr[1], addr[2], addr[3],
429                         addr[4], addr[5]);
430         } else {
431                 memset(zero_mac_addr, 0, ETH_ALEN);
432                 addr = &zero_mac_addr[0];
433                 QPRINTK(qdev, IFUP, DEBUG,
434                                 "Clearing MAC address on %s\n",
435                                 qdev->ndev->name);
436         }
437         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
438         if (status)
439                 return status;
440         status = ql_set_mac_addr_reg(qdev, (u8 *) addr,
441                         MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
442         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
443         if (status)
444                 QPRINTK(qdev, IFUP, ERR, "Failed to init mac "
445                         "address.\n");
446         return status;
447 }
448
449 void ql_link_on(struct ql_adapter *qdev)
450 {
451         QPRINTK(qdev, LINK, ERR, "%s: Link is up.\n",
452                                  qdev->ndev->name);
453         netif_carrier_on(qdev->ndev);
454         ql_set_mac_addr(qdev, 1);
455 }
456
457 void ql_link_off(struct ql_adapter *qdev)
458 {
459         QPRINTK(qdev, LINK, ERR, "%s: Link is down.\n",
460                                  qdev->ndev->name);
461         netif_carrier_off(qdev->ndev);
462         ql_set_mac_addr(qdev, 0);
463 }
464
465 /* Get a specific frame routing value from the CAM.
466  * Used for debug and reg dump.
467  */
468 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
469 {
470         int status = 0;
471
472         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
473         if (status)
474                 goto exit;
475
476         ql_write32(qdev, RT_IDX,
477                    RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
478         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
479         if (status)
480                 goto exit;
481         *value = ql_read32(qdev, RT_DATA);
482 exit:
483         return status;
484 }
485
486 /* The NIC function for this chip has 16 routing indexes.  Each one can be used
487  * to route different frame types to various inbound queues.  We send broadcast/
488  * multicast/error frames to the default queue for slow handling,
489  * and CAM hit/RSS frames to the fast handling queues.
490  */
491 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
492                               int enable)
493 {
494         int status = -EINVAL; /* Return error if no mask match. */
495         u32 value = 0;
496
497         QPRINTK(qdev, IFUP, DEBUG,
498                 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
499                 (enable ? "Adding" : "Removing"),
500                 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
501                 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
502                 ((index ==
503                   RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
504                 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
505                 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
506                 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
507                 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
508                 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
509                 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
510                 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
511                 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
512                 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
513                 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
514                 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
515                 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
516                 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
517                 (enable ? "to" : "from"));
518
519         switch (mask) {
520         case RT_IDX_CAM_HIT:
521                 {
522                         value = RT_IDX_DST_CAM_Q |      /* dest */
523                             RT_IDX_TYPE_NICQ |  /* type */
524                             (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
525                         break;
526                 }
527         case RT_IDX_VALID:      /* Promiscuous Mode frames. */
528                 {
529                         value = RT_IDX_DST_DFLT_Q |     /* dest */
530                             RT_IDX_TYPE_NICQ |  /* type */
531                             (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
532                         break;
533                 }
534         case RT_IDX_ERR:        /* Pass up MAC,IP,TCP/UDP error frames. */
535                 {
536                         value = RT_IDX_DST_DFLT_Q |     /* dest */
537                             RT_IDX_TYPE_NICQ |  /* type */
538                             (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
539                         break;
540                 }
541         case RT_IDX_BCAST:      /* Pass up Broadcast frames to default Q. */
542                 {
543                         value = RT_IDX_DST_DFLT_Q |     /* dest */
544                             RT_IDX_TYPE_NICQ |  /* type */
545                             (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
546                         break;
547                 }
548         case RT_IDX_MCAST:      /* Pass up All Multicast frames. */
549                 {
550                         value = RT_IDX_DST_CAM_Q |      /* dest */
551                             RT_IDX_TYPE_NICQ |  /* type */
552                             (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
553                         break;
554                 }
555         case RT_IDX_MCAST_MATCH:        /* Pass up matched Multicast frames. */
556                 {
557                         value = RT_IDX_DST_CAM_Q |      /* dest */
558                             RT_IDX_TYPE_NICQ |  /* type */
559                             (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
560                         break;
561                 }
562         case RT_IDX_RSS_MATCH:  /* Pass up matched RSS frames. */
563                 {
564                         value = RT_IDX_DST_RSS |        /* dest */
565                             RT_IDX_TYPE_NICQ |  /* type */
566                             (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
567                         break;
568                 }
569         case 0:         /* Clear the E-bit on an entry. */
570                 {
571                         value = RT_IDX_DST_DFLT_Q |     /* dest */
572                             RT_IDX_TYPE_NICQ |  /* type */
573                             (index << RT_IDX_IDX_SHIFT);/* index */
574                         break;
575                 }
576         default:
577                 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
578                         mask);
579                 status = -EPERM;
580                 goto exit;
581         }
582
583         if (value) {
584                 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
585                 if (status)
586                         goto exit;
587                 value |= (enable ? RT_IDX_E : 0);
588                 ql_write32(qdev, RT_IDX, value);
589                 ql_write32(qdev, RT_DATA, enable ? mask : 0);
590         }
591 exit:
592         return status;
593 }
594
595 static void ql_enable_interrupts(struct ql_adapter *qdev)
596 {
597         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
598 }
599
600 static void ql_disable_interrupts(struct ql_adapter *qdev)
601 {
602         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
603 }
604
605 /* If we're running with multiple MSI-X vectors then we enable on the fly.
606  * Otherwise, we may have multiple outstanding workers and don't want to
607  * enable until the last one finishes. In this case, the irq_cnt gets
608  * incremented everytime we queue a worker and decremented everytime
609  * a worker finishes.  Once it hits zero we enable the interrupt.
610  */
611 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
612 {
613         u32 var = 0;
614         unsigned long hw_flags = 0;
615         struct intr_context *ctx = qdev->intr_context + intr;
616
617         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
618                 /* Always enable if we're MSIX multi interrupts and
619                  * it's not the default (zeroeth) interrupt.
620                  */
621                 ql_write32(qdev, INTR_EN,
622                            ctx->intr_en_mask);
623                 var = ql_read32(qdev, STS);
624                 return var;
625         }
626
627         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
628         if (atomic_dec_and_test(&ctx->irq_cnt)) {
629                 ql_write32(qdev, INTR_EN,
630                            ctx->intr_en_mask);
631                 var = ql_read32(qdev, STS);
632         }
633         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
634         return var;
635 }
636
637 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
638 {
639         u32 var = 0;
640         struct intr_context *ctx;
641
642         /* HW disables for us if we're MSIX multi interrupts and
643          * it's not the default (zeroeth) interrupt.
644          */
645         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
646                 return 0;
647
648         ctx = qdev->intr_context + intr;
649         spin_lock(&qdev->hw_lock);
650         if (!atomic_read(&ctx->irq_cnt)) {
651                 ql_write32(qdev, INTR_EN,
652                 ctx->intr_dis_mask);
653                 var = ql_read32(qdev, STS);
654         }
655         atomic_inc(&ctx->irq_cnt);
656         spin_unlock(&qdev->hw_lock);
657         return var;
658 }
659
660 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
661 {
662         int i;
663         for (i = 0; i < qdev->intr_count; i++) {
664                 /* The enable call does a atomic_dec_and_test
665                  * and enables only if the result is zero.
666                  * So we precharge it here.
667                  */
668                 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
669                         i == 0))
670                         atomic_set(&qdev->intr_context[i].irq_cnt, 1);
671                 ql_enable_completion_interrupt(qdev, i);
672         }
673
674 }
675
676 static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str)
677 {
678         int status, i;
679         u16 csum = 0;
680         __le16 *flash = (__le16 *)&qdev->flash;
681
682         status = strncmp((char *)&qdev->flash, str, 4);
683         if (status) {
684                 QPRINTK(qdev, IFUP, ERR, "Invalid flash signature.\n");
685                 return  status;
686         }
687
688         for (i = 0; i < size; i++)
689                 csum += le16_to_cpu(*flash++);
690
691         if (csum)
692                 QPRINTK(qdev, IFUP, ERR,
693                         "Invalid flash checksum, csum = 0x%.04x.\n", csum);
694
695         return csum;
696 }
697
698 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
699 {
700         int status = 0;
701         /* wait for reg to come ready */
702         status = ql_wait_reg_rdy(qdev,
703                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
704         if (status)
705                 goto exit;
706         /* set up for reg read */
707         ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
708         /* wait for reg to come ready */
709         status = ql_wait_reg_rdy(qdev,
710                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
711         if (status)
712                 goto exit;
713          /* This data is stored on flash as an array of
714          * __le32.  Since ql_read32() returns cpu endian
715          * we need to swap it back.
716          */
717         *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
718 exit:
719         return status;
720 }
721
722 static int ql_get_8000_flash_params(struct ql_adapter *qdev)
723 {
724         u32 i, size;
725         int status;
726         __le32 *p = (__le32 *)&qdev->flash;
727         u32 offset;
728         u8 mac_addr[6];
729
730         /* Get flash offset for function and adjust
731          * for dword access.
732          */
733         if (!qdev->port)
734                 offset = FUNC0_FLASH_OFFSET / sizeof(u32);
735         else
736                 offset = FUNC1_FLASH_OFFSET / sizeof(u32);
737
738         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
739                 return -ETIMEDOUT;
740
741         size = sizeof(struct flash_params_8000) / sizeof(u32);
742         for (i = 0; i < size; i++, p++) {
743                 status = ql_read_flash_word(qdev, i+offset, p);
744                 if (status) {
745                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
746                         goto exit;
747                 }
748         }
749
750         status = ql_validate_flash(qdev,
751                         sizeof(struct flash_params_8000) / sizeof(u16),
752                         "8000");
753         if (status) {
754                 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
755                 status = -EINVAL;
756                 goto exit;
757         }
758
759         /* Extract either manufacturer or BOFM modified
760          * MAC address.
761          */
762         if (qdev->flash.flash_params_8000.data_type1 == 2)
763                 memcpy(mac_addr,
764                         qdev->flash.flash_params_8000.mac_addr1,
765                         qdev->ndev->addr_len);
766         else
767                 memcpy(mac_addr,
768                         qdev->flash.flash_params_8000.mac_addr,
769                         qdev->ndev->addr_len);
770
771         if (!is_valid_ether_addr(mac_addr)) {
772                 QPRINTK(qdev, IFUP, ERR, "Invalid MAC address.\n");
773                 status = -EINVAL;
774                 goto exit;
775         }
776
777         memcpy(qdev->ndev->dev_addr,
778                 mac_addr,
779                 qdev->ndev->addr_len);
780
781 exit:
782         ql_sem_unlock(qdev, SEM_FLASH_MASK);
783         return status;
784 }
785
786 static int ql_get_8012_flash_params(struct ql_adapter *qdev)
787 {
788         int i;
789         int status;
790         __le32 *p = (__le32 *)&qdev->flash;
791         u32 offset = 0;
792         u32 size = sizeof(struct flash_params_8012) / sizeof(u32);
793
794         /* Second function's parameters follow the first
795          * function's.
796          */
797         if (qdev->port)
798                 offset = size;
799
800         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
801                 return -ETIMEDOUT;
802
803         for (i = 0; i < size; i++, p++) {
804                 status = ql_read_flash_word(qdev, i+offset, p);
805                 if (status) {
806                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
807                         goto exit;
808                 }
809
810         }
811
812         status = ql_validate_flash(qdev,
813                         sizeof(struct flash_params_8012) / sizeof(u16),
814                         "8012");
815         if (status) {
816                 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
817                 status = -EINVAL;
818                 goto exit;
819         }
820
821         if (!is_valid_ether_addr(qdev->flash.flash_params_8012.mac_addr)) {
822                 status = -EINVAL;
823                 goto exit;
824         }
825
826         memcpy(qdev->ndev->dev_addr,
827                 qdev->flash.flash_params_8012.mac_addr,
828                 qdev->ndev->addr_len);
829
830 exit:
831         ql_sem_unlock(qdev, SEM_FLASH_MASK);
832         return status;
833 }
834
835 /* xgmac register are located behind the xgmac_addr and xgmac_data
836  * register pair.  Each read/write requires us to wait for the ready
837  * bit before reading/writing the data.
838  */
839 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
840 {
841         int status;
842         /* wait for reg to come ready */
843         status = ql_wait_reg_rdy(qdev,
844                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
845         if (status)
846                 return status;
847         /* write the data to the data reg */
848         ql_write32(qdev, XGMAC_DATA, data);
849         /* trigger the write */
850         ql_write32(qdev, XGMAC_ADDR, reg);
851         return status;
852 }
853
854 /* xgmac register are located behind the xgmac_addr and xgmac_data
855  * register pair.  Each read/write requires us to wait for the ready
856  * bit before reading/writing the data.
857  */
858 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
859 {
860         int status = 0;
861         /* wait for reg to come ready */
862         status = ql_wait_reg_rdy(qdev,
863                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
864         if (status)
865                 goto exit;
866         /* set up for reg read */
867         ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
868         /* wait for reg to come ready */
869         status = ql_wait_reg_rdy(qdev,
870                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
871         if (status)
872                 goto exit;
873         /* get the data */
874         *data = ql_read32(qdev, XGMAC_DATA);
875 exit:
876         return status;
877 }
878
879 /* This is used for reading the 64-bit statistics regs. */
880 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
881 {
882         int status = 0;
883         u32 hi = 0;
884         u32 lo = 0;
885
886         status = ql_read_xgmac_reg(qdev, reg, &lo);
887         if (status)
888                 goto exit;
889
890         status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
891         if (status)
892                 goto exit;
893
894         *data = (u64) lo | ((u64) hi << 32);
895
896 exit:
897         return status;
898 }
899
900 static int ql_8000_port_initialize(struct ql_adapter *qdev)
901 {
902         int status;
903         /*
904          * Get MPI firmware version for driver banner
905          * and ethool info.
906          */
907         status = ql_mb_about_fw(qdev);
908         if (status)
909                 goto exit;
910         status = ql_mb_get_fw_state(qdev);
911         if (status)
912                 goto exit;
913         /* Wake up a worker to get/set the TX/RX frame sizes. */
914         queue_delayed_work(qdev->workqueue, &qdev->mpi_port_cfg_work, 0);
915 exit:
916         return status;
917 }
918
919 /* Take the MAC Core out of reset.
920  * Enable statistics counting.
921  * Take the transmitter/receiver out of reset.
922  * This functionality may be done in the MPI firmware at a
923  * later date.
924  */
925 static int ql_8012_port_initialize(struct ql_adapter *qdev)
926 {
927         int status = 0;
928         u32 data;
929
930         if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
931                 /* Another function has the semaphore, so
932                  * wait for the port init bit to come ready.
933                  */
934                 QPRINTK(qdev, LINK, INFO,
935                         "Another function has the semaphore, so wait for the port init bit to come ready.\n");
936                 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
937                 if (status) {
938                         QPRINTK(qdev, LINK, CRIT,
939                                 "Port initialize timed out.\n");
940                 }
941                 return status;
942         }
943
944         QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
945         /* Set the core reset. */
946         status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
947         if (status)
948                 goto end;
949         data |= GLOBAL_CFG_RESET;
950         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
951         if (status)
952                 goto end;
953
954         /* Clear the core reset and turn on jumbo for receiver. */
955         data &= ~GLOBAL_CFG_RESET;      /* Clear core reset. */
956         data |= GLOBAL_CFG_JUMBO;       /* Turn on jumbo. */
957         data |= GLOBAL_CFG_TX_STAT_EN;
958         data |= GLOBAL_CFG_RX_STAT_EN;
959         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
960         if (status)
961                 goto end;
962
963         /* Enable transmitter, and clear it's reset. */
964         status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
965         if (status)
966                 goto end;
967         data &= ~TX_CFG_RESET;  /* Clear the TX MAC reset. */
968         data |= TX_CFG_EN;      /* Enable the transmitter. */
969         status = ql_write_xgmac_reg(qdev, TX_CFG, data);
970         if (status)
971                 goto end;
972
973         /* Enable receiver and clear it's reset. */
974         status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
975         if (status)
976                 goto end;
977         data &= ~RX_CFG_RESET;  /* Clear the RX MAC reset. */
978         data |= RX_CFG_EN;      /* Enable the receiver. */
979         status = ql_write_xgmac_reg(qdev, RX_CFG, data);
980         if (status)
981                 goto end;
982
983         /* Turn on jumbo. */
984         status =
985             ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
986         if (status)
987                 goto end;
988         status =
989             ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
990         if (status)
991                 goto end;
992
993         /* Signal to the world that the port is enabled.        */
994         ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
995 end:
996         ql_sem_unlock(qdev, qdev->xg_sem_mask);
997         return status;
998 }
999
1000 /* Get the next large buffer. */
1001 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
1002 {
1003         struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
1004         rx_ring->lbq_curr_idx++;
1005         if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
1006                 rx_ring->lbq_curr_idx = 0;
1007         rx_ring->lbq_free_cnt++;
1008         return lbq_desc;
1009 }
1010
1011 /* Get the next small buffer. */
1012 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
1013 {
1014         struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
1015         rx_ring->sbq_curr_idx++;
1016         if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
1017                 rx_ring->sbq_curr_idx = 0;
1018         rx_ring->sbq_free_cnt++;
1019         return sbq_desc;
1020 }
1021
1022 /* Update an rx ring index. */
1023 static void ql_update_cq(struct rx_ring *rx_ring)
1024 {
1025         rx_ring->cnsmr_idx++;
1026         rx_ring->curr_entry++;
1027         if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
1028                 rx_ring->cnsmr_idx = 0;
1029                 rx_ring->curr_entry = rx_ring->cq_base;
1030         }
1031 }
1032
1033 static void ql_write_cq_idx(struct rx_ring *rx_ring)
1034 {
1035         ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
1036 }
1037
1038 /* Process (refill) a large buffer queue. */
1039 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1040 {
1041         u32 clean_idx = rx_ring->lbq_clean_idx;
1042         u32 start_idx = clean_idx;
1043         struct bq_desc *lbq_desc;
1044         u64 map;
1045         int i;
1046
1047         while (rx_ring->lbq_free_cnt > 16) {
1048                 for (i = 0; i < 16; i++) {
1049                         QPRINTK(qdev, RX_STATUS, DEBUG,
1050                                 "lbq: try cleaning clean_idx = %d.\n",
1051                                 clean_idx);
1052                         lbq_desc = &rx_ring->lbq[clean_idx];
1053                         if (lbq_desc->p.lbq_page == NULL) {
1054                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1055                                         "lbq: getting new page for index %d.\n",
1056                                         lbq_desc->index);
1057                                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
1058                                 if (lbq_desc->p.lbq_page == NULL) {
1059                                         rx_ring->lbq_clean_idx = clean_idx;
1060                                         QPRINTK(qdev, RX_STATUS, ERR,
1061                                                 "Couldn't get a page.\n");
1062                                         return;
1063                                 }
1064                                 map = pci_map_page(qdev->pdev,
1065                                                    lbq_desc->p.lbq_page,
1066                                                    0, PAGE_SIZE,
1067                                                    PCI_DMA_FROMDEVICE);
1068                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
1069                                         rx_ring->lbq_clean_idx = clean_idx;
1070                                         put_page(lbq_desc->p.lbq_page);
1071                                         lbq_desc->p.lbq_page = NULL;
1072                                         QPRINTK(qdev, RX_STATUS, ERR,
1073                                                 "PCI mapping failed.\n");
1074                                         return;
1075                                 }
1076                                 pci_unmap_addr_set(lbq_desc, mapaddr, map);
1077                                 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
1078                                 *lbq_desc->addr = cpu_to_le64(map);
1079                         }
1080                         clean_idx++;
1081                         if (clean_idx == rx_ring->lbq_len)
1082                                 clean_idx = 0;
1083                 }
1084
1085                 rx_ring->lbq_clean_idx = clean_idx;
1086                 rx_ring->lbq_prod_idx += 16;
1087                 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
1088                         rx_ring->lbq_prod_idx = 0;
1089                 rx_ring->lbq_free_cnt -= 16;
1090         }
1091
1092         if (start_idx != clean_idx) {
1093                 QPRINTK(qdev, RX_STATUS, DEBUG,
1094                         "lbq: updating prod idx = %d.\n",
1095                         rx_ring->lbq_prod_idx);
1096                 ql_write_db_reg(rx_ring->lbq_prod_idx,
1097                                 rx_ring->lbq_prod_idx_db_reg);
1098         }
1099 }
1100
1101 /* Process (refill) a small buffer queue. */
1102 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1103 {
1104         u32 clean_idx = rx_ring->sbq_clean_idx;
1105         u32 start_idx = clean_idx;
1106         struct bq_desc *sbq_desc;
1107         u64 map;
1108         int i;
1109
1110         while (rx_ring->sbq_free_cnt > 16) {
1111                 for (i = 0; i < 16; i++) {
1112                         sbq_desc = &rx_ring->sbq[clean_idx];
1113                         QPRINTK(qdev, RX_STATUS, DEBUG,
1114                                 "sbq: try cleaning clean_idx = %d.\n",
1115                                 clean_idx);
1116                         if (sbq_desc->p.skb == NULL) {
1117                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1118                                         "sbq: getting new skb for index %d.\n",
1119                                         sbq_desc->index);
1120                                 sbq_desc->p.skb =
1121                                     netdev_alloc_skb(qdev->ndev,
1122                                                      rx_ring->sbq_buf_size);
1123                                 if (sbq_desc->p.skb == NULL) {
1124                                         QPRINTK(qdev, PROBE, ERR,
1125                                                 "Couldn't get an skb.\n");
1126                                         rx_ring->sbq_clean_idx = clean_idx;
1127                                         return;
1128                                 }
1129                                 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
1130                                 map = pci_map_single(qdev->pdev,
1131                                                      sbq_desc->p.skb->data,
1132                                                      rx_ring->sbq_buf_size /
1133                                                      2, PCI_DMA_FROMDEVICE);
1134                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
1135                                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
1136                                         rx_ring->sbq_clean_idx = clean_idx;
1137                                         dev_kfree_skb_any(sbq_desc->p.skb);
1138                                         sbq_desc->p.skb = NULL;
1139                                         return;
1140                                 }
1141                                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
1142                                 pci_unmap_len_set(sbq_desc, maplen,
1143                                                   rx_ring->sbq_buf_size / 2);
1144                                 *sbq_desc->addr = cpu_to_le64(map);
1145                         }
1146
1147                         clean_idx++;
1148                         if (clean_idx == rx_ring->sbq_len)
1149                                 clean_idx = 0;
1150                 }
1151                 rx_ring->sbq_clean_idx = clean_idx;
1152                 rx_ring->sbq_prod_idx += 16;
1153                 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
1154                         rx_ring->sbq_prod_idx = 0;
1155                 rx_ring->sbq_free_cnt -= 16;
1156         }
1157
1158         if (start_idx != clean_idx) {
1159                 QPRINTK(qdev, RX_STATUS, DEBUG,
1160                         "sbq: updating prod idx = %d.\n",
1161                         rx_ring->sbq_prod_idx);
1162                 ql_write_db_reg(rx_ring->sbq_prod_idx,
1163                                 rx_ring->sbq_prod_idx_db_reg);
1164         }
1165 }
1166
1167 static void ql_update_buffer_queues(struct ql_adapter *qdev,
1168                                     struct rx_ring *rx_ring)
1169 {
1170         ql_update_sbq(qdev, rx_ring);
1171         ql_update_lbq(qdev, rx_ring);
1172 }
1173
1174 /* Unmaps tx buffers.  Can be called from send() if a pci mapping
1175  * fails at some stage, or from the interrupt when a tx completes.
1176  */
1177 static void ql_unmap_send(struct ql_adapter *qdev,
1178                           struct tx_ring_desc *tx_ring_desc, int mapped)
1179 {
1180         int i;
1181         for (i = 0; i < mapped; i++) {
1182                 if (i == 0 || (i == 7 && mapped > 7)) {
1183                         /*
1184                          * Unmap the skb->data area, or the
1185                          * external sglist (AKA the Outbound
1186                          * Address List (OAL)).
1187                          * If its the zeroeth element, then it's
1188                          * the skb->data area.  If it's the 7th
1189                          * element and there is more than 6 frags,
1190                          * then its an OAL.
1191                          */
1192                         if (i == 7) {
1193                                 QPRINTK(qdev, TX_DONE, DEBUG,
1194                                         "unmapping OAL area.\n");
1195                         }
1196                         pci_unmap_single(qdev->pdev,
1197                                          pci_unmap_addr(&tx_ring_desc->map[i],
1198                                                         mapaddr),
1199                                          pci_unmap_len(&tx_ring_desc->map[i],
1200                                                        maplen),
1201                                          PCI_DMA_TODEVICE);
1202                 } else {
1203                         QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1204                                 i);
1205                         pci_unmap_page(qdev->pdev,
1206                                        pci_unmap_addr(&tx_ring_desc->map[i],
1207                                                       mapaddr),
1208                                        pci_unmap_len(&tx_ring_desc->map[i],
1209                                                      maplen), PCI_DMA_TODEVICE);
1210                 }
1211         }
1212
1213 }
1214
1215 /* Map the buffers for this transmit.  This will return
1216  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1217  */
1218 static int ql_map_send(struct ql_adapter *qdev,
1219                        struct ob_mac_iocb_req *mac_iocb_ptr,
1220                        struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1221 {
1222         int len = skb_headlen(skb);
1223         dma_addr_t map;
1224         int frag_idx, err, map_idx = 0;
1225         struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1226         int frag_cnt = skb_shinfo(skb)->nr_frags;
1227
1228         if (frag_cnt) {
1229                 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1230         }
1231         /*
1232          * Map the skb buffer first.
1233          */
1234         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1235
1236         err = pci_dma_mapping_error(qdev->pdev, map);
1237         if (err) {
1238                 QPRINTK(qdev, TX_QUEUED, ERR,
1239                         "PCI mapping failed with error: %d\n", err);
1240
1241                 return NETDEV_TX_BUSY;
1242         }
1243
1244         tbd->len = cpu_to_le32(len);
1245         tbd->addr = cpu_to_le64(map);
1246         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1247         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1248         map_idx++;
1249
1250         /*
1251          * This loop fills the remainder of the 8 address descriptors
1252          * in the IOCB.  If there are more than 7 fragments, then the
1253          * eighth address desc will point to an external list (OAL).
1254          * When this happens, the remainder of the frags will be stored
1255          * in this list.
1256          */
1257         for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1258                 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1259                 tbd++;
1260                 if (frag_idx == 6 && frag_cnt > 7) {
1261                         /* Let's tack on an sglist.
1262                          * Our control block will now
1263                          * look like this:
1264                          * iocb->seg[0] = skb->data
1265                          * iocb->seg[1] = frag[0]
1266                          * iocb->seg[2] = frag[1]
1267                          * iocb->seg[3] = frag[2]
1268                          * iocb->seg[4] = frag[3]
1269                          * iocb->seg[5] = frag[4]
1270                          * iocb->seg[6] = frag[5]
1271                          * iocb->seg[7] = ptr to OAL (external sglist)
1272                          * oal->seg[0] = frag[6]
1273                          * oal->seg[1] = frag[7]
1274                          * oal->seg[2] = frag[8]
1275                          * oal->seg[3] = frag[9]
1276                          * oal->seg[4] = frag[10]
1277                          *      etc...
1278                          */
1279                         /* Tack on the OAL in the eighth segment of IOCB. */
1280                         map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1281                                              sizeof(struct oal),
1282                                              PCI_DMA_TODEVICE);
1283                         err = pci_dma_mapping_error(qdev->pdev, map);
1284                         if (err) {
1285                                 QPRINTK(qdev, TX_QUEUED, ERR,
1286                                         "PCI mapping outbound address list with error: %d\n",
1287                                         err);
1288                                 goto map_error;
1289                         }
1290
1291                         tbd->addr = cpu_to_le64(map);
1292                         /*
1293                          * The length is the number of fragments
1294                          * that remain to be mapped times the length
1295                          * of our sglist (OAL).
1296                          */
1297                         tbd->len =
1298                             cpu_to_le32((sizeof(struct tx_buf_desc) *
1299                                          (frag_cnt - frag_idx)) | TX_DESC_C);
1300                         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1301                                            map);
1302                         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1303                                           sizeof(struct oal));
1304                         tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1305                         map_idx++;
1306                 }
1307
1308                 map =
1309                     pci_map_page(qdev->pdev, frag->page,
1310                                  frag->page_offset, frag->size,
1311                                  PCI_DMA_TODEVICE);
1312
1313                 err = pci_dma_mapping_error(qdev->pdev, map);
1314                 if (err) {
1315                         QPRINTK(qdev, TX_QUEUED, ERR,
1316                                 "PCI mapping frags failed with error: %d.\n",
1317                                 err);
1318                         goto map_error;
1319                 }
1320
1321                 tbd->addr = cpu_to_le64(map);
1322                 tbd->len = cpu_to_le32(frag->size);
1323                 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1324                 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1325                                   frag->size);
1326
1327         }
1328         /* Save the number of segments we've mapped. */
1329         tx_ring_desc->map_cnt = map_idx;
1330         /* Terminate the last segment. */
1331         tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1332         return NETDEV_TX_OK;
1333
1334 map_error:
1335         /*
1336          * If the first frag mapping failed, then i will be zero.
1337          * This causes the unmap of the skb->data area.  Otherwise
1338          * we pass in the number of frags that mapped successfully
1339          * so they can be umapped.
1340          */
1341         ql_unmap_send(qdev, tx_ring_desc, map_idx);
1342         return NETDEV_TX_BUSY;
1343 }
1344
1345 static void ql_realign_skb(struct sk_buff *skb, int len)
1346 {
1347         void *temp_addr = skb->data;
1348
1349         /* Undo the skb_reserve(skb,32) we did before
1350          * giving to hardware, and realign data on
1351          * a 2-byte boundary.
1352          */
1353         skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1354         skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1355         skb_copy_to_linear_data(skb, temp_addr,
1356                 (unsigned int)len);
1357 }
1358
1359 /*
1360  * This function builds an skb for the given inbound
1361  * completion.  It will be rewritten for readability in the near
1362  * future, but for not it works well.
1363  */
1364 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1365                                        struct rx_ring *rx_ring,
1366                                        struct ib_mac_iocb_rsp *ib_mac_rsp)
1367 {
1368         struct bq_desc *lbq_desc;
1369         struct bq_desc *sbq_desc;
1370         struct sk_buff *skb = NULL;
1371         u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1372        u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1373
1374         /*
1375          * Handle the header buffer if present.
1376          */
1377         if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1378             ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1379                 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1380                 /*
1381                  * Headers fit nicely into a small buffer.
1382                  */
1383                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1384                 pci_unmap_single(qdev->pdev,
1385                                 pci_unmap_addr(sbq_desc, mapaddr),
1386                                 pci_unmap_len(sbq_desc, maplen),
1387                                 PCI_DMA_FROMDEVICE);
1388                 skb = sbq_desc->p.skb;
1389                 ql_realign_skb(skb, hdr_len);
1390                 skb_put(skb, hdr_len);
1391                 sbq_desc->p.skb = NULL;
1392         }
1393
1394         /*
1395          * Handle the data buffer(s).
1396          */
1397         if (unlikely(!length)) {        /* Is there data too? */
1398                 QPRINTK(qdev, RX_STATUS, DEBUG,
1399                         "No Data buffer in this packet.\n");
1400                 return skb;
1401         }
1402
1403         if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1404                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1405                         QPRINTK(qdev, RX_STATUS, DEBUG,
1406                                 "Headers in small, data of %d bytes in small, combine them.\n", length);
1407                         /*
1408                          * Data is less than small buffer size so it's
1409                          * stuffed in a small buffer.
1410                          * For this case we append the data
1411                          * from the "data" small buffer to the "header" small
1412                          * buffer.
1413                          */
1414                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1415                         pci_dma_sync_single_for_cpu(qdev->pdev,
1416                                                     pci_unmap_addr
1417                                                     (sbq_desc, mapaddr),
1418                                                     pci_unmap_len
1419                                                     (sbq_desc, maplen),
1420                                                     PCI_DMA_FROMDEVICE);
1421                         memcpy(skb_put(skb, length),
1422                                sbq_desc->p.skb->data, length);
1423                         pci_dma_sync_single_for_device(qdev->pdev,
1424                                                        pci_unmap_addr
1425                                                        (sbq_desc,
1426                                                         mapaddr),
1427                                                        pci_unmap_len
1428                                                        (sbq_desc,
1429                                                         maplen),
1430                                                        PCI_DMA_FROMDEVICE);
1431                 } else {
1432                         QPRINTK(qdev, RX_STATUS, DEBUG,
1433                                 "%d bytes in a single small buffer.\n", length);
1434                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1435                         skb = sbq_desc->p.skb;
1436                         ql_realign_skb(skb, length);
1437                         skb_put(skb, length);
1438                         pci_unmap_single(qdev->pdev,
1439                                          pci_unmap_addr(sbq_desc,
1440                                                         mapaddr),
1441                                          pci_unmap_len(sbq_desc,
1442                                                        maplen),
1443                                          PCI_DMA_FROMDEVICE);
1444                         sbq_desc->p.skb = NULL;
1445                 }
1446         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1447                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1448                         QPRINTK(qdev, RX_STATUS, DEBUG,
1449                                 "Header in small, %d bytes in large. Chain large to small!\n", length);
1450                         /*
1451                          * The data is in a single large buffer.  We
1452                          * chain it to the header buffer's skb and let
1453                          * it rip.
1454                          */
1455                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1456                         pci_unmap_page(qdev->pdev,
1457                                        pci_unmap_addr(lbq_desc,
1458                                                       mapaddr),
1459                                        pci_unmap_len(lbq_desc, maplen),
1460                                        PCI_DMA_FROMDEVICE);
1461                         QPRINTK(qdev, RX_STATUS, DEBUG,
1462                                 "Chaining page to skb.\n");
1463                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1464                                            0, length);
1465                         skb->len += length;
1466                         skb->data_len += length;
1467                         skb->truesize += length;
1468                         lbq_desc->p.lbq_page = NULL;
1469                 } else {
1470                         /*
1471                          * The headers and data are in a single large buffer. We
1472                          * copy it to a new skb and let it go. This can happen with
1473                          * jumbo mtu on a non-TCP/UDP frame.
1474                          */
1475                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1476                         skb = netdev_alloc_skb(qdev->ndev, length);
1477                         if (skb == NULL) {
1478                                 QPRINTK(qdev, PROBE, DEBUG,
1479                                         "No skb available, drop the packet.\n");
1480                                 return NULL;
1481                         }
1482                         pci_unmap_page(qdev->pdev,
1483                                        pci_unmap_addr(lbq_desc,
1484                                                       mapaddr),
1485                                        pci_unmap_len(lbq_desc, maplen),
1486                                        PCI_DMA_FROMDEVICE);
1487                         skb_reserve(skb, NET_IP_ALIGN);
1488                         QPRINTK(qdev, RX_STATUS, DEBUG,
1489                                 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1490                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1491                                            0, length);
1492                         skb->len += length;
1493                         skb->data_len += length;
1494                         skb->truesize += length;
1495                         length -= length;
1496                         lbq_desc->p.lbq_page = NULL;
1497                         __pskb_pull_tail(skb,
1498                                 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1499                                 VLAN_ETH_HLEN : ETH_HLEN);
1500                 }
1501         } else {
1502                 /*
1503                  * The data is in a chain of large buffers
1504                  * pointed to by a small buffer.  We loop
1505                  * thru and chain them to the our small header
1506                  * buffer's skb.
1507                  * frags:  There are 18 max frags and our small
1508                  *         buffer will hold 32 of them. The thing is,
1509                  *         we'll use 3 max for our 9000 byte jumbo
1510                  *         frames.  If the MTU goes up we could
1511                  *          eventually be in trouble.
1512                  */
1513                 int size, offset, i = 0;
1514                 __le64 *bq, bq_array[8];
1515                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1516                 pci_unmap_single(qdev->pdev,
1517                                  pci_unmap_addr(sbq_desc, mapaddr),
1518                                  pci_unmap_len(sbq_desc, maplen),
1519                                  PCI_DMA_FROMDEVICE);
1520                 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1521                         /*
1522                          * This is an non TCP/UDP IP frame, so
1523                          * the headers aren't split into a small
1524                          * buffer.  We have to use the small buffer
1525                          * that contains our sg list as our skb to
1526                          * send upstairs. Copy the sg list here to
1527                          * a local buffer and use it to find the
1528                          * pages to chain.
1529                          */
1530                         QPRINTK(qdev, RX_STATUS, DEBUG,
1531                                 "%d bytes of headers & data in chain of large.\n", length);
1532                         skb = sbq_desc->p.skb;
1533                         bq = &bq_array[0];
1534                         memcpy(bq, skb->data, sizeof(bq_array));
1535                         sbq_desc->p.skb = NULL;
1536                         skb_reserve(skb, NET_IP_ALIGN);
1537                 } else {
1538                         QPRINTK(qdev, RX_STATUS, DEBUG,
1539                                 "Headers in small, %d bytes of data in chain of large.\n", length);
1540                         bq = (__le64 *)sbq_desc->p.skb->data;
1541                 }
1542                 while (length > 0) {
1543                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1544                         pci_unmap_page(qdev->pdev,
1545                                        pci_unmap_addr(lbq_desc,
1546                                                       mapaddr),
1547                                        pci_unmap_len(lbq_desc,
1548                                                      maplen),
1549                                        PCI_DMA_FROMDEVICE);
1550                         size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1551                         offset = 0;
1552
1553                         QPRINTK(qdev, RX_STATUS, DEBUG,
1554                                 "Adding page %d to skb for %d bytes.\n",
1555                                 i, size);
1556                         skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1557                                            offset, size);
1558                         skb->len += size;
1559                         skb->data_len += size;
1560                         skb->truesize += size;
1561                         length -= size;
1562                         lbq_desc->p.lbq_page = NULL;
1563                         bq++;
1564                         i++;
1565                 }
1566                 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1567                                 VLAN_ETH_HLEN : ETH_HLEN);
1568         }
1569         return skb;
1570 }
1571
1572 /* Process an inbound completion from an rx ring. */
1573 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1574                                    struct rx_ring *rx_ring,
1575                                    struct ib_mac_iocb_rsp *ib_mac_rsp)
1576 {
1577         struct net_device *ndev = qdev->ndev;
1578         struct sk_buff *skb = NULL;
1579         u16 vlan_id = (le16_to_cpu(ib_mac_rsp->vlan_id) &
1580                         IB_MAC_IOCB_RSP_VLAN_MASK)
1581
1582         QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1583
1584         skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1585         if (unlikely(!skb)) {
1586                 QPRINTK(qdev, RX_STATUS, DEBUG,
1587                         "No skb available, drop packet.\n");
1588                 return;
1589         }
1590
1591         /* Frame error, so drop the packet. */
1592         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1593                 QPRINTK(qdev, DRV, ERR, "Receive error, flags2 = 0x%x\n",
1594                                         ib_mac_rsp->flags2);
1595                 dev_kfree_skb_any(skb);
1596                 return;
1597         }
1598
1599         /* The max framesize filter on this chip is set higher than
1600          * MTU since FCoE uses 2k frames.
1601          */
1602         if (skb->len > ndev->mtu + ETH_HLEN) {
1603                 dev_kfree_skb_any(skb);
1604                 return;
1605         }
1606
1607         prefetch(skb->data);
1608         skb->dev = ndev;
1609         if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1610                 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1611                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1612                         IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1613                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1614                         IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1615                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1616                         IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1617         }
1618         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1619                 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1620         }
1621
1622         skb->protocol = eth_type_trans(skb, ndev);
1623         skb->ip_summed = CHECKSUM_NONE;
1624
1625         /* If rx checksum is on, and there are no
1626          * csum or frame errors.
1627          */
1628         if (qdev->rx_csum &&
1629                 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1630                 /* TCP frame. */
1631                 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1632                         QPRINTK(qdev, RX_STATUS, DEBUG,
1633                                         "TCP checksum done!\n");
1634                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1635                 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1636                                 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1637                 /* Unfragmented ipv4 UDP frame. */
1638                         struct iphdr *iph = (struct iphdr *) skb->data;
1639                         if (!(iph->frag_off &
1640                                 cpu_to_be16(IP_MF|IP_OFFSET))) {
1641                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1642                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1643                                                 "TCP checksum done!\n");
1644                         }
1645                 }
1646         }
1647
1648         qdev->stats.rx_packets++;
1649         qdev->stats.rx_bytes += skb->len;
1650         skb_record_rx_queue(skb, rx_ring->cq_id);
1651         if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
1652                 if (qdev->vlgrp &&
1653                         (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
1654                         (vlan_id != 0))
1655                         vlan_gro_receive(&rx_ring->napi, qdev->vlgrp,
1656                                 vlan_id, skb);
1657                 else
1658                         napi_gro_receive(&rx_ring->napi, skb);
1659         } else {
1660                 if (qdev->vlgrp &&
1661                         (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
1662                         (vlan_id != 0))
1663                         vlan_hwaccel_receive_skb(skb, qdev->vlgrp, vlan_id);
1664                 else
1665                         netif_receive_skb(skb);
1666         }
1667 }
1668
1669 /* Process an outbound completion from an rx ring. */
1670 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1671                                    struct ob_mac_iocb_rsp *mac_rsp)
1672 {
1673         struct tx_ring *tx_ring;
1674         struct tx_ring_desc *tx_ring_desc;
1675
1676         QL_DUMP_OB_MAC_RSP(mac_rsp);
1677         tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1678         tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1679         ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1680         qdev->stats.tx_bytes += (tx_ring_desc->skb)->len;
1681         qdev->stats.tx_packets++;
1682         dev_kfree_skb(tx_ring_desc->skb);
1683         tx_ring_desc->skb = NULL;
1684
1685         if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1686                                         OB_MAC_IOCB_RSP_S |
1687                                         OB_MAC_IOCB_RSP_L |
1688                                         OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1689                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1690                         QPRINTK(qdev, TX_DONE, WARNING,
1691                                 "Total descriptor length did not match transfer length.\n");
1692                 }
1693                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1694                         QPRINTK(qdev, TX_DONE, WARNING,
1695                                 "Frame too short to be legal, not sent.\n");
1696                 }
1697                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1698                         QPRINTK(qdev, TX_DONE, WARNING,
1699                                 "Frame too long, but sent anyway.\n");
1700                 }
1701                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1702                         QPRINTK(qdev, TX_DONE, WARNING,
1703                                 "PCI backplane error. Frame not sent.\n");
1704                 }
1705         }
1706         atomic_inc(&tx_ring->tx_count);
1707 }
1708
1709 /* Fire up a handler to reset the MPI processor. */
1710 void ql_queue_fw_error(struct ql_adapter *qdev)
1711 {
1712         ql_link_off(qdev);
1713         queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1714 }
1715
1716 void ql_queue_asic_error(struct ql_adapter *qdev)
1717 {
1718         ql_link_off(qdev);
1719         ql_disable_interrupts(qdev);
1720         /* Clear adapter up bit to signal the recovery
1721          * process that it shouldn't kill the reset worker
1722          * thread
1723          */
1724         clear_bit(QL_ADAPTER_UP, &qdev->flags);
1725         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1726 }
1727
1728 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1729                                     struct ib_ae_iocb_rsp *ib_ae_rsp)
1730 {
1731         switch (ib_ae_rsp->event) {
1732         case MGMT_ERR_EVENT:
1733                 QPRINTK(qdev, RX_ERR, ERR,
1734                         "Management Processor Fatal Error.\n");
1735                 ql_queue_fw_error(qdev);
1736                 return;
1737
1738         case CAM_LOOKUP_ERR_EVENT:
1739                 QPRINTK(qdev, LINK, ERR,
1740                         "Multiple CAM hits lookup occurred.\n");
1741                 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1742                 ql_queue_asic_error(qdev);
1743                 return;
1744
1745         case SOFT_ECC_ERROR_EVENT:
1746                 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1747                 ql_queue_asic_error(qdev);
1748                 break;
1749
1750         case PCI_ERR_ANON_BUF_RD:
1751                 QPRINTK(qdev, RX_ERR, ERR,
1752                         "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1753                         ib_ae_rsp->q_id);
1754                 ql_queue_asic_error(qdev);
1755                 break;
1756
1757         default:
1758                 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1759                         ib_ae_rsp->event);
1760                 ql_queue_asic_error(qdev);
1761                 break;
1762         }
1763 }
1764
1765 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1766 {
1767         struct ql_adapter *qdev = rx_ring->qdev;
1768         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1769         struct ob_mac_iocb_rsp *net_rsp = NULL;
1770         int count = 0;
1771
1772         struct tx_ring *tx_ring;
1773         /* While there are entries in the completion queue. */
1774         while (prod != rx_ring->cnsmr_idx) {
1775
1776                 QPRINTK(qdev, RX_STATUS, DEBUG,
1777                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1778                         prod, rx_ring->cnsmr_idx);
1779
1780                 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1781                 rmb();
1782                 switch (net_rsp->opcode) {
1783
1784                 case OPCODE_OB_MAC_TSO_IOCB:
1785                 case OPCODE_OB_MAC_IOCB:
1786                         ql_process_mac_tx_intr(qdev, net_rsp);
1787                         break;
1788                 default:
1789                         QPRINTK(qdev, RX_STATUS, DEBUG,
1790                                 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1791                                 net_rsp->opcode);
1792                 }
1793                 count++;
1794                 ql_update_cq(rx_ring);
1795                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1796         }
1797         ql_write_cq_idx(rx_ring);
1798         tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1799         if (__netif_subqueue_stopped(qdev->ndev, tx_ring->wq_id) &&
1800                                         net_rsp != NULL) {
1801                 if (atomic_read(&tx_ring->queue_stopped) &&
1802                     (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1803                         /*
1804                          * The queue got stopped because the tx_ring was full.
1805                          * Wake it up, because it's now at least 25% empty.
1806                          */
1807                         netif_wake_subqueue(qdev->ndev, tx_ring->wq_id);
1808         }
1809
1810         return count;
1811 }
1812
1813 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1814 {
1815         struct ql_adapter *qdev = rx_ring->qdev;
1816         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1817         struct ql_net_rsp_iocb *net_rsp;
1818         int count = 0;
1819
1820         /* While there are entries in the completion queue. */
1821         while (prod != rx_ring->cnsmr_idx) {
1822
1823                 QPRINTK(qdev, RX_STATUS, DEBUG,
1824                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1825                         prod, rx_ring->cnsmr_idx);
1826
1827                 net_rsp = rx_ring->curr_entry;
1828                 rmb();
1829                 switch (net_rsp->opcode) {
1830                 case OPCODE_IB_MAC_IOCB:
1831                         ql_process_mac_rx_intr(qdev, rx_ring,
1832                                                (struct ib_mac_iocb_rsp *)
1833                                                net_rsp);
1834                         break;
1835
1836                 case OPCODE_IB_AE_IOCB:
1837                         ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1838                                                 net_rsp);
1839                         break;
1840                 default:
1841                         {
1842                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1843                                         "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1844                                         net_rsp->opcode);
1845                         }
1846                 }
1847                 count++;
1848                 ql_update_cq(rx_ring);
1849                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1850                 if (count == budget)
1851                         break;
1852         }
1853         ql_update_buffer_queues(qdev, rx_ring);
1854         ql_write_cq_idx(rx_ring);
1855         return count;
1856 }
1857
1858 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1859 {
1860         struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1861         struct ql_adapter *qdev = rx_ring->qdev;
1862         int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1863
1864         QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1865                 rx_ring->cq_id);
1866
1867         if (work_done < budget) {
1868                 napi_complete(napi);
1869                 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1870         }
1871         return work_done;
1872 }
1873
1874 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1875 {
1876         struct ql_adapter *qdev = netdev_priv(ndev);
1877
1878         qdev->vlgrp = grp;
1879         if (grp) {
1880                 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1881                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1882                            NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1883         } else {
1884                 QPRINTK(qdev, IFUP, DEBUG,
1885                         "Turning off VLAN in NIC_RCV_CFG.\n");
1886                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1887         }
1888 }
1889
1890 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1891 {
1892         struct ql_adapter *qdev = netdev_priv(ndev);
1893         u32 enable_bit = MAC_ADDR_E;
1894         int status;
1895
1896         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1897         if (status)
1898                 return;
1899         spin_lock(&qdev->hw_lock);
1900         if (ql_set_mac_addr_reg
1901             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1902                 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1903         }
1904         spin_unlock(&qdev->hw_lock);
1905         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1906 }
1907
1908 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1909 {
1910         struct ql_adapter *qdev = netdev_priv(ndev);
1911         u32 enable_bit = 0;
1912         int status;
1913
1914         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1915         if (status)
1916                 return;
1917
1918         spin_lock(&qdev->hw_lock);
1919         if (ql_set_mac_addr_reg
1920             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1921                 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1922         }
1923         spin_unlock(&qdev->hw_lock);
1924         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1925
1926 }
1927
1928 /* Worker thread to process a given rx_ring that is dedicated
1929  * to outbound completions.
1930  */
1931 static void ql_tx_clean(struct work_struct *work)
1932 {
1933         struct rx_ring *rx_ring =
1934             container_of(work, struct rx_ring, rx_work.work);
1935         ql_clean_outbound_rx_ring(rx_ring);
1936         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1937
1938 }
1939
1940 /* Worker thread to process a given rx_ring that is dedicated
1941  * to inbound completions.
1942  */
1943 static void ql_rx_clean(struct work_struct *work)
1944 {
1945         struct rx_ring *rx_ring =
1946             container_of(work, struct rx_ring, rx_work.work);
1947         ql_clean_inbound_rx_ring(rx_ring, 64);
1948         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1949 }
1950
1951 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1952 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1953 {
1954         struct rx_ring *rx_ring = dev_id;
1955         queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1956                               &rx_ring->rx_work, 0);
1957         return IRQ_HANDLED;
1958 }
1959
1960 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1961 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1962 {
1963         struct rx_ring *rx_ring = dev_id;
1964         napi_schedule(&rx_ring->napi);
1965         return IRQ_HANDLED;
1966 }
1967
1968 /* This handles a fatal error, MPI activity, and the default
1969  * rx_ring in an MSI-X multiple vector environment.
1970  * In MSI/Legacy environment it also process the rest of
1971  * the rx_rings.
1972  */
1973 static irqreturn_t qlge_isr(int irq, void *dev_id)
1974 {
1975         struct rx_ring *rx_ring = dev_id;
1976         struct ql_adapter *qdev = rx_ring->qdev;
1977         struct intr_context *intr_context = &qdev->intr_context[0];
1978         u32 var;
1979         int i;
1980         int work_done = 0;
1981
1982         spin_lock(&qdev->hw_lock);
1983         if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1984                 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1985                 spin_unlock(&qdev->hw_lock);
1986                 return IRQ_NONE;
1987         }
1988         spin_unlock(&qdev->hw_lock);
1989
1990         var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1991
1992         /*
1993          * Check for fatal error.
1994          */
1995         if (var & STS_FE) {
1996                 ql_queue_asic_error(qdev);
1997                 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1998                 var = ql_read32(qdev, ERR_STS);
1999                 QPRINTK(qdev, INTR, ERR,
2000                         "Resetting chip. Error Status Register = 0x%x\n", var);
2001                 return IRQ_HANDLED;
2002         }
2003
2004         /*
2005          * Check MPI processor activity.
2006          */
2007         if (var & STS_PI) {
2008                 /*
2009                  * We've got an async event or mailbox completion.
2010                  * Handle it and clear the source of the interrupt.
2011                  */
2012                 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
2013                 ql_disable_completion_interrupt(qdev, intr_context->intr);
2014                 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
2015                                       &qdev->mpi_work, 0);
2016                 work_done++;
2017         }
2018
2019         /*
2020          * Check the default queue and wake handler if active.
2021          */
2022         rx_ring = &qdev->rx_ring[0];
2023         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
2024                 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
2025                 ql_disable_completion_interrupt(qdev, intr_context->intr);
2026                 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
2027                                       &rx_ring->rx_work, 0);
2028                 work_done++;
2029         }
2030
2031         if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2032                 /*
2033                  * Start the DPC for each active queue.
2034                  */
2035                 for (i = 1; i < qdev->rx_ring_count; i++) {
2036                         rx_ring = &qdev->rx_ring[i];
2037                         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
2038                             rx_ring->cnsmr_idx) {
2039                                 QPRINTK(qdev, INTR, INFO,
2040                                         "Waking handler for rx_ring[%d].\n", i);
2041                                 ql_disable_completion_interrupt(qdev,
2042                                                                 intr_context->
2043                                                                 intr);
2044                                 if (i >= qdev->rss_ring_count)
2045                                         queue_delayed_work_on(rx_ring->cpu,
2046                                                               qdev->q_workqueue,
2047                                                               &rx_ring->rx_work,
2048                                                               0);
2049                                 else
2050                                         napi_schedule(&rx_ring->napi);
2051                                 work_done++;
2052                         }
2053                 }
2054         }
2055         ql_enable_completion_interrupt(qdev, intr_context->intr);
2056         return work_done ? IRQ_HANDLED : IRQ_NONE;
2057 }
2058
2059 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2060 {
2061
2062         if (skb_is_gso(skb)) {
2063                 int err;
2064                 if (skb_header_cloned(skb)) {
2065                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2066                         if (err)
2067                                 return err;
2068                 }
2069
2070                 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2071                 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
2072                 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2073                 mac_iocb_ptr->total_hdrs_len =
2074                     cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
2075                 mac_iocb_ptr->net_trans_offset =
2076                     cpu_to_le16(skb_network_offset(skb) |
2077                                 skb_transport_offset(skb)
2078                                 << OB_MAC_TRANSPORT_HDR_SHIFT);
2079                 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
2080                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
2081                 if (likely(skb->protocol == htons(ETH_P_IP))) {
2082                         struct iphdr *iph = ip_hdr(skb);
2083                         iph->check = 0;
2084                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2085                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2086                                                                  iph->daddr, 0,
2087                                                                  IPPROTO_TCP,
2088                                                                  0);
2089                 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2090                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
2091                         tcp_hdr(skb)->check =
2092                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2093                                              &ipv6_hdr(skb)->daddr,
2094                                              0, IPPROTO_TCP, 0);
2095                 }
2096                 return 1;
2097         }
2098         return 0;
2099 }
2100
2101 static void ql_hw_csum_setup(struct sk_buff *skb,
2102                              struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2103 {
2104         int len;
2105         struct iphdr *iph = ip_hdr(skb);
2106         __sum16 *check;
2107         mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2108         mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2109         mac_iocb_ptr->net_trans_offset =
2110                 cpu_to_le16(skb_network_offset(skb) |
2111                 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
2112
2113         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2114         len = (ntohs(iph->tot_len) - (iph->ihl << 2));
2115         if (likely(iph->protocol == IPPROTO_TCP)) {
2116                 check = &(tcp_hdr(skb)->check);
2117                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
2118                 mac_iocb_ptr->total_hdrs_len =
2119                     cpu_to_le16(skb_transport_offset(skb) +
2120                                 (tcp_hdr(skb)->doff << 2));
2121         } else {
2122                 check = &(udp_hdr(skb)->check);
2123                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
2124                 mac_iocb_ptr->total_hdrs_len =
2125                     cpu_to_le16(skb_transport_offset(skb) +
2126                                 sizeof(struct udphdr));
2127         }
2128         *check = ~csum_tcpudp_magic(iph->saddr,
2129                                     iph->daddr, len, iph->protocol, 0);
2130 }
2131
2132 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
2133 {
2134         struct tx_ring_desc *tx_ring_desc;
2135         struct ob_mac_iocb_req *mac_iocb_ptr;
2136         struct ql_adapter *qdev = netdev_priv(ndev);
2137         int tso;
2138         struct tx_ring *tx_ring;
2139         u32 tx_ring_idx = (u32) skb->queue_mapping;
2140
2141         tx_ring = &qdev->tx_ring[tx_ring_idx];
2142
2143         if (skb_padto(skb, ETH_ZLEN))
2144                 return NETDEV_TX_OK;
2145
2146         if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
2147                 QPRINTK(qdev, TX_QUEUED, INFO,
2148                         "%s: shutting down tx queue %d du to lack of resources.\n",
2149                         __func__, tx_ring_idx);
2150                 netif_stop_subqueue(ndev, tx_ring->wq_id);
2151                 atomic_inc(&tx_ring->queue_stopped);
2152                 return NETDEV_TX_BUSY;
2153         }
2154         tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
2155         mac_iocb_ptr = tx_ring_desc->queue_entry;
2156         memset((void *)mac_iocb_ptr, 0, sizeof(*mac_iocb_ptr));
2157
2158         mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
2159         mac_iocb_ptr->tid = tx_ring_desc->index;
2160         /* We use the upper 32-bits to store the tx queue for this IO.
2161          * When we get the completion we can use it to establish the context.
2162          */
2163         mac_iocb_ptr->txq_idx = tx_ring_idx;
2164         tx_ring_desc->skb = skb;
2165
2166         mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
2167
2168         if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
2169                 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
2170                         vlan_tx_tag_get(skb));
2171                 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
2172                 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
2173         }
2174         tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2175         if (tso < 0) {
2176                 dev_kfree_skb_any(skb);
2177                 return NETDEV_TX_OK;
2178         } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
2179                 ql_hw_csum_setup(skb,
2180                                  (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2181         }
2182         if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
2183                         NETDEV_TX_OK) {
2184                 QPRINTK(qdev, TX_QUEUED, ERR,
2185                                 "Could not map the segments.\n");
2186                 return NETDEV_TX_BUSY;
2187         }
2188         QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
2189         tx_ring->prod_idx++;
2190         if (tx_ring->prod_idx == tx_ring->wq_len)
2191                 tx_ring->prod_idx = 0;
2192         wmb();
2193
2194         ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
2195         QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
2196                 tx_ring->prod_idx, skb->len);
2197
2198         atomic_dec(&tx_ring->tx_count);
2199         return NETDEV_TX_OK;
2200 }
2201
2202 static void ql_free_shadow_space(struct ql_adapter *qdev)
2203 {
2204         if (qdev->rx_ring_shadow_reg_area) {
2205                 pci_free_consistent(qdev->pdev,
2206                                     PAGE_SIZE,
2207                                     qdev->rx_ring_shadow_reg_area,
2208                                     qdev->rx_ring_shadow_reg_dma);
2209                 qdev->rx_ring_shadow_reg_area = NULL;
2210         }
2211         if (qdev->tx_ring_shadow_reg_area) {
2212                 pci_free_consistent(qdev->pdev,
2213                                     PAGE_SIZE,
2214                                     qdev->tx_ring_shadow_reg_area,
2215                                     qdev->tx_ring_shadow_reg_dma);
2216                 qdev->tx_ring_shadow_reg_area = NULL;
2217         }
2218 }
2219
2220 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2221 {
2222         qdev->rx_ring_shadow_reg_area =
2223             pci_alloc_consistent(qdev->pdev,
2224                                  PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2225         if (qdev->rx_ring_shadow_reg_area == NULL) {
2226                 QPRINTK(qdev, IFUP, ERR,
2227                         "Allocation of RX shadow space failed.\n");
2228                 return -ENOMEM;
2229         }
2230         memset(qdev->rx_ring_shadow_reg_area, 0, PAGE_SIZE);
2231         qdev->tx_ring_shadow_reg_area =
2232             pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2233                                  &qdev->tx_ring_shadow_reg_dma);
2234         if (qdev->tx_ring_shadow_reg_area == NULL) {
2235                 QPRINTK(qdev, IFUP, ERR,
2236                         "Allocation of TX shadow space failed.\n");
2237                 goto err_wqp_sh_area;
2238         }
2239         memset(qdev->tx_ring_shadow_reg_area, 0, PAGE_SIZE);
2240         return 0;
2241
2242 err_wqp_sh_area:
2243         pci_free_consistent(qdev->pdev,
2244                             PAGE_SIZE,
2245                             qdev->rx_ring_shadow_reg_area,
2246                             qdev->rx_ring_shadow_reg_dma);
2247         return -ENOMEM;
2248 }
2249
2250 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2251 {
2252         struct tx_ring_desc *tx_ring_desc;
2253         int i;
2254         struct ob_mac_iocb_req *mac_iocb_ptr;
2255
2256         mac_iocb_ptr = tx_ring->wq_base;
2257         tx_ring_desc = tx_ring->q;
2258         for (i = 0; i < tx_ring->wq_len; i++) {
2259                 tx_ring_desc->index = i;
2260                 tx_ring_desc->skb = NULL;
2261                 tx_ring_desc->queue_entry = mac_iocb_ptr;
2262                 mac_iocb_ptr++;
2263                 tx_ring_desc++;
2264         }
2265         atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2266         atomic_set(&tx_ring->queue_stopped, 0);
2267 }
2268
2269 static void ql_free_tx_resources(struct ql_adapter *qdev,
2270                                  struct tx_ring *tx_ring)
2271 {
2272         if (tx_ring->wq_base) {
2273                 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2274                                     tx_ring->wq_base, tx_ring->wq_base_dma);
2275                 tx_ring->wq_base = NULL;
2276         }
2277         kfree(tx_ring->q);
2278         tx_ring->q = NULL;
2279 }
2280
2281 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2282                                  struct tx_ring *tx_ring)
2283 {
2284         tx_ring->wq_base =
2285             pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2286                                  &tx_ring->wq_base_dma);
2287
2288         if ((tx_ring->wq_base == NULL)
2289                 || tx_ring->wq_base_dma & WQ_ADDR_ALIGN) {
2290                 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2291                 return -ENOMEM;
2292         }
2293         tx_ring->q =
2294             kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2295         if (tx_ring->q == NULL)
2296                 goto err;
2297
2298         return 0;
2299 err:
2300         pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2301                             tx_ring->wq_base, tx_ring->wq_base_dma);
2302         return -ENOMEM;
2303 }
2304
2305 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2306 {
2307         int i;
2308         struct bq_desc *lbq_desc;
2309
2310         for (i = 0; i < rx_ring->lbq_len; i++) {
2311                 lbq_desc = &rx_ring->lbq[i];
2312                 if (lbq_desc->p.lbq_page) {
2313                         pci_unmap_page(qdev->pdev,
2314                                        pci_unmap_addr(lbq_desc, mapaddr),
2315                                        pci_unmap_len(lbq_desc, maplen),
2316                                        PCI_DMA_FROMDEVICE);
2317
2318                         put_page(lbq_desc->p.lbq_page);
2319                         lbq_desc->p.lbq_page = NULL;
2320                 }
2321         }
2322 }
2323
2324 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2325 {
2326         int i;
2327         struct bq_desc *sbq_desc;
2328
2329         for (i = 0; i < rx_ring->sbq_len; i++) {
2330                 sbq_desc = &rx_ring->sbq[i];
2331                 if (sbq_desc == NULL) {
2332                         QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2333                         return;
2334                 }
2335                 if (sbq_desc->p.skb) {
2336                         pci_unmap_single(qdev->pdev,
2337                                          pci_unmap_addr(sbq_desc, mapaddr),
2338                                          pci_unmap_len(sbq_desc, maplen),
2339                                          PCI_DMA_FROMDEVICE);
2340                         dev_kfree_skb(sbq_desc->p.skb);
2341                         sbq_desc->p.skb = NULL;
2342                 }
2343         }
2344 }
2345
2346 /* Free all large and small rx buffers associated
2347  * with the completion queues for this device.
2348  */
2349 static void ql_free_rx_buffers(struct ql_adapter *qdev)
2350 {
2351         int i;
2352         struct rx_ring *rx_ring;
2353
2354         for (i = 0; i < qdev->rx_ring_count; i++) {
2355                 rx_ring = &qdev->rx_ring[i];
2356                 if (rx_ring->lbq)
2357                         ql_free_lbq_buffers(qdev, rx_ring);
2358                 if (rx_ring->sbq)
2359                         ql_free_sbq_buffers(qdev, rx_ring);
2360         }
2361 }
2362
2363 static void ql_alloc_rx_buffers(struct ql_adapter *qdev)
2364 {
2365         struct rx_ring *rx_ring;
2366         int i;
2367
2368         for (i = 0; i < qdev->rx_ring_count; i++) {
2369                 rx_ring = &qdev->rx_ring[i];
2370                 if (rx_ring->type != TX_Q)
2371                         ql_update_buffer_queues(qdev, rx_ring);
2372         }
2373 }
2374
2375 static void ql_init_lbq_ring(struct ql_adapter *qdev,
2376                                 struct rx_ring *rx_ring)
2377 {
2378         int i;
2379         struct bq_desc *lbq_desc;
2380         __le64 *bq = rx_ring->lbq_base;
2381
2382         memset(rx_ring->lbq, 0, rx_ring->lbq_len * sizeof(struct bq_desc));
2383         for (i = 0; i < rx_ring->lbq_len; i++) {
2384                 lbq_desc = &rx_ring->lbq[i];
2385                 memset(lbq_desc, 0, sizeof(*lbq_desc));
2386                 lbq_desc->index = i;
2387                 lbq_desc->addr = bq;
2388                 bq++;
2389         }
2390 }
2391
2392 static void ql_init_sbq_ring(struct ql_adapter *qdev,
2393                                 struct rx_ring *rx_ring)
2394 {
2395         int i;
2396         struct bq_desc *sbq_desc;
2397         __le64 *bq = rx_ring->sbq_base;
2398
2399         memset(rx_ring->sbq, 0, rx_ring->sbq_len * sizeof(struct bq_desc));
2400         for (i = 0; i < rx_ring->sbq_len; i++) {
2401                 sbq_desc = &rx_ring->sbq[i];
2402                 memset(sbq_desc, 0, sizeof(*sbq_desc));
2403                 sbq_desc->index = i;
2404                 sbq_desc->addr = bq;
2405                 bq++;
2406         }
2407 }
2408
2409 static void ql_free_rx_resources(struct ql_adapter *qdev,
2410                                  struct rx_ring *rx_ring)
2411 {
2412         /* Free the small buffer queue. */
2413         if (rx_ring->sbq_base) {
2414                 pci_free_consistent(qdev->pdev,
2415                                     rx_ring->sbq_size,
2416                                     rx_ring->sbq_base, rx_ring->sbq_base_dma);
2417                 rx_ring->sbq_base = NULL;
2418         }
2419
2420         /* Free the small buffer queue control blocks. */
2421         kfree(rx_ring->sbq);
2422         rx_ring->sbq = NULL;
2423
2424         /* Free the large buffer queue. */
2425         if (rx_ring->lbq_base) {
2426                 pci_free_consistent(qdev->pdev,
2427                                     rx_ring->lbq_size,
2428                                     rx_ring->lbq_base, rx_ring->lbq_base_dma);
2429                 rx_ring->lbq_base = NULL;
2430         }
2431
2432         /* Free the large buffer queue control blocks. */
2433         kfree(rx_ring->lbq);
2434         rx_ring->lbq = NULL;
2435
2436         /* Free the rx queue. */
2437         if (rx_ring->cq_base) {
2438                 pci_free_consistent(qdev->pdev,
2439                                     rx_ring->cq_size,
2440                                     rx_ring->cq_base, rx_ring->cq_base_dma);
2441                 rx_ring->cq_base = NULL;
2442         }
2443 }
2444
2445 /* Allocate queues and buffers for this completions queue based
2446  * on the values in the parameter structure. */
2447 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2448                                  struct rx_ring *rx_ring)
2449 {
2450
2451         /*
2452          * Allocate the completion queue for this rx_ring.
2453          */
2454         rx_ring->cq_base =
2455             pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2456                                  &rx_ring->cq_base_dma);
2457
2458         if (rx_ring->cq_base == NULL) {
2459                 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2460                 return -ENOMEM;
2461         }
2462
2463         if (rx_ring->sbq_len) {
2464                 /*
2465                  * Allocate small buffer queue.
2466                  */
2467                 rx_ring->sbq_base =
2468                     pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2469                                          &rx_ring->sbq_base_dma);
2470
2471                 if (rx_ring->sbq_base == NULL) {
2472                         QPRINTK(qdev, IFUP, ERR,
2473                                 "Small buffer queue allocation failed.\n");
2474                         goto err_mem;
2475                 }
2476
2477                 /*
2478                  * Allocate small buffer queue control blocks.
2479                  */
2480                 rx_ring->sbq =
2481                     kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2482                             GFP_KERNEL);
2483                 if (rx_ring->sbq == NULL) {
2484                         QPRINTK(qdev, IFUP, ERR,
2485                                 "Small buffer queue control block allocation failed.\n");
2486                         goto err_mem;
2487                 }
2488
2489                 ql_init_sbq_ring(qdev, rx_ring);
2490         }
2491
2492         if (rx_ring->lbq_len) {
2493                 /*
2494                  * Allocate large buffer queue.
2495                  */
2496                 rx_ring->lbq_base =
2497                     pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2498                                          &rx_ring->lbq_base_dma);
2499
2500                 if (rx_ring->lbq_base == NULL) {
2501                         QPRINTK(qdev, IFUP, ERR,
2502                                 "Large buffer queue allocation failed.\n");
2503                         goto err_mem;
2504                 }
2505                 /*
2506                  * Allocate large buffer queue control blocks.
2507                  */
2508                 rx_ring->lbq =
2509                     kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2510                             GFP_KERNEL);
2511                 if (rx_ring->lbq == NULL) {
2512                         QPRINTK(qdev, IFUP, ERR,
2513                                 "Large buffer queue control block allocation failed.\n");
2514                         goto err_mem;
2515                 }
2516
2517                 ql_init_lbq_ring(qdev, rx_ring);
2518         }
2519
2520         return 0;
2521
2522 err_mem:
2523         ql_free_rx_resources(qdev, rx_ring);
2524         return -ENOMEM;
2525 }
2526
2527 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2528 {
2529         struct tx_ring *tx_ring;
2530         struct tx_ring_desc *tx_ring_desc;
2531         int i, j;
2532
2533         /*
2534          * Loop through all queues and free
2535          * any resources.
2536          */
2537         for (j = 0; j < qdev->tx_ring_count; j++) {
2538                 tx_ring = &qdev->tx_ring[j];
2539                 for (i = 0; i < tx_ring->wq_len; i++) {
2540                         tx_ring_desc = &tx_ring->q[i];
2541                         if (tx_ring_desc && tx_ring_desc->skb) {
2542                                 QPRINTK(qdev, IFDOWN, ERR,
2543                                 "Freeing lost SKB %p, from queue %d, index %d.\n",
2544                                         tx_ring_desc->skb, j,
2545                                         tx_ring_desc->index);
2546                                 ql_unmap_send(qdev, tx_ring_desc,
2547                                               tx_ring_desc->map_cnt);
2548                                 dev_kfree_skb(tx_ring_desc->skb);
2549                                 tx_ring_desc->skb = NULL;
2550                         }
2551                 }
2552         }
2553 }
2554
2555 static void ql_free_mem_resources(struct ql_adapter *qdev)
2556 {
2557         int i;
2558
2559         for (i = 0; i < qdev->tx_ring_count; i++)
2560                 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2561         for (i = 0; i < qdev->rx_ring_count; i++)
2562                 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2563         ql_free_shadow_space(qdev);
2564 }
2565
2566 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2567 {
2568         int i;
2569
2570         /* Allocate space for our shadow registers and such. */
2571         if (ql_alloc_shadow_space(qdev))
2572                 return -ENOMEM;
2573
2574         for (i = 0; i < qdev->rx_ring_count; i++) {
2575                 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2576                         QPRINTK(qdev, IFUP, ERR,
2577                                 "RX resource allocation failed.\n");
2578                         goto err_mem;
2579                 }
2580         }
2581         /* Allocate tx queue resources */
2582         for (i = 0; i < qdev->tx_ring_count; i++) {
2583                 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2584                         QPRINTK(qdev, IFUP, ERR,
2585                                 "TX resource allocation failed.\n");
2586                         goto err_mem;
2587                 }
2588         }
2589         return 0;
2590
2591 err_mem:
2592         ql_free_mem_resources(qdev);
2593         return -ENOMEM;
2594 }
2595
2596 /* Set up the rx ring control block and pass it to the chip.
2597  * The control block is defined as
2598  * "Completion Queue Initialization Control Block", or cqicb.
2599  */
2600 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2601 {
2602         struct cqicb *cqicb = &rx_ring->cqicb;
2603         void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2604                 (rx_ring->cq_id * RX_RING_SHADOW_SPACE);
2605         u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2606                 (rx_ring->cq_id * RX_RING_SHADOW_SPACE);
2607         void __iomem *doorbell_area =
2608             qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2609         int err = 0;
2610         u16 bq_len;
2611         u64 tmp;
2612         __le64 *base_indirect_ptr;
2613         int page_entries;
2614
2615         /* Set up the shadow registers for this ring. */
2616         rx_ring->prod_idx_sh_reg = shadow_reg;
2617         rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2618         shadow_reg += sizeof(u64);
2619         shadow_reg_dma += sizeof(u64);
2620         rx_ring->lbq_base_indirect = shadow_reg;
2621         rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2622         shadow_reg += (sizeof(u64) * MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
2623         shadow_reg_dma += (sizeof(u64) * MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
2624         rx_ring->sbq_base_indirect = shadow_reg;
2625         rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2626
2627         /* PCI doorbell mem area + 0x00 for consumer index register */
2628         rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2629         rx_ring->cnsmr_idx = 0;
2630         rx_ring->curr_entry = rx_ring->cq_base;
2631
2632         /* PCI doorbell mem area + 0x04 for valid register */
2633         rx_ring->valid_db_reg = doorbell_area + 0x04;
2634
2635         /* PCI doorbell mem area + 0x18 for large buffer consumer */
2636         rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2637
2638         /* PCI doorbell mem area + 0x1c */
2639         rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2640
2641         memset((void *)cqicb, 0, sizeof(struct cqicb));
2642         cqicb->msix_vect = rx_ring->irq;
2643
2644         bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2645         cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
2646
2647         cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
2648
2649         cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
2650
2651         /*
2652          * Set up the control block load flags.
2653          */
2654         cqicb->flags = FLAGS_LC |       /* Load queue base address */
2655             FLAGS_LV |          /* Load MSI-X vector */
2656             FLAGS_LI;           /* Load irq delay values */
2657         if (rx_ring->lbq_len) {
2658                 cqicb->flags |= FLAGS_LL;       /* Load lbq values */
2659                 tmp = (u64)rx_ring->lbq_base_dma;;
2660                 base_indirect_ptr = (__le64 *) rx_ring->lbq_base_indirect;
2661                 page_entries = 0;
2662                 do {
2663                         *base_indirect_ptr = cpu_to_le64(tmp);
2664                         tmp += DB_PAGE_SIZE;
2665                         base_indirect_ptr++;
2666                         page_entries++;
2667                 } while (page_entries < MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
2668                 cqicb->lbq_addr =
2669                     cpu_to_le64(rx_ring->lbq_base_indirect_dma);
2670                 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2671                         (u16) rx_ring->lbq_buf_size;
2672                 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2673                 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2674                         (u16) rx_ring->lbq_len;
2675                 cqicb->lbq_len = cpu_to_le16(bq_len);
2676                 rx_ring->lbq_prod_idx = 0;
2677                 rx_ring->lbq_curr_idx = 0;
2678                 rx_ring->lbq_clean_idx = 0;
2679                 rx_ring->lbq_free_cnt = rx_ring->lbq_len;
2680         }
2681         if (rx_ring->sbq_len) {
2682                 cqicb->flags |= FLAGS_LS;       /* Load sbq values */
2683                 tmp = (u64)rx_ring->sbq_base_dma;;
2684                 base_indirect_ptr = (__le64 *) rx_ring->sbq_base_indirect;
2685                 page_entries = 0;
2686                 do {
2687                         *base_indirect_ptr = cpu_to_le64(tmp);
2688                         tmp += DB_PAGE_SIZE;
2689                         base_indirect_ptr++;
2690                         page_entries++;
2691                 } while (page_entries < MAX_DB_PAGES_PER_BQ(rx_ring->sbq_len));
2692                 cqicb->sbq_addr =
2693                     cpu_to_le64(rx_ring->sbq_base_indirect_dma);
2694                 cqicb->sbq_buf_size =
2695                     cpu_to_le16((u16)(rx_ring->sbq_buf_size/2));
2696                 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2697                         (u16) rx_ring->sbq_len;
2698                 cqicb->sbq_len = cpu_to_le16(bq_len);
2699                 rx_ring->sbq_prod_idx = 0;
2700                 rx_ring->sbq_curr_idx = 0;
2701                 rx_ring->sbq_clean_idx = 0;
2702                 rx_ring->sbq_free_cnt = rx_ring->sbq_len;
2703         }
2704         switch (rx_ring->type) {
2705         case TX_Q:
2706                 /* If there's only one interrupt, then we use
2707                  * worker threads to process the outbound
2708                  * completion handling rx_rings. We do this so
2709                  * they can be run on multiple CPUs. There is
2710                  * room to play with this more where we would only
2711                  * run in a worker if there are more than x number
2712                  * of outbound completions on the queue and more
2713                  * than one queue active.  Some threshold that
2714                  * would indicate a benefit in spite of the cost
2715                  * of a context switch.
2716                  * If there's more than one interrupt, then the
2717                  * outbound completions are processed in the ISR.
2718                  */
2719                 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2720                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2721                 else {
2722                         /* With all debug warnings on we see a WARN_ON message
2723                          * when we free the skb in the interrupt context.
2724                          */
2725                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2726                 }
2727                 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2728                 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2729                 break;
2730         case DEFAULT_Q:
2731                 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2732                 cqicb->irq_delay = 0;
2733                 cqicb->pkt_delay = 0;
2734                 break;
2735         case RX_Q:
2736                 /* Inbound completion handling rx_rings run in
2737                  * separate NAPI contexts.
2738                  */
2739                 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2740                                64);
2741                 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2742                 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2743                 break;
2744         default:
2745                 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2746                         rx_ring->type);
2747         }
2748         QPRINTK(qdev, IFUP, DEBUG, "Initializing rx work queue.\n");
2749         err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2750                            CFG_LCQ, rx_ring->cq_id);
2751         if (err) {
2752                 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2753                 return err;
2754         }
2755         return err;
2756 }
2757
2758 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2759 {
2760         struct wqicb *wqicb = (struct wqicb *)tx_ring;
2761         void __iomem *doorbell_area =
2762             qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2763         void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2764             (tx_ring->wq_id * sizeof(u64));
2765         u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2766             (tx_ring->wq_id * sizeof(u64));
2767         int err = 0;
2768
2769         /*
2770          * Assign doorbell registers for this tx_ring.
2771          */
2772         /* TX PCI doorbell mem area for tx producer index */
2773         tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2774         tx_ring->prod_idx = 0;
2775         /* TX PCI doorbell mem area + 0x04 */
2776         tx_ring->valid_db_reg = doorbell_area + 0x04;
2777
2778         /*
2779          * Assign shadow registers for this tx_ring.
2780          */
2781         tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2782         tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2783
2784         wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2785         wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2786                                    Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2787         wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2788         wqicb->rid = 0;
2789         wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
2790
2791         wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
2792
2793         ql_init_tx_ring(qdev, tx_ring);
2794
2795         err = ql_write_cfg(qdev, wqicb, sizeof(*wqicb), CFG_LRQ,
2796                            (u16) tx_ring->wq_id);
2797         if (err) {
2798                 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2799                 return err;
2800         }
2801         QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded WQICB.\n");
2802         return err;
2803 }
2804
2805 static void ql_disable_msix(struct ql_adapter *qdev)
2806 {
2807         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2808                 pci_disable_msix(qdev->pdev);
2809                 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2810                 kfree(qdev->msi_x_entry);
2811                 qdev->msi_x_entry = NULL;
2812         } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2813                 pci_disable_msi(qdev->pdev);
2814                 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2815         }
2816 }
2817
2818 static void ql_enable_msix(struct ql_adapter *qdev)
2819 {
2820         int i;
2821
2822         qdev->intr_count = 1;
2823         /* Get the MSIX vectors. */
2824         if (irq_type == MSIX_IRQ) {
2825                 /* Try to alloc space for the msix struct,
2826                  * if it fails then go to MSI/legacy.
2827                  */
2828                 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2829                                             sizeof(struct msix_entry),
2830                                             GFP_KERNEL);
2831                 if (!qdev->msi_x_entry) {
2832                         irq_type = MSI_IRQ;
2833                         goto msi;
2834                 }
2835
2836                 for (i = 0; i < qdev->rx_ring_count; i++)
2837                         qdev->msi_x_entry[i].entry = i;
2838
2839                 if (!pci_enable_msix
2840                     (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2841                         set_bit(QL_MSIX_ENABLED, &qdev->flags);
2842                         qdev->intr_count = qdev->rx_ring_count;
2843                         QPRINTK(qdev, IFUP, DEBUG,
2844                                 "MSI-X Enabled, got %d vectors.\n",
2845                                 qdev->intr_count);
2846                         return;
2847                 } else {
2848                         kfree(qdev->msi_x_entry);
2849                         qdev->msi_x_entry = NULL;
2850                         QPRINTK(qdev, IFUP, WARNING,
2851                                 "MSI-X Enable failed, trying MSI.\n");
2852                         irq_type = MSI_IRQ;
2853                 }
2854         }
2855 msi:
2856         if (irq_type == MSI_IRQ) {
2857                 if (!pci_enable_msi(qdev->pdev)) {
2858                         set_bit(QL_MSI_ENABLED, &qdev->flags);
2859                         QPRINTK(qdev, IFUP, INFO,
2860                                 "Running with MSI interrupts.\n");
2861                         return;
2862                 }
2863         }
2864         irq_type = LEG_IRQ;
2865         QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2866 }
2867
2868 /*
2869  * Here we build the intr_context structures based on
2870  * our rx_ring count and intr vector count.
2871  * The intr_context structure is used to hook each vector
2872  * to possibly different handlers.
2873  */
2874 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2875 {
2876         int i = 0;
2877         struct intr_context *intr_context = &qdev->intr_context[0];
2878
2879         ql_enable_msix(qdev);
2880
2881         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2882                 /* Each rx_ring has it's
2883                  * own intr_context since we have separate
2884                  * vectors for each queue.
2885                  * This only true when MSI-X is enabled.
2886                  */
2887                 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2888                         qdev->rx_ring[i].irq = i;
2889                         intr_context->intr = i;
2890                         intr_context->qdev = qdev;
2891                         /*
2892                          * We set up each vectors enable/disable/read bits so
2893                          * there's no bit/mask calculations in the critical path.
2894                          */
2895                         intr_context->intr_en_mask =
2896                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2897                             INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2898                             | i;
2899                         intr_context->intr_dis_mask =
2900                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2901                             INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2902                             INTR_EN_IHD | i;
2903                         intr_context->intr_read_mask =
2904                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2905                             INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2906                             i;
2907
2908                         if (i < qdev->rss_ring_count) {
2909                                 /*
2910                                  * Inbound queues handle unicast frames only.
2911                                  */
2912                                 intr_context->handler = qlge_msix_rx_isr;
2913                                 sprintf(intr_context->name, "%s-rx-%d",
2914                                         qdev->ndev->name, i);
2915                         } else {
2916                                 /*
2917                                  * Outbound queue is for outbound completions only.
2918                                  */
2919                                 intr_context->handler = qlge_msix_tx_isr;
2920                                 sprintf(intr_context->name, "%s-tx-%d",
2921                                         qdev->ndev->name, i);
2922                         }
2923                 }
2924         } else {
2925                 /*
2926                  * All rx_rings use the same intr_context since
2927                  * there is only one vector.
2928                  */
2929                 intr_context->intr = 0;
2930                 intr_context->qdev = qdev;
2931                 /*
2932                  * We set up each vectors enable/disable/read bits so
2933                  * there's no bit/mask calculations in the critical path.
2934                  */
2935                 intr_context->intr_en_mask =
2936                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2937                 intr_context->intr_dis_mask =
2938                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2939                     INTR_EN_TYPE_DISABLE;
2940                 intr_context->intr_read_mask =
2941                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2942                 /*
2943                  * Single interrupt means one handler for all rings.
2944                  */
2945                 intr_context->handler = qlge_isr;
2946                 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2947                 for (i = 0; i < qdev->rx_ring_count; i++)
2948                         qdev->rx_ring[i].irq = 0;
2949         }
2950 }
2951
2952 static void ql_free_irq(struct ql_adapter *qdev)
2953 {
2954         int i;
2955         struct intr_context *intr_context = &qdev->intr_context[0];
2956
2957         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2958                 if (intr_context->hooked) {
2959                         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2960                                 free_irq(qdev->msi_x_entry[i].vector,
2961                                          &qdev->rx_ring[i]);
2962                                 QPRINTK(qdev, IFDOWN, DEBUG,
2963                                         "freeing msix interrupt %d.\n", i);
2964                         } else {
2965                                 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2966                                 QPRINTK(qdev, IFDOWN, DEBUG,
2967                                         "freeing msi interrupt %d.\n", i);
2968                         }
2969                 }
2970         }
2971         ql_disable_msix(qdev);
2972 }
2973
2974 static int ql_request_irq(struct ql_adapter *qdev)
2975 {
2976         int i;
2977         int status = 0;
2978         struct pci_dev *pdev = qdev->pdev;
2979         struct intr_context *intr_context = &qdev->intr_context[0];
2980
2981         ql_resolve_queues_to_irqs(qdev);
2982
2983         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2984                 atomic_set(&intr_context->irq_cnt, 0);
2985                 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2986                         status = request_irq(qdev->msi_x_entry[i].vector,
2987                                              intr_context->handler,
2988                                              0,
2989                                              intr_context->name,
2990                                              &qdev->rx_ring[i]);
2991                         if (status) {
2992                                 QPRINTK(qdev, IFUP, ERR,
2993                                         "Failed request for MSIX interrupt %d.\n",
2994                                         i);
2995                                 goto err_irq;
2996                         } else {
2997                                 QPRINTK(qdev, IFUP, DEBUG,
2998                                         "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2999                                         i,
3000                                         qdev->rx_ring[i].type ==
3001                                         DEFAULT_Q ? "DEFAULT_Q" : "",
3002                                         qdev->rx_ring[i].type ==
3003                                         TX_Q ? "TX_Q" : "",
3004                                         qdev->rx_ring[i].type ==
3005                                         RX_Q ? "RX_Q" : "", intr_context->name);
3006                         }
3007                 } else {
3008                         QPRINTK(qdev, IFUP, DEBUG,
3009                                 "trying msi or legacy interrupts.\n");
3010                         QPRINTK(qdev, IFUP, DEBUG,
3011                                 "%s: irq = %d.\n", __func__, pdev->irq);
3012                         QPRINTK(qdev, IFUP, DEBUG,
3013                                 "%s: context->name = %s.\n", __func__,
3014                                intr_context->name);
3015                         QPRINTK(qdev, IFUP, DEBUG,
3016                                 "%s: dev_id = 0x%p.\n", __func__,
3017                                &qdev->rx_ring[0]);
3018                         status =
3019                             request_irq(pdev->irq, qlge_isr,
3020                                         test_bit(QL_MSI_ENABLED,
3021                                                  &qdev->
3022                                                  flags) ? 0 : IRQF_SHARED,
3023                                         intr_context->name, &qdev->rx_ring[0]);
3024                         if (status)
3025                                 goto err_irq;
3026
3027                         QPRINTK(qdev, IFUP, ERR,
3028                                 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
3029                                 i,
3030                                 qdev->rx_ring[0].type ==
3031                                 DEFAULT_Q ? "DEFAULT_Q" : "",
3032                                 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
3033                                 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
3034                                 intr_context->name);
3035                 }
3036                 intr_context->hooked = 1;
3037         }
3038         return status;
3039 err_irq:
3040         QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
3041         ql_free_irq(qdev);
3042         return status;
3043 }
3044
3045 static int ql_start_rss(struct ql_adapter *qdev)
3046 {
3047         struct ricb *ricb = &qdev->ricb;
3048         int status = 0;
3049         int i;
3050         u8 *hash_id = (u8 *) ricb->hash_cq_id;
3051
3052         memset((void *)ricb, 0, sizeof(*ricb));
3053
3054         ricb->base_cq = RSS_L4K;
3055         ricb->flags =
3056             (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
3057              RSS_RT6);
3058         ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
3059
3060         /*
3061          * Fill out the Indirection Table.
3062          */
3063         for (i = 0; i < 256; i++)
3064                 hash_id[i] = i & (qdev->rss_ring_count - 1);
3065
3066         /*
3067          * Random values for the IPv6 and IPv4 Hash Keys.
3068          */
3069         get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
3070         get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
3071
3072         QPRINTK(qdev, IFUP, DEBUG, "Initializing RSS.\n");
3073
3074         status = ql_write_cfg(qdev, ricb, sizeof(*ricb), CFG_LR, 0);
3075         if (status) {
3076                 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
3077                 return status;
3078         }
3079         QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded RICB.\n");
3080         return status;
3081 }
3082
3083 static int ql_clear_routing_entries(struct ql_adapter *qdev)
3084 {
3085         int i, status = 0;
3086
3087         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3088         if (status)
3089                 return status;
3090         /* Clear all the entries in the routing table. */
3091         for (i = 0; i < 16; i++) {
3092                 status = ql_set_routing_reg(qdev, i, 0, 0);
3093                 if (status) {
3094                         QPRINTK(qdev, IFUP, ERR,
3095                                 "Failed to init routing register for CAM "
3096                                 "packets.\n");
3097                         break;
3098                 }
3099         }
3100         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3101         return status;
3102 }
3103
3104 /* Initialize the frame-to-queue routing. */
3105 static int ql_route_initialize(struct ql_adapter *qdev)
3106 {
3107         int status = 0;
3108
3109         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3110         if (status)
3111                 return status;
3112
3113         /* Clear all the entries in the routing table. */
3114         status = ql_clear_routing_entries(qdev);
3115         if (status)
3116                 goto exit;
3117
3118         status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
3119         if (status) {
3120                 QPRINTK(qdev, IFUP, ERR,
3121                         "Failed to init routing register for error packets.\n");
3122                 goto exit;
3123         }
3124         status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
3125         if (status) {
3126                 QPRINTK(qdev, IFUP, ERR,
3127                         "Failed to init routing register for broadcast packets.\n");
3128                 goto exit;
3129         }
3130         /* If we have more than one inbound queue, then turn on RSS in the
3131          * routing block.
3132          */
3133         if (qdev->rss_ring_count > 1) {
3134                 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
3135                                         RT_IDX_RSS_MATCH, 1);
3136                 if (status) {
3137                         QPRINTK(qdev, IFUP, ERR,
3138                                 "Failed to init routing register for MATCH RSS packets.\n");
3139                         goto exit;
3140                 }
3141         }
3142
3143         status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
3144                                     RT_IDX_CAM_HIT, 1);
3145         if (status)
3146                 QPRINTK(qdev, IFUP, ERR,
3147                         "Failed to init routing register for CAM packets.\n");
3148 exit:
3149         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3150         return status;
3151 }
3152
3153 int ql_cam_route_initialize(struct ql_adapter *qdev)
3154 {
3155         int status, set;
3156
3157         /* If check if the link is up and use to
3158          * determine if we are setting or clearing
3159          * the MAC address in the CAM.
3160          */
3161         set = ql_read32(qdev, STS);
3162         set &= qdev->port_link_up;
3163         status = ql_set_mac_addr(qdev, set);
3164         if (status) {
3165                 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3166                 return status;
3167         }
3168
3169         status = ql_route_initialize(qdev);
3170         if (status)
3171                 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3172
3173         return status;
3174 }
3175
3176 static int ql_adapter_initialize(struct ql_adapter *qdev)
3177 {
3178         u32 value, mask;
3179         int i;
3180         int status = 0;
3181
3182         /*
3183          * Set up the System register to halt on errors.
3184          */
3185         value = SYS_EFE | SYS_FAE;
3186         mask = value << 16;
3187         ql_write32(qdev, SYS, mask | value);
3188
3189         /* Set the default queue, and VLAN behavior. */
3190         value = NIC_RCV_CFG_DFQ | NIC_RCV_CFG_RV;
3191         mask = NIC_RCV_CFG_DFQ_MASK | (NIC_RCV_CFG_RV << 16);
3192         ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3193
3194         /* Set the MPI interrupt to enabled. */
3195         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3196
3197         /* Enable the function, set pagesize, enable error checking. */
3198         value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3199             FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
3200
3201         /* Set/clear header splitting. */
3202         mask = FSC_VM_PAGESIZE_MASK |
3203             FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3204         ql_write32(qdev, FSC, mask | value);
3205
3206         ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3207                 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3208
3209         /* Start up the rx queues. */
3210         for (i = 0; i < qdev->rx_ring_count; i++) {
3211                 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3212                 if (status) {
3213                         QPRINTK(qdev, IFUP, ERR,
3214                                 "Failed to start rx ring[%d].\n", i);
3215                         return status;
3216                 }
3217         }
3218
3219         /* If there is more than one inbound completion queue
3220          * then download a RICB to configure RSS.
3221          */
3222         if (qdev->rss_ring_count > 1) {
3223                 status = ql_start_rss(qdev);
3224                 if (status) {
3225                         QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3226                         return status;
3227                 }
3228         }
3229
3230         /* Start up the tx queues. */
3231         for (i = 0; i < qdev->tx_ring_count; i++) {
3232                 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3233                 if (status) {
3234                         QPRINTK(qdev, IFUP, ERR,
3235                                 "Failed to start tx ring[%d].\n", i);
3236                         return status;
3237                 }
3238         }
3239
3240         /* Initialize the port and set the max framesize. */
3241         status = qdev->nic_ops->port_initialize(qdev);
3242        if (status) {
3243               QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3244               return status;
3245        }
3246
3247         /* Set up the MAC address and frame routing filter. */
3248         status = ql_cam_route_initialize(qdev);
3249         if (status) {
3250                 QPRINTK(qdev, IFUP, ERR,
3251                                 "Failed to init CAM/Routing tables.\n");
3252                 return status;
3253         }
3254
3255         /* Start NAPI for the RSS queues. */
3256         for (i = 0; i < qdev->rss_ring_count; i++) {
3257                 QPRINTK(qdev, IFUP, DEBUG, "Enabling NAPI for rx_ring[%d].\n",
3258                         i);
3259                 napi_enable(&qdev->rx_ring[i].napi);
3260         }
3261
3262         return status;
3263 }
3264
3265 /* Issue soft reset to chip. */
3266 static int ql_adapter_reset(struct ql_adapter *qdev)
3267 {
3268         u32 value;
3269         int status = 0;
3270         unsigned long end_jiffies;
3271
3272         /* Clear all the entries in the routing table. */
3273         status = ql_clear_routing_entries(qdev);
3274         if (status) {
3275                 QPRINTK(qdev, IFUP, ERR, "Failed to clear routing bits.\n");
3276                 return status;
3277         }
3278
3279         end_jiffies = jiffies +
3280                 max((unsigned long)1, usecs_to_jiffies(30));
3281         ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3282
3283         do {
3284                 value = ql_read32(qdev, RST_FO);
3285                 if ((value & RST_FO_FR) == 0)
3286                         break;
3287                 cpu_relax();
3288         } while (time_before(jiffies, end_jiffies));
3289
3290         if (value & RST_FO_FR) {
3291                 QPRINTK(qdev, IFDOWN, ERR,
3292                         "ETIMEDOUT!!! errored out of resetting the chip!\n");
3293                 status = -ETIMEDOUT;
3294         }
3295
3296         return status;
3297 }
3298
3299 static void ql_display_dev_info(struct net_device *ndev)
3300 {
3301         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3302
3303         QPRINTK(qdev, PROBE, INFO,
3304                 "Function #%d, Port %d, NIC Roll %d, NIC Rev = %d, "
3305                 "XG Roll = %d, XG Rev = %d.\n",
3306                 qdev->func,
3307                 qdev->port,
3308                 qdev->chip_rev_id & 0x0000000f,
3309                 qdev->chip_rev_id >> 4 & 0x0000000f,
3310                 qdev->chip_rev_id >> 8 & 0x0000000f,
3311                 qdev->chip_rev_id >> 12 & 0x0000000f);
3312         QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3313 }
3314
3315 static int ql_adapter_down(struct ql_adapter *qdev)
3316 {
3317         int i, status = 0;
3318         struct rx_ring *rx_ring;
3319
3320         ql_link_off(qdev);
3321
3322         /* Don't kill the reset worker thread if we
3323          * are in the process of recovery.
3324          */
3325         if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3326                 cancel_delayed_work_sync(&qdev->asic_reset_work);
3327         cancel_delayed_work_sync(&qdev->mpi_reset_work);
3328         cancel_delayed_work_sync(&qdev->mpi_work);
3329         cancel_delayed_work_sync(&qdev->mpi_idc_work);
3330         cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
3331
3332         /* The default queue at index 0 is always processed in
3333          * a workqueue.
3334          */
3335         cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3336
3337         /* The rest of the rx_rings are processed in
3338          * a workqueue only if it's a single interrupt
3339          * environment (MSI/Legacy).
3340          */
3341         for (i = 1; i < qdev->rx_ring_count; i++) {
3342                 rx_ring = &qdev->rx_ring[i];
3343                 /* Only the RSS rings use NAPI on multi irq
3344                  * environment.  Outbound completion processing
3345                  * is done in interrupt context.
3346                  */
3347                 if (i <= qdev->rss_ring_count) {
3348                         napi_disable(&rx_ring->napi);
3349                 } else {
3350                         cancel_delayed_work_sync(&rx_ring->rx_work);
3351                 }
3352         }
3353
3354         clear_bit(QL_ADAPTER_UP, &qdev->flags);
3355
3356         ql_disable_interrupts(qdev);
3357
3358         ql_tx_ring_clean(qdev);
3359
3360         /* Call netif_napi_del() from common point.
3361          */
3362         for (i = 0; i < qdev->rss_ring_count; i++)
3363                 netif_napi_del(&qdev->rx_ring[i].napi);
3364
3365         ql_free_rx_buffers(qdev);
3366
3367         spin_lock(&qdev->hw_lock);
3368         status = ql_adapter_reset(qdev);
3369         if (status)
3370                 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3371                         qdev->func);
3372         spin_unlock(&qdev->hw_lock);
3373         return status;
3374 }
3375
3376 static int ql_adapter_up(struct ql_adapter *qdev)
3377 {
3378         int err = 0;
3379
3380         err = ql_adapter_initialize(qdev);
3381         if (err) {
3382                 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3383                 goto err_init;
3384         }
3385         set_bit(QL_ADAPTER_UP, &qdev->flags);
3386         ql_alloc_rx_buffers(qdev);
3387         /* If the port is initialized and the
3388          * link is up the turn on the carrier.
3389          */
3390         if ((ql_read32(qdev, STS) & qdev->port_init) &&
3391                         (ql_read32(qdev, STS) & qdev->port_link_up))
3392                 ql_link_on(qdev);
3393         ql_enable_interrupts(qdev);
3394         ql_enable_all_completion_interrupts(qdev);
3395         netif_tx_start_all_queues(qdev->ndev);
3396
3397         return 0;
3398 err_init:
3399         ql_adapter_reset(qdev);
3400         return err;
3401 }
3402
3403 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3404 {
3405         ql_free_mem_resources(qdev);
3406         ql_free_irq(qdev);
3407 }
3408
3409 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3410 {
3411         int status = 0;
3412
3413         if (ql_alloc_mem_resources(qdev)) {
3414                 QPRINTK(qdev, IFUP, ERR, "Unable to  allocate memory.\n");
3415                 return -ENOMEM;
3416         }
3417         status = ql_request_irq(qdev);
3418         return status;
3419 }
3420
3421 static int qlge_close(struct net_device *ndev)
3422 {
3423         struct ql_adapter *qdev = netdev_priv(ndev);
3424
3425         /*
3426          * Wait for device to recover from a reset.
3427          * (Rarely happens, but possible.)
3428          */
3429         while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3430                 msleep(1);
3431         ql_adapter_down(qdev);
3432         ql_release_adapter_resources(qdev);
3433         return 0;
3434 }
3435
3436 static int ql_configure_rings(struct ql_adapter *qdev)
3437 {
3438         int i;
3439         struct rx_ring *rx_ring;
3440         struct tx_ring *tx_ring;
3441         int cpu_cnt = num_online_cpus();
3442
3443         /*
3444          * For each processor present we allocate one
3445          * rx_ring for outbound completions, and one
3446          * rx_ring for inbound completions.  Plus there is
3447          * always the one default queue.  For the CPU
3448          * counts we end up with the following rx_rings:
3449          * rx_ring count =
3450          *  one default queue +
3451          *  (CPU count * outbound completion rx_ring) +
3452          *  (CPU count * inbound (RSS) completion rx_ring)
3453          * To keep it simple we limit the total number of
3454          * queues to < 32, so we truncate CPU to 8.
3455          * This limitation can be removed when requested.
3456          */
3457
3458         if (cpu_cnt > MAX_CPUS)
3459                 cpu_cnt = MAX_CPUS;
3460
3461         /*
3462          * rx_ring[0] is always the default queue.
3463          */
3464         /* Allocate outbound completion ring for each CPU. */
3465         qdev->tx_ring_count = cpu_cnt;
3466         /* Allocate inbound completion (RSS) ring for each CPU. */
3467         qdev->rss_ring_count = cpu_cnt;
3468         /*
3469          * qdev->rx_ring_count:
3470          * Total number of rx_rings.  This includes the one
3471          * default queue, a number of outbound completion
3472          * handler rx_rings, and the number of inbound
3473          * completion handler rx_rings.
3474          */
3475         qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count;
3476
3477         for (i = 0; i < qdev->tx_ring_count; i++) {
3478                 tx_ring = &qdev->tx_ring[i];
3479                 memset((void *)tx_ring, 0, sizeof(*tx_ring));
3480                 tx_ring->qdev = qdev;
3481                 tx_ring->wq_id = i;
3482                 tx_ring->wq_len = qdev->tx_ring_size;
3483                 tx_ring->wq_size =
3484                     tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3485
3486                 /*
3487                  * The completion queue ID for the tx rings start
3488                  * immediately after the default Q ID, which is zero.
3489                  */
3490                 tx_ring->cq_id = i + qdev->rss_ring_count;
3491         }
3492
3493         for (i = 0; i < qdev->rx_ring_count; i++) {
3494                 rx_ring = &qdev->rx_ring[i];
3495                 memset((void *)rx_ring, 0, sizeof(*rx_ring));
3496                 rx_ring->qdev = qdev;
3497                 rx_ring->cq_id = i;
3498                 rx_ring->cpu = i % cpu_cnt;     /* CPU to run handler on. */
3499                 if (i < qdev->rss_ring_count) {
3500                         /* Inbound completions (RSS) queues */
3501                         rx_ring->cq_len = qdev->rx_ring_size;
3502                         rx_ring->cq_size =
3503                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3504                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3505                         rx_ring->lbq_size =
3506                             rx_ring->lbq_len * sizeof(__le64);
3507                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3508                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3509                         rx_ring->sbq_size =
3510                             rx_ring->sbq_len * sizeof(__le64);
3511                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3512                         rx_ring->type = RX_Q;
3513                 } else {
3514                         /*
3515                          * Outbound queue handles outbound completions only.
3516                          */
3517                         /* outbound cq is same size as tx_ring it services. */
3518                         rx_ring->cq_len = qdev->tx_ring_size;
3519                         rx_ring->cq_size =
3520                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3521                         rx_ring->lbq_len = 0;
3522                         rx_ring->lbq_size = 0;
3523                         rx_ring->lbq_buf_size = 0;
3524                         rx_ring->sbq_len = 0;
3525                         rx_ring->sbq_size = 0;
3526                         rx_ring->sbq_buf_size = 0;
3527                         rx_ring->type = TX_Q;
3528                 }
3529         }
3530         return 0;
3531 }
3532
3533 static int qlge_open(struct net_device *ndev)
3534 {
3535         int err = 0;
3536         struct ql_adapter *qdev = netdev_priv(ndev);
3537
3538         err = ql_configure_rings(qdev);
3539         if (err)
3540                 return err;
3541
3542         err = ql_get_adapter_resources(qdev);
3543         if (err)
3544                 goto error_up;
3545
3546         err = ql_adapter_up(qdev);
3547         if (err)
3548                 goto error_up;
3549
3550         return err;
3551
3552 error_up:
3553         ql_release_adapter_resources(qdev);
3554         return err;
3555 }
3556
3557 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3558 {
3559         struct ql_adapter *qdev = netdev_priv(ndev);
3560
3561         if (ndev->mtu == 1500 && new_mtu == 9000) {
3562                 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3563                 queue_delayed_work(qdev->workqueue,
3564                                 &qdev->mpi_port_cfg_work, 0);
3565         } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3566                 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3567         } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3568                    (ndev->mtu == 9000 && new_mtu == 9000)) {
3569                 return 0;
3570         } else
3571                 return -EINVAL;
3572         ndev->mtu = new_mtu;
3573         return 0;
3574 }
3575
3576 static struct net_device_stats *qlge_get_stats(struct net_device
3577                                                *ndev)
3578 {
3579         struct ql_adapter *qdev = netdev_priv(ndev);
3580         return &qdev->stats;
3581 }
3582
3583 static void qlge_set_multicast_list(struct net_device *ndev)
3584 {
3585         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3586         struct dev_mc_list *mc_ptr;
3587         int i, status;
3588
3589         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3590         if (status)
3591                 return;
3592         spin_lock(&qdev->hw_lock);
3593         /*
3594          * Set or clear promiscuous mode if a
3595          * transition is taking place.
3596          */
3597         if (ndev->flags & IFF_PROMISC) {
3598                 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3599                         if (ql_set_routing_reg
3600                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3601                                 QPRINTK(qdev, HW, ERR,
3602                                         "Failed to set promiscous mode.\n");
3603                         } else {
3604                                 set_bit(QL_PROMISCUOUS, &qdev->flags);
3605                         }
3606                 }
3607         } else {
3608                 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3609                         if (ql_set_routing_reg
3610                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3611                                 QPRINTK(qdev, HW, ERR,
3612                                         "Failed to clear promiscous mode.\n");
3613                         } else {
3614                                 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3615                         }
3616                 }
3617         }
3618
3619         /*
3620          * Set or clear all multicast mode if a
3621          * transition is taking place.
3622          */
3623         if ((ndev->flags & IFF_ALLMULTI) ||
3624             (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3625                 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3626                         if (ql_set_routing_reg
3627                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3628                                 QPRINTK(qdev, HW, ERR,
3629                                         "Failed to set all-multi mode.\n");
3630                         } else {
3631                                 set_bit(QL_ALLMULTI, &qdev->flags);
3632                         }
3633                 }
3634         } else {
3635                 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3636                         if (ql_set_routing_reg
3637                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3638                                 QPRINTK(qdev, HW, ERR,
3639                                         "Failed to clear all-multi mode.\n");
3640                         } else {
3641                                 clear_bit(QL_ALLMULTI, &qdev->flags);
3642                         }
3643                 }
3644         }
3645
3646         if (ndev->mc_count) {
3647                 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3648                 if (status)
3649                         goto exit;
3650                 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3651                      i++, mc_ptr = mc_ptr->next)
3652                         if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3653                                                 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3654                                 QPRINTK(qdev, HW, ERR,
3655                                         "Failed to loadmulticast address.\n");
3656                                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3657                                 goto exit;
3658                         }
3659                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3660                 if (ql_set_routing_reg
3661                     (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3662                         QPRINTK(qdev, HW, ERR,
3663                                 "Failed to set multicast match mode.\n");
3664                 } else {
3665                         set_bit(QL_ALLMULTI, &qdev->flags);
3666                 }
3667         }
3668 exit:
3669         spin_unlock(&qdev->hw_lock);
3670         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3671 }
3672
3673 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3674 {
3675         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3676         struct sockaddr *addr = p;
3677         int status;
3678
3679         if (netif_running(ndev))
3680                 return -EBUSY;
3681
3682         if (!is_valid_ether_addr(addr->sa_data))
3683                 return -EADDRNOTAVAIL;
3684         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3685
3686         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3687         if (status)
3688                 return status;
3689         spin_lock(&qdev->hw_lock);
3690         status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3691                         MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3692         spin_unlock(&qdev->hw_lock);
3693         if (status)
3694                 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3695         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3696         return status;
3697 }
3698
3699 static void qlge_tx_timeout(struct net_device *ndev)
3700 {
3701         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3702         ql_queue_asic_error(qdev);
3703 }
3704
3705 static void ql_asic_reset_work(struct work_struct *work)
3706 {
3707         struct ql_adapter *qdev =
3708             container_of(work, struct ql_adapter, asic_reset_work.work);
3709         int status;
3710
3711         status = ql_adapter_down(qdev);
3712         if (status)
3713                 goto error;
3714
3715         status = ql_adapter_up(qdev);
3716         if (status)
3717                 goto error;
3718
3719         return;
3720 error:
3721         QPRINTK(qdev, IFUP, ALERT,
3722                 "Driver up/down cycle failed, closing device\n");
3723         rtnl_lock();
3724         set_bit(QL_ADAPTER_UP, &qdev->flags);
3725         dev_close(qdev->ndev);
3726         rtnl_unlock();
3727 }
3728
3729 static struct nic_operations qla8012_nic_ops = {
3730         .get_flash              = ql_get_8012_flash_params,
3731         .port_initialize        = ql_8012_port_initialize,
3732 };
3733
3734 static struct nic_operations qla8000_nic_ops = {
3735         .get_flash              = ql_get_8000_flash_params,
3736         .port_initialize        = ql_8000_port_initialize,
3737 };
3738
3739 /* Find the pcie function number for the other NIC
3740  * on this chip.  Since both NIC functions share a
3741  * common firmware we have the lowest enabled function
3742  * do any common work.  Examples would be resetting
3743  * after a fatal firmware error, or doing a firmware
3744  * coredump.
3745  */
3746 static int ql_get_alt_pcie_func(struct ql_adapter *qdev)
3747 {
3748         int status = 0;
3749         u32 temp;
3750         u32 nic_func1, nic_func2;
3751
3752         status = ql_read_mpi_reg(qdev, MPI_TEST_FUNC_PORT_CFG,
3753                         &temp);
3754         if (status)
3755                 return status;
3756
3757         nic_func1 = ((temp >> MPI_TEST_NIC1_FUNC_SHIFT) &
3758                         MPI_TEST_NIC_FUNC_MASK);
3759         nic_func2 = ((temp >> MPI_TEST_NIC2_FUNC_SHIFT) &
3760                         MPI_TEST_NIC_FUNC_MASK);
3761
3762         if (qdev->func == nic_func1)
3763                 qdev->alt_func = nic_func2;
3764         else if (qdev->func == nic_func2)
3765                 qdev->alt_func = nic_func1;
3766         else
3767                 status = -EIO;
3768
3769         return status;
3770 }
3771
3772 static int ql_get_board_info(struct ql_adapter *qdev)
3773 {
3774         int status;
3775         qdev->func =
3776             (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3777         if (qdev->func > 3)
3778                 return -EIO;
3779
3780         status = ql_get_alt_pcie_func(qdev);
3781         if (status)
3782                 return status;
3783
3784         qdev->port = (qdev->func < qdev->alt_func) ? 0 : 1;
3785         if (qdev->port) {
3786                 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3787                 qdev->port_link_up = STS_PL1;
3788                 qdev->port_init = STS_PI1;
3789                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3790                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3791         } else {
3792                 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3793                 qdev->port_link_up = STS_PL0;
3794                 qdev->port_init = STS_PI0;
3795                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3796                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3797         }
3798         qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3799         qdev->device_id = qdev->pdev->device;
3800         if (qdev->device_id == QLGE_DEVICE_ID_8012)
3801                 qdev->nic_ops = &qla8012_nic_ops;
3802         else if (qdev->device_id == QLGE_DEVICE_ID_8000)
3803                 qdev->nic_ops = &qla8000_nic_ops;
3804         return status;
3805 }
3806
3807 static void ql_release_all(struct pci_dev *pdev)
3808 {
3809         struct net_device *ndev = pci_get_drvdata(pdev);
3810         struct ql_adapter *qdev = netdev_priv(ndev);
3811
3812         if (qdev->workqueue) {
3813                 destroy_workqueue(qdev->workqueue);
3814                 qdev->workqueue = NULL;
3815         }
3816         if (qdev->q_workqueue) {
3817                 destroy_workqueue(qdev->q_workqueue);
3818                 qdev->q_workqueue = NULL;
3819         }
3820         if (qdev->reg_base)
3821                 iounmap(qdev->reg_base);
3822         if (qdev->doorbell_area)
3823                 iounmap(qdev->doorbell_area);
3824         pci_release_regions(pdev);
3825         pci_set_drvdata(pdev, NULL);
3826 }
3827
3828 static int __devinit ql_init_device(struct pci_dev *pdev,
3829                                     struct net_device *ndev, int cards_found)
3830 {
3831         struct ql_adapter *qdev = netdev_priv(ndev);
3832         int pos, err = 0;
3833         u16 val16;
3834
3835         memset((void *)qdev, 0, sizeof(*qdev));
3836         err = pci_enable_device(pdev);
3837         if (err) {
3838                 dev_err(&pdev->dev, "PCI device enable failed.\n");
3839                 return err;
3840         }
3841
3842         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3843         if (pos <= 0) {
3844                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3845                         "aborting.\n");
3846                 goto err_out;
3847         } else {
3848                 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3849                 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3850                 val16 |= (PCI_EXP_DEVCTL_CERE |
3851                           PCI_EXP_DEVCTL_NFERE |
3852                           PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3853                 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3854         }
3855
3856         err = pci_request_regions(pdev, DRV_NAME);
3857         if (err) {
3858                 dev_err(&pdev->dev, "PCI region request failed.\n");
3859                 goto err_out;
3860         }
3861
3862         pci_set_master(pdev);
3863         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3864                 set_bit(QL_DMA64, &qdev->flags);
3865                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3866         } else {
3867                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3868                 if (!err)
3869                        err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3870         }
3871
3872         if (err) {
3873                 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3874                 goto err_out;
3875         }
3876
3877         pci_set_drvdata(pdev, ndev);
3878         qdev->reg_base =
3879             ioremap_nocache(pci_resource_start(pdev, 1),
3880                             pci_resource_len(pdev, 1));
3881         if (!qdev->reg_base) {
3882                 dev_err(&pdev->dev, "Register mapping failed.\n");
3883                 err = -ENOMEM;
3884                 goto err_out;
3885         }
3886
3887         qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3888         qdev->doorbell_area =
3889             ioremap_nocache(pci_resource_start(pdev, 3),
3890                             pci_resource_len(pdev, 3));
3891         if (!qdev->doorbell_area) {
3892                 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3893                 err = -ENOMEM;
3894                 goto err_out;
3895         }
3896
3897         qdev->ndev = ndev;
3898         qdev->pdev = pdev;
3899         err = ql_get_board_info(qdev);
3900         if (err) {
3901                 dev_err(&pdev->dev, "Register access failed.\n");
3902                 err = -EIO;
3903                 goto err_out;
3904         }
3905         qdev->msg_enable = netif_msg_init(debug, default_msg);
3906         spin_lock_init(&qdev->hw_lock);
3907         spin_lock_init(&qdev->stats_lock);
3908
3909         /* make sure the EEPROM is good */
3910         err = qdev->nic_ops->get_flash(qdev);
3911         if (err) {
3912                 dev_err(&pdev->dev, "Invalid FLASH.\n");
3913                 goto err_out;
3914         }
3915
3916         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3917
3918         /* Set up the default ring sizes. */
3919         qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3920         qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3921
3922         /* Set up the coalescing parameters. */
3923         qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3924         qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3925         qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3926         qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3927
3928         /*
3929          * Set up the operating parameters.
3930          */
3931         qdev->rx_csum = 1;
3932
3933         qdev->q_workqueue = create_workqueue(ndev->name);
3934         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3935         INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3936         INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3937         INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3938         INIT_DELAYED_WORK(&qdev->mpi_port_cfg_work, ql_mpi_port_cfg_work);
3939         INIT_DELAYED_WORK(&qdev->mpi_idc_work, ql_mpi_idc_work);
3940         mutex_init(&qdev->mpi_mutex);
3941         init_completion(&qdev->ide_completion);
3942
3943         if (!cards_found) {
3944                 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3945                 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3946                          DRV_NAME, DRV_VERSION);
3947         }
3948         return 0;
3949 err_out:
3950         ql_release_all(pdev);
3951         pci_disable_device(pdev);
3952         return err;
3953 }
3954
3955
3956 static const struct net_device_ops qlge_netdev_ops = {
3957         .ndo_open               = qlge_open,
3958         .ndo_stop               = qlge_close,
3959         .ndo_start_xmit         = qlge_send,
3960         .ndo_change_mtu         = qlge_change_mtu,
3961         .ndo_get_stats          = qlge_get_stats,
3962         .ndo_set_multicast_list = qlge_set_multicast_list,
3963         .ndo_set_mac_address    = qlge_set_mac_address,
3964         .ndo_validate_addr      = eth_validate_addr,
3965         .ndo_tx_timeout         = qlge_tx_timeout,
3966         .ndo_vlan_rx_register   = ql_vlan_rx_register,
3967         .ndo_vlan_rx_add_vid    = ql_vlan_rx_add_vid,
3968         .ndo_vlan_rx_kill_vid   = ql_vlan_rx_kill_vid,
3969 };
3970
3971 static int __devinit qlge_probe(struct pci_dev *pdev,
3972                                 const struct pci_device_id *pci_entry)
3973 {
3974         struct net_device *ndev = NULL;
3975         struct ql_adapter *qdev = NULL;
3976         static int cards_found = 0;
3977         int err = 0;
3978
3979         ndev = alloc_etherdev_mq(sizeof(struct ql_adapter),
3980                         min(MAX_CPUS, (int)num_online_cpus()));
3981         if (!ndev)
3982                 return -ENOMEM;
3983
3984         err = ql_init_device(pdev, ndev, cards_found);
3985         if (err < 0) {
3986                 free_netdev(ndev);
3987                 return err;
3988         }
3989
3990         qdev = netdev_priv(ndev);
3991         SET_NETDEV_DEV(ndev, &pdev->dev);
3992         ndev->features = (0
3993                           | NETIF_F_IP_CSUM
3994                           | NETIF_F_SG
3995                           | NETIF_F_TSO
3996                           | NETIF_F_TSO6
3997                           | NETIF_F_TSO_ECN
3998                           | NETIF_F_HW_VLAN_TX
3999                           | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
4000         ndev->features |= NETIF_F_GRO;
4001
4002         if (test_bit(QL_DMA64, &qdev->flags))
4003                 ndev->features |= NETIF_F_HIGHDMA;
4004
4005         /*
4006          * Set up net_device structure.
4007          */
4008         ndev->tx_queue_len = qdev->tx_ring_size;
4009         ndev->irq = pdev->irq;
4010
4011         ndev->netdev_ops = &qlge_netdev_ops;
4012         SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
4013         ndev->watchdog_timeo = 10 * HZ;
4014
4015         err = register_netdev(ndev);
4016         if (err) {
4017                 dev_err(&pdev->dev, "net device registration failed.\n");
4018                 ql_release_all(pdev);
4019                 pci_disable_device(pdev);
4020                 return err;
4021         }
4022         ql_link_off(qdev);
4023         ql_display_dev_info(ndev);
4024         cards_found++;
4025         return 0;
4026 }
4027
4028 static void __devexit qlge_remove(struct pci_dev *pdev)
4029 {
4030         struct net_device *ndev = pci_get_drvdata(pdev);
4031         unregister_netdev(ndev);
4032         ql_release_all(pdev);
4033         pci_disable_device(pdev);
4034         free_netdev(ndev);
4035 }
4036
4037 /*
4038  * This callback is called by the PCI subsystem whenever
4039  * a PCI bus error is detected.
4040  */
4041 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
4042                                                enum pci_channel_state state)
4043 {
4044         struct net_device *ndev = pci_get_drvdata(pdev);
4045         struct ql_adapter *qdev = netdev_priv(ndev);
4046
4047         netif_device_detach(ndev);
4048
4049         if (state == pci_channel_io_perm_failure)
4050                 return PCI_ERS_RESULT_DISCONNECT;
4051
4052         if (netif_running(ndev))
4053                 ql_adapter_down(qdev);
4054
4055         pci_disable_device(pdev);
4056
4057         /* Request a slot reset. */
4058         return PCI_ERS_RESULT_NEED_RESET;
4059 }
4060
4061 /*
4062  * This callback is called after the PCI buss has been reset.
4063  * Basically, this tries to restart the card from scratch.
4064  * This is a shortened version of the device probe/discovery code,
4065  * it resembles the first-half of the () routine.
4066  */
4067 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
4068 {
4069         struct net_device *ndev = pci_get_drvdata(pdev);
4070         struct ql_adapter *qdev = netdev_priv(ndev);
4071
4072         if (pci_enable_device(pdev)) {
4073                 QPRINTK(qdev, IFUP, ERR,
4074                         "Cannot re-enable PCI device after reset.\n");
4075                 return PCI_ERS_RESULT_DISCONNECT;
4076         }
4077
4078         pci_set_master(pdev);
4079
4080         netif_carrier_off(ndev);
4081         ql_adapter_reset(qdev);
4082
4083         /* Make sure the EEPROM is good */
4084         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
4085
4086         if (!is_valid_ether_addr(ndev->perm_addr)) {
4087                 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
4088                 return PCI_ERS_RESULT_DISCONNECT;
4089         }
4090
4091         return PCI_ERS_RESULT_RECOVERED;
4092 }
4093
4094 static void qlge_io_resume(struct pci_dev *pdev)
4095 {
4096         struct net_device *ndev = pci_get_drvdata(pdev);
4097         struct ql_adapter *qdev = netdev_priv(ndev);
4098
4099         pci_set_master(pdev);
4100
4101         if (netif_running(ndev)) {
4102                 if (ql_adapter_up(qdev)) {
4103                         QPRINTK(qdev, IFUP, ERR,
4104                                 "Device initialization failed after reset.\n");
4105                         return;
4106                 }
4107         }
4108
4109         netif_device_attach(ndev);
4110 }
4111
4112 static struct pci_error_handlers qlge_err_handler = {
4113         .error_detected = qlge_io_error_detected,
4114         .slot_reset = qlge_io_slot_reset,
4115         .resume = qlge_io_resume,
4116 };
4117
4118 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
4119 {
4120         struct net_device *ndev = pci_get_drvdata(pdev);
4121         struct ql_adapter *qdev = netdev_priv(ndev);
4122         int err;
4123
4124         netif_device_detach(ndev);
4125
4126         if (netif_running(ndev)) {
4127                 err = ql_adapter_down(qdev);
4128                 if (!err)
4129                         return err;
4130         }
4131
4132         err = pci_save_state(pdev);
4133         if (err)
4134                 return err;
4135
4136         pci_disable_device(pdev);
4137
4138         pci_set_power_state(pdev, pci_choose_state(pdev, state));
4139
4140         return 0;
4141 }
4142
4143 #ifdef CONFIG_PM
4144 static int qlge_resume(struct pci_dev *pdev)
4145 {
4146         struct net_device *ndev = pci_get_drvdata(pdev);
4147         struct ql_adapter *qdev = netdev_priv(ndev);
4148         int err;
4149
4150         pci_set_power_state(pdev, PCI_D0);
4151         pci_restore_state(pdev);
4152         err = pci_enable_device(pdev);
4153         if (err) {
4154                 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
4155                 return err;
4156         }
4157         pci_set_master(pdev);
4158
4159         pci_enable_wake(pdev, PCI_D3hot, 0);
4160         pci_enable_wake(pdev, PCI_D3cold, 0);
4161
4162         if (netif_running(ndev)) {
4163                 err = ql_adapter_up(qdev);
4164                 if (err)
4165                         return err;
4166         }
4167
4168         netif_device_attach(ndev);
4169
4170         return 0;
4171 }
4172 #endif /* CONFIG_PM */
4173
4174 static void qlge_shutdown(struct pci_dev *pdev)
4175 {
4176         qlge_suspend(pdev, PMSG_SUSPEND);
4177 }
4178
4179 static struct pci_driver qlge_driver = {
4180         .name = DRV_NAME,
4181         .id_table = qlge_pci_tbl,
4182         .probe = qlge_probe,
4183         .remove = __devexit_p(qlge_remove),
4184 #ifdef CONFIG_PM
4185         .suspend = qlge_suspend,
4186         .resume = qlge_resume,
4187 #endif
4188         .shutdown = qlge_shutdown,
4189         .err_handler = &qlge_err_handler
4190 };
4191
4192 static int __init qlge_init_module(void)
4193 {
4194         return pci_register_driver(&qlge_driver);
4195 }
4196
4197 static void __exit qlge_exit(void)
4198 {
4199         pci_unregister_driver(&qlge_driver);
4200 }
4201
4202 module_init(qlge_init_module);
4203 module_exit(qlge_exit);