trivial: fix ETIMEOUT -> ETIMEDOUT typos
[linux-2.6.git] / drivers / net / qlge / qlge_main.c
1 /*
2  * QLogic qlge NIC HBA Driver
3  * Copyright (c)  2003-2008 QLogic Corporation
4  * See LICENSE.qlge for copyright and licensing details.
5  * Author:     Linux qlge network device driver by
6  *                      Ron Mercer <ron.mercer@qlogic.com>
7  */
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/pagemap.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/dmapool.h>
19 #include <linux/mempool.h>
20 #include <linux/spinlock.h>
21 #include <linux/kthread.h>
22 #include <linux/interrupt.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/in.h>
26 #include <linux/ip.h>
27 #include <linux/ipv6.h>
28 #include <net/ipv6.h>
29 #include <linux/tcp.h>
30 #include <linux/udp.h>
31 #include <linux/if_arp.h>
32 #include <linux/if_ether.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/skbuff.h>
37 #include <linux/rtnetlink.h>
38 #include <linux/if_vlan.h>
39 #include <linux/delay.h>
40 #include <linux/mm.h>
41 #include <linux/vmalloc.h>
42 #include <net/ip6_checksum.h>
43
44 #include "qlge.h"
45
46 char qlge_driver_name[] = DRV_NAME;
47 const char qlge_driver_version[] = DRV_VERSION;
48
49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
50 MODULE_DESCRIPTION(DRV_STRING " ");
51 MODULE_LICENSE("GPL");
52 MODULE_VERSION(DRV_VERSION);
53
54 static const u32 default_msg =
55     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
56 /* NETIF_MSG_TIMER |    */
57     NETIF_MSG_IFDOWN |
58     NETIF_MSG_IFUP |
59     NETIF_MSG_RX_ERR |
60     NETIF_MSG_TX_ERR |
61 /*  NETIF_MSG_TX_QUEUED | */
62 /*  NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS | */
63 /* NETIF_MSG_PKTDATA | */
64     NETIF_MSG_HW | NETIF_MSG_WOL | 0;
65
66 static int debug = 0x00007fff;  /* defaults above */
67 module_param(debug, int, 0);
68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
69
70 #define MSIX_IRQ 0
71 #define MSI_IRQ 1
72 #define LEG_IRQ 2
73 static int irq_type = MSIX_IRQ;
74 module_param(irq_type, int, MSIX_IRQ);
75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
76
77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
78         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8012)},
79         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8000)},
80         /* required last entry */
81         {0,}
82 };
83
84 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
85
86 /* This hardware semaphore causes exclusive access to
87  * resources shared between the NIC driver, MPI firmware,
88  * FCOE firmware and the FC driver.
89  */
90 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
91 {
92         u32 sem_bits = 0;
93
94         switch (sem_mask) {
95         case SEM_XGMAC0_MASK:
96                 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
97                 break;
98         case SEM_XGMAC1_MASK:
99                 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
100                 break;
101         case SEM_ICB_MASK:
102                 sem_bits = SEM_SET << SEM_ICB_SHIFT;
103                 break;
104         case SEM_MAC_ADDR_MASK:
105                 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
106                 break;
107         case SEM_FLASH_MASK:
108                 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
109                 break;
110         case SEM_PROBE_MASK:
111                 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
112                 break;
113         case SEM_RT_IDX_MASK:
114                 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
115                 break;
116         case SEM_PROC_REG_MASK:
117                 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
118                 break;
119         default:
120                 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
121                 return -EINVAL;
122         }
123
124         ql_write32(qdev, SEM, sem_bits | sem_mask);
125         return !(ql_read32(qdev, SEM) & sem_bits);
126 }
127
128 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
129 {
130         unsigned int wait_count = 30;
131         do {
132                 if (!ql_sem_trylock(qdev, sem_mask))
133                         return 0;
134                 udelay(100);
135         } while (--wait_count);
136         return -ETIMEDOUT;
137 }
138
139 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
140 {
141         ql_write32(qdev, SEM, sem_mask);
142         ql_read32(qdev, SEM);   /* flush */
143 }
144
145 /* This function waits for a specific bit to come ready
146  * in a given register.  It is used mostly by the initialize
147  * process, but is also used in kernel thread API such as
148  * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
149  */
150 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
151 {
152         u32 temp;
153         int count = UDELAY_COUNT;
154
155         while (count) {
156                 temp = ql_read32(qdev, reg);
157
158                 /* check for errors */
159                 if (temp & err_bit) {
160                         QPRINTK(qdev, PROBE, ALERT,
161                                 "register 0x%.08x access error, value = 0x%.08x!.\n",
162                                 reg, temp);
163                         return -EIO;
164                 } else if (temp & bit)
165                         return 0;
166                 udelay(UDELAY_DELAY);
167                 count--;
168         }
169         QPRINTK(qdev, PROBE, ALERT,
170                 "Timed out waiting for reg %x to come ready.\n", reg);
171         return -ETIMEDOUT;
172 }
173
174 /* The CFG register is used to download TX and RX control blocks
175  * to the chip. This function waits for an operation to complete.
176  */
177 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
178 {
179         int count = UDELAY_COUNT;
180         u32 temp;
181
182         while (count) {
183                 temp = ql_read32(qdev, CFG);
184                 if (temp & CFG_LE)
185                         return -EIO;
186                 if (!(temp & bit))
187                         return 0;
188                 udelay(UDELAY_DELAY);
189                 count--;
190         }
191         return -ETIMEDOUT;
192 }
193
194
195 /* Used to issue init control blocks to hw. Maps control block,
196  * sets address, triggers download, waits for completion.
197  */
198 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
199                  u16 q_id)
200 {
201         u64 map;
202         int status = 0;
203         int direction;
204         u32 mask;
205         u32 value;
206
207         direction =
208             (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
209             PCI_DMA_FROMDEVICE;
210
211         map = pci_map_single(qdev->pdev, ptr, size, direction);
212         if (pci_dma_mapping_error(qdev->pdev, map)) {
213                 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
214                 return -ENOMEM;
215         }
216
217         status = ql_wait_cfg(qdev, bit);
218         if (status) {
219                 QPRINTK(qdev, IFUP, ERR,
220                         "Timed out waiting for CFG to come ready.\n");
221                 goto exit;
222         }
223
224         status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
225         if (status)
226                 goto exit;
227         ql_write32(qdev, ICB_L, (u32) map);
228         ql_write32(qdev, ICB_H, (u32) (map >> 32));
229         ql_sem_unlock(qdev, SEM_ICB_MASK);      /* does flush too */
230
231         mask = CFG_Q_MASK | (bit << 16);
232         value = bit | (q_id << CFG_Q_SHIFT);
233         ql_write32(qdev, CFG, (mask | value));
234
235         /*
236          * Wait for the bit to clear after signaling hw.
237          */
238         status = ql_wait_cfg(qdev, bit);
239 exit:
240         pci_unmap_single(qdev->pdev, map, size, direction);
241         return status;
242 }
243
244 /* Get a specific MAC address from the CAM.  Used for debug and reg dump. */
245 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
246                         u32 *value)
247 {
248         u32 offset = 0;
249         int status;
250
251         switch (type) {
252         case MAC_ADDR_TYPE_MULTI_MAC:
253         case MAC_ADDR_TYPE_CAM_MAC:
254                 {
255                         status =
256                             ql_wait_reg_rdy(qdev,
257                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
258                         if (status)
259                                 goto exit;
260                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
261                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
262                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
263                         status =
264                             ql_wait_reg_rdy(qdev,
265                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
266                         if (status)
267                                 goto exit;
268                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
269                         status =
270                             ql_wait_reg_rdy(qdev,
271                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
272                         if (status)
273                                 goto exit;
274                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
275                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
276                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
277                         status =
278                             ql_wait_reg_rdy(qdev,
279                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
280                         if (status)
281                                 goto exit;
282                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
283                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
284                                 status =
285                                     ql_wait_reg_rdy(qdev,
286                                         MAC_ADDR_IDX, MAC_ADDR_MW, 0);
287                                 if (status)
288                                         goto exit;
289                                 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
290                                            (index << MAC_ADDR_IDX_SHIFT) | /* index */
291                                            MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
292                                 status =
293                                     ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
294                                                     MAC_ADDR_MR, 0);
295                                 if (status)
296                                         goto exit;
297                                 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
298                         }
299                         break;
300                 }
301         case MAC_ADDR_TYPE_VLAN:
302         case MAC_ADDR_TYPE_MULTI_FLTR:
303         default:
304                 QPRINTK(qdev, IFUP, CRIT,
305                         "Address type %d not yet supported.\n", type);
306                 status = -EPERM;
307         }
308 exit:
309         return status;
310 }
311
312 /* Set up a MAC, multicast or VLAN address for the
313  * inbound frame matching.
314  */
315 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
316                                u16 index)
317 {
318         u32 offset = 0;
319         int status = 0;
320
321         switch (type) {
322         case MAC_ADDR_TYPE_MULTI_MAC:
323         case MAC_ADDR_TYPE_CAM_MAC:
324                 {
325                         u32 cam_output;
326                         u32 upper = (addr[0] << 8) | addr[1];
327                         u32 lower =
328                             (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
329                             (addr[5]);
330
331                         QPRINTK(qdev, IFUP, DEBUG,
332                                 "Adding %s address %pM"
333                                 " at index %d in the CAM.\n",
334                                 ((type ==
335                                   MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
336                                  "UNICAST"), addr, index);
337
338                         status =
339                             ql_wait_reg_rdy(qdev,
340                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
341                         if (status)
342                                 goto exit;
343                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
344                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
345                                    type);       /* type */
346                         ql_write32(qdev, MAC_ADDR_DATA, lower);
347                         status =
348                             ql_wait_reg_rdy(qdev,
349                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
350                         if (status)
351                                 goto exit;
352                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
353                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
354                                    type);       /* type */
355                         ql_write32(qdev, MAC_ADDR_DATA, upper);
356                         status =
357                             ql_wait_reg_rdy(qdev,
358                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
359                         if (status)
360                                 goto exit;
361                         ql_write32(qdev, MAC_ADDR_IDX, (offset) |       /* offset */
362                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
363                                    type);       /* type */
364                         /* This field should also include the queue id
365                            and possibly the function id.  Right now we hardcode
366                            the route field to NIC core.
367                          */
368                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
369                                 cam_output = (CAM_OUT_ROUTE_NIC |
370                                               (qdev->
371                                                func << CAM_OUT_FUNC_SHIFT) |
372                                               (qdev->
373                                                rss_ring_first_cq_id <<
374                                                CAM_OUT_CQ_ID_SHIFT));
375                                 if (qdev->vlgrp)
376                                         cam_output |= CAM_OUT_RV;
377                                 /* route to NIC core */
378                                 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
379                         }
380                         break;
381                 }
382         case MAC_ADDR_TYPE_VLAN:
383                 {
384                         u32 enable_bit = *((u32 *) &addr[0]);
385                         /* For VLAN, the addr actually holds a bit that
386                          * either enables or disables the vlan id we are
387                          * addressing. It's either MAC_ADDR_E on or off.
388                          * That's bit-27 we're talking about.
389                          */
390                         QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
391                                 (enable_bit ? "Adding" : "Removing"),
392                                 index, (enable_bit ? "to" : "from"));
393
394                         status =
395                             ql_wait_reg_rdy(qdev,
396                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
397                         if (status)
398                                 goto exit;
399                         ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
400                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
401                                    type |       /* type */
402                                    enable_bit); /* enable/disable */
403                         break;
404                 }
405         case MAC_ADDR_TYPE_MULTI_FLTR:
406         default:
407                 QPRINTK(qdev, IFUP, CRIT,
408                         "Address type %d not yet supported.\n", type);
409                 status = -EPERM;
410         }
411 exit:
412         return status;
413 }
414
415 /* Get a specific frame routing value from the CAM.
416  * Used for debug and reg dump.
417  */
418 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
419 {
420         int status = 0;
421
422         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
423         if (status)
424                 goto exit;
425
426         ql_write32(qdev, RT_IDX,
427                    RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
428         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
429         if (status)
430                 goto exit;
431         *value = ql_read32(qdev, RT_DATA);
432 exit:
433         return status;
434 }
435
436 /* The NIC function for this chip has 16 routing indexes.  Each one can be used
437  * to route different frame types to various inbound queues.  We send broadcast/
438  * multicast/error frames to the default queue for slow handling,
439  * and CAM hit/RSS frames to the fast handling queues.
440  */
441 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
442                               int enable)
443 {
444         int status = -EINVAL; /* Return error if no mask match. */
445         u32 value = 0;
446
447         QPRINTK(qdev, IFUP, DEBUG,
448                 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
449                 (enable ? "Adding" : "Removing"),
450                 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
451                 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
452                 ((index ==
453                   RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
454                 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
455                 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
456                 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
457                 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
458                 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
459                 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
460                 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
461                 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
462                 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
463                 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
464                 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
465                 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
466                 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
467                 (enable ? "to" : "from"));
468
469         switch (mask) {
470         case RT_IDX_CAM_HIT:
471                 {
472                         value = RT_IDX_DST_CAM_Q |      /* dest */
473                             RT_IDX_TYPE_NICQ |  /* type */
474                             (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
475                         break;
476                 }
477         case RT_IDX_VALID:      /* Promiscuous Mode frames. */
478                 {
479                         value = RT_IDX_DST_DFLT_Q |     /* dest */
480                             RT_IDX_TYPE_NICQ |  /* type */
481                             (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
482                         break;
483                 }
484         case RT_IDX_ERR:        /* Pass up MAC,IP,TCP/UDP error frames. */
485                 {
486                         value = RT_IDX_DST_DFLT_Q |     /* dest */
487                             RT_IDX_TYPE_NICQ |  /* type */
488                             (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
489                         break;
490                 }
491         case RT_IDX_BCAST:      /* Pass up Broadcast frames to default Q. */
492                 {
493                         value = RT_IDX_DST_DFLT_Q |     /* dest */
494                             RT_IDX_TYPE_NICQ |  /* type */
495                             (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
496                         break;
497                 }
498         case RT_IDX_MCAST:      /* Pass up All Multicast frames. */
499                 {
500                         value = RT_IDX_DST_CAM_Q |      /* dest */
501                             RT_IDX_TYPE_NICQ |  /* type */
502                             (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
503                         break;
504                 }
505         case RT_IDX_MCAST_MATCH:        /* Pass up matched Multicast frames. */
506                 {
507                         value = RT_IDX_DST_CAM_Q |      /* dest */
508                             RT_IDX_TYPE_NICQ |  /* type */
509                             (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
510                         break;
511                 }
512         case RT_IDX_RSS_MATCH:  /* Pass up matched RSS frames. */
513                 {
514                         value = RT_IDX_DST_RSS |        /* dest */
515                             RT_IDX_TYPE_NICQ |  /* type */
516                             (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
517                         break;
518                 }
519         case 0:         /* Clear the E-bit on an entry. */
520                 {
521                         value = RT_IDX_DST_DFLT_Q |     /* dest */
522                             RT_IDX_TYPE_NICQ |  /* type */
523                             (index << RT_IDX_IDX_SHIFT);/* index */
524                         break;
525                 }
526         default:
527                 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
528                         mask);
529                 status = -EPERM;
530                 goto exit;
531         }
532
533         if (value) {
534                 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
535                 if (status)
536                         goto exit;
537                 value |= (enable ? RT_IDX_E : 0);
538                 ql_write32(qdev, RT_IDX, value);
539                 ql_write32(qdev, RT_DATA, enable ? mask : 0);
540         }
541 exit:
542         return status;
543 }
544
545 static void ql_enable_interrupts(struct ql_adapter *qdev)
546 {
547         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
548 }
549
550 static void ql_disable_interrupts(struct ql_adapter *qdev)
551 {
552         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
553 }
554
555 /* If we're running with multiple MSI-X vectors then we enable on the fly.
556  * Otherwise, we may have multiple outstanding workers and don't want to
557  * enable until the last one finishes. In this case, the irq_cnt gets
558  * incremented everytime we queue a worker and decremented everytime
559  * a worker finishes.  Once it hits zero we enable the interrupt.
560  */
561 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
562 {
563         u32 var = 0;
564         unsigned long hw_flags = 0;
565         struct intr_context *ctx = qdev->intr_context + intr;
566
567         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
568                 /* Always enable if we're MSIX multi interrupts and
569                  * it's not the default (zeroeth) interrupt.
570                  */
571                 ql_write32(qdev, INTR_EN,
572                            ctx->intr_en_mask);
573                 var = ql_read32(qdev, STS);
574                 return var;
575         }
576
577         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
578         if (atomic_dec_and_test(&ctx->irq_cnt)) {
579                 ql_write32(qdev, INTR_EN,
580                            ctx->intr_en_mask);
581                 var = ql_read32(qdev, STS);
582         }
583         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
584         return var;
585 }
586
587 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
588 {
589         u32 var = 0;
590         struct intr_context *ctx;
591
592         /* HW disables for us if we're MSIX multi interrupts and
593          * it's not the default (zeroeth) interrupt.
594          */
595         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
596                 return 0;
597
598         ctx = qdev->intr_context + intr;
599         spin_lock(&qdev->hw_lock);
600         if (!atomic_read(&ctx->irq_cnt)) {
601                 ql_write32(qdev, INTR_EN,
602                 ctx->intr_dis_mask);
603                 var = ql_read32(qdev, STS);
604         }
605         atomic_inc(&ctx->irq_cnt);
606         spin_unlock(&qdev->hw_lock);
607         return var;
608 }
609
610 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
611 {
612         int i;
613         for (i = 0; i < qdev->intr_count; i++) {
614                 /* The enable call does a atomic_dec_and_test
615                  * and enables only if the result is zero.
616                  * So we precharge it here.
617                  */
618                 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
619                         i == 0))
620                         atomic_set(&qdev->intr_context[i].irq_cnt, 1);
621                 ql_enable_completion_interrupt(qdev, i);
622         }
623
624 }
625
626 static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str)
627 {
628         int status, i;
629         u16 csum = 0;
630         __le16 *flash = (__le16 *)&qdev->flash;
631
632         status = strncmp((char *)&qdev->flash, str, 4);
633         if (status) {
634                 QPRINTK(qdev, IFUP, ERR, "Invalid flash signature.\n");
635                 return  status;
636         }
637
638         for (i = 0; i < size; i++)
639                 csum += le16_to_cpu(*flash++);
640
641         if (csum)
642                 QPRINTK(qdev, IFUP, ERR,
643                         "Invalid flash checksum, csum = 0x%.04x.\n", csum);
644
645         return csum;
646 }
647
648 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
649 {
650         int status = 0;
651         /* wait for reg to come ready */
652         status = ql_wait_reg_rdy(qdev,
653                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
654         if (status)
655                 goto exit;
656         /* set up for reg read */
657         ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
658         /* wait for reg to come ready */
659         status = ql_wait_reg_rdy(qdev,
660                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
661         if (status)
662                 goto exit;
663          /* This data is stored on flash as an array of
664          * __le32.  Since ql_read32() returns cpu endian
665          * we need to swap it back.
666          */
667         *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
668 exit:
669         return status;
670 }
671
672 static int ql_get_8000_flash_params(struct ql_adapter *qdev)
673 {
674         u32 i, size;
675         int status;
676         __le32 *p = (__le32 *)&qdev->flash;
677         u32 offset;
678
679         /* Get flash offset for function and adjust
680          * for dword access.
681          */
682         if (!qdev->func)
683                 offset = FUNC0_FLASH_OFFSET / sizeof(u32);
684         else
685                 offset = FUNC1_FLASH_OFFSET / sizeof(u32);
686
687         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
688                 return -ETIMEDOUT;
689
690         size = sizeof(struct flash_params_8000) / sizeof(u32);
691         for (i = 0; i < size; i++, p++) {
692                 status = ql_read_flash_word(qdev, i+offset, p);
693                 if (status) {
694                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
695                         goto exit;
696                 }
697         }
698
699         status = ql_validate_flash(qdev,
700                         sizeof(struct flash_params_8000) / sizeof(u16),
701                         "8000");
702         if (status) {
703                 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
704                 status = -EINVAL;
705                 goto exit;
706         }
707
708         if (!is_valid_ether_addr(qdev->flash.flash_params_8000.mac_addr)) {
709                 QPRINTK(qdev, IFUP, ERR, "Invalid MAC address.\n");
710                 status = -EINVAL;
711                 goto exit;
712         }
713
714         memcpy(qdev->ndev->dev_addr,
715                 qdev->flash.flash_params_8000.mac_addr,
716                 qdev->ndev->addr_len);
717
718 exit:
719         ql_sem_unlock(qdev, SEM_FLASH_MASK);
720         return status;
721 }
722
723 static int ql_get_8012_flash_params(struct ql_adapter *qdev)
724 {
725         int i;
726         int status;
727         __le32 *p = (__le32 *)&qdev->flash;
728         u32 offset = 0;
729         u32 size = sizeof(struct flash_params_8012) / sizeof(u32);
730
731         /* Second function's parameters follow the first
732          * function's.
733          */
734         if (qdev->func)
735                 offset = size;
736
737         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
738                 return -ETIMEDOUT;
739
740         for (i = 0; i < size; i++, p++) {
741                 status = ql_read_flash_word(qdev, i+offset, p);
742                 if (status) {
743                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
744                         goto exit;
745                 }
746
747         }
748
749         status = ql_validate_flash(qdev,
750                         sizeof(struct flash_params_8012) / sizeof(u16),
751                         "8012");
752         if (status) {
753                 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
754                 status = -EINVAL;
755                 goto exit;
756         }
757
758         if (!is_valid_ether_addr(qdev->flash.flash_params_8012.mac_addr)) {
759                 status = -EINVAL;
760                 goto exit;
761         }
762
763         memcpy(qdev->ndev->dev_addr,
764                 qdev->flash.flash_params_8012.mac_addr,
765                 qdev->ndev->addr_len);
766
767 exit:
768         ql_sem_unlock(qdev, SEM_FLASH_MASK);
769         return status;
770 }
771
772 /* xgmac register are located behind the xgmac_addr and xgmac_data
773  * register pair.  Each read/write requires us to wait for the ready
774  * bit before reading/writing the data.
775  */
776 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
777 {
778         int status;
779         /* wait for reg to come ready */
780         status = ql_wait_reg_rdy(qdev,
781                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
782         if (status)
783                 return status;
784         /* write the data to the data reg */
785         ql_write32(qdev, XGMAC_DATA, data);
786         /* trigger the write */
787         ql_write32(qdev, XGMAC_ADDR, reg);
788         return status;
789 }
790
791 /* xgmac register are located behind the xgmac_addr and xgmac_data
792  * register pair.  Each read/write requires us to wait for the ready
793  * bit before reading/writing the data.
794  */
795 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
796 {
797         int status = 0;
798         /* wait for reg to come ready */
799         status = ql_wait_reg_rdy(qdev,
800                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
801         if (status)
802                 goto exit;
803         /* set up for reg read */
804         ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
805         /* wait for reg to come ready */
806         status = ql_wait_reg_rdy(qdev,
807                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
808         if (status)
809                 goto exit;
810         /* get the data */
811         *data = ql_read32(qdev, XGMAC_DATA);
812 exit:
813         return status;
814 }
815
816 /* This is used for reading the 64-bit statistics regs. */
817 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
818 {
819         int status = 0;
820         u32 hi = 0;
821         u32 lo = 0;
822
823         status = ql_read_xgmac_reg(qdev, reg, &lo);
824         if (status)
825                 goto exit;
826
827         status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
828         if (status)
829                 goto exit;
830
831         *data = (u64) lo | ((u64) hi << 32);
832
833 exit:
834         return status;
835 }
836
837 static int ql_8000_port_initialize(struct ql_adapter *qdev)
838 {
839         int status;
840         status = ql_mb_get_fw_state(qdev);
841         if (status)
842                 goto exit;
843         /* Wake up a worker to get/set the TX/RX frame sizes. */
844         queue_delayed_work(qdev->workqueue, &qdev->mpi_port_cfg_work, 0);
845 exit:
846         return status;
847 }
848
849 /* Take the MAC Core out of reset.
850  * Enable statistics counting.
851  * Take the transmitter/receiver out of reset.
852  * This functionality may be done in the MPI firmware at a
853  * later date.
854  */
855 static int ql_8012_port_initialize(struct ql_adapter *qdev)
856 {
857         int status = 0;
858         u32 data;
859
860         if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
861                 /* Another function has the semaphore, so
862                  * wait for the port init bit to come ready.
863                  */
864                 QPRINTK(qdev, LINK, INFO,
865                         "Another function has the semaphore, so wait for the port init bit to come ready.\n");
866                 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
867                 if (status) {
868                         QPRINTK(qdev, LINK, CRIT,
869                                 "Port initialize timed out.\n");
870                 }
871                 return status;
872         }
873
874         QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
875         /* Set the core reset. */
876         status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
877         if (status)
878                 goto end;
879         data |= GLOBAL_CFG_RESET;
880         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
881         if (status)
882                 goto end;
883
884         /* Clear the core reset and turn on jumbo for receiver. */
885         data &= ~GLOBAL_CFG_RESET;      /* Clear core reset. */
886         data |= GLOBAL_CFG_JUMBO;       /* Turn on jumbo. */
887         data |= GLOBAL_CFG_TX_STAT_EN;
888         data |= GLOBAL_CFG_RX_STAT_EN;
889         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
890         if (status)
891                 goto end;
892
893         /* Enable transmitter, and clear it's reset. */
894         status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
895         if (status)
896                 goto end;
897         data &= ~TX_CFG_RESET;  /* Clear the TX MAC reset. */
898         data |= TX_CFG_EN;      /* Enable the transmitter. */
899         status = ql_write_xgmac_reg(qdev, TX_CFG, data);
900         if (status)
901                 goto end;
902
903         /* Enable receiver and clear it's reset. */
904         status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
905         if (status)
906                 goto end;
907         data &= ~RX_CFG_RESET;  /* Clear the RX MAC reset. */
908         data |= RX_CFG_EN;      /* Enable the receiver. */
909         status = ql_write_xgmac_reg(qdev, RX_CFG, data);
910         if (status)
911                 goto end;
912
913         /* Turn on jumbo. */
914         status =
915             ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
916         if (status)
917                 goto end;
918         status =
919             ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
920         if (status)
921                 goto end;
922
923         /* Signal to the world that the port is enabled.        */
924         ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
925 end:
926         ql_sem_unlock(qdev, qdev->xg_sem_mask);
927         return status;
928 }
929
930 /* Get the next large buffer. */
931 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
932 {
933         struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
934         rx_ring->lbq_curr_idx++;
935         if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
936                 rx_ring->lbq_curr_idx = 0;
937         rx_ring->lbq_free_cnt++;
938         return lbq_desc;
939 }
940
941 /* Get the next small buffer. */
942 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
943 {
944         struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
945         rx_ring->sbq_curr_idx++;
946         if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
947                 rx_ring->sbq_curr_idx = 0;
948         rx_ring->sbq_free_cnt++;
949         return sbq_desc;
950 }
951
952 /* Update an rx ring index. */
953 static void ql_update_cq(struct rx_ring *rx_ring)
954 {
955         rx_ring->cnsmr_idx++;
956         rx_ring->curr_entry++;
957         if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
958                 rx_ring->cnsmr_idx = 0;
959                 rx_ring->curr_entry = rx_ring->cq_base;
960         }
961 }
962
963 static void ql_write_cq_idx(struct rx_ring *rx_ring)
964 {
965         ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
966 }
967
968 /* Process (refill) a large buffer queue. */
969 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
970 {
971         u32 clean_idx = rx_ring->lbq_clean_idx;
972         u32 start_idx = clean_idx;
973         struct bq_desc *lbq_desc;
974         u64 map;
975         int i;
976
977         while (rx_ring->lbq_free_cnt > 16) {
978                 for (i = 0; i < 16; i++) {
979                         QPRINTK(qdev, RX_STATUS, DEBUG,
980                                 "lbq: try cleaning clean_idx = %d.\n",
981                                 clean_idx);
982                         lbq_desc = &rx_ring->lbq[clean_idx];
983                         if (lbq_desc->p.lbq_page == NULL) {
984                                 QPRINTK(qdev, RX_STATUS, DEBUG,
985                                         "lbq: getting new page for index %d.\n",
986                                         lbq_desc->index);
987                                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
988                                 if (lbq_desc->p.lbq_page == NULL) {
989                                         rx_ring->lbq_clean_idx = clean_idx;
990                                         QPRINTK(qdev, RX_STATUS, ERR,
991                                                 "Couldn't get a page.\n");
992                                         return;
993                                 }
994                                 map = pci_map_page(qdev->pdev,
995                                                    lbq_desc->p.lbq_page,
996                                                    0, PAGE_SIZE,
997                                                    PCI_DMA_FROMDEVICE);
998                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
999                                         rx_ring->lbq_clean_idx = clean_idx;
1000                                         put_page(lbq_desc->p.lbq_page);
1001                                         lbq_desc->p.lbq_page = NULL;
1002                                         QPRINTK(qdev, RX_STATUS, ERR,
1003                                                 "PCI mapping failed.\n");
1004                                         return;
1005                                 }
1006                                 pci_unmap_addr_set(lbq_desc, mapaddr, map);
1007                                 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
1008                                 *lbq_desc->addr = cpu_to_le64(map);
1009                         }
1010                         clean_idx++;
1011                         if (clean_idx == rx_ring->lbq_len)
1012                                 clean_idx = 0;
1013                 }
1014
1015                 rx_ring->lbq_clean_idx = clean_idx;
1016                 rx_ring->lbq_prod_idx += 16;
1017                 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
1018                         rx_ring->lbq_prod_idx = 0;
1019                 rx_ring->lbq_free_cnt -= 16;
1020         }
1021
1022         if (start_idx != clean_idx) {
1023                 QPRINTK(qdev, RX_STATUS, DEBUG,
1024                         "lbq: updating prod idx = %d.\n",
1025                         rx_ring->lbq_prod_idx);
1026                 ql_write_db_reg(rx_ring->lbq_prod_idx,
1027                                 rx_ring->lbq_prod_idx_db_reg);
1028         }
1029 }
1030
1031 /* Process (refill) a small buffer queue. */
1032 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1033 {
1034         u32 clean_idx = rx_ring->sbq_clean_idx;
1035         u32 start_idx = clean_idx;
1036         struct bq_desc *sbq_desc;
1037         u64 map;
1038         int i;
1039
1040         while (rx_ring->sbq_free_cnt > 16) {
1041                 for (i = 0; i < 16; i++) {
1042                         sbq_desc = &rx_ring->sbq[clean_idx];
1043                         QPRINTK(qdev, RX_STATUS, DEBUG,
1044                                 "sbq: try cleaning clean_idx = %d.\n",
1045                                 clean_idx);
1046                         if (sbq_desc->p.skb == NULL) {
1047                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1048                                         "sbq: getting new skb for index %d.\n",
1049                                         sbq_desc->index);
1050                                 sbq_desc->p.skb =
1051                                     netdev_alloc_skb(qdev->ndev,
1052                                                      rx_ring->sbq_buf_size);
1053                                 if (sbq_desc->p.skb == NULL) {
1054                                         QPRINTK(qdev, PROBE, ERR,
1055                                                 "Couldn't get an skb.\n");
1056                                         rx_ring->sbq_clean_idx = clean_idx;
1057                                         return;
1058                                 }
1059                                 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
1060                                 map = pci_map_single(qdev->pdev,
1061                                                      sbq_desc->p.skb->data,
1062                                                      rx_ring->sbq_buf_size /
1063                                                      2, PCI_DMA_FROMDEVICE);
1064                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
1065                                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
1066                                         rx_ring->sbq_clean_idx = clean_idx;
1067                                         dev_kfree_skb_any(sbq_desc->p.skb);
1068                                         sbq_desc->p.skb = NULL;
1069                                         return;
1070                                 }
1071                                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
1072                                 pci_unmap_len_set(sbq_desc, maplen,
1073                                                   rx_ring->sbq_buf_size / 2);
1074                                 *sbq_desc->addr = cpu_to_le64(map);
1075                         }
1076
1077                         clean_idx++;
1078                         if (clean_idx == rx_ring->sbq_len)
1079                                 clean_idx = 0;
1080                 }
1081                 rx_ring->sbq_clean_idx = clean_idx;
1082                 rx_ring->sbq_prod_idx += 16;
1083                 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
1084                         rx_ring->sbq_prod_idx = 0;
1085                 rx_ring->sbq_free_cnt -= 16;
1086         }
1087
1088         if (start_idx != clean_idx) {
1089                 QPRINTK(qdev, RX_STATUS, DEBUG,
1090                         "sbq: updating prod idx = %d.\n",
1091                         rx_ring->sbq_prod_idx);
1092                 ql_write_db_reg(rx_ring->sbq_prod_idx,
1093                                 rx_ring->sbq_prod_idx_db_reg);
1094         }
1095 }
1096
1097 static void ql_update_buffer_queues(struct ql_adapter *qdev,
1098                                     struct rx_ring *rx_ring)
1099 {
1100         ql_update_sbq(qdev, rx_ring);
1101         ql_update_lbq(qdev, rx_ring);
1102 }
1103
1104 /* Unmaps tx buffers.  Can be called from send() if a pci mapping
1105  * fails at some stage, or from the interrupt when a tx completes.
1106  */
1107 static void ql_unmap_send(struct ql_adapter *qdev,
1108                           struct tx_ring_desc *tx_ring_desc, int mapped)
1109 {
1110         int i;
1111         for (i = 0; i < mapped; i++) {
1112                 if (i == 0 || (i == 7 && mapped > 7)) {
1113                         /*
1114                          * Unmap the skb->data area, or the
1115                          * external sglist (AKA the Outbound
1116                          * Address List (OAL)).
1117                          * If its the zeroeth element, then it's
1118                          * the skb->data area.  If it's the 7th
1119                          * element and there is more than 6 frags,
1120                          * then its an OAL.
1121                          */
1122                         if (i == 7) {
1123                                 QPRINTK(qdev, TX_DONE, DEBUG,
1124                                         "unmapping OAL area.\n");
1125                         }
1126                         pci_unmap_single(qdev->pdev,
1127                                          pci_unmap_addr(&tx_ring_desc->map[i],
1128                                                         mapaddr),
1129                                          pci_unmap_len(&tx_ring_desc->map[i],
1130                                                        maplen),
1131                                          PCI_DMA_TODEVICE);
1132                 } else {
1133                         QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1134                                 i);
1135                         pci_unmap_page(qdev->pdev,
1136                                        pci_unmap_addr(&tx_ring_desc->map[i],
1137                                                       mapaddr),
1138                                        pci_unmap_len(&tx_ring_desc->map[i],
1139                                                      maplen), PCI_DMA_TODEVICE);
1140                 }
1141         }
1142
1143 }
1144
1145 /* Map the buffers for this transmit.  This will return
1146  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1147  */
1148 static int ql_map_send(struct ql_adapter *qdev,
1149                        struct ob_mac_iocb_req *mac_iocb_ptr,
1150                        struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1151 {
1152         int len = skb_headlen(skb);
1153         dma_addr_t map;
1154         int frag_idx, err, map_idx = 0;
1155         struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1156         int frag_cnt = skb_shinfo(skb)->nr_frags;
1157
1158         if (frag_cnt) {
1159                 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1160         }
1161         /*
1162          * Map the skb buffer first.
1163          */
1164         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1165
1166         err = pci_dma_mapping_error(qdev->pdev, map);
1167         if (err) {
1168                 QPRINTK(qdev, TX_QUEUED, ERR,
1169                         "PCI mapping failed with error: %d\n", err);
1170
1171                 return NETDEV_TX_BUSY;
1172         }
1173
1174         tbd->len = cpu_to_le32(len);
1175         tbd->addr = cpu_to_le64(map);
1176         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1177         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1178         map_idx++;
1179
1180         /*
1181          * This loop fills the remainder of the 8 address descriptors
1182          * in the IOCB.  If there are more than 7 fragments, then the
1183          * eighth address desc will point to an external list (OAL).
1184          * When this happens, the remainder of the frags will be stored
1185          * in this list.
1186          */
1187         for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1188                 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1189                 tbd++;
1190                 if (frag_idx == 6 && frag_cnt > 7) {
1191                         /* Let's tack on an sglist.
1192                          * Our control block will now
1193                          * look like this:
1194                          * iocb->seg[0] = skb->data
1195                          * iocb->seg[1] = frag[0]
1196                          * iocb->seg[2] = frag[1]
1197                          * iocb->seg[3] = frag[2]
1198                          * iocb->seg[4] = frag[3]
1199                          * iocb->seg[5] = frag[4]
1200                          * iocb->seg[6] = frag[5]
1201                          * iocb->seg[7] = ptr to OAL (external sglist)
1202                          * oal->seg[0] = frag[6]
1203                          * oal->seg[1] = frag[7]
1204                          * oal->seg[2] = frag[8]
1205                          * oal->seg[3] = frag[9]
1206                          * oal->seg[4] = frag[10]
1207                          *      etc...
1208                          */
1209                         /* Tack on the OAL in the eighth segment of IOCB. */
1210                         map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1211                                              sizeof(struct oal),
1212                                              PCI_DMA_TODEVICE);
1213                         err = pci_dma_mapping_error(qdev->pdev, map);
1214                         if (err) {
1215                                 QPRINTK(qdev, TX_QUEUED, ERR,
1216                                         "PCI mapping outbound address list with error: %d\n",
1217                                         err);
1218                                 goto map_error;
1219                         }
1220
1221                         tbd->addr = cpu_to_le64(map);
1222                         /*
1223                          * The length is the number of fragments
1224                          * that remain to be mapped times the length
1225                          * of our sglist (OAL).
1226                          */
1227                         tbd->len =
1228                             cpu_to_le32((sizeof(struct tx_buf_desc) *
1229                                          (frag_cnt - frag_idx)) | TX_DESC_C);
1230                         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1231                                            map);
1232                         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1233                                           sizeof(struct oal));
1234                         tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1235                         map_idx++;
1236                 }
1237
1238                 map =
1239                     pci_map_page(qdev->pdev, frag->page,
1240                                  frag->page_offset, frag->size,
1241                                  PCI_DMA_TODEVICE);
1242
1243                 err = pci_dma_mapping_error(qdev->pdev, map);
1244                 if (err) {
1245                         QPRINTK(qdev, TX_QUEUED, ERR,
1246                                 "PCI mapping frags failed with error: %d.\n",
1247                                 err);
1248                         goto map_error;
1249                 }
1250
1251                 tbd->addr = cpu_to_le64(map);
1252                 tbd->len = cpu_to_le32(frag->size);
1253                 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1254                 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1255                                   frag->size);
1256
1257         }
1258         /* Save the number of segments we've mapped. */
1259         tx_ring_desc->map_cnt = map_idx;
1260         /* Terminate the last segment. */
1261         tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1262         return NETDEV_TX_OK;
1263
1264 map_error:
1265         /*
1266          * If the first frag mapping failed, then i will be zero.
1267          * This causes the unmap of the skb->data area.  Otherwise
1268          * we pass in the number of frags that mapped successfully
1269          * so they can be umapped.
1270          */
1271         ql_unmap_send(qdev, tx_ring_desc, map_idx);
1272         return NETDEV_TX_BUSY;
1273 }
1274
1275 static void ql_realign_skb(struct sk_buff *skb, int len)
1276 {
1277         void *temp_addr = skb->data;
1278
1279         /* Undo the skb_reserve(skb,32) we did before
1280          * giving to hardware, and realign data on
1281          * a 2-byte boundary.
1282          */
1283         skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1284         skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1285         skb_copy_to_linear_data(skb, temp_addr,
1286                 (unsigned int)len);
1287 }
1288
1289 /*
1290  * This function builds an skb for the given inbound
1291  * completion.  It will be rewritten for readability in the near
1292  * future, but for not it works well.
1293  */
1294 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1295                                        struct rx_ring *rx_ring,
1296                                        struct ib_mac_iocb_rsp *ib_mac_rsp)
1297 {
1298         struct bq_desc *lbq_desc;
1299         struct bq_desc *sbq_desc;
1300         struct sk_buff *skb = NULL;
1301         u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1302        u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1303
1304         /*
1305          * Handle the header buffer if present.
1306          */
1307         if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1308             ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1309                 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1310                 /*
1311                  * Headers fit nicely into a small buffer.
1312                  */
1313                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1314                 pci_unmap_single(qdev->pdev,
1315                                 pci_unmap_addr(sbq_desc, mapaddr),
1316                                 pci_unmap_len(sbq_desc, maplen),
1317                                 PCI_DMA_FROMDEVICE);
1318                 skb = sbq_desc->p.skb;
1319                 ql_realign_skb(skb, hdr_len);
1320                 skb_put(skb, hdr_len);
1321                 sbq_desc->p.skb = NULL;
1322         }
1323
1324         /*
1325          * Handle the data buffer(s).
1326          */
1327         if (unlikely(!length)) {        /* Is there data too? */
1328                 QPRINTK(qdev, RX_STATUS, DEBUG,
1329                         "No Data buffer in this packet.\n");
1330                 return skb;
1331         }
1332
1333         if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1334                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1335                         QPRINTK(qdev, RX_STATUS, DEBUG,
1336                                 "Headers in small, data of %d bytes in small, combine them.\n", length);
1337                         /*
1338                          * Data is less than small buffer size so it's
1339                          * stuffed in a small buffer.
1340                          * For this case we append the data
1341                          * from the "data" small buffer to the "header" small
1342                          * buffer.
1343                          */
1344                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1345                         pci_dma_sync_single_for_cpu(qdev->pdev,
1346                                                     pci_unmap_addr
1347                                                     (sbq_desc, mapaddr),
1348                                                     pci_unmap_len
1349                                                     (sbq_desc, maplen),
1350                                                     PCI_DMA_FROMDEVICE);
1351                         memcpy(skb_put(skb, length),
1352                                sbq_desc->p.skb->data, length);
1353                         pci_dma_sync_single_for_device(qdev->pdev,
1354                                                        pci_unmap_addr
1355                                                        (sbq_desc,
1356                                                         mapaddr),
1357                                                        pci_unmap_len
1358                                                        (sbq_desc,
1359                                                         maplen),
1360                                                        PCI_DMA_FROMDEVICE);
1361                 } else {
1362                         QPRINTK(qdev, RX_STATUS, DEBUG,
1363                                 "%d bytes in a single small buffer.\n", length);
1364                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1365                         skb = sbq_desc->p.skb;
1366                         ql_realign_skb(skb, length);
1367                         skb_put(skb, length);
1368                         pci_unmap_single(qdev->pdev,
1369                                          pci_unmap_addr(sbq_desc,
1370                                                         mapaddr),
1371                                          pci_unmap_len(sbq_desc,
1372                                                        maplen),
1373                                          PCI_DMA_FROMDEVICE);
1374                         sbq_desc->p.skb = NULL;
1375                 }
1376         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1377                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1378                         QPRINTK(qdev, RX_STATUS, DEBUG,
1379                                 "Header in small, %d bytes in large. Chain large to small!\n", length);
1380                         /*
1381                          * The data is in a single large buffer.  We
1382                          * chain it to the header buffer's skb and let
1383                          * it rip.
1384                          */
1385                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1386                         pci_unmap_page(qdev->pdev,
1387                                        pci_unmap_addr(lbq_desc,
1388                                                       mapaddr),
1389                                        pci_unmap_len(lbq_desc, maplen),
1390                                        PCI_DMA_FROMDEVICE);
1391                         QPRINTK(qdev, RX_STATUS, DEBUG,
1392                                 "Chaining page to skb.\n");
1393                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1394                                            0, length);
1395                         skb->len += length;
1396                         skb->data_len += length;
1397                         skb->truesize += length;
1398                         lbq_desc->p.lbq_page = NULL;
1399                 } else {
1400                         /*
1401                          * The headers and data are in a single large buffer. We
1402                          * copy it to a new skb and let it go. This can happen with
1403                          * jumbo mtu on a non-TCP/UDP frame.
1404                          */
1405                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1406                         skb = netdev_alloc_skb(qdev->ndev, length);
1407                         if (skb == NULL) {
1408                                 QPRINTK(qdev, PROBE, DEBUG,
1409                                         "No skb available, drop the packet.\n");
1410                                 return NULL;
1411                         }
1412                         pci_unmap_page(qdev->pdev,
1413                                        pci_unmap_addr(lbq_desc,
1414                                                       mapaddr),
1415                                        pci_unmap_len(lbq_desc, maplen),
1416                                        PCI_DMA_FROMDEVICE);
1417                         skb_reserve(skb, NET_IP_ALIGN);
1418                         QPRINTK(qdev, RX_STATUS, DEBUG,
1419                                 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1420                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1421                                            0, length);
1422                         skb->len += length;
1423                         skb->data_len += length;
1424                         skb->truesize += length;
1425                         length -= length;
1426                         lbq_desc->p.lbq_page = NULL;
1427                         __pskb_pull_tail(skb,
1428                                 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1429                                 VLAN_ETH_HLEN : ETH_HLEN);
1430                 }
1431         } else {
1432                 /*
1433                  * The data is in a chain of large buffers
1434                  * pointed to by a small buffer.  We loop
1435                  * thru and chain them to the our small header
1436                  * buffer's skb.
1437                  * frags:  There are 18 max frags and our small
1438                  *         buffer will hold 32 of them. The thing is,
1439                  *         we'll use 3 max for our 9000 byte jumbo
1440                  *         frames.  If the MTU goes up we could
1441                  *          eventually be in trouble.
1442                  */
1443                 int size, offset, i = 0;
1444                 __le64 *bq, bq_array[8];
1445                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1446                 pci_unmap_single(qdev->pdev,
1447                                  pci_unmap_addr(sbq_desc, mapaddr),
1448                                  pci_unmap_len(sbq_desc, maplen),
1449                                  PCI_DMA_FROMDEVICE);
1450                 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1451                         /*
1452                          * This is an non TCP/UDP IP frame, so
1453                          * the headers aren't split into a small
1454                          * buffer.  We have to use the small buffer
1455                          * that contains our sg list as our skb to
1456                          * send upstairs. Copy the sg list here to
1457                          * a local buffer and use it to find the
1458                          * pages to chain.
1459                          */
1460                         QPRINTK(qdev, RX_STATUS, DEBUG,
1461                                 "%d bytes of headers & data in chain of large.\n", length);
1462                         skb = sbq_desc->p.skb;
1463                         bq = &bq_array[0];
1464                         memcpy(bq, skb->data, sizeof(bq_array));
1465                         sbq_desc->p.skb = NULL;
1466                         skb_reserve(skb, NET_IP_ALIGN);
1467                 } else {
1468                         QPRINTK(qdev, RX_STATUS, DEBUG,
1469                                 "Headers in small, %d bytes of data in chain of large.\n", length);
1470                         bq = (__le64 *)sbq_desc->p.skb->data;
1471                 }
1472                 while (length > 0) {
1473                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1474                         pci_unmap_page(qdev->pdev,
1475                                        pci_unmap_addr(lbq_desc,
1476                                                       mapaddr),
1477                                        pci_unmap_len(lbq_desc,
1478                                                      maplen),
1479                                        PCI_DMA_FROMDEVICE);
1480                         size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1481                         offset = 0;
1482
1483                         QPRINTK(qdev, RX_STATUS, DEBUG,
1484                                 "Adding page %d to skb for %d bytes.\n",
1485                                 i, size);
1486                         skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1487                                            offset, size);
1488                         skb->len += size;
1489                         skb->data_len += size;
1490                         skb->truesize += size;
1491                         length -= size;
1492                         lbq_desc->p.lbq_page = NULL;
1493                         bq++;
1494                         i++;
1495                 }
1496                 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1497                                 VLAN_ETH_HLEN : ETH_HLEN);
1498         }
1499         return skb;
1500 }
1501
1502 /* Process an inbound completion from an rx ring. */
1503 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1504                                    struct rx_ring *rx_ring,
1505                                    struct ib_mac_iocb_rsp *ib_mac_rsp)
1506 {
1507         struct net_device *ndev = qdev->ndev;
1508         struct sk_buff *skb = NULL;
1509         u16 vlan_id = (le16_to_cpu(ib_mac_rsp->vlan_id) &
1510                         IB_MAC_IOCB_RSP_VLAN_MASK)
1511
1512         QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1513
1514         skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1515         if (unlikely(!skb)) {
1516                 QPRINTK(qdev, RX_STATUS, DEBUG,
1517                         "No skb available, drop packet.\n");
1518                 return;
1519         }
1520
1521         prefetch(skb->data);
1522         skb->dev = ndev;
1523         if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1524                 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1525                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1526                         IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1527                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1528                         IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1529                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1530                         IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1531         }
1532         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1533                 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1534         }
1535
1536         skb->protocol = eth_type_trans(skb, ndev);
1537         skb->ip_summed = CHECKSUM_NONE;
1538
1539         /* If rx checksum is on, and there are no
1540          * csum or frame errors.
1541          */
1542         if (qdev->rx_csum &&
1543                 !(ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) &&
1544                 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1545                 /* TCP frame. */
1546                 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1547                         QPRINTK(qdev, RX_STATUS, DEBUG,
1548                                         "TCP checksum done!\n");
1549                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1550                 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1551                                 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1552                 /* Unfragmented ipv4 UDP frame. */
1553                         struct iphdr *iph = (struct iphdr *) skb->data;
1554                         if (!(iph->frag_off &
1555                                 cpu_to_be16(IP_MF|IP_OFFSET))) {
1556                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1557                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1558                                                 "TCP checksum done!\n");
1559                         }
1560                 }
1561         }
1562
1563         qdev->stats.rx_packets++;
1564         qdev->stats.rx_bytes += skb->len;
1565         skb_record_rx_queue(skb,
1566                 rx_ring->cq_id - qdev->rss_ring_first_cq_id);
1567         if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
1568                 if (qdev->vlgrp &&
1569                         (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
1570                         (vlan_id != 0))
1571                         vlan_gro_receive(&rx_ring->napi, qdev->vlgrp,
1572                                 vlan_id, skb);
1573                 else
1574                         napi_gro_receive(&rx_ring->napi, skb);
1575         } else {
1576                 if (qdev->vlgrp &&
1577                         (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
1578                         (vlan_id != 0))
1579                         vlan_hwaccel_receive_skb(skb, qdev->vlgrp, vlan_id);
1580                 else
1581                         netif_receive_skb(skb);
1582         }
1583 }
1584
1585 /* Process an outbound completion from an rx ring. */
1586 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1587                                    struct ob_mac_iocb_rsp *mac_rsp)
1588 {
1589         struct tx_ring *tx_ring;
1590         struct tx_ring_desc *tx_ring_desc;
1591
1592         QL_DUMP_OB_MAC_RSP(mac_rsp);
1593         tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1594         tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1595         ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1596         qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1597         qdev->stats.tx_packets++;
1598         dev_kfree_skb(tx_ring_desc->skb);
1599         tx_ring_desc->skb = NULL;
1600
1601         if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1602                                         OB_MAC_IOCB_RSP_S |
1603                                         OB_MAC_IOCB_RSP_L |
1604                                         OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1605                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1606                         QPRINTK(qdev, TX_DONE, WARNING,
1607                                 "Total descriptor length did not match transfer length.\n");
1608                 }
1609                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1610                         QPRINTK(qdev, TX_DONE, WARNING,
1611                                 "Frame too short to be legal, not sent.\n");
1612                 }
1613                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1614                         QPRINTK(qdev, TX_DONE, WARNING,
1615                                 "Frame too long, but sent anyway.\n");
1616                 }
1617                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1618                         QPRINTK(qdev, TX_DONE, WARNING,
1619                                 "PCI backplane error. Frame not sent.\n");
1620                 }
1621         }
1622         atomic_inc(&tx_ring->tx_count);
1623 }
1624
1625 /* Fire up a handler to reset the MPI processor. */
1626 void ql_queue_fw_error(struct ql_adapter *qdev)
1627 {
1628         netif_carrier_off(qdev->ndev);
1629         queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1630 }
1631
1632 void ql_queue_asic_error(struct ql_adapter *qdev)
1633 {
1634         netif_carrier_off(qdev->ndev);
1635         ql_disable_interrupts(qdev);
1636         /* Clear adapter up bit to signal the recovery
1637          * process that it shouldn't kill the reset worker
1638          * thread
1639          */
1640         clear_bit(QL_ADAPTER_UP, &qdev->flags);
1641         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1642 }
1643
1644 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1645                                     struct ib_ae_iocb_rsp *ib_ae_rsp)
1646 {
1647         switch (ib_ae_rsp->event) {
1648         case MGMT_ERR_EVENT:
1649                 QPRINTK(qdev, RX_ERR, ERR,
1650                         "Management Processor Fatal Error.\n");
1651                 ql_queue_fw_error(qdev);
1652                 return;
1653
1654         case CAM_LOOKUP_ERR_EVENT:
1655                 QPRINTK(qdev, LINK, ERR,
1656                         "Multiple CAM hits lookup occurred.\n");
1657                 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1658                 ql_queue_asic_error(qdev);
1659                 return;
1660
1661         case SOFT_ECC_ERROR_EVENT:
1662                 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1663                 ql_queue_asic_error(qdev);
1664                 break;
1665
1666         case PCI_ERR_ANON_BUF_RD:
1667                 QPRINTK(qdev, RX_ERR, ERR,
1668                         "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1669                         ib_ae_rsp->q_id);
1670                 ql_queue_asic_error(qdev);
1671                 break;
1672
1673         default:
1674                 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1675                         ib_ae_rsp->event);
1676                 ql_queue_asic_error(qdev);
1677                 break;
1678         }
1679 }
1680
1681 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1682 {
1683         struct ql_adapter *qdev = rx_ring->qdev;
1684         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1685         struct ob_mac_iocb_rsp *net_rsp = NULL;
1686         int count = 0;
1687
1688         struct tx_ring *tx_ring;
1689         /* While there are entries in the completion queue. */
1690         while (prod != rx_ring->cnsmr_idx) {
1691
1692                 QPRINTK(qdev, RX_STATUS, DEBUG,
1693                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1694                         prod, rx_ring->cnsmr_idx);
1695
1696                 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1697                 rmb();
1698                 switch (net_rsp->opcode) {
1699
1700                 case OPCODE_OB_MAC_TSO_IOCB:
1701                 case OPCODE_OB_MAC_IOCB:
1702                         ql_process_mac_tx_intr(qdev, net_rsp);
1703                         break;
1704                 default:
1705                         QPRINTK(qdev, RX_STATUS, DEBUG,
1706                                 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1707                                 net_rsp->opcode);
1708                 }
1709                 count++;
1710                 ql_update_cq(rx_ring);
1711                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1712         }
1713         ql_write_cq_idx(rx_ring);
1714         tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1715         if (__netif_subqueue_stopped(qdev->ndev, tx_ring->wq_id) &&
1716                                         net_rsp != NULL) {
1717                 if (atomic_read(&tx_ring->queue_stopped) &&
1718                     (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1719                         /*
1720                          * The queue got stopped because the tx_ring was full.
1721                          * Wake it up, because it's now at least 25% empty.
1722                          */
1723                         netif_wake_subqueue(qdev->ndev, tx_ring->wq_id);
1724         }
1725
1726         return count;
1727 }
1728
1729 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1730 {
1731         struct ql_adapter *qdev = rx_ring->qdev;
1732         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1733         struct ql_net_rsp_iocb *net_rsp;
1734         int count = 0;
1735
1736         /* While there are entries in the completion queue. */
1737         while (prod != rx_ring->cnsmr_idx) {
1738
1739                 QPRINTK(qdev, RX_STATUS, DEBUG,
1740                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1741                         prod, rx_ring->cnsmr_idx);
1742
1743                 net_rsp = rx_ring->curr_entry;
1744                 rmb();
1745                 switch (net_rsp->opcode) {
1746                 case OPCODE_IB_MAC_IOCB:
1747                         ql_process_mac_rx_intr(qdev, rx_ring,
1748                                                (struct ib_mac_iocb_rsp *)
1749                                                net_rsp);
1750                         break;
1751
1752                 case OPCODE_IB_AE_IOCB:
1753                         ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1754                                                 net_rsp);
1755                         break;
1756                 default:
1757                         {
1758                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1759                                         "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1760                                         net_rsp->opcode);
1761                         }
1762                 }
1763                 count++;
1764                 ql_update_cq(rx_ring);
1765                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1766                 if (count == budget)
1767                         break;
1768         }
1769         ql_update_buffer_queues(qdev, rx_ring);
1770         ql_write_cq_idx(rx_ring);
1771         return count;
1772 }
1773
1774 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1775 {
1776         struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1777         struct ql_adapter *qdev = rx_ring->qdev;
1778         int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1779
1780         QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1781                 rx_ring->cq_id);
1782
1783         if (work_done < budget) {
1784                 napi_complete(napi);
1785                 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1786         }
1787         return work_done;
1788 }
1789
1790 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1791 {
1792         struct ql_adapter *qdev = netdev_priv(ndev);
1793
1794         qdev->vlgrp = grp;
1795         if (grp) {
1796                 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1797                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1798                            NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1799         } else {
1800                 QPRINTK(qdev, IFUP, DEBUG,
1801                         "Turning off VLAN in NIC_RCV_CFG.\n");
1802                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1803         }
1804 }
1805
1806 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1807 {
1808         struct ql_adapter *qdev = netdev_priv(ndev);
1809         u32 enable_bit = MAC_ADDR_E;
1810         int status;
1811
1812         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1813         if (status)
1814                 return;
1815         spin_lock(&qdev->hw_lock);
1816         if (ql_set_mac_addr_reg
1817             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1818                 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1819         }
1820         spin_unlock(&qdev->hw_lock);
1821         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1822 }
1823
1824 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1825 {
1826         struct ql_adapter *qdev = netdev_priv(ndev);
1827         u32 enable_bit = 0;
1828         int status;
1829
1830         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1831         if (status)
1832                 return;
1833
1834         spin_lock(&qdev->hw_lock);
1835         if (ql_set_mac_addr_reg
1836             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1837                 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1838         }
1839         spin_unlock(&qdev->hw_lock);
1840         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1841
1842 }
1843
1844 /* Worker thread to process a given rx_ring that is dedicated
1845  * to outbound completions.
1846  */
1847 static void ql_tx_clean(struct work_struct *work)
1848 {
1849         struct rx_ring *rx_ring =
1850             container_of(work, struct rx_ring, rx_work.work);
1851         ql_clean_outbound_rx_ring(rx_ring);
1852         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1853
1854 }
1855
1856 /* Worker thread to process a given rx_ring that is dedicated
1857  * to inbound completions.
1858  */
1859 static void ql_rx_clean(struct work_struct *work)
1860 {
1861         struct rx_ring *rx_ring =
1862             container_of(work, struct rx_ring, rx_work.work);
1863         ql_clean_inbound_rx_ring(rx_ring, 64);
1864         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1865 }
1866
1867 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1868 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1869 {
1870         struct rx_ring *rx_ring = dev_id;
1871         queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1872                               &rx_ring->rx_work, 0);
1873         return IRQ_HANDLED;
1874 }
1875
1876 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1877 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1878 {
1879         struct rx_ring *rx_ring = dev_id;
1880         napi_schedule(&rx_ring->napi);
1881         return IRQ_HANDLED;
1882 }
1883
1884 /* This handles a fatal error, MPI activity, and the default
1885  * rx_ring in an MSI-X multiple vector environment.
1886  * In MSI/Legacy environment it also process the rest of
1887  * the rx_rings.
1888  */
1889 static irqreturn_t qlge_isr(int irq, void *dev_id)
1890 {
1891         struct rx_ring *rx_ring = dev_id;
1892         struct ql_adapter *qdev = rx_ring->qdev;
1893         struct intr_context *intr_context = &qdev->intr_context[0];
1894         u32 var;
1895         int i;
1896         int work_done = 0;
1897
1898         spin_lock(&qdev->hw_lock);
1899         if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1900                 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1901                 spin_unlock(&qdev->hw_lock);
1902                 return IRQ_NONE;
1903         }
1904         spin_unlock(&qdev->hw_lock);
1905
1906         var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1907
1908         /*
1909          * Check for fatal error.
1910          */
1911         if (var & STS_FE) {
1912                 ql_queue_asic_error(qdev);
1913                 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1914                 var = ql_read32(qdev, ERR_STS);
1915                 QPRINTK(qdev, INTR, ERR,
1916                         "Resetting chip. Error Status Register = 0x%x\n", var);
1917                 return IRQ_HANDLED;
1918         }
1919
1920         /*
1921          * Check MPI processor activity.
1922          */
1923         if (var & STS_PI) {
1924                 /*
1925                  * We've got an async event or mailbox completion.
1926                  * Handle it and clear the source of the interrupt.
1927                  */
1928                 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1929                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1930                 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1931                                       &qdev->mpi_work, 0);
1932                 work_done++;
1933         }
1934
1935         /*
1936          * Check the default queue and wake handler if active.
1937          */
1938         rx_ring = &qdev->rx_ring[0];
1939         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1940                 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1941                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1942                 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1943                                       &rx_ring->rx_work, 0);
1944                 work_done++;
1945         }
1946
1947         if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1948                 /*
1949                  * Start the DPC for each active queue.
1950                  */
1951                 for (i = 1; i < qdev->rx_ring_count; i++) {
1952                         rx_ring = &qdev->rx_ring[i];
1953                         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1954                             rx_ring->cnsmr_idx) {
1955                                 QPRINTK(qdev, INTR, INFO,
1956                                         "Waking handler for rx_ring[%d].\n", i);
1957                                 ql_disable_completion_interrupt(qdev,
1958                                                                 intr_context->
1959                                                                 intr);
1960                                 if (i < qdev->rss_ring_first_cq_id)
1961                                         queue_delayed_work_on(rx_ring->cpu,
1962                                                               qdev->q_workqueue,
1963                                                               &rx_ring->rx_work,
1964                                                               0);
1965                                 else
1966                                         napi_schedule(&rx_ring->napi);
1967                                 work_done++;
1968                         }
1969                 }
1970         }
1971         ql_enable_completion_interrupt(qdev, intr_context->intr);
1972         return work_done ? IRQ_HANDLED : IRQ_NONE;
1973 }
1974
1975 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1976 {
1977
1978         if (skb_is_gso(skb)) {
1979                 int err;
1980                 if (skb_header_cloned(skb)) {
1981                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1982                         if (err)
1983                                 return err;
1984                 }
1985
1986                 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1987                 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1988                 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1989                 mac_iocb_ptr->total_hdrs_len =
1990                     cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1991                 mac_iocb_ptr->net_trans_offset =
1992                     cpu_to_le16(skb_network_offset(skb) |
1993                                 skb_transport_offset(skb)
1994                                 << OB_MAC_TRANSPORT_HDR_SHIFT);
1995                 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1996                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1997                 if (likely(skb->protocol == htons(ETH_P_IP))) {
1998                         struct iphdr *iph = ip_hdr(skb);
1999                         iph->check = 0;
2000                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2001                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2002                                                                  iph->daddr, 0,
2003                                                                  IPPROTO_TCP,
2004                                                                  0);
2005                 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2006                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
2007                         tcp_hdr(skb)->check =
2008                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2009                                              &ipv6_hdr(skb)->daddr,
2010                                              0, IPPROTO_TCP, 0);
2011                 }
2012                 return 1;
2013         }
2014         return 0;
2015 }
2016
2017 static void ql_hw_csum_setup(struct sk_buff *skb,
2018                              struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2019 {
2020         int len;
2021         struct iphdr *iph = ip_hdr(skb);
2022         __sum16 *check;
2023         mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2024         mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2025         mac_iocb_ptr->net_trans_offset =
2026                 cpu_to_le16(skb_network_offset(skb) |
2027                 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
2028
2029         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2030         len = (ntohs(iph->tot_len) - (iph->ihl << 2));
2031         if (likely(iph->protocol == IPPROTO_TCP)) {
2032                 check = &(tcp_hdr(skb)->check);
2033                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
2034                 mac_iocb_ptr->total_hdrs_len =
2035                     cpu_to_le16(skb_transport_offset(skb) +
2036                                 (tcp_hdr(skb)->doff << 2));
2037         } else {
2038                 check = &(udp_hdr(skb)->check);
2039                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
2040                 mac_iocb_ptr->total_hdrs_len =
2041                     cpu_to_le16(skb_transport_offset(skb) +
2042                                 sizeof(struct udphdr));
2043         }
2044         *check = ~csum_tcpudp_magic(iph->saddr,
2045                                     iph->daddr, len, iph->protocol, 0);
2046 }
2047
2048 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
2049 {
2050         struct tx_ring_desc *tx_ring_desc;
2051         struct ob_mac_iocb_req *mac_iocb_ptr;
2052         struct ql_adapter *qdev = netdev_priv(ndev);
2053         int tso;
2054         struct tx_ring *tx_ring;
2055         u32 tx_ring_idx = (u32) skb->queue_mapping;
2056
2057         tx_ring = &qdev->tx_ring[tx_ring_idx];
2058
2059         if (skb_padto(skb, ETH_ZLEN))
2060                 return NETDEV_TX_OK;
2061
2062         if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
2063                 QPRINTK(qdev, TX_QUEUED, INFO,
2064                         "%s: shutting down tx queue %d du to lack of resources.\n",
2065                         __func__, tx_ring_idx);
2066                 netif_stop_subqueue(ndev, tx_ring->wq_id);
2067                 atomic_inc(&tx_ring->queue_stopped);
2068                 return NETDEV_TX_BUSY;
2069         }
2070         tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
2071         mac_iocb_ptr = tx_ring_desc->queue_entry;
2072         memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
2073
2074         mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
2075         mac_iocb_ptr->tid = tx_ring_desc->index;
2076         /* We use the upper 32-bits to store the tx queue for this IO.
2077          * When we get the completion we can use it to establish the context.
2078          */
2079         mac_iocb_ptr->txq_idx = tx_ring_idx;
2080         tx_ring_desc->skb = skb;
2081
2082         mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
2083
2084         if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
2085                 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
2086                         vlan_tx_tag_get(skb));
2087                 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
2088                 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
2089         }
2090         tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2091         if (tso < 0) {
2092                 dev_kfree_skb_any(skb);
2093                 return NETDEV_TX_OK;
2094         } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
2095                 ql_hw_csum_setup(skb,
2096                                  (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2097         }
2098         if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
2099                         NETDEV_TX_OK) {
2100                 QPRINTK(qdev, TX_QUEUED, ERR,
2101                                 "Could not map the segments.\n");
2102                 return NETDEV_TX_BUSY;
2103         }
2104         QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
2105         tx_ring->prod_idx++;
2106         if (tx_ring->prod_idx == tx_ring->wq_len)
2107                 tx_ring->prod_idx = 0;
2108         wmb();
2109
2110         ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
2111         ndev->trans_start = jiffies;
2112         QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
2113                 tx_ring->prod_idx, skb->len);
2114
2115         atomic_dec(&tx_ring->tx_count);
2116         return NETDEV_TX_OK;
2117 }
2118
2119 static void ql_free_shadow_space(struct ql_adapter *qdev)
2120 {
2121         if (qdev->rx_ring_shadow_reg_area) {
2122                 pci_free_consistent(qdev->pdev,
2123                                     PAGE_SIZE,
2124                                     qdev->rx_ring_shadow_reg_area,
2125                                     qdev->rx_ring_shadow_reg_dma);
2126                 qdev->rx_ring_shadow_reg_area = NULL;
2127         }
2128         if (qdev->tx_ring_shadow_reg_area) {
2129                 pci_free_consistent(qdev->pdev,
2130                                     PAGE_SIZE,
2131                                     qdev->tx_ring_shadow_reg_area,
2132                                     qdev->tx_ring_shadow_reg_dma);
2133                 qdev->tx_ring_shadow_reg_area = NULL;
2134         }
2135 }
2136
2137 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2138 {
2139         qdev->rx_ring_shadow_reg_area =
2140             pci_alloc_consistent(qdev->pdev,
2141                                  PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2142         if (qdev->rx_ring_shadow_reg_area == NULL) {
2143                 QPRINTK(qdev, IFUP, ERR,
2144                         "Allocation of RX shadow space failed.\n");
2145                 return -ENOMEM;
2146         }
2147         memset(qdev->rx_ring_shadow_reg_area, 0, PAGE_SIZE);
2148         qdev->tx_ring_shadow_reg_area =
2149             pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2150                                  &qdev->tx_ring_shadow_reg_dma);
2151         if (qdev->tx_ring_shadow_reg_area == NULL) {
2152                 QPRINTK(qdev, IFUP, ERR,
2153                         "Allocation of TX shadow space failed.\n");
2154                 goto err_wqp_sh_area;
2155         }
2156         memset(qdev->tx_ring_shadow_reg_area, 0, PAGE_SIZE);
2157         return 0;
2158
2159 err_wqp_sh_area:
2160         pci_free_consistent(qdev->pdev,
2161                             PAGE_SIZE,
2162                             qdev->rx_ring_shadow_reg_area,
2163                             qdev->rx_ring_shadow_reg_dma);
2164         return -ENOMEM;
2165 }
2166
2167 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2168 {
2169         struct tx_ring_desc *tx_ring_desc;
2170         int i;
2171         struct ob_mac_iocb_req *mac_iocb_ptr;
2172
2173         mac_iocb_ptr = tx_ring->wq_base;
2174         tx_ring_desc = tx_ring->q;
2175         for (i = 0; i < tx_ring->wq_len; i++) {
2176                 tx_ring_desc->index = i;
2177                 tx_ring_desc->skb = NULL;
2178                 tx_ring_desc->queue_entry = mac_iocb_ptr;
2179                 mac_iocb_ptr++;
2180                 tx_ring_desc++;
2181         }
2182         atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2183         atomic_set(&tx_ring->queue_stopped, 0);
2184 }
2185
2186 static void ql_free_tx_resources(struct ql_adapter *qdev,
2187                                  struct tx_ring *tx_ring)
2188 {
2189         if (tx_ring->wq_base) {
2190                 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2191                                     tx_ring->wq_base, tx_ring->wq_base_dma);
2192                 tx_ring->wq_base = NULL;
2193         }
2194         kfree(tx_ring->q);
2195         tx_ring->q = NULL;
2196 }
2197
2198 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2199                                  struct tx_ring *tx_ring)
2200 {
2201         tx_ring->wq_base =
2202             pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2203                                  &tx_ring->wq_base_dma);
2204
2205         if ((tx_ring->wq_base == NULL)
2206             || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2207                 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2208                 return -ENOMEM;
2209         }
2210         tx_ring->q =
2211             kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2212         if (tx_ring->q == NULL)
2213                 goto err;
2214
2215         return 0;
2216 err:
2217         pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2218                             tx_ring->wq_base, tx_ring->wq_base_dma);
2219         return -ENOMEM;
2220 }
2221
2222 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2223 {
2224         int i;
2225         struct bq_desc *lbq_desc;
2226
2227         for (i = 0; i < rx_ring->lbq_len; i++) {
2228                 lbq_desc = &rx_ring->lbq[i];
2229                 if (lbq_desc->p.lbq_page) {
2230                         pci_unmap_page(qdev->pdev,
2231                                        pci_unmap_addr(lbq_desc, mapaddr),
2232                                        pci_unmap_len(lbq_desc, maplen),
2233                                        PCI_DMA_FROMDEVICE);
2234
2235                         put_page(lbq_desc->p.lbq_page);
2236                         lbq_desc->p.lbq_page = NULL;
2237                 }
2238         }
2239 }
2240
2241 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2242 {
2243         int i;
2244         struct bq_desc *sbq_desc;
2245
2246         for (i = 0; i < rx_ring->sbq_len; i++) {
2247                 sbq_desc = &rx_ring->sbq[i];
2248                 if (sbq_desc == NULL) {
2249                         QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2250                         return;
2251                 }
2252                 if (sbq_desc->p.skb) {
2253                         pci_unmap_single(qdev->pdev,
2254                                          pci_unmap_addr(sbq_desc, mapaddr),
2255                                          pci_unmap_len(sbq_desc, maplen),
2256                                          PCI_DMA_FROMDEVICE);
2257                         dev_kfree_skb(sbq_desc->p.skb);
2258                         sbq_desc->p.skb = NULL;
2259                 }
2260         }
2261 }
2262
2263 /* Free all large and small rx buffers associated
2264  * with the completion queues for this device.
2265  */
2266 static void ql_free_rx_buffers(struct ql_adapter *qdev)
2267 {
2268         int i;
2269         struct rx_ring *rx_ring;
2270
2271         for (i = 0; i < qdev->rx_ring_count; i++) {
2272                 rx_ring = &qdev->rx_ring[i];
2273                 if (rx_ring->lbq)
2274                         ql_free_lbq_buffers(qdev, rx_ring);
2275                 if (rx_ring->sbq)
2276                         ql_free_sbq_buffers(qdev, rx_ring);
2277         }
2278 }
2279
2280 static void ql_alloc_rx_buffers(struct ql_adapter *qdev)
2281 {
2282         struct rx_ring *rx_ring;
2283         int i;
2284
2285         for (i = 0; i < qdev->rx_ring_count; i++) {
2286                 rx_ring = &qdev->rx_ring[i];
2287                 if (rx_ring->type != TX_Q)
2288                         ql_update_buffer_queues(qdev, rx_ring);
2289         }
2290 }
2291
2292 static void ql_init_lbq_ring(struct ql_adapter *qdev,
2293                                 struct rx_ring *rx_ring)
2294 {
2295         int i;
2296         struct bq_desc *lbq_desc;
2297         __le64 *bq = rx_ring->lbq_base;
2298
2299         memset(rx_ring->lbq, 0, rx_ring->lbq_len * sizeof(struct bq_desc));
2300         for (i = 0; i < rx_ring->lbq_len; i++) {
2301                 lbq_desc = &rx_ring->lbq[i];
2302                 memset(lbq_desc, 0, sizeof(*lbq_desc));
2303                 lbq_desc->index = i;
2304                 lbq_desc->addr = bq;
2305                 bq++;
2306         }
2307 }
2308
2309 static void ql_init_sbq_ring(struct ql_adapter *qdev,
2310                                 struct rx_ring *rx_ring)
2311 {
2312         int i;
2313         struct bq_desc *sbq_desc;
2314         __le64 *bq = rx_ring->sbq_base;
2315
2316         memset(rx_ring->sbq, 0, rx_ring->sbq_len * sizeof(struct bq_desc));
2317         for (i = 0; i < rx_ring->sbq_len; i++) {
2318                 sbq_desc = &rx_ring->sbq[i];
2319                 memset(sbq_desc, 0, sizeof(*sbq_desc));
2320                 sbq_desc->index = i;
2321                 sbq_desc->addr = bq;
2322                 bq++;
2323         }
2324 }
2325
2326 static void ql_free_rx_resources(struct ql_adapter *qdev,
2327                                  struct rx_ring *rx_ring)
2328 {
2329         /* Free the small buffer queue. */
2330         if (rx_ring->sbq_base) {
2331                 pci_free_consistent(qdev->pdev,
2332                                     rx_ring->sbq_size,
2333                                     rx_ring->sbq_base, rx_ring->sbq_base_dma);
2334                 rx_ring->sbq_base = NULL;
2335         }
2336
2337         /* Free the small buffer queue control blocks. */
2338         kfree(rx_ring->sbq);
2339         rx_ring->sbq = NULL;
2340
2341         /* Free the large buffer queue. */
2342         if (rx_ring->lbq_base) {
2343                 pci_free_consistent(qdev->pdev,
2344                                     rx_ring->lbq_size,
2345                                     rx_ring->lbq_base, rx_ring->lbq_base_dma);
2346                 rx_ring->lbq_base = NULL;
2347         }
2348
2349         /* Free the large buffer queue control blocks. */
2350         kfree(rx_ring->lbq);
2351         rx_ring->lbq = NULL;
2352
2353         /* Free the rx queue. */
2354         if (rx_ring->cq_base) {
2355                 pci_free_consistent(qdev->pdev,
2356                                     rx_ring->cq_size,
2357                                     rx_ring->cq_base, rx_ring->cq_base_dma);
2358                 rx_ring->cq_base = NULL;
2359         }
2360 }
2361
2362 /* Allocate queues and buffers for this completions queue based
2363  * on the values in the parameter structure. */
2364 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2365                                  struct rx_ring *rx_ring)
2366 {
2367
2368         /*
2369          * Allocate the completion queue for this rx_ring.
2370          */
2371         rx_ring->cq_base =
2372             pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2373                                  &rx_ring->cq_base_dma);
2374
2375         if (rx_ring->cq_base == NULL) {
2376                 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2377                 return -ENOMEM;
2378         }
2379
2380         if (rx_ring->sbq_len) {
2381                 /*
2382                  * Allocate small buffer queue.
2383                  */
2384                 rx_ring->sbq_base =
2385                     pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2386                                          &rx_ring->sbq_base_dma);
2387
2388                 if (rx_ring->sbq_base == NULL) {
2389                         QPRINTK(qdev, IFUP, ERR,
2390                                 "Small buffer queue allocation failed.\n");
2391                         goto err_mem;
2392                 }
2393
2394                 /*
2395                  * Allocate small buffer queue control blocks.
2396                  */
2397                 rx_ring->sbq =
2398                     kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2399                             GFP_KERNEL);
2400                 if (rx_ring->sbq == NULL) {
2401                         QPRINTK(qdev, IFUP, ERR,
2402                                 "Small buffer queue control block allocation failed.\n");
2403                         goto err_mem;
2404                 }
2405
2406                 ql_init_sbq_ring(qdev, rx_ring);
2407         }
2408
2409         if (rx_ring->lbq_len) {
2410                 /*
2411                  * Allocate large buffer queue.
2412                  */
2413                 rx_ring->lbq_base =
2414                     pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2415                                          &rx_ring->lbq_base_dma);
2416
2417                 if (rx_ring->lbq_base == NULL) {
2418                         QPRINTK(qdev, IFUP, ERR,
2419                                 "Large buffer queue allocation failed.\n");
2420                         goto err_mem;
2421                 }
2422                 /*
2423                  * Allocate large buffer queue control blocks.
2424                  */
2425                 rx_ring->lbq =
2426                     kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2427                             GFP_KERNEL);
2428                 if (rx_ring->lbq == NULL) {
2429                         QPRINTK(qdev, IFUP, ERR,
2430                                 "Large buffer queue control block allocation failed.\n");
2431                         goto err_mem;
2432                 }
2433
2434                 ql_init_lbq_ring(qdev, rx_ring);
2435         }
2436
2437         return 0;
2438
2439 err_mem:
2440         ql_free_rx_resources(qdev, rx_ring);
2441         return -ENOMEM;
2442 }
2443
2444 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2445 {
2446         struct tx_ring *tx_ring;
2447         struct tx_ring_desc *tx_ring_desc;
2448         int i, j;
2449
2450         /*
2451          * Loop through all queues and free
2452          * any resources.
2453          */
2454         for (j = 0; j < qdev->tx_ring_count; j++) {
2455                 tx_ring = &qdev->tx_ring[j];
2456                 for (i = 0; i < tx_ring->wq_len; i++) {
2457                         tx_ring_desc = &tx_ring->q[i];
2458                         if (tx_ring_desc && tx_ring_desc->skb) {
2459                                 QPRINTK(qdev, IFDOWN, ERR,
2460                                 "Freeing lost SKB %p, from queue %d, index %d.\n",
2461                                         tx_ring_desc->skb, j,
2462                                         tx_ring_desc->index);
2463                                 ql_unmap_send(qdev, tx_ring_desc,
2464                                               tx_ring_desc->map_cnt);
2465                                 dev_kfree_skb(tx_ring_desc->skb);
2466                                 tx_ring_desc->skb = NULL;
2467                         }
2468                 }
2469         }
2470 }
2471
2472 static void ql_free_mem_resources(struct ql_adapter *qdev)
2473 {
2474         int i;
2475
2476         for (i = 0; i < qdev->tx_ring_count; i++)
2477                 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2478         for (i = 0; i < qdev->rx_ring_count; i++)
2479                 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2480         ql_free_shadow_space(qdev);
2481 }
2482
2483 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2484 {
2485         int i;
2486
2487         /* Allocate space for our shadow registers and such. */
2488         if (ql_alloc_shadow_space(qdev))
2489                 return -ENOMEM;
2490
2491         for (i = 0; i < qdev->rx_ring_count; i++) {
2492                 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2493                         QPRINTK(qdev, IFUP, ERR,
2494                                 "RX resource allocation failed.\n");
2495                         goto err_mem;
2496                 }
2497         }
2498         /* Allocate tx queue resources */
2499         for (i = 0; i < qdev->tx_ring_count; i++) {
2500                 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2501                         QPRINTK(qdev, IFUP, ERR,
2502                                 "TX resource allocation failed.\n");
2503                         goto err_mem;
2504                 }
2505         }
2506         return 0;
2507
2508 err_mem:
2509         ql_free_mem_resources(qdev);
2510         return -ENOMEM;
2511 }
2512
2513 /* Set up the rx ring control block and pass it to the chip.
2514  * The control block is defined as
2515  * "Completion Queue Initialization Control Block", or cqicb.
2516  */
2517 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2518 {
2519         struct cqicb *cqicb = &rx_ring->cqicb;
2520         void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2521             (rx_ring->cq_id * sizeof(u64) * 4);
2522         u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2523             (rx_ring->cq_id * sizeof(u64) * 4);
2524         void __iomem *doorbell_area =
2525             qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2526         int err = 0;
2527         u16 bq_len;
2528         u64 tmp;
2529
2530         /* Set up the shadow registers for this ring. */
2531         rx_ring->prod_idx_sh_reg = shadow_reg;
2532         rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2533         shadow_reg += sizeof(u64);
2534         shadow_reg_dma += sizeof(u64);
2535         rx_ring->lbq_base_indirect = shadow_reg;
2536         rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2537         shadow_reg += sizeof(u64);
2538         shadow_reg_dma += sizeof(u64);
2539         rx_ring->sbq_base_indirect = shadow_reg;
2540         rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2541
2542         /* PCI doorbell mem area + 0x00 for consumer index register */
2543         rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2544         rx_ring->cnsmr_idx = 0;
2545         rx_ring->curr_entry = rx_ring->cq_base;
2546
2547         /* PCI doorbell mem area + 0x04 for valid register */
2548         rx_ring->valid_db_reg = doorbell_area + 0x04;
2549
2550         /* PCI doorbell mem area + 0x18 for large buffer consumer */
2551         rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2552
2553         /* PCI doorbell mem area + 0x1c */
2554         rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2555
2556         memset((void *)cqicb, 0, sizeof(struct cqicb));
2557         cqicb->msix_vect = rx_ring->irq;
2558
2559         bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2560         cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
2561
2562         cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
2563
2564         cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
2565
2566         /*
2567          * Set up the control block load flags.
2568          */
2569         cqicb->flags = FLAGS_LC |       /* Load queue base address */
2570             FLAGS_LV |          /* Load MSI-X vector */
2571             FLAGS_LI;           /* Load irq delay values */
2572         if (rx_ring->lbq_len) {
2573                 cqicb->flags |= FLAGS_LL;       /* Load lbq values */
2574                 tmp = (u64)rx_ring->lbq_base_dma;;
2575                 *((__le64 *) rx_ring->lbq_base_indirect) = cpu_to_le64(tmp);
2576                 cqicb->lbq_addr =
2577                     cpu_to_le64(rx_ring->lbq_base_indirect_dma);
2578                 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2579                         (u16) rx_ring->lbq_buf_size;
2580                 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2581                 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2582                         (u16) rx_ring->lbq_len;
2583                 cqicb->lbq_len = cpu_to_le16(bq_len);
2584                 rx_ring->lbq_prod_idx = 0;
2585                 rx_ring->lbq_curr_idx = 0;
2586                 rx_ring->lbq_clean_idx = 0;
2587                 rx_ring->lbq_free_cnt = rx_ring->lbq_len;
2588         }
2589         if (rx_ring->sbq_len) {
2590                 cqicb->flags |= FLAGS_LS;       /* Load sbq values */
2591                 tmp = (u64)rx_ring->sbq_base_dma;;
2592                 *((__le64 *) rx_ring->sbq_base_indirect) = cpu_to_le64(tmp);
2593                 cqicb->sbq_addr =
2594                     cpu_to_le64(rx_ring->sbq_base_indirect_dma);
2595                 cqicb->sbq_buf_size =
2596                     cpu_to_le16((u16)(rx_ring->sbq_buf_size/2));
2597                 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2598                         (u16) rx_ring->sbq_len;
2599                 cqicb->sbq_len = cpu_to_le16(bq_len);
2600                 rx_ring->sbq_prod_idx = 0;
2601                 rx_ring->sbq_curr_idx = 0;
2602                 rx_ring->sbq_clean_idx = 0;
2603                 rx_ring->sbq_free_cnt = rx_ring->sbq_len;
2604         }
2605         switch (rx_ring->type) {
2606         case TX_Q:
2607                 /* If there's only one interrupt, then we use
2608                  * worker threads to process the outbound
2609                  * completion handling rx_rings. We do this so
2610                  * they can be run on multiple CPUs. There is
2611                  * room to play with this more where we would only
2612                  * run in a worker if there are more than x number
2613                  * of outbound completions on the queue and more
2614                  * than one queue active.  Some threshold that
2615                  * would indicate a benefit in spite of the cost
2616                  * of a context switch.
2617                  * If there's more than one interrupt, then the
2618                  * outbound completions are processed in the ISR.
2619                  */
2620                 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2621                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2622                 else {
2623                         /* With all debug warnings on we see a WARN_ON message
2624                          * when we free the skb in the interrupt context.
2625                          */
2626                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2627                 }
2628                 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2629                 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2630                 break;
2631         case DEFAULT_Q:
2632                 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2633                 cqicb->irq_delay = 0;
2634                 cqicb->pkt_delay = 0;
2635                 break;
2636         case RX_Q:
2637                 /* Inbound completion handling rx_rings run in
2638                  * separate NAPI contexts.
2639                  */
2640                 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2641                                64);
2642                 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2643                 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2644                 break;
2645         default:
2646                 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2647                         rx_ring->type);
2648         }
2649         QPRINTK(qdev, IFUP, DEBUG, "Initializing rx work queue.\n");
2650         err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2651                            CFG_LCQ, rx_ring->cq_id);
2652         if (err) {
2653                 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2654                 return err;
2655         }
2656         return err;
2657 }
2658
2659 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2660 {
2661         struct wqicb *wqicb = (struct wqicb *)tx_ring;
2662         void __iomem *doorbell_area =
2663             qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2664         void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2665             (tx_ring->wq_id * sizeof(u64));
2666         u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2667             (tx_ring->wq_id * sizeof(u64));
2668         int err = 0;
2669
2670         /*
2671          * Assign doorbell registers for this tx_ring.
2672          */
2673         /* TX PCI doorbell mem area for tx producer index */
2674         tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2675         tx_ring->prod_idx = 0;
2676         /* TX PCI doorbell mem area + 0x04 */
2677         tx_ring->valid_db_reg = doorbell_area + 0x04;
2678
2679         /*
2680          * Assign shadow registers for this tx_ring.
2681          */
2682         tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2683         tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2684
2685         wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2686         wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2687                                    Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2688         wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2689         wqicb->rid = 0;
2690         wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
2691
2692         wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
2693
2694         ql_init_tx_ring(qdev, tx_ring);
2695
2696         err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2697                            (u16) tx_ring->wq_id);
2698         if (err) {
2699                 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2700                 return err;
2701         }
2702         QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded WQICB.\n");
2703         return err;
2704 }
2705
2706 static void ql_disable_msix(struct ql_adapter *qdev)
2707 {
2708         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2709                 pci_disable_msix(qdev->pdev);
2710                 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2711                 kfree(qdev->msi_x_entry);
2712                 qdev->msi_x_entry = NULL;
2713         } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2714                 pci_disable_msi(qdev->pdev);
2715                 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2716         }
2717 }
2718
2719 static void ql_enable_msix(struct ql_adapter *qdev)
2720 {
2721         int i;
2722
2723         qdev->intr_count = 1;
2724         /* Get the MSIX vectors. */
2725         if (irq_type == MSIX_IRQ) {
2726                 /* Try to alloc space for the msix struct,
2727                  * if it fails then go to MSI/legacy.
2728                  */
2729                 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2730                                             sizeof(struct msix_entry),
2731                                             GFP_KERNEL);
2732                 if (!qdev->msi_x_entry) {
2733                         irq_type = MSI_IRQ;
2734                         goto msi;
2735                 }
2736
2737                 for (i = 0; i < qdev->rx_ring_count; i++)
2738                         qdev->msi_x_entry[i].entry = i;
2739
2740                 if (!pci_enable_msix
2741                     (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2742                         set_bit(QL_MSIX_ENABLED, &qdev->flags);
2743                         qdev->intr_count = qdev->rx_ring_count;
2744                         QPRINTK(qdev, IFUP, DEBUG,
2745                                 "MSI-X Enabled, got %d vectors.\n",
2746                                 qdev->intr_count);
2747                         return;
2748                 } else {
2749                         kfree(qdev->msi_x_entry);
2750                         qdev->msi_x_entry = NULL;
2751                         QPRINTK(qdev, IFUP, WARNING,
2752                                 "MSI-X Enable failed, trying MSI.\n");
2753                         irq_type = MSI_IRQ;
2754                 }
2755         }
2756 msi:
2757         if (irq_type == MSI_IRQ) {
2758                 if (!pci_enable_msi(qdev->pdev)) {
2759                         set_bit(QL_MSI_ENABLED, &qdev->flags);
2760                         QPRINTK(qdev, IFUP, INFO,
2761                                 "Running with MSI interrupts.\n");
2762                         return;
2763                 }
2764         }
2765         irq_type = LEG_IRQ;
2766         QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2767 }
2768
2769 /*
2770  * Here we build the intr_context structures based on
2771  * our rx_ring count and intr vector count.
2772  * The intr_context structure is used to hook each vector
2773  * to possibly different handlers.
2774  */
2775 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2776 {
2777         int i = 0;
2778         struct intr_context *intr_context = &qdev->intr_context[0];
2779
2780         ql_enable_msix(qdev);
2781
2782         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2783                 /* Each rx_ring has it's
2784                  * own intr_context since we have separate
2785                  * vectors for each queue.
2786                  * This only true when MSI-X is enabled.
2787                  */
2788                 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2789                         qdev->rx_ring[i].irq = i;
2790                         intr_context->intr = i;
2791                         intr_context->qdev = qdev;
2792                         /*
2793                          * We set up each vectors enable/disable/read bits so
2794                          * there's no bit/mask calculations in the critical path.
2795                          */
2796                         intr_context->intr_en_mask =
2797                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2798                             INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2799                             | i;
2800                         intr_context->intr_dis_mask =
2801                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2802                             INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2803                             INTR_EN_IHD | i;
2804                         intr_context->intr_read_mask =
2805                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2806                             INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2807                             i;
2808
2809                         if (i == 0) {
2810                                 /*
2811                                  * Default queue handles bcast/mcast plus
2812                                  * async events.  Needs buffers.
2813                                  */
2814                                 intr_context->handler = qlge_isr;
2815                                 sprintf(intr_context->name, "%s-default-queue",
2816                                         qdev->ndev->name);
2817                         } else if (i < qdev->rss_ring_first_cq_id) {
2818                                 /*
2819                                  * Outbound queue is for outbound completions only.
2820                                  */
2821                                 intr_context->handler = qlge_msix_tx_isr;
2822                                 sprintf(intr_context->name, "%s-tx-%d",
2823                                         qdev->ndev->name, i);
2824                         } else {
2825                                 /*
2826                                  * Inbound queues handle unicast frames only.
2827                                  */
2828                                 intr_context->handler = qlge_msix_rx_isr;
2829                                 sprintf(intr_context->name, "%s-rx-%d",
2830                                         qdev->ndev->name, i);
2831                         }
2832                 }
2833         } else {
2834                 /*
2835                  * All rx_rings use the same intr_context since
2836                  * there is only one vector.
2837                  */
2838                 intr_context->intr = 0;
2839                 intr_context->qdev = qdev;
2840                 /*
2841                  * We set up each vectors enable/disable/read bits so
2842                  * there's no bit/mask calculations in the critical path.
2843                  */
2844                 intr_context->intr_en_mask =
2845                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2846                 intr_context->intr_dis_mask =
2847                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2848                     INTR_EN_TYPE_DISABLE;
2849                 intr_context->intr_read_mask =
2850                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2851                 /*
2852                  * Single interrupt means one handler for all rings.
2853                  */
2854                 intr_context->handler = qlge_isr;
2855                 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2856                 for (i = 0; i < qdev->rx_ring_count; i++)
2857                         qdev->rx_ring[i].irq = 0;
2858         }
2859 }
2860
2861 static void ql_free_irq(struct ql_adapter *qdev)
2862 {
2863         int i;
2864         struct intr_context *intr_context = &qdev->intr_context[0];
2865
2866         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2867                 if (intr_context->hooked) {
2868                         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2869                                 free_irq(qdev->msi_x_entry[i].vector,
2870                                          &qdev->rx_ring[i]);
2871                                 QPRINTK(qdev, IFDOWN, DEBUG,
2872                                         "freeing msix interrupt %d.\n", i);
2873                         } else {
2874                                 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2875                                 QPRINTK(qdev, IFDOWN, DEBUG,
2876                                         "freeing msi interrupt %d.\n", i);
2877                         }
2878                 }
2879         }
2880         ql_disable_msix(qdev);
2881 }
2882
2883 static int ql_request_irq(struct ql_adapter *qdev)
2884 {
2885         int i;
2886         int status = 0;
2887         struct pci_dev *pdev = qdev->pdev;
2888         struct intr_context *intr_context = &qdev->intr_context[0];
2889
2890         ql_resolve_queues_to_irqs(qdev);
2891
2892         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2893                 atomic_set(&intr_context->irq_cnt, 0);
2894                 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2895                         status = request_irq(qdev->msi_x_entry[i].vector,
2896                                              intr_context->handler,
2897                                              0,
2898                                              intr_context->name,
2899                                              &qdev->rx_ring[i]);
2900                         if (status) {
2901                                 QPRINTK(qdev, IFUP, ERR,
2902                                         "Failed request for MSIX interrupt %d.\n",
2903                                         i);
2904                                 goto err_irq;
2905                         } else {
2906                                 QPRINTK(qdev, IFUP, DEBUG,
2907                                         "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2908                                         i,
2909                                         qdev->rx_ring[i].type ==
2910                                         DEFAULT_Q ? "DEFAULT_Q" : "",
2911                                         qdev->rx_ring[i].type ==
2912                                         TX_Q ? "TX_Q" : "",
2913                                         qdev->rx_ring[i].type ==
2914                                         RX_Q ? "RX_Q" : "", intr_context->name);
2915                         }
2916                 } else {
2917                         QPRINTK(qdev, IFUP, DEBUG,
2918                                 "trying msi or legacy interrupts.\n");
2919                         QPRINTK(qdev, IFUP, DEBUG,
2920                                 "%s: irq = %d.\n", __func__, pdev->irq);
2921                         QPRINTK(qdev, IFUP, DEBUG,
2922                                 "%s: context->name = %s.\n", __func__,
2923                                intr_context->name);
2924                         QPRINTK(qdev, IFUP, DEBUG,
2925                                 "%s: dev_id = 0x%p.\n", __func__,
2926                                &qdev->rx_ring[0]);
2927                         status =
2928                             request_irq(pdev->irq, qlge_isr,
2929                                         test_bit(QL_MSI_ENABLED,
2930                                                  &qdev->
2931                                                  flags) ? 0 : IRQF_SHARED,
2932                                         intr_context->name, &qdev->rx_ring[0]);
2933                         if (status)
2934                                 goto err_irq;
2935
2936                         QPRINTK(qdev, IFUP, ERR,
2937                                 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2938                                 i,
2939                                 qdev->rx_ring[0].type ==
2940                                 DEFAULT_Q ? "DEFAULT_Q" : "",
2941                                 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2942                                 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2943                                 intr_context->name);
2944                 }
2945                 intr_context->hooked = 1;
2946         }
2947         return status;
2948 err_irq:
2949         QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2950         ql_free_irq(qdev);
2951         return status;
2952 }
2953
2954 static int ql_start_rss(struct ql_adapter *qdev)
2955 {
2956         struct ricb *ricb = &qdev->ricb;
2957         int status = 0;
2958         int i;
2959         u8 *hash_id = (u8 *) ricb->hash_cq_id;
2960
2961         memset((void *)ricb, 0, sizeof(ricb));
2962
2963         ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2964         ricb->flags =
2965             (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2966              RSS_RT6);
2967         ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2968
2969         /*
2970          * Fill out the Indirection Table.
2971          */
2972         for (i = 0; i < 256; i++)
2973                 hash_id[i] = i & (qdev->rss_ring_count - 1);
2974
2975         /*
2976          * Random values for the IPv6 and IPv4 Hash Keys.
2977          */
2978         get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2979         get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2980
2981         QPRINTK(qdev, IFUP, DEBUG, "Initializing RSS.\n");
2982
2983         status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2984         if (status) {
2985                 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2986                 return status;
2987         }
2988         QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded RICB.\n");
2989         return status;
2990 }
2991
2992 /* Initialize the frame-to-queue routing. */
2993 static int ql_route_initialize(struct ql_adapter *qdev)
2994 {
2995         int status = 0;
2996         int i;
2997
2998         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
2999         if (status)
3000                 return status;
3001
3002         /* Clear all the entries in the routing table. */
3003         for (i = 0; i < 16; i++) {
3004                 status = ql_set_routing_reg(qdev, i, 0, 0);
3005                 if (status) {
3006                         QPRINTK(qdev, IFUP, ERR,
3007                                 "Failed to init routing register for CAM packets.\n");
3008                         goto exit;
3009                 }
3010         }
3011
3012         status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
3013         if (status) {
3014                 QPRINTK(qdev, IFUP, ERR,
3015                         "Failed to init routing register for error packets.\n");
3016                 goto exit;
3017         }
3018         status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
3019         if (status) {
3020                 QPRINTK(qdev, IFUP, ERR,
3021                         "Failed to init routing register for broadcast packets.\n");
3022                 goto exit;
3023         }
3024         /* If we have more than one inbound queue, then turn on RSS in the
3025          * routing block.
3026          */
3027         if (qdev->rss_ring_count > 1) {
3028                 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
3029                                         RT_IDX_RSS_MATCH, 1);
3030                 if (status) {
3031                         QPRINTK(qdev, IFUP, ERR,
3032                                 "Failed to init routing register for MATCH RSS packets.\n");
3033                         goto exit;
3034                 }
3035         }
3036
3037         status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
3038                                     RT_IDX_CAM_HIT, 1);
3039         if (status)
3040                 QPRINTK(qdev, IFUP, ERR,
3041                         "Failed to init routing register for CAM packets.\n");
3042 exit:
3043         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3044         return status;
3045 }
3046
3047 int ql_cam_route_initialize(struct ql_adapter *qdev)
3048 {
3049         int status;
3050
3051         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3052         if (status)
3053                 return status;
3054         status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3055                              MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3056         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3057         if (status) {
3058                 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3059                 return status;
3060         }
3061
3062         status = ql_route_initialize(qdev);
3063         if (status)
3064                 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3065
3066         return status;
3067 }
3068
3069 static int ql_adapter_initialize(struct ql_adapter *qdev)
3070 {
3071         u32 value, mask;
3072         int i;
3073         int status = 0;
3074
3075         /*
3076          * Set up the System register to halt on errors.
3077          */
3078         value = SYS_EFE | SYS_FAE;
3079         mask = value << 16;
3080         ql_write32(qdev, SYS, mask | value);
3081
3082         /* Set the default queue, and VLAN behavior. */
3083         value = NIC_RCV_CFG_DFQ | NIC_RCV_CFG_RV;
3084         mask = NIC_RCV_CFG_DFQ_MASK | (NIC_RCV_CFG_RV << 16);
3085         ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3086
3087         /* Set the MPI interrupt to enabled. */
3088         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3089
3090         /* Enable the function, set pagesize, enable error checking. */
3091         value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3092             FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
3093
3094         /* Set/clear header splitting. */
3095         mask = FSC_VM_PAGESIZE_MASK |
3096             FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3097         ql_write32(qdev, FSC, mask | value);
3098
3099         ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3100                 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3101
3102         /* Start up the rx queues. */
3103         for (i = 0; i < qdev->rx_ring_count; i++) {
3104                 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3105                 if (status) {
3106                         QPRINTK(qdev, IFUP, ERR,
3107                                 "Failed to start rx ring[%d].\n", i);
3108                         return status;
3109                 }
3110         }
3111
3112         /* If there is more than one inbound completion queue
3113          * then download a RICB to configure RSS.
3114          */
3115         if (qdev->rss_ring_count > 1) {
3116                 status = ql_start_rss(qdev);
3117                 if (status) {
3118                         QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3119                         return status;
3120                 }
3121         }
3122
3123         /* Start up the tx queues. */
3124         for (i = 0; i < qdev->tx_ring_count; i++) {
3125                 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3126                 if (status) {
3127                         QPRINTK(qdev, IFUP, ERR,
3128                                 "Failed to start tx ring[%d].\n", i);
3129                         return status;
3130                 }
3131         }
3132
3133         /* Initialize the port and set the max framesize. */
3134         status = qdev->nic_ops->port_initialize(qdev);
3135        if (status) {
3136               QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3137               return status;
3138        }
3139
3140         /* Set up the MAC address and frame routing filter. */
3141         status = ql_cam_route_initialize(qdev);
3142         if (status) {
3143                 QPRINTK(qdev, IFUP, ERR,
3144                                 "Failed to init CAM/Routing tables.\n");
3145                 return status;
3146         }
3147
3148         /* Start NAPI for the RSS queues. */
3149         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3150                 QPRINTK(qdev, IFUP, DEBUG, "Enabling NAPI for rx_ring[%d].\n",
3151                         i);
3152                 napi_enable(&qdev->rx_ring[i].napi);
3153         }
3154
3155         return status;
3156 }
3157
3158 /* Issue soft reset to chip. */
3159 static int ql_adapter_reset(struct ql_adapter *qdev)
3160 {
3161         u32 value;
3162         int status = 0;
3163         unsigned long end_jiffies = jiffies +
3164                 max((unsigned long)1, usecs_to_jiffies(30));
3165
3166         ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3167
3168         do {
3169                 value = ql_read32(qdev, RST_FO);
3170                 if ((value & RST_FO_FR) == 0)
3171                         break;
3172                 cpu_relax();
3173         } while (time_before(jiffies, end_jiffies));
3174
3175         if (value & RST_FO_FR) {
3176                 QPRINTK(qdev, IFDOWN, ERR,
3177                         "ETIMEDOUT!!! errored out of resetting the chip!\n");
3178                 status = -ETIMEDOUT;
3179         }
3180
3181         return status;
3182 }
3183
3184 static void ql_display_dev_info(struct net_device *ndev)
3185 {
3186         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3187
3188         QPRINTK(qdev, PROBE, INFO,
3189                 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3190                 "XG Roll = %d, XG Rev = %d.\n",
3191                 qdev->func,
3192                 qdev->chip_rev_id & 0x0000000f,
3193                 qdev->chip_rev_id >> 4 & 0x0000000f,
3194                 qdev->chip_rev_id >> 8 & 0x0000000f,
3195                 qdev->chip_rev_id >> 12 & 0x0000000f);
3196         QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3197 }
3198
3199 static int ql_adapter_down(struct ql_adapter *qdev)
3200 {
3201         int i, status = 0;
3202         struct rx_ring *rx_ring;
3203
3204         netif_carrier_off(qdev->ndev);
3205
3206         /* Don't kill the reset worker thread if we
3207          * are in the process of recovery.
3208          */
3209         if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3210                 cancel_delayed_work_sync(&qdev->asic_reset_work);
3211         cancel_delayed_work_sync(&qdev->mpi_reset_work);
3212         cancel_delayed_work_sync(&qdev->mpi_work);
3213         cancel_delayed_work_sync(&qdev->mpi_idc_work);
3214         cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
3215
3216         /* The default queue at index 0 is always processed in
3217          * a workqueue.
3218          */
3219         cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3220
3221         /* The rest of the rx_rings are processed in
3222          * a workqueue only if it's a single interrupt
3223          * environment (MSI/Legacy).
3224          */
3225         for (i = 1; i < qdev->rx_ring_count; i++) {
3226                 rx_ring = &qdev->rx_ring[i];
3227                 /* Only the RSS rings use NAPI on multi irq
3228                  * environment.  Outbound completion processing
3229                  * is done in interrupt context.
3230                  */
3231                 if (i >= qdev->rss_ring_first_cq_id) {
3232                         napi_disable(&rx_ring->napi);
3233                 } else {
3234                         cancel_delayed_work_sync(&rx_ring->rx_work);
3235                 }
3236         }
3237
3238         clear_bit(QL_ADAPTER_UP, &qdev->flags);
3239
3240         ql_disable_interrupts(qdev);
3241
3242         ql_tx_ring_clean(qdev);
3243
3244         /* Call netif_napi_del() from common point.
3245          */
3246         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++)
3247                 netif_napi_del(&qdev->rx_ring[i].napi);
3248
3249         ql_free_rx_buffers(qdev);
3250
3251         spin_lock(&qdev->hw_lock);
3252         status = ql_adapter_reset(qdev);
3253         if (status)
3254                 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3255                         qdev->func);
3256         spin_unlock(&qdev->hw_lock);
3257         return status;
3258 }
3259
3260 static int ql_adapter_up(struct ql_adapter *qdev)
3261 {
3262         int err = 0;
3263
3264         err = ql_adapter_initialize(qdev);
3265         if (err) {
3266                 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3267                 spin_unlock(&qdev->hw_lock);
3268                 goto err_init;
3269         }
3270         set_bit(QL_ADAPTER_UP, &qdev->flags);
3271         ql_alloc_rx_buffers(qdev);
3272         if ((ql_read32(qdev, STS) & qdev->port_init))
3273                 netif_carrier_on(qdev->ndev);
3274         ql_enable_interrupts(qdev);
3275         ql_enable_all_completion_interrupts(qdev);
3276         netif_tx_start_all_queues(qdev->ndev);
3277
3278         return 0;
3279 err_init:
3280         ql_adapter_reset(qdev);
3281         return err;
3282 }
3283
3284 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3285 {
3286         ql_free_mem_resources(qdev);
3287         ql_free_irq(qdev);
3288 }
3289
3290 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3291 {
3292         int status = 0;
3293
3294         if (ql_alloc_mem_resources(qdev)) {
3295                 QPRINTK(qdev, IFUP, ERR, "Unable to  allocate memory.\n");
3296                 return -ENOMEM;
3297         }
3298         status = ql_request_irq(qdev);
3299         if (status)
3300                 goto err_irq;
3301         return status;
3302 err_irq:
3303         ql_free_mem_resources(qdev);
3304         return status;
3305 }
3306
3307 static int qlge_close(struct net_device *ndev)
3308 {
3309         struct ql_adapter *qdev = netdev_priv(ndev);
3310
3311         /*
3312          * Wait for device to recover from a reset.
3313          * (Rarely happens, but possible.)
3314          */
3315         while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3316                 msleep(1);
3317         ql_adapter_down(qdev);
3318         ql_release_adapter_resources(qdev);
3319         return 0;
3320 }
3321
3322 static int ql_configure_rings(struct ql_adapter *qdev)
3323 {
3324         int i;
3325         struct rx_ring *rx_ring;
3326         struct tx_ring *tx_ring;
3327         int cpu_cnt = num_online_cpus();
3328
3329         /*
3330          * For each processor present we allocate one
3331          * rx_ring for outbound completions, and one
3332          * rx_ring for inbound completions.  Plus there is
3333          * always the one default queue.  For the CPU
3334          * counts we end up with the following rx_rings:
3335          * rx_ring count =
3336          *  one default queue +
3337          *  (CPU count * outbound completion rx_ring) +
3338          *  (CPU count * inbound (RSS) completion rx_ring)
3339          * To keep it simple we limit the total number of
3340          * queues to < 32, so we truncate CPU to 8.
3341          * This limitation can be removed when requested.
3342          */
3343
3344         if (cpu_cnt > MAX_CPUS)
3345                 cpu_cnt = MAX_CPUS;
3346
3347         /*
3348          * rx_ring[0] is always the default queue.
3349          */
3350         /* Allocate outbound completion ring for each CPU. */
3351         qdev->tx_ring_count = cpu_cnt;
3352         /* Allocate inbound completion (RSS) ring for each CPU. */
3353         qdev->rss_ring_count = cpu_cnt;
3354         /* cq_id for the first inbound ring handler. */
3355         qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3356         /*
3357          * qdev->rx_ring_count:
3358          * Total number of rx_rings.  This includes the one
3359          * default queue, a number of outbound completion
3360          * handler rx_rings, and the number of inbound
3361          * completion handler rx_rings.
3362          */
3363         qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3364         netif_set_gso_max_size(qdev->ndev, 65536);
3365
3366         for (i = 0; i < qdev->tx_ring_count; i++) {
3367                 tx_ring = &qdev->tx_ring[i];
3368                 memset((void *)tx_ring, 0, sizeof(tx_ring));
3369                 tx_ring->qdev = qdev;
3370                 tx_ring->wq_id = i;
3371                 tx_ring->wq_len = qdev->tx_ring_size;
3372                 tx_ring->wq_size =
3373                     tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3374
3375                 /*
3376                  * The completion queue ID for the tx rings start
3377                  * immediately after the default Q ID, which is zero.
3378                  */
3379                 tx_ring->cq_id = i + 1;
3380         }
3381
3382         for (i = 0; i < qdev->rx_ring_count; i++) {
3383                 rx_ring = &qdev->rx_ring[i];
3384                 memset((void *)rx_ring, 0, sizeof(rx_ring));
3385                 rx_ring->qdev = qdev;
3386                 rx_ring->cq_id = i;
3387                 rx_ring->cpu = i % cpu_cnt;     /* CPU to run handler on. */
3388                 if (i == 0) {   /* Default queue at index 0. */
3389                         /*
3390                          * Default queue handles bcast/mcast plus
3391                          * async events.  Needs buffers.
3392                          */
3393                         rx_ring->cq_len = qdev->rx_ring_size;
3394                         rx_ring->cq_size =
3395                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3396                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3397                         rx_ring->lbq_size =
3398                             rx_ring->lbq_len * sizeof(__le64);
3399                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3400                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3401                         rx_ring->sbq_size =
3402                             rx_ring->sbq_len * sizeof(__le64);
3403                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3404                         rx_ring->type = DEFAULT_Q;
3405                 } else if (i < qdev->rss_ring_first_cq_id) {
3406                         /*
3407                          * Outbound queue handles outbound completions only.
3408                          */
3409                         /* outbound cq is same size as tx_ring it services. */
3410                         rx_ring->cq_len = qdev->tx_ring_size;
3411                         rx_ring->cq_size =
3412                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3413                         rx_ring->lbq_len = 0;
3414                         rx_ring->lbq_size = 0;
3415                         rx_ring->lbq_buf_size = 0;
3416                         rx_ring->sbq_len = 0;
3417                         rx_ring->sbq_size = 0;
3418                         rx_ring->sbq_buf_size = 0;
3419                         rx_ring->type = TX_Q;
3420                 } else {        /* Inbound completions (RSS) queues */
3421                         /*
3422                          * Inbound queues handle unicast frames only.
3423                          */
3424                         rx_ring->cq_len = qdev->rx_ring_size;
3425                         rx_ring->cq_size =
3426                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3427                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3428                         rx_ring->lbq_size =
3429                             rx_ring->lbq_len * sizeof(__le64);
3430                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3431                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3432                         rx_ring->sbq_size =
3433                             rx_ring->sbq_len * sizeof(__le64);
3434                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3435                         rx_ring->type = RX_Q;
3436                 }
3437         }
3438         return 0;
3439 }
3440
3441 static int qlge_open(struct net_device *ndev)
3442 {
3443         int err = 0;
3444         struct ql_adapter *qdev = netdev_priv(ndev);
3445
3446         err = ql_configure_rings(qdev);
3447         if (err)
3448                 return err;
3449
3450         err = ql_get_adapter_resources(qdev);
3451         if (err)
3452                 goto error_up;
3453
3454         err = ql_adapter_up(qdev);
3455         if (err)
3456                 goto error_up;
3457
3458         return err;
3459
3460 error_up:
3461         ql_release_adapter_resources(qdev);
3462         return err;
3463 }
3464
3465 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3466 {
3467         struct ql_adapter *qdev = netdev_priv(ndev);
3468
3469         if (ndev->mtu == 1500 && new_mtu == 9000) {
3470                 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3471                 queue_delayed_work(qdev->workqueue,
3472                                 &qdev->mpi_port_cfg_work, 0);
3473         } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3474                 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3475         } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3476                    (ndev->mtu == 9000 && new_mtu == 9000)) {
3477                 return 0;
3478         } else
3479                 return -EINVAL;
3480         ndev->mtu = new_mtu;
3481         return 0;
3482 }
3483
3484 static struct net_device_stats *qlge_get_stats(struct net_device
3485                                                *ndev)
3486 {
3487         struct ql_adapter *qdev = netdev_priv(ndev);
3488         return &qdev->stats;
3489 }
3490
3491 static void qlge_set_multicast_list(struct net_device *ndev)
3492 {
3493         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3494         struct dev_mc_list *mc_ptr;
3495         int i, status;
3496
3497         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3498         if (status)
3499                 return;
3500         spin_lock(&qdev->hw_lock);
3501         /*
3502          * Set or clear promiscuous mode if a
3503          * transition is taking place.
3504          */
3505         if (ndev->flags & IFF_PROMISC) {
3506                 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3507                         if (ql_set_routing_reg
3508                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3509                                 QPRINTK(qdev, HW, ERR,
3510                                         "Failed to set promiscous mode.\n");
3511                         } else {
3512                                 set_bit(QL_PROMISCUOUS, &qdev->flags);
3513                         }
3514                 }
3515         } else {
3516                 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3517                         if (ql_set_routing_reg
3518                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3519                                 QPRINTK(qdev, HW, ERR,
3520                                         "Failed to clear promiscous mode.\n");
3521                         } else {
3522                                 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3523                         }
3524                 }
3525         }
3526
3527         /*
3528          * Set or clear all multicast mode if a
3529          * transition is taking place.
3530          */
3531         if ((ndev->flags & IFF_ALLMULTI) ||
3532             (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3533                 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3534                         if (ql_set_routing_reg
3535                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3536                                 QPRINTK(qdev, HW, ERR,
3537                                         "Failed to set all-multi mode.\n");
3538                         } else {
3539                                 set_bit(QL_ALLMULTI, &qdev->flags);
3540                         }
3541                 }
3542         } else {
3543                 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3544                         if (ql_set_routing_reg
3545                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3546                                 QPRINTK(qdev, HW, ERR,
3547                                         "Failed to clear all-multi mode.\n");
3548                         } else {
3549                                 clear_bit(QL_ALLMULTI, &qdev->flags);
3550                         }
3551                 }
3552         }
3553
3554         if (ndev->mc_count) {
3555                 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3556                 if (status)
3557                         goto exit;
3558                 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3559                      i++, mc_ptr = mc_ptr->next)
3560                         if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3561                                                 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3562                                 QPRINTK(qdev, HW, ERR,
3563                                         "Failed to loadmulticast address.\n");
3564                                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3565                                 goto exit;
3566                         }
3567                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3568                 if (ql_set_routing_reg
3569                     (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3570                         QPRINTK(qdev, HW, ERR,
3571                                 "Failed to set multicast match mode.\n");
3572                 } else {
3573                         set_bit(QL_ALLMULTI, &qdev->flags);
3574                 }
3575         }
3576 exit:
3577         spin_unlock(&qdev->hw_lock);
3578         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3579 }
3580
3581 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3582 {
3583         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3584         struct sockaddr *addr = p;
3585         int status;
3586
3587         if (netif_running(ndev))
3588                 return -EBUSY;
3589
3590         if (!is_valid_ether_addr(addr->sa_data))
3591                 return -EADDRNOTAVAIL;
3592         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3593
3594         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3595         if (status)
3596                 return status;
3597         spin_lock(&qdev->hw_lock);
3598         status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3599                         MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3600         spin_unlock(&qdev->hw_lock);
3601         if (status)
3602                 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3603         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3604         return status;
3605 }
3606
3607 static void qlge_tx_timeout(struct net_device *ndev)
3608 {
3609         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3610         ql_queue_asic_error(qdev);
3611 }
3612
3613 static void ql_asic_reset_work(struct work_struct *work)
3614 {
3615         struct ql_adapter *qdev =
3616             container_of(work, struct ql_adapter, asic_reset_work.work);
3617         int status;
3618
3619         status = ql_adapter_down(qdev);
3620         if (status)
3621                 goto error;
3622
3623         status = ql_adapter_up(qdev);
3624         if (status)
3625                 goto error;
3626
3627         return;
3628 error:
3629         QPRINTK(qdev, IFUP, ALERT,
3630                 "Driver up/down cycle failed, closing device\n");
3631         rtnl_lock();
3632         set_bit(QL_ADAPTER_UP, &qdev->flags);
3633         dev_close(qdev->ndev);
3634         rtnl_unlock();
3635 }
3636
3637 static struct nic_operations qla8012_nic_ops = {
3638         .get_flash              = ql_get_8012_flash_params,
3639         .port_initialize        = ql_8012_port_initialize,
3640 };
3641
3642 static struct nic_operations qla8000_nic_ops = {
3643         .get_flash              = ql_get_8000_flash_params,
3644         .port_initialize        = ql_8000_port_initialize,
3645 };
3646
3647
3648 static void ql_get_board_info(struct ql_adapter *qdev)
3649 {
3650         qdev->func =
3651             (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3652         if (qdev->func) {
3653                 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3654                 qdev->port_link_up = STS_PL1;
3655                 qdev->port_init = STS_PI1;
3656                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3657                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3658         } else {
3659                 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3660                 qdev->port_link_up = STS_PL0;
3661                 qdev->port_init = STS_PI0;
3662                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3663                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3664         }
3665         qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3666         qdev->device_id = qdev->pdev->device;
3667         if (qdev->device_id == QLGE_DEVICE_ID_8012)
3668                 qdev->nic_ops = &qla8012_nic_ops;
3669         else if (qdev->device_id == QLGE_DEVICE_ID_8000)
3670                 qdev->nic_ops = &qla8000_nic_ops;
3671 }
3672
3673 static void ql_release_all(struct pci_dev *pdev)
3674 {
3675         struct net_device *ndev = pci_get_drvdata(pdev);
3676         struct ql_adapter *qdev = netdev_priv(ndev);
3677
3678         if (qdev->workqueue) {
3679                 destroy_workqueue(qdev->workqueue);
3680                 qdev->workqueue = NULL;
3681         }
3682         if (qdev->q_workqueue) {
3683                 destroy_workqueue(qdev->q_workqueue);
3684                 qdev->q_workqueue = NULL;
3685         }
3686         if (qdev->reg_base)
3687                 iounmap(qdev->reg_base);
3688         if (qdev->doorbell_area)
3689                 iounmap(qdev->doorbell_area);
3690         pci_release_regions(pdev);
3691         pci_set_drvdata(pdev, NULL);
3692 }
3693
3694 static int __devinit ql_init_device(struct pci_dev *pdev,
3695                                     struct net_device *ndev, int cards_found)
3696 {
3697         struct ql_adapter *qdev = netdev_priv(ndev);
3698         int pos, err = 0;
3699         u16 val16;
3700
3701         memset((void *)qdev, 0, sizeof(qdev));
3702         err = pci_enable_device(pdev);
3703         if (err) {
3704                 dev_err(&pdev->dev, "PCI device enable failed.\n");
3705                 return err;
3706         }
3707
3708         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3709         if (pos <= 0) {
3710                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3711                         "aborting.\n");
3712                 goto err_out;
3713         } else {
3714                 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3715                 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3716                 val16 |= (PCI_EXP_DEVCTL_CERE |
3717                           PCI_EXP_DEVCTL_NFERE |
3718                           PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3719                 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3720         }
3721
3722         err = pci_request_regions(pdev, DRV_NAME);
3723         if (err) {
3724                 dev_err(&pdev->dev, "PCI region request failed.\n");
3725                 goto err_out;
3726         }
3727
3728         pci_set_master(pdev);
3729         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3730                 set_bit(QL_DMA64, &qdev->flags);
3731                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3732         } else {
3733                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3734                 if (!err)
3735                        err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3736         }
3737
3738         if (err) {
3739                 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3740                 goto err_out;
3741         }
3742
3743         pci_set_drvdata(pdev, ndev);
3744         qdev->reg_base =
3745             ioremap_nocache(pci_resource_start(pdev, 1),
3746                             pci_resource_len(pdev, 1));
3747         if (!qdev->reg_base) {
3748                 dev_err(&pdev->dev, "Register mapping failed.\n");
3749                 err = -ENOMEM;
3750                 goto err_out;
3751         }
3752
3753         qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3754         qdev->doorbell_area =
3755             ioremap_nocache(pci_resource_start(pdev, 3),
3756                             pci_resource_len(pdev, 3));
3757         if (!qdev->doorbell_area) {
3758                 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3759                 err = -ENOMEM;
3760                 goto err_out;
3761         }
3762
3763         qdev->ndev = ndev;
3764         qdev->pdev = pdev;
3765         ql_get_board_info(qdev);
3766         qdev->msg_enable = netif_msg_init(debug, default_msg);
3767         spin_lock_init(&qdev->hw_lock);
3768         spin_lock_init(&qdev->stats_lock);
3769
3770         /* make sure the EEPROM is good */
3771         err = qdev->nic_ops->get_flash(qdev);
3772         if (err) {
3773                 dev_err(&pdev->dev, "Invalid FLASH.\n");
3774                 goto err_out;
3775         }
3776
3777         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3778
3779         /* Set up the default ring sizes. */
3780         qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3781         qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3782
3783         /* Set up the coalescing parameters. */
3784         qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3785         qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3786         qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3787         qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3788
3789         /*
3790          * Set up the operating parameters.
3791          */
3792         qdev->rx_csum = 1;
3793
3794         qdev->q_workqueue = create_workqueue(ndev->name);
3795         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3796         INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3797         INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3798         INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3799         INIT_DELAYED_WORK(&qdev->mpi_port_cfg_work, ql_mpi_port_cfg_work);
3800         INIT_DELAYED_WORK(&qdev->mpi_idc_work, ql_mpi_idc_work);
3801         mutex_init(&qdev->mpi_mutex);
3802         init_completion(&qdev->ide_completion);
3803
3804         if (!cards_found) {
3805                 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3806                 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3807                          DRV_NAME, DRV_VERSION);
3808         }
3809         return 0;
3810 err_out:
3811         ql_release_all(pdev);
3812         pci_disable_device(pdev);
3813         return err;
3814 }
3815
3816
3817 static const struct net_device_ops qlge_netdev_ops = {
3818         .ndo_open               = qlge_open,
3819         .ndo_stop               = qlge_close,
3820         .ndo_start_xmit         = qlge_send,
3821         .ndo_change_mtu         = qlge_change_mtu,
3822         .ndo_get_stats          = qlge_get_stats,
3823         .ndo_set_multicast_list = qlge_set_multicast_list,
3824         .ndo_set_mac_address    = qlge_set_mac_address,
3825         .ndo_validate_addr      = eth_validate_addr,
3826         .ndo_tx_timeout         = qlge_tx_timeout,
3827         .ndo_vlan_rx_register   = ql_vlan_rx_register,
3828         .ndo_vlan_rx_add_vid    = ql_vlan_rx_add_vid,
3829         .ndo_vlan_rx_kill_vid   = ql_vlan_rx_kill_vid,
3830 };
3831
3832 static int __devinit qlge_probe(struct pci_dev *pdev,
3833                                 const struct pci_device_id *pci_entry)
3834 {
3835         struct net_device *ndev = NULL;
3836         struct ql_adapter *qdev = NULL;
3837         static int cards_found = 0;
3838         int err = 0;
3839
3840         ndev = alloc_etherdev_mq(sizeof(struct ql_adapter),
3841                         min(MAX_CPUS, (int)num_online_cpus()));
3842         if (!ndev)
3843                 return -ENOMEM;
3844
3845         err = ql_init_device(pdev, ndev, cards_found);
3846         if (err < 0) {
3847                 free_netdev(ndev);
3848                 return err;
3849         }
3850
3851         qdev = netdev_priv(ndev);
3852         SET_NETDEV_DEV(ndev, &pdev->dev);
3853         ndev->features = (0
3854                           | NETIF_F_IP_CSUM
3855                           | NETIF_F_SG
3856                           | NETIF_F_TSO
3857                           | NETIF_F_TSO6
3858                           | NETIF_F_TSO_ECN
3859                           | NETIF_F_HW_VLAN_TX
3860                           | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3861         ndev->features |= NETIF_F_GRO;
3862
3863         if (test_bit(QL_DMA64, &qdev->flags))
3864                 ndev->features |= NETIF_F_HIGHDMA;
3865
3866         /*
3867          * Set up net_device structure.
3868          */
3869         ndev->tx_queue_len = qdev->tx_ring_size;
3870         ndev->irq = pdev->irq;
3871
3872         ndev->netdev_ops = &qlge_netdev_ops;
3873         SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
3874         ndev->watchdog_timeo = 10 * HZ;
3875
3876         err = register_netdev(ndev);
3877         if (err) {
3878                 dev_err(&pdev->dev, "net device registration failed.\n");
3879                 ql_release_all(pdev);
3880                 pci_disable_device(pdev);
3881                 return err;
3882         }
3883         netif_carrier_off(ndev);
3884         ql_display_dev_info(ndev);
3885         cards_found++;
3886         return 0;
3887 }
3888
3889 static void __devexit qlge_remove(struct pci_dev *pdev)
3890 {
3891         struct net_device *ndev = pci_get_drvdata(pdev);
3892         unregister_netdev(ndev);
3893         ql_release_all(pdev);
3894         pci_disable_device(pdev);
3895         free_netdev(ndev);
3896 }
3897
3898 /*
3899  * This callback is called by the PCI subsystem whenever
3900  * a PCI bus error is detected.
3901  */
3902 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3903                                                enum pci_channel_state state)
3904 {
3905         struct net_device *ndev = pci_get_drvdata(pdev);
3906         struct ql_adapter *qdev = netdev_priv(ndev);
3907
3908         if (netif_running(ndev))
3909                 ql_adapter_down(qdev);
3910
3911         pci_disable_device(pdev);
3912
3913         /* Request a slot reset. */
3914         return PCI_ERS_RESULT_NEED_RESET;
3915 }
3916
3917 /*
3918  * This callback is called after the PCI buss has been reset.
3919  * Basically, this tries to restart the card from scratch.
3920  * This is a shortened version of the device probe/discovery code,
3921  * it resembles the first-half of the () routine.
3922  */
3923 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3924 {
3925         struct net_device *ndev = pci_get_drvdata(pdev);
3926         struct ql_adapter *qdev = netdev_priv(ndev);
3927
3928         if (pci_enable_device(pdev)) {
3929                 QPRINTK(qdev, IFUP, ERR,
3930                         "Cannot re-enable PCI device after reset.\n");
3931                 return PCI_ERS_RESULT_DISCONNECT;
3932         }
3933
3934         pci_set_master(pdev);
3935
3936         netif_carrier_off(ndev);
3937         ql_adapter_reset(qdev);
3938
3939         /* Make sure the EEPROM is good */
3940         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3941
3942         if (!is_valid_ether_addr(ndev->perm_addr)) {
3943                 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3944                 return PCI_ERS_RESULT_DISCONNECT;
3945         }
3946
3947         return PCI_ERS_RESULT_RECOVERED;
3948 }
3949
3950 static void qlge_io_resume(struct pci_dev *pdev)
3951 {
3952         struct net_device *ndev = pci_get_drvdata(pdev);
3953         struct ql_adapter *qdev = netdev_priv(ndev);
3954
3955         pci_set_master(pdev);
3956
3957         if (netif_running(ndev)) {
3958                 if (ql_adapter_up(qdev)) {
3959                         QPRINTK(qdev, IFUP, ERR,
3960                                 "Device initialization failed after reset.\n");
3961                         return;
3962                 }
3963         }
3964
3965         netif_device_attach(ndev);
3966 }
3967
3968 static struct pci_error_handlers qlge_err_handler = {
3969         .error_detected = qlge_io_error_detected,
3970         .slot_reset = qlge_io_slot_reset,
3971         .resume = qlge_io_resume,
3972 };
3973
3974 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3975 {
3976         struct net_device *ndev = pci_get_drvdata(pdev);
3977         struct ql_adapter *qdev = netdev_priv(ndev);
3978         int err;
3979
3980         netif_device_detach(ndev);
3981
3982         if (netif_running(ndev)) {
3983                 err = ql_adapter_down(qdev);
3984                 if (!err)
3985                         return err;
3986         }
3987
3988         err = pci_save_state(pdev);
3989         if (err)
3990                 return err;
3991
3992         pci_disable_device(pdev);
3993
3994         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3995
3996         return 0;
3997 }
3998
3999 #ifdef CONFIG_PM
4000 static int qlge_resume(struct pci_dev *pdev)
4001 {
4002         struct net_device *ndev = pci_get_drvdata(pdev);
4003         struct ql_adapter *qdev = netdev_priv(ndev);
4004         int err;
4005
4006         pci_set_power_state(pdev, PCI_D0);
4007         pci_restore_state(pdev);
4008         err = pci_enable_device(pdev);
4009         if (err) {
4010                 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
4011                 return err;
4012         }
4013         pci_set_master(pdev);
4014
4015         pci_enable_wake(pdev, PCI_D3hot, 0);
4016         pci_enable_wake(pdev, PCI_D3cold, 0);
4017
4018         if (netif_running(ndev)) {
4019                 err = ql_adapter_up(qdev);
4020                 if (err)
4021                         return err;
4022         }
4023
4024         netif_device_attach(ndev);
4025
4026         return 0;
4027 }
4028 #endif /* CONFIG_PM */
4029
4030 static void qlge_shutdown(struct pci_dev *pdev)
4031 {
4032         qlge_suspend(pdev, PMSG_SUSPEND);
4033 }
4034
4035 static struct pci_driver qlge_driver = {
4036         .name = DRV_NAME,
4037         .id_table = qlge_pci_tbl,
4038         .probe = qlge_probe,
4039         .remove = __devexit_p(qlge_remove),
4040 #ifdef CONFIG_PM
4041         .suspend = qlge_suspend,
4042         .resume = qlge_resume,
4043 #endif
4044         .shutdown = qlge_shutdown,
4045         .err_handler = &qlge_err_handler
4046 };
4047
4048 static int __init qlge_init_module(void)
4049 {
4050         return pci_register_driver(&qlge_driver);
4051 }
4052
4053 static void __exit qlge_exit(void)
4054 {
4055         pci_unregister_driver(&qlge_driver);
4056 }
4057
4058 module_init(qlge_init_module);
4059 module_exit(qlge_exit);