qlge: Add tx multiqueue support.
[linux-2.6.git] / drivers / net / qlge / qlge_main.c
1 /*
2  * QLogic qlge NIC HBA Driver
3  * Copyright (c)  2003-2008 QLogic Corporation
4  * See LICENSE.qlge for copyright and licensing details.
5  * Author:     Linux qlge network device driver by
6  *                      Ron Mercer <ron.mercer@qlogic.com>
7  */
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/pagemap.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/dmapool.h>
19 #include <linux/mempool.h>
20 #include <linux/spinlock.h>
21 #include <linux/kthread.h>
22 #include <linux/interrupt.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/in.h>
26 #include <linux/ip.h>
27 #include <linux/ipv6.h>
28 #include <net/ipv6.h>
29 #include <linux/tcp.h>
30 #include <linux/udp.h>
31 #include <linux/if_arp.h>
32 #include <linux/if_ether.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/skbuff.h>
37 #include <linux/rtnetlink.h>
38 #include <linux/if_vlan.h>
39 #include <linux/delay.h>
40 #include <linux/mm.h>
41 #include <linux/vmalloc.h>
42 #include <net/ip6_checksum.h>
43
44 #include "qlge.h"
45
46 char qlge_driver_name[] = DRV_NAME;
47 const char qlge_driver_version[] = DRV_VERSION;
48
49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
50 MODULE_DESCRIPTION(DRV_STRING " ");
51 MODULE_LICENSE("GPL");
52 MODULE_VERSION(DRV_VERSION);
53
54 static const u32 default_msg =
55     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
56 /* NETIF_MSG_TIMER |    */
57     NETIF_MSG_IFDOWN |
58     NETIF_MSG_IFUP |
59     NETIF_MSG_RX_ERR |
60     NETIF_MSG_TX_ERR |
61 /*  NETIF_MSG_TX_QUEUED | */
62 /*  NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS | */
63 /* NETIF_MSG_PKTDATA | */
64     NETIF_MSG_HW | NETIF_MSG_WOL | 0;
65
66 static int debug = 0x00007fff;  /* defaults above */
67 module_param(debug, int, 0);
68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
69
70 #define MSIX_IRQ 0
71 #define MSI_IRQ 1
72 #define LEG_IRQ 2
73 static int irq_type = MSIX_IRQ;
74 module_param(irq_type, int, MSIX_IRQ);
75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
76
77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
78         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8012)},
79         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8000)},
80         /* required last entry */
81         {0,}
82 };
83
84 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
85
86 /* This hardware semaphore causes exclusive access to
87  * resources shared between the NIC driver, MPI firmware,
88  * FCOE firmware and the FC driver.
89  */
90 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
91 {
92         u32 sem_bits = 0;
93
94         switch (sem_mask) {
95         case SEM_XGMAC0_MASK:
96                 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
97                 break;
98         case SEM_XGMAC1_MASK:
99                 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
100                 break;
101         case SEM_ICB_MASK:
102                 sem_bits = SEM_SET << SEM_ICB_SHIFT;
103                 break;
104         case SEM_MAC_ADDR_MASK:
105                 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
106                 break;
107         case SEM_FLASH_MASK:
108                 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
109                 break;
110         case SEM_PROBE_MASK:
111                 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
112                 break;
113         case SEM_RT_IDX_MASK:
114                 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
115                 break;
116         case SEM_PROC_REG_MASK:
117                 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
118                 break;
119         default:
120                 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
121                 return -EINVAL;
122         }
123
124         ql_write32(qdev, SEM, sem_bits | sem_mask);
125         return !(ql_read32(qdev, SEM) & sem_bits);
126 }
127
128 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
129 {
130         unsigned int wait_count = 30;
131         do {
132                 if (!ql_sem_trylock(qdev, sem_mask))
133                         return 0;
134                 udelay(100);
135         } while (--wait_count);
136         return -ETIMEDOUT;
137 }
138
139 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
140 {
141         ql_write32(qdev, SEM, sem_mask);
142         ql_read32(qdev, SEM);   /* flush */
143 }
144
145 /* This function waits for a specific bit to come ready
146  * in a given register.  It is used mostly by the initialize
147  * process, but is also used in kernel thread API such as
148  * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
149  */
150 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
151 {
152         u32 temp;
153         int count = UDELAY_COUNT;
154
155         while (count) {
156                 temp = ql_read32(qdev, reg);
157
158                 /* check for errors */
159                 if (temp & err_bit) {
160                         QPRINTK(qdev, PROBE, ALERT,
161                                 "register 0x%.08x access error, value = 0x%.08x!.\n",
162                                 reg, temp);
163                         return -EIO;
164                 } else if (temp & bit)
165                         return 0;
166                 udelay(UDELAY_DELAY);
167                 count--;
168         }
169         QPRINTK(qdev, PROBE, ALERT,
170                 "Timed out waiting for reg %x to come ready.\n", reg);
171         return -ETIMEDOUT;
172 }
173
174 /* The CFG register is used to download TX and RX control blocks
175  * to the chip. This function waits for an operation to complete.
176  */
177 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
178 {
179         int count = UDELAY_COUNT;
180         u32 temp;
181
182         while (count) {
183                 temp = ql_read32(qdev, CFG);
184                 if (temp & CFG_LE)
185                         return -EIO;
186                 if (!(temp & bit))
187                         return 0;
188                 udelay(UDELAY_DELAY);
189                 count--;
190         }
191         return -ETIMEDOUT;
192 }
193
194
195 /* Used to issue init control blocks to hw. Maps control block,
196  * sets address, triggers download, waits for completion.
197  */
198 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
199                  u16 q_id)
200 {
201         u64 map;
202         int status = 0;
203         int direction;
204         u32 mask;
205         u32 value;
206
207         direction =
208             (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
209             PCI_DMA_FROMDEVICE;
210
211         map = pci_map_single(qdev->pdev, ptr, size, direction);
212         if (pci_dma_mapping_error(qdev->pdev, map)) {
213                 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
214                 return -ENOMEM;
215         }
216
217         status = ql_wait_cfg(qdev, bit);
218         if (status) {
219                 QPRINTK(qdev, IFUP, ERR,
220                         "Timed out waiting for CFG to come ready.\n");
221                 goto exit;
222         }
223
224         status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
225         if (status)
226                 goto exit;
227         ql_write32(qdev, ICB_L, (u32) map);
228         ql_write32(qdev, ICB_H, (u32) (map >> 32));
229         ql_sem_unlock(qdev, SEM_ICB_MASK);      /* does flush too */
230
231         mask = CFG_Q_MASK | (bit << 16);
232         value = bit | (q_id << CFG_Q_SHIFT);
233         ql_write32(qdev, CFG, (mask | value));
234
235         /*
236          * Wait for the bit to clear after signaling hw.
237          */
238         status = ql_wait_cfg(qdev, bit);
239 exit:
240         pci_unmap_single(qdev->pdev, map, size, direction);
241         return status;
242 }
243
244 /* Get a specific MAC address from the CAM.  Used for debug and reg dump. */
245 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
246                         u32 *value)
247 {
248         u32 offset = 0;
249         int status;
250
251         switch (type) {
252         case MAC_ADDR_TYPE_MULTI_MAC:
253         case MAC_ADDR_TYPE_CAM_MAC:
254                 {
255                         status =
256                             ql_wait_reg_rdy(qdev,
257                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
258                         if (status)
259                                 goto exit;
260                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
261                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
262                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
263                         status =
264                             ql_wait_reg_rdy(qdev,
265                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
266                         if (status)
267                                 goto exit;
268                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
269                         status =
270                             ql_wait_reg_rdy(qdev,
271                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
272                         if (status)
273                                 goto exit;
274                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
275                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
276                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
277                         status =
278                             ql_wait_reg_rdy(qdev,
279                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
280                         if (status)
281                                 goto exit;
282                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
283                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
284                                 status =
285                                     ql_wait_reg_rdy(qdev,
286                                         MAC_ADDR_IDX, MAC_ADDR_MW, 0);
287                                 if (status)
288                                         goto exit;
289                                 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
290                                            (index << MAC_ADDR_IDX_SHIFT) | /* index */
291                                            MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
292                                 status =
293                                     ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
294                                                     MAC_ADDR_MR, 0);
295                                 if (status)
296                                         goto exit;
297                                 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
298                         }
299                         break;
300                 }
301         case MAC_ADDR_TYPE_VLAN:
302         case MAC_ADDR_TYPE_MULTI_FLTR:
303         default:
304                 QPRINTK(qdev, IFUP, CRIT,
305                         "Address type %d not yet supported.\n", type);
306                 status = -EPERM;
307         }
308 exit:
309         return status;
310 }
311
312 /* Set up a MAC, multicast or VLAN address for the
313  * inbound frame matching.
314  */
315 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
316                                u16 index)
317 {
318         u32 offset = 0;
319         int status = 0;
320
321         switch (type) {
322         case MAC_ADDR_TYPE_MULTI_MAC:
323         case MAC_ADDR_TYPE_CAM_MAC:
324                 {
325                         u32 cam_output;
326                         u32 upper = (addr[0] << 8) | addr[1];
327                         u32 lower =
328                             (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
329                             (addr[5]);
330
331                         QPRINTK(qdev, IFUP, DEBUG,
332                                 "Adding %s address %pM"
333                                 " at index %d in the CAM.\n",
334                                 ((type ==
335                                   MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
336                                  "UNICAST"), addr, index);
337
338                         status =
339                             ql_wait_reg_rdy(qdev,
340                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
341                         if (status)
342                                 goto exit;
343                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
344                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
345                                    type);       /* type */
346                         ql_write32(qdev, MAC_ADDR_DATA, lower);
347                         status =
348                             ql_wait_reg_rdy(qdev,
349                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
350                         if (status)
351                                 goto exit;
352                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
353                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
354                                    type);       /* type */
355                         ql_write32(qdev, MAC_ADDR_DATA, upper);
356                         status =
357                             ql_wait_reg_rdy(qdev,
358                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
359                         if (status)
360                                 goto exit;
361                         ql_write32(qdev, MAC_ADDR_IDX, (offset) |       /* offset */
362                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
363                                    type);       /* type */
364                         /* This field should also include the queue id
365                            and possibly the function id.  Right now we hardcode
366                            the route field to NIC core.
367                          */
368                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
369                                 cam_output = (CAM_OUT_ROUTE_NIC |
370                                               (qdev->
371                                                func << CAM_OUT_FUNC_SHIFT) |
372                                               (qdev->
373                                                rss_ring_first_cq_id <<
374                                                CAM_OUT_CQ_ID_SHIFT));
375                                 if (qdev->vlgrp)
376                                         cam_output |= CAM_OUT_RV;
377                                 /* route to NIC core */
378                                 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
379                         }
380                         break;
381                 }
382         case MAC_ADDR_TYPE_VLAN:
383                 {
384                         u32 enable_bit = *((u32 *) &addr[0]);
385                         /* For VLAN, the addr actually holds a bit that
386                          * either enables or disables the vlan id we are
387                          * addressing. It's either MAC_ADDR_E on or off.
388                          * That's bit-27 we're talking about.
389                          */
390                         QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
391                                 (enable_bit ? "Adding" : "Removing"),
392                                 index, (enable_bit ? "to" : "from"));
393
394                         status =
395                             ql_wait_reg_rdy(qdev,
396                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
397                         if (status)
398                                 goto exit;
399                         ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
400                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
401                                    type |       /* type */
402                                    enable_bit); /* enable/disable */
403                         break;
404                 }
405         case MAC_ADDR_TYPE_MULTI_FLTR:
406         default:
407                 QPRINTK(qdev, IFUP, CRIT,
408                         "Address type %d not yet supported.\n", type);
409                 status = -EPERM;
410         }
411 exit:
412         return status;
413 }
414
415 /* Get a specific frame routing value from the CAM.
416  * Used for debug and reg dump.
417  */
418 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
419 {
420         int status = 0;
421
422         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
423         if (status)
424                 goto exit;
425
426         ql_write32(qdev, RT_IDX,
427                    RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
428         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
429         if (status)
430                 goto exit;
431         *value = ql_read32(qdev, RT_DATA);
432 exit:
433         return status;
434 }
435
436 /* The NIC function for this chip has 16 routing indexes.  Each one can be used
437  * to route different frame types to various inbound queues.  We send broadcast/
438  * multicast/error frames to the default queue for slow handling,
439  * and CAM hit/RSS frames to the fast handling queues.
440  */
441 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
442                               int enable)
443 {
444         int status = -EINVAL; /* Return error if no mask match. */
445         u32 value = 0;
446
447         QPRINTK(qdev, IFUP, DEBUG,
448                 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
449                 (enable ? "Adding" : "Removing"),
450                 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
451                 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
452                 ((index ==
453                   RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
454                 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
455                 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
456                 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
457                 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
458                 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
459                 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
460                 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
461                 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
462                 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
463                 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
464                 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
465                 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
466                 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
467                 (enable ? "to" : "from"));
468
469         switch (mask) {
470         case RT_IDX_CAM_HIT:
471                 {
472                         value = RT_IDX_DST_CAM_Q |      /* dest */
473                             RT_IDX_TYPE_NICQ |  /* type */
474                             (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
475                         break;
476                 }
477         case RT_IDX_VALID:      /* Promiscuous Mode frames. */
478                 {
479                         value = RT_IDX_DST_DFLT_Q |     /* dest */
480                             RT_IDX_TYPE_NICQ |  /* type */
481                             (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
482                         break;
483                 }
484         case RT_IDX_ERR:        /* Pass up MAC,IP,TCP/UDP error frames. */
485                 {
486                         value = RT_IDX_DST_DFLT_Q |     /* dest */
487                             RT_IDX_TYPE_NICQ |  /* type */
488                             (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
489                         break;
490                 }
491         case RT_IDX_BCAST:      /* Pass up Broadcast frames to default Q. */
492                 {
493                         value = RT_IDX_DST_DFLT_Q |     /* dest */
494                             RT_IDX_TYPE_NICQ |  /* type */
495                             (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
496                         break;
497                 }
498         case RT_IDX_MCAST:      /* Pass up All Multicast frames. */
499                 {
500                         value = RT_IDX_DST_CAM_Q |      /* dest */
501                             RT_IDX_TYPE_NICQ |  /* type */
502                             (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
503                         break;
504                 }
505         case RT_IDX_MCAST_MATCH:        /* Pass up matched Multicast frames. */
506                 {
507                         value = RT_IDX_DST_CAM_Q |      /* dest */
508                             RT_IDX_TYPE_NICQ |  /* type */
509                             (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
510                         break;
511                 }
512         case RT_IDX_RSS_MATCH:  /* Pass up matched RSS frames. */
513                 {
514                         value = RT_IDX_DST_RSS |        /* dest */
515                             RT_IDX_TYPE_NICQ |  /* type */
516                             (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
517                         break;
518                 }
519         case 0:         /* Clear the E-bit on an entry. */
520                 {
521                         value = RT_IDX_DST_DFLT_Q |     /* dest */
522                             RT_IDX_TYPE_NICQ |  /* type */
523                             (index << RT_IDX_IDX_SHIFT);/* index */
524                         break;
525                 }
526         default:
527                 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
528                         mask);
529                 status = -EPERM;
530                 goto exit;
531         }
532
533         if (value) {
534                 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
535                 if (status)
536                         goto exit;
537                 value |= (enable ? RT_IDX_E : 0);
538                 ql_write32(qdev, RT_IDX, value);
539                 ql_write32(qdev, RT_DATA, enable ? mask : 0);
540         }
541 exit:
542         return status;
543 }
544
545 static void ql_enable_interrupts(struct ql_adapter *qdev)
546 {
547         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
548 }
549
550 static void ql_disable_interrupts(struct ql_adapter *qdev)
551 {
552         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
553 }
554
555 /* If we're running with multiple MSI-X vectors then we enable on the fly.
556  * Otherwise, we may have multiple outstanding workers and don't want to
557  * enable until the last one finishes. In this case, the irq_cnt gets
558  * incremented everytime we queue a worker and decremented everytime
559  * a worker finishes.  Once it hits zero we enable the interrupt.
560  */
561 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
562 {
563         u32 var = 0;
564         unsigned long hw_flags = 0;
565         struct intr_context *ctx = qdev->intr_context + intr;
566
567         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
568                 /* Always enable if we're MSIX multi interrupts and
569                  * it's not the default (zeroeth) interrupt.
570                  */
571                 ql_write32(qdev, INTR_EN,
572                            ctx->intr_en_mask);
573                 var = ql_read32(qdev, STS);
574                 return var;
575         }
576
577         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
578         if (atomic_dec_and_test(&ctx->irq_cnt)) {
579                 ql_write32(qdev, INTR_EN,
580                            ctx->intr_en_mask);
581                 var = ql_read32(qdev, STS);
582         }
583         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
584         return var;
585 }
586
587 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
588 {
589         u32 var = 0;
590         unsigned long hw_flags;
591         struct intr_context *ctx;
592
593         /* HW disables for us if we're MSIX multi interrupts and
594          * it's not the default (zeroeth) interrupt.
595          */
596         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
597                 return 0;
598
599         ctx = qdev->intr_context + intr;
600         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
601         if (!atomic_read(&ctx->irq_cnt)) {
602                 ql_write32(qdev, INTR_EN,
603                 ctx->intr_dis_mask);
604                 var = ql_read32(qdev, STS);
605         }
606         atomic_inc(&ctx->irq_cnt);
607         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
608         return var;
609 }
610
611 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
612 {
613         int i;
614         for (i = 0; i < qdev->intr_count; i++) {
615                 /* The enable call does a atomic_dec_and_test
616                  * and enables only if the result is zero.
617                  * So we precharge it here.
618                  */
619                 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
620                         i == 0))
621                         atomic_set(&qdev->intr_context[i].irq_cnt, 1);
622                 ql_enable_completion_interrupt(qdev, i);
623         }
624
625 }
626
627 static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str)
628 {
629         int status, i;
630         u16 csum = 0;
631         __le16 *flash = (__le16 *)&qdev->flash;
632
633         status = strncmp((char *)&qdev->flash, str, 4);
634         if (status) {
635                 QPRINTK(qdev, IFUP, ERR, "Invalid flash signature.\n");
636                 return  status;
637         }
638
639         for (i = 0; i < size; i++)
640                 csum += le16_to_cpu(*flash++);
641
642         if (csum)
643                 QPRINTK(qdev, IFUP, ERR,
644                         "Invalid flash checksum, csum = 0x%.04x.\n", csum);
645
646         return csum;
647 }
648
649 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
650 {
651         int status = 0;
652         /* wait for reg to come ready */
653         status = ql_wait_reg_rdy(qdev,
654                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
655         if (status)
656                 goto exit;
657         /* set up for reg read */
658         ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
659         /* wait for reg to come ready */
660         status = ql_wait_reg_rdy(qdev,
661                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
662         if (status)
663                 goto exit;
664          /* This data is stored on flash as an array of
665          * __le32.  Since ql_read32() returns cpu endian
666          * we need to swap it back.
667          */
668         *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
669 exit:
670         return status;
671 }
672
673 static int ql_get_8000_flash_params(struct ql_adapter *qdev)
674 {
675         u32 i, size;
676         int status;
677         __le32 *p = (__le32 *)&qdev->flash;
678         u32 offset;
679
680         /* Get flash offset for function and adjust
681          * for dword access.
682          */
683         if (!qdev->func)
684                 offset = FUNC0_FLASH_OFFSET / sizeof(u32);
685         else
686                 offset = FUNC1_FLASH_OFFSET / sizeof(u32);
687
688         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
689                 return -ETIMEDOUT;
690
691         size = sizeof(struct flash_params_8000) / sizeof(u32);
692         for (i = 0; i < size; i++, p++) {
693                 status = ql_read_flash_word(qdev, i+offset, p);
694                 if (status) {
695                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
696                         goto exit;
697                 }
698         }
699
700         status = ql_validate_flash(qdev,
701                         sizeof(struct flash_params_8000) / sizeof(u16),
702                         "8000");
703         if (status) {
704                 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
705                 status = -EINVAL;
706                 goto exit;
707         }
708
709         if (!is_valid_ether_addr(qdev->flash.flash_params_8000.mac_addr)) {
710                 QPRINTK(qdev, IFUP, ERR, "Invalid MAC address.\n");
711                 status = -EINVAL;
712                 goto exit;
713         }
714
715         memcpy(qdev->ndev->dev_addr,
716                 qdev->flash.flash_params_8000.mac_addr,
717                 qdev->ndev->addr_len);
718
719 exit:
720         ql_sem_unlock(qdev, SEM_FLASH_MASK);
721         return status;
722 }
723
724 static int ql_get_8012_flash_params(struct ql_adapter *qdev)
725 {
726         int i;
727         int status;
728         __le32 *p = (__le32 *)&qdev->flash;
729         u32 offset = 0;
730         u32 size = sizeof(struct flash_params_8012) / sizeof(u32);
731
732         /* Second function's parameters follow the first
733          * function's.
734          */
735         if (qdev->func)
736                 offset = size;
737
738         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
739                 return -ETIMEDOUT;
740
741         for (i = 0; i < size; i++, p++) {
742                 status = ql_read_flash_word(qdev, i+offset, p);
743                 if (status) {
744                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
745                         goto exit;
746                 }
747
748         }
749
750         status = ql_validate_flash(qdev,
751                         sizeof(struct flash_params_8012) / sizeof(u16),
752                         "8012");
753         if (status) {
754                 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
755                 status = -EINVAL;
756                 goto exit;
757         }
758
759         if (!is_valid_ether_addr(qdev->flash.flash_params_8012.mac_addr)) {
760                 status = -EINVAL;
761                 goto exit;
762         }
763
764         memcpy(qdev->ndev->dev_addr,
765                 qdev->flash.flash_params_8012.mac_addr,
766                 qdev->ndev->addr_len);
767
768 exit:
769         ql_sem_unlock(qdev, SEM_FLASH_MASK);
770         return status;
771 }
772
773 /* xgmac register are located behind the xgmac_addr and xgmac_data
774  * register pair.  Each read/write requires us to wait for the ready
775  * bit before reading/writing the data.
776  */
777 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
778 {
779         int status;
780         /* wait for reg to come ready */
781         status = ql_wait_reg_rdy(qdev,
782                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
783         if (status)
784                 return status;
785         /* write the data to the data reg */
786         ql_write32(qdev, XGMAC_DATA, data);
787         /* trigger the write */
788         ql_write32(qdev, XGMAC_ADDR, reg);
789         return status;
790 }
791
792 /* xgmac register are located behind the xgmac_addr and xgmac_data
793  * register pair.  Each read/write requires us to wait for the ready
794  * bit before reading/writing the data.
795  */
796 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
797 {
798         int status = 0;
799         /* wait for reg to come ready */
800         status = ql_wait_reg_rdy(qdev,
801                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
802         if (status)
803                 goto exit;
804         /* set up for reg read */
805         ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
806         /* wait for reg to come ready */
807         status = ql_wait_reg_rdy(qdev,
808                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
809         if (status)
810                 goto exit;
811         /* get the data */
812         *data = ql_read32(qdev, XGMAC_DATA);
813 exit:
814         return status;
815 }
816
817 /* This is used for reading the 64-bit statistics regs. */
818 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
819 {
820         int status = 0;
821         u32 hi = 0;
822         u32 lo = 0;
823
824         status = ql_read_xgmac_reg(qdev, reg, &lo);
825         if (status)
826                 goto exit;
827
828         status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
829         if (status)
830                 goto exit;
831
832         *data = (u64) lo | ((u64) hi << 32);
833
834 exit:
835         return status;
836 }
837
838 static int ql_8000_port_initialize(struct ql_adapter *qdev)
839 {
840         int status;
841         status = ql_mb_get_fw_state(qdev);
842         if (status)
843                 goto exit;
844         /* Wake up a worker to get/set the TX/RX frame sizes. */
845         queue_delayed_work(qdev->workqueue, &qdev->mpi_port_cfg_work, 0);
846 exit:
847         return status;
848 }
849
850 /* Take the MAC Core out of reset.
851  * Enable statistics counting.
852  * Take the transmitter/receiver out of reset.
853  * This functionality may be done in the MPI firmware at a
854  * later date.
855  */
856 static int ql_8012_port_initialize(struct ql_adapter *qdev)
857 {
858         int status = 0;
859         u32 data;
860
861         if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
862                 /* Another function has the semaphore, so
863                  * wait for the port init bit to come ready.
864                  */
865                 QPRINTK(qdev, LINK, INFO,
866                         "Another function has the semaphore, so wait for the port init bit to come ready.\n");
867                 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
868                 if (status) {
869                         QPRINTK(qdev, LINK, CRIT,
870                                 "Port initialize timed out.\n");
871                 }
872                 return status;
873         }
874
875         QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
876         /* Set the core reset. */
877         status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
878         if (status)
879                 goto end;
880         data |= GLOBAL_CFG_RESET;
881         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
882         if (status)
883                 goto end;
884
885         /* Clear the core reset and turn on jumbo for receiver. */
886         data &= ~GLOBAL_CFG_RESET;      /* Clear core reset. */
887         data |= GLOBAL_CFG_JUMBO;       /* Turn on jumbo. */
888         data |= GLOBAL_CFG_TX_STAT_EN;
889         data |= GLOBAL_CFG_RX_STAT_EN;
890         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
891         if (status)
892                 goto end;
893
894         /* Enable transmitter, and clear it's reset. */
895         status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
896         if (status)
897                 goto end;
898         data &= ~TX_CFG_RESET;  /* Clear the TX MAC reset. */
899         data |= TX_CFG_EN;      /* Enable the transmitter. */
900         status = ql_write_xgmac_reg(qdev, TX_CFG, data);
901         if (status)
902                 goto end;
903
904         /* Enable receiver and clear it's reset. */
905         status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
906         if (status)
907                 goto end;
908         data &= ~RX_CFG_RESET;  /* Clear the RX MAC reset. */
909         data |= RX_CFG_EN;      /* Enable the receiver. */
910         status = ql_write_xgmac_reg(qdev, RX_CFG, data);
911         if (status)
912                 goto end;
913
914         /* Turn on jumbo. */
915         status =
916             ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
917         if (status)
918                 goto end;
919         status =
920             ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
921         if (status)
922                 goto end;
923
924         /* Signal to the world that the port is enabled.        */
925         ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
926 end:
927         ql_sem_unlock(qdev, qdev->xg_sem_mask);
928         return status;
929 }
930
931 /* Get the next large buffer. */
932 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
933 {
934         struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
935         rx_ring->lbq_curr_idx++;
936         if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
937                 rx_ring->lbq_curr_idx = 0;
938         rx_ring->lbq_free_cnt++;
939         return lbq_desc;
940 }
941
942 /* Get the next small buffer. */
943 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
944 {
945         struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
946         rx_ring->sbq_curr_idx++;
947         if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
948                 rx_ring->sbq_curr_idx = 0;
949         rx_ring->sbq_free_cnt++;
950         return sbq_desc;
951 }
952
953 /* Update an rx ring index. */
954 static void ql_update_cq(struct rx_ring *rx_ring)
955 {
956         rx_ring->cnsmr_idx++;
957         rx_ring->curr_entry++;
958         if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
959                 rx_ring->cnsmr_idx = 0;
960                 rx_ring->curr_entry = rx_ring->cq_base;
961         }
962 }
963
964 static void ql_write_cq_idx(struct rx_ring *rx_ring)
965 {
966         ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
967 }
968
969 /* Process (refill) a large buffer queue. */
970 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
971 {
972         u32 clean_idx = rx_ring->lbq_clean_idx;
973         u32 start_idx = clean_idx;
974         struct bq_desc *lbq_desc;
975         u64 map;
976         int i;
977
978         while (rx_ring->lbq_free_cnt > 16) {
979                 for (i = 0; i < 16; i++) {
980                         QPRINTK(qdev, RX_STATUS, DEBUG,
981                                 "lbq: try cleaning clean_idx = %d.\n",
982                                 clean_idx);
983                         lbq_desc = &rx_ring->lbq[clean_idx];
984                         if (lbq_desc->p.lbq_page == NULL) {
985                                 QPRINTK(qdev, RX_STATUS, DEBUG,
986                                         "lbq: getting new page for index %d.\n",
987                                         lbq_desc->index);
988                                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
989                                 if (lbq_desc->p.lbq_page == NULL) {
990                                         rx_ring->lbq_clean_idx = clean_idx;
991                                         QPRINTK(qdev, RX_STATUS, ERR,
992                                                 "Couldn't get a page.\n");
993                                         return;
994                                 }
995                                 map = pci_map_page(qdev->pdev,
996                                                    lbq_desc->p.lbq_page,
997                                                    0, PAGE_SIZE,
998                                                    PCI_DMA_FROMDEVICE);
999                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
1000                                         rx_ring->lbq_clean_idx = clean_idx;
1001                                         put_page(lbq_desc->p.lbq_page);
1002                                         lbq_desc->p.lbq_page = NULL;
1003                                         QPRINTK(qdev, RX_STATUS, ERR,
1004                                                 "PCI mapping failed.\n");
1005                                         return;
1006                                 }
1007                                 pci_unmap_addr_set(lbq_desc, mapaddr, map);
1008                                 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
1009                                 *lbq_desc->addr = cpu_to_le64(map);
1010                         }
1011                         clean_idx++;
1012                         if (clean_idx == rx_ring->lbq_len)
1013                                 clean_idx = 0;
1014                 }
1015
1016                 rx_ring->lbq_clean_idx = clean_idx;
1017                 rx_ring->lbq_prod_idx += 16;
1018                 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
1019                         rx_ring->lbq_prod_idx = 0;
1020                 rx_ring->lbq_free_cnt -= 16;
1021         }
1022
1023         if (start_idx != clean_idx) {
1024                 QPRINTK(qdev, RX_STATUS, DEBUG,
1025                         "lbq: updating prod idx = %d.\n",
1026                         rx_ring->lbq_prod_idx);
1027                 ql_write_db_reg(rx_ring->lbq_prod_idx,
1028                                 rx_ring->lbq_prod_idx_db_reg);
1029         }
1030 }
1031
1032 /* Process (refill) a small buffer queue. */
1033 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1034 {
1035         u32 clean_idx = rx_ring->sbq_clean_idx;
1036         u32 start_idx = clean_idx;
1037         struct bq_desc *sbq_desc;
1038         u64 map;
1039         int i;
1040
1041         while (rx_ring->sbq_free_cnt > 16) {
1042                 for (i = 0; i < 16; i++) {
1043                         sbq_desc = &rx_ring->sbq[clean_idx];
1044                         QPRINTK(qdev, RX_STATUS, DEBUG,
1045                                 "sbq: try cleaning clean_idx = %d.\n",
1046                                 clean_idx);
1047                         if (sbq_desc->p.skb == NULL) {
1048                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1049                                         "sbq: getting new skb for index %d.\n",
1050                                         sbq_desc->index);
1051                                 sbq_desc->p.skb =
1052                                     netdev_alloc_skb(qdev->ndev,
1053                                                      rx_ring->sbq_buf_size);
1054                                 if (sbq_desc->p.skb == NULL) {
1055                                         QPRINTK(qdev, PROBE, ERR,
1056                                                 "Couldn't get an skb.\n");
1057                                         rx_ring->sbq_clean_idx = clean_idx;
1058                                         return;
1059                                 }
1060                                 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
1061                                 map = pci_map_single(qdev->pdev,
1062                                                      sbq_desc->p.skb->data,
1063                                                      rx_ring->sbq_buf_size /
1064                                                      2, PCI_DMA_FROMDEVICE);
1065                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
1066                                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
1067                                         rx_ring->sbq_clean_idx = clean_idx;
1068                                         dev_kfree_skb_any(sbq_desc->p.skb);
1069                                         sbq_desc->p.skb = NULL;
1070                                         return;
1071                                 }
1072                                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
1073                                 pci_unmap_len_set(sbq_desc, maplen,
1074                                                   rx_ring->sbq_buf_size / 2);
1075                                 *sbq_desc->addr = cpu_to_le64(map);
1076                         }
1077
1078                         clean_idx++;
1079                         if (clean_idx == rx_ring->sbq_len)
1080                                 clean_idx = 0;
1081                 }
1082                 rx_ring->sbq_clean_idx = clean_idx;
1083                 rx_ring->sbq_prod_idx += 16;
1084                 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
1085                         rx_ring->sbq_prod_idx = 0;
1086                 rx_ring->sbq_free_cnt -= 16;
1087         }
1088
1089         if (start_idx != clean_idx) {
1090                 QPRINTK(qdev, RX_STATUS, DEBUG,
1091                         "sbq: updating prod idx = %d.\n",
1092                         rx_ring->sbq_prod_idx);
1093                 ql_write_db_reg(rx_ring->sbq_prod_idx,
1094                                 rx_ring->sbq_prod_idx_db_reg);
1095         }
1096 }
1097
1098 static void ql_update_buffer_queues(struct ql_adapter *qdev,
1099                                     struct rx_ring *rx_ring)
1100 {
1101         ql_update_sbq(qdev, rx_ring);
1102         ql_update_lbq(qdev, rx_ring);
1103 }
1104
1105 /* Unmaps tx buffers.  Can be called from send() if a pci mapping
1106  * fails at some stage, or from the interrupt when a tx completes.
1107  */
1108 static void ql_unmap_send(struct ql_adapter *qdev,
1109                           struct tx_ring_desc *tx_ring_desc, int mapped)
1110 {
1111         int i;
1112         for (i = 0; i < mapped; i++) {
1113                 if (i == 0 || (i == 7 && mapped > 7)) {
1114                         /*
1115                          * Unmap the skb->data area, or the
1116                          * external sglist (AKA the Outbound
1117                          * Address List (OAL)).
1118                          * If its the zeroeth element, then it's
1119                          * the skb->data area.  If it's the 7th
1120                          * element and there is more than 6 frags,
1121                          * then its an OAL.
1122                          */
1123                         if (i == 7) {
1124                                 QPRINTK(qdev, TX_DONE, DEBUG,
1125                                         "unmapping OAL area.\n");
1126                         }
1127                         pci_unmap_single(qdev->pdev,
1128                                          pci_unmap_addr(&tx_ring_desc->map[i],
1129                                                         mapaddr),
1130                                          pci_unmap_len(&tx_ring_desc->map[i],
1131                                                        maplen),
1132                                          PCI_DMA_TODEVICE);
1133                 } else {
1134                         QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1135                                 i);
1136                         pci_unmap_page(qdev->pdev,
1137                                        pci_unmap_addr(&tx_ring_desc->map[i],
1138                                                       mapaddr),
1139                                        pci_unmap_len(&tx_ring_desc->map[i],
1140                                                      maplen), PCI_DMA_TODEVICE);
1141                 }
1142         }
1143
1144 }
1145
1146 /* Map the buffers for this transmit.  This will return
1147  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1148  */
1149 static int ql_map_send(struct ql_adapter *qdev,
1150                        struct ob_mac_iocb_req *mac_iocb_ptr,
1151                        struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1152 {
1153         int len = skb_headlen(skb);
1154         dma_addr_t map;
1155         int frag_idx, err, map_idx = 0;
1156         struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1157         int frag_cnt = skb_shinfo(skb)->nr_frags;
1158
1159         if (frag_cnt) {
1160                 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1161         }
1162         /*
1163          * Map the skb buffer first.
1164          */
1165         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1166
1167         err = pci_dma_mapping_error(qdev->pdev, map);
1168         if (err) {
1169                 QPRINTK(qdev, TX_QUEUED, ERR,
1170                         "PCI mapping failed with error: %d\n", err);
1171
1172                 return NETDEV_TX_BUSY;
1173         }
1174
1175         tbd->len = cpu_to_le32(len);
1176         tbd->addr = cpu_to_le64(map);
1177         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1178         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1179         map_idx++;
1180
1181         /*
1182          * This loop fills the remainder of the 8 address descriptors
1183          * in the IOCB.  If there are more than 7 fragments, then the
1184          * eighth address desc will point to an external list (OAL).
1185          * When this happens, the remainder of the frags will be stored
1186          * in this list.
1187          */
1188         for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1189                 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1190                 tbd++;
1191                 if (frag_idx == 6 && frag_cnt > 7) {
1192                         /* Let's tack on an sglist.
1193                          * Our control block will now
1194                          * look like this:
1195                          * iocb->seg[0] = skb->data
1196                          * iocb->seg[1] = frag[0]
1197                          * iocb->seg[2] = frag[1]
1198                          * iocb->seg[3] = frag[2]
1199                          * iocb->seg[4] = frag[3]
1200                          * iocb->seg[5] = frag[4]
1201                          * iocb->seg[6] = frag[5]
1202                          * iocb->seg[7] = ptr to OAL (external sglist)
1203                          * oal->seg[0] = frag[6]
1204                          * oal->seg[1] = frag[7]
1205                          * oal->seg[2] = frag[8]
1206                          * oal->seg[3] = frag[9]
1207                          * oal->seg[4] = frag[10]
1208                          *      etc...
1209                          */
1210                         /* Tack on the OAL in the eighth segment of IOCB. */
1211                         map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1212                                              sizeof(struct oal),
1213                                              PCI_DMA_TODEVICE);
1214                         err = pci_dma_mapping_error(qdev->pdev, map);
1215                         if (err) {
1216                                 QPRINTK(qdev, TX_QUEUED, ERR,
1217                                         "PCI mapping outbound address list with error: %d\n",
1218                                         err);
1219                                 goto map_error;
1220                         }
1221
1222                         tbd->addr = cpu_to_le64(map);
1223                         /*
1224                          * The length is the number of fragments
1225                          * that remain to be mapped times the length
1226                          * of our sglist (OAL).
1227                          */
1228                         tbd->len =
1229                             cpu_to_le32((sizeof(struct tx_buf_desc) *
1230                                          (frag_cnt - frag_idx)) | TX_DESC_C);
1231                         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1232                                            map);
1233                         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1234                                           sizeof(struct oal));
1235                         tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1236                         map_idx++;
1237                 }
1238
1239                 map =
1240                     pci_map_page(qdev->pdev, frag->page,
1241                                  frag->page_offset, frag->size,
1242                                  PCI_DMA_TODEVICE);
1243
1244                 err = pci_dma_mapping_error(qdev->pdev, map);
1245                 if (err) {
1246                         QPRINTK(qdev, TX_QUEUED, ERR,
1247                                 "PCI mapping frags failed with error: %d.\n",
1248                                 err);
1249                         goto map_error;
1250                 }
1251
1252                 tbd->addr = cpu_to_le64(map);
1253                 tbd->len = cpu_to_le32(frag->size);
1254                 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1255                 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1256                                   frag->size);
1257
1258         }
1259         /* Save the number of segments we've mapped. */
1260         tx_ring_desc->map_cnt = map_idx;
1261         /* Terminate the last segment. */
1262         tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1263         return NETDEV_TX_OK;
1264
1265 map_error:
1266         /*
1267          * If the first frag mapping failed, then i will be zero.
1268          * This causes the unmap of the skb->data area.  Otherwise
1269          * we pass in the number of frags that mapped successfully
1270          * so they can be umapped.
1271          */
1272         ql_unmap_send(qdev, tx_ring_desc, map_idx);
1273         return NETDEV_TX_BUSY;
1274 }
1275
1276 static void ql_realign_skb(struct sk_buff *skb, int len)
1277 {
1278         void *temp_addr = skb->data;
1279
1280         /* Undo the skb_reserve(skb,32) we did before
1281          * giving to hardware, and realign data on
1282          * a 2-byte boundary.
1283          */
1284         skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1285         skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1286         skb_copy_to_linear_data(skb, temp_addr,
1287                 (unsigned int)len);
1288 }
1289
1290 /*
1291  * This function builds an skb for the given inbound
1292  * completion.  It will be rewritten for readability in the near
1293  * future, but for not it works well.
1294  */
1295 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1296                                        struct rx_ring *rx_ring,
1297                                        struct ib_mac_iocb_rsp *ib_mac_rsp)
1298 {
1299         struct bq_desc *lbq_desc;
1300         struct bq_desc *sbq_desc;
1301         struct sk_buff *skb = NULL;
1302         u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1303        u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1304
1305         /*
1306          * Handle the header buffer if present.
1307          */
1308         if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1309             ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1310                 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1311                 /*
1312                  * Headers fit nicely into a small buffer.
1313                  */
1314                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1315                 pci_unmap_single(qdev->pdev,
1316                                 pci_unmap_addr(sbq_desc, mapaddr),
1317                                 pci_unmap_len(sbq_desc, maplen),
1318                                 PCI_DMA_FROMDEVICE);
1319                 skb = sbq_desc->p.skb;
1320                 ql_realign_skb(skb, hdr_len);
1321                 skb_put(skb, hdr_len);
1322                 sbq_desc->p.skb = NULL;
1323         }
1324
1325         /*
1326          * Handle the data buffer(s).
1327          */
1328         if (unlikely(!length)) {        /* Is there data too? */
1329                 QPRINTK(qdev, RX_STATUS, DEBUG,
1330                         "No Data buffer in this packet.\n");
1331                 return skb;
1332         }
1333
1334         if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1335                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1336                         QPRINTK(qdev, RX_STATUS, DEBUG,
1337                                 "Headers in small, data of %d bytes in small, combine them.\n", length);
1338                         /*
1339                          * Data is less than small buffer size so it's
1340                          * stuffed in a small buffer.
1341                          * For this case we append the data
1342                          * from the "data" small buffer to the "header" small
1343                          * buffer.
1344                          */
1345                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1346                         pci_dma_sync_single_for_cpu(qdev->pdev,
1347                                                     pci_unmap_addr
1348                                                     (sbq_desc, mapaddr),
1349                                                     pci_unmap_len
1350                                                     (sbq_desc, maplen),
1351                                                     PCI_DMA_FROMDEVICE);
1352                         memcpy(skb_put(skb, length),
1353                                sbq_desc->p.skb->data, length);
1354                         pci_dma_sync_single_for_device(qdev->pdev,
1355                                                        pci_unmap_addr
1356                                                        (sbq_desc,
1357                                                         mapaddr),
1358                                                        pci_unmap_len
1359                                                        (sbq_desc,
1360                                                         maplen),
1361                                                        PCI_DMA_FROMDEVICE);
1362                 } else {
1363                         QPRINTK(qdev, RX_STATUS, DEBUG,
1364                                 "%d bytes in a single small buffer.\n", length);
1365                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1366                         skb = sbq_desc->p.skb;
1367                         ql_realign_skb(skb, length);
1368                         skb_put(skb, length);
1369                         pci_unmap_single(qdev->pdev,
1370                                          pci_unmap_addr(sbq_desc,
1371                                                         mapaddr),
1372                                          pci_unmap_len(sbq_desc,
1373                                                        maplen),
1374                                          PCI_DMA_FROMDEVICE);
1375                         sbq_desc->p.skb = NULL;
1376                 }
1377         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1378                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1379                         QPRINTK(qdev, RX_STATUS, DEBUG,
1380                                 "Header in small, %d bytes in large. Chain large to small!\n", length);
1381                         /*
1382                          * The data is in a single large buffer.  We
1383                          * chain it to the header buffer's skb and let
1384                          * it rip.
1385                          */
1386                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1387                         pci_unmap_page(qdev->pdev,
1388                                        pci_unmap_addr(lbq_desc,
1389                                                       mapaddr),
1390                                        pci_unmap_len(lbq_desc, maplen),
1391                                        PCI_DMA_FROMDEVICE);
1392                         QPRINTK(qdev, RX_STATUS, DEBUG,
1393                                 "Chaining page to skb.\n");
1394                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1395                                            0, length);
1396                         skb->len += length;
1397                         skb->data_len += length;
1398                         skb->truesize += length;
1399                         lbq_desc->p.lbq_page = NULL;
1400                 } else {
1401                         /*
1402                          * The headers and data are in a single large buffer. We
1403                          * copy it to a new skb and let it go. This can happen with
1404                          * jumbo mtu on a non-TCP/UDP frame.
1405                          */
1406                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1407                         skb = netdev_alloc_skb(qdev->ndev, length);
1408                         if (skb == NULL) {
1409                                 QPRINTK(qdev, PROBE, DEBUG,
1410                                         "No skb available, drop the packet.\n");
1411                                 return NULL;
1412                         }
1413                         pci_unmap_page(qdev->pdev,
1414                                        pci_unmap_addr(lbq_desc,
1415                                                       mapaddr),
1416                                        pci_unmap_len(lbq_desc, maplen),
1417                                        PCI_DMA_FROMDEVICE);
1418                         skb_reserve(skb, NET_IP_ALIGN);
1419                         QPRINTK(qdev, RX_STATUS, DEBUG,
1420                                 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1421                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1422                                            0, length);
1423                         skb->len += length;
1424                         skb->data_len += length;
1425                         skb->truesize += length;
1426                         length -= length;
1427                         lbq_desc->p.lbq_page = NULL;
1428                         __pskb_pull_tail(skb,
1429                                 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1430                                 VLAN_ETH_HLEN : ETH_HLEN);
1431                 }
1432         } else {
1433                 /*
1434                  * The data is in a chain of large buffers
1435                  * pointed to by a small buffer.  We loop
1436                  * thru and chain them to the our small header
1437                  * buffer's skb.
1438                  * frags:  There are 18 max frags and our small
1439                  *         buffer will hold 32 of them. The thing is,
1440                  *         we'll use 3 max for our 9000 byte jumbo
1441                  *         frames.  If the MTU goes up we could
1442                  *          eventually be in trouble.
1443                  */
1444                 int size, offset, i = 0;
1445                 __le64 *bq, bq_array[8];
1446                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1447                 pci_unmap_single(qdev->pdev,
1448                                  pci_unmap_addr(sbq_desc, mapaddr),
1449                                  pci_unmap_len(sbq_desc, maplen),
1450                                  PCI_DMA_FROMDEVICE);
1451                 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1452                         /*
1453                          * This is an non TCP/UDP IP frame, so
1454                          * the headers aren't split into a small
1455                          * buffer.  We have to use the small buffer
1456                          * that contains our sg list as our skb to
1457                          * send upstairs. Copy the sg list here to
1458                          * a local buffer and use it to find the
1459                          * pages to chain.
1460                          */
1461                         QPRINTK(qdev, RX_STATUS, DEBUG,
1462                                 "%d bytes of headers & data in chain of large.\n", length);
1463                         skb = sbq_desc->p.skb;
1464                         bq = &bq_array[0];
1465                         memcpy(bq, skb->data, sizeof(bq_array));
1466                         sbq_desc->p.skb = NULL;
1467                         skb_reserve(skb, NET_IP_ALIGN);
1468                 } else {
1469                         QPRINTK(qdev, RX_STATUS, DEBUG,
1470                                 "Headers in small, %d bytes of data in chain of large.\n", length);
1471                         bq = (__le64 *)sbq_desc->p.skb->data;
1472                 }
1473                 while (length > 0) {
1474                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1475                         pci_unmap_page(qdev->pdev,
1476                                        pci_unmap_addr(lbq_desc,
1477                                                       mapaddr),
1478                                        pci_unmap_len(lbq_desc,
1479                                                      maplen),
1480                                        PCI_DMA_FROMDEVICE);
1481                         size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1482                         offset = 0;
1483
1484                         QPRINTK(qdev, RX_STATUS, DEBUG,
1485                                 "Adding page %d to skb for %d bytes.\n",
1486                                 i, size);
1487                         skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1488                                            offset, size);
1489                         skb->len += size;
1490                         skb->data_len += size;
1491                         skb->truesize += size;
1492                         length -= size;
1493                         lbq_desc->p.lbq_page = NULL;
1494                         bq++;
1495                         i++;
1496                 }
1497                 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1498                                 VLAN_ETH_HLEN : ETH_HLEN);
1499         }
1500         return skb;
1501 }
1502
1503 /* Process an inbound completion from an rx ring. */
1504 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1505                                    struct rx_ring *rx_ring,
1506                                    struct ib_mac_iocb_rsp *ib_mac_rsp)
1507 {
1508         struct net_device *ndev = qdev->ndev;
1509         struct sk_buff *skb = NULL;
1510         u16 vlan_id = (le16_to_cpu(ib_mac_rsp->vlan_id) &
1511                         IB_MAC_IOCB_RSP_VLAN_MASK)
1512
1513         QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1514
1515         skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1516         if (unlikely(!skb)) {
1517                 QPRINTK(qdev, RX_STATUS, DEBUG,
1518                         "No skb available, drop packet.\n");
1519                 return;
1520         }
1521
1522         prefetch(skb->data);
1523         skb->dev = ndev;
1524         if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1525                 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1526                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1527                         IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1528                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1529                         IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1530                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1531                         IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1532         }
1533         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1534                 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1535         }
1536
1537
1538         skb->protocol = eth_type_trans(skb, ndev);
1539         skb->ip_summed = CHECKSUM_NONE;
1540
1541         /* If rx checksum is on, and there are no
1542          * csum or frame errors.
1543          */
1544         if (qdev->rx_csum &&
1545                 !(ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) &&
1546                 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1547                 /* TCP frame. */
1548                 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1549                         QPRINTK(qdev, RX_STATUS, DEBUG,
1550                                         "TCP checksum done!\n");
1551                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1552                 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1553                                 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1554                 /* Unfragmented ipv4 UDP frame. */
1555                         struct iphdr *iph = (struct iphdr *) skb->data;
1556                         if (!(iph->frag_off &
1557                                 cpu_to_be16(IP_MF|IP_OFFSET))) {
1558                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1559                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1560                                                 "TCP checksum done!\n");
1561                         }
1562                 }
1563         }
1564
1565         qdev->stats.rx_packets++;
1566         qdev->stats.rx_bytes += skb->len;
1567         skb_record_rx_queue(skb,
1568                 rx_ring->cq_id - qdev->rss_ring_first_cq_id);
1569         if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
1570                 if (qdev->vlgrp &&
1571                         (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
1572                         (vlan_id != 0))
1573                         vlan_gro_receive(&rx_ring->napi, qdev->vlgrp,
1574                                 vlan_id, skb);
1575                 else
1576                         napi_gro_receive(&rx_ring->napi, skb);
1577         } else {
1578                 if (qdev->vlgrp &&
1579                         (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
1580                         (vlan_id != 0))
1581                         vlan_hwaccel_receive_skb(skb, qdev->vlgrp, vlan_id);
1582                 else
1583                         netif_receive_skb(skb);
1584         }
1585 }
1586
1587 /* Process an outbound completion from an rx ring. */
1588 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1589                                    struct ob_mac_iocb_rsp *mac_rsp)
1590 {
1591         struct tx_ring *tx_ring;
1592         struct tx_ring_desc *tx_ring_desc;
1593
1594         QL_DUMP_OB_MAC_RSP(mac_rsp);
1595         tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1596         tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1597         ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1598         qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1599         qdev->stats.tx_packets++;
1600         dev_kfree_skb(tx_ring_desc->skb);
1601         tx_ring_desc->skb = NULL;
1602
1603         if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1604                                         OB_MAC_IOCB_RSP_S |
1605                                         OB_MAC_IOCB_RSP_L |
1606                                         OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1607                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1608                         QPRINTK(qdev, TX_DONE, WARNING,
1609                                 "Total descriptor length did not match transfer length.\n");
1610                 }
1611                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1612                         QPRINTK(qdev, TX_DONE, WARNING,
1613                                 "Frame too short to be legal, not sent.\n");
1614                 }
1615                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1616                         QPRINTK(qdev, TX_DONE, WARNING,
1617                                 "Frame too long, but sent anyway.\n");
1618                 }
1619                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1620                         QPRINTK(qdev, TX_DONE, WARNING,
1621                                 "PCI backplane error. Frame not sent.\n");
1622                 }
1623         }
1624         atomic_inc(&tx_ring->tx_count);
1625 }
1626
1627 /* Fire up a handler to reset the MPI processor. */
1628 void ql_queue_fw_error(struct ql_adapter *qdev)
1629 {
1630         netif_carrier_off(qdev->ndev);
1631         queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1632 }
1633
1634 void ql_queue_asic_error(struct ql_adapter *qdev)
1635 {
1636         netif_carrier_off(qdev->ndev);
1637         ql_disable_interrupts(qdev);
1638         /* Clear adapter up bit to signal the recovery
1639          * process that it shouldn't kill the reset worker
1640          * thread
1641          */
1642         clear_bit(QL_ADAPTER_UP, &qdev->flags);
1643         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1644 }
1645
1646 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1647                                     struct ib_ae_iocb_rsp *ib_ae_rsp)
1648 {
1649         switch (ib_ae_rsp->event) {
1650         case MGMT_ERR_EVENT:
1651                 QPRINTK(qdev, RX_ERR, ERR,
1652                         "Management Processor Fatal Error.\n");
1653                 ql_queue_fw_error(qdev);
1654                 return;
1655
1656         case CAM_LOOKUP_ERR_EVENT:
1657                 QPRINTK(qdev, LINK, ERR,
1658                         "Multiple CAM hits lookup occurred.\n");
1659                 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1660                 ql_queue_asic_error(qdev);
1661                 return;
1662
1663         case SOFT_ECC_ERROR_EVENT:
1664                 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1665                 ql_queue_asic_error(qdev);
1666                 break;
1667
1668         case PCI_ERR_ANON_BUF_RD:
1669                 QPRINTK(qdev, RX_ERR, ERR,
1670                         "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1671                         ib_ae_rsp->q_id);
1672                 ql_queue_asic_error(qdev);
1673                 break;
1674
1675         default:
1676                 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1677                         ib_ae_rsp->event);
1678                 ql_queue_asic_error(qdev);
1679                 break;
1680         }
1681 }
1682
1683 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1684 {
1685         struct ql_adapter *qdev = rx_ring->qdev;
1686         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1687         struct ob_mac_iocb_rsp *net_rsp = NULL;
1688         int count = 0;
1689
1690         struct tx_ring *tx_ring;
1691         /* While there are entries in the completion queue. */
1692         while (prod != rx_ring->cnsmr_idx) {
1693
1694                 QPRINTK(qdev, RX_STATUS, DEBUG,
1695                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1696                         prod, rx_ring->cnsmr_idx);
1697
1698                 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1699                 rmb();
1700                 switch (net_rsp->opcode) {
1701
1702                 case OPCODE_OB_MAC_TSO_IOCB:
1703                 case OPCODE_OB_MAC_IOCB:
1704                         ql_process_mac_tx_intr(qdev, net_rsp);
1705                         break;
1706                 default:
1707                         QPRINTK(qdev, RX_STATUS, DEBUG,
1708                                 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1709                                 net_rsp->opcode);
1710                 }
1711                 count++;
1712                 ql_update_cq(rx_ring);
1713                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1714         }
1715         ql_write_cq_idx(rx_ring);
1716         tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1717         if (__netif_subqueue_stopped(qdev->ndev, tx_ring->wq_id) &&
1718                                         net_rsp != NULL) {
1719                 if (atomic_read(&tx_ring->queue_stopped) &&
1720                     (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1721                         /*
1722                          * The queue got stopped because the tx_ring was full.
1723                          * Wake it up, because it's now at least 25% empty.
1724                          */
1725                         netif_wake_subqueue(qdev->ndev, tx_ring->wq_id);
1726         }
1727
1728         return count;
1729 }
1730
1731 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1732 {
1733         struct ql_adapter *qdev = rx_ring->qdev;
1734         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1735         struct ql_net_rsp_iocb *net_rsp;
1736         int count = 0;
1737
1738         /* While there are entries in the completion queue. */
1739         while (prod != rx_ring->cnsmr_idx) {
1740
1741                 QPRINTK(qdev, RX_STATUS, DEBUG,
1742                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1743                         prod, rx_ring->cnsmr_idx);
1744
1745                 net_rsp = rx_ring->curr_entry;
1746                 rmb();
1747                 switch (net_rsp->opcode) {
1748                 case OPCODE_IB_MAC_IOCB:
1749                         ql_process_mac_rx_intr(qdev, rx_ring,
1750                                                (struct ib_mac_iocb_rsp *)
1751                                                net_rsp);
1752                         break;
1753
1754                 case OPCODE_IB_AE_IOCB:
1755                         ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1756                                                 net_rsp);
1757                         break;
1758                 default:
1759                         {
1760                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1761                                         "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1762                                         net_rsp->opcode);
1763                         }
1764                 }
1765                 count++;
1766                 ql_update_cq(rx_ring);
1767                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1768                 if (count == budget)
1769                         break;
1770         }
1771         ql_update_buffer_queues(qdev, rx_ring);
1772         ql_write_cq_idx(rx_ring);
1773         return count;
1774 }
1775
1776 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1777 {
1778         struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1779         struct ql_adapter *qdev = rx_ring->qdev;
1780         int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1781
1782         QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1783                 rx_ring->cq_id);
1784
1785         if (work_done < budget) {
1786                 napi_complete(napi);
1787                 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1788         }
1789         return work_done;
1790 }
1791
1792 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1793 {
1794         struct ql_adapter *qdev = netdev_priv(ndev);
1795
1796         qdev->vlgrp = grp;
1797         if (grp) {
1798                 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1799                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1800                            NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1801         } else {
1802                 QPRINTK(qdev, IFUP, DEBUG,
1803                         "Turning off VLAN in NIC_RCV_CFG.\n");
1804                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1805         }
1806 }
1807
1808 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1809 {
1810         struct ql_adapter *qdev = netdev_priv(ndev);
1811         u32 enable_bit = MAC_ADDR_E;
1812         int status;
1813
1814         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1815         if (status)
1816                 return;
1817         spin_lock(&qdev->hw_lock);
1818         if (ql_set_mac_addr_reg
1819             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1820                 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1821         }
1822         spin_unlock(&qdev->hw_lock);
1823         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1824 }
1825
1826 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1827 {
1828         struct ql_adapter *qdev = netdev_priv(ndev);
1829         u32 enable_bit = 0;
1830         int status;
1831
1832         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1833         if (status)
1834                 return;
1835
1836         spin_lock(&qdev->hw_lock);
1837         if (ql_set_mac_addr_reg
1838             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1839                 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1840         }
1841         spin_unlock(&qdev->hw_lock);
1842         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1843
1844 }
1845
1846 /* Worker thread to process a given rx_ring that is dedicated
1847  * to outbound completions.
1848  */
1849 static void ql_tx_clean(struct work_struct *work)
1850 {
1851         struct rx_ring *rx_ring =
1852             container_of(work, struct rx_ring, rx_work.work);
1853         ql_clean_outbound_rx_ring(rx_ring);
1854         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1855
1856 }
1857
1858 /* Worker thread to process a given rx_ring that is dedicated
1859  * to inbound completions.
1860  */
1861 static void ql_rx_clean(struct work_struct *work)
1862 {
1863         struct rx_ring *rx_ring =
1864             container_of(work, struct rx_ring, rx_work.work);
1865         ql_clean_inbound_rx_ring(rx_ring, 64);
1866         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1867 }
1868
1869 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1870 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1871 {
1872         struct rx_ring *rx_ring = dev_id;
1873         queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1874                               &rx_ring->rx_work, 0);
1875         return IRQ_HANDLED;
1876 }
1877
1878 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1879 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1880 {
1881         struct rx_ring *rx_ring = dev_id;
1882         napi_schedule(&rx_ring->napi);
1883         return IRQ_HANDLED;
1884 }
1885
1886 /* This handles a fatal error, MPI activity, and the default
1887  * rx_ring in an MSI-X multiple vector environment.
1888  * In MSI/Legacy environment it also process the rest of
1889  * the rx_rings.
1890  */
1891 static irqreturn_t qlge_isr(int irq, void *dev_id)
1892 {
1893         struct rx_ring *rx_ring = dev_id;
1894         struct ql_adapter *qdev = rx_ring->qdev;
1895         struct intr_context *intr_context = &qdev->intr_context[0];
1896         u32 var;
1897         int i;
1898         int work_done = 0;
1899
1900         spin_lock(&qdev->hw_lock);
1901         if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1902                 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1903                 spin_unlock(&qdev->hw_lock);
1904                 return IRQ_NONE;
1905         }
1906         spin_unlock(&qdev->hw_lock);
1907
1908         var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1909
1910         /*
1911          * Check for fatal error.
1912          */
1913         if (var & STS_FE) {
1914                 ql_queue_asic_error(qdev);
1915                 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1916                 var = ql_read32(qdev, ERR_STS);
1917                 QPRINTK(qdev, INTR, ERR,
1918                         "Resetting chip. Error Status Register = 0x%x\n", var);
1919                 return IRQ_HANDLED;
1920         }
1921
1922         /*
1923          * Check MPI processor activity.
1924          */
1925         if (var & STS_PI) {
1926                 /*
1927                  * We've got an async event or mailbox completion.
1928                  * Handle it and clear the source of the interrupt.
1929                  */
1930                 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1931                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1932                 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1933                                       &qdev->mpi_work, 0);
1934                 work_done++;
1935         }
1936
1937         /*
1938          * Check the default queue and wake handler if active.
1939          */
1940         rx_ring = &qdev->rx_ring[0];
1941         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1942                 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1943                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1944                 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1945                                       &rx_ring->rx_work, 0);
1946                 work_done++;
1947         }
1948
1949         if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1950                 /*
1951                  * Start the DPC for each active queue.
1952                  */
1953                 for (i = 1; i < qdev->rx_ring_count; i++) {
1954                         rx_ring = &qdev->rx_ring[i];
1955                         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1956                             rx_ring->cnsmr_idx) {
1957                                 QPRINTK(qdev, INTR, INFO,
1958                                         "Waking handler for rx_ring[%d].\n", i);
1959                                 ql_disable_completion_interrupt(qdev,
1960                                                                 intr_context->
1961                                                                 intr);
1962                                 if (i < qdev->rss_ring_first_cq_id)
1963                                         queue_delayed_work_on(rx_ring->cpu,
1964                                                               qdev->q_workqueue,
1965                                                               &rx_ring->rx_work,
1966                                                               0);
1967                                 else
1968                                         napi_schedule(&rx_ring->napi);
1969                                 work_done++;
1970                         }
1971                 }
1972         }
1973         ql_enable_completion_interrupt(qdev, intr_context->intr);
1974         return work_done ? IRQ_HANDLED : IRQ_NONE;
1975 }
1976
1977 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1978 {
1979
1980         if (skb_is_gso(skb)) {
1981                 int err;
1982                 if (skb_header_cloned(skb)) {
1983                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1984                         if (err)
1985                                 return err;
1986                 }
1987
1988                 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1989                 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1990                 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1991                 mac_iocb_ptr->total_hdrs_len =
1992                     cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1993                 mac_iocb_ptr->net_trans_offset =
1994                     cpu_to_le16(skb_network_offset(skb) |
1995                                 skb_transport_offset(skb)
1996                                 << OB_MAC_TRANSPORT_HDR_SHIFT);
1997                 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1998                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1999                 if (likely(skb->protocol == htons(ETH_P_IP))) {
2000                         struct iphdr *iph = ip_hdr(skb);
2001                         iph->check = 0;
2002                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2003                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2004                                                                  iph->daddr, 0,
2005                                                                  IPPROTO_TCP,
2006                                                                  0);
2007                 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2008                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
2009                         tcp_hdr(skb)->check =
2010                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2011                                              &ipv6_hdr(skb)->daddr,
2012                                              0, IPPROTO_TCP, 0);
2013                 }
2014                 return 1;
2015         }
2016         return 0;
2017 }
2018
2019 static void ql_hw_csum_setup(struct sk_buff *skb,
2020                              struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2021 {
2022         int len;
2023         struct iphdr *iph = ip_hdr(skb);
2024         __sum16 *check;
2025         mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2026         mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2027         mac_iocb_ptr->net_trans_offset =
2028                 cpu_to_le16(skb_network_offset(skb) |
2029                 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
2030
2031         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2032         len = (ntohs(iph->tot_len) - (iph->ihl << 2));
2033         if (likely(iph->protocol == IPPROTO_TCP)) {
2034                 check = &(tcp_hdr(skb)->check);
2035                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
2036                 mac_iocb_ptr->total_hdrs_len =
2037                     cpu_to_le16(skb_transport_offset(skb) +
2038                                 (tcp_hdr(skb)->doff << 2));
2039         } else {
2040                 check = &(udp_hdr(skb)->check);
2041                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
2042                 mac_iocb_ptr->total_hdrs_len =
2043                     cpu_to_le16(skb_transport_offset(skb) +
2044                                 sizeof(struct udphdr));
2045         }
2046         *check = ~csum_tcpudp_magic(iph->saddr,
2047                                     iph->daddr, len, iph->protocol, 0);
2048 }
2049
2050 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
2051 {
2052         struct tx_ring_desc *tx_ring_desc;
2053         struct ob_mac_iocb_req *mac_iocb_ptr;
2054         struct ql_adapter *qdev = netdev_priv(ndev);
2055         int tso;
2056         struct tx_ring *tx_ring;
2057         u32 tx_ring_idx = (u32) skb->queue_mapping;
2058
2059         tx_ring = &qdev->tx_ring[tx_ring_idx];
2060
2061         if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
2062                 QPRINTK(qdev, TX_QUEUED, INFO,
2063                         "%s: shutting down tx queue %d du to lack of resources.\n",
2064                         __func__, tx_ring_idx);
2065                 netif_stop_subqueue(ndev, tx_ring->wq_id);
2066                 atomic_inc(&tx_ring->queue_stopped);
2067                 return NETDEV_TX_BUSY;
2068         }
2069         tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
2070         mac_iocb_ptr = tx_ring_desc->queue_entry;
2071         memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
2072
2073         mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
2074         mac_iocb_ptr->tid = tx_ring_desc->index;
2075         /* We use the upper 32-bits to store the tx queue for this IO.
2076          * When we get the completion we can use it to establish the context.
2077          */
2078         mac_iocb_ptr->txq_idx = tx_ring_idx;
2079         tx_ring_desc->skb = skb;
2080
2081         mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
2082
2083         if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
2084                 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
2085                         vlan_tx_tag_get(skb));
2086                 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
2087                 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
2088         }
2089         tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2090         if (tso < 0) {
2091                 dev_kfree_skb_any(skb);
2092                 return NETDEV_TX_OK;
2093         } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
2094                 ql_hw_csum_setup(skb,
2095                                  (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2096         }
2097         if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
2098                         NETDEV_TX_OK) {
2099                 QPRINTK(qdev, TX_QUEUED, ERR,
2100                                 "Could not map the segments.\n");
2101                 return NETDEV_TX_BUSY;
2102         }
2103         QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
2104         tx_ring->prod_idx++;
2105         if (tx_ring->prod_idx == tx_ring->wq_len)
2106                 tx_ring->prod_idx = 0;
2107         wmb();
2108
2109         ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
2110         ndev->trans_start = jiffies;
2111         QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
2112                 tx_ring->prod_idx, skb->len);
2113
2114         atomic_dec(&tx_ring->tx_count);
2115         return NETDEV_TX_OK;
2116 }
2117
2118 static void ql_free_shadow_space(struct ql_adapter *qdev)
2119 {
2120         if (qdev->rx_ring_shadow_reg_area) {
2121                 pci_free_consistent(qdev->pdev,
2122                                     PAGE_SIZE,
2123                                     qdev->rx_ring_shadow_reg_area,
2124                                     qdev->rx_ring_shadow_reg_dma);
2125                 qdev->rx_ring_shadow_reg_area = NULL;
2126         }
2127         if (qdev->tx_ring_shadow_reg_area) {
2128                 pci_free_consistent(qdev->pdev,
2129                                     PAGE_SIZE,
2130                                     qdev->tx_ring_shadow_reg_area,
2131                                     qdev->tx_ring_shadow_reg_dma);
2132                 qdev->tx_ring_shadow_reg_area = NULL;
2133         }
2134 }
2135
2136 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2137 {
2138         qdev->rx_ring_shadow_reg_area =
2139             pci_alloc_consistent(qdev->pdev,
2140                                  PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2141         if (qdev->rx_ring_shadow_reg_area == NULL) {
2142                 QPRINTK(qdev, IFUP, ERR,
2143                         "Allocation of RX shadow space failed.\n");
2144                 return -ENOMEM;
2145         }
2146         qdev->tx_ring_shadow_reg_area =
2147             pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2148                                  &qdev->tx_ring_shadow_reg_dma);
2149         if (qdev->tx_ring_shadow_reg_area == NULL) {
2150                 QPRINTK(qdev, IFUP, ERR,
2151                         "Allocation of TX shadow space failed.\n");
2152                 goto err_wqp_sh_area;
2153         }
2154         return 0;
2155
2156 err_wqp_sh_area:
2157         pci_free_consistent(qdev->pdev,
2158                             PAGE_SIZE,
2159                             qdev->rx_ring_shadow_reg_area,
2160                             qdev->rx_ring_shadow_reg_dma);
2161         return -ENOMEM;
2162 }
2163
2164 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2165 {
2166         struct tx_ring_desc *tx_ring_desc;
2167         int i;
2168         struct ob_mac_iocb_req *mac_iocb_ptr;
2169
2170         mac_iocb_ptr = tx_ring->wq_base;
2171         tx_ring_desc = tx_ring->q;
2172         for (i = 0; i < tx_ring->wq_len; i++) {
2173                 tx_ring_desc->index = i;
2174                 tx_ring_desc->skb = NULL;
2175                 tx_ring_desc->queue_entry = mac_iocb_ptr;
2176                 mac_iocb_ptr++;
2177                 tx_ring_desc++;
2178         }
2179         atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2180         atomic_set(&tx_ring->queue_stopped, 0);
2181 }
2182
2183 static void ql_free_tx_resources(struct ql_adapter *qdev,
2184                                  struct tx_ring *tx_ring)
2185 {
2186         if (tx_ring->wq_base) {
2187                 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2188                                     tx_ring->wq_base, tx_ring->wq_base_dma);
2189                 tx_ring->wq_base = NULL;
2190         }
2191         kfree(tx_ring->q);
2192         tx_ring->q = NULL;
2193 }
2194
2195 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2196                                  struct tx_ring *tx_ring)
2197 {
2198         tx_ring->wq_base =
2199             pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2200                                  &tx_ring->wq_base_dma);
2201
2202         if ((tx_ring->wq_base == NULL)
2203             || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2204                 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2205                 return -ENOMEM;
2206         }
2207         tx_ring->q =
2208             kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2209         if (tx_ring->q == NULL)
2210                 goto err;
2211
2212         return 0;
2213 err:
2214         pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2215                             tx_ring->wq_base, tx_ring->wq_base_dma);
2216         return -ENOMEM;
2217 }
2218
2219 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2220 {
2221         int i;
2222         struct bq_desc *lbq_desc;
2223
2224         for (i = 0; i < rx_ring->lbq_len; i++) {
2225                 lbq_desc = &rx_ring->lbq[i];
2226                 if (lbq_desc->p.lbq_page) {
2227                         pci_unmap_page(qdev->pdev,
2228                                        pci_unmap_addr(lbq_desc, mapaddr),
2229                                        pci_unmap_len(lbq_desc, maplen),
2230                                        PCI_DMA_FROMDEVICE);
2231
2232                         put_page(lbq_desc->p.lbq_page);
2233                         lbq_desc->p.lbq_page = NULL;
2234                 }
2235         }
2236 }
2237
2238 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2239 {
2240         int i;
2241         struct bq_desc *sbq_desc;
2242
2243         for (i = 0; i < rx_ring->sbq_len; i++) {
2244                 sbq_desc = &rx_ring->sbq[i];
2245                 if (sbq_desc == NULL) {
2246                         QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2247                         return;
2248                 }
2249                 if (sbq_desc->p.skb) {
2250                         pci_unmap_single(qdev->pdev,
2251                                          pci_unmap_addr(sbq_desc, mapaddr),
2252                                          pci_unmap_len(sbq_desc, maplen),
2253                                          PCI_DMA_FROMDEVICE);
2254                         dev_kfree_skb(sbq_desc->p.skb);
2255                         sbq_desc->p.skb = NULL;
2256                 }
2257         }
2258 }
2259
2260 /* Free all large and small rx buffers associated
2261  * with the completion queues for this device.
2262  */
2263 static void ql_free_rx_buffers(struct ql_adapter *qdev)
2264 {
2265         int i;
2266         struct rx_ring *rx_ring;
2267
2268         for (i = 0; i < qdev->rx_ring_count; i++) {
2269                 rx_ring = &qdev->rx_ring[i];
2270                 if (rx_ring->lbq)
2271                         ql_free_lbq_buffers(qdev, rx_ring);
2272                 if (rx_ring->sbq)
2273                         ql_free_sbq_buffers(qdev, rx_ring);
2274         }
2275 }
2276
2277 static void ql_alloc_rx_buffers(struct ql_adapter *qdev)
2278 {
2279         struct rx_ring *rx_ring;
2280         int i;
2281
2282         for (i = 0; i < qdev->rx_ring_count; i++) {
2283                 rx_ring = &qdev->rx_ring[i];
2284                 if (rx_ring->type != TX_Q)
2285                         ql_update_buffer_queues(qdev, rx_ring);
2286         }
2287 }
2288
2289 static void ql_init_lbq_ring(struct ql_adapter *qdev,
2290                                 struct rx_ring *rx_ring)
2291 {
2292         int i;
2293         struct bq_desc *lbq_desc;
2294         __le64 *bq = rx_ring->lbq_base;
2295
2296         memset(rx_ring->lbq, 0, rx_ring->lbq_len * sizeof(struct bq_desc));
2297         for (i = 0; i < rx_ring->lbq_len; i++) {
2298                 lbq_desc = &rx_ring->lbq[i];
2299                 memset(lbq_desc, 0, sizeof(*lbq_desc));
2300                 lbq_desc->index = i;
2301                 lbq_desc->addr = bq;
2302                 bq++;
2303         }
2304 }
2305
2306 static void ql_init_sbq_ring(struct ql_adapter *qdev,
2307                                 struct rx_ring *rx_ring)
2308 {
2309         int i;
2310         struct bq_desc *sbq_desc;
2311         __le64 *bq = rx_ring->sbq_base;
2312
2313         memset(rx_ring->sbq, 0, rx_ring->sbq_len * sizeof(struct bq_desc));
2314         for (i = 0; i < rx_ring->sbq_len; i++) {
2315                 sbq_desc = &rx_ring->sbq[i];
2316                 memset(sbq_desc, 0, sizeof(*sbq_desc));
2317                 sbq_desc->index = i;
2318                 sbq_desc->addr = bq;
2319                 bq++;
2320         }
2321 }
2322
2323 static void ql_free_rx_resources(struct ql_adapter *qdev,
2324                                  struct rx_ring *rx_ring)
2325 {
2326         /* Free the small buffer queue. */
2327         if (rx_ring->sbq_base) {
2328                 pci_free_consistent(qdev->pdev,
2329                                     rx_ring->sbq_size,
2330                                     rx_ring->sbq_base, rx_ring->sbq_base_dma);
2331                 rx_ring->sbq_base = NULL;
2332         }
2333
2334         /* Free the small buffer queue control blocks. */
2335         kfree(rx_ring->sbq);
2336         rx_ring->sbq = NULL;
2337
2338         /* Free the large buffer queue. */
2339         if (rx_ring->lbq_base) {
2340                 pci_free_consistent(qdev->pdev,
2341                                     rx_ring->lbq_size,
2342                                     rx_ring->lbq_base, rx_ring->lbq_base_dma);
2343                 rx_ring->lbq_base = NULL;
2344         }
2345
2346         /* Free the large buffer queue control blocks. */
2347         kfree(rx_ring->lbq);
2348         rx_ring->lbq = NULL;
2349
2350         /* Free the rx queue. */
2351         if (rx_ring->cq_base) {
2352                 pci_free_consistent(qdev->pdev,
2353                                     rx_ring->cq_size,
2354                                     rx_ring->cq_base, rx_ring->cq_base_dma);
2355                 rx_ring->cq_base = NULL;
2356         }
2357 }
2358
2359 /* Allocate queues and buffers for this completions queue based
2360  * on the values in the parameter structure. */
2361 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2362                                  struct rx_ring *rx_ring)
2363 {
2364
2365         /*
2366          * Allocate the completion queue for this rx_ring.
2367          */
2368         rx_ring->cq_base =
2369             pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2370                                  &rx_ring->cq_base_dma);
2371
2372         if (rx_ring->cq_base == NULL) {
2373                 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2374                 return -ENOMEM;
2375         }
2376
2377         if (rx_ring->sbq_len) {
2378                 /*
2379                  * Allocate small buffer queue.
2380                  */
2381                 rx_ring->sbq_base =
2382                     pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2383                                          &rx_ring->sbq_base_dma);
2384
2385                 if (rx_ring->sbq_base == NULL) {
2386                         QPRINTK(qdev, IFUP, ERR,
2387                                 "Small buffer queue allocation failed.\n");
2388                         goto err_mem;
2389                 }
2390
2391                 /*
2392                  * Allocate small buffer queue control blocks.
2393                  */
2394                 rx_ring->sbq =
2395                     kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2396                             GFP_KERNEL);
2397                 if (rx_ring->sbq == NULL) {
2398                         QPRINTK(qdev, IFUP, ERR,
2399                                 "Small buffer queue control block allocation failed.\n");
2400                         goto err_mem;
2401                 }
2402
2403                 ql_init_sbq_ring(qdev, rx_ring);
2404         }
2405
2406         if (rx_ring->lbq_len) {
2407                 /*
2408                  * Allocate large buffer queue.
2409                  */
2410                 rx_ring->lbq_base =
2411                     pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2412                                          &rx_ring->lbq_base_dma);
2413
2414                 if (rx_ring->lbq_base == NULL) {
2415                         QPRINTK(qdev, IFUP, ERR,
2416                                 "Large buffer queue allocation failed.\n");
2417                         goto err_mem;
2418                 }
2419                 /*
2420                  * Allocate large buffer queue control blocks.
2421                  */
2422                 rx_ring->lbq =
2423                     kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2424                             GFP_KERNEL);
2425                 if (rx_ring->lbq == NULL) {
2426                         QPRINTK(qdev, IFUP, ERR,
2427                                 "Large buffer queue control block allocation failed.\n");
2428                         goto err_mem;
2429                 }
2430
2431                 ql_init_lbq_ring(qdev, rx_ring);
2432         }
2433
2434         return 0;
2435
2436 err_mem:
2437         ql_free_rx_resources(qdev, rx_ring);
2438         return -ENOMEM;
2439 }
2440
2441 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2442 {
2443         struct tx_ring *tx_ring;
2444         struct tx_ring_desc *tx_ring_desc;
2445         int i, j;
2446
2447         /*
2448          * Loop through all queues and free
2449          * any resources.
2450          */
2451         for (j = 0; j < qdev->tx_ring_count; j++) {
2452                 tx_ring = &qdev->tx_ring[j];
2453                 for (i = 0; i < tx_ring->wq_len; i++) {
2454                         tx_ring_desc = &tx_ring->q[i];
2455                         if (tx_ring_desc && tx_ring_desc->skb) {
2456                                 QPRINTK(qdev, IFDOWN, ERR,
2457                                 "Freeing lost SKB %p, from queue %d, index %d.\n",
2458                                         tx_ring_desc->skb, j,
2459                                         tx_ring_desc->index);
2460                                 ql_unmap_send(qdev, tx_ring_desc,
2461                                               tx_ring_desc->map_cnt);
2462                                 dev_kfree_skb(tx_ring_desc->skb);
2463                                 tx_ring_desc->skb = NULL;
2464                         }
2465                 }
2466         }
2467 }
2468
2469 static void ql_free_mem_resources(struct ql_adapter *qdev)
2470 {
2471         int i;
2472
2473         for (i = 0; i < qdev->tx_ring_count; i++)
2474                 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2475         for (i = 0; i < qdev->rx_ring_count; i++)
2476                 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2477         ql_free_shadow_space(qdev);
2478 }
2479
2480 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2481 {
2482         int i;
2483
2484         /* Allocate space for our shadow registers and such. */
2485         if (ql_alloc_shadow_space(qdev))
2486                 return -ENOMEM;
2487
2488         for (i = 0; i < qdev->rx_ring_count; i++) {
2489                 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2490                         QPRINTK(qdev, IFUP, ERR,
2491                                 "RX resource allocation failed.\n");
2492                         goto err_mem;
2493                 }
2494         }
2495         /* Allocate tx queue resources */
2496         for (i = 0; i < qdev->tx_ring_count; i++) {
2497                 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2498                         QPRINTK(qdev, IFUP, ERR,
2499                                 "TX resource allocation failed.\n");
2500                         goto err_mem;
2501                 }
2502         }
2503         return 0;
2504
2505 err_mem:
2506         ql_free_mem_resources(qdev);
2507         return -ENOMEM;
2508 }
2509
2510 /* Set up the rx ring control block and pass it to the chip.
2511  * The control block is defined as
2512  * "Completion Queue Initialization Control Block", or cqicb.
2513  */
2514 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2515 {
2516         struct cqicb *cqicb = &rx_ring->cqicb;
2517         void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2518             (rx_ring->cq_id * sizeof(u64) * 4);
2519         u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2520             (rx_ring->cq_id * sizeof(u64) * 4);
2521         void __iomem *doorbell_area =
2522             qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2523         int err = 0;
2524         u16 bq_len;
2525
2526         /* Set up the shadow registers for this ring. */
2527         rx_ring->prod_idx_sh_reg = shadow_reg;
2528         rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2529         shadow_reg += sizeof(u64);
2530         shadow_reg_dma += sizeof(u64);
2531         rx_ring->lbq_base_indirect = shadow_reg;
2532         rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2533         shadow_reg += sizeof(u64);
2534         shadow_reg_dma += sizeof(u64);
2535         rx_ring->sbq_base_indirect = shadow_reg;
2536         rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2537
2538         /* PCI doorbell mem area + 0x00 for consumer index register */
2539         rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2540         rx_ring->cnsmr_idx = 0;
2541         rx_ring->curr_entry = rx_ring->cq_base;
2542
2543         /* PCI doorbell mem area + 0x04 for valid register */
2544         rx_ring->valid_db_reg = doorbell_area + 0x04;
2545
2546         /* PCI doorbell mem area + 0x18 for large buffer consumer */
2547         rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2548
2549         /* PCI doorbell mem area + 0x1c */
2550         rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2551
2552         memset((void *)cqicb, 0, sizeof(struct cqicb));
2553         cqicb->msix_vect = rx_ring->irq;
2554
2555         bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2556         cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
2557
2558         cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
2559
2560         cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
2561
2562         /*
2563          * Set up the control block load flags.
2564          */
2565         cqicb->flags = FLAGS_LC |       /* Load queue base address */
2566             FLAGS_LV |          /* Load MSI-X vector */
2567             FLAGS_LI;           /* Load irq delay values */
2568         if (rx_ring->lbq_len) {
2569                 cqicb->flags |= FLAGS_LL;       /* Load lbq values */
2570                 *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma;
2571                 cqicb->lbq_addr =
2572                     cpu_to_le64(rx_ring->lbq_base_indirect_dma);
2573                 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2574                         (u16) rx_ring->lbq_buf_size;
2575                 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2576                 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2577                         (u16) rx_ring->lbq_len;
2578                 cqicb->lbq_len = cpu_to_le16(bq_len);
2579                 rx_ring->lbq_prod_idx = 0;
2580                 rx_ring->lbq_curr_idx = 0;
2581                 rx_ring->lbq_clean_idx = 0;
2582                 rx_ring->lbq_free_cnt = rx_ring->lbq_len;
2583         }
2584         if (rx_ring->sbq_len) {
2585                 cqicb->flags |= FLAGS_LS;       /* Load sbq values */
2586                 *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma;
2587                 cqicb->sbq_addr =
2588                     cpu_to_le64(rx_ring->sbq_base_indirect_dma);
2589                 cqicb->sbq_buf_size =
2590                     cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
2591                 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2592                         (u16) rx_ring->sbq_len;
2593                 cqicb->sbq_len = cpu_to_le16(bq_len);
2594                 rx_ring->sbq_prod_idx = 0;
2595                 rx_ring->sbq_curr_idx = 0;
2596                 rx_ring->sbq_clean_idx = 0;
2597                 rx_ring->sbq_free_cnt = rx_ring->sbq_len;
2598         }
2599         switch (rx_ring->type) {
2600         case TX_Q:
2601                 /* If there's only one interrupt, then we use
2602                  * worker threads to process the outbound
2603                  * completion handling rx_rings. We do this so
2604                  * they can be run on multiple CPUs. There is
2605                  * room to play with this more where we would only
2606                  * run in a worker if there are more than x number
2607                  * of outbound completions on the queue and more
2608                  * than one queue active.  Some threshold that
2609                  * would indicate a benefit in spite of the cost
2610                  * of a context switch.
2611                  * If there's more than one interrupt, then the
2612                  * outbound completions are processed in the ISR.
2613                  */
2614                 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2615                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2616                 else {
2617                         /* With all debug warnings on we see a WARN_ON message
2618                          * when we free the skb in the interrupt context.
2619                          */
2620                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2621                 }
2622                 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2623                 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2624                 break;
2625         case DEFAULT_Q:
2626                 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2627                 cqicb->irq_delay = 0;
2628                 cqicb->pkt_delay = 0;
2629                 break;
2630         case RX_Q:
2631                 /* Inbound completion handling rx_rings run in
2632                  * separate NAPI contexts.
2633                  */
2634                 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2635                                64);
2636                 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2637                 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2638                 break;
2639         default:
2640                 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2641                         rx_ring->type);
2642         }
2643         QPRINTK(qdev, IFUP, DEBUG, "Initializing rx work queue.\n");
2644         err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2645                            CFG_LCQ, rx_ring->cq_id);
2646         if (err) {
2647                 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2648                 return err;
2649         }
2650         return err;
2651 }
2652
2653 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2654 {
2655         struct wqicb *wqicb = (struct wqicb *)tx_ring;
2656         void __iomem *doorbell_area =
2657             qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2658         void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2659             (tx_ring->wq_id * sizeof(u64));
2660         u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2661             (tx_ring->wq_id * sizeof(u64));
2662         int err = 0;
2663
2664         /*
2665          * Assign doorbell registers for this tx_ring.
2666          */
2667         /* TX PCI doorbell mem area for tx producer index */
2668         tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2669         tx_ring->prod_idx = 0;
2670         /* TX PCI doorbell mem area + 0x04 */
2671         tx_ring->valid_db_reg = doorbell_area + 0x04;
2672
2673         /*
2674          * Assign shadow registers for this tx_ring.
2675          */
2676         tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2677         tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2678
2679         wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2680         wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2681                                    Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2682         wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2683         wqicb->rid = 0;
2684         wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
2685
2686         wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
2687
2688         ql_init_tx_ring(qdev, tx_ring);
2689
2690         err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2691                            (u16) tx_ring->wq_id);
2692         if (err) {
2693                 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2694                 return err;
2695         }
2696         QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded WQICB.\n");
2697         return err;
2698 }
2699
2700 static void ql_disable_msix(struct ql_adapter *qdev)
2701 {
2702         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2703                 pci_disable_msix(qdev->pdev);
2704                 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2705                 kfree(qdev->msi_x_entry);
2706                 qdev->msi_x_entry = NULL;
2707         } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2708                 pci_disable_msi(qdev->pdev);
2709                 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2710         }
2711 }
2712
2713 static void ql_enable_msix(struct ql_adapter *qdev)
2714 {
2715         int i;
2716
2717         qdev->intr_count = 1;
2718         /* Get the MSIX vectors. */
2719         if (irq_type == MSIX_IRQ) {
2720                 /* Try to alloc space for the msix struct,
2721                  * if it fails then go to MSI/legacy.
2722                  */
2723                 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2724                                             sizeof(struct msix_entry),
2725                                             GFP_KERNEL);
2726                 if (!qdev->msi_x_entry) {
2727                         irq_type = MSI_IRQ;
2728                         goto msi;
2729                 }
2730
2731                 for (i = 0; i < qdev->rx_ring_count; i++)
2732                         qdev->msi_x_entry[i].entry = i;
2733
2734                 if (!pci_enable_msix
2735                     (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2736                         set_bit(QL_MSIX_ENABLED, &qdev->flags);
2737                         qdev->intr_count = qdev->rx_ring_count;
2738                         QPRINTK(qdev, IFUP, DEBUG,
2739                                 "MSI-X Enabled, got %d vectors.\n",
2740                                 qdev->intr_count);
2741                         return;
2742                 } else {
2743                         kfree(qdev->msi_x_entry);
2744                         qdev->msi_x_entry = NULL;
2745                         QPRINTK(qdev, IFUP, WARNING,
2746                                 "MSI-X Enable failed, trying MSI.\n");
2747                         irq_type = MSI_IRQ;
2748                 }
2749         }
2750 msi:
2751         if (irq_type == MSI_IRQ) {
2752                 if (!pci_enable_msi(qdev->pdev)) {
2753                         set_bit(QL_MSI_ENABLED, &qdev->flags);
2754                         QPRINTK(qdev, IFUP, INFO,
2755                                 "Running with MSI interrupts.\n");
2756                         return;
2757                 }
2758         }
2759         irq_type = LEG_IRQ;
2760         QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2761 }
2762
2763 /*
2764  * Here we build the intr_context structures based on
2765  * our rx_ring count and intr vector count.
2766  * The intr_context structure is used to hook each vector
2767  * to possibly different handlers.
2768  */
2769 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2770 {
2771         int i = 0;
2772         struct intr_context *intr_context = &qdev->intr_context[0];
2773
2774         ql_enable_msix(qdev);
2775
2776         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2777                 /* Each rx_ring has it's
2778                  * own intr_context since we have separate
2779                  * vectors for each queue.
2780                  * This only true when MSI-X is enabled.
2781                  */
2782                 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2783                         qdev->rx_ring[i].irq = i;
2784                         intr_context->intr = i;
2785                         intr_context->qdev = qdev;
2786                         /*
2787                          * We set up each vectors enable/disable/read bits so
2788                          * there's no bit/mask calculations in the critical path.
2789                          */
2790                         intr_context->intr_en_mask =
2791                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2792                             INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2793                             | i;
2794                         intr_context->intr_dis_mask =
2795                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2796                             INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2797                             INTR_EN_IHD | i;
2798                         intr_context->intr_read_mask =
2799                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2800                             INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2801                             i;
2802
2803                         if (i == 0) {
2804                                 /*
2805                                  * Default queue handles bcast/mcast plus
2806                                  * async events.  Needs buffers.
2807                                  */
2808                                 intr_context->handler = qlge_isr;
2809                                 sprintf(intr_context->name, "%s-default-queue",
2810                                         qdev->ndev->name);
2811                         } else if (i < qdev->rss_ring_first_cq_id) {
2812                                 /*
2813                                  * Outbound queue is for outbound completions only.
2814                                  */
2815                                 intr_context->handler = qlge_msix_tx_isr;
2816                                 sprintf(intr_context->name, "%s-tx-%d",
2817                                         qdev->ndev->name, i);
2818                         } else {
2819                                 /*
2820                                  * Inbound queues handle unicast frames only.
2821                                  */
2822                                 intr_context->handler = qlge_msix_rx_isr;
2823                                 sprintf(intr_context->name, "%s-rx-%d",
2824                                         qdev->ndev->name, i);
2825                         }
2826                 }
2827         } else {
2828                 /*
2829                  * All rx_rings use the same intr_context since
2830                  * there is only one vector.
2831                  */
2832                 intr_context->intr = 0;
2833                 intr_context->qdev = qdev;
2834                 /*
2835                  * We set up each vectors enable/disable/read bits so
2836                  * there's no bit/mask calculations in the critical path.
2837                  */
2838                 intr_context->intr_en_mask =
2839                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2840                 intr_context->intr_dis_mask =
2841                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2842                     INTR_EN_TYPE_DISABLE;
2843                 intr_context->intr_read_mask =
2844                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2845                 /*
2846                  * Single interrupt means one handler for all rings.
2847                  */
2848                 intr_context->handler = qlge_isr;
2849                 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2850                 for (i = 0; i < qdev->rx_ring_count; i++)
2851                         qdev->rx_ring[i].irq = 0;
2852         }
2853 }
2854
2855 static void ql_free_irq(struct ql_adapter *qdev)
2856 {
2857         int i;
2858         struct intr_context *intr_context = &qdev->intr_context[0];
2859
2860         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2861                 if (intr_context->hooked) {
2862                         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2863                                 free_irq(qdev->msi_x_entry[i].vector,
2864                                          &qdev->rx_ring[i]);
2865                                 QPRINTK(qdev, IFDOWN, DEBUG,
2866                                         "freeing msix interrupt %d.\n", i);
2867                         } else {
2868                                 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2869                                 QPRINTK(qdev, IFDOWN, DEBUG,
2870                                         "freeing msi interrupt %d.\n", i);
2871                         }
2872                 }
2873         }
2874         ql_disable_msix(qdev);
2875 }
2876
2877 static int ql_request_irq(struct ql_adapter *qdev)
2878 {
2879         int i;
2880         int status = 0;
2881         struct pci_dev *pdev = qdev->pdev;
2882         struct intr_context *intr_context = &qdev->intr_context[0];
2883
2884         ql_resolve_queues_to_irqs(qdev);
2885
2886         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2887                 atomic_set(&intr_context->irq_cnt, 0);
2888                 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2889                         status = request_irq(qdev->msi_x_entry[i].vector,
2890                                              intr_context->handler,
2891                                              0,
2892                                              intr_context->name,
2893                                              &qdev->rx_ring[i]);
2894                         if (status) {
2895                                 QPRINTK(qdev, IFUP, ERR,
2896                                         "Failed request for MSIX interrupt %d.\n",
2897                                         i);
2898                                 goto err_irq;
2899                         } else {
2900                                 QPRINTK(qdev, IFUP, DEBUG,
2901                                         "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2902                                         i,
2903                                         qdev->rx_ring[i].type ==
2904                                         DEFAULT_Q ? "DEFAULT_Q" : "",
2905                                         qdev->rx_ring[i].type ==
2906                                         TX_Q ? "TX_Q" : "",
2907                                         qdev->rx_ring[i].type ==
2908                                         RX_Q ? "RX_Q" : "", intr_context->name);
2909                         }
2910                 } else {
2911                         QPRINTK(qdev, IFUP, DEBUG,
2912                                 "trying msi or legacy interrupts.\n");
2913                         QPRINTK(qdev, IFUP, DEBUG,
2914                                 "%s: irq = %d.\n", __func__, pdev->irq);
2915                         QPRINTK(qdev, IFUP, DEBUG,
2916                                 "%s: context->name = %s.\n", __func__,
2917                                intr_context->name);
2918                         QPRINTK(qdev, IFUP, DEBUG,
2919                                 "%s: dev_id = 0x%p.\n", __func__,
2920                                &qdev->rx_ring[0]);
2921                         status =
2922                             request_irq(pdev->irq, qlge_isr,
2923                                         test_bit(QL_MSI_ENABLED,
2924                                                  &qdev->
2925                                                  flags) ? 0 : IRQF_SHARED,
2926                                         intr_context->name, &qdev->rx_ring[0]);
2927                         if (status)
2928                                 goto err_irq;
2929
2930                         QPRINTK(qdev, IFUP, ERR,
2931                                 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2932                                 i,
2933                                 qdev->rx_ring[0].type ==
2934                                 DEFAULT_Q ? "DEFAULT_Q" : "",
2935                                 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2936                                 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2937                                 intr_context->name);
2938                 }
2939                 intr_context->hooked = 1;
2940         }
2941         return status;
2942 err_irq:
2943         QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2944         ql_free_irq(qdev);
2945         return status;
2946 }
2947
2948 static int ql_start_rss(struct ql_adapter *qdev)
2949 {
2950         struct ricb *ricb = &qdev->ricb;
2951         int status = 0;
2952         int i;
2953         u8 *hash_id = (u8 *) ricb->hash_cq_id;
2954
2955         memset((void *)ricb, 0, sizeof(ricb));
2956
2957         ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2958         ricb->flags =
2959             (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2960              RSS_RT6);
2961         ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2962
2963         /*
2964          * Fill out the Indirection Table.
2965          */
2966         for (i = 0; i < 256; i++)
2967                 hash_id[i] = i & (qdev->rss_ring_count - 1);
2968
2969         /*
2970          * Random values for the IPv6 and IPv4 Hash Keys.
2971          */
2972         get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2973         get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2974
2975         QPRINTK(qdev, IFUP, DEBUG, "Initializing RSS.\n");
2976
2977         status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2978         if (status) {
2979                 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2980                 return status;
2981         }
2982         QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded RICB.\n");
2983         return status;
2984 }
2985
2986 /* Initialize the frame-to-queue routing. */
2987 static int ql_route_initialize(struct ql_adapter *qdev)
2988 {
2989         int status = 0;
2990         int i;
2991
2992         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
2993         if (status)
2994                 return status;
2995
2996         /* Clear all the entries in the routing table. */
2997         for (i = 0; i < 16; i++) {
2998                 status = ql_set_routing_reg(qdev, i, 0, 0);
2999                 if (status) {
3000                         QPRINTK(qdev, IFUP, ERR,
3001                                 "Failed to init routing register for CAM packets.\n");
3002                         goto exit;
3003                 }
3004         }
3005
3006         status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
3007         if (status) {
3008                 QPRINTK(qdev, IFUP, ERR,
3009                         "Failed to init routing register for error packets.\n");
3010                 goto exit;
3011         }
3012         status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
3013         if (status) {
3014                 QPRINTK(qdev, IFUP, ERR,
3015                         "Failed to init routing register for broadcast packets.\n");
3016                 goto exit;
3017         }
3018         /* If we have more than one inbound queue, then turn on RSS in the
3019          * routing block.
3020          */
3021         if (qdev->rss_ring_count > 1) {
3022                 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
3023                                         RT_IDX_RSS_MATCH, 1);
3024                 if (status) {
3025                         QPRINTK(qdev, IFUP, ERR,
3026                                 "Failed to init routing register for MATCH RSS packets.\n");
3027                         goto exit;
3028                 }
3029         }
3030
3031         status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
3032                                     RT_IDX_CAM_HIT, 1);
3033         if (status)
3034                 QPRINTK(qdev, IFUP, ERR,
3035                         "Failed to init routing register for CAM packets.\n");
3036 exit:
3037         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3038         return status;
3039 }
3040
3041 int ql_cam_route_initialize(struct ql_adapter *qdev)
3042 {
3043         int status;
3044
3045         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3046         if (status)
3047                 return status;
3048         status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3049                              MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3050         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3051         if (status) {
3052                 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3053                 return status;
3054         }
3055
3056         status = ql_route_initialize(qdev);
3057         if (status)
3058                 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3059
3060         return status;
3061 }
3062
3063 static int ql_adapter_initialize(struct ql_adapter *qdev)
3064 {
3065         u32 value, mask;
3066         int i;
3067         int status = 0;
3068
3069         /*
3070          * Set up the System register to halt on errors.
3071          */
3072         value = SYS_EFE | SYS_FAE;
3073         mask = value << 16;
3074         ql_write32(qdev, SYS, mask | value);
3075
3076         /* Set the default queue. */
3077         value = NIC_RCV_CFG_DFQ;
3078         mask = NIC_RCV_CFG_DFQ_MASK;
3079         ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3080
3081         /* Set the MPI interrupt to enabled. */
3082         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3083
3084         /* Enable the function, set pagesize, enable error checking. */
3085         value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3086             FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
3087
3088         /* Set/clear header splitting. */
3089         mask = FSC_VM_PAGESIZE_MASK |
3090             FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3091         ql_write32(qdev, FSC, mask | value);
3092
3093         ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3094                 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3095
3096         /* Start up the rx queues. */
3097         for (i = 0; i < qdev->rx_ring_count; i++) {
3098                 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3099                 if (status) {
3100                         QPRINTK(qdev, IFUP, ERR,
3101                                 "Failed to start rx ring[%d].\n", i);
3102                         return status;
3103                 }
3104         }
3105
3106         /* If there is more than one inbound completion queue
3107          * then download a RICB to configure RSS.
3108          */
3109         if (qdev->rss_ring_count > 1) {
3110                 status = ql_start_rss(qdev);
3111                 if (status) {
3112                         QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3113                         return status;
3114                 }
3115         }
3116
3117         /* Start up the tx queues. */
3118         for (i = 0; i < qdev->tx_ring_count; i++) {
3119                 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3120                 if (status) {
3121                         QPRINTK(qdev, IFUP, ERR,
3122                                 "Failed to start tx ring[%d].\n", i);
3123                         return status;
3124                 }
3125         }
3126
3127         /* Initialize the port and set the max framesize. */
3128         status = qdev->nic_ops->port_initialize(qdev);
3129        if (status) {
3130               QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3131               return status;
3132        }
3133
3134         /* Set up the MAC address and frame routing filter. */
3135         status = ql_cam_route_initialize(qdev);
3136         if (status) {
3137                 QPRINTK(qdev, IFUP, ERR,
3138                                 "Failed to init CAM/Routing tables.\n");
3139                 return status;
3140         }
3141
3142         /* Start NAPI for the RSS queues. */
3143         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3144                 QPRINTK(qdev, IFUP, DEBUG, "Enabling NAPI for rx_ring[%d].\n",
3145                         i);
3146                 napi_enable(&qdev->rx_ring[i].napi);
3147         }
3148
3149         return status;
3150 }
3151
3152 /* Issue soft reset to chip. */
3153 static int ql_adapter_reset(struct ql_adapter *qdev)
3154 {
3155         u32 value;
3156         int status = 0;
3157         unsigned long end_jiffies = jiffies +
3158                 max((unsigned long)1, usecs_to_jiffies(30));
3159
3160         ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3161
3162         do {
3163                 value = ql_read32(qdev, RST_FO);
3164                 if ((value & RST_FO_FR) == 0)
3165                         break;
3166                 cpu_relax();
3167         } while (time_before(jiffies, end_jiffies));
3168
3169         if (value & RST_FO_FR) {
3170                 QPRINTK(qdev, IFDOWN, ERR,
3171                         "ETIMEOUT!!! errored out of resetting the chip!\n");
3172                 status = -ETIMEDOUT;
3173         }
3174
3175         return status;
3176 }
3177
3178 static void ql_display_dev_info(struct net_device *ndev)
3179 {
3180         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3181
3182         QPRINTK(qdev, PROBE, INFO,
3183                 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3184                 "XG Roll = %d, XG Rev = %d.\n",
3185                 qdev->func,
3186                 qdev->chip_rev_id & 0x0000000f,
3187                 qdev->chip_rev_id >> 4 & 0x0000000f,
3188                 qdev->chip_rev_id >> 8 & 0x0000000f,
3189                 qdev->chip_rev_id >> 12 & 0x0000000f);
3190         QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3191 }
3192
3193 static int ql_adapter_down(struct ql_adapter *qdev)
3194 {
3195         int i, status = 0;
3196         struct rx_ring *rx_ring;
3197
3198         netif_carrier_off(qdev->ndev);
3199
3200         /* Don't kill the reset worker thread if we
3201          * are in the process of recovery.
3202          */
3203         if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3204                 cancel_delayed_work_sync(&qdev->asic_reset_work);
3205         cancel_delayed_work_sync(&qdev->mpi_reset_work);
3206         cancel_delayed_work_sync(&qdev->mpi_work);
3207         cancel_delayed_work_sync(&qdev->mpi_idc_work);
3208         cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
3209
3210         /* The default queue at index 0 is always processed in
3211          * a workqueue.
3212          */
3213         cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3214
3215         /* The rest of the rx_rings are processed in
3216          * a workqueue only if it's a single interrupt
3217          * environment (MSI/Legacy).
3218          */
3219         for (i = 1; i < qdev->rx_ring_count; i++) {
3220                 rx_ring = &qdev->rx_ring[i];
3221                 /* Only the RSS rings use NAPI on multi irq
3222                  * environment.  Outbound completion processing
3223                  * is done in interrupt context.
3224                  */
3225                 if (i >= qdev->rss_ring_first_cq_id) {
3226                         napi_disable(&rx_ring->napi);
3227                 } else {
3228                         cancel_delayed_work_sync(&rx_ring->rx_work);
3229                 }
3230         }
3231
3232         clear_bit(QL_ADAPTER_UP, &qdev->flags);
3233
3234         ql_disable_interrupts(qdev);
3235
3236         ql_tx_ring_clean(qdev);
3237
3238         ql_free_rx_buffers(qdev);
3239         spin_lock(&qdev->hw_lock);
3240         status = ql_adapter_reset(qdev);
3241         if (status)
3242                 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3243                         qdev->func);
3244         spin_unlock(&qdev->hw_lock);
3245         return status;
3246 }
3247
3248 static int ql_adapter_up(struct ql_adapter *qdev)
3249 {
3250         int err = 0;
3251
3252         spin_lock(&qdev->hw_lock);
3253         err = ql_adapter_initialize(qdev);
3254         if (err) {
3255                 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3256                 spin_unlock(&qdev->hw_lock);
3257                 goto err_init;
3258         }
3259         spin_unlock(&qdev->hw_lock);
3260         set_bit(QL_ADAPTER_UP, &qdev->flags);
3261         ql_alloc_rx_buffers(qdev);
3262         if ((ql_read32(qdev, STS) & qdev->port_init))
3263                 netif_carrier_on(qdev->ndev);
3264         ql_enable_interrupts(qdev);
3265         ql_enable_all_completion_interrupts(qdev);
3266         netif_tx_start_all_queues(qdev->ndev);
3267
3268         return 0;
3269 err_init:
3270         ql_adapter_reset(qdev);
3271         return err;
3272 }
3273
3274 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3275 {
3276         ql_free_mem_resources(qdev);
3277         ql_free_irq(qdev);
3278 }
3279
3280 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3281 {
3282         int status = 0;
3283
3284         if (ql_alloc_mem_resources(qdev)) {
3285                 QPRINTK(qdev, IFUP, ERR, "Unable to  allocate memory.\n");
3286                 return -ENOMEM;
3287         }
3288         status = ql_request_irq(qdev);
3289         if (status)
3290                 goto err_irq;
3291         return status;
3292 err_irq:
3293         ql_free_mem_resources(qdev);
3294         return status;
3295 }
3296
3297 static int qlge_close(struct net_device *ndev)
3298 {
3299         struct ql_adapter *qdev = netdev_priv(ndev);
3300
3301         /*
3302          * Wait for device to recover from a reset.
3303          * (Rarely happens, but possible.)
3304          */
3305         while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3306                 msleep(1);
3307         ql_adapter_down(qdev);
3308         ql_release_adapter_resources(qdev);
3309         return 0;
3310 }
3311
3312 static int ql_configure_rings(struct ql_adapter *qdev)
3313 {
3314         int i;
3315         struct rx_ring *rx_ring;
3316         struct tx_ring *tx_ring;
3317         int cpu_cnt = num_online_cpus();
3318
3319         /*
3320          * For each processor present we allocate one
3321          * rx_ring for outbound completions, and one
3322          * rx_ring for inbound completions.  Plus there is
3323          * always the one default queue.  For the CPU
3324          * counts we end up with the following rx_rings:
3325          * rx_ring count =
3326          *  one default queue +
3327          *  (CPU count * outbound completion rx_ring) +
3328          *  (CPU count * inbound (RSS) completion rx_ring)
3329          * To keep it simple we limit the total number of
3330          * queues to < 32, so we truncate CPU to 8.
3331          * This limitation can be removed when requested.
3332          */
3333
3334         if (cpu_cnt > MAX_CPUS)
3335                 cpu_cnt = MAX_CPUS;
3336
3337         /*
3338          * rx_ring[0] is always the default queue.
3339          */
3340         /* Allocate outbound completion ring for each CPU. */
3341         qdev->tx_ring_count = cpu_cnt;
3342         /* Allocate inbound completion (RSS) ring for each CPU. */
3343         qdev->rss_ring_count = cpu_cnt;
3344         /* cq_id for the first inbound ring handler. */
3345         qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3346         /*
3347          * qdev->rx_ring_count:
3348          * Total number of rx_rings.  This includes the one
3349          * default queue, a number of outbound completion
3350          * handler rx_rings, and the number of inbound
3351          * completion handler rx_rings.
3352          */
3353         qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3354         netif_set_gso_max_size(qdev->ndev, 65536);
3355
3356         for (i = 0; i < qdev->tx_ring_count; i++) {
3357                 tx_ring = &qdev->tx_ring[i];
3358                 memset((void *)tx_ring, 0, sizeof(tx_ring));
3359                 tx_ring->qdev = qdev;
3360                 tx_ring->wq_id = i;
3361                 tx_ring->wq_len = qdev->tx_ring_size;
3362                 tx_ring->wq_size =
3363                     tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3364
3365                 /*
3366                  * The completion queue ID for the tx rings start
3367                  * immediately after the default Q ID, which is zero.
3368                  */
3369                 tx_ring->cq_id = i + 1;
3370         }
3371
3372         for (i = 0; i < qdev->rx_ring_count; i++) {
3373                 rx_ring = &qdev->rx_ring[i];
3374                 memset((void *)rx_ring, 0, sizeof(rx_ring));
3375                 rx_ring->qdev = qdev;
3376                 rx_ring->cq_id = i;
3377                 rx_ring->cpu = i % cpu_cnt;     /* CPU to run handler on. */
3378                 if (i == 0) {   /* Default queue at index 0. */
3379                         /*
3380                          * Default queue handles bcast/mcast plus
3381                          * async events.  Needs buffers.
3382                          */
3383                         rx_ring->cq_len = qdev->rx_ring_size;
3384                         rx_ring->cq_size =
3385                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3386                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3387                         rx_ring->lbq_size =
3388                             rx_ring->lbq_len * sizeof(__le64);
3389                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3390                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3391                         rx_ring->sbq_size =
3392                             rx_ring->sbq_len * sizeof(__le64);
3393                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3394                         rx_ring->type = DEFAULT_Q;
3395                 } else if (i < qdev->rss_ring_first_cq_id) {
3396                         /*
3397                          * Outbound queue handles outbound completions only.
3398                          */
3399                         /* outbound cq is same size as tx_ring it services. */
3400                         rx_ring->cq_len = qdev->tx_ring_size;
3401                         rx_ring->cq_size =
3402                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3403                         rx_ring->lbq_len = 0;
3404                         rx_ring->lbq_size = 0;
3405                         rx_ring->lbq_buf_size = 0;
3406                         rx_ring->sbq_len = 0;
3407                         rx_ring->sbq_size = 0;
3408                         rx_ring->sbq_buf_size = 0;
3409                         rx_ring->type = TX_Q;
3410                 } else {        /* Inbound completions (RSS) queues */
3411                         /*
3412                          * Inbound queues handle unicast frames only.
3413                          */
3414                         rx_ring->cq_len = qdev->rx_ring_size;
3415                         rx_ring->cq_size =
3416                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3417                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3418                         rx_ring->lbq_size =
3419                             rx_ring->lbq_len * sizeof(__le64);
3420                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3421                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3422                         rx_ring->sbq_size =
3423                             rx_ring->sbq_len * sizeof(__le64);
3424                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3425                         rx_ring->type = RX_Q;
3426                 }
3427         }
3428         return 0;
3429 }
3430
3431 static int qlge_open(struct net_device *ndev)
3432 {
3433         int err = 0;
3434         struct ql_adapter *qdev = netdev_priv(ndev);
3435
3436         err = ql_configure_rings(qdev);
3437         if (err)
3438                 return err;
3439
3440         err = ql_get_adapter_resources(qdev);
3441         if (err)
3442                 goto error_up;
3443
3444         err = ql_adapter_up(qdev);
3445         if (err)
3446                 goto error_up;
3447
3448         return err;
3449
3450 error_up:
3451         ql_release_adapter_resources(qdev);
3452         return err;
3453 }
3454
3455 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3456 {
3457         struct ql_adapter *qdev = netdev_priv(ndev);
3458
3459         if (ndev->mtu == 1500 && new_mtu == 9000) {
3460                 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3461                 queue_delayed_work(qdev->workqueue,
3462                                 &qdev->mpi_port_cfg_work, 0);
3463         } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3464                 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3465         } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3466                    (ndev->mtu == 9000 && new_mtu == 9000)) {
3467                 return 0;
3468         } else
3469                 return -EINVAL;
3470         ndev->mtu = new_mtu;
3471         return 0;
3472 }
3473
3474 static struct net_device_stats *qlge_get_stats(struct net_device
3475                                                *ndev)
3476 {
3477         struct ql_adapter *qdev = netdev_priv(ndev);
3478         return &qdev->stats;
3479 }
3480
3481 static void qlge_set_multicast_list(struct net_device *ndev)
3482 {
3483         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3484         struct dev_mc_list *mc_ptr;
3485         int i, status;
3486
3487         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3488         if (status)
3489                 return;
3490         spin_lock(&qdev->hw_lock);
3491         /*
3492          * Set or clear promiscuous mode if a
3493          * transition is taking place.
3494          */
3495         if (ndev->flags & IFF_PROMISC) {
3496                 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3497                         if (ql_set_routing_reg
3498                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3499                                 QPRINTK(qdev, HW, ERR,
3500                                         "Failed to set promiscous mode.\n");
3501                         } else {
3502                                 set_bit(QL_PROMISCUOUS, &qdev->flags);
3503                         }
3504                 }
3505         } else {
3506                 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3507                         if (ql_set_routing_reg
3508                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3509                                 QPRINTK(qdev, HW, ERR,
3510                                         "Failed to clear promiscous mode.\n");
3511                         } else {
3512                                 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3513                         }
3514                 }
3515         }
3516
3517         /*
3518          * Set or clear all multicast mode if a
3519          * transition is taking place.
3520          */
3521         if ((ndev->flags & IFF_ALLMULTI) ||
3522             (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3523                 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3524                         if (ql_set_routing_reg
3525                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3526                                 QPRINTK(qdev, HW, ERR,
3527                                         "Failed to set all-multi mode.\n");
3528                         } else {
3529                                 set_bit(QL_ALLMULTI, &qdev->flags);
3530                         }
3531                 }
3532         } else {
3533                 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3534                         if (ql_set_routing_reg
3535                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3536                                 QPRINTK(qdev, HW, ERR,
3537                                         "Failed to clear all-multi mode.\n");
3538                         } else {
3539                                 clear_bit(QL_ALLMULTI, &qdev->flags);
3540                         }
3541                 }
3542         }
3543
3544         if (ndev->mc_count) {
3545                 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3546                 if (status)
3547                         goto exit;
3548                 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3549                      i++, mc_ptr = mc_ptr->next)
3550                         if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3551                                                 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3552                                 QPRINTK(qdev, HW, ERR,
3553                                         "Failed to loadmulticast address.\n");
3554                                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3555                                 goto exit;
3556                         }
3557                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3558                 if (ql_set_routing_reg
3559                     (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3560                         QPRINTK(qdev, HW, ERR,
3561                                 "Failed to set multicast match mode.\n");
3562                 } else {
3563                         set_bit(QL_ALLMULTI, &qdev->flags);
3564                 }
3565         }
3566 exit:
3567         spin_unlock(&qdev->hw_lock);
3568         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3569 }
3570
3571 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3572 {
3573         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3574         struct sockaddr *addr = p;
3575         int status;
3576
3577         if (netif_running(ndev))
3578                 return -EBUSY;
3579
3580         if (!is_valid_ether_addr(addr->sa_data))
3581                 return -EADDRNOTAVAIL;
3582         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3583
3584         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3585         if (status)
3586                 return status;
3587         spin_lock(&qdev->hw_lock);
3588         status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3589                         MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3590         spin_unlock(&qdev->hw_lock);
3591         if (status)
3592                 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3593         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3594         return status;
3595 }
3596
3597 static void qlge_tx_timeout(struct net_device *ndev)
3598 {
3599         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3600         ql_queue_asic_error(qdev);
3601 }
3602
3603 static void ql_asic_reset_work(struct work_struct *work)
3604 {
3605         struct ql_adapter *qdev =
3606             container_of(work, struct ql_adapter, asic_reset_work.work);
3607         int status;
3608
3609         status = ql_adapter_down(qdev);
3610         if (status)
3611                 goto error;
3612
3613         status = ql_adapter_up(qdev);
3614         if (status)
3615                 goto error;
3616
3617         return;
3618 error:
3619         QPRINTK(qdev, IFUP, ALERT,
3620                 "Driver up/down cycle failed, closing device\n");
3621         rtnl_lock();
3622         set_bit(QL_ADAPTER_UP, &qdev->flags);
3623         dev_close(qdev->ndev);
3624         rtnl_unlock();
3625 }
3626
3627 static struct nic_operations qla8012_nic_ops = {
3628         .get_flash              = ql_get_8012_flash_params,
3629         .port_initialize        = ql_8012_port_initialize,
3630 };
3631
3632 static struct nic_operations qla8000_nic_ops = {
3633         .get_flash              = ql_get_8000_flash_params,
3634         .port_initialize        = ql_8000_port_initialize,
3635 };
3636
3637
3638 static void ql_get_board_info(struct ql_adapter *qdev)
3639 {
3640         qdev->func =
3641             (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3642         if (qdev->func) {
3643                 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3644                 qdev->port_link_up = STS_PL1;
3645                 qdev->port_init = STS_PI1;
3646                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3647                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3648         } else {
3649                 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3650                 qdev->port_link_up = STS_PL0;
3651                 qdev->port_init = STS_PI0;
3652                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3653                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3654         }
3655         qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3656         qdev->device_id = qdev->pdev->device;
3657         if (qdev->device_id == QLGE_DEVICE_ID_8012)
3658                 qdev->nic_ops = &qla8012_nic_ops;
3659         else if (qdev->device_id == QLGE_DEVICE_ID_8000)
3660                 qdev->nic_ops = &qla8000_nic_ops;
3661 }
3662
3663 static void ql_release_all(struct pci_dev *pdev)
3664 {
3665         struct net_device *ndev = pci_get_drvdata(pdev);
3666         struct ql_adapter *qdev = netdev_priv(ndev);
3667
3668         if (qdev->workqueue) {
3669                 destroy_workqueue(qdev->workqueue);
3670                 qdev->workqueue = NULL;
3671         }
3672         if (qdev->q_workqueue) {
3673                 destroy_workqueue(qdev->q_workqueue);
3674                 qdev->q_workqueue = NULL;
3675         }
3676         if (qdev->reg_base)
3677                 iounmap(qdev->reg_base);
3678         if (qdev->doorbell_area)
3679                 iounmap(qdev->doorbell_area);
3680         pci_release_regions(pdev);
3681         pci_set_drvdata(pdev, NULL);
3682 }
3683
3684 static int __devinit ql_init_device(struct pci_dev *pdev,
3685                                     struct net_device *ndev, int cards_found)
3686 {
3687         struct ql_adapter *qdev = netdev_priv(ndev);
3688         int pos, err = 0;
3689         u16 val16;
3690
3691         memset((void *)qdev, 0, sizeof(qdev));
3692         err = pci_enable_device(pdev);
3693         if (err) {
3694                 dev_err(&pdev->dev, "PCI device enable failed.\n");
3695                 return err;
3696         }
3697
3698         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3699         if (pos <= 0) {
3700                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3701                         "aborting.\n");
3702                 goto err_out;
3703         } else {
3704                 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3705                 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3706                 val16 |= (PCI_EXP_DEVCTL_CERE |
3707                           PCI_EXP_DEVCTL_NFERE |
3708                           PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3709                 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3710         }
3711
3712         err = pci_request_regions(pdev, DRV_NAME);
3713         if (err) {
3714                 dev_err(&pdev->dev, "PCI region request failed.\n");
3715                 goto err_out;
3716         }
3717
3718         pci_set_master(pdev);
3719         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3720                 set_bit(QL_DMA64, &qdev->flags);
3721                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3722         } else {
3723                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3724                 if (!err)
3725                        err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3726         }
3727
3728         if (err) {
3729                 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3730                 goto err_out;
3731         }
3732
3733         pci_set_drvdata(pdev, ndev);
3734         qdev->reg_base =
3735             ioremap_nocache(pci_resource_start(pdev, 1),
3736                             pci_resource_len(pdev, 1));
3737         if (!qdev->reg_base) {
3738                 dev_err(&pdev->dev, "Register mapping failed.\n");
3739                 err = -ENOMEM;
3740                 goto err_out;
3741         }
3742
3743         qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3744         qdev->doorbell_area =
3745             ioremap_nocache(pci_resource_start(pdev, 3),
3746                             pci_resource_len(pdev, 3));
3747         if (!qdev->doorbell_area) {
3748                 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3749                 err = -ENOMEM;
3750                 goto err_out;
3751         }
3752
3753         qdev->ndev = ndev;
3754         qdev->pdev = pdev;
3755         ql_get_board_info(qdev);
3756         qdev->msg_enable = netif_msg_init(debug, default_msg);
3757         spin_lock_init(&qdev->hw_lock);
3758         spin_lock_init(&qdev->stats_lock);
3759
3760         /* make sure the EEPROM is good */
3761         err = qdev->nic_ops->get_flash(qdev);
3762         if (err) {
3763                 dev_err(&pdev->dev, "Invalid FLASH.\n");
3764                 goto err_out;
3765         }
3766
3767         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3768
3769         /* Set up the default ring sizes. */
3770         qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3771         qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3772
3773         /* Set up the coalescing parameters. */
3774         qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3775         qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3776         qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3777         qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3778
3779         /*
3780          * Set up the operating parameters.
3781          */
3782         qdev->rx_csum = 1;
3783
3784         qdev->q_workqueue = create_workqueue(ndev->name);
3785         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3786         INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3787         INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3788         INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3789         INIT_DELAYED_WORK(&qdev->mpi_port_cfg_work, ql_mpi_port_cfg_work);
3790         INIT_DELAYED_WORK(&qdev->mpi_idc_work, ql_mpi_idc_work);
3791         mutex_init(&qdev->mpi_mutex);
3792         init_completion(&qdev->ide_completion);
3793
3794         if (!cards_found) {
3795                 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3796                 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3797                          DRV_NAME, DRV_VERSION);
3798         }
3799         return 0;
3800 err_out:
3801         ql_release_all(pdev);
3802         pci_disable_device(pdev);
3803         return err;
3804 }
3805
3806
3807 static const struct net_device_ops qlge_netdev_ops = {
3808         .ndo_open               = qlge_open,
3809         .ndo_stop               = qlge_close,
3810         .ndo_start_xmit         = qlge_send,
3811         .ndo_change_mtu         = qlge_change_mtu,
3812         .ndo_get_stats          = qlge_get_stats,
3813         .ndo_set_multicast_list = qlge_set_multicast_list,
3814         .ndo_set_mac_address    = qlge_set_mac_address,
3815         .ndo_validate_addr      = eth_validate_addr,
3816         .ndo_tx_timeout         = qlge_tx_timeout,
3817         .ndo_vlan_rx_register   = ql_vlan_rx_register,
3818         .ndo_vlan_rx_add_vid    = ql_vlan_rx_add_vid,
3819         .ndo_vlan_rx_kill_vid   = ql_vlan_rx_kill_vid,
3820 };
3821
3822 static int __devinit qlge_probe(struct pci_dev *pdev,
3823                                 const struct pci_device_id *pci_entry)
3824 {
3825         struct net_device *ndev = NULL;
3826         struct ql_adapter *qdev = NULL;
3827         static int cards_found = 0;
3828         int err = 0;
3829
3830         ndev = alloc_etherdev_mq(sizeof(struct ql_adapter),
3831                         min(MAX_CPUS, (int)num_online_cpus()));
3832         if (!ndev)
3833                 return -ENOMEM;
3834
3835         err = ql_init_device(pdev, ndev, cards_found);
3836         if (err < 0) {
3837                 free_netdev(ndev);
3838                 return err;
3839         }
3840
3841         qdev = netdev_priv(ndev);
3842         SET_NETDEV_DEV(ndev, &pdev->dev);
3843         ndev->features = (0
3844                           | NETIF_F_IP_CSUM
3845                           | NETIF_F_SG
3846                           | NETIF_F_TSO
3847                           | NETIF_F_TSO6
3848                           | NETIF_F_TSO_ECN
3849                           | NETIF_F_HW_VLAN_TX
3850                           | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3851         ndev->features |= NETIF_F_GRO;
3852
3853         if (test_bit(QL_DMA64, &qdev->flags))
3854                 ndev->features |= NETIF_F_HIGHDMA;
3855
3856         /*
3857          * Set up net_device structure.
3858          */
3859         ndev->tx_queue_len = qdev->tx_ring_size;
3860         ndev->irq = pdev->irq;
3861
3862         ndev->netdev_ops = &qlge_netdev_ops;
3863         SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
3864         ndev->watchdog_timeo = 10 * HZ;
3865
3866         err = register_netdev(ndev);
3867         if (err) {
3868                 dev_err(&pdev->dev, "net device registration failed.\n");
3869                 ql_release_all(pdev);
3870                 pci_disable_device(pdev);
3871                 return err;
3872         }
3873         netif_carrier_off(ndev);
3874         ql_display_dev_info(ndev);
3875         cards_found++;
3876         return 0;
3877 }
3878
3879 static void __devexit qlge_remove(struct pci_dev *pdev)
3880 {
3881         struct net_device *ndev = pci_get_drvdata(pdev);
3882         unregister_netdev(ndev);
3883         ql_release_all(pdev);
3884         pci_disable_device(pdev);
3885         free_netdev(ndev);
3886 }
3887
3888 /*
3889  * This callback is called by the PCI subsystem whenever
3890  * a PCI bus error is detected.
3891  */
3892 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3893                                                enum pci_channel_state state)
3894 {
3895         struct net_device *ndev = pci_get_drvdata(pdev);
3896         struct ql_adapter *qdev = netdev_priv(ndev);
3897
3898         if (netif_running(ndev))
3899                 ql_adapter_down(qdev);
3900
3901         pci_disable_device(pdev);
3902
3903         /* Request a slot reset. */
3904         return PCI_ERS_RESULT_NEED_RESET;
3905 }
3906
3907 /*
3908  * This callback is called after the PCI buss has been reset.
3909  * Basically, this tries to restart the card from scratch.
3910  * This is a shortened version of the device probe/discovery code,
3911  * it resembles the first-half of the () routine.
3912  */
3913 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3914 {
3915         struct net_device *ndev = pci_get_drvdata(pdev);
3916         struct ql_adapter *qdev = netdev_priv(ndev);
3917
3918         if (pci_enable_device(pdev)) {
3919                 QPRINTK(qdev, IFUP, ERR,
3920                         "Cannot re-enable PCI device after reset.\n");
3921                 return PCI_ERS_RESULT_DISCONNECT;
3922         }
3923
3924         pci_set_master(pdev);
3925
3926         netif_carrier_off(ndev);
3927         ql_adapter_reset(qdev);
3928
3929         /* Make sure the EEPROM is good */
3930         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3931
3932         if (!is_valid_ether_addr(ndev->perm_addr)) {
3933                 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3934                 return PCI_ERS_RESULT_DISCONNECT;
3935         }
3936
3937         return PCI_ERS_RESULT_RECOVERED;
3938 }
3939
3940 static void qlge_io_resume(struct pci_dev *pdev)
3941 {
3942         struct net_device *ndev = pci_get_drvdata(pdev);
3943         struct ql_adapter *qdev = netdev_priv(ndev);
3944
3945         pci_set_master(pdev);
3946
3947         if (netif_running(ndev)) {
3948                 if (ql_adapter_up(qdev)) {
3949                         QPRINTK(qdev, IFUP, ERR,
3950                                 "Device initialization failed after reset.\n");
3951                         return;
3952                 }
3953         }
3954
3955         netif_device_attach(ndev);
3956 }
3957
3958 static struct pci_error_handlers qlge_err_handler = {
3959         .error_detected = qlge_io_error_detected,
3960         .slot_reset = qlge_io_slot_reset,
3961         .resume = qlge_io_resume,
3962 };
3963
3964 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3965 {
3966         struct net_device *ndev = pci_get_drvdata(pdev);
3967         struct ql_adapter *qdev = netdev_priv(ndev);
3968         int err, i;
3969
3970         netif_device_detach(ndev);
3971
3972         if (netif_running(ndev)) {
3973                 err = ql_adapter_down(qdev);
3974                 if (!err)
3975                         return err;
3976         }
3977
3978         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++)
3979                 netif_napi_del(&qdev->rx_ring[i].napi);
3980
3981         err = pci_save_state(pdev);
3982         if (err)
3983                 return err;
3984
3985         pci_disable_device(pdev);
3986
3987         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3988
3989         return 0;
3990 }
3991
3992 #ifdef CONFIG_PM
3993 static int qlge_resume(struct pci_dev *pdev)
3994 {
3995         struct net_device *ndev = pci_get_drvdata(pdev);
3996         struct ql_adapter *qdev = netdev_priv(ndev);
3997         int err;
3998
3999         pci_set_power_state(pdev, PCI_D0);
4000         pci_restore_state(pdev);
4001         err = pci_enable_device(pdev);
4002         if (err) {
4003                 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
4004                 return err;
4005         }
4006         pci_set_master(pdev);
4007
4008         pci_enable_wake(pdev, PCI_D3hot, 0);
4009         pci_enable_wake(pdev, PCI_D3cold, 0);
4010
4011         if (netif_running(ndev)) {
4012                 err = ql_adapter_up(qdev);
4013                 if (err)
4014                         return err;
4015         }
4016
4017         netif_device_attach(ndev);
4018
4019         return 0;
4020 }
4021 #endif /* CONFIG_PM */
4022
4023 static void qlge_shutdown(struct pci_dev *pdev)
4024 {
4025         qlge_suspend(pdev, PMSG_SUSPEND);
4026 }
4027
4028 static struct pci_driver qlge_driver = {
4029         .name = DRV_NAME,
4030         .id_table = qlge_pci_tbl,
4031         .probe = qlge_probe,
4032         .remove = __devexit_p(qlge_remove),
4033 #ifdef CONFIG_PM
4034         .suspend = qlge_suspend,
4035         .resume = qlge_resume,
4036 #endif
4037         .shutdown = qlge_shutdown,
4038         .err_handler = &qlge_err_handler
4039 };
4040
4041 static int __init qlge_init_module(void)
4042 {
4043         return pci_register_driver(&qlge_driver);
4044 }
4045
4046 static void __exit qlge_exit(void)
4047 {
4048         pci_unregister_driver(&qlge_driver);
4049 }
4050
4051 module_init(qlge_init_module);
4052 module_exit(qlge_exit);