45ad4cc298bf594ddf55218cf4847211d24643e7
[linux-2.6.git] / drivers / net / qlge / qlge_main.c
1 /*
2  * QLogic qlge NIC HBA Driver
3  * Copyright (c)  2003-2008 QLogic Corporation
4  * See LICENSE.qlge for copyright and licensing details.
5  * Author:     Linux qlge network device driver by
6  *                      Ron Mercer <ron.mercer@qlogic.com>
7  */
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/pagemap.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/dmapool.h>
19 #include <linux/mempool.h>
20 #include <linux/spinlock.h>
21 #include <linux/kthread.h>
22 #include <linux/interrupt.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/in.h>
26 #include <linux/ip.h>
27 #include <linux/ipv6.h>
28 #include <net/ipv6.h>
29 #include <linux/tcp.h>
30 #include <linux/udp.h>
31 #include <linux/if_arp.h>
32 #include <linux/if_ether.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/skbuff.h>
37 #include <linux/rtnetlink.h>
38 #include <linux/if_vlan.h>
39 #include <linux/delay.h>
40 #include <linux/mm.h>
41 #include <linux/vmalloc.h>
42 #include <net/ip6_checksum.h>
43
44 #include "qlge.h"
45
46 char qlge_driver_name[] = DRV_NAME;
47 const char qlge_driver_version[] = DRV_VERSION;
48
49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
50 MODULE_DESCRIPTION(DRV_STRING " ");
51 MODULE_LICENSE("GPL");
52 MODULE_VERSION(DRV_VERSION);
53
54 static const u32 default_msg =
55     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
56 /* NETIF_MSG_TIMER |    */
57     NETIF_MSG_IFDOWN |
58     NETIF_MSG_IFUP |
59     NETIF_MSG_RX_ERR |
60     NETIF_MSG_TX_ERR |
61 /*  NETIF_MSG_TX_QUEUED | */
62 /*  NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS | */
63 /* NETIF_MSG_PKTDATA | */
64     NETIF_MSG_HW | NETIF_MSG_WOL | 0;
65
66 static int debug = 0x00007fff;  /* defaults above */
67 module_param(debug, int, 0);
68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
69
70 #define MSIX_IRQ 0
71 #define MSI_IRQ 1
72 #define LEG_IRQ 2
73 static int irq_type = MSIX_IRQ;
74 module_param(irq_type, int, MSIX_IRQ);
75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
76
77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
78         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8012)},
79         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8000)},
80         /* required last entry */
81         {0,}
82 };
83
84 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
85
86 /* This hardware semaphore causes exclusive access to
87  * resources shared between the NIC driver, MPI firmware,
88  * FCOE firmware and the FC driver.
89  */
90 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
91 {
92         u32 sem_bits = 0;
93
94         switch (sem_mask) {
95         case SEM_XGMAC0_MASK:
96                 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
97                 break;
98         case SEM_XGMAC1_MASK:
99                 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
100                 break;
101         case SEM_ICB_MASK:
102                 sem_bits = SEM_SET << SEM_ICB_SHIFT;
103                 break;
104         case SEM_MAC_ADDR_MASK:
105                 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
106                 break;
107         case SEM_FLASH_MASK:
108                 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
109                 break;
110         case SEM_PROBE_MASK:
111                 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
112                 break;
113         case SEM_RT_IDX_MASK:
114                 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
115                 break;
116         case SEM_PROC_REG_MASK:
117                 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
118                 break;
119         default:
120                 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
121                 return -EINVAL;
122         }
123
124         ql_write32(qdev, SEM, sem_bits | sem_mask);
125         return !(ql_read32(qdev, SEM) & sem_bits);
126 }
127
128 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
129 {
130         unsigned int wait_count = 30;
131         do {
132                 if (!ql_sem_trylock(qdev, sem_mask))
133                         return 0;
134                 udelay(100);
135         } while (--wait_count);
136         return -ETIMEDOUT;
137 }
138
139 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
140 {
141         ql_write32(qdev, SEM, sem_mask);
142         ql_read32(qdev, SEM);   /* flush */
143 }
144
145 /* This function waits for a specific bit to come ready
146  * in a given register.  It is used mostly by the initialize
147  * process, but is also used in kernel thread API such as
148  * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
149  */
150 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
151 {
152         u32 temp;
153         int count = UDELAY_COUNT;
154
155         while (count) {
156                 temp = ql_read32(qdev, reg);
157
158                 /* check for errors */
159                 if (temp & err_bit) {
160                         QPRINTK(qdev, PROBE, ALERT,
161                                 "register 0x%.08x access error, value = 0x%.08x!.\n",
162                                 reg, temp);
163                         return -EIO;
164                 } else if (temp & bit)
165                         return 0;
166                 udelay(UDELAY_DELAY);
167                 count--;
168         }
169         QPRINTK(qdev, PROBE, ALERT,
170                 "Timed out waiting for reg %x to come ready.\n", reg);
171         return -ETIMEDOUT;
172 }
173
174 /* The CFG register is used to download TX and RX control blocks
175  * to the chip. This function waits for an operation to complete.
176  */
177 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
178 {
179         int count = UDELAY_COUNT;
180         u32 temp;
181
182         while (count) {
183                 temp = ql_read32(qdev, CFG);
184                 if (temp & CFG_LE)
185                         return -EIO;
186                 if (!(temp & bit))
187                         return 0;
188                 udelay(UDELAY_DELAY);
189                 count--;
190         }
191         return -ETIMEDOUT;
192 }
193
194
195 /* Used to issue init control blocks to hw. Maps control block,
196  * sets address, triggers download, waits for completion.
197  */
198 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
199                  u16 q_id)
200 {
201         u64 map;
202         int status = 0;
203         int direction;
204         u32 mask;
205         u32 value;
206
207         direction =
208             (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
209             PCI_DMA_FROMDEVICE;
210
211         map = pci_map_single(qdev->pdev, ptr, size, direction);
212         if (pci_dma_mapping_error(qdev->pdev, map)) {
213                 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
214                 return -ENOMEM;
215         }
216
217         status = ql_wait_cfg(qdev, bit);
218         if (status) {
219                 QPRINTK(qdev, IFUP, ERR,
220                         "Timed out waiting for CFG to come ready.\n");
221                 goto exit;
222         }
223
224         status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
225         if (status)
226                 goto exit;
227         ql_write32(qdev, ICB_L, (u32) map);
228         ql_write32(qdev, ICB_H, (u32) (map >> 32));
229         ql_sem_unlock(qdev, SEM_ICB_MASK);      /* does flush too */
230
231         mask = CFG_Q_MASK | (bit << 16);
232         value = bit | (q_id << CFG_Q_SHIFT);
233         ql_write32(qdev, CFG, (mask | value));
234
235         /*
236          * Wait for the bit to clear after signaling hw.
237          */
238         status = ql_wait_cfg(qdev, bit);
239 exit:
240         pci_unmap_single(qdev->pdev, map, size, direction);
241         return status;
242 }
243
244 /* Get a specific MAC address from the CAM.  Used for debug and reg dump. */
245 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
246                         u32 *value)
247 {
248         u32 offset = 0;
249         int status;
250
251         switch (type) {
252         case MAC_ADDR_TYPE_MULTI_MAC:
253         case MAC_ADDR_TYPE_CAM_MAC:
254                 {
255                         status =
256                             ql_wait_reg_rdy(qdev,
257                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
258                         if (status)
259                                 goto exit;
260                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
261                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
262                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
263                         status =
264                             ql_wait_reg_rdy(qdev,
265                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
266                         if (status)
267                                 goto exit;
268                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
269                         status =
270                             ql_wait_reg_rdy(qdev,
271                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
272                         if (status)
273                                 goto exit;
274                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
275                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
276                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
277                         status =
278                             ql_wait_reg_rdy(qdev,
279                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
280                         if (status)
281                                 goto exit;
282                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
283                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
284                                 status =
285                                     ql_wait_reg_rdy(qdev,
286                                         MAC_ADDR_IDX, MAC_ADDR_MW, 0);
287                                 if (status)
288                                         goto exit;
289                                 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
290                                            (index << MAC_ADDR_IDX_SHIFT) | /* index */
291                                            MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
292                                 status =
293                                     ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
294                                                     MAC_ADDR_MR, 0);
295                                 if (status)
296                                         goto exit;
297                                 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
298                         }
299                         break;
300                 }
301         case MAC_ADDR_TYPE_VLAN:
302         case MAC_ADDR_TYPE_MULTI_FLTR:
303         default:
304                 QPRINTK(qdev, IFUP, CRIT,
305                         "Address type %d not yet supported.\n", type);
306                 status = -EPERM;
307         }
308 exit:
309         return status;
310 }
311
312 /* Set up a MAC, multicast or VLAN address for the
313  * inbound frame matching.
314  */
315 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
316                                u16 index)
317 {
318         u32 offset = 0;
319         int status = 0;
320
321         switch (type) {
322         case MAC_ADDR_TYPE_MULTI_MAC:
323         case MAC_ADDR_TYPE_CAM_MAC:
324                 {
325                         u32 cam_output;
326                         u32 upper = (addr[0] << 8) | addr[1];
327                         u32 lower =
328                             (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
329                             (addr[5]);
330
331                         QPRINTK(qdev, IFUP, DEBUG,
332                                 "Adding %s address %pM"
333                                 " at index %d in the CAM.\n",
334                                 ((type ==
335                                   MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
336                                  "UNICAST"), addr, index);
337
338                         status =
339                             ql_wait_reg_rdy(qdev,
340                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
341                         if (status)
342                                 goto exit;
343                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
344                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
345                                    type);       /* type */
346                         ql_write32(qdev, MAC_ADDR_DATA, lower);
347                         status =
348                             ql_wait_reg_rdy(qdev,
349                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
350                         if (status)
351                                 goto exit;
352                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
353                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
354                                    type);       /* type */
355                         ql_write32(qdev, MAC_ADDR_DATA, upper);
356                         status =
357                             ql_wait_reg_rdy(qdev,
358                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
359                         if (status)
360                                 goto exit;
361                         ql_write32(qdev, MAC_ADDR_IDX, (offset) |       /* offset */
362                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
363                                    type);       /* type */
364                         /* This field should also include the queue id
365                            and possibly the function id.  Right now we hardcode
366                            the route field to NIC core.
367                          */
368                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
369                                 cam_output = (CAM_OUT_ROUTE_NIC |
370                                               (qdev->
371                                                func << CAM_OUT_FUNC_SHIFT) |
372                                               (qdev->
373                                                rss_ring_first_cq_id <<
374                                                CAM_OUT_CQ_ID_SHIFT));
375                                 if (qdev->vlgrp)
376                                         cam_output |= CAM_OUT_RV;
377                                 /* route to NIC core */
378                                 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
379                         }
380                         break;
381                 }
382         case MAC_ADDR_TYPE_VLAN:
383                 {
384                         u32 enable_bit = *((u32 *) &addr[0]);
385                         /* For VLAN, the addr actually holds a bit that
386                          * either enables or disables the vlan id we are
387                          * addressing. It's either MAC_ADDR_E on or off.
388                          * That's bit-27 we're talking about.
389                          */
390                         QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
391                                 (enable_bit ? "Adding" : "Removing"),
392                                 index, (enable_bit ? "to" : "from"));
393
394                         status =
395                             ql_wait_reg_rdy(qdev,
396                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
397                         if (status)
398                                 goto exit;
399                         ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
400                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
401                                    type |       /* type */
402                                    enable_bit); /* enable/disable */
403                         break;
404                 }
405         case MAC_ADDR_TYPE_MULTI_FLTR:
406         default:
407                 QPRINTK(qdev, IFUP, CRIT,
408                         "Address type %d not yet supported.\n", type);
409                 status = -EPERM;
410         }
411 exit:
412         return status;
413 }
414
415 /* Get a specific frame routing value from the CAM.
416  * Used for debug and reg dump.
417  */
418 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
419 {
420         int status = 0;
421
422         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
423         if (status)
424                 goto exit;
425
426         ql_write32(qdev, RT_IDX,
427                    RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
428         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
429         if (status)
430                 goto exit;
431         *value = ql_read32(qdev, RT_DATA);
432 exit:
433         return status;
434 }
435
436 /* The NIC function for this chip has 16 routing indexes.  Each one can be used
437  * to route different frame types to various inbound queues.  We send broadcast/
438  * multicast/error frames to the default queue for slow handling,
439  * and CAM hit/RSS frames to the fast handling queues.
440  */
441 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
442                               int enable)
443 {
444         int status = -EINVAL; /* Return error if no mask match. */
445         u32 value = 0;
446
447         QPRINTK(qdev, IFUP, DEBUG,
448                 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
449                 (enable ? "Adding" : "Removing"),
450                 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
451                 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
452                 ((index ==
453                   RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
454                 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
455                 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
456                 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
457                 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
458                 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
459                 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
460                 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
461                 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
462                 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
463                 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
464                 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
465                 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
466                 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
467                 (enable ? "to" : "from"));
468
469         switch (mask) {
470         case RT_IDX_CAM_HIT:
471                 {
472                         value = RT_IDX_DST_CAM_Q |      /* dest */
473                             RT_IDX_TYPE_NICQ |  /* type */
474                             (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
475                         break;
476                 }
477         case RT_IDX_VALID:      /* Promiscuous Mode frames. */
478                 {
479                         value = RT_IDX_DST_DFLT_Q |     /* dest */
480                             RT_IDX_TYPE_NICQ |  /* type */
481                             (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
482                         break;
483                 }
484         case RT_IDX_ERR:        /* Pass up MAC,IP,TCP/UDP error frames. */
485                 {
486                         value = RT_IDX_DST_DFLT_Q |     /* dest */
487                             RT_IDX_TYPE_NICQ |  /* type */
488                             (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
489                         break;
490                 }
491         case RT_IDX_BCAST:      /* Pass up Broadcast frames to default Q. */
492                 {
493                         value = RT_IDX_DST_DFLT_Q |     /* dest */
494                             RT_IDX_TYPE_NICQ |  /* type */
495                             (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
496                         break;
497                 }
498         case RT_IDX_MCAST:      /* Pass up All Multicast frames. */
499                 {
500                         value = RT_IDX_DST_CAM_Q |      /* dest */
501                             RT_IDX_TYPE_NICQ |  /* type */
502                             (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
503                         break;
504                 }
505         case RT_IDX_MCAST_MATCH:        /* Pass up matched Multicast frames. */
506                 {
507                         value = RT_IDX_DST_CAM_Q |      /* dest */
508                             RT_IDX_TYPE_NICQ |  /* type */
509                             (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
510                         break;
511                 }
512         case RT_IDX_RSS_MATCH:  /* Pass up matched RSS frames. */
513                 {
514                         value = RT_IDX_DST_RSS |        /* dest */
515                             RT_IDX_TYPE_NICQ |  /* type */
516                             (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
517                         break;
518                 }
519         case 0:         /* Clear the E-bit on an entry. */
520                 {
521                         value = RT_IDX_DST_DFLT_Q |     /* dest */
522                             RT_IDX_TYPE_NICQ |  /* type */
523                             (index << RT_IDX_IDX_SHIFT);/* index */
524                         break;
525                 }
526         default:
527                 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
528                         mask);
529                 status = -EPERM;
530                 goto exit;
531         }
532
533         if (value) {
534                 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
535                 if (status)
536                         goto exit;
537                 value |= (enable ? RT_IDX_E : 0);
538                 ql_write32(qdev, RT_IDX, value);
539                 ql_write32(qdev, RT_DATA, enable ? mask : 0);
540         }
541 exit:
542         return status;
543 }
544
545 static void ql_enable_interrupts(struct ql_adapter *qdev)
546 {
547         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
548 }
549
550 static void ql_disable_interrupts(struct ql_adapter *qdev)
551 {
552         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
553 }
554
555 /* If we're running with multiple MSI-X vectors then we enable on the fly.
556  * Otherwise, we may have multiple outstanding workers and don't want to
557  * enable until the last one finishes. In this case, the irq_cnt gets
558  * incremented everytime we queue a worker and decremented everytime
559  * a worker finishes.  Once it hits zero we enable the interrupt.
560  */
561 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
562 {
563         u32 var = 0;
564         unsigned long hw_flags = 0;
565         struct intr_context *ctx = qdev->intr_context + intr;
566
567         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
568                 /* Always enable if we're MSIX multi interrupts and
569                  * it's not the default (zeroeth) interrupt.
570                  */
571                 ql_write32(qdev, INTR_EN,
572                            ctx->intr_en_mask);
573                 var = ql_read32(qdev, STS);
574                 return var;
575         }
576
577         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
578         if (atomic_dec_and_test(&ctx->irq_cnt)) {
579                 ql_write32(qdev, INTR_EN,
580                            ctx->intr_en_mask);
581                 var = ql_read32(qdev, STS);
582         }
583         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
584         return var;
585 }
586
587 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
588 {
589         u32 var = 0;
590         struct intr_context *ctx;
591
592         /* HW disables for us if we're MSIX multi interrupts and
593          * it's not the default (zeroeth) interrupt.
594          */
595         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
596                 return 0;
597
598         ctx = qdev->intr_context + intr;
599         spin_lock(&qdev->hw_lock);
600         if (!atomic_read(&ctx->irq_cnt)) {
601                 ql_write32(qdev, INTR_EN,
602                 ctx->intr_dis_mask);
603                 var = ql_read32(qdev, STS);
604         }
605         atomic_inc(&ctx->irq_cnt);
606         spin_unlock(&qdev->hw_lock);
607         return var;
608 }
609
610 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
611 {
612         int i;
613         for (i = 0; i < qdev->intr_count; i++) {
614                 /* The enable call does a atomic_dec_and_test
615                  * and enables only if the result is zero.
616                  * So we precharge it here.
617                  */
618                 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
619                         i == 0))
620                         atomic_set(&qdev->intr_context[i].irq_cnt, 1);
621                 ql_enable_completion_interrupt(qdev, i);
622         }
623
624 }
625
626 static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str)
627 {
628         int status, i;
629         u16 csum = 0;
630         __le16 *flash = (__le16 *)&qdev->flash;
631
632         status = strncmp((char *)&qdev->flash, str, 4);
633         if (status) {
634                 QPRINTK(qdev, IFUP, ERR, "Invalid flash signature.\n");
635                 return  status;
636         }
637
638         for (i = 0; i < size; i++)
639                 csum += le16_to_cpu(*flash++);
640
641         if (csum)
642                 QPRINTK(qdev, IFUP, ERR,
643                         "Invalid flash checksum, csum = 0x%.04x.\n", csum);
644
645         return csum;
646 }
647
648 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
649 {
650         int status = 0;
651         /* wait for reg to come ready */
652         status = ql_wait_reg_rdy(qdev,
653                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
654         if (status)
655                 goto exit;
656         /* set up for reg read */
657         ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
658         /* wait for reg to come ready */
659         status = ql_wait_reg_rdy(qdev,
660                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
661         if (status)
662                 goto exit;
663          /* This data is stored on flash as an array of
664          * __le32.  Since ql_read32() returns cpu endian
665          * we need to swap it back.
666          */
667         *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
668 exit:
669         return status;
670 }
671
672 static int ql_get_8000_flash_params(struct ql_adapter *qdev)
673 {
674         u32 i, size;
675         int status;
676         __le32 *p = (__le32 *)&qdev->flash;
677         u32 offset;
678
679         /* Get flash offset for function and adjust
680          * for dword access.
681          */
682         if (!qdev->func)
683                 offset = FUNC0_FLASH_OFFSET / sizeof(u32);
684         else
685                 offset = FUNC1_FLASH_OFFSET / sizeof(u32);
686
687         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
688                 return -ETIMEDOUT;
689
690         size = sizeof(struct flash_params_8000) / sizeof(u32);
691         for (i = 0; i < size; i++, p++) {
692                 status = ql_read_flash_word(qdev, i+offset, p);
693                 if (status) {
694                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
695                         goto exit;
696                 }
697         }
698
699         status = ql_validate_flash(qdev,
700                         sizeof(struct flash_params_8000) / sizeof(u16),
701                         "8000");
702         if (status) {
703                 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
704                 status = -EINVAL;
705                 goto exit;
706         }
707
708         if (!is_valid_ether_addr(qdev->flash.flash_params_8000.mac_addr)) {
709                 QPRINTK(qdev, IFUP, ERR, "Invalid MAC address.\n");
710                 status = -EINVAL;
711                 goto exit;
712         }
713
714         memcpy(qdev->ndev->dev_addr,
715                 qdev->flash.flash_params_8000.mac_addr,
716                 qdev->ndev->addr_len);
717
718 exit:
719         ql_sem_unlock(qdev, SEM_FLASH_MASK);
720         return status;
721 }
722
723 static int ql_get_8012_flash_params(struct ql_adapter *qdev)
724 {
725         int i;
726         int status;
727         __le32 *p = (__le32 *)&qdev->flash;
728         u32 offset = 0;
729         u32 size = sizeof(struct flash_params_8012) / sizeof(u32);
730
731         /* Second function's parameters follow the first
732          * function's.
733          */
734         if (qdev->func)
735                 offset = size;
736
737         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
738                 return -ETIMEDOUT;
739
740         for (i = 0; i < size; i++, p++) {
741                 status = ql_read_flash_word(qdev, i+offset, p);
742                 if (status) {
743                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
744                         goto exit;
745                 }
746
747         }
748
749         status = ql_validate_flash(qdev,
750                         sizeof(struct flash_params_8012) / sizeof(u16),
751                         "8012");
752         if (status) {
753                 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
754                 status = -EINVAL;
755                 goto exit;
756         }
757
758         if (!is_valid_ether_addr(qdev->flash.flash_params_8012.mac_addr)) {
759                 status = -EINVAL;
760                 goto exit;
761         }
762
763         memcpy(qdev->ndev->dev_addr,
764                 qdev->flash.flash_params_8012.mac_addr,
765                 qdev->ndev->addr_len);
766
767 exit:
768         ql_sem_unlock(qdev, SEM_FLASH_MASK);
769         return status;
770 }
771
772 /* xgmac register are located behind the xgmac_addr and xgmac_data
773  * register pair.  Each read/write requires us to wait for the ready
774  * bit before reading/writing the data.
775  */
776 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
777 {
778         int status;
779         /* wait for reg to come ready */
780         status = ql_wait_reg_rdy(qdev,
781                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
782         if (status)
783                 return status;
784         /* write the data to the data reg */
785         ql_write32(qdev, XGMAC_DATA, data);
786         /* trigger the write */
787         ql_write32(qdev, XGMAC_ADDR, reg);
788         return status;
789 }
790
791 /* xgmac register are located behind the xgmac_addr and xgmac_data
792  * register pair.  Each read/write requires us to wait for the ready
793  * bit before reading/writing the data.
794  */
795 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
796 {
797         int status = 0;
798         /* wait for reg to come ready */
799         status = ql_wait_reg_rdy(qdev,
800                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
801         if (status)
802                 goto exit;
803         /* set up for reg read */
804         ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
805         /* wait for reg to come ready */
806         status = ql_wait_reg_rdy(qdev,
807                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
808         if (status)
809                 goto exit;
810         /* get the data */
811         *data = ql_read32(qdev, XGMAC_DATA);
812 exit:
813         return status;
814 }
815
816 /* This is used for reading the 64-bit statistics regs. */
817 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
818 {
819         int status = 0;
820         u32 hi = 0;
821         u32 lo = 0;
822
823         status = ql_read_xgmac_reg(qdev, reg, &lo);
824         if (status)
825                 goto exit;
826
827         status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
828         if (status)
829                 goto exit;
830
831         *data = (u64) lo | ((u64) hi << 32);
832
833 exit:
834         return status;
835 }
836
837 static int ql_8000_port_initialize(struct ql_adapter *qdev)
838 {
839         int status;
840         status = ql_mb_get_fw_state(qdev);
841         if (status)
842                 goto exit;
843         /* Wake up a worker to get/set the TX/RX frame sizes. */
844         queue_delayed_work(qdev->workqueue, &qdev->mpi_port_cfg_work, 0);
845 exit:
846         return status;
847 }
848
849 /* Take the MAC Core out of reset.
850  * Enable statistics counting.
851  * Take the transmitter/receiver out of reset.
852  * This functionality may be done in the MPI firmware at a
853  * later date.
854  */
855 static int ql_8012_port_initialize(struct ql_adapter *qdev)
856 {
857         int status = 0;
858         u32 data;
859
860         if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
861                 /* Another function has the semaphore, so
862                  * wait for the port init bit to come ready.
863                  */
864                 QPRINTK(qdev, LINK, INFO,
865                         "Another function has the semaphore, so wait for the port init bit to come ready.\n");
866                 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
867                 if (status) {
868                         QPRINTK(qdev, LINK, CRIT,
869                                 "Port initialize timed out.\n");
870                 }
871                 return status;
872         }
873
874         QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
875         /* Set the core reset. */
876         status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
877         if (status)
878                 goto end;
879         data |= GLOBAL_CFG_RESET;
880         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
881         if (status)
882                 goto end;
883
884         /* Clear the core reset and turn on jumbo for receiver. */
885         data &= ~GLOBAL_CFG_RESET;      /* Clear core reset. */
886         data |= GLOBAL_CFG_JUMBO;       /* Turn on jumbo. */
887         data |= GLOBAL_CFG_TX_STAT_EN;
888         data |= GLOBAL_CFG_RX_STAT_EN;
889         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
890         if (status)
891                 goto end;
892
893         /* Enable transmitter, and clear it's reset. */
894         status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
895         if (status)
896                 goto end;
897         data &= ~TX_CFG_RESET;  /* Clear the TX MAC reset. */
898         data |= TX_CFG_EN;      /* Enable the transmitter. */
899         status = ql_write_xgmac_reg(qdev, TX_CFG, data);
900         if (status)
901                 goto end;
902
903         /* Enable receiver and clear it's reset. */
904         status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
905         if (status)
906                 goto end;
907         data &= ~RX_CFG_RESET;  /* Clear the RX MAC reset. */
908         data |= RX_CFG_EN;      /* Enable the receiver. */
909         status = ql_write_xgmac_reg(qdev, RX_CFG, data);
910         if (status)
911                 goto end;
912
913         /* Turn on jumbo. */
914         status =
915             ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
916         if (status)
917                 goto end;
918         status =
919             ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
920         if (status)
921                 goto end;
922
923         /* Signal to the world that the port is enabled.        */
924         ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
925 end:
926         ql_sem_unlock(qdev, qdev->xg_sem_mask);
927         return status;
928 }
929
930 /* Get the next large buffer. */
931 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
932 {
933         struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
934         rx_ring->lbq_curr_idx++;
935         if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
936                 rx_ring->lbq_curr_idx = 0;
937         rx_ring->lbq_free_cnt++;
938         return lbq_desc;
939 }
940
941 /* Get the next small buffer. */
942 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
943 {
944         struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
945         rx_ring->sbq_curr_idx++;
946         if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
947                 rx_ring->sbq_curr_idx = 0;
948         rx_ring->sbq_free_cnt++;
949         return sbq_desc;
950 }
951
952 /* Update an rx ring index. */
953 static void ql_update_cq(struct rx_ring *rx_ring)
954 {
955         rx_ring->cnsmr_idx++;
956         rx_ring->curr_entry++;
957         if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
958                 rx_ring->cnsmr_idx = 0;
959                 rx_ring->curr_entry = rx_ring->cq_base;
960         }
961 }
962
963 static void ql_write_cq_idx(struct rx_ring *rx_ring)
964 {
965         ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
966 }
967
968 /* Process (refill) a large buffer queue. */
969 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
970 {
971         u32 clean_idx = rx_ring->lbq_clean_idx;
972         u32 start_idx = clean_idx;
973         struct bq_desc *lbq_desc;
974         u64 map;
975         int i;
976
977         while (rx_ring->lbq_free_cnt > 16) {
978                 for (i = 0; i < 16; i++) {
979                         QPRINTK(qdev, RX_STATUS, DEBUG,
980                                 "lbq: try cleaning clean_idx = %d.\n",
981                                 clean_idx);
982                         lbq_desc = &rx_ring->lbq[clean_idx];
983                         if (lbq_desc->p.lbq_page == NULL) {
984                                 QPRINTK(qdev, RX_STATUS, DEBUG,
985                                         "lbq: getting new page for index %d.\n",
986                                         lbq_desc->index);
987                                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
988                                 if (lbq_desc->p.lbq_page == NULL) {
989                                         rx_ring->lbq_clean_idx = clean_idx;
990                                         QPRINTK(qdev, RX_STATUS, ERR,
991                                                 "Couldn't get a page.\n");
992                                         return;
993                                 }
994                                 map = pci_map_page(qdev->pdev,
995                                                    lbq_desc->p.lbq_page,
996                                                    0, PAGE_SIZE,
997                                                    PCI_DMA_FROMDEVICE);
998                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
999                                         rx_ring->lbq_clean_idx = clean_idx;
1000                                         put_page(lbq_desc->p.lbq_page);
1001                                         lbq_desc->p.lbq_page = NULL;
1002                                         QPRINTK(qdev, RX_STATUS, ERR,
1003                                                 "PCI mapping failed.\n");
1004                                         return;
1005                                 }
1006                                 pci_unmap_addr_set(lbq_desc, mapaddr, map);
1007                                 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
1008                                 *lbq_desc->addr = cpu_to_le64(map);
1009                         }
1010                         clean_idx++;
1011                         if (clean_idx == rx_ring->lbq_len)
1012                                 clean_idx = 0;
1013                 }
1014
1015                 rx_ring->lbq_clean_idx = clean_idx;
1016                 rx_ring->lbq_prod_idx += 16;
1017                 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
1018                         rx_ring->lbq_prod_idx = 0;
1019                 rx_ring->lbq_free_cnt -= 16;
1020         }
1021
1022         if (start_idx != clean_idx) {
1023                 QPRINTK(qdev, RX_STATUS, DEBUG,
1024                         "lbq: updating prod idx = %d.\n",
1025                         rx_ring->lbq_prod_idx);
1026                 ql_write_db_reg(rx_ring->lbq_prod_idx,
1027                                 rx_ring->lbq_prod_idx_db_reg);
1028         }
1029 }
1030
1031 /* Process (refill) a small buffer queue. */
1032 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1033 {
1034         u32 clean_idx = rx_ring->sbq_clean_idx;
1035         u32 start_idx = clean_idx;
1036         struct bq_desc *sbq_desc;
1037         u64 map;
1038         int i;
1039
1040         while (rx_ring->sbq_free_cnt > 16) {
1041                 for (i = 0; i < 16; i++) {
1042                         sbq_desc = &rx_ring->sbq[clean_idx];
1043                         QPRINTK(qdev, RX_STATUS, DEBUG,
1044                                 "sbq: try cleaning clean_idx = %d.\n",
1045                                 clean_idx);
1046                         if (sbq_desc->p.skb == NULL) {
1047                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1048                                         "sbq: getting new skb for index %d.\n",
1049                                         sbq_desc->index);
1050                                 sbq_desc->p.skb =
1051                                     netdev_alloc_skb(qdev->ndev,
1052                                                      rx_ring->sbq_buf_size);
1053                                 if (sbq_desc->p.skb == NULL) {
1054                                         QPRINTK(qdev, PROBE, ERR,
1055                                                 "Couldn't get an skb.\n");
1056                                         rx_ring->sbq_clean_idx = clean_idx;
1057                                         return;
1058                                 }
1059                                 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
1060                                 map = pci_map_single(qdev->pdev,
1061                                                      sbq_desc->p.skb->data,
1062                                                      rx_ring->sbq_buf_size /
1063                                                      2, PCI_DMA_FROMDEVICE);
1064                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
1065                                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
1066                                         rx_ring->sbq_clean_idx = clean_idx;
1067                                         dev_kfree_skb_any(sbq_desc->p.skb);
1068                                         sbq_desc->p.skb = NULL;
1069                                         return;
1070                                 }
1071                                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
1072                                 pci_unmap_len_set(sbq_desc, maplen,
1073                                                   rx_ring->sbq_buf_size / 2);
1074                                 *sbq_desc->addr = cpu_to_le64(map);
1075                         }
1076
1077                         clean_idx++;
1078                         if (clean_idx == rx_ring->sbq_len)
1079                                 clean_idx = 0;
1080                 }
1081                 rx_ring->sbq_clean_idx = clean_idx;
1082                 rx_ring->sbq_prod_idx += 16;
1083                 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
1084                         rx_ring->sbq_prod_idx = 0;
1085                 rx_ring->sbq_free_cnt -= 16;
1086         }
1087
1088         if (start_idx != clean_idx) {
1089                 QPRINTK(qdev, RX_STATUS, DEBUG,
1090                         "sbq: updating prod idx = %d.\n",
1091                         rx_ring->sbq_prod_idx);
1092                 ql_write_db_reg(rx_ring->sbq_prod_idx,
1093                                 rx_ring->sbq_prod_idx_db_reg);
1094         }
1095 }
1096
1097 static void ql_update_buffer_queues(struct ql_adapter *qdev,
1098                                     struct rx_ring *rx_ring)
1099 {
1100         ql_update_sbq(qdev, rx_ring);
1101         ql_update_lbq(qdev, rx_ring);
1102 }
1103
1104 /* Unmaps tx buffers.  Can be called from send() if a pci mapping
1105  * fails at some stage, or from the interrupt when a tx completes.
1106  */
1107 static void ql_unmap_send(struct ql_adapter *qdev,
1108                           struct tx_ring_desc *tx_ring_desc, int mapped)
1109 {
1110         int i;
1111         for (i = 0; i < mapped; i++) {
1112                 if (i == 0 || (i == 7 && mapped > 7)) {
1113                         /*
1114                          * Unmap the skb->data area, or the
1115                          * external sglist (AKA the Outbound
1116                          * Address List (OAL)).
1117                          * If its the zeroeth element, then it's
1118                          * the skb->data area.  If it's the 7th
1119                          * element and there is more than 6 frags,
1120                          * then its an OAL.
1121                          */
1122                         if (i == 7) {
1123                                 QPRINTK(qdev, TX_DONE, DEBUG,
1124                                         "unmapping OAL area.\n");
1125                         }
1126                         pci_unmap_single(qdev->pdev,
1127                                          pci_unmap_addr(&tx_ring_desc->map[i],
1128                                                         mapaddr),
1129                                          pci_unmap_len(&tx_ring_desc->map[i],
1130                                                        maplen),
1131                                          PCI_DMA_TODEVICE);
1132                 } else {
1133                         QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1134                                 i);
1135                         pci_unmap_page(qdev->pdev,
1136                                        pci_unmap_addr(&tx_ring_desc->map[i],
1137                                                       mapaddr),
1138                                        pci_unmap_len(&tx_ring_desc->map[i],
1139                                                      maplen), PCI_DMA_TODEVICE);
1140                 }
1141         }
1142
1143 }
1144
1145 /* Map the buffers for this transmit.  This will return
1146  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1147  */
1148 static int ql_map_send(struct ql_adapter *qdev,
1149                        struct ob_mac_iocb_req *mac_iocb_ptr,
1150                        struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1151 {
1152         int len = skb_headlen(skb);
1153         dma_addr_t map;
1154         int frag_idx, err, map_idx = 0;
1155         struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1156         int frag_cnt = skb_shinfo(skb)->nr_frags;
1157
1158         if (frag_cnt) {
1159                 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1160         }
1161         /*
1162          * Map the skb buffer first.
1163          */
1164         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1165
1166         err = pci_dma_mapping_error(qdev->pdev, map);
1167         if (err) {
1168                 QPRINTK(qdev, TX_QUEUED, ERR,
1169                         "PCI mapping failed with error: %d\n", err);
1170
1171                 return NETDEV_TX_BUSY;
1172         }
1173
1174         tbd->len = cpu_to_le32(len);
1175         tbd->addr = cpu_to_le64(map);
1176         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1177         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1178         map_idx++;
1179
1180         /*
1181          * This loop fills the remainder of the 8 address descriptors
1182          * in the IOCB.  If there are more than 7 fragments, then the
1183          * eighth address desc will point to an external list (OAL).
1184          * When this happens, the remainder of the frags will be stored
1185          * in this list.
1186          */
1187         for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1188                 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1189                 tbd++;
1190                 if (frag_idx == 6 && frag_cnt > 7) {
1191                         /* Let's tack on an sglist.
1192                          * Our control block will now
1193                          * look like this:
1194                          * iocb->seg[0] = skb->data
1195                          * iocb->seg[1] = frag[0]
1196                          * iocb->seg[2] = frag[1]
1197                          * iocb->seg[3] = frag[2]
1198                          * iocb->seg[4] = frag[3]
1199                          * iocb->seg[5] = frag[4]
1200                          * iocb->seg[6] = frag[5]
1201                          * iocb->seg[7] = ptr to OAL (external sglist)
1202                          * oal->seg[0] = frag[6]
1203                          * oal->seg[1] = frag[7]
1204                          * oal->seg[2] = frag[8]
1205                          * oal->seg[3] = frag[9]
1206                          * oal->seg[4] = frag[10]
1207                          *      etc...
1208                          */
1209                         /* Tack on the OAL in the eighth segment of IOCB. */
1210                         map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1211                                              sizeof(struct oal),
1212                                              PCI_DMA_TODEVICE);
1213                         err = pci_dma_mapping_error(qdev->pdev, map);
1214                         if (err) {
1215                                 QPRINTK(qdev, TX_QUEUED, ERR,
1216                                         "PCI mapping outbound address list with error: %d\n",
1217                                         err);
1218                                 goto map_error;
1219                         }
1220
1221                         tbd->addr = cpu_to_le64(map);
1222                         /*
1223                          * The length is the number of fragments
1224                          * that remain to be mapped times the length
1225                          * of our sglist (OAL).
1226                          */
1227                         tbd->len =
1228                             cpu_to_le32((sizeof(struct tx_buf_desc) *
1229                                          (frag_cnt - frag_idx)) | TX_DESC_C);
1230                         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1231                                            map);
1232                         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1233                                           sizeof(struct oal));
1234                         tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1235                         map_idx++;
1236                 }
1237
1238                 map =
1239                     pci_map_page(qdev->pdev, frag->page,
1240                                  frag->page_offset, frag->size,
1241                                  PCI_DMA_TODEVICE);
1242
1243                 err = pci_dma_mapping_error(qdev->pdev, map);
1244                 if (err) {
1245                         QPRINTK(qdev, TX_QUEUED, ERR,
1246                                 "PCI mapping frags failed with error: %d.\n",
1247                                 err);
1248                         goto map_error;
1249                 }
1250
1251                 tbd->addr = cpu_to_le64(map);
1252                 tbd->len = cpu_to_le32(frag->size);
1253                 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1254                 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1255                                   frag->size);
1256
1257         }
1258         /* Save the number of segments we've mapped. */
1259         tx_ring_desc->map_cnt = map_idx;
1260         /* Terminate the last segment. */
1261         tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1262         return NETDEV_TX_OK;
1263
1264 map_error:
1265         /*
1266          * If the first frag mapping failed, then i will be zero.
1267          * This causes the unmap of the skb->data area.  Otherwise
1268          * we pass in the number of frags that mapped successfully
1269          * so they can be umapped.
1270          */
1271         ql_unmap_send(qdev, tx_ring_desc, map_idx);
1272         return NETDEV_TX_BUSY;
1273 }
1274
1275 static void ql_realign_skb(struct sk_buff *skb, int len)
1276 {
1277         void *temp_addr = skb->data;
1278
1279         /* Undo the skb_reserve(skb,32) we did before
1280          * giving to hardware, and realign data on
1281          * a 2-byte boundary.
1282          */
1283         skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1284         skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1285         skb_copy_to_linear_data(skb, temp_addr,
1286                 (unsigned int)len);
1287 }
1288
1289 /*
1290  * This function builds an skb for the given inbound
1291  * completion.  It will be rewritten for readability in the near
1292  * future, but for not it works well.
1293  */
1294 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1295                                        struct rx_ring *rx_ring,
1296                                        struct ib_mac_iocb_rsp *ib_mac_rsp)
1297 {
1298         struct bq_desc *lbq_desc;
1299         struct bq_desc *sbq_desc;
1300         struct sk_buff *skb = NULL;
1301         u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1302        u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1303
1304         /*
1305          * Handle the header buffer if present.
1306          */
1307         if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1308             ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1309                 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1310                 /*
1311                  * Headers fit nicely into a small buffer.
1312                  */
1313                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1314                 pci_unmap_single(qdev->pdev,
1315                                 pci_unmap_addr(sbq_desc, mapaddr),
1316                                 pci_unmap_len(sbq_desc, maplen),
1317                                 PCI_DMA_FROMDEVICE);
1318                 skb = sbq_desc->p.skb;
1319                 ql_realign_skb(skb, hdr_len);
1320                 skb_put(skb, hdr_len);
1321                 sbq_desc->p.skb = NULL;
1322         }
1323
1324         /*
1325          * Handle the data buffer(s).
1326          */
1327         if (unlikely(!length)) {        /* Is there data too? */
1328                 QPRINTK(qdev, RX_STATUS, DEBUG,
1329                         "No Data buffer in this packet.\n");
1330                 return skb;
1331         }
1332
1333         if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1334                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1335                         QPRINTK(qdev, RX_STATUS, DEBUG,
1336                                 "Headers in small, data of %d bytes in small, combine them.\n", length);
1337                         /*
1338                          * Data is less than small buffer size so it's
1339                          * stuffed in a small buffer.
1340                          * For this case we append the data
1341                          * from the "data" small buffer to the "header" small
1342                          * buffer.
1343                          */
1344                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1345                         pci_dma_sync_single_for_cpu(qdev->pdev,
1346                                                     pci_unmap_addr
1347                                                     (sbq_desc, mapaddr),
1348                                                     pci_unmap_len
1349                                                     (sbq_desc, maplen),
1350                                                     PCI_DMA_FROMDEVICE);
1351                         memcpy(skb_put(skb, length),
1352                                sbq_desc->p.skb->data, length);
1353                         pci_dma_sync_single_for_device(qdev->pdev,
1354                                                        pci_unmap_addr
1355                                                        (sbq_desc,
1356                                                         mapaddr),
1357                                                        pci_unmap_len
1358                                                        (sbq_desc,
1359                                                         maplen),
1360                                                        PCI_DMA_FROMDEVICE);
1361                 } else {
1362                         QPRINTK(qdev, RX_STATUS, DEBUG,
1363                                 "%d bytes in a single small buffer.\n", length);
1364                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1365                         skb = sbq_desc->p.skb;
1366                         ql_realign_skb(skb, length);
1367                         skb_put(skb, length);
1368                         pci_unmap_single(qdev->pdev,
1369                                          pci_unmap_addr(sbq_desc,
1370                                                         mapaddr),
1371                                          pci_unmap_len(sbq_desc,
1372                                                        maplen),
1373                                          PCI_DMA_FROMDEVICE);
1374                         sbq_desc->p.skb = NULL;
1375                 }
1376         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1377                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1378                         QPRINTK(qdev, RX_STATUS, DEBUG,
1379                                 "Header in small, %d bytes in large. Chain large to small!\n", length);
1380                         /*
1381                          * The data is in a single large buffer.  We
1382                          * chain it to the header buffer's skb and let
1383                          * it rip.
1384                          */
1385                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1386                         pci_unmap_page(qdev->pdev,
1387                                        pci_unmap_addr(lbq_desc,
1388                                                       mapaddr),
1389                                        pci_unmap_len(lbq_desc, maplen),
1390                                        PCI_DMA_FROMDEVICE);
1391                         QPRINTK(qdev, RX_STATUS, DEBUG,
1392                                 "Chaining page to skb.\n");
1393                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1394                                            0, length);
1395                         skb->len += length;
1396                         skb->data_len += length;
1397                         skb->truesize += length;
1398                         lbq_desc->p.lbq_page = NULL;
1399                 } else {
1400                         /*
1401                          * The headers and data are in a single large buffer. We
1402                          * copy it to a new skb and let it go. This can happen with
1403                          * jumbo mtu on a non-TCP/UDP frame.
1404                          */
1405                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1406                         skb = netdev_alloc_skb(qdev->ndev, length);
1407                         if (skb == NULL) {
1408                                 QPRINTK(qdev, PROBE, DEBUG,
1409                                         "No skb available, drop the packet.\n");
1410                                 return NULL;
1411                         }
1412                         pci_unmap_page(qdev->pdev,
1413                                        pci_unmap_addr(lbq_desc,
1414                                                       mapaddr),
1415                                        pci_unmap_len(lbq_desc, maplen),
1416                                        PCI_DMA_FROMDEVICE);
1417                         skb_reserve(skb, NET_IP_ALIGN);
1418                         QPRINTK(qdev, RX_STATUS, DEBUG,
1419                                 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1420                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1421                                            0, length);
1422                         skb->len += length;
1423                         skb->data_len += length;
1424                         skb->truesize += length;
1425                         length -= length;
1426                         lbq_desc->p.lbq_page = NULL;
1427                         __pskb_pull_tail(skb,
1428                                 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1429                                 VLAN_ETH_HLEN : ETH_HLEN);
1430                 }
1431         } else {
1432                 /*
1433                  * The data is in a chain of large buffers
1434                  * pointed to by a small buffer.  We loop
1435                  * thru and chain them to the our small header
1436                  * buffer's skb.
1437                  * frags:  There are 18 max frags and our small
1438                  *         buffer will hold 32 of them. The thing is,
1439                  *         we'll use 3 max for our 9000 byte jumbo
1440                  *         frames.  If the MTU goes up we could
1441                  *          eventually be in trouble.
1442                  */
1443                 int size, offset, i = 0;
1444                 __le64 *bq, bq_array[8];
1445                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1446                 pci_unmap_single(qdev->pdev,
1447                                  pci_unmap_addr(sbq_desc, mapaddr),
1448                                  pci_unmap_len(sbq_desc, maplen),
1449                                  PCI_DMA_FROMDEVICE);
1450                 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1451                         /*
1452                          * This is an non TCP/UDP IP frame, so
1453                          * the headers aren't split into a small
1454                          * buffer.  We have to use the small buffer
1455                          * that contains our sg list as our skb to
1456                          * send upstairs. Copy the sg list here to
1457                          * a local buffer and use it to find the
1458                          * pages to chain.
1459                          */
1460                         QPRINTK(qdev, RX_STATUS, DEBUG,
1461                                 "%d bytes of headers & data in chain of large.\n", length);
1462                         skb = sbq_desc->p.skb;
1463                         bq = &bq_array[0];
1464                         memcpy(bq, skb->data, sizeof(bq_array));
1465                         sbq_desc->p.skb = NULL;
1466                         skb_reserve(skb, NET_IP_ALIGN);
1467                 } else {
1468                         QPRINTK(qdev, RX_STATUS, DEBUG,
1469                                 "Headers in small, %d bytes of data in chain of large.\n", length);
1470                         bq = (__le64 *)sbq_desc->p.skb->data;
1471                 }
1472                 while (length > 0) {
1473                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1474                         pci_unmap_page(qdev->pdev,
1475                                        pci_unmap_addr(lbq_desc,
1476                                                       mapaddr),
1477                                        pci_unmap_len(lbq_desc,
1478                                                      maplen),
1479                                        PCI_DMA_FROMDEVICE);
1480                         size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1481                         offset = 0;
1482
1483                         QPRINTK(qdev, RX_STATUS, DEBUG,
1484                                 "Adding page %d to skb for %d bytes.\n",
1485                                 i, size);
1486                         skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1487                                            offset, size);
1488                         skb->len += size;
1489                         skb->data_len += size;
1490                         skb->truesize += size;
1491                         length -= size;
1492                         lbq_desc->p.lbq_page = NULL;
1493                         bq++;
1494                         i++;
1495                 }
1496                 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1497                                 VLAN_ETH_HLEN : ETH_HLEN);
1498         }
1499         return skb;
1500 }
1501
1502 /* Process an inbound completion from an rx ring. */
1503 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1504                                    struct rx_ring *rx_ring,
1505                                    struct ib_mac_iocb_rsp *ib_mac_rsp)
1506 {
1507         struct net_device *ndev = qdev->ndev;
1508         struct sk_buff *skb = NULL;
1509         u16 vlan_id = (le16_to_cpu(ib_mac_rsp->vlan_id) &
1510                         IB_MAC_IOCB_RSP_VLAN_MASK)
1511
1512         QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1513
1514         skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1515         if (unlikely(!skb)) {
1516                 QPRINTK(qdev, RX_STATUS, DEBUG,
1517                         "No skb available, drop packet.\n");
1518                 return;
1519         }
1520
1521         prefetch(skb->data);
1522         skb->dev = ndev;
1523         if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1524                 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1525                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1526                         IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1527                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1528                         IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1529                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1530                         IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1531         }
1532         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1533                 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1534         }
1535
1536
1537         skb->protocol = eth_type_trans(skb, ndev);
1538         skb->ip_summed = CHECKSUM_NONE;
1539
1540         /* If rx checksum is on, and there are no
1541          * csum or frame errors.
1542          */
1543         if (qdev->rx_csum &&
1544                 !(ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) &&
1545                 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1546                 /* TCP frame. */
1547                 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1548                         QPRINTK(qdev, RX_STATUS, DEBUG,
1549                                         "TCP checksum done!\n");
1550                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1551                 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1552                                 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1553                 /* Unfragmented ipv4 UDP frame. */
1554                         struct iphdr *iph = (struct iphdr *) skb->data;
1555                         if (!(iph->frag_off &
1556                                 cpu_to_be16(IP_MF|IP_OFFSET))) {
1557                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1558                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1559                                                 "TCP checksum done!\n");
1560                         }
1561                 }
1562         }
1563
1564         qdev->stats.rx_packets++;
1565         qdev->stats.rx_bytes += skb->len;
1566         skb_record_rx_queue(skb,
1567                 rx_ring->cq_id - qdev->rss_ring_first_cq_id);
1568         if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
1569                 if (qdev->vlgrp &&
1570                         (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
1571                         (vlan_id != 0))
1572                         vlan_gro_receive(&rx_ring->napi, qdev->vlgrp,
1573                                 vlan_id, skb);
1574                 else
1575                         napi_gro_receive(&rx_ring->napi, skb);
1576         } else {
1577                 if (qdev->vlgrp &&
1578                         (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
1579                         (vlan_id != 0))
1580                         vlan_hwaccel_receive_skb(skb, qdev->vlgrp, vlan_id);
1581                 else
1582                         netif_receive_skb(skb);
1583         }
1584 }
1585
1586 /* Process an outbound completion from an rx ring. */
1587 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1588                                    struct ob_mac_iocb_rsp *mac_rsp)
1589 {
1590         struct tx_ring *tx_ring;
1591         struct tx_ring_desc *tx_ring_desc;
1592
1593         QL_DUMP_OB_MAC_RSP(mac_rsp);
1594         tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1595         tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1596         ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1597         qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1598         qdev->stats.tx_packets++;
1599         dev_kfree_skb(tx_ring_desc->skb);
1600         tx_ring_desc->skb = NULL;
1601
1602         if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1603                                         OB_MAC_IOCB_RSP_S |
1604                                         OB_MAC_IOCB_RSP_L |
1605                                         OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1606                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1607                         QPRINTK(qdev, TX_DONE, WARNING,
1608                                 "Total descriptor length did not match transfer length.\n");
1609                 }
1610                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1611                         QPRINTK(qdev, TX_DONE, WARNING,
1612                                 "Frame too short to be legal, not sent.\n");
1613                 }
1614                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1615                         QPRINTK(qdev, TX_DONE, WARNING,
1616                                 "Frame too long, but sent anyway.\n");
1617                 }
1618                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1619                         QPRINTK(qdev, TX_DONE, WARNING,
1620                                 "PCI backplane error. Frame not sent.\n");
1621                 }
1622         }
1623         atomic_inc(&tx_ring->tx_count);
1624 }
1625
1626 /* Fire up a handler to reset the MPI processor. */
1627 void ql_queue_fw_error(struct ql_adapter *qdev)
1628 {
1629         netif_carrier_off(qdev->ndev);
1630         queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1631 }
1632
1633 void ql_queue_asic_error(struct ql_adapter *qdev)
1634 {
1635         netif_carrier_off(qdev->ndev);
1636         ql_disable_interrupts(qdev);
1637         /* Clear adapter up bit to signal the recovery
1638          * process that it shouldn't kill the reset worker
1639          * thread
1640          */
1641         clear_bit(QL_ADAPTER_UP, &qdev->flags);
1642         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1643 }
1644
1645 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1646                                     struct ib_ae_iocb_rsp *ib_ae_rsp)
1647 {
1648         switch (ib_ae_rsp->event) {
1649         case MGMT_ERR_EVENT:
1650                 QPRINTK(qdev, RX_ERR, ERR,
1651                         "Management Processor Fatal Error.\n");
1652                 ql_queue_fw_error(qdev);
1653                 return;
1654
1655         case CAM_LOOKUP_ERR_EVENT:
1656                 QPRINTK(qdev, LINK, ERR,
1657                         "Multiple CAM hits lookup occurred.\n");
1658                 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1659                 ql_queue_asic_error(qdev);
1660                 return;
1661
1662         case SOFT_ECC_ERROR_EVENT:
1663                 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1664                 ql_queue_asic_error(qdev);
1665                 break;
1666
1667         case PCI_ERR_ANON_BUF_RD:
1668                 QPRINTK(qdev, RX_ERR, ERR,
1669                         "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1670                         ib_ae_rsp->q_id);
1671                 ql_queue_asic_error(qdev);
1672                 break;
1673
1674         default:
1675                 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1676                         ib_ae_rsp->event);
1677                 ql_queue_asic_error(qdev);
1678                 break;
1679         }
1680 }
1681
1682 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1683 {
1684         struct ql_adapter *qdev = rx_ring->qdev;
1685         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1686         struct ob_mac_iocb_rsp *net_rsp = NULL;
1687         int count = 0;
1688
1689         struct tx_ring *tx_ring;
1690         /* While there are entries in the completion queue. */
1691         while (prod != rx_ring->cnsmr_idx) {
1692
1693                 QPRINTK(qdev, RX_STATUS, DEBUG,
1694                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1695                         prod, rx_ring->cnsmr_idx);
1696
1697                 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1698                 rmb();
1699                 switch (net_rsp->opcode) {
1700
1701                 case OPCODE_OB_MAC_TSO_IOCB:
1702                 case OPCODE_OB_MAC_IOCB:
1703                         ql_process_mac_tx_intr(qdev, net_rsp);
1704                         break;
1705                 default:
1706                         QPRINTK(qdev, RX_STATUS, DEBUG,
1707                                 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1708                                 net_rsp->opcode);
1709                 }
1710                 count++;
1711                 ql_update_cq(rx_ring);
1712                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1713         }
1714         ql_write_cq_idx(rx_ring);
1715         tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1716         if (__netif_subqueue_stopped(qdev->ndev, tx_ring->wq_id) &&
1717                                         net_rsp != NULL) {
1718                 if (atomic_read(&tx_ring->queue_stopped) &&
1719                     (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1720                         /*
1721                          * The queue got stopped because the tx_ring was full.
1722                          * Wake it up, because it's now at least 25% empty.
1723                          */
1724                         netif_wake_subqueue(qdev->ndev, tx_ring->wq_id);
1725         }
1726
1727         return count;
1728 }
1729
1730 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1731 {
1732         struct ql_adapter *qdev = rx_ring->qdev;
1733         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1734         struct ql_net_rsp_iocb *net_rsp;
1735         int count = 0;
1736
1737         /* While there are entries in the completion queue. */
1738         while (prod != rx_ring->cnsmr_idx) {
1739
1740                 QPRINTK(qdev, RX_STATUS, DEBUG,
1741                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1742                         prod, rx_ring->cnsmr_idx);
1743
1744                 net_rsp = rx_ring->curr_entry;
1745                 rmb();
1746                 switch (net_rsp->opcode) {
1747                 case OPCODE_IB_MAC_IOCB:
1748                         ql_process_mac_rx_intr(qdev, rx_ring,
1749                                                (struct ib_mac_iocb_rsp *)
1750                                                net_rsp);
1751                         break;
1752
1753                 case OPCODE_IB_AE_IOCB:
1754                         ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1755                                                 net_rsp);
1756                         break;
1757                 default:
1758                         {
1759                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1760                                         "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1761                                         net_rsp->opcode);
1762                         }
1763                 }
1764                 count++;
1765                 ql_update_cq(rx_ring);
1766                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1767                 if (count == budget)
1768                         break;
1769         }
1770         ql_update_buffer_queues(qdev, rx_ring);
1771         ql_write_cq_idx(rx_ring);
1772         return count;
1773 }
1774
1775 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1776 {
1777         struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1778         struct ql_adapter *qdev = rx_ring->qdev;
1779         int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1780
1781         QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1782                 rx_ring->cq_id);
1783
1784         if (work_done < budget) {
1785                 napi_complete(napi);
1786                 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1787         }
1788         return work_done;
1789 }
1790
1791 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1792 {
1793         struct ql_adapter *qdev = netdev_priv(ndev);
1794
1795         qdev->vlgrp = grp;
1796         if (grp) {
1797                 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1798                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1799                            NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1800         } else {
1801                 QPRINTK(qdev, IFUP, DEBUG,
1802                         "Turning off VLAN in NIC_RCV_CFG.\n");
1803                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1804         }
1805 }
1806
1807 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1808 {
1809         struct ql_adapter *qdev = netdev_priv(ndev);
1810         u32 enable_bit = MAC_ADDR_E;
1811         int status;
1812
1813         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1814         if (status)
1815                 return;
1816         spin_lock(&qdev->hw_lock);
1817         if (ql_set_mac_addr_reg
1818             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1819                 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1820         }
1821         spin_unlock(&qdev->hw_lock);
1822         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1823 }
1824
1825 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1826 {
1827         struct ql_adapter *qdev = netdev_priv(ndev);
1828         u32 enable_bit = 0;
1829         int status;
1830
1831         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1832         if (status)
1833                 return;
1834
1835         spin_lock(&qdev->hw_lock);
1836         if (ql_set_mac_addr_reg
1837             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1838                 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1839         }
1840         spin_unlock(&qdev->hw_lock);
1841         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1842
1843 }
1844
1845 /* Worker thread to process a given rx_ring that is dedicated
1846  * to outbound completions.
1847  */
1848 static void ql_tx_clean(struct work_struct *work)
1849 {
1850         struct rx_ring *rx_ring =
1851             container_of(work, struct rx_ring, rx_work.work);
1852         ql_clean_outbound_rx_ring(rx_ring);
1853         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1854
1855 }
1856
1857 /* Worker thread to process a given rx_ring that is dedicated
1858  * to inbound completions.
1859  */
1860 static void ql_rx_clean(struct work_struct *work)
1861 {
1862         struct rx_ring *rx_ring =
1863             container_of(work, struct rx_ring, rx_work.work);
1864         ql_clean_inbound_rx_ring(rx_ring, 64);
1865         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1866 }
1867
1868 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1869 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1870 {
1871         struct rx_ring *rx_ring = dev_id;
1872         queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1873                               &rx_ring->rx_work, 0);
1874         return IRQ_HANDLED;
1875 }
1876
1877 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1878 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1879 {
1880         struct rx_ring *rx_ring = dev_id;
1881         napi_schedule(&rx_ring->napi);
1882         return IRQ_HANDLED;
1883 }
1884
1885 /* This handles a fatal error, MPI activity, and the default
1886  * rx_ring in an MSI-X multiple vector environment.
1887  * In MSI/Legacy environment it also process the rest of
1888  * the rx_rings.
1889  */
1890 static irqreturn_t qlge_isr(int irq, void *dev_id)
1891 {
1892         struct rx_ring *rx_ring = dev_id;
1893         struct ql_adapter *qdev = rx_ring->qdev;
1894         struct intr_context *intr_context = &qdev->intr_context[0];
1895         u32 var;
1896         int i;
1897         int work_done = 0;
1898
1899         spin_lock(&qdev->hw_lock);
1900         if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1901                 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1902                 spin_unlock(&qdev->hw_lock);
1903                 return IRQ_NONE;
1904         }
1905         spin_unlock(&qdev->hw_lock);
1906
1907         var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1908
1909         /*
1910          * Check for fatal error.
1911          */
1912         if (var & STS_FE) {
1913                 ql_queue_asic_error(qdev);
1914                 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1915                 var = ql_read32(qdev, ERR_STS);
1916                 QPRINTK(qdev, INTR, ERR,
1917                         "Resetting chip. Error Status Register = 0x%x\n", var);
1918                 return IRQ_HANDLED;
1919         }
1920
1921         /*
1922          * Check MPI processor activity.
1923          */
1924         if (var & STS_PI) {
1925                 /*
1926                  * We've got an async event or mailbox completion.
1927                  * Handle it and clear the source of the interrupt.
1928                  */
1929                 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1930                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1931                 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1932                                       &qdev->mpi_work, 0);
1933                 work_done++;
1934         }
1935
1936         /*
1937          * Check the default queue and wake handler if active.
1938          */
1939         rx_ring = &qdev->rx_ring[0];
1940         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1941                 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1942                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1943                 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1944                                       &rx_ring->rx_work, 0);
1945                 work_done++;
1946         }
1947
1948         if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1949                 /*
1950                  * Start the DPC for each active queue.
1951                  */
1952                 for (i = 1; i < qdev->rx_ring_count; i++) {
1953                         rx_ring = &qdev->rx_ring[i];
1954                         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1955                             rx_ring->cnsmr_idx) {
1956                                 QPRINTK(qdev, INTR, INFO,
1957                                         "Waking handler for rx_ring[%d].\n", i);
1958                                 ql_disable_completion_interrupt(qdev,
1959                                                                 intr_context->
1960                                                                 intr);
1961                                 if (i < qdev->rss_ring_first_cq_id)
1962                                         queue_delayed_work_on(rx_ring->cpu,
1963                                                               qdev->q_workqueue,
1964                                                               &rx_ring->rx_work,
1965                                                               0);
1966                                 else
1967                                         napi_schedule(&rx_ring->napi);
1968                                 work_done++;
1969                         }
1970                 }
1971         }
1972         ql_enable_completion_interrupt(qdev, intr_context->intr);
1973         return work_done ? IRQ_HANDLED : IRQ_NONE;
1974 }
1975
1976 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1977 {
1978
1979         if (skb_is_gso(skb)) {
1980                 int err;
1981                 if (skb_header_cloned(skb)) {
1982                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1983                         if (err)
1984                                 return err;
1985                 }
1986
1987                 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1988                 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1989                 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1990                 mac_iocb_ptr->total_hdrs_len =
1991                     cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1992                 mac_iocb_ptr->net_trans_offset =
1993                     cpu_to_le16(skb_network_offset(skb) |
1994                                 skb_transport_offset(skb)
1995                                 << OB_MAC_TRANSPORT_HDR_SHIFT);
1996                 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1997                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1998                 if (likely(skb->protocol == htons(ETH_P_IP))) {
1999                         struct iphdr *iph = ip_hdr(skb);
2000                         iph->check = 0;
2001                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2002                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2003                                                                  iph->daddr, 0,
2004                                                                  IPPROTO_TCP,
2005                                                                  0);
2006                 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2007                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
2008                         tcp_hdr(skb)->check =
2009                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2010                                              &ipv6_hdr(skb)->daddr,
2011                                              0, IPPROTO_TCP, 0);
2012                 }
2013                 return 1;
2014         }
2015         return 0;
2016 }
2017
2018 static void ql_hw_csum_setup(struct sk_buff *skb,
2019                              struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2020 {
2021         int len;
2022         struct iphdr *iph = ip_hdr(skb);
2023         __sum16 *check;
2024         mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2025         mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2026         mac_iocb_ptr->net_trans_offset =
2027                 cpu_to_le16(skb_network_offset(skb) |
2028                 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
2029
2030         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2031         len = (ntohs(iph->tot_len) - (iph->ihl << 2));
2032         if (likely(iph->protocol == IPPROTO_TCP)) {
2033                 check = &(tcp_hdr(skb)->check);
2034                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
2035                 mac_iocb_ptr->total_hdrs_len =
2036                     cpu_to_le16(skb_transport_offset(skb) +
2037                                 (tcp_hdr(skb)->doff << 2));
2038         } else {
2039                 check = &(udp_hdr(skb)->check);
2040                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
2041                 mac_iocb_ptr->total_hdrs_len =
2042                     cpu_to_le16(skb_transport_offset(skb) +
2043                                 sizeof(struct udphdr));
2044         }
2045         *check = ~csum_tcpudp_magic(iph->saddr,
2046                                     iph->daddr, len, iph->protocol, 0);
2047 }
2048
2049 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
2050 {
2051         struct tx_ring_desc *tx_ring_desc;
2052         struct ob_mac_iocb_req *mac_iocb_ptr;
2053         struct ql_adapter *qdev = netdev_priv(ndev);
2054         int tso;
2055         struct tx_ring *tx_ring;
2056         u32 tx_ring_idx = (u32) skb->queue_mapping;
2057
2058         tx_ring = &qdev->tx_ring[tx_ring_idx];
2059
2060         if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
2061                 QPRINTK(qdev, TX_QUEUED, INFO,
2062                         "%s: shutting down tx queue %d du to lack of resources.\n",
2063                         __func__, tx_ring_idx);
2064                 netif_stop_subqueue(ndev, tx_ring->wq_id);
2065                 atomic_inc(&tx_ring->queue_stopped);
2066                 return NETDEV_TX_BUSY;
2067         }
2068         tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
2069         mac_iocb_ptr = tx_ring_desc->queue_entry;
2070         memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
2071
2072         mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
2073         mac_iocb_ptr->tid = tx_ring_desc->index;
2074         /* We use the upper 32-bits to store the tx queue for this IO.
2075          * When we get the completion we can use it to establish the context.
2076          */
2077         mac_iocb_ptr->txq_idx = tx_ring_idx;
2078         tx_ring_desc->skb = skb;
2079
2080         mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
2081
2082         if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
2083                 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
2084                         vlan_tx_tag_get(skb));
2085                 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
2086                 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
2087         }
2088         tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2089         if (tso < 0) {
2090                 dev_kfree_skb_any(skb);
2091                 return NETDEV_TX_OK;
2092         } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
2093                 ql_hw_csum_setup(skb,
2094                                  (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2095         }
2096         if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
2097                         NETDEV_TX_OK) {
2098                 QPRINTK(qdev, TX_QUEUED, ERR,
2099                                 "Could not map the segments.\n");
2100                 return NETDEV_TX_BUSY;
2101         }
2102         QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
2103         tx_ring->prod_idx++;
2104         if (tx_ring->prod_idx == tx_ring->wq_len)
2105                 tx_ring->prod_idx = 0;
2106         wmb();
2107
2108         ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
2109         ndev->trans_start = jiffies;
2110         QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
2111                 tx_ring->prod_idx, skb->len);
2112
2113         atomic_dec(&tx_ring->tx_count);
2114         return NETDEV_TX_OK;
2115 }
2116
2117 static void ql_free_shadow_space(struct ql_adapter *qdev)
2118 {
2119         if (qdev->rx_ring_shadow_reg_area) {
2120                 pci_free_consistent(qdev->pdev,
2121                                     PAGE_SIZE,
2122                                     qdev->rx_ring_shadow_reg_area,
2123                                     qdev->rx_ring_shadow_reg_dma);
2124                 qdev->rx_ring_shadow_reg_area = NULL;
2125         }
2126         if (qdev->tx_ring_shadow_reg_area) {
2127                 pci_free_consistent(qdev->pdev,
2128                                     PAGE_SIZE,
2129                                     qdev->tx_ring_shadow_reg_area,
2130                                     qdev->tx_ring_shadow_reg_dma);
2131                 qdev->tx_ring_shadow_reg_area = NULL;
2132         }
2133 }
2134
2135 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2136 {
2137         qdev->rx_ring_shadow_reg_area =
2138             pci_alloc_consistent(qdev->pdev,
2139                                  PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2140         if (qdev->rx_ring_shadow_reg_area == NULL) {
2141                 QPRINTK(qdev, IFUP, ERR,
2142                         "Allocation of RX shadow space failed.\n");
2143                 return -ENOMEM;
2144         }
2145         qdev->tx_ring_shadow_reg_area =
2146             pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2147                                  &qdev->tx_ring_shadow_reg_dma);
2148         if (qdev->tx_ring_shadow_reg_area == NULL) {
2149                 QPRINTK(qdev, IFUP, ERR,
2150                         "Allocation of TX shadow space failed.\n");
2151                 goto err_wqp_sh_area;
2152         }
2153         return 0;
2154
2155 err_wqp_sh_area:
2156         pci_free_consistent(qdev->pdev,
2157                             PAGE_SIZE,
2158                             qdev->rx_ring_shadow_reg_area,
2159                             qdev->rx_ring_shadow_reg_dma);
2160         return -ENOMEM;
2161 }
2162
2163 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2164 {
2165         struct tx_ring_desc *tx_ring_desc;
2166         int i;
2167         struct ob_mac_iocb_req *mac_iocb_ptr;
2168
2169         mac_iocb_ptr = tx_ring->wq_base;
2170         tx_ring_desc = tx_ring->q;
2171         for (i = 0; i < tx_ring->wq_len; i++) {
2172                 tx_ring_desc->index = i;
2173                 tx_ring_desc->skb = NULL;
2174                 tx_ring_desc->queue_entry = mac_iocb_ptr;
2175                 mac_iocb_ptr++;
2176                 tx_ring_desc++;
2177         }
2178         atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2179         atomic_set(&tx_ring->queue_stopped, 0);
2180 }
2181
2182 static void ql_free_tx_resources(struct ql_adapter *qdev,
2183                                  struct tx_ring *tx_ring)
2184 {
2185         if (tx_ring->wq_base) {
2186                 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2187                                     tx_ring->wq_base, tx_ring->wq_base_dma);
2188                 tx_ring->wq_base = NULL;
2189         }
2190         kfree(tx_ring->q);
2191         tx_ring->q = NULL;
2192 }
2193
2194 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2195                                  struct tx_ring *tx_ring)
2196 {
2197         tx_ring->wq_base =
2198             pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2199                                  &tx_ring->wq_base_dma);
2200
2201         if ((tx_ring->wq_base == NULL)
2202             || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2203                 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2204                 return -ENOMEM;
2205         }
2206         tx_ring->q =
2207             kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2208         if (tx_ring->q == NULL)
2209                 goto err;
2210
2211         return 0;
2212 err:
2213         pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2214                             tx_ring->wq_base, tx_ring->wq_base_dma);
2215         return -ENOMEM;
2216 }
2217
2218 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2219 {
2220         int i;
2221         struct bq_desc *lbq_desc;
2222
2223         for (i = 0; i < rx_ring->lbq_len; i++) {
2224                 lbq_desc = &rx_ring->lbq[i];
2225                 if (lbq_desc->p.lbq_page) {
2226                         pci_unmap_page(qdev->pdev,
2227                                        pci_unmap_addr(lbq_desc, mapaddr),
2228                                        pci_unmap_len(lbq_desc, maplen),
2229                                        PCI_DMA_FROMDEVICE);
2230
2231                         put_page(lbq_desc->p.lbq_page);
2232                         lbq_desc->p.lbq_page = NULL;
2233                 }
2234         }
2235 }
2236
2237 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2238 {
2239         int i;
2240         struct bq_desc *sbq_desc;
2241
2242         for (i = 0; i < rx_ring->sbq_len; i++) {
2243                 sbq_desc = &rx_ring->sbq[i];
2244                 if (sbq_desc == NULL) {
2245                         QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2246                         return;
2247                 }
2248                 if (sbq_desc->p.skb) {
2249                         pci_unmap_single(qdev->pdev,
2250                                          pci_unmap_addr(sbq_desc, mapaddr),
2251                                          pci_unmap_len(sbq_desc, maplen),
2252                                          PCI_DMA_FROMDEVICE);
2253                         dev_kfree_skb(sbq_desc->p.skb);
2254                         sbq_desc->p.skb = NULL;
2255                 }
2256         }
2257 }
2258
2259 /* Free all large and small rx buffers associated
2260  * with the completion queues for this device.
2261  */
2262 static void ql_free_rx_buffers(struct ql_adapter *qdev)
2263 {
2264         int i;
2265         struct rx_ring *rx_ring;
2266
2267         for (i = 0; i < qdev->rx_ring_count; i++) {
2268                 rx_ring = &qdev->rx_ring[i];
2269                 if (rx_ring->lbq)
2270                         ql_free_lbq_buffers(qdev, rx_ring);
2271                 if (rx_ring->sbq)
2272                         ql_free_sbq_buffers(qdev, rx_ring);
2273         }
2274 }
2275
2276 static void ql_alloc_rx_buffers(struct ql_adapter *qdev)
2277 {
2278         struct rx_ring *rx_ring;
2279         int i;
2280
2281         for (i = 0; i < qdev->rx_ring_count; i++) {
2282                 rx_ring = &qdev->rx_ring[i];
2283                 if (rx_ring->type != TX_Q)
2284                         ql_update_buffer_queues(qdev, rx_ring);
2285         }
2286 }
2287
2288 static void ql_init_lbq_ring(struct ql_adapter *qdev,
2289                                 struct rx_ring *rx_ring)
2290 {
2291         int i;
2292         struct bq_desc *lbq_desc;
2293         __le64 *bq = rx_ring->lbq_base;
2294
2295         memset(rx_ring->lbq, 0, rx_ring->lbq_len * sizeof(struct bq_desc));
2296         for (i = 0; i < rx_ring->lbq_len; i++) {
2297                 lbq_desc = &rx_ring->lbq[i];
2298                 memset(lbq_desc, 0, sizeof(*lbq_desc));
2299                 lbq_desc->index = i;
2300                 lbq_desc->addr = bq;
2301                 bq++;
2302         }
2303 }
2304
2305 static void ql_init_sbq_ring(struct ql_adapter *qdev,
2306                                 struct rx_ring *rx_ring)
2307 {
2308         int i;
2309         struct bq_desc *sbq_desc;
2310         __le64 *bq = rx_ring->sbq_base;
2311
2312         memset(rx_ring->sbq, 0, rx_ring->sbq_len * sizeof(struct bq_desc));
2313         for (i = 0; i < rx_ring->sbq_len; i++) {
2314                 sbq_desc = &rx_ring->sbq[i];
2315                 memset(sbq_desc, 0, sizeof(*sbq_desc));
2316                 sbq_desc->index = i;
2317                 sbq_desc->addr = bq;
2318                 bq++;
2319         }
2320 }
2321
2322 static void ql_free_rx_resources(struct ql_adapter *qdev,
2323                                  struct rx_ring *rx_ring)
2324 {
2325         /* Free the small buffer queue. */
2326         if (rx_ring->sbq_base) {
2327                 pci_free_consistent(qdev->pdev,
2328                                     rx_ring->sbq_size,
2329                                     rx_ring->sbq_base, rx_ring->sbq_base_dma);
2330                 rx_ring->sbq_base = NULL;
2331         }
2332
2333         /* Free the small buffer queue control blocks. */
2334         kfree(rx_ring->sbq);
2335         rx_ring->sbq = NULL;
2336
2337         /* Free the large buffer queue. */
2338         if (rx_ring->lbq_base) {
2339                 pci_free_consistent(qdev->pdev,
2340                                     rx_ring->lbq_size,
2341                                     rx_ring->lbq_base, rx_ring->lbq_base_dma);
2342                 rx_ring->lbq_base = NULL;
2343         }
2344
2345         /* Free the large buffer queue control blocks. */
2346         kfree(rx_ring->lbq);
2347         rx_ring->lbq = NULL;
2348
2349         /* Free the rx queue. */
2350         if (rx_ring->cq_base) {
2351                 pci_free_consistent(qdev->pdev,
2352                                     rx_ring->cq_size,
2353                                     rx_ring->cq_base, rx_ring->cq_base_dma);
2354                 rx_ring->cq_base = NULL;
2355         }
2356 }
2357
2358 /* Allocate queues and buffers for this completions queue based
2359  * on the values in the parameter structure. */
2360 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2361                                  struct rx_ring *rx_ring)
2362 {
2363
2364         /*
2365          * Allocate the completion queue for this rx_ring.
2366          */
2367         rx_ring->cq_base =
2368             pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2369                                  &rx_ring->cq_base_dma);
2370
2371         if (rx_ring->cq_base == NULL) {
2372                 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2373                 return -ENOMEM;
2374         }
2375
2376         if (rx_ring->sbq_len) {
2377                 /*
2378                  * Allocate small buffer queue.
2379                  */
2380                 rx_ring->sbq_base =
2381                     pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2382                                          &rx_ring->sbq_base_dma);
2383
2384                 if (rx_ring->sbq_base == NULL) {
2385                         QPRINTK(qdev, IFUP, ERR,
2386                                 "Small buffer queue allocation failed.\n");
2387                         goto err_mem;
2388                 }
2389
2390                 /*
2391                  * Allocate small buffer queue control blocks.
2392                  */
2393                 rx_ring->sbq =
2394                     kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2395                             GFP_KERNEL);
2396                 if (rx_ring->sbq == NULL) {
2397                         QPRINTK(qdev, IFUP, ERR,
2398                                 "Small buffer queue control block allocation failed.\n");
2399                         goto err_mem;
2400                 }
2401
2402                 ql_init_sbq_ring(qdev, rx_ring);
2403         }
2404
2405         if (rx_ring->lbq_len) {
2406                 /*
2407                  * Allocate large buffer queue.
2408                  */
2409                 rx_ring->lbq_base =
2410                     pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2411                                          &rx_ring->lbq_base_dma);
2412
2413                 if (rx_ring->lbq_base == NULL) {
2414                         QPRINTK(qdev, IFUP, ERR,
2415                                 "Large buffer queue allocation failed.\n");
2416                         goto err_mem;
2417                 }
2418                 /*
2419                  * Allocate large buffer queue control blocks.
2420                  */
2421                 rx_ring->lbq =
2422                     kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2423                             GFP_KERNEL);
2424                 if (rx_ring->lbq == NULL) {
2425                         QPRINTK(qdev, IFUP, ERR,
2426                                 "Large buffer queue control block allocation failed.\n");
2427                         goto err_mem;
2428                 }
2429
2430                 ql_init_lbq_ring(qdev, rx_ring);
2431         }
2432
2433         return 0;
2434
2435 err_mem:
2436         ql_free_rx_resources(qdev, rx_ring);
2437         return -ENOMEM;
2438 }
2439
2440 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2441 {
2442         struct tx_ring *tx_ring;
2443         struct tx_ring_desc *tx_ring_desc;
2444         int i, j;
2445
2446         /*
2447          * Loop through all queues and free
2448          * any resources.
2449          */
2450         for (j = 0; j < qdev->tx_ring_count; j++) {
2451                 tx_ring = &qdev->tx_ring[j];
2452                 for (i = 0; i < tx_ring->wq_len; i++) {
2453                         tx_ring_desc = &tx_ring->q[i];
2454                         if (tx_ring_desc && tx_ring_desc->skb) {
2455                                 QPRINTK(qdev, IFDOWN, ERR,
2456                                 "Freeing lost SKB %p, from queue %d, index %d.\n",
2457                                         tx_ring_desc->skb, j,
2458                                         tx_ring_desc->index);
2459                                 ql_unmap_send(qdev, tx_ring_desc,
2460                                               tx_ring_desc->map_cnt);
2461                                 dev_kfree_skb(tx_ring_desc->skb);
2462                                 tx_ring_desc->skb = NULL;
2463                         }
2464                 }
2465         }
2466 }
2467
2468 static void ql_free_mem_resources(struct ql_adapter *qdev)
2469 {
2470         int i;
2471
2472         for (i = 0; i < qdev->tx_ring_count; i++)
2473                 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2474         for (i = 0; i < qdev->rx_ring_count; i++)
2475                 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2476         ql_free_shadow_space(qdev);
2477 }
2478
2479 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2480 {
2481         int i;
2482
2483         /* Allocate space for our shadow registers and such. */
2484         if (ql_alloc_shadow_space(qdev))
2485                 return -ENOMEM;
2486
2487         for (i = 0; i < qdev->rx_ring_count; i++) {
2488                 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2489                         QPRINTK(qdev, IFUP, ERR,
2490                                 "RX resource allocation failed.\n");
2491                         goto err_mem;
2492                 }
2493         }
2494         /* Allocate tx queue resources */
2495         for (i = 0; i < qdev->tx_ring_count; i++) {
2496                 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2497                         QPRINTK(qdev, IFUP, ERR,
2498                                 "TX resource allocation failed.\n");
2499                         goto err_mem;
2500                 }
2501         }
2502         return 0;
2503
2504 err_mem:
2505         ql_free_mem_resources(qdev);
2506         return -ENOMEM;
2507 }
2508
2509 /* Set up the rx ring control block and pass it to the chip.
2510  * The control block is defined as
2511  * "Completion Queue Initialization Control Block", or cqicb.
2512  */
2513 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2514 {
2515         struct cqicb *cqicb = &rx_ring->cqicb;
2516         void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2517             (rx_ring->cq_id * sizeof(u64) * 4);
2518         u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2519             (rx_ring->cq_id * sizeof(u64) * 4);
2520         void __iomem *doorbell_area =
2521             qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2522         int err = 0;
2523         u16 bq_len;
2524
2525         /* Set up the shadow registers for this ring. */
2526         rx_ring->prod_idx_sh_reg = shadow_reg;
2527         rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2528         shadow_reg += sizeof(u64);
2529         shadow_reg_dma += sizeof(u64);
2530         rx_ring->lbq_base_indirect = shadow_reg;
2531         rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2532         shadow_reg += sizeof(u64);
2533         shadow_reg_dma += sizeof(u64);
2534         rx_ring->sbq_base_indirect = shadow_reg;
2535         rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2536
2537         /* PCI doorbell mem area + 0x00 for consumer index register */
2538         rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2539         rx_ring->cnsmr_idx = 0;
2540         rx_ring->curr_entry = rx_ring->cq_base;
2541
2542         /* PCI doorbell mem area + 0x04 for valid register */
2543         rx_ring->valid_db_reg = doorbell_area + 0x04;
2544
2545         /* PCI doorbell mem area + 0x18 for large buffer consumer */
2546         rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2547
2548         /* PCI doorbell mem area + 0x1c */
2549         rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2550
2551         memset((void *)cqicb, 0, sizeof(struct cqicb));
2552         cqicb->msix_vect = rx_ring->irq;
2553
2554         bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2555         cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
2556
2557         cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
2558
2559         cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
2560
2561         /*
2562          * Set up the control block load flags.
2563          */
2564         cqicb->flags = FLAGS_LC |       /* Load queue base address */
2565             FLAGS_LV |          /* Load MSI-X vector */
2566             FLAGS_LI;           /* Load irq delay values */
2567         if (rx_ring->lbq_len) {
2568                 cqicb->flags |= FLAGS_LL;       /* Load lbq values */
2569                 *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma;
2570                 cqicb->lbq_addr =
2571                     cpu_to_le64(rx_ring->lbq_base_indirect_dma);
2572                 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2573                         (u16) rx_ring->lbq_buf_size;
2574                 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2575                 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2576                         (u16) rx_ring->lbq_len;
2577                 cqicb->lbq_len = cpu_to_le16(bq_len);
2578                 rx_ring->lbq_prod_idx = 0;
2579                 rx_ring->lbq_curr_idx = 0;
2580                 rx_ring->lbq_clean_idx = 0;
2581                 rx_ring->lbq_free_cnt = rx_ring->lbq_len;
2582         }
2583         if (rx_ring->sbq_len) {
2584                 cqicb->flags |= FLAGS_LS;       /* Load sbq values */
2585                 *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma;
2586                 cqicb->sbq_addr =
2587                     cpu_to_le64(rx_ring->sbq_base_indirect_dma);
2588                 cqicb->sbq_buf_size =
2589                     cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
2590                 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2591                         (u16) rx_ring->sbq_len;
2592                 cqicb->sbq_len = cpu_to_le16(bq_len);
2593                 rx_ring->sbq_prod_idx = 0;
2594                 rx_ring->sbq_curr_idx = 0;
2595                 rx_ring->sbq_clean_idx = 0;
2596                 rx_ring->sbq_free_cnt = rx_ring->sbq_len;
2597         }
2598         switch (rx_ring->type) {
2599         case TX_Q:
2600                 /* If there's only one interrupt, then we use
2601                  * worker threads to process the outbound
2602                  * completion handling rx_rings. We do this so
2603                  * they can be run on multiple CPUs. There is
2604                  * room to play with this more where we would only
2605                  * run in a worker if there are more than x number
2606                  * of outbound completions on the queue and more
2607                  * than one queue active.  Some threshold that
2608                  * would indicate a benefit in spite of the cost
2609                  * of a context switch.
2610                  * If there's more than one interrupt, then the
2611                  * outbound completions are processed in the ISR.
2612                  */
2613                 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2614                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2615                 else {
2616                         /* With all debug warnings on we see a WARN_ON message
2617                          * when we free the skb in the interrupt context.
2618                          */
2619                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2620                 }
2621                 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2622                 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2623                 break;
2624         case DEFAULT_Q:
2625                 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2626                 cqicb->irq_delay = 0;
2627                 cqicb->pkt_delay = 0;
2628                 break;
2629         case RX_Q:
2630                 /* Inbound completion handling rx_rings run in
2631                  * separate NAPI contexts.
2632                  */
2633                 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2634                                64);
2635                 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2636                 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2637                 break;
2638         default:
2639                 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2640                         rx_ring->type);
2641         }
2642         QPRINTK(qdev, IFUP, DEBUG, "Initializing rx work queue.\n");
2643         err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2644                            CFG_LCQ, rx_ring->cq_id);
2645         if (err) {
2646                 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2647                 return err;
2648         }
2649         return err;
2650 }
2651
2652 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2653 {
2654         struct wqicb *wqicb = (struct wqicb *)tx_ring;
2655         void __iomem *doorbell_area =
2656             qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2657         void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2658             (tx_ring->wq_id * sizeof(u64));
2659         u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2660             (tx_ring->wq_id * sizeof(u64));
2661         int err = 0;
2662
2663         /*
2664          * Assign doorbell registers for this tx_ring.
2665          */
2666         /* TX PCI doorbell mem area for tx producer index */
2667         tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2668         tx_ring->prod_idx = 0;
2669         /* TX PCI doorbell mem area + 0x04 */
2670         tx_ring->valid_db_reg = doorbell_area + 0x04;
2671
2672         /*
2673          * Assign shadow registers for this tx_ring.
2674          */
2675         tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2676         tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2677
2678         wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2679         wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2680                                    Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2681         wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2682         wqicb->rid = 0;
2683         wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
2684
2685         wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
2686
2687         ql_init_tx_ring(qdev, tx_ring);
2688
2689         err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2690                            (u16) tx_ring->wq_id);
2691         if (err) {
2692                 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2693                 return err;
2694         }
2695         QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded WQICB.\n");
2696         return err;
2697 }
2698
2699 static void ql_disable_msix(struct ql_adapter *qdev)
2700 {
2701         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2702                 pci_disable_msix(qdev->pdev);
2703                 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2704                 kfree(qdev->msi_x_entry);
2705                 qdev->msi_x_entry = NULL;
2706         } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2707                 pci_disable_msi(qdev->pdev);
2708                 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2709         }
2710 }
2711
2712 static void ql_enable_msix(struct ql_adapter *qdev)
2713 {
2714         int i;
2715
2716         qdev->intr_count = 1;
2717         /* Get the MSIX vectors. */
2718         if (irq_type == MSIX_IRQ) {
2719                 /* Try to alloc space for the msix struct,
2720                  * if it fails then go to MSI/legacy.
2721                  */
2722                 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2723                                             sizeof(struct msix_entry),
2724                                             GFP_KERNEL);
2725                 if (!qdev->msi_x_entry) {
2726                         irq_type = MSI_IRQ;
2727                         goto msi;
2728                 }
2729
2730                 for (i = 0; i < qdev->rx_ring_count; i++)
2731                         qdev->msi_x_entry[i].entry = i;
2732
2733                 if (!pci_enable_msix
2734                     (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2735                         set_bit(QL_MSIX_ENABLED, &qdev->flags);
2736                         qdev->intr_count = qdev->rx_ring_count;
2737                         QPRINTK(qdev, IFUP, DEBUG,
2738                                 "MSI-X Enabled, got %d vectors.\n",
2739                                 qdev->intr_count);
2740                         return;
2741                 } else {
2742                         kfree(qdev->msi_x_entry);
2743                         qdev->msi_x_entry = NULL;
2744                         QPRINTK(qdev, IFUP, WARNING,
2745                                 "MSI-X Enable failed, trying MSI.\n");
2746                         irq_type = MSI_IRQ;
2747                 }
2748         }
2749 msi:
2750         if (irq_type == MSI_IRQ) {
2751                 if (!pci_enable_msi(qdev->pdev)) {
2752                         set_bit(QL_MSI_ENABLED, &qdev->flags);
2753                         QPRINTK(qdev, IFUP, INFO,
2754                                 "Running with MSI interrupts.\n");
2755                         return;
2756                 }
2757         }
2758         irq_type = LEG_IRQ;
2759         QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2760 }
2761
2762 /*
2763  * Here we build the intr_context structures based on
2764  * our rx_ring count and intr vector count.
2765  * The intr_context structure is used to hook each vector
2766  * to possibly different handlers.
2767  */
2768 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2769 {
2770         int i = 0;
2771         struct intr_context *intr_context = &qdev->intr_context[0];
2772
2773         ql_enable_msix(qdev);
2774
2775         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2776                 /* Each rx_ring has it's
2777                  * own intr_context since we have separate
2778                  * vectors for each queue.
2779                  * This only true when MSI-X is enabled.
2780                  */
2781                 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2782                         qdev->rx_ring[i].irq = i;
2783                         intr_context->intr = i;
2784                         intr_context->qdev = qdev;
2785                         /*
2786                          * We set up each vectors enable/disable/read bits so
2787                          * there's no bit/mask calculations in the critical path.
2788                          */
2789                         intr_context->intr_en_mask =
2790                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2791                             INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2792                             | i;
2793                         intr_context->intr_dis_mask =
2794                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2795                             INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2796                             INTR_EN_IHD | i;
2797                         intr_context->intr_read_mask =
2798                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2799                             INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2800                             i;
2801
2802                         if (i == 0) {
2803                                 /*
2804                                  * Default queue handles bcast/mcast plus
2805                                  * async events.  Needs buffers.
2806                                  */
2807                                 intr_context->handler = qlge_isr;
2808                                 sprintf(intr_context->name, "%s-default-queue",
2809                                         qdev->ndev->name);
2810                         } else if (i < qdev->rss_ring_first_cq_id) {
2811                                 /*
2812                                  * Outbound queue is for outbound completions only.
2813                                  */
2814                                 intr_context->handler = qlge_msix_tx_isr;
2815                                 sprintf(intr_context->name, "%s-tx-%d",
2816                                         qdev->ndev->name, i);
2817                         } else {
2818                                 /*
2819                                  * Inbound queues handle unicast frames only.
2820                                  */
2821                                 intr_context->handler = qlge_msix_rx_isr;
2822                                 sprintf(intr_context->name, "%s-rx-%d",
2823                                         qdev->ndev->name, i);
2824                         }
2825                 }
2826         } else {
2827                 /*
2828                  * All rx_rings use the same intr_context since
2829                  * there is only one vector.
2830                  */
2831                 intr_context->intr = 0;
2832                 intr_context->qdev = qdev;
2833                 /*
2834                  * We set up each vectors enable/disable/read bits so
2835                  * there's no bit/mask calculations in the critical path.
2836                  */
2837                 intr_context->intr_en_mask =
2838                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2839                 intr_context->intr_dis_mask =
2840                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2841                     INTR_EN_TYPE_DISABLE;
2842                 intr_context->intr_read_mask =
2843                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2844                 /*
2845                  * Single interrupt means one handler for all rings.
2846                  */
2847                 intr_context->handler = qlge_isr;
2848                 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2849                 for (i = 0; i < qdev->rx_ring_count; i++)
2850                         qdev->rx_ring[i].irq = 0;
2851         }
2852 }
2853
2854 static void ql_free_irq(struct ql_adapter *qdev)
2855 {
2856         int i;
2857         struct intr_context *intr_context = &qdev->intr_context[0];
2858
2859         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2860                 if (intr_context->hooked) {
2861                         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2862                                 free_irq(qdev->msi_x_entry[i].vector,
2863                                          &qdev->rx_ring[i]);
2864                                 QPRINTK(qdev, IFDOWN, DEBUG,
2865                                         "freeing msix interrupt %d.\n", i);
2866                         } else {
2867                                 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2868                                 QPRINTK(qdev, IFDOWN, DEBUG,
2869                                         "freeing msi interrupt %d.\n", i);
2870                         }
2871                 }
2872         }
2873         ql_disable_msix(qdev);
2874 }
2875
2876 static int ql_request_irq(struct ql_adapter *qdev)
2877 {
2878         int i;
2879         int status = 0;
2880         struct pci_dev *pdev = qdev->pdev;
2881         struct intr_context *intr_context = &qdev->intr_context[0];
2882
2883         ql_resolve_queues_to_irqs(qdev);
2884
2885         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2886                 atomic_set(&intr_context->irq_cnt, 0);
2887                 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2888                         status = request_irq(qdev->msi_x_entry[i].vector,
2889                                              intr_context->handler,
2890                                              0,
2891                                              intr_context->name,
2892                                              &qdev->rx_ring[i]);
2893                         if (status) {
2894                                 QPRINTK(qdev, IFUP, ERR,
2895                                         "Failed request for MSIX interrupt %d.\n",
2896                                         i);
2897                                 goto err_irq;
2898                         } else {
2899                                 QPRINTK(qdev, IFUP, DEBUG,
2900                                         "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2901                                         i,
2902                                         qdev->rx_ring[i].type ==
2903                                         DEFAULT_Q ? "DEFAULT_Q" : "",
2904                                         qdev->rx_ring[i].type ==
2905                                         TX_Q ? "TX_Q" : "",
2906                                         qdev->rx_ring[i].type ==
2907                                         RX_Q ? "RX_Q" : "", intr_context->name);
2908                         }
2909                 } else {
2910                         QPRINTK(qdev, IFUP, DEBUG,
2911                                 "trying msi or legacy interrupts.\n");
2912                         QPRINTK(qdev, IFUP, DEBUG,
2913                                 "%s: irq = %d.\n", __func__, pdev->irq);
2914                         QPRINTK(qdev, IFUP, DEBUG,
2915                                 "%s: context->name = %s.\n", __func__,
2916                                intr_context->name);
2917                         QPRINTK(qdev, IFUP, DEBUG,
2918                                 "%s: dev_id = 0x%p.\n", __func__,
2919                                &qdev->rx_ring[0]);
2920                         status =
2921                             request_irq(pdev->irq, qlge_isr,
2922                                         test_bit(QL_MSI_ENABLED,
2923                                                  &qdev->
2924                                                  flags) ? 0 : IRQF_SHARED,
2925                                         intr_context->name, &qdev->rx_ring[0]);
2926                         if (status)
2927                                 goto err_irq;
2928
2929                         QPRINTK(qdev, IFUP, ERR,
2930                                 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2931                                 i,
2932                                 qdev->rx_ring[0].type ==
2933                                 DEFAULT_Q ? "DEFAULT_Q" : "",
2934                                 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2935                                 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2936                                 intr_context->name);
2937                 }
2938                 intr_context->hooked = 1;
2939         }
2940         return status;
2941 err_irq:
2942         QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2943         ql_free_irq(qdev);
2944         return status;
2945 }
2946
2947 static int ql_start_rss(struct ql_adapter *qdev)
2948 {
2949         struct ricb *ricb = &qdev->ricb;
2950         int status = 0;
2951         int i;
2952         u8 *hash_id = (u8 *) ricb->hash_cq_id;
2953
2954         memset((void *)ricb, 0, sizeof(ricb));
2955
2956         ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2957         ricb->flags =
2958             (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2959              RSS_RT6);
2960         ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2961
2962         /*
2963          * Fill out the Indirection Table.
2964          */
2965         for (i = 0; i < 256; i++)
2966                 hash_id[i] = i & (qdev->rss_ring_count - 1);
2967
2968         /*
2969          * Random values for the IPv6 and IPv4 Hash Keys.
2970          */
2971         get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2972         get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2973
2974         QPRINTK(qdev, IFUP, DEBUG, "Initializing RSS.\n");
2975
2976         status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2977         if (status) {
2978                 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2979                 return status;
2980         }
2981         QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded RICB.\n");
2982         return status;
2983 }
2984
2985 /* Initialize the frame-to-queue routing. */
2986 static int ql_route_initialize(struct ql_adapter *qdev)
2987 {
2988         int status = 0;
2989         int i;
2990
2991         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
2992         if (status)
2993                 return status;
2994
2995         /* Clear all the entries in the routing table. */
2996         for (i = 0; i < 16; i++) {
2997                 status = ql_set_routing_reg(qdev, i, 0, 0);
2998                 if (status) {
2999                         QPRINTK(qdev, IFUP, ERR,
3000                                 "Failed to init routing register for CAM packets.\n");
3001                         goto exit;
3002                 }
3003         }
3004
3005         status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
3006         if (status) {
3007                 QPRINTK(qdev, IFUP, ERR,
3008                         "Failed to init routing register for error packets.\n");
3009                 goto exit;
3010         }
3011         status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
3012         if (status) {
3013                 QPRINTK(qdev, IFUP, ERR,
3014                         "Failed to init routing register for broadcast packets.\n");
3015                 goto exit;
3016         }
3017         /* If we have more than one inbound queue, then turn on RSS in the
3018          * routing block.
3019          */
3020         if (qdev->rss_ring_count > 1) {
3021                 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
3022                                         RT_IDX_RSS_MATCH, 1);
3023                 if (status) {
3024                         QPRINTK(qdev, IFUP, ERR,
3025                                 "Failed to init routing register for MATCH RSS packets.\n");
3026                         goto exit;
3027                 }
3028         }
3029
3030         status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
3031                                     RT_IDX_CAM_HIT, 1);
3032         if (status)
3033                 QPRINTK(qdev, IFUP, ERR,
3034                         "Failed to init routing register for CAM packets.\n");
3035 exit:
3036         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3037         return status;
3038 }
3039
3040 int ql_cam_route_initialize(struct ql_adapter *qdev)
3041 {
3042         int status;
3043
3044         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3045         if (status)
3046                 return status;
3047         status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3048                              MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3049         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3050         if (status) {
3051                 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3052                 return status;
3053         }
3054
3055         status = ql_route_initialize(qdev);
3056         if (status)
3057                 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3058
3059         return status;
3060 }
3061
3062 static int ql_adapter_initialize(struct ql_adapter *qdev)
3063 {
3064         u32 value, mask;
3065         int i;
3066         int status = 0;
3067
3068         /*
3069          * Set up the System register to halt on errors.
3070          */
3071         value = SYS_EFE | SYS_FAE;
3072         mask = value << 16;
3073         ql_write32(qdev, SYS, mask | value);
3074
3075         /* Set the default queue, and VLAN behavior. */
3076         value = NIC_RCV_CFG_DFQ | NIC_RCV_CFG_RV;
3077         mask = NIC_RCV_CFG_DFQ_MASK | (NIC_RCV_CFG_RV << 16);
3078         ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3079
3080         /* Set the MPI interrupt to enabled. */
3081         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3082
3083         /* Enable the function, set pagesize, enable error checking. */
3084         value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3085             FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
3086
3087         /* Set/clear header splitting. */
3088         mask = FSC_VM_PAGESIZE_MASK |
3089             FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3090         ql_write32(qdev, FSC, mask | value);
3091
3092         ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3093                 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3094
3095         /* Start up the rx queues. */
3096         for (i = 0; i < qdev->rx_ring_count; i++) {
3097                 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3098                 if (status) {
3099                         QPRINTK(qdev, IFUP, ERR,
3100                                 "Failed to start rx ring[%d].\n", i);
3101                         return status;
3102                 }
3103         }
3104
3105         /* If there is more than one inbound completion queue
3106          * then download a RICB to configure RSS.
3107          */
3108         if (qdev->rss_ring_count > 1) {
3109                 status = ql_start_rss(qdev);
3110                 if (status) {
3111                         QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3112                         return status;
3113                 }
3114         }
3115
3116         /* Start up the tx queues. */
3117         for (i = 0; i < qdev->tx_ring_count; i++) {
3118                 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3119                 if (status) {
3120                         QPRINTK(qdev, IFUP, ERR,
3121                                 "Failed to start tx ring[%d].\n", i);
3122                         return status;
3123                 }
3124         }
3125
3126         /* Initialize the port and set the max framesize. */
3127         status = qdev->nic_ops->port_initialize(qdev);
3128        if (status) {
3129               QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3130               return status;
3131        }
3132
3133         /* Set up the MAC address and frame routing filter. */
3134         status = ql_cam_route_initialize(qdev);
3135         if (status) {
3136                 QPRINTK(qdev, IFUP, ERR,
3137                                 "Failed to init CAM/Routing tables.\n");
3138                 return status;
3139         }
3140
3141         /* Start NAPI for the RSS queues. */
3142         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3143                 QPRINTK(qdev, IFUP, DEBUG, "Enabling NAPI for rx_ring[%d].\n",
3144                         i);
3145                 napi_enable(&qdev->rx_ring[i].napi);
3146         }
3147
3148         return status;
3149 }
3150
3151 /* Issue soft reset to chip. */
3152 static int ql_adapter_reset(struct ql_adapter *qdev)
3153 {
3154         u32 value;
3155         int status = 0;
3156         unsigned long end_jiffies = jiffies +
3157                 max((unsigned long)1, usecs_to_jiffies(30));
3158
3159         ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3160
3161         do {
3162                 value = ql_read32(qdev, RST_FO);
3163                 if ((value & RST_FO_FR) == 0)
3164                         break;
3165                 cpu_relax();
3166         } while (time_before(jiffies, end_jiffies));
3167
3168         if (value & RST_FO_FR) {
3169                 QPRINTK(qdev, IFDOWN, ERR,
3170                         "ETIMEOUT!!! errored out of resetting the chip!\n");
3171                 status = -ETIMEDOUT;
3172         }
3173
3174         return status;
3175 }
3176
3177 static void ql_display_dev_info(struct net_device *ndev)
3178 {
3179         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3180
3181         QPRINTK(qdev, PROBE, INFO,
3182                 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3183                 "XG Roll = %d, XG Rev = %d.\n",
3184                 qdev->func,
3185                 qdev->chip_rev_id & 0x0000000f,
3186                 qdev->chip_rev_id >> 4 & 0x0000000f,
3187                 qdev->chip_rev_id >> 8 & 0x0000000f,
3188                 qdev->chip_rev_id >> 12 & 0x0000000f);
3189         QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3190 }
3191
3192 static int ql_adapter_down(struct ql_adapter *qdev)
3193 {
3194         int i, status = 0;
3195         struct rx_ring *rx_ring;
3196
3197         netif_carrier_off(qdev->ndev);
3198
3199         /* Don't kill the reset worker thread if we
3200          * are in the process of recovery.
3201          */
3202         if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3203                 cancel_delayed_work_sync(&qdev->asic_reset_work);
3204         cancel_delayed_work_sync(&qdev->mpi_reset_work);
3205         cancel_delayed_work_sync(&qdev->mpi_work);
3206         cancel_delayed_work_sync(&qdev->mpi_idc_work);
3207         cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
3208
3209         /* The default queue at index 0 is always processed in
3210          * a workqueue.
3211          */
3212         cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3213
3214         /* The rest of the rx_rings are processed in
3215          * a workqueue only if it's a single interrupt
3216          * environment (MSI/Legacy).
3217          */
3218         for (i = 1; i < qdev->rx_ring_count; i++) {
3219                 rx_ring = &qdev->rx_ring[i];
3220                 /* Only the RSS rings use NAPI on multi irq
3221                  * environment.  Outbound completion processing
3222                  * is done in interrupt context.
3223                  */
3224                 if (i >= qdev->rss_ring_first_cq_id) {
3225                         napi_disable(&rx_ring->napi);
3226                 } else {
3227                         cancel_delayed_work_sync(&rx_ring->rx_work);
3228                 }
3229         }
3230
3231         clear_bit(QL_ADAPTER_UP, &qdev->flags);
3232
3233         ql_disable_interrupts(qdev);
3234
3235         ql_tx_ring_clean(qdev);
3236
3237         ql_free_rx_buffers(qdev);
3238         spin_lock(&qdev->hw_lock);
3239         status = ql_adapter_reset(qdev);
3240         if (status)
3241                 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3242                         qdev->func);
3243         spin_unlock(&qdev->hw_lock);
3244         return status;
3245 }
3246
3247 static int ql_adapter_up(struct ql_adapter *qdev)
3248 {
3249         int err = 0;
3250
3251         spin_lock(&qdev->hw_lock);
3252         err = ql_adapter_initialize(qdev);
3253         if (err) {
3254                 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3255                 spin_unlock(&qdev->hw_lock);
3256                 goto err_init;
3257         }
3258         spin_unlock(&qdev->hw_lock);
3259         set_bit(QL_ADAPTER_UP, &qdev->flags);
3260         ql_alloc_rx_buffers(qdev);
3261         if ((ql_read32(qdev, STS) & qdev->port_init))
3262                 netif_carrier_on(qdev->ndev);
3263         ql_enable_interrupts(qdev);
3264         ql_enable_all_completion_interrupts(qdev);
3265         netif_tx_start_all_queues(qdev->ndev);
3266
3267         return 0;
3268 err_init:
3269         ql_adapter_reset(qdev);
3270         return err;
3271 }
3272
3273 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3274 {
3275         ql_free_mem_resources(qdev);
3276         ql_free_irq(qdev);
3277 }
3278
3279 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3280 {
3281         int status = 0;
3282
3283         if (ql_alloc_mem_resources(qdev)) {
3284                 QPRINTK(qdev, IFUP, ERR, "Unable to  allocate memory.\n");
3285                 return -ENOMEM;
3286         }
3287         status = ql_request_irq(qdev);
3288         if (status)
3289                 goto err_irq;
3290         return status;
3291 err_irq:
3292         ql_free_mem_resources(qdev);
3293         return status;
3294 }
3295
3296 static int qlge_close(struct net_device *ndev)
3297 {
3298         struct ql_adapter *qdev = netdev_priv(ndev);
3299
3300         /*
3301          * Wait for device to recover from a reset.
3302          * (Rarely happens, but possible.)
3303          */
3304         while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3305                 msleep(1);
3306         ql_adapter_down(qdev);
3307         ql_release_adapter_resources(qdev);
3308         return 0;
3309 }
3310
3311 static int ql_configure_rings(struct ql_adapter *qdev)
3312 {
3313         int i;
3314         struct rx_ring *rx_ring;
3315         struct tx_ring *tx_ring;
3316         int cpu_cnt = num_online_cpus();
3317
3318         /*
3319          * For each processor present we allocate one
3320          * rx_ring for outbound completions, and one
3321          * rx_ring for inbound completions.  Plus there is
3322          * always the one default queue.  For the CPU
3323          * counts we end up with the following rx_rings:
3324          * rx_ring count =
3325          *  one default queue +
3326          *  (CPU count * outbound completion rx_ring) +
3327          *  (CPU count * inbound (RSS) completion rx_ring)
3328          * To keep it simple we limit the total number of
3329          * queues to < 32, so we truncate CPU to 8.
3330          * This limitation can be removed when requested.
3331          */
3332
3333         if (cpu_cnt > MAX_CPUS)
3334                 cpu_cnt = MAX_CPUS;
3335
3336         /*
3337          * rx_ring[0] is always the default queue.
3338          */
3339         /* Allocate outbound completion ring for each CPU. */
3340         qdev->tx_ring_count = cpu_cnt;
3341         /* Allocate inbound completion (RSS) ring for each CPU. */
3342         qdev->rss_ring_count = cpu_cnt;
3343         /* cq_id for the first inbound ring handler. */
3344         qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3345         /*
3346          * qdev->rx_ring_count:
3347          * Total number of rx_rings.  This includes the one
3348          * default queue, a number of outbound completion
3349          * handler rx_rings, and the number of inbound
3350          * completion handler rx_rings.
3351          */
3352         qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3353         netif_set_gso_max_size(qdev->ndev, 65536);
3354
3355         for (i = 0; i < qdev->tx_ring_count; i++) {
3356                 tx_ring = &qdev->tx_ring[i];
3357                 memset((void *)tx_ring, 0, sizeof(tx_ring));
3358                 tx_ring->qdev = qdev;
3359                 tx_ring->wq_id = i;
3360                 tx_ring->wq_len = qdev->tx_ring_size;
3361                 tx_ring->wq_size =
3362                     tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3363
3364                 /*
3365                  * The completion queue ID for the tx rings start
3366                  * immediately after the default Q ID, which is zero.
3367                  */
3368                 tx_ring->cq_id = i + 1;
3369         }
3370
3371         for (i = 0; i < qdev->rx_ring_count; i++) {
3372                 rx_ring = &qdev->rx_ring[i];
3373                 memset((void *)rx_ring, 0, sizeof(rx_ring));
3374                 rx_ring->qdev = qdev;
3375                 rx_ring->cq_id = i;
3376                 rx_ring->cpu = i % cpu_cnt;     /* CPU to run handler on. */
3377                 if (i == 0) {   /* Default queue at index 0. */
3378                         /*
3379                          * Default queue handles bcast/mcast plus
3380                          * async events.  Needs buffers.
3381                          */
3382                         rx_ring->cq_len = qdev->rx_ring_size;
3383                         rx_ring->cq_size =
3384                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3385                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3386                         rx_ring->lbq_size =
3387                             rx_ring->lbq_len * sizeof(__le64);
3388                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3389                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3390                         rx_ring->sbq_size =
3391                             rx_ring->sbq_len * sizeof(__le64);
3392                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3393                         rx_ring->type = DEFAULT_Q;
3394                 } else if (i < qdev->rss_ring_first_cq_id) {
3395                         /*
3396                          * Outbound queue handles outbound completions only.
3397                          */
3398                         /* outbound cq is same size as tx_ring it services. */
3399                         rx_ring->cq_len = qdev->tx_ring_size;
3400                         rx_ring->cq_size =
3401                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3402                         rx_ring->lbq_len = 0;
3403                         rx_ring->lbq_size = 0;
3404                         rx_ring->lbq_buf_size = 0;
3405                         rx_ring->sbq_len = 0;
3406                         rx_ring->sbq_size = 0;
3407                         rx_ring->sbq_buf_size = 0;
3408                         rx_ring->type = TX_Q;
3409                 } else {        /* Inbound completions (RSS) queues */
3410                         /*
3411                          * Inbound queues handle unicast frames only.
3412                          */
3413                         rx_ring->cq_len = qdev->rx_ring_size;
3414                         rx_ring->cq_size =
3415                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3416                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3417                         rx_ring->lbq_size =
3418                             rx_ring->lbq_len * sizeof(__le64);
3419                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3420                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3421                         rx_ring->sbq_size =
3422                             rx_ring->sbq_len * sizeof(__le64);
3423                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3424                         rx_ring->type = RX_Q;
3425                 }
3426         }
3427         return 0;
3428 }
3429
3430 static int qlge_open(struct net_device *ndev)
3431 {
3432         int err = 0;
3433         struct ql_adapter *qdev = netdev_priv(ndev);
3434
3435         err = ql_configure_rings(qdev);
3436         if (err)
3437                 return err;
3438
3439         err = ql_get_adapter_resources(qdev);
3440         if (err)
3441                 goto error_up;
3442
3443         err = ql_adapter_up(qdev);
3444         if (err)
3445                 goto error_up;
3446
3447         return err;
3448
3449 error_up:
3450         ql_release_adapter_resources(qdev);
3451         return err;
3452 }
3453
3454 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3455 {
3456         struct ql_adapter *qdev = netdev_priv(ndev);
3457
3458         if (ndev->mtu == 1500 && new_mtu == 9000) {
3459                 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3460                 queue_delayed_work(qdev->workqueue,
3461                                 &qdev->mpi_port_cfg_work, 0);
3462         } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3463                 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3464         } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3465                    (ndev->mtu == 9000 && new_mtu == 9000)) {
3466                 return 0;
3467         } else
3468                 return -EINVAL;
3469         ndev->mtu = new_mtu;
3470         return 0;
3471 }
3472
3473 static struct net_device_stats *qlge_get_stats(struct net_device
3474                                                *ndev)
3475 {
3476         struct ql_adapter *qdev = netdev_priv(ndev);
3477         return &qdev->stats;
3478 }
3479
3480 static void qlge_set_multicast_list(struct net_device *ndev)
3481 {
3482         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3483         struct dev_mc_list *mc_ptr;
3484         int i, status;
3485
3486         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3487         if (status)
3488                 return;
3489         spin_lock(&qdev->hw_lock);
3490         /*
3491          * Set or clear promiscuous mode if a
3492          * transition is taking place.
3493          */
3494         if (ndev->flags & IFF_PROMISC) {
3495                 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3496                         if (ql_set_routing_reg
3497                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3498                                 QPRINTK(qdev, HW, ERR,
3499                                         "Failed to set promiscous mode.\n");
3500                         } else {
3501                                 set_bit(QL_PROMISCUOUS, &qdev->flags);
3502                         }
3503                 }
3504         } else {
3505                 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3506                         if (ql_set_routing_reg
3507                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3508                                 QPRINTK(qdev, HW, ERR,
3509                                         "Failed to clear promiscous mode.\n");
3510                         } else {
3511                                 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3512                         }
3513                 }
3514         }
3515
3516         /*
3517          * Set or clear all multicast mode if a
3518          * transition is taking place.
3519          */
3520         if ((ndev->flags & IFF_ALLMULTI) ||
3521             (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3522                 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3523                         if (ql_set_routing_reg
3524                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3525                                 QPRINTK(qdev, HW, ERR,
3526                                         "Failed to set all-multi mode.\n");
3527                         } else {
3528                                 set_bit(QL_ALLMULTI, &qdev->flags);
3529                         }
3530                 }
3531         } else {
3532                 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3533                         if (ql_set_routing_reg
3534                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3535                                 QPRINTK(qdev, HW, ERR,
3536                                         "Failed to clear all-multi mode.\n");
3537                         } else {
3538                                 clear_bit(QL_ALLMULTI, &qdev->flags);
3539                         }
3540                 }
3541         }
3542
3543         if (ndev->mc_count) {
3544                 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3545                 if (status)
3546                         goto exit;
3547                 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3548                      i++, mc_ptr = mc_ptr->next)
3549                         if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3550                                                 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3551                                 QPRINTK(qdev, HW, ERR,
3552                                         "Failed to loadmulticast address.\n");
3553                                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3554                                 goto exit;
3555                         }
3556                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3557                 if (ql_set_routing_reg
3558                     (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3559                         QPRINTK(qdev, HW, ERR,
3560                                 "Failed to set multicast match mode.\n");
3561                 } else {
3562                         set_bit(QL_ALLMULTI, &qdev->flags);
3563                 }
3564         }
3565 exit:
3566         spin_unlock(&qdev->hw_lock);
3567         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3568 }
3569
3570 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3571 {
3572         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3573         struct sockaddr *addr = p;
3574         int status;
3575
3576         if (netif_running(ndev))
3577                 return -EBUSY;
3578
3579         if (!is_valid_ether_addr(addr->sa_data))
3580                 return -EADDRNOTAVAIL;
3581         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3582
3583         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3584         if (status)
3585                 return status;
3586         spin_lock(&qdev->hw_lock);
3587         status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3588                         MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3589         spin_unlock(&qdev->hw_lock);
3590         if (status)
3591                 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3592         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3593         return status;
3594 }
3595
3596 static void qlge_tx_timeout(struct net_device *ndev)
3597 {
3598         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3599         ql_queue_asic_error(qdev);
3600 }
3601
3602 static void ql_asic_reset_work(struct work_struct *work)
3603 {
3604         struct ql_adapter *qdev =
3605             container_of(work, struct ql_adapter, asic_reset_work.work);
3606         int status;
3607
3608         status = ql_adapter_down(qdev);
3609         if (status)
3610                 goto error;
3611
3612         status = ql_adapter_up(qdev);
3613         if (status)
3614                 goto error;
3615
3616         return;
3617 error:
3618         QPRINTK(qdev, IFUP, ALERT,
3619                 "Driver up/down cycle failed, closing device\n");
3620         rtnl_lock();
3621         set_bit(QL_ADAPTER_UP, &qdev->flags);
3622         dev_close(qdev->ndev);
3623         rtnl_unlock();
3624 }
3625
3626 static struct nic_operations qla8012_nic_ops = {
3627         .get_flash              = ql_get_8012_flash_params,
3628         .port_initialize        = ql_8012_port_initialize,
3629 };
3630
3631 static struct nic_operations qla8000_nic_ops = {
3632         .get_flash              = ql_get_8000_flash_params,
3633         .port_initialize        = ql_8000_port_initialize,
3634 };
3635
3636
3637 static void ql_get_board_info(struct ql_adapter *qdev)
3638 {
3639         qdev->func =
3640             (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3641         if (qdev->func) {
3642                 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3643                 qdev->port_link_up = STS_PL1;
3644                 qdev->port_init = STS_PI1;
3645                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3646                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3647         } else {
3648                 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3649                 qdev->port_link_up = STS_PL0;
3650                 qdev->port_init = STS_PI0;
3651                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3652                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3653         }
3654         qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3655         qdev->device_id = qdev->pdev->device;
3656         if (qdev->device_id == QLGE_DEVICE_ID_8012)
3657                 qdev->nic_ops = &qla8012_nic_ops;
3658         else if (qdev->device_id == QLGE_DEVICE_ID_8000)
3659                 qdev->nic_ops = &qla8000_nic_ops;
3660 }
3661
3662 static void ql_release_all(struct pci_dev *pdev)
3663 {
3664         struct net_device *ndev = pci_get_drvdata(pdev);
3665         struct ql_adapter *qdev = netdev_priv(ndev);
3666
3667         if (qdev->workqueue) {
3668                 destroy_workqueue(qdev->workqueue);
3669                 qdev->workqueue = NULL;
3670         }
3671         if (qdev->q_workqueue) {
3672                 destroy_workqueue(qdev->q_workqueue);
3673                 qdev->q_workqueue = NULL;
3674         }
3675         if (qdev->reg_base)
3676                 iounmap(qdev->reg_base);
3677         if (qdev->doorbell_area)
3678                 iounmap(qdev->doorbell_area);
3679         pci_release_regions(pdev);
3680         pci_set_drvdata(pdev, NULL);
3681 }
3682
3683 static int __devinit ql_init_device(struct pci_dev *pdev,
3684                                     struct net_device *ndev, int cards_found)
3685 {
3686         struct ql_adapter *qdev = netdev_priv(ndev);
3687         int pos, err = 0;
3688         u16 val16;
3689
3690         memset((void *)qdev, 0, sizeof(qdev));
3691         err = pci_enable_device(pdev);
3692         if (err) {
3693                 dev_err(&pdev->dev, "PCI device enable failed.\n");
3694                 return err;
3695         }
3696
3697         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3698         if (pos <= 0) {
3699                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3700                         "aborting.\n");
3701                 goto err_out;
3702         } else {
3703                 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3704                 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3705                 val16 |= (PCI_EXP_DEVCTL_CERE |
3706                           PCI_EXP_DEVCTL_NFERE |
3707                           PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3708                 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3709         }
3710
3711         err = pci_request_regions(pdev, DRV_NAME);
3712         if (err) {
3713                 dev_err(&pdev->dev, "PCI region request failed.\n");
3714                 goto err_out;
3715         }
3716
3717         pci_set_master(pdev);
3718         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3719                 set_bit(QL_DMA64, &qdev->flags);
3720                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3721         } else {
3722                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3723                 if (!err)
3724                        err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3725         }
3726
3727         if (err) {
3728                 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3729                 goto err_out;
3730         }
3731
3732         pci_set_drvdata(pdev, ndev);
3733         qdev->reg_base =
3734             ioremap_nocache(pci_resource_start(pdev, 1),
3735                             pci_resource_len(pdev, 1));
3736         if (!qdev->reg_base) {
3737                 dev_err(&pdev->dev, "Register mapping failed.\n");
3738                 err = -ENOMEM;
3739                 goto err_out;
3740         }
3741
3742         qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3743         qdev->doorbell_area =
3744             ioremap_nocache(pci_resource_start(pdev, 3),
3745                             pci_resource_len(pdev, 3));
3746         if (!qdev->doorbell_area) {
3747                 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3748                 err = -ENOMEM;
3749                 goto err_out;
3750         }
3751
3752         qdev->ndev = ndev;
3753         qdev->pdev = pdev;
3754         ql_get_board_info(qdev);
3755         qdev->msg_enable = netif_msg_init(debug, default_msg);
3756         spin_lock_init(&qdev->hw_lock);
3757         spin_lock_init(&qdev->stats_lock);
3758
3759         /* make sure the EEPROM is good */
3760         err = qdev->nic_ops->get_flash(qdev);
3761         if (err) {
3762                 dev_err(&pdev->dev, "Invalid FLASH.\n");
3763                 goto err_out;
3764         }
3765
3766         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3767
3768         /* Set up the default ring sizes. */
3769         qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3770         qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3771
3772         /* Set up the coalescing parameters. */
3773         qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3774         qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3775         qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3776         qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3777
3778         /*
3779          * Set up the operating parameters.
3780          */
3781         qdev->rx_csum = 1;
3782
3783         qdev->q_workqueue = create_workqueue(ndev->name);
3784         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3785         INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3786         INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3787         INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3788         INIT_DELAYED_WORK(&qdev->mpi_port_cfg_work, ql_mpi_port_cfg_work);
3789         INIT_DELAYED_WORK(&qdev->mpi_idc_work, ql_mpi_idc_work);
3790         mutex_init(&qdev->mpi_mutex);
3791         init_completion(&qdev->ide_completion);
3792
3793         if (!cards_found) {
3794                 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3795                 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3796                          DRV_NAME, DRV_VERSION);
3797         }
3798         return 0;
3799 err_out:
3800         ql_release_all(pdev);
3801         pci_disable_device(pdev);
3802         return err;
3803 }
3804
3805
3806 static const struct net_device_ops qlge_netdev_ops = {
3807         .ndo_open               = qlge_open,
3808         .ndo_stop               = qlge_close,
3809         .ndo_start_xmit         = qlge_send,
3810         .ndo_change_mtu         = qlge_change_mtu,
3811         .ndo_get_stats          = qlge_get_stats,
3812         .ndo_set_multicast_list = qlge_set_multicast_list,
3813         .ndo_set_mac_address    = qlge_set_mac_address,
3814         .ndo_validate_addr      = eth_validate_addr,
3815         .ndo_tx_timeout         = qlge_tx_timeout,
3816         .ndo_vlan_rx_register   = ql_vlan_rx_register,
3817         .ndo_vlan_rx_add_vid    = ql_vlan_rx_add_vid,
3818         .ndo_vlan_rx_kill_vid   = ql_vlan_rx_kill_vid,
3819 };
3820
3821 static int __devinit qlge_probe(struct pci_dev *pdev,
3822                                 const struct pci_device_id *pci_entry)
3823 {
3824         struct net_device *ndev = NULL;
3825         struct ql_adapter *qdev = NULL;
3826         static int cards_found = 0;
3827         int err = 0;
3828
3829         ndev = alloc_etherdev_mq(sizeof(struct ql_adapter),
3830                         min(MAX_CPUS, (int)num_online_cpus()));
3831         if (!ndev)
3832                 return -ENOMEM;
3833
3834         err = ql_init_device(pdev, ndev, cards_found);
3835         if (err < 0) {
3836                 free_netdev(ndev);
3837                 return err;
3838         }
3839
3840         qdev = netdev_priv(ndev);
3841         SET_NETDEV_DEV(ndev, &pdev->dev);
3842         ndev->features = (0
3843                           | NETIF_F_IP_CSUM
3844                           | NETIF_F_SG
3845                           | NETIF_F_TSO
3846                           | NETIF_F_TSO6
3847                           | NETIF_F_TSO_ECN
3848                           | NETIF_F_HW_VLAN_TX
3849                           | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3850         ndev->features |= NETIF_F_GRO;
3851
3852         if (test_bit(QL_DMA64, &qdev->flags))
3853                 ndev->features |= NETIF_F_HIGHDMA;
3854
3855         /*
3856          * Set up net_device structure.
3857          */
3858         ndev->tx_queue_len = qdev->tx_ring_size;
3859         ndev->irq = pdev->irq;
3860
3861         ndev->netdev_ops = &qlge_netdev_ops;
3862         SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
3863         ndev->watchdog_timeo = 10 * HZ;
3864
3865         err = register_netdev(ndev);
3866         if (err) {
3867                 dev_err(&pdev->dev, "net device registration failed.\n");
3868                 ql_release_all(pdev);
3869                 pci_disable_device(pdev);
3870                 return err;
3871         }
3872         netif_carrier_off(ndev);
3873         ql_display_dev_info(ndev);
3874         cards_found++;
3875         return 0;
3876 }
3877
3878 static void __devexit qlge_remove(struct pci_dev *pdev)
3879 {
3880         struct net_device *ndev = pci_get_drvdata(pdev);
3881         unregister_netdev(ndev);
3882         ql_release_all(pdev);
3883         pci_disable_device(pdev);
3884         free_netdev(ndev);
3885 }
3886
3887 /*
3888  * This callback is called by the PCI subsystem whenever
3889  * a PCI bus error is detected.
3890  */
3891 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3892                                                enum pci_channel_state state)
3893 {
3894         struct net_device *ndev = pci_get_drvdata(pdev);
3895         struct ql_adapter *qdev = netdev_priv(ndev);
3896
3897         if (netif_running(ndev))
3898                 ql_adapter_down(qdev);
3899
3900         pci_disable_device(pdev);
3901
3902         /* Request a slot reset. */
3903         return PCI_ERS_RESULT_NEED_RESET;
3904 }
3905
3906 /*
3907  * This callback is called after the PCI buss has been reset.
3908  * Basically, this tries to restart the card from scratch.
3909  * This is a shortened version of the device probe/discovery code,
3910  * it resembles the first-half of the () routine.
3911  */
3912 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3913 {
3914         struct net_device *ndev = pci_get_drvdata(pdev);
3915         struct ql_adapter *qdev = netdev_priv(ndev);
3916
3917         if (pci_enable_device(pdev)) {
3918                 QPRINTK(qdev, IFUP, ERR,
3919                         "Cannot re-enable PCI device after reset.\n");
3920                 return PCI_ERS_RESULT_DISCONNECT;
3921         }
3922
3923         pci_set_master(pdev);
3924
3925         netif_carrier_off(ndev);
3926         ql_adapter_reset(qdev);
3927
3928         /* Make sure the EEPROM is good */
3929         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3930
3931         if (!is_valid_ether_addr(ndev->perm_addr)) {
3932                 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3933                 return PCI_ERS_RESULT_DISCONNECT;
3934         }
3935
3936         return PCI_ERS_RESULT_RECOVERED;
3937 }
3938
3939 static void qlge_io_resume(struct pci_dev *pdev)
3940 {
3941         struct net_device *ndev = pci_get_drvdata(pdev);
3942         struct ql_adapter *qdev = netdev_priv(ndev);
3943
3944         pci_set_master(pdev);
3945
3946         if (netif_running(ndev)) {
3947                 if (ql_adapter_up(qdev)) {
3948                         QPRINTK(qdev, IFUP, ERR,
3949                                 "Device initialization failed after reset.\n");
3950                         return;
3951                 }
3952         }
3953
3954         netif_device_attach(ndev);
3955 }
3956
3957 static struct pci_error_handlers qlge_err_handler = {
3958         .error_detected = qlge_io_error_detected,
3959         .slot_reset = qlge_io_slot_reset,
3960         .resume = qlge_io_resume,
3961 };
3962
3963 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3964 {
3965         struct net_device *ndev = pci_get_drvdata(pdev);
3966         struct ql_adapter *qdev = netdev_priv(ndev);
3967         int err, i;
3968
3969         netif_device_detach(ndev);
3970
3971         if (netif_running(ndev)) {
3972                 err = ql_adapter_down(qdev);
3973                 if (!err)
3974                         return err;
3975         }
3976
3977         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++)
3978                 netif_napi_del(&qdev->rx_ring[i].napi);
3979
3980         err = pci_save_state(pdev);
3981         if (err)
3982                 return err;
3983
3984         pci_disable_device(pdev);
3985
3986         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3987
3988         return 0;
3989 }
3990
3991 #ifdef CONFIG_PM
3992 static int qlge_resume(struct pci_dev *pdev)
3993 {
3994         struct net_device *ndev = pci_get_drvdata(pdev);
3995         struct ql_adapter *qdev = netdev_priv(ndev);
3996         int err;
3997
3998         pci_set_power_state(pdev, PCI_D0);
3999         pci_restore_state(pdev);
4000         err = pci_enable_device(pdev);
4001         if (err) {
4002                 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
4003                 return err;
4004         }
4005         pci_set_master(pdev);
4006
4007         pci_enable_wake(pdev, PCI_D3hot, 0);
4008         pci_enable_wake(pdev, PCI_D3cold, 0);
4009
4010         if (netif_running(ndev)) {
4011                 err = ql_adapter_up(qdev);
4012                 if (err)
4013                         return err;
4014         }
4015
4016         netif_device_attach(ndev);
4017
4018         return 0;
4019 }
4020 #endif /* CONFIG_PM */
4021
4022 static void qlge_shutdown(struct pci_dev *pdev)
4023 {
4024         qlge_suspend(pdev, PMSG_SUSPEND);
4025 }
4026
4027 static struct pci_driver qlge_driver = {
4028         .name = DRV_NAME,
4029         .id_table = qlge_pci_tbl,
4030         .probe = qlge_probe,
4031         .remove = __devexit_p(qlge_remove),
4032 #ifdef CONFIG_PM
4033         .suspend = qlge_suspend,
4034         .resume = qlge_resume,
4035 #endif
4036         .shutdown = qlge_shutdown,
4037         .err_handler = &qlge_err_handler
4038 };
4039
4040 static int __init qlge_init_module(void)
4041 {
4042         return pci_register_driver(&qlge_driver);
4043 }
4044
4045 static void __exit qlge_exit(void)
4046 {
4047         pci_unregister_driver(&qlge_driver);
4048 }
4049
4050 module_init(qlge_init_module);
4051 module_exit(qlge_exit);