14c999ab42229dcce1b829f4676ed1d4e04c615d
[linux-2.6.git] / drivers / net / qlcnic / qlcnic_hw.c
1 /*
2  * Copyright (C) 2009 - QLogic Corporation.
3  * All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License
7  * as published by the Free Software Foundation; either version 2
8  * of the License, or (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18  * MA  02111-1307, USA.
19  *
20  * The full GNU General Public License is included in this distribution
21  * in the file called "COPYING".
22  *
23  */
24
25 #include "qlcnic.h"
26
27 #include <net/ip.h>
28
29 #define MASK(n) ((1ULL<<(n))-1)
30 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
31
32 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
33
34 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
35 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
36 #define CRB_WINDOW_2M   (0x130060)
37 #define CRB_HI(off)     ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
38 #define CRB_INDIRECT_2M (0x1e0000UL)
39
40
41 #ifndef readq
42 static inline u64 readq(void __iomem *addr)
43 {
44         return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
45 }
46 #endif
47
48 #ifndef writeq
49 static inline void writeq(u64 val, void __iomem *addr)
50 {
51         writel(((u32) (val)), (addr));
52         writel(((u32) (val >> 32)), (addr + 4));
53 }
54 #endif
55
56 static const struct crb_128M_2M_block_map
57 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
58     {{{0, 0,         0,         0} } },         /* 0: PCI */
59     {{{1, 0x0100000, 0x0102000, 0x120000},      /* 1: PCIE */
60           {1, 0x0110000, 0x0120000, 0x130000},
61           {1, 0x0120000, 0x0122000, 0x124000},
62           {1, 0x0130000, 0x0132000, 0x126000},
63           {1, 0x0140000, 0x0142000, 0x128000},
64           {1, 0x0150000, 0x0152000, 0x12a000},
65           {1, 0x0160000, 0x0170000, 0x110000},
66           {1, 0x0170000, 0x0172000, 0x12e000},
67           {0, 0x0000000, 0x0000000, 0x000000},
68           {0, 0x0000000, 0x0000000, 0x000000},
69           {0, 0x0000000, 0x0000000, 0x000000},
70           {0, 0x0000000, 0x0000000, 0x000000},
71           {0, 0x0000000, 0x0000000, 0x000000},
72           {0, 0x0000000, 0x0000000, 0x000000},
73           {1, 0x01e0000, 0x01e0800, 0x122000},
74           {0, 0x0000000, 0x0000000, 0x000000} } },
75         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
76     {{{0, 0,         0,         0} } },     /* 3: */
77     {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
78     {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
79     {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
80     {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
81     {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
82       {0, 0x0000000, 0x0000000, 0x000000},
83       {0, 0x0000000, 0x0000000, 0x000000},
84       {0, 0x0000000, 0x0000000, 0x000000},
85       {0, 0x0000000, 0x0000000, 0x000000},
86       {0, 0x0000000, 0x0000000, 0x000000},
87       {0, 0x0000000, 0x0000000, 0x000000},
88       {0, 0x0000000, 0x0000000, 0x000000},
89       {0, 0x0000000, 0x0000000, 0x000000},
90       {0, 0x0000000, 0x0000000, 0x000000},
91       {0, 0x0000000, 0x0000000, 0x000000},
92       {0, 0x0000000, 0x0000000, 0x000000},
93       {0, 0x0000000, 0x0000000, 0x000000},
94       {0, 0x0000000, 0x0000000, 0x000000},
95       {0, 0x0000000, 0x0000000, 0x000000},
96       {1, 0x08f0000, 0x08f2000, 0x172000} } },
97     {{{1, 0x0900000, 0x0902000, 0x174000},      /* 9: SQM1*/
98       {0, 0x0000000, 0x0000000, 0x000000},
99       {0, 0x0000000, 0x0000000, 0x000000},
100       {0, 0x0000000, 0x0000000, 0x000000},
101       {0, 0x0000000, 0x0000000, 0x000000},
102       {0, 0x0000000, 0x0000000, 0x000000},
103       {0, 0x0000000, 0x0000000, 0x000000},
104       {0, 0x0000000, 0x0000000, 0x000000},
105       {0, 0x0000000, 0x0000000, 0x000000},
106       {0, 0x0000000, 0x0000000, 0x000000},
107       {0, 0x0000000, 0x0000000, 0x000000},
108       {0, 0x0000000, 0x0000000, 0x000000},
109       {0, 0x0000000, 0x0000000, 0x000000},
110       {0, 0x0000000, 0x0000000, 0x000000},
111       {0, 0x0000000, 0x0000000, 0x000000},
112       {1, 0x09f0000, 0x09f2000, 0x176000} } },
113     {{{0, 0x0a00000, 0x0a02000, 0x178000},      /* 10: SQM2*/
114       {0, 0x0000000, 0x0000000, 0x000000},
115       {0, 0x0000000, 0x0000000, 0x000000},
116       {0, 0x0000000, 0x0000000, 0x000000},
117       {0, 0x0000000, 0x0000000, 0x000000},
118       {0, 0x0000000, 0x0000000, 0x000000},
119       {0, 0x0000000, 0x0000000, 0x000000},
120       {0, 0x0000000, 0x0000000, 0x000000},
121       {0, 0x0000000, 0x0000000, 0x000000},
122       {0, 0x0000000, 0x0000000, 0x000000},
123       {0, 0x0000000, 0x0000000, 0x000000},
124       {0, 0x0000000, 0x0000000, 0x000000},
125       {0, 0x0000000, 0x0000000, 0x000000},
126       {0, 0x0000000, 0x0000000, 0x000000},
127       {0, 0x0000000, 0x0000000, 0x000000},
128       {1, 0x0af0000, 0x0af2000, 0x17a000} } },
129     {{{0, 0x0b00000, 0x0b02000, 0x17c000},      /* 11: SQM3*/
130       {0, 0x0000000, 0x0000000, 0x000000},
131       {0, 0x0000000, 0x0000000, 0x000000},
132       {0, 0x0000000, 0x0000000, 0x000000},
133       {0, 0x0000000, 0x0000000, 0x000000},
134       {0, 0x0000000, 0x0000000, 0x000000},
135       {0, 0x0000000, 0x0000000, 0x000000},
136       {0, 0x0000000, 0x0000000, 0x000000},
137       {0, 0x0000000, 0x0000000, 0x000000},
138       {0, 0x0000000, 0x0000000, 0x000000},
139       {0, 0x0000000, 0x0000000, 0x000000},
140       {0, 0x0000000, 0x0000000, 0x000000},
141       {0, 0x0000000, 0x0000000, 0x000000},
142       {0, 0x0000000, 0x0000000, 0x000000},
143       {0, 0x0000000, 0x0000000, 0x000000},
144       {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
145         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
146         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
147         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
148         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
149         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
150         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
151         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
152         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
153         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
154         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
155         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
156         {{{0, 0,         0,         0} } },     /* 23: */
157         {{{0, 0,         0,         0} } },     /* 24: */
158         {{{0, 0,         0,         0} } },     /* 25: */
159         {{{0, 0,         0,         0} } },     /* 26: */
160         {{{0, 0,         0,         0} } },     /* 27: */
161         {{{0, 0,         0,         0} } },     /* 28: */
162         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
163     {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
164     {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
165         {{{0} } },                              /* 32: PCI */
166         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
167           {1, 0x2110000, 0x2120000, 0x130000},
168           {1, 0x2120000, 0x2122000, 0x124000},
169           {1, 0x2130000, 0x2132000, 0x126000},
170           {1, 0x2140000, 0x2142000, 0x128000},
171           {1, 0x2150000, 0x2152000, 0x12a000},
172           {1, 0x2160000, 0x2170000, 0x110000},
173           {1, 0x2170000, 0x2172000, 0x12e000},
174           {0, 0x0000000, 0x0000000, 0x000000},
175           {0, 0x0000000, 0x0000000, 0x000000},
176           {0, 0x0000000, 0x0000000, 0x000000},
177           {0, 0x0000000, 0x0000000, 0x000000},
178           {0, 0x0000000, 0x0000000, 0x000000},
179           {0, 0x0000000, 0x0000000, 0x000000},
180           {0, 0x0000000, 0x0000000, 0x000000},
181           {0, 0x0000000, 0x0000000, 0x000000} } },
182         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
183         {{{0} } },                              /* 35: */
184         {{{0} } },                              /* 36: */
185         {{{0} } },                              /* 37: */
186         {{{0} } },                              /* 38: */
187         {{{0} } },                              /* 39: */
188         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
189         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
190         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
191         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
192         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
193         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
194         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
195         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
196         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
197         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
198         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
199         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
200         {{{0} } },                              /* 52: */
201         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
202         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
203         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
204         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
205         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
206         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
207         {{{0} } },                              /* 59: I2C0 */
208         {{{0} } },                              /* 60: I2C1 */
209         {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
210         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
211         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
212 };
213
214 /*
215  * top 12 bits of crb internal address (hub, agent)
216  */
217 static const unsigned crb_hub_agt[64] = {
218         0,
219         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
220         QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
221         QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
222         0,
223         QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
224         QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
225         QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
226         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
227         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
228         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
229         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
230         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
231         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
232         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
233         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
234         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
235         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
236         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
237         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
238         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
239         QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
240         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
241         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
242         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
243         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
244         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
245         0,
246         QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
247         QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
248         0,
249         QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
250         0,
251         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
252         QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
253         0,
254         0,
255         0,
256         0,
257         0,
258         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
259         0,
260         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
261         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
262         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
263         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
264         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
265         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
266         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
267         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
268         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
269         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
270         0,
271         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
272         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
273         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
274         QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
275         0,
276         QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
277         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
278         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
279         0,
280         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
281         0,
282 };
283
284 /*  PCI Windowing for DDR regions.  */
285
286 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
287
288 int
289 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
290 {
291         int done = 0, timeout = 0;
292
293         while (!done) {
294                 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
295                 if (done == 1)
296                         break;
297                 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
298                         dev_err(&adapter->pdev->dev,
299                                 "Failed to acquire sem=%d lock;reg_id=%d\n",
300                                 sem, id_reg);
301                         return -EIO;
302                 }
303                 msleep(1);
304         }
305
306         if (id_reg)
307                 QLCWR32(adapter, id_reg, adapter->portnum);
308
309         return 0;
310 }
311
312 void
313 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
314 {
315         QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
316 }
317
318 static int
319 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
320                 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
321 {
322         u32 i, producer, consumer;
323         struct qlcnic_cmd_buffer *pbuf;
324         struct cmd_desc_type0 *cmd_desc;
325         struct qlcnic_host_tx_ring *tx_ring;
326
327         i = 0;
328
329         if (adapter->is_up != QLCNIC_ADAPTER_UP_MAGIC)
330                 return -EIO;
331
332         tx_ring = adapter->tx_ring;
333         __netif_tx_lock_bh(tx_ring->txq);
334
335         producer = tx_ring->producer;
336         consumer = tx_ring->sw_consumer;
337
338         if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
339                 netif_tx_stop_queue(tx_ring->txq);
340                 __netif_tx_unlock_bh(tx_ring->txq);
341                 adapter->stats.xmit_off++;
342                 return -EBUSY;
343         }
344
345         do {
346                 cmd_desc = &cmd_desc_arr[i];
347
348                 pbuf = &tx_ring->cmd_buf_arr[producer];
349                 pbuf->skb = NULL;
350                 pbuf->frag_count = 0;
351
352                 memcpy(&tx_ring->desc_head[producer],
353                         &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
354
355                 producer = get_next_index(producer, tx_ring->num_desc);
356                 i++;
357
358         } while (i != nr_desc);
359
360         tx_ring->producer = producer;
361
362         qlcnic_update_cmd_producer(adapter, tx_ring);
363
364         __netif_tx_unlock_bh(tx_ring->txq);
365
366         return 0;
367 }
368
369 static int
370 qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
371                                 unsigned op)
372 {
373         struct qlcnic_nic_req req;
374         struct qlcnic_mac_req *mac_req;
375         u64 word;
376
377         memset(&req, 0, sizeof(struct qlcnic_nic_req));
378         req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
379
380         word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
381         req.req_hdr = cpu_to_le64(word);
382
383         mac_req = (struct qlcnic_mac_req *)&req.words[0];
384         mac_req->op = op;
385         memcpy(mac_req->mac_addr, addr, 6);
386
387         return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
388 }
389
390 static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, u8 *addr)
391 {
392         struct list_head *head;
393         struct qlcnic_mac_list_s *cur;
394
395         /* look up if already exists */
396         list_for_each(head, &adapter->mac_list) {
397                 cur = list_entry(head, struct qlcnic_mac_list_s, list);
398                 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
399                         return 0;
400         }
401
402         cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
403         if (cur == NULL) {
404                 dev_err(&adapter->netdev->dev,
405                         "failed to add mac address filter\n");
406                 return -ENOMEM;
407         }
408         memcpy(cur->mac_addr, addr, ETH_ALEN);
409         list_add_tail(&cur->list, &adapter->mac_list);
410
411         return qlcnic_sre_macaddr_change(adapter,
412                                 cur->mac_addr, QLCNIC_MAC_ADD);
413 }
414
415 void qlcnic_set_multi(struct net_device *netdev)
416 {
417         struct qlcnic_adapter *adapter = netdev_priv(netdev);
418         struct dev_mc_list *mc_ptr;
419         u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
420         u32 mode = VPORT_MISS_MODE_DROP;
421
422         qlcnic_nic_add_mac(adapter, adapter->mac_addr);
423         qlcnic_nic_add_mac(adapter, bcast_addr);
424
425         if (netdev->flags & IFF_PROMISC) {
426                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
427                 goto send_fw_cmd;
428         }
429
430         if ((netdev->flags & IFF_ALLMULTI) ||
431             (netdev_mc_count(netdev) > adapter->max_mc_count)) {
432                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
433                 goto send_fw_cmd;
434         }
435
436         if (!netdev_mc_empty(netdev)) {
437                 netdev_for_each_mc_addr(mc_ptr, netdev) {
438                         qlcnic_nic_add_mac(adapter, mc_ptr->dmi_addr);
439                 }
440         }
441
442 send_fw_cmd:
443         qlcnic_nic_set_promisc(adapter, mode);
444 }
445
446 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
447 {
448         struct qlcnic_nic_req req;
449         u64 word;
450
451         memset(&req, 0, sizeof(struct qlcnic_nic_req));
452
453         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
454
455         word = QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
456                         ((u64)adapter->portnum << 16);
457         req.req_hdr = cpu_to_le64(word);
458
459         req.words[0] = cpu_to_le64(mode);
460
461         return qlcnic_send_cmd_descs(adapter,
462                                 (struct cmd_desc_type0 *)&req, 1);
463 }
464
465 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
466 {
467         struct qlcnic_mac_list_s *cur;
468         struct list_head *head = &adapter->mac_list;
469
470         while (!list_empty(head)) {
471                 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
472                 qlcnic_sre_macaddr_change(adapter,
473                                 cur->mac_addr, QLCNIC_MAC_DEL);
474                 list_del(&cur->list);
475                 kfree(cur);
476         }
477 }
478
479 #define QLCNIC_CONFIG_INTR_COALESCE     3
480
481 /*
482  * Send the interrupt coalescing parameter set by ethtool to the card.
483  */
484 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
485 {
486         struct qlcnic_nic_req req;
487         u64 word[6];
488         int rv, i;
489
490         memset(&req, 0, sizeof(struct qlcnic_nic_req));
491
492         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
493
494         word[0] = QLCNIC_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
495         req.req_hdr = cpu_to_le64(word[0]);
496
497         memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
498         for (i = 0; i < 6; i++)
499                 req.words[i] = cpu_to_le64(word[i]);
500
501         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
502         if (rv != 0)
503                 dev_err(&adapter->netdev->dev,
504                         "Could not send interrupt coalescing parameters\n");
505
506         return rv;
507 }
508
509 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
510 {
511         struct qlcnic_nic_req req;
512         u64 word;
513         int rv;
514
515         if ((adapter->flags & QLCNIC_LRO_ENABLED) == enable)
516                 return 0;
517
518         memset(&req, 0, sizeof(struct qlcnic_nic_req));
519
520         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
521
522         word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
523         req.req_hdr = cpu_to_le64(word);
524
525         req.words[0] = cpu_to_le64(enable);
526
527         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
528         if (rv != 0)
529                 dev_err(&adapter->netdev->dev,
530                         "Could not send configure hw lro request\n");
531
532         adapter->flags ^= QLCNIC_LRO_ENABLED;
533
534         return rv;
535 }
536
537 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, int enable)
538 {
539         struct qlcnic_nic_req req;
540         u64 word;
541         int rv;
542
543         if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
544                 return 0;
545
546         memset(&req, 0, sizeof(struct qlcnic_nic_req));
547
548         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
549
550         word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
551                 ((u64)adapter->portnum << 16);
552         req.req_hdr = cpu_to_le64(word);
553
554         req.words[0] = cpu_to_le64(enable);
555
556         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
557         if (rv != 0)
558                 dev_err(&adapter->netdev->dev,
559                         "Could not send configure bridge mode request\n");
560
561         adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
562
563         return rv;
564 }
565
566
567 #define RSS_HASHTYPE_IP_TCP     0x3
568
569 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
570 {
571         struct qlcnic_nic_req req;
572         u64 word;
573         int i, rv;
574
575         const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
576                         0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
577                         0x255b0ec26d5a56daULL };
578
579
580         memset(&req, 0, sizeof(struct qlcnic_nic_req));
581         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
582
583         word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
584         req.req_hdr = cpu_to_le64(word);
585
586         /*
587          * RSS request:
588          * bits 3-0: hash_method
589          *      5-4: hash_type_ipv4
590          *      7-6: hash_type_ipv6
591          *        8: enable
592          *        9: use indirection table
593          *    47-10: reserved
594          *    63-48: indirection table mask
595          */
596         word =  ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
597                 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
598                 ((u64)(enable & 0x1) << 8) |
599                 ((0x7ULL) << 48);
600         req.words[0] = cpu_to_le64(word);
601         for (i = 0; i < 5; i++)
602                 req.words[i+1] = cpu_to_le64(key[i]);
603
604         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
605         if (rv != 0)
606                 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
607
608         return rv;
609 }
610
611 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, u32 ip, int cmd)
612 {
613         struct qlcnic_nic_req req;
614         u64 word;
615         int rv;
616
617         memset(&req, 0, sizeof(struct qlcnic_nic_req));
618         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
619
620         word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
621         req.req_hdr = cpu_to_le64(word);
622
623         req.words[0] = cpu_to_le64(cmd);
624         req.words[1] = cpu_to_le64(ip);
625
626         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
627         if (rv != 0)
628                 dev_err(&adapter->netdev->dev,
629                                 "could not notify %s IP 0x%x reuqest\n",
630                                 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
631
632         return rv;
633 }
634
635 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable)
636 {
637         struct qlcnic_nic_req req;
638         u64 word;
639         int rv;
640
641         memset(&req, 0, sizeof(struct qlcnic_nic_req));
642         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
643
644         word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
645         req.req_hdr = cpu_to_le64(word);
646         req.words[0] = cpu_to_le64(enable | (enable << 8));
647
648         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
649         if (rv != 0)
650                 dev_err(&adapter->netdev->dev,
651                                 "could not configure link notification\n");
652
653         return rv;
654 }
655
656 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
657 {
658         struct qlcnic_nic_req req;
659         u64 word;
660         int rv;
661
662         memset(&req, 0, sizeof(struct qlcnic_nic_req));
663         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
664
665         word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
666                 ((u64)adapter->portnum << 16) |
667                 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
668
669         req.req_hdr = cpu_to_le64(word);
670
671         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
672         if (rv != 0)
673                 dev_err(&adapter->netdev->dev,
674                                  "could not cleanup lro flows\n");
675
676         return rv;
677 }
678
679 /*
680  * qlcnic_change_mtu - Change the Maximum Transfer Unit
681  * @returns 0 on success, negative on failure
682  */
683
684 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
685 {
686         struct qlcnic_adapter *adapter = netdev_priv(netdev);
687         int rc = 0;
688
689         if (mtu > P3_MAX_MTU) {
690                 dev_err(&adapter->netdev->dev, "mtu > %d bytes unsupported\n",
691                                                 P3_MAX_MTU);
692                 return -EINVAL;
693         }
694
695         rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
696
697         if (!rc)
698                 netdev->mtu = mtu;
699
700         return rc;
701 }
702
703 int qlcnic_get_mac_addr(struct qlcnic_adapter *adapter, u64 *mac)
704 {
705         u32 crbaddr, mac_hi, mac_lo;
706         int pci_func = adapter->ahw.pci_func;
707
708         crbaddr = CRB_MAC_BLOCK_START +
709                 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
710
711         mac_lo = QLCRD32(adapter, crbaddr);
712         mac_hi = QLCRD32(adapter, crbaddr+4);
713
714         if (pci_func & 1)
715                 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
716         else
717                 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
718
719         return 0;
720 }
721
722 /*
723  * Changes the CRB window to the specified window.
724  */
725  /* Returns < 0 if off is not valid,
726  *       1 if window access is needed. 'off' is set to offset from
727  *         CRB space in 128M pci map
728  *       0 if no window access is needed. 'off' is set to 2M addr
729  * In: 'off' is offset from base in 128M pci map
730  */
731 static int
732 qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter *adapter,
733                 ulong off, void __iomem **addr)
734 {
735         const struct crb_128M_2M_sub_block_map *m;
736
737         if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
738                 return -EINVAL;
739
740         off -= QLCNIC_PCI_CRBSPACE;
741
742         /*
743          * Try direct map
744          */
745         m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
746
747         if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
748                 *addr = adapter->ahw.pci_base0 + m->start_2M +
749                         (off - m->start_128M);
750                 return 0;
751         }
752
753         /*
754          * Not in direct map, use crb window
755          */
756         *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
757         return 1;
758 }
759
760 /*
761  * In: 'off' is offset from CRB space in 128M pci map
762  * Out: 'off' is 2M pci map addr
763  * side effect: lock crb window
764  */
765 static void
766 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
767 {
768         u32 window;
769         void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
770
771         off -= QLCNIC_PCI_CRBSPACE;
772
773         window = CRB_HI(off);
774
775         if (adapter->ahw.crb_win == window)
776                 return;
777
778         writel(window, addr);
779         if (readl(addr) != window) {
780                 if (printk_ratelimit())
781                         dev_warn(&adapter->pdev->dev,
782                                 "failed to set CRB window to %d off 0x%lx\n",
783                                 window, off);
784         }
785         adapter->ahw.crb_win = window;
786 }
787
788 int
789 qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, u32 data)
790 {
791         unsigned long flags;
792         int rv;
793         void __iomem *addr = NULL;
794
795         rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
796
797         if (rv == 0) {
798                 writel(data, addr);
799                 return 0;
800         }
801
802         if (rv > 0) {
803                 /* indirect access */
804                 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
805                 crb_win_lock(adapter);
806                 qlcnic_pci_set_crbwindow_2M(adapter, off);
807                 writel(data, addr);
808                 crb_win_unlock(adapter);
809                 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
810                 return 0;
811         }
812
813         dev_err(&adapter->pdev->dev,
814                         "%s: invalid offset: 0x%016lx\n", __func__, off);
815         dump_stack();
816         return -EIO;
817 }
818
819 u32
820 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
821 {
822         unsigned long flags;
823         int rv;
824         u32 data;
825         void __iomem *addr = NULL;
826
827         rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
828
829         if (rv == 0)
830                 return readl(addr);
831
832         if (rv > 0) {
833                 /* indirect access */
834                 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
835                 crb_win_lock(adapter);
836                 qlcnic_pci_set_crbwindow_2M(adapter, off);
837                 data = readl(addr);
838                 crb_win_unlock(adapter);
839                 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
840                 return data;
841         }
842
843         dev_err(&adapter->pdev->dev,
844                         "%s: invalid offset: 0x%016lx\n", __func__, off);
845         dump_stack();
846         return -1;
847 }
848
849
850 void __iomem *
851 qlcnic_get_ioaddr(struct qlcnic_adapter *adapter, u32 offset)
852 {
853         void __iomem *addr = NULL;
854
855         WARN_ON(qlcnic_pci_get_crb_addr_2M(adapter, offset, &addr));
856
857         return addr;
858 }
859
860
861 static int
862 qlcnic_pci_set_window_2M(struct qlcnic_adapter *adapter,
863                 u64 addr, u32 *start)
864 {
865         u32 window;
866
867         window = OCM_WIN_P3P(addr);
868
869         writel(window, adapter->ahw.ocm_win_crb);
870         /* read back to flush */
871         readl(adapter->ahw.ocm_win_crb);
872
873         adapter->ahw.ocm_win = window;
874         *start = QLCNIC_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
875         return 0;
876 }
877
878 static int
879 qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, u64 off,
880                 u64 *data, int op)
881 {
882         void __iomem *addr;
883         int ret;
884         u32 start;
885
886         mutex_lock(&adapter->ahw.mem_lock);
887
888         ret = qlcnic_pci_set_window_2M(adapter, off, &start);
889         if (ret != 0)
890                 goto unlock;
891
892         addr = adapter->ahw.pci_base0 + start;
893
894         if (op == 0)    /* read */
895                 *data = readq(addr);
896         else            /* write */
897                 writeq(*data, addr);
898
899 unlock:
900         mutex_unlock(&adapter->ahw.mem_lock);
901
902         return ret;
903 }
904
905 void
906 qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
907 {
908         void __iomem *addr = adapter->ahw.pci_base0 +
909                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
910
911         mutex_lock(&adapter->ahw.mem_lock);
912         *data = readq(addr);
913         mutex_unlock(&adapter->ahw.mem_lock);
914 }
915
916 void
917 qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
918 {
919         void __iomem *addr = adapter->ahw.pci_base0 +
920                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
921
922         mutex_lock(&adapter->ahw.mem_lock);
923         writeq(data, addr);
924         mutex_unlock(&adapter->ahw.mem_lock);
925 }
926
927 #define MAX_CTL_CHECK   1000
928
929 int
930 qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
931                 u64 off, u64 data)
932 {
933         int i, j, ret;
934         u32 temp, off8;
935         void __iomem *mem_crb;
936
937         /* Only 64-bit aligned access */
938         if (off & 7)
939                 return -EIO;
940
941         /* P3 onward, test agent base for MIU and SIU is same */
942         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
943                                 QLCNIC_ADDR_QDR_NET_MAX)) {
944                 mem_crb = qlcnic_get_ioaddr(adapter,
945                                 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
946                 goto correct;
947         }
948
949         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
950                 mem_crb = qlcnic_get_ioaddr(adapter,
951                                 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
952                 goto correct;
953         }
954
955         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
956                 return qlcnic_pci_mem_access_direct(adapter, off, &data, 1);
957
958         return -EIO;
959
960 correct:
961         off8 = off & ~0xf;
962
963         mutex_lock(&adapter->ahw.mem_lock);
964
965         writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
966         writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
967
968         i = 0;
969         writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
970         writel((TA_CTL_START | TA_CTL_ENABLE),
971                         (mem_crb + TEST_AGT_CTRL));
972
973         for (j = 0; j < MAX_CTL_CHECK; j++) {
974                 temp = readl(mem_crb + TEST_AGT_CTRL);
975                 if ((temp & TA_CTL_BUSY) == 0)
976                         break;
977         }
978
979         if (j >= MAX_CTL_CHECK) {
980                 ret = -EIO;
981                 goto done;
982         }
983
984         i = (off & 0xf) ? 0 : 2;
985         writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
986                         mem_crb + MIU_TEST_AGT_WRDATA(i));
987         writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
988                         mem_crb + MIU_TEST_AGT_WRDATA(i+1));
989         i = (off & 0xf) ? 2 : 0;
990
991         writel(data & 0xffffffff,
992                         mem_crb + MIU_TEST_AGT_WRDATA(i));
993         writel((data >> 32) & 0xffffffff,
994                         mem_crb + MIU_TEST_AGT_WRDATA(i+1));
995
996         writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
997         writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
998                         (mem_crb + TEST_AGT_CTRL));
999
1000         for (j = 0; j < MAX_CTL_CHECK; j++) {
1001                 temp = readl(mem_crb + TEST_AGT_CTRL);
1002                 if ((temp & TA_CTL_BUSY) == 0)
1003                         break;
1004         }
1005
1006         if (j >= MAX_CTL_CHECK) {
1007                 if (printk_ratelimit())
1008                         dev_err(&adapter->pdev->dev,
1009                                         "failed to write through agent\n");
1010                 ret = -EIO;
1011         } else
1012                 ret = 0;
1013
1014 done:
1015         mutex_unlock(&adapter->ahw.mem_lock);
1016
1017         return ret;
1018 }
1019
1020 int
1021 qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
1022                 u64 off, u64 *data)
1023 {
1024         int j, ret;
1025         u32 temp, off8;
1026         u64 val;
1027         void __iomem *mem_crb;
1028
1029         /* Only 64-bit aligned access */
1030         if (off & 7)
1031                 return -EIO;
1032
1033         /* P3 onward, test agent base for MIU and SIU is same */
1034         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1035                                 QLCNIC_ADDR_QDR_NET_MAX)) {
1036                 mem_crb = qlcnic_get_ioaddr(adapter,
1037                                 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1038                 goto correct;
1039         }
1040
1041         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1042                 mem_crb = qlcnic_get_ioaddr(adapter,
1043                                 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1044                 goto correct;
1045         }
1046
1047         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) {
1048                 return qlcnic_pci_mem_access_direct(adapter,
1049                                 off, data, 0);
1050         }
1051
1052         return -EIO;
1053
1054 correct:
1055         off8 = off & ~0xf;
1056
1057         mutex_lock(&adapter->ahw.mem_lock);
1058
1059         writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1060         writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1061         writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1062         writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1063
1064         for (j = 0; j < MAX_CTL_CHECK; j++) {
1065                 temp = readl(mem_crb + TEST_AGT_CTRL);
1066                 if ((temp & TA_CTL_BUSY) == 0)
1067                         break;
1068         }
1069
1070         if (j >= MAX_CTL_CHECK) {
1071                 if (printk_ratelimit())
1072                         dev_err(&adapter->pdev->dev,
1073                                         "failed to read through agent\n");
1074                 ret = -EIO;
1075         } else {
1076                 off8 = MIU_TEST_AGT_RDDATA_LO;
1077                 if (off & 0xf)
1078                         off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
1079
1080                 temp = readl(mem_crb + off8 + 4);
1081                 val = (u64)temp << 32;
1082                 val |= readl(mem_crb + off8);
1083                 *data = val;
1084                 ret = 0;
1085         }
1086
1087         mutex_unlock(&adapter->ahw.mem_lock);
1088
1089         return ret;
1090 }
1091
1092 int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
1093 {
1094         int offset, board_type, magic;
1095         struct pci_dev *pdev = adapter->pdev;
1096
1097         offset = QLCNIC_FW_MAGIC_OFFSET;
1098         if (qlcnic_rom_fast_read(adapter, offset, &magic))
1099                 return -EIO;
1100
1101         if (magic != QLCNIC_BDINFO_MAGIC) {
1102                 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1103                         magic);
1104                 return -EIO;
1105         }
1106
1107         offset = QLCNIC_BRDTYPE_OFFSET;
1108         if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1109                 return -EIO;
1110
1111         adapter->ahw.board_type = board_type;
1112
1113         if (board_type == QLCNIC_BRDTYPE_P3_4_GB_MM) {
1114                 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1115                 if ((gpio & 0x8000) == 0)
1116                         board_type = QLCNIC_BRDTYPE_P3_10G_TP;
1117         }
1118
1119         switch (board_type) {
1120         case QLCNIC_BRDTYPE_P3_HMEZ:
1121         case QLCNIC_BRDTYPE_P3_XG_LOM:
1122         case QLCNIC_BRDTYPE_P3_10G_CX4:
1123         case QLCNIC_BRDTYPE_P3_10G_CX4_LP:
1124         case QLCNIC_BRDTYPE_P3_IMEZ:
1125         case QLCNIC_BRDTYPE_P3_10G_SFP_PLUS:
1126         case QLCNIC_BRDTYPE_P3_10G_SFP_CT:
1127         case QLCNIC_BRDTYPE_P3_10G_SFP_QT:
1128         case QLCNIC_BRDTYPE_P3_10G_XFP:
1129         case QLCNIC_BRDTYPE_P3_10000_BASE_T:
1130                 adapter->ahw.port_type = QLCNIC_XGBE;
1131                 break;
1132         case QLCNIC_BRDTYPE_P3_REF_QG:
1133         case QLCNIC_BRDTYPE_P3_4_GB:
1134         case QLCNIC_BRDTYPE_P3_4_GB_MM:
1135                 adapter->ahw.port_type = QLCNIC_GBE;
1136                 break;
1137         case QLCNIC_BRDTYPE_P3_10G_TP:
1138                 adapter->ahw.port_type = (adapter->portnum < 2) ?
1139                         QLCNIC_XGBE : QLCNIC_GBE;
1140                 break;
1141         default:
1142                 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1143                 adapter->ahw.port_type = QLCNIC_XGBE;
1144                 break;
1145         }
1146
1147         return 0;
1148 }
1149
1150 int
1151 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1152 {
1153         u32 wol_cfg;
1154
1155         wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1156         if (wol_cfg & (1UL << adapter->portnum)) {
1157                 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1158                 if (wol_cfg & (1 << adapter->portnum))
1159                         return 1;
1160         }
1161
1162         return 0;
1163 }
1164
1165 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1166 {
1167         struct qlcnic_nic_req   req;
1168         int rv;
1169         u64 word;
1170
1171         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1172         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1173
1174         word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1175         req.req_hdr = cpu_to_le64(word);
1176
1177         req.words[0] = cpu_to_le64((u64)rate << 32);
1178         req.words[1] = cpu_to_le64(state);
1179
1180         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1181         if (rv)
1182                 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1183
1184         return rv;
1185 }
1186
1187 static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u32 flag)
1188 {
1189         struct qlcnic_nic_req   req;
1190         int                     rv;
1191         u64                     word;
1192
1193         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1194         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1195
1196         word = QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
1197                         ((u64)adapter->portnum << 16);
1198         req.req_hdr = cpu_to_le64(word);
1199         req.words[0] = cpu_to_le64(flag);
1200
1201         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1202         if (rv)
1203                 dev_err(&adapter->pdev->dev,
1204                         "%sting loopback mode failed.\n",
1205                                         flag ? "Set" : "Reset");
1206         return rv;
1207 }
1208
1209 int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter)
1210 {
1211         if (qlcnic_set_fw_loopback(adapter, 1))
1212                 return -EIO;
1213
1214         if (qlcnic_nic_set_promisc(adapter,
1215                                 VPORT_MISS_MODE_ACCEPT_ALL)) {
1216                 qlcnic_set_fw_loopback(adapter, 0);
1217                 return -EIO;
1218         }
1219
1220         msleep(1000);
1221         return 0;
1222 }
1223
1224 void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter)
1225 {
1226         int mode = VPORT_MISS_MODE_DROP;
1227         struct net_device *netdev = adapter->netdev;
1228
1229         qlcnic_set_fw_loopback(adapter, 0);
1230
1231         if (netdev->flags & IFF_PROMISC)
1232                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1233         else if (netdev->flags & IFF_ALLMULTI)
1234                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
1235
1236         qlcnic_nic_set_promisc(adapter, mode);
1237 }