qla3xxx: Add ethtool get_pauseparam for improved bonding support.
[linux-2.6.git] / drivers / net / qla3xxx.c
1 /*
2  * QLogic QLA3xxx NIC HBA Driver
3  * Copyright (c)  2003-2006 QLogic Corporation
4  *
5  * See LICENSE.qla3xxx for copyright and licensing details.
6  */
7
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
17 #include <linux/dmapool.h>
18 #include <linux/mempool.h>
19 #include <linux/spinlock.h>
20 #include <linux/kthread.h>
21 #include <linux/interrupt.h>
22 #include <linux/errno.h>
23 #include <linux/ioport.h>
24 #include <linux/ip.h>
25 #include <linux/in.h>
26 #include <linux/if_arp.h>
27 #include <linux/if_ether.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/ethtool.h>
31 #include <linux/skbuff.h>
32 #include <linux/rtnetlink.h>
33 #include <linux/if_vlan.h>
34 #include <linux/init.h>
35 #include <linux/delay.h>
36 #include <linux/mm.h>
37
38 #include "qla3xxx.h"
39
40 #define DRV_NAME        "qla3xxx"
41 #define DRV_STRING      "QLogic ISP3XXX Network Driver"
42 #define DRV_VERSION     "v2.03.00-k3"
43 #define PFX             DRV_NAME " "
44
45 static const char ql3xxx_driver_name[] = DRV_NAME;
46 static const char ql3xxx_driver_version[] = DRV_VERSION;
47
48 MODULE_AUTHOR("QLogic Corporation");
49 MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
50 MODULE_LICENSE("GPL");
51 MODULE_VERSION(DRV_VERSION);
52
53 static const u32 default_msg
54     = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
55     | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
56
57 static int debug = -1;          /* defaults above */
58 module_param(debug, int, 0);
59 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
60
61 static int msi;
62 module_param(msi, int, 0);
63 MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
64
65 static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
66         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
67         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
68         /* required last entry */
69         {0,}
70 };
71
72 MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
73
74 /*
75  * Caller must take hw_lock.
76  */
77 static int ql_sem_spinlock(struct ql3_adapter *qdev,
78                             u32 sem_mask, u32 sem_bits)
79 {
80         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
81         u32 value;
82         unsigned int seconds = 3;
83
84         do {
85                 writel((sem_mask | sem_bits),
86                        &port_regs->CommonRegs.semaphoreReg);
87                 value = readl(&port_regs->CommonRegs.semaphoreReg);
88                 if ((value & (sem_mask >> 16)) == sem_bits)
89                         return 0;
90                 ssleep(1);
91         } while(--seconds);
92         return -1;
93 }
94
95 static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
96 {
97         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
98         writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
99         readl(&port_regs->CommonRegs.semaphoreReg);
100 }
101
102 static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
103 {
104         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
105         u32 value;
106
107         writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
108         value = readl(&port_regs->CommonRegs.semaphoreReg);
109         return ((value & (sem_mask >> 16)) == sem_bits);
110 }
111
112 /*
113  * Caller holds hw_lock.
114  */
115 static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
116 {
117         int i = 0;
118
119         while (1) {
120                 if (!ql_sem_lock(qdev,
121                                  QL_DRVR_SEM_MASK,
122                                  (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
123                                   * 2) << 1)) {
124                         if (i < 10) {
125                                 ssleep(1);
126                                 i++;
127                         } else {
128                                 printk(KERN_ERR PFX "%s: Timed out waiting for "
129                                        "driver lock...\n",
130                                        qdev->ndev->name);
131                                 return 0;
132                         }
133                 } else {
134                         printk(KERN_DEBUG PFX
135                                "%s: driver lock acquired.\n",
136                                qdev->ndev->name);
137                         return 1;
138                 }
139         }
140 }
141
142 static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
143 {
144         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
145
146         writel(((ISP_CONTROL_NP_MASK << 16) | page),
147                         &port_regs->CommonRegs.ispControlStatus);
148         readl(&port_regs->CommonRegs.ispControlStatus);
149         qdev->current_page = page;
150 }
151
152 static u32 ql_read_common_reg_l(struct ql3_adapter *qdev,
153                               u32 __iomem * reg)
154 {
155         u32 value;
156         unsigned long hw_flags;
157
158         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
159         value = readl(reg);
160         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
161
162         return value;
163 }
164
165 static u32 ql_read_common_reg(struct ql3_adapter *qdev,
166                               u32 __iomem * reg)
167 {
168         return readl(reg);
169 }
170
171 static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
172 {
173         u32 value;
174         unsigned long hw_flags;
175
176         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
177
178         if (qdev->current_page != 0)
179                 ql_set_register_page(qdev,0);
180         value = readl(reg);
181
182         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
183         return value;
184 }
185
186 static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
187 {
188         if (qdev->current_page != 0)
189                 ql_set_register_page(qdev,0);
190         return readl(reg);
191 }
192
193 static void ql_write_common_reg_l(struct ql3_adapter *qdev,
194                                 u32 __iomem *reg, u32 value)
195 {
196         unsigned long hw_flags;
197
198         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
199         writel(value, reg);
200         readl(reg);
201         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
202         return;
203 }
204
205 static void ql_write_common_reg(struct ql3_adapter *qdev,
206                                 u32 __iomem *reg, u32 value)
207 {
208         writel(value, reg);
209         readl(reg);
210         return;
211 }
212
213 static void ql_write_nvram_reg(struct ql3_adapter *qdev,
214                                 u32 __iomem *reg, u32 value)
215 {
216         writel(value, reg);
217         readl(reg);
218         udelay(1);
219         return;
220 }
221
222 static void ql_write_page0_reg(struct ql3_adapter *qdev,
223                                u32 __iomem *reg, u32 value)
224 {
225         if (qdev->current_page != 0)
226                 ql_set_register_page(qdev,0);
227         writel(value, reg);
228         readl(reg);
229         return;
230 }
231
232 /*
233  * Caller holds hw_lock. Only called during init.
234  */
235 static void ql_write_page1_reg(struct ql3_adapter *qdev,
236                                u32 __iomem *reg, u32 value)
237 {
238         if (qdev->current_page != 1)
239                 ql_set_register_page(qdev,1);
240         writel(value, reg);
241         readl(reg);
242         return;
243 }
244
245 /*
246  * Caller holds hw_lock. Only called during init.
247  */
248 static void ql_write_page2_reg(struct ql3_adapter *qdev,
249                                u32 __iomem *reg, u32 value)
250 {
251         if (qdev->current_page != 2)
252                 ql_set_register_page(qdev,2);
253         writel(value, reg);
254         readl(reg);
255         return;
256 }
257
258 static void ql_disable_interrupts(struct ql3_adapter *qdev)
259 {
260         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
261
262         ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
263                             (ISP_IMR_ENABLE_INT << 16));
264
265 }
266
267 static void ql_enable_interrupts(struct ql3_adapter *qdev)
268 {
269         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
270
271         ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
272                             ((0xff << 16) | ISP_IMR_ENABLE_INT));
273
274 }
275
276 static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
277                                             struct ql_rcv_buf_cb *lrg_buf_cb)
278 {
279         dma_addr_t map;
280         int err;
281         lrg_buf_cb->next = NULL;
282
283         if (qdev->lrg_buf_free_tail == NULL) {  /* The list is empty  */
284                 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
285         } else {
286                 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
287                 qdev->lrg_buf_free_tail = lrg_buf_cb;
288         }
289
290         if (!lrg_buf_cb->skb) {
291                 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
292                                                    qdev->lrg_buffer_len);
293                 if (unlikely(!lrg_buf_cb->skb)) {
294                         printk(KERN_ERR PFX "%s: failed netdev_alloc_skb().\n",
295                                qdev->ndev->name);
296                         qdev->lrg_buf_skb_check++;
297                 } else {
298                         /*
299                          * We save some space to copy the ethhdr from first
300                          * buffer
301                          */
302                         skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
303                         map = pci_map_single(qdev->pdev,
304                                              lrg_buf_cb->skb->data,
305                                              qdev->lrg_buffer_len -
306                                              QL_HEADER_SPACE,
307                                              PCI_DMA_FROMDEVICE);
308                         err = pci_dma_mapping_error(map);
309                         if(err) {
310                                 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n", 
311                                        qdev->ndev->name, err);
312                                 dev_kfree_skb(lrg_buf_cb->skb);
313                                 lrg_buf_cb->skb = NULL;
314
315                                 qdev->lrg_buf_skb_check++;
316                                 return;
317                         }
318
319                         lrg_buf_cb->buf_phy_addr_low =
320                             cpu_to_le32(LS_64BITS(map));
321                         lrg_buf_cb->buf_phy_addr_high =
322                             cpu_to_le32(MS_64BITS(map));
323                         pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
324                         pci_unmap_len_set(lrg_buf_cb, maplen,
325                                           qdev->lrg_buffer_len -
326                                           QL_HEADER_SPACE);
327                 }
328         }
329
330         qdev->lrg_buf_free_count++;
331 }
332
333 static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
334                                                            *qdev)
335 {
336         struct ql_rcv_buf_cb *lrg_buf_cb;
337
338         if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) {
339                 if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL)
340                         qdev->lrg_buf_free_tail = NULL;
341                 qdev->lrg_buf_free_count--;
342         }
343
344         return lrg_buf_cb;
345 }
346
347 static u32 addrBits = EEPROM_NO_ADDR_BITS;
348 static u32 dataBits = EEPROM_NO_DATA_BITS;
349
350 static void fm93c56a_deselect(struct ql3_adapter *qdev);
351 static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
352                             unsigned short *value);
353
354 /*
355  * Caller holds hw_lock.
356  */
357 static void fm93c56a_select(struct ql3_adapter *qdev)
358 {
359         struct ql3xxx_port_registers __iomem *port_regs =
360                         qdev->mem_map_registers;
361
362         qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
363         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
364                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
365         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
366                             ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
367 }
368
369 /*
370  * Caller holds hw_lock.
371  */
372 static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
373 {
374         int i;
375         u32 mask;
376         u32 dataBit;
377         u32 previousBit;
378         struct ql3xxx_port_registers __iomem *port_regs =
379                         qdev->mem_map_registers;
380
381         /* Clock in a zero, then do the start bit */
382         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
383                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
384                             AUBURN_EEPROM_DO_1);
385         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
386                             ISP_NVRAM_MASK | qdev->
387                             eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
388                             AUBURN_EEPROM_CLK_RISE);
389         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
390                             ISP_NVRAM_MASK | qdev->
391                             eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
392                             AUBURN_EEPROM_CLK_FALL);
393
394         mask = 1 << (FM93C56A_CMD_BITS - 1);
395         /* Force the previous data bit to be different */
396         previousBit = 0xffff;
397         for (i = 0; i < FM93C56A_CMD_BITS; i++) {
398                 dataBit =
399                     (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0;
400                 if (previousBit != dataBit) {
401                         /*
402                          * If the bit changed, then change the DO state to
403                          * match
404                          */
405                         ql_write_nvram_reg(qdev,
406                                             &port_regs->CommonRegs.
407                                             serialPortInterfaceReg,
408                                             ISP_NVRAM_MASK | qdev->
409                                             eeprom_cmd_data | dataBit);
410                         previousBit = dataBit;
411                 }
412                 ql_write_nvram_reg(qdev,
413                                     &port_regs->CommonRegs.
414                                     serialPortInterfaceReg,
415                                     ISP_NVRAM_MASK | qdev->
416                                     eeprom_cmd_data | dataBit |
417                                     AUBURN_EEPROM_CLK_RISE);
418                 ql_write_nvram_reg(qdev,
419                                     &port_regs->CommonRegs.
420                                     serialPortInterfaceReg,
421                                     ISP_NVRAM_MASK | qdev->
422                                     eeprom_cmd_data | dataBit |
423                                     AUBURN_EEPROM_CLK_FALL);
424                 cmd = cmd << 1;
425         }
426
427         mask = 1 << (addrBits - 1);
428         /* Force the previous data bit to be different */
429         previousBit = 0xffff;
430         for (i = 0; i < addrBits; i++) {
431                 dataBit =
432                     (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 :
433                     AUBURN_EEPROM_DO_0;
434                 if (previousBit != dataBit) {
435                         /*
436                          * If the bit changed, then change the DO state to
437                          * match
438                          */
439                         ql_write_nvram_reg(qdev,
440                                             &port_regs->CommonRegs.
441                                             serialPortInterfaceReg,
442                                             ISP_NVRAM_MASK | qdev->
443                                             eeprom_cmd_data | dataBit);
444                         previousBit = dataBit;
445                 }
446                 ql_write_nvram_reg(qdev,
447                                     &port_regs->CommonRegs.
448                                     serialPortInterfaceReg,
449                                     ISP_NVRAM_MASK | qdev->
450                                     eeprom_cmd_data | dataBit |
451                                     AUBURN_EEPROM_CLK_RISE);
452                 ql_write_nvram_reg(qdev,
453                                     &port_regs->CommonRegs.
454                                     serialPortInterfaceReg,
455                                     ISP_NVRAM_MASK | qdev->
456                                     eeprom_cmd_data | dataBit |
457                                     AUBURN_EEPROM_CLK_FALL);
458                 eepromAddr = eepromAddr << 1;
459         }
460 }
461
462 /*
463  * Caller holds hw_lock.
464  */
465 static void fm93c56a_deselect(struct ql3_adapter *qdev)
466 {
467         struct ql3xxx_port_registers __iomem *port_regs =
468                         qdev->mem_map_registers;
469         qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
470         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
471                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
472 }
473
474 /*
475  * Caller holds hw_lock.
476  */
477 static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
478 {
479         int i;
480         u32 data = 0;
481         u32 dataBit;
482         struct ql3xxx_port_registers __iomem *port_regs =
483                         qdev->mem_map_registers;
484
485         /* Read the data bits */
486         /* The first bit is a dummy.  Clock right over it. */
487         for (i = 0; i < dataBits; i++) {
488                 ql_write_nvram_reg(qdev,
489                                     &port_regs->CommonRegs.
490                                     serialPortInterfaceReg,
491                                     ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
492                                     AUBURN_EEPROM_CLK_RISE);
493                 ql_write_nvram_reg(qdev,
494                                     &port_regs->CommonRegs.
495                                     serialPortInterfaceReg,
496                                     ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
497                                     AUBURN_EEPROM_CLK_FALL);
498                 dataBit =
499                     (ql_read_common_reg
500                      (qdev,
501                       &port_regs->CommonRegs.
502                       serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0;
503                 data = (data << 1) | dataBit;
504         }
505         *value = (u16) data;
506 }
507
508 /*
509  * Caller holds hw_lock.
510  */
511 static void eeprom_readword(struct ql3_adapter *qdev,
512                             u32 eepromAddr, unsigned short *value)
513 {
514         fm93c56a_select(qdev);
515         fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
516         fm93c56a_datain(qdev, value);
517         fm93c56a_deselect(qdev);
518 }
519
520 static void ql_swap_mac_addr(u8 * macAddress)
521 {
522 #ifdef __BIG_ENDIAN
523         u8 temp;
524         temp = macAddress[0];
525         macAddress[0] = macAddress[1];
526         macAddress[1] = temp;
527         temp = macAddress[2];
528         macAddress[2] = macAddress[3];
529         macAddress[3] = temp;
530         temp = macAddress[4];
531         macAddress[4] = macAddress[5];
532         macAddress[5] = temp;
533 #endif
534 }
535
536 static int ql_get_nvram_params(struct ql3_adapter *qdev)
537 {
538         u16 *pEEPROMData;
539         u16 checksum = 0;
540         u32 index;
541         unsigned long hw_flags;
542
543         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
544
545         pEEPROMData = (u16 *) & qdev->nvram_data;
546         qdev->eeprom_cmd_data = 0;
547         if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
548                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
549                          2) << 10)) {
550                 printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n",
551                         __func__);
552                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
553                 return -1;
554         }
555
556         for (index = 0; index < EEPROM_SIZE; index++) {
557                 eeprom_readword(qdev, index, pEEPROMData);
558                 checksum += *pEEPROMData;
559                 pEEPROMData++;
560         }
561         ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
562
563         if (checksum != 0) {
564                 printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n",
565                        qdev->ndev->name, checksum);
566                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
567                 return -1;
568         }
569
570         /*
571          * We have a problem with endianness for the MAC addresses
572          * and the two 8-bit values version, and numPorts.  We
573          * have to swap them on big endian systems.
574          */
575         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn0.macAddress);
576         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn1.macAddress);
577         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn2.macAddress);
578         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn3.macAddress);
579         pEEPROMData = (u16 *) & qdev->nvram_data.version;
580         *pEEPROMData = le16_to_cpu(*pEEPROMData);
581
582         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
583         return checksum;
584 }
585
586 static const u32 PHYAddr[2] = {
587         PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
588 };
589
590 static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
591 {
592         struct ql3xxx_port_registers __iomem *port_regs =
593                         qdev->mem_map_registers;
594         u32 temp;
595         int count = 1000;
596
597         while (count) {
598                 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
599                 if (!(temp & MAC_MII_STATUS_BSY))
600                         return 0;
601                 udelay(10);
602                 count--;
603         }
604         return -1;
605 }
606
607 static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
608 {
609         struct ql3xxx_port_registers __iomem *port_regs =
610                         qdev->mem_map_registers;
611         u32 scanControl;
612
613         if (qdev->numPorts > 1) {
614                 /* Auto scan will cycle through multiple ports */
615                 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
616         } else {
617                 scanControl = MAC_MII_CONTROL_SC;
618         }
619
620         /*
621          * Scan register 1 of PHY/PETBI,
622          * Set up to scan both devices
623          * The autoscan starts from the first register, completes
624          * the last one before rolling over to the first
625          */
626         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
627                            PHYAddr[0] | MII_SCAN_REGISTER);
628
629         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
630                            (scanControl) |
631                            ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
632 }
633
634 static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
635 {
636         u8 ret;
637         struct ql3xxx_port_registers __iomem *port_regs =
638                                         qdev->mem_map_registers;
639
640         /* See if scan mode is enabled before we turn it off */
641         if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
642             (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
643                 /* Scan is enabled */
644                 ret = 1;
645         } else {
646                 /* Scan is disabled */
647                 ret = 0;
648         }
649
650         /*
651          * When disabling scan mode you must first change the MII register
652          * address
653          */
654         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
655                            PHYAddr[0] | MII_SCAN_REGISTER);
656
657         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
658                            ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
659                              MAC_MII_CONTROL_RC) << 16));
660
661         return ret;
662 }
663
664 static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
665                                u16 regAddr, u16 value, u32 mac_index)
666 {
667         struct ql3xxx_port_registers __iomem *port_regs =
668                         qdev->mem_map_registers;
669         u8 scanWasEnabled;
670
671         scanWasEnabled = ql_mii_disable_scan_mode(qdev);
672
673         if (ql_wait_for_mii_ready(qdev)) {
674                 if (netif_msg_link(qdev))
675                         printk(KERN_WARNING PFX
676                                "%s Timed out waiting for management port to "
677                                "get free before issuing command.\n",
678                                qdev->ndev->name);
679                 return -1;
680         }
681
682         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
683                            PHYAddr[mac_index] | regAddr);
684
685         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
686
687         /* Wait for write to complete 9/10/04 SJP */
688         if (ql_wait_for_mii_ready(qdev)) {
689                 if (netif_msg_link(qdev))
690                         printk(KERN_WARNING PFX
691                                "%s: Timed out waiting for management port to"
692                                "get free before issuing command.\n",
693                                qdev->ndev->name);
694                 return -1;
695         }
696
697         if (scanWasEnabled)
698                 ql_mii_enable_scan_mode(qdev);
699
700         return 0;
701 }
702
703 static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
704                               u16 * value, u32 mac_index)
705 {
706         struct ql3xxx_port_registers __iomem *port_regs =
707                         qdev->mem_map_registers;
708         u8 scanWasEnabled;
709         u32 temp;
710
711         scanWasEnabled = ql_mii_disable_scan_mode(qdev);
712
713         if (ql_wait_for_mii_ready(qdev)) {
714                 if (netif_msg_link(qdev))
715                         printk(KERN_WARNING PFX
716                                "%s: Timed out waiting for management port to "
717                                "get free before issuing command.\n",
718                                qdev->ndev->name);
719                 return -1;
720         }
721
722         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
723                            PHYAddr[mac_index] | regAddr);
724
725         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
726                            (MAC_MII_CONTROL_RC << 16));
727
728         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
729                            (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
730
731         /* Wait for the read to complete */
732         if (ql_wait_for_mii_ready(qdev)) {
733                 if (netif_msg_link(qdev))
734                         printk(KERN_WARNING PFX
735                                "%s: Timed out waiting for management port to "
736                                "get free after issuing command.\n",
737                                qdev->ndev->name);
738                 return -1;
739         }
740
741         temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
742         *value = (u16) temp;
743
744         if (scanWasEnabled)
745                 ql_mii_enable_scan_mode(qdev);
746
747         return 0;
748 }
749
750 static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
751 {
752         struct ql3xxx_port_registers __iomem *port_regs =
753                         qdev->mem_map_registers;
754
755         ql_mii_disable_scan_mode(qdev);
756
757         if (ql_wait_for_mii_ready(qdev)) {
758                 if (netif_msg_link(qdev))
759                         printk(KERN_WARNING PFX
760                                "%s: Timed out waiting for management port to "
761                                "get free before issuing command.\n",
762                                qdev->ndev->name);
763                 return -1;
764         }
765
766         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
767                            qdev->PHYAddr | regAddr);
768
769         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
770
771         /* Wait for write to complete. */
772         if (ql_wait_for_mii_ready(qdev)) {
773                 if (netif_msg_link(qdev))
774                         printk(KERN_WARNING PFX
775                                "%s: Timed out waiting for management port to "
776                                "get free before issuing command.\n",
777                                qdev->ndev->name);
778                 return -1;
779         }
780
781         ql_mii_enable_scan_mode(qdev);
782
783         return 0;
784 }
785
786 static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
787 {
788         u32 temp;
789         struct ql3xxx_port_registers __iomem *port_regs =
790                         qdev->mem_map_registers;
791
792         ql_mii_disable_scan_mode(qdev);
793
794         if (ql_wait_for_mii_ready(qdev)) {
795                 if (netif_msg_link(qdev))
796                         printk(KERN_WARNING PFX
797                                "%s: Timed out waiting for management port to "
798                                "get free before issuing command.\n",
799                                qdev->ndev->name);
800                 return -1;
801         }
802
803         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
804                            qdev->PHYAddr | regAddr);
805
806         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
807                            (MAC_MII_CONTROL_RC << 16));
808
809         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
810                            (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
811
812         /* Wait for the read to complete */
813         if (ql_wait_for_mii_ready(qdev)) {
814                 if (netif_msg_link(qdev))
815                         printk(KERN_WARNING PFX
816                                "%s: Timed out waiting for management port to "
817                                "get free before issuing command.\n",
818                                qdev->ndev->name);
819                 return -1;
820         }
821
822         temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
823         *value = (u16) temp;
824
825         ql_mii_enable_scan_mode(qdev);
826
827         return 0;
828 }
829
830 static void ql_petbi_reset(struct ql3_adapter *qdev)
831 {
832         ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
833 }
834
835 static void ql_petbi_start_neg(struct ql3_adapter *qdev)
836 {
837         u16 reg;
838
839         /* Enable Auto-negotiation sense */
840         ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
841         reg |= PETBI_TBI_AUTO_SENSE;
842         ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
843
844         ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
845                          PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
846
847         ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
848                          PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
849                          PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
850
851 }
852
853 static void ql_petbi_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
854 {
855         ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
856                             mac_index);
857 }
858
859 static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
860 {
861         u16 reg;
862
863         /* Enable Auto-negotiation sense */
864         ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg, mac_index);
865         reg |= PETBI_TBI_AUTO_SENSE;
866         ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg, mac_index);
867
868         ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
869                             PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX, mac_index);
870
871         ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
872                             PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
873                             PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
874                             mac_index);
875 }
876
877 static void ql_petbi_init(struct ql3_adapter *qdev)
878 {
879         ql_petbi_reset(qdev);
880         ql_petbi_start_neg(qdev);
881 }
882
883 static void ql_petbi_init_ex(struct ql3_adapter *qdev, u32 mac_index)
884 {
885         ql_petbi_reset_ex(qdev, mac_index);
886         ql_petbi_start_neg_ex(qdev, mac_index);
887 }
888
889 static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
890 {
891         u16 reg;
892
893         if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
894                 return 0;
895
896         return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
897 }
898
899 static int ql_phy_get_speed(struct ql3_adapter *qdev)
900 {
901         u16 reg;
902
903         if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
904                 return 0;
905
906         reg = (((reg & 0x18) >> 3) & 3);
907
908         if (reg == 2)
909                 return SPEED_1000;
910         else if (reg == 1)
911                 return SPEED_100;
912         else if (reg == 0)
913                 return SPEED_10;
914         else
915                 return -1;
916 }
917
918 static int ql_is_full_dup(struct ql3_adapter *qdev)
919 {
920         u16 reg;
921
922         if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
923                 return 0;
924
925         return (reg & PHY_AUX_DUPLEX_STAT) != 0;
926 }
927
928 static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
929 {
930         u16 reg;
931
932         if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
933                 return 0;
934
935         return (reg & PHY_NEG_PAUSE) != 0;
936 }
937
938 /*
939  * Caller holds hw_lock.
940  */
941 static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
942 {
943         struct ql3xxx_port_registers __iomem *port_regs =
944                         qdev->mem_map_registers;
945         u32 value;
946
947         if (enable)
948                 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
949         else
950                 value = (MAC_CONFIG_REG_PE << 16);
951
952         if (qdev->mac_index)
953                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
954         else
955                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
956 }
957
958 /*
959  * Caller holds hw_lock.
960  */
961 static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
962 {
963         struct ql3xxx_port_registers __iomem *port_regs =
964                         qdev->mem_map_registers;
965         u32 value;
966
967         if (enable)
968                 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
969         else
970                 value = (MAC_CONFIG_REG_SR << 16);
971
972         if (qdev->mac_index)
973                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
974         else
975                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
976 }
977
978 /*
979  * Caller holds hw_lock.
980  */
981 static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
982 {
983         struct ql3xxx_port_registers __iomem *port_regs =
984                         qdev->mem_map_registers;
985         u32 value;
986
987         if (enable)
988                 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
989         else
990                 value = (MAC_CONFIG_REG_GM << 16);
991
992         if (qdev->mac_index)
993                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
994         else
995                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
996 }
997
998 /*
999  * Caller holds hw_lock.
1000  */
1001 static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1002 {
1003         struct ql3xxx_port_registers __iomem *port_regs =
1004                         qdev->mem_map_registers;
1005         u32 value;
1006
1007         if (enable)
1008                 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1009         else
1010                 value = (MAC_CONFIG_REG_FD << 16);
1011
1012         if (qdev->mac_index)
1013                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1014         else
1015                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1016 }
1017
1018 /*
1019  * Caller holds hw_lock.
1020  */
1021 static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1022 {
1023         struct ql3xxx_port_registers __iomem *port_regs =
1024                         qdev->mem_map_registers;
1025         u32 value;
1026
1027         if (enable)
1028                 value =
1029                     ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1030                      ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1031         else
1032                 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1033
1034         if (qdev->mac_index)
1035                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1036         else
1037                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1038 }
1039
1040 /*
1041  * Caller holds hw_lock.
1042  */
1043 static int ql_is_fiber(struct ql3_adapter *qdev)
1044 {
1045         struct ql3xxx_port_registers __iomem *port_regs =
1046                         qdev->mem_map_registers;
1047         u32 bitToCheck = 0;
1048         u32 temp;
1049
1050         switch (qdev->mac_index) {
1051         case 0:
1052                 bitToCheck = PORT_STATUS_SM0;
1053                 break;
1054         case 1:
1055                 bitToCheck = PORT_STATUS_SM1;
1056                 break;
1057         }
1058
1059         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1060         return (temp & bitToCheck) != 0;
1061 }
1062
1063 static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1064 {
1065         u16 reg;
1066         ql_mii_read_reg(qdev, 0x00, &reg);
1067         return (reg & 0x1000) != 0;
1068 }
1069
1070 /*
1071  * Caller holds hw_lock.
1072  */
1073 static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1074 {
1075         struct ql3xxx_port_registers __iomem *port_regs =
1076                         qdev->mem_map_registers;
1077         u32 bitToCheck = 0;
1078         u32 temp;
1079
1080         switch (qdev->mac_index) {
1081         case 0:
1082                 bitToCheck = PORT_STATUS_AC0;
1083                 break;
1084         case 1:
1085                 bitToCheck = PORT_STATUS_AC1;
1086                 break;
1087         }
1088
1089         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1090         if (temp & bitToCheck) {
1091                 if (netif_msg_link(qdev))
1092                         printk(KERN_INFO PFX
1093                                "%s: Auto-Negotiate complete.\n",
1094                                qdev->ndev->name);
1095                 return 1;
1096         } else {
1097                 if (netif_msg_link(qdev))
1098                         printk(KERN_WARNING PFX
1099                                "%s: Auto-Negotiate incomplete.\n",
1100                                qdev->ndev->name);
1101                 return 0;
1102         }
1103 }
1104
1105 /*
1106  *  ql_is_neg_pause() returns 1 if pause was negotiated to be on
1107  */
1108 static int ql_is_neg_pause(struct ql3_adapter *qdev)
1109 {
1110         if (ql_is_fiber(qdev))
1111                 return ql_is_petbi_neg_pause(qdev);
1112         else
1113                 return ql_is_phy_neg_pause(qdev);
1114 }
1115
1116 static int ql_auto_neg_error(struct ql3_adapter *qdev)
1117 {
1118         struct ql3xxx_port_registers __iomem *port_regs =
1119                         qdev->mem_map_registers;
1120         u32 bitToCheck = 0;
1121         u32 temp;
1122
1123         switch (qdev->mac_index) {
1124         case 0:
1125                 bitToCheck = PORT_STATUS_AE0;
1126                 break;
1127         case 1:
1128                 bitToCheck = PORT_STATUS_AE1;
1129                 break;
1130         }
1131         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1132         return (temp & bitToCheck) != 0;
1133 }
1134
1135 static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1136 {
1137         if (ql_is_fiber(qdev))
1138                 return SPEED_1000;
1139         else
1140                 return ql_phy_get_speed(qdev);
1141 }
1142
1143 static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1144 {
1145         if (ql_is_fiber(qdev))
1146                 return 1;
1147         else
1148                 return ql_is_full_dup(qdev);
1149 }
1150
1151 /*
1152  * Caller holds hw_lock.
1153  */
1154 static int ql_link_down_detect(struct ql3_adapter *qdev)
1155 {
1156         struct ql3xxx_port_registers __iomem *port_regs =
1157                         qdev->mem_map_registers;
1158         u32 bitToCheck = 0;
1159         u32 temp;
1160
1161         switch (qdev->mac_index) {
1162         case 0:
1163                 bitToCheck = ISP_CONTROL_LINK_DN_0;
1164                 break;
1165         case 1:
1166                 bitToCheck = ISP_CONTROL_LINK_DN_1;
1167                 break;
1168         }
1169
1170         temp =
1171             ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1172         return (temp & bitToCheck) != 0;
1173 }
1174
1175 /*
1176  * Caller holds hw_lock.
1177  */
1178 static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1179 {
1180         struct ql3xxx_port_registers __iomem *port_regs =
1181                         qdev->mem_map_registers;
1182
1183         switch (qdev->mac_index) {
1184         case 0:
1185                 ql_write_common_reg(qdev,
1186                                     &port_regs->CommonRegs.ispControlStatus,
1187                                     (ISP_CONTROL_LINK_DN_0) |
1188                                     (ISP_CONTROL_LINK_DN_0 << 16));
1189                 break;
1190
1191         case 1:
1192                 ql_write_common_reg(qdev,
1193                                     &port_regs->CommonRegs.ispControlStatus,
1194                                     (ISP_CONTROL_LINK_DN_1) |
1195                                     (ISP_CONTROL_LINK_DN_1 << 16));
1196                 break;
1197
1198         default:
1199                 return 1;
1200         }
1201
1202         return 0;
1203 }
1204
1205 /*
1206  * Caller holds hw_lock.
1207  */
1208 static int ql_this_adapter_controls_port(struct ql3_adapter *qdev,
1209                                          u32 mac_index)
1210 {
1211         struct ql3xxx_port_registers __iomem *port_regs =
1212                         qdev->mem_map_registers;
1213         u32 bitToCheck = 0;
1214         u32 temp;
1215
1216         switch (mac_index) {
1217         case 0:
1218                 bitToCheck = PORT_STATUS_F1_ENABLED;
1219                 break;
1220         case 1:
1221                 bitToCheck = PORT_STATUS_F3_ENABLED;
1222                 break;
1223         default:
1224                 break;
1225         }
1226
1227         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1228         if (temp & bitToCheck) {
1229                 if (netif_msg_link(qdev))
1230                         printk(KERN_DEBUG PFX
1231                                "%s: is not link master.\n", qdev->ndev->name);
1232                 return 0;
1233         } else {
1234                 if (netif_msg_link(qdev))
1235                         printk(KERN_DEBUG PFX
1236                                "%s: is link master.\n", qdev->ndev->name);
1237                 return 1;
1238         }
1239 }
1240
1241 static void ql_phy_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
1242 {
1243         ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET, mac_index);
1244 }
1245
1246 static void ql_phy_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
1247 {
1248         u16 reg;
1249
1250         ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER,
1251                             PHY_NEG_PAUSE | PHY_NEG_ADV_SPEED | 1, mac_index);
1252
1253         ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, mac_index);
1254         ql_mii_write_reg_ex(qdev, CONTROL_REG, reg | PHY_CTRL_RESTART_NEG,
1255                             mac_index);
1256 }
1257
1258 static void ql_phy_init_ex(struct ql3_adapter *qdev, u32 mac_index)
1259 {
1260         ql_phy_reset_ex(qdev, mac_index);
1261         ql_phy_start_neg_ex(qdev, mac_index);
1262 }
1263
1264 /*
1265  * Caller holds hw_lock.
1266  */
1267 static u32 ql_get_link_state(struct ql3_adapter *qdev)
1268 {
1269         struct ql3xxx_port_registers __iomem *port_regs =
1270                         qdev->mem_map_registers;
1271         u32 bitToCheck = 0;
1272         u32 temp, linkState;
1273
1274         switch (qdev->mac_index) {
1275         case 0:
1276                 bitToCheck = PORT_STATUS_UP0;
1277                 break;
1278         case 1:
1279                 bitToCheck = PORT_STATUS_UP1;
1280                 break;
1281         }
1282         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1283         if (temp & bitToCheck) {
1284                 linkState = LS_UP;
1285         } else {
1286                 linkState = LS_DOWN;
1287                 if (netif_msg_link(qdev))
1288                         printk(KERN_WARNING PFX
1289                                "%s: Link is down.\n", qdev->ndev->name);
1290         }
1291         return linkState;
1292 }
1293
1294 static int ql_port_start(struct ql3_adapter *qdev)
1295 {
1296         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1297                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1298                          2) << 7))
1299                 return -1;
1300
1301         if (ql_is_fiber(qdev)) {
1302                 ql_petbi_init(qdev);
1303         } else {
1304                 /* Copper port */
1305                 ql_phy_init_ex(qdev, qdev->mac_index);
1306         }
1307
1308         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1309         return 0;
1310 }
1311
1312 static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1313 {
1314
1315         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1316                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1317                          2) << 7))
1318                 return -1;
1319
1320         if (!ql_auto_neg_error(qdev)) {
1321                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1322                         /* configure the MAC */
1323                         if (netif_msg_link(qdev))
1324                                 printk(KERN_DEBUG PFX
1325                                        "%s: Configuring link.\n",
1326                                        qdev->ndev->
1327                                        name);
1328                         ql_mac_cfg_soft_reset(qdev, 1);
1329                         ql_mac_cfg_gig(qdev,
1330                                        (ql_get_link_speed
1331                                         (qdev) ==
1332                                         SPEED_1000));
1333                         ql_mac_cfg_full_dup(qdev,
1334                                             ql_is_link_full_dup
1335                                             (qdev));
1336                         ql_mac_cfg_pause(qdev,
1337                                          ql_is_neg_pause
1338                                          (qdev));
1339                         ql_mac_cfg_soft_reset(qdev, 0);
1340
1341                         /* enable the MAC */
1342                         if (netif_msg_link(qdev))
1343                                 printk(KERN_DEBUG PFX
1344                                        "%s: Enabling mac.\n",
1345                                        qdev->ndev->
1346                                                name);
1347                         ql_mac_enable(qdev, 1);
1348                 }
1349
1350                 if (netif_msg_link(qdev))
1351                         printk(KERN_DEBUG PFX
1352                                "%s: Change port_link_state LS_DOWN to LS_UP.\n",
1353                                qdev->ndev->name);
1354                 qdev->port_link_state = LS_UP;
1355                 netif_start_queue(qdev->ndev);
1356                 netif_carrier_on(qdev->ndev);
1357                 if (netif_msg_link(qdev))
1358                         printk(KERN_INFO PFX
1359                                "%s: Link is up at %d Mbps, %s duplex.\n",
1360                                qdev->ndev->name,
1361                                ql_get_link_speed(qdev),
1362                                ql_is_link_full_dup(qdev)
1363                                ? "full" : "half");
1364
1365         } else {        /* Remote error detected */
1366
1367                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1368                         if (netif_msg_link(qdev))
1369                                 printk(KERN_DEBUG PFX
1370                                        "%s: Remote error detected. "
1371                                        "Calling ql_port_start().\n",
1372                                        qdev->ndev->
1373                                        name);
1374                         /*
1375                          * ql_port_start() is shared code and needs
1376                          * to lock the PHY on it's own.
1377                          */
1378                         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1379                         if(ql_port_start(qdev)) {/* Restart port */
1380                                 return -1;
1381                         } else
1382                                 return 0;
1383                 }
1384         }
1385         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1386         return 0;
1387 }
1388
1389 static void ql_link_state_machine(struct ql3_adapter *qdev)
1390 {
1391         u32 curr_link_state;
1392         unsigned long hw_flags;
1393
1394         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1395
1396         curr_link_state = ql_get_link_state(qdev);
1397
1398         if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
1399                 if (netif_msg_link(qdev))
1400                         printk(KERN_INFO PFX
1401                                "%s: Reset in progress, skip processing link "
1402                                "state.\n", qdev->ndev->name);
1403
1404                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);               
1405                 return;
1406         }
1407
1408         switch (qdev->port_link_state) {
1409         default:
1410                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1411                         ql_port_start(qdev);
1412                 }
1413                 qdev->port_link_state = LS_DOWN;
1414                 /* Fall Through */
1415
1416         case LS_DOWN:
1417                 if (netif_msg_link(qdev))
1418                         printk(KERN_DEBUG PFX
1419                                "%s: port_link_state = LS_DOWN.\n",
1420                                qdev->ndev->name);
1421                 if (curr_link_state == LS_UP) {
1422                         if (netif_msg_link(qdev))
1423                                 printk(KERN_DEBUG PFX
1424                                        "%s: curr_link_state = LS_UP.\n",
1425                                        qdev->ndev->name);
1426                         if (ql_is_auto_neg_complete(qdev))
1427                                 ql_finish_auto_neg(qdev);
1428
1429                         if (qdev->port_link_state == LS_UP)
1430                                 ql_link_down_detect_clear(qdev);
1431
1432                 }
1433                 break;
1434
1435         case LS_UP:
1436                 /*
1437                  * See if the link is currently down or went down and came
1438                  * back up
1439                  */
1440                 if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) {
1441                         if (netif_msg_link(qdev))
1442                                 printk(KERN_INFO PFX "%s: Link is down.\n",
1443                                        qdev->ndev->name);
1444                         qdev->port_link_state = LS_DOWN;
1445                 }
1446                 break;
1447         }
1448         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1449 }
1450
1451 /*
1452  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1453  */
1454 static void ql_get_phy_owner(struct ql3_adapter *qdev)
1455 {
1456         if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1457                 set_bit(QL_LINK_MASTER,&qdev->flags);
1458         else
1459                 clear_bit(QL_LINK_MASTER,&qdev->flags);
1460 }
1461
1462 /*
1463  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1464  */
1465 static void ql_init_scan_mode(struct ql3_adapter *qdev)
1466 {
1467         ql_mii_enable_scan_mode(qdev);
1468
1469         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1470                 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1471                         ql_petbi_init_ex(qdev, qdev->mac_index);
1472         } else {
1473                 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1474                         ql_phy_init_ex(qdev, qdev->mac_index);
1475         }
1476 }
1477
1478 /*
1479  * MII_Setup needs to be called before taking the PHY out of reset so that the
1480  * management interface clock speed can be set properly.  It would be better if
1481  * we had a way to disable MDC until after the PHY is out of reset, but we
1482  * don't have that capability.
1483  */
1484 static int ql_mii_setup(struct ql3_adapter *qdev)
1485 {
1486         u32 reg;
1487         struct ql3xxx_port_registers __iomem *port_regs =
1488                         qdev->mem_map_registers;
1489
1490         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1491                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1492                          2) << 7))
1493                 return -1;
1494
1495         if (qdev->device_id == QL3032_DEVICE_ID)
1496                 ql_write_page0_reg(qdev, 
1497                         &port_regs->macMIIMgmtControlReg, 0x0f00000);
1498
1499         /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1500         reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1501
1502         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1503                            reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1504
1505         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1506         return 0;
1507 }
1508
1509 static u32 ql_supported_modes(struct ql3_adapter *qdev)
1510 {
1511         u32 supported;
1512
1513         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1514                 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
1515                     | SUPPORTED_Autoneg;
1516         } else {
1517                 supported = SUPPORTED_10baseT_Half
1518                     | SUPPORTED_10baseT_Full
1519                     | SUPPORTED_100baseT_Half
1520                     | SUPPORTED_100baseT_Full
1521                     | SUPPORTED_1000baseT_Half
1522                     | SUPPORTED_1000baseT_Full
1523                     | SUPPORTED_Autoneg | SUPPORTED_TP;
1524         }
1525
1526         return supported;
1527 }
1528
1529 static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1530 {
1531         int status;
1532         unsigned long hw_flags;
1533         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1534         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1535                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1536                          2) << 7)) {
1537                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1538                 return 0;
1539         }
1540         status = ql_is_auto_cfg(qdev);
1541         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1542         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1543         return status;
1544 }
1545
1546 static u32 ql_get_speed(struct ql3_adapter *qdev)
1547 {
1548         u32 status;
1549         unsigned long hw_flags;
1550         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1551         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1552                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1553                          2) << 7)) {
1554                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1555                 return 0;
1556         }
1557         status = ql_get_link_speed(qdev);
1558         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1559         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1560         return status;
1561 }
1562
1563 static int ql_get_full_dup(struct ql3_adapter *qdev)
1564 {
1565         int status;
1566         unsigned long hw_flags;
1567         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1568         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1569                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1570                          2) << 7)) {
1571                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1572                 return 0;
1573         }
1574         status = ql_is_link_full_dup(qdev);
1575         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1576         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1577         return status;
1578 }
1579
1580
1581 static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1582 {
1583         struct ql3_adapter *qdev = netdev_priv(ndev);
1584
1585         ecmd->transceiver = XCVR_INTERNAL;
1586         ecmd->supported = ql_supported_modes(qdev);
1587
1588         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1589                 ecmd->port = PORT_FIBRE;
1590         } else {
1591                 ecmd->port = PORT_TP;
1592                 ecmd->phy_address = qdev->PHYAddr;
1593         }
1594         ecmd->advertising = ql_supported_modes(qdev);
1595         ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1596         ecmd->speed = ql_get_speed(qdev);
1597         ecmd->duplex = ql_get_full_dup(qdev);
1598         return 0;
1599 }
1600
1601 static void ql_get_drvinfo(struct net_device *ndev,
1602                            struct ethtool_drvinfo *drvinfo)
1603 {
1604         struct ql3_adapter *qdev = netdev_priv(ndev);
1605         strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
1606         strncpy(drvinfo->version, ql3xxx_driver_version, 32);
1607         strncpy(drvinfo->fw_version, "N/A", 32);
1608         strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
1609         drvinfo->n_stats = 0;
1610         drvinfo->testinfo_len = 0;
1611         drvinfo->regdump_len = 0;
1612         drvinfo->eedump_len = 0;
1613 }
1614
1615 static u32 ql_get_msglevel(struct net_device *ndev)
1616 {
1617         struct ql3_adapter *qdev = netdev_priv(ndev);
1618         return qdev->msg_enable;
1619 }
1620
1621 static void ql_set_msglevel(struct net_device *ndev, u32 value)
1622 {
1623         struct ql3_adapter *qdev = netdev_priv(ndev);
1624         qdev->msg_enable = value;
1625 }
1626
1627 static void ql_get_pauseparam(struct net_device *ndev,
1628                               struct ethtool_pauseparam *pause)
1629 {
1630         struct ql3_adapter *qdev = netdev_priv(ndev);
1631         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1632
1633         u32 reg;
1634         if(qdev->mac_index == 0)
1635                 reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg);
1636         else
1637                 reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg);
1638
1639         pause->autoneg  = ql_get_auto_cfg_status(qdev);
1640         pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2;
1641         pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1;
1642 }
1643
1644 static const struct ethtool_ops ql3xxx_ethtool_ops = {
1645         .get_settings = ql_get_settings,
1646         .get_drvinfo = ql_get_drvinfo,
1647         .get_perm_addr = ethtool_op_get_perm_addr,
1648         .get_link = ethtool_op_get_link,
1649         .get_msglevel = ql_get_msglevel,
1650         .set_msglevel = ql_set_msglevel,
1651         .get_pauseparam = ql_get_pauseparam,
1652 };
1653
1654 static int ql_populate_free_queue(struct ql3_adapter *qdev)
1655 {
1656         struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1657         dma_addr_t map;
1658         int err;
1659
1660         while (lrg_buf_cb) {
1661                 if (!lrg_buf_cb->skb) {
1662                         lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
1663                                                            qdev->lrg_buffer_len);
1664                         if (unlikely(!lrg_buf_cb->skb)) {
1665                                 printk(KERN_DEBUG PFX
1666                                        "%s: Failed netdev_alloc_skb().\n",
1667                                        qdev->ndev->name);
1668                                 break;
1669                         } else {
1670                                 /*
1671                                  * We save some space to copy the ethhdr from
1672                                  * first buffer
1673                                  */
1674                                 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1675                                 map = pci_map_single(qdev->pdev,
1676                                                      lrg_buf_cb->skb->data,
1677                                                      qdev->lrg_buffer_len -
1678                                                      QL_HEADER_SPACE,
1679                                                      PCI_DMA_FROMDEVICE);
1680
1681                                 err = pci_dma_mapping_error(map);
1682                                 if(err) {
1683                                         printk(KERN_ERR "%s: PCI mapping failed with error: %d\n", 
1684                                                qdev->ndev->name, err);
1685                                         dev_kfree_skb(lrg_buf_cb->skb);
1686                                         lrg_buf_cb->skb = NULL;
1687                                         break;
1688                                 }
1689
1690
1691                                 lrg_buf_cb->buf_phy_addr_low =
1692                                     cpu_to_le32(LS_64BITS(map));
1693                                 lrg_buf_cb->buf_phy_addr_high =
1694                                     cpu_to_le32(MS_64BITS(map));
1695                                 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1696                                 pci_unmap_len_set(lrg_buf_cb, maplen,
1697                                                   qdev->lrg_buffer_len -
1698                                                   QL_HEADER_SPACE);
1699                                 --qdev->lrg_buf_skb_check;
1700                                 if (!qdev->lrg_buf_skb_check)
1701                                         return 1;
1702                         }
1703                 }
1704                 lrg_buf_cb = lrg_buf_cb->next;
1705         }
1706         return 0;
1707 }
1708
1709 /*
1710  * Caller holds hw_lock.
1711  */
1712 static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
1713 {
1714         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1715         if (qdev->small_buf_release_cnt >= 16) {
1716                 while (qdev->small_buf_release_cnt >= 16) {
1717                         qdev->small_buf_q_producer_index++;
1718
1719                         if (qdev->small_buf_q_producer_index ==
1720                             NUM_SBUFQ_ENTRIES)
1721                                 qdev->small_buf_q_producer_index = 0;
1722                         qdev->small_buf_release_cnt -= 8;
1723                 }
1724                 wmb();
1725                 writel(qdev->small_buf_q_producer_index,
1726                         &port_regs->CommonRegs.rxSmallQProducerIndex);
1727         }
1728 }
1729
1730 /*
1731  * Caller holds hw_lock.
1732  */
1733 static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1734 {
1735         struct bufq_addr_element *lrg_buf_q_ele;
1736         int i;
1737         struct ql_rcv_buf_cb *lrg_buf_cb;
1738         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1739
1740         if ((qdev->lrg_buf_free_count >= 8)
1741             && (qdev->lrg_buf_release_cnt >= 16)) {
1742
1743                 if (qdev->lrg_buf_skb_check)
1744                         if (!ql_populate_free_queue(qdev))
1745                                 return;
1746
1747                 lrg_buf_q_ele = qdev->lrg_buf_next_free;
1748
1749                 while ((qdev->lrg_buf_release_cnt >= 16)
1750                        && (qdev->lrg_buf_free_count >= 8)) {
1751
1752                         for (i = 0; i < 8; i++) {
1753                                 lrg_buf_cb =
1754                                     ql_get_from_lrg_buf_free_list(qdev);
1755                                 lrg_buf_q_ele->addr_high =
1756                                     lrg_buf_cb->buf_phy_addr_high;
1757                                 lrg_buf_q_ele->addr_low =
1758                                     lrg_buf_cb->buf_phy_addr_low;
1759                                 lrg_buf_q_ele++;
1760
1761                                 qdev->lrg_buf_release_cnt--;
1762                         }
1763
1764                         qdev->lrg_buf_q_producer_index++;
1765
1766                         if (qdev->lrg_buf_q_producer_index == qdev->num_lbufq_entries)
1767                                 qdev->lrg_buf_q_producer_index = 0;
1768
1769                         if (qdev->lrg_buf_q_producer_index ==
1770                             (qdev->num_lbufq_entries - 1)) {
1771                                 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
1772                         }
1773                 }
1774                 wmb();
1775                 qdev->lrg_buf_next_free = lrg_buf_q_ele;
1776                 writel(qdev->lrg_buf_q_producer_index,
1777                         &port_regs->CommonRegs.rxLargeQProducerIndex);
1778         }
1779 }
1780
1781 static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
1782                                    struct ob_mac_iocb_rsp *mac_rsp)
1783 {
1784         struct ql_tx_buf_cb *tx_cb;
1785         int i;
1786         int retval = 0;
1787
1788         if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1789                 printk(KERN_WARNING "Frame short but, frame was padded and sent.\n");
1790         }
1791         
1792         tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
1793
1794         /*  Check the transmit response flags for any errors */
1795         if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1796                 printk(KERN_ERR "Frame too short to be legal, frame not sent.\n");
1797
1798                 qdev->stats.tx_errors++;
1799                 retval = -EIO;
1800                 goto frame_not_sent;
1801         }
1802
1803         if(tx_cb->seg_count == 0) {
1804                 printk(KERN_ERR "tx_cb->seg_count == 0: %d\n", mac_rsp->transaction_id);
1805
1806                 qdev->stats.tx_errors++;
1807                 retval = -EIO;
1808                 goto invalid_seg_count;
1809         }
1810
1811         pci_unmap_single(qdev->pdev,
1812                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
1813                          pci_unmap_len(&tx_cb->map[0], maplen),
1814                          PCI_DMA_TODEVICE);
1815         tx_cb->seg_count--;
1816         if (tx_cb->seg_count) {
1817                 for (i = 1; i < tx_cb->seg_count; i++) {
1818                         pci_unmap_page(qdev->pdev,
1819                                        pci_unmap_addr(&tx_cb->map[i],
1820                                                       mapaddr),
1821                                        pci_unmap_len(&tx_cb->map[i], maplen),
1822                                        PCI_DMA_TODEVICE);
1823                 }
1824         }
1825         qdev->stats.tx_packets++;
1826         qdev->stats.tx_bytes += tx_cb->skb->len;
1827
1828 frame_not_sent:
1829         dev_kfree_skb_irq(tx_cb->skb);
1830         tx_cb->skb = NULL;
1831
1832 invalid_seg_count:
1833         atomic_inc(&qdev->tx_count);
1834 }
1835
1836 static void ql_get_sbuf(struct ql3_adapter *qdev)
1837 {
1838         if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1839                 qdev->small_buf_index = 0;
1840         qdev->small_buf_release_cnt++;
1841 }
1842
1843 static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
1844 {
1845         struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
1846         lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
1847         qdev->lrg_buf_release_cnt++;
1848         if (++qdev->lrg_buf_index == qdev->num_large_buffers)
1849                 qdev->lrg_buf_index = 0;
1850         return(lrg_buf_cb);
1851 }
1852
1853 /*
1854  * The difference between 3022 and 3032 for inbound completions:
1855  * 3022 uses two buffers per completion.  The first buffer contains 
1856  * (some) header info, the second the remainder of the headers plus 
1857  * the data.  For this chip we reserve some space at the top of the 
1858  * receive buffer so that the header info in buffer one can be 
1859  * prepended to the buffer two.  Buffer two is the sent up while 
1860  * buffer one is returned to the hardware to be reused.
1861  * 3032 receives all of it's data and headers in one buffer for a 
1862  * simpler process.  3032 also supports checksum verification as
1863  * can be seen in ql_process_macip_rx_intr().
1864  */
1865 static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
1866                                    struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
1867 {
1868         struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1869         struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
1870         struct sk_buff *skb;
1871         u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
1872
1873         /*
1874          * Get the inbound address list (small buffer).
1875          */
1876         ql_get_sbuf(qdev);
1877
1878         if (qdev->device_id == QL3022_DEVICE_ID)
1879                 lrg_buf_cb1 = ql_get_lbuf(qdev);
1880
1881         /* start of second buffer */
1882         lrg_buf_cb2 = ql_get_lbuf(qdev);
1883         skb = lrg_buf_cb2->skb;
1884
1885         qdev->stats.rx_packets++;
1886         qdev->stats.rx_bytes += length;
1887
1888         skb_put(skb, length);
1889         pci_unmap_single(qdev->pdev,
1890                          pci_unmap_addr(lrg_buf_cb2, mapaddr),
1891                          pci_unmap_len(lrg_buf_cb2, maplen),
1892                          PCI_DMA_FROMDEVICE);
1893         prefetch(skb->data);
1894         skb->ip_summed = CHECKSUM_NONE;
1895         skb->protocol = eth_type_trans(skb, qdev->ndev);
1896
1897         netif_receive_skb(skb);
1898         qdev->ndev->last_rx = jiffies;
1899         lrg_buf_cb2->skb = NULL;
1900
1901         if (qdev->device_id == QL3022_DEVICE_ID)
1902                 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
1903         ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1904 }
1905
1906 static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
1907                                      struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
1908 {
1909         struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1910         struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
1911         struct sk_buff *skb1 = NULL, *skb2;
1912         struct net_device *ndev = qdev->ndev;
1913         u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
1914         u16 size = 0;
1915
1916         /*
1917          * Get the inbound address list (small buffer).
1918          */
1919
1920         ql_get_sbuf(qdev);
1921
1922         if (qdev->device_id == QL3022_DEVICE_ID) {
1923                 /* start of first buffer on 3022 */
1924                 lrg_buf_cb1 = ql_get_lbuf(qdev);
1925                 skb1 = lrg_buf_cb1->skb;
1926                 size = ETH_HLEN;
1927                 if (*((u16 *) skb1->data) != 0xFFFF)
1928                         size += VLAN_ETH_HLEN - ETH_HLEN;
1929         }
1930
1931         /* start of second buffer */
1932         lrg_buf_cb2 = ql_get_lbuf(qdev);
1933         skb2 = lrg_buf_cb2->skb;
1934
1935         skb_put(skb2, length);  /* Just the second buffer length here. */
1936         pci_unmap_single(qdev->pdev,
1937                          pci_unmap_addr(lrg_buf_cb2, mapaddr),
1938                          pci_unmap_len(lrg_buf_cb2, maplen),
1939                          PCI_DMA_FROMDEVICE);
1940         prefetch(skb2->data);
1941
1942         skb2->ip_summed = CHECKSUM_NONE;
1943         if (qdev->device_id == QL3022_DEVICE_ID) {
1944                 /*
1945                  * Copy the ethhdr from first buffer to second. This
1946                  * is necessary for 3022 IP completions.
1947                  */
1948                 skb_copy_from_linear_data_offset(skb1, VLAN_ID_LEN,
1949                                                  skb_push(skb2, size), size);
1950         } else {
1951                 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
1952                 if (checksum & 
1953                         (IB_IP_IOCB_RSP_3032_ICE | 
1954                          IB_IP_IOCB_RSP_3032_CE)) { 
1955                         printk(KERN_ERR
1956                                "%s: Bad checksum for this %s packet, checksum = %x.\n",
1957                                __func__,
1958                                ((checksum & 
1959                                 IB_IP_IOCB_RSP_3032_TCP) ? "TCP" :
1960                                 "UDP"),checksum);
1961                 } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
1962                                 (checksum & IB_IP_IOCB_RSP_3032_UDP &&
1963                                 !(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
1964                         skb2->ip_summed = CHECKSUM_UNNECESSARY;
1965                 }
1966         }
1967         skb2->protocol = eth_type_trans(skb2, qdev->ndev);
1968
1969         netif_receive_skb(skb2);
1970         qdev->stats.rx_packets++;
1971         qdev->stats.rx_bytes += length;
1972         ndev->last_rx = jiffies;
1973         lrg_buf_cb2->skb = NULL;
1974
1975         if (qdev->device_id == QL3022_DEVICE_ID)
1976                 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
1977         ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1978 }
1979
1980 static int ql_tx_rx_clean(struct ql3_adapter *qdev,
1981                           int *tx_cleaned, int *rx_cleaned, int work_to_do)
1982 {
1983         struct net_rsp_iocb *net_rsp;
1984         struct net_device *ndev = qdev->ndev;
1985         int work_done = 0;
1986
1987         /* While there are entries in the completion queue. */
1988         while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
1989                 qdev->rsp_consumer_index) && (work_done < work_to_do)) {
1990
1991                 net_rsp = qdev->rsp_current;
1992                 switch (net_rsp->opcode) {
1993
1994                 case OPCODE_OB_MAC_IOCB_FN0:
1995                 case OPCODE_OB_MAC_IOCB_FN2:
1996                         ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
1997                                                net_rsp);
1998                         (*tx_cleaned)++;
1999                         break;
2000
2001                 case OPCODE_IB_MAC_IOCB:
2002                 case OPCODE_IB_3032_MAC_IOCB:
2003                         ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
2004                                                net_rsp);
2005                         (*rx_cleaned)++;
2006                         break;
2007
2008                 case OPCODE_IB_IP_IOCB:
2009                 case OPCODE_IB_3032_IP_IOCB:
2010                         ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
2011                                                  net_rsp);
2012                         (*rx_cleaned)++;
2013                         break;
2014                 default:
2015                         {
2016                                 u32 *tmp = (u32 *) net_rsp;
2017                                 printk(KERN_ERR PFX
2018                                        "%s: Hit default case, not "
2019                                        "handled!\n"
2020                                        "        dropping the packet, opcode = "
2021                                        "%x.\n",
2022                                        ndev->name, net_rsp->opcode);
2023                                 printk(KERN_ERR PFX
2024                                        "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
2025                                        (unsigned long int)tmp[0],
2026                                        (unsigned long int)tmp[1],
2027                                        (unsigned long int)tmp[2],
2028                                        (unsigned long int)tmp[3]);
2029                         }
2030                 }
2031
2032                 qdev->rsp_consumer_index++;
2033
2034                 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2035                         qdev->rsp_consumer_index = 0;
2036                         qdev->rsp_current = qdev->rsp_q_virt_addr;
2037                 } else {
2038                         qdev->rsp_current++;
2039                 }
2040
2041                 work_done = *tx_cleaned + *rx_cleaned;
2042         }
2043
2044         return work_done;
2045 }
2046
2047 static int ql_poll(struct net_device *ndev, int *budget)
2048 {
2049         struct ql3_adapter *qdev = netdev_priv(ndev);
2050         int work_to_do = min(*budget, ndev->quota);
2051         int rx_cleaned = 0, tx_cleaned = 0;
2052         unsigned long hw_flags;
2053         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2054
2055         if (!netif_carrier_ok(ndev))
2056                 goto quit_polling;
2057
2058         ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, work_to_do);
2059         *budget -= rx_cleaned;
2060         ndev->quota -= rx_cleaned;
2061
2062         if( tx_cleaned + rx_cleaned != work_to_do ||
2063             !netif_running(ndev)) {
2064 quit_polling:
2065                 netif_rx_complete(ndev);
2066
2067                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
2068                 ql_update_small_bufq_prod_index(qdev);
2069                 ql_update_lrg_bufq_prod_index(qdev);
2070                 writel(qdev->rsp_consumer_index,
2071                             &port_regs->CommonRegs.rspQConsumerIndex);
2072                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2073
2074                 ql_enable_interrupts(qdev);
2075                 return 0;
2076         }
2077         return 1;
2078 }
2079
2080 static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2081 {
2082
2083         struct net_device *ndev = dev_id;
2084         struct ql3_adapter *qdev = netdev_priv(ndev);
2085         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2086         u32 value;
2087         int handled = 1;
2088         u32 var;
2089
2090         port_regs = qdev->mem_map_registers;
2091
2092         value =
2093             ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
2094
2095         if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2096                 spin_lock(&qdev->adapter_lock);
2097                 netif_stop_queue(qdev->ndev);
2098                 netif_carrier_off(qdev->ndev);
2099                 ql_disable_interrupts(qdev);
2100                 qdev->port_link_state = LS_DOWN;
2101                 set_bit(QL_RESET_ACTIVE,&qdev->flags) ;
2102
2103                 if (value & ISP_CONTROL_FE) {
2104                         /*
2105                          * Chip Fatal Error.
2106                          */
2107                         var =
2108                             ql_read_page0_reg_l(qdev,
2109                                               &port_regs->PortFatalErrStatus);
2110                         printk(KERN_WARNING PFX
2111                                "%s: Resetting chip. PortFatalErrStatus "
2112                                "register = 0x%x\n", ndev->name, var);
2113                         set_bit(QL_RESET_START,&qdev->flags) ;
2114                 } else {
2115                         /*
2116                          * Soft Reset Requested.
2117                          */
2118                         set_bit(QL_RESET_PER_SCSI,&qdev->flags) ;
2119                         printk(KERN_ERR PFX
2120                                "%s: Another function issued a reset to the "
2121                                "chip. ISR value = %x.\n", ndev->name, value);
2122                 }
2123                 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2124                 spin_unlock(&qdev->adapter_lock);
2125         } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2126                 ql_disable_interrupts(qdev);
2127                 if (likely(netif_rx_schedule_prep(ndev))) {
2128                         __netif_rx_schedule(ndev);
2129                 }
2130         } else {
2131                 return IRQ_NONE;
2132         }
2133
2134         return IRQ_RETVAL(handled);
2135 }
2136
2137 /*
2138  * Get the total number of segments needed for the 
2139  * given number of fragments.  This is necessary because
2140  * outbound address lists (OAL) will be used when more than
2141  * two frags are given.  Each address list has 5 addr/len 
2142  * pairs.  The 5th pair in each AOL is used to  point to
2143  * the next AOL if more frags are coming.  
2144  * That is why the frags:segment count  ratio is not linear.
2145  */
2146 static int ql_get_seg_count(struct ql3_adapter *qdev,
2147                             unsigned short frags)
2148 {
2149         if (qdev->device_id == QL3022_DEVICE_ID)
2150                 return 1;
2151
2152         switch(frags) {
2153         case 0: return 1;       /* just the skb->data seg */
2154         case 1: return 2;       /* skb->data + 1 frag */
2155         case 2: return 3;       /* skb->data + 2 frags */
2156         case 3: return 5;       /* skb->data + 1 frag + 1 AOL containting 2 frags */
2157         case 4: return 6;
2158         case 5: return 7;
2159         case 6: return 8;
2160         case 7: return 10;
2161         case 8: return 11;
2162         case 9: return 12;
2163         case 10: return 13;
2164         case 11: return 15;
2165         case 12: return 16;
2166         case 13: return 17;
2167         case 14: return 18;
2168         case 15: return 20;
2169         case 16: return 21;
2170         case 17: return 22;
2171         case 18: return 23;
2172         }
2173         return -1;
2174 }
2175
2176 static void ql_hw_csum_setup(struct sk_buff *skb,
2177                              struct ob_mac_iocb_req *mac_iocb_ptr)
2178 {
2179         struct ethhdr *eth;
2180         struct iphdr *ip = NULL;
2181         u8 offset = ETH_HLEN;
2182
2183         eth = (struct ethhdr *)(skb->data);
2184
2185         if (eth->h_proto == __constant_htons(ETH_P_IP)) {
2186                 ip = (struct iphdr *)&skb->data[ETH_HLEN];
2187         } else if (eth->h_proto == htons(ETH_P_8021Q) &&
2188                    ((struct vlan_ethhdr *)skb->data)->
2189                    h_vlan_encapsulated_proto == __constant_htons(ETH_P_IP)) {
2190                 ip = (struct iphdr *)&skb->data[VLAN_ETH_HLEN];
2191                 offset = VLAN_ETH_HLEN;
2192         }
2193
2194         if (ip) {
2195                 if (ip->protocol == IPPROTO_TCP) {
2196                         mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC | 
2197                         OB_3032MAC_IOCB_REQ_IC;
2198                         mac_iocb_ptr->ip_hdr_off = offset;
2199                         mac_iocb_ptr->ip_hdr_len = ip->ihl;
2200                 } else if (ip->protocol == IPPROTO_UDP) {
2201                         mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC | 
2202                         OB_3032MAC_IOCB_REQ_IC;
2203                         mac_iocb_ptr->ip_hdr_off = offset;
2204                         mac_iocb_ptr->ip_hdr_len = ip->ihl;
2205                 }
2206         }
2207 }
2208
2209 /*
2210  * Map the buffers for this transmit.  This will return
2211  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
2212  */
2213 static int ql_send_map(struct ql3_adapter *qdev,
2214                                 struct ob_mac_iocb_req *mac_iocb_ptr,
2215                                 struct ql_tx_buf_cb *tx_cb,
2216                                 struct sk_buff *skb)
2217 {
2218         struct oal *oal;
2219         struct oal_entry *oal_entry;
2220         int len = skb_headlen(skb);
2221         dma_addr_t map;
2222         int err;
2223         int completed_segs, i;
2224         int seg_cnt, seg = 0;
2225         int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2226
2227         seg_cnt = tx_cb->seg_count;
2228         /*
2229          * Map the skb buffer first.
2230          */
2231         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
2232
2233         err = pci_dma_mapping_error(map);
2234         if(err) {
2235                 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n", 
2236                        qdev->ndev->name, err);
2237
2238                 return NETDEV_TX_BUSY;
2239         }
2240         
2241         oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2242         oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2243         oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2244         oal_entry->len = cpu_to_le32(len);
2245         pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2246         pci_unmap_len_set(&tx_cb->map[seg], maplen, len);
2247         seg++;
2248
2249         if (seg_cnt == 1) {
2250                 /* Terminate the last segment. */
2251                 oal_entry->len =
2252                     cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2253         } else {
2254                 oal = tx_cb->oal;
2255                 for (completed_segs=0; completed_segs<frag_cnt; completed_segs++,seg++) {
2256                         skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
2257                         oal_entry++;
2258                         if ((seg == 2 && seg_cnt > 3) ||        /* Check for continuation */
2259                             (seg == 7 && seg_cnt > 8) ||        /* requirements. It's strange */
2260                             (seg == 12 && seg_cnt > 13) ||      /* but necessary. */
2261                             (seg == 17 && seg_cnt > 18)) {
2262                                 /* Continuation entry points to outbound address list. */
2263                                 map = pci_map_single(qdev->pdev, oal,
2264                                                      sizeof(struct oal),
2265                                                      PCI_DMA_TODEVICE);
2266
2267                                 err = pci_dma_mapping_error(map);
2268                                 if(err) {
2269
2270                                         printk(KERN_ERR "%s: PCI mapping outbound address list with error: %d\n", 
2271                                                qdev->ndev->name, err);
2272                                         goto map_error;
2273                                 }
2274
2275                                 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2276                                 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2277                                 oal_entry->len =
2278                                     cpu_to_le32(sizeof(struct oal) |
2279                                                 OAL_CONT_ENTRY);
2280                                 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr,
2281                                                    map);
2282                                 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2283                                                   sizeof(struct oal));
2284                                 oal_entry = (struct oal_entry *)oal;
2285                                 oal++;
2286                                 seg++;
2287                         }
2288
2289                         map =
2290                             pci_map_page(qdev->pdev, frag->page,
2291                                          frag->page_offset, frag->size,
2292                                          PCI_DMA_TODEVICE);
2293
2294                         err = pci_dma_mapping_error(map);
2295                         if(err) {
2296                                 printk(KERN_ERR "%s: PCI mapping frags failed with error: %d\n", 
2297                                        qdev->ndev->name, err);
2298                                 goto map_error;
2299                         }
2300
2301                         oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2302                         oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2303                         oal_entry->len = cpu_to_le32(frag->size);
2304                         pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2305                         pci_unmap_len_set(&tx_cb->map[seg], maplen,
2306                                           frag->size);
2307                 }
2308                 /* Terminate the last segment. */
2309                 oal_entry->len =
2310                     cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2311         }
2312
2313         return NETDEV_TX_OK;
2314
2315 map_error:
2316         /* A PCI mapping failed and now we will need to back out
2317          * We need to traverse through the oal's and associated pages which 
2318          * have been mapped and now we must unmap them to clean up properly
2319          */
2320         
2321         seg = 1;
2322         oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2323         oal = tx_cb->oal;
2324         for (i=0; i<completed_segs; i++,seg++) {
2325                 oal_entry++;
2326
2327                 if((seg == 2 && seg_cnt > 3) ||        /* Check for continuation */
2328                    (seg == 7 && seg_cnt > 8) ||        /* requirements. It's strange */
2329                    (seg == 12 && seg_cnt > 13) ||      /* but necessary. */
2330                    (seg == 17 && seg_cnt > 18)) {
2331                         pci_unmap_single(qdev->pdev,
2332                                 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2333                                 pci_unmap_len(&tx_cb->map[seg], maplen),
2334                                  PCI_DMA_TODEVICE);
2335                         oal++;
2336                         seg++;
2337                 }
2338
2339                 pci_unmap_page(qdev->pdev,
2340                                pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2341                                pci_unmap_len(&tx_cb->map[seg], maplen),
2342                                PCI_DMA_TODEVICE);
2343         }
2344
2345         pci_unmap_single(qdev->pdev,
2346                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
2347                          pci_unmap_addr(&tx_cb->map[0], maplen),
2348                          PCI_DMA_TODEVICE);
2349
2350         return NETDEV_TX_BUSY;
2351
2352 }
2353
2354 /*
2355  * The difference between 3022 and 3032 sends:
2356  * 3022 only supports a simple single segment transmission.
2357  * 3032 supports checksumming and scatter/gather lists (fragments).
2358  * The 3032 supports sglists by using the 3 addr/len pairs (ALP) 
2359  * in the IOCB plus a chain of outbound address lists (OAL) that 
2360  * each contain 5 ALPs.  The last ALP of the IOCB (3rd) or OAL (5th) 
2361  * will used to point to an OAL when more ALP entries are required.  
2362  * The IOCB is always the top of the chain followed by one or more 
2363  * OALs (when necessary).
2364  */
2365 static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev)
2366 {
2367         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
2368         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2369         struct ql_tx_buf_cb *tx_cb;
2370         u32 tot_len = skb->len;
2371         struct ob_mac_iocb_req *mac_iocb_ptr;
2372
2373         if (unlikely(atomic_read(&qdev->tx_count) < 2)) {
2374                 return NETDEV_TX_BUSY;
2375         }
2376         
2377         tx_cb = &qdev->tx_buf[qdev->req_producer_index] ;
2378         if((tx_cb->seg_count = ql_get_seg_count(qdev,
2379                                                 (skb_shinfo(skb)->nr_frags))) == -1) {
2380                 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2381                 return NETDEV_TX_OK;
2382         }
2383         
2384         mac_iocb_ptr = tx_cb->queue_entry;
2385         memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
2386         mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2387         mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2388         mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2389         mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2390         mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2391         tx_cb->skb = skb;
2392         if (qdev->device_id == QL3032_DEVICE_ID &&
2393             skb->ip_summed == CHECKSUM_PARTIAL)
2394                 ql_hw_csum_setup(skb, mac_iocb_ptr);
2395         
2396         if(ql_send_map(qdev,mac_iocb_ptr,tx_cb,skb) != NETDEV_TX_OK) {
2397                 printk(KERN_ERR PFX"%s: Could not map the segments!\n",__func__);
2398                 return NETDEV_TX_BUSY;
2399         }
2400         
2401         wmb();
2402         qdev->req_producer_index++;
2403         if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2404                 qdev->req_producer_index = 0;
2405         wmb();
2406         ql_write_common_reg_l(qdev,
2407                             &port_regs->CommonRegs.reqQProducerIndex,
2408                             qdev->req_producer_index);
2409
2410         ndev->trans_start = jiffies;
2411         if (netif_msg_tx_queued(qdev))
2412                 printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n",
2413                        ndev->name, qdev->req_producer_index, skb->len);
2414
2415         atomic_dec(&qdev->tx_count);
2416         return NETDEV_TX_OK;
2417 }
2418
2419 static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2420 {
2421         qdev->req_q_size =
2422             (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2423
2424         qdev->req_q_virt_addr =
2425             pci_alloc_consistent(qdev->pdev,
2426                                  (size_t) qdev->req_q_size,
2427                                  &qdev->req_q_phy_addr);
2428
2429         if ((qdev->req_q_virt_addr == NULL) ||
2430             LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2431                 printk(KERN_ERR PFX "%s: reqQ failed.\n",
2432                        qdev->ndev->name);
2433                 return -ENOMEM;
2434         }
2435
2436         qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2437
2438         qdev->rsp_q_virt_addr =
2439             pci_alloc_consistent(qdev->pdev,
2440                                  (size_t) qdev->rsp_q_size,
2441                                  &qdev->rsp_q_phy_addr);
2442
2443         if ((qdev->rsp_q_virt_addr == NULL) ||
2444             LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2445                 printk(KERN_ERR PFX
2446                        "%s: rspQ allocation failed\n",
2447                        qdev->ndev->name);
2448                 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2449                                     qdev->req_q_virt_addr,
2450                                     qdev->req_q_phy_addr);
2451                 return -ENOMEM;
2452         }
2453
2454         set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2455
2456         return 0;
2457 }
2458
2459 static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2460 {
2461         if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) {
2462                 printk(KERN_INFO PFX
2463                        "%s: Already done.\n", qdev->ndev->name);
2464                 return;
2465         }
2466
2467         pci_free_consistent(qdev->pdev,
2468                             qdev->req_q_size,
2469                             qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2470
2471         qdev->req_q_virt_addr = NULL;
2472
2473         pci_free_consistent(qdev->pdev,
2474                             qdev->rsp_q_size,
2475                             qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2476
2477         qdev->rsp_q_virt_addr = NULL;
2478
2479         clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2480 }
2481
2482 static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2483 {
2484         /* Create Large Buffer Queue */
2485         qdev->lrg_buf_q_size =
2486             qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2487         if (qdev->lrg_buf_q_size < PAGE_SIZE)
2488                 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2489         else
2490                 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2491
2492         qdev->lrg_buf = kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),GFP_KERNEL);
2493         if (qdev->lrg_buf == NULL) {
2494                 printk(KERN_ERR PFX
2495                        "%s: qdev->lrg_buf alloc failed.\n", qdev->ndev->name);
2496                 return -ENOMEM;
2497         }
2498         
2499         qdev->lrg_buf_q_alloc_virt_addr =
2500             pci_alloc_consistent(qdev->pdev,
2501                                  qdev->lrg_buf_q_alloc_size,
2502                                  &qdev->lrg_buf_q_alloc_phy_addr);
2503
2504         if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2505                 printk(KERN_ERR PFX
2506                        "%s: lBufQ failed\n", qdev->ndev->name);
2507                 return -ENOMEM;
2508         }
2509         qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2510         qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2511
2512         /* Create Small Buffer Queue */
2513         qdev->small_buf_q_size =
2514             NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2515         if (qdev->small_buf_q_size < PAGE_SIZE)
2516                 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2517         else
2518                 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2519
2520         qdev->small_buf_q_alloc_virt_addr =
2521             pci_alloc_consistent(qdev->pdev,
2522                                  qdev->small_buf_q_alloc_size,
2523                                  &qdev->small_buf_q_alloc_phy_addr);
2524
2525         if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2526                 printk(KERN_ERR PFX
2527                        "%s: Small Buffer Queue allocation failed.\n",
2528                        qdev->ndev->name);
2529                 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2530                                     qdev->lrg_buf_q_alloc_virt_addr,
2531                                     qdev->lrg_buf_q_alloc_phy_addr);
2532                 return -ENOMEM;
2533         }
2534
2535         qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2536         qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2537         set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2538         return 0;
2539 }
2540
2541 static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2542 {
2543         if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) {
2544                 printk(KERN_INFO PFX
2545                        "%s: Already done.\n", qdev->ndev->name);
2546                 return;
2547         }
2548         if(qdev->lrg_buf) kfree(qdev->lrg_buf);
2549         pci_free_consistent(qdev->pdev,
2550                             qdev->lrg_buf_q_alloc_size,
2551                             qdev->lrg_buf_q_alloc_virt_addr,
2552                             qdev->lrg_buf_q_alloc_phy_addr);
2553
2554         qdev->lrg_buf_q_virt_addr = NULL;
2555
2556         pci_free_consistent(qdev->pdev,
2557                             qdev->small_buf_q_alloc_size,
2558                             qdev->small_buf_q_alloc_virt_addr,
2559                             qdev->small_buf_q_alloc_phy_addr);
2560
2561         qdev->small_buf_q_virt_addr = NULL;
2562
2563         clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2564 }
2565
2566 static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2567 {
2568         int i;
2569         struct bufq_addr_element *small_buf_q_entry;
2570
2571         /* Currently we allocate on one of memory and use it for smallbuffers */
2572         qdev->small_buf_total_size =
2573             (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2574              QL_SMALL_BUFFER_SIZE);
2575
2576         qdev->small_buf_virt_addr =
2577             pci_alloc_consistent(qdev->pdev,
2578                                  qdev->small_buf_total_size,
2579                                  &qdev->small_buf_phy_addr);
2580
2581         if (qdev->small_buf_virt_addr == NULL) {
2582                 printk(KERN_ERR PFX
2583                        "%s: Failed to get small buffer memory.\n",
2584                        qdev->ndev->name);
2585                 return -ENOMEM;
2586         }
2587
2588         qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2589         qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2590
2591         small_buf_q_entry = qdev->small_buf_q_virt_addr;
2592
2593         /* Initialize the small buffer queue. */
2594         for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2595                 small_buf_q_entry->addr_high =
2596                     cpu_to_le32(qdev->small_buf_phy_addr_high);
2597                 small_buf_q_entry->addr_low =
2598                     cpu_to_le32(qdev->small_buf_phy_addr_low +
2599                                 (i * QL_SMALL_BUFFER_SIZE));
2600                 small_buf_q_entry++;
2601         }
2602         qdev->small_buf_index = 0;
2603         set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags);
2604         return 0;
2605 }
2606
2607 static void ql_free_small_buffers(struct ql3_adapter *qdev)
2608 {
2609         if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) {
2610                 printk(KERN_INFO PFX
2611                        "%s: Already done.\n", qdev->ndev->name);
2612                 return;
2613         }
2614         if (qdev->small_buf_virt_addr != NULL) {
2615                 pci_free_consistent(qdev->pdev,
2616                                     qdev->small_buf_total_size,
2617                                     qdev->small_buf_virt_addr,
2618                                     qdev->small_buf_phy_addr);
2619
2620                 qdev->small_buf_virt_addr = NULL;
2621         }
2622 }
2623
2624 static void ql_free_large_buffers(struct ql3_adapter *qdev)
2625 {
2626         int i = 0;
2627         struct ql_rcv_buf_cb *lrg_buf_cb;
2628
2629         for (i = 0; i < qdev->num_large_buffers; i++) {
2630                 lrg_buf_cb = &qdev->lrg_buf[i];
2631                 if (lrg_buf_cb->skb) {
2632                         dev_kfree_skb(lrg_buf_cb->skb);
2633                         pci_unmap_single(qdev->pdev,
2634                                          pci_unmap_addr(lrg_buf_cb, mapaddr),
2635                                          pci_unmap_len(lrg_buf_cb, maplen),
2636                                          PCI_DMA_FROMDEVICE);
2637                         memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2638                 } else {
2639                         break;
2640                 }
2641         }
2642 }
2643
2644 static void ql_init_large_buffers(struct ql3_adapter *qdev)
2645 {
2646         int i;
2647         struct ql_rcv_buf_cb *lrg_buf_cb;
2648         struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2649
2650         for (i = 0; i < qdev->num_large_buffers; i++) {
2651                 lrg_buf_cb = &qdev->lrg_buf[i];
2652                 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2653                 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2654                 buf_addr_ele++;
2655         }
2656         qdev->lrg_buf_index = 0;
2657         qdev->lrg_buf_skb_check = 0;
2658 }
2659
2660 static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2661 {
2662         int i;
2663         struct ql_rcv_buf_cb *lrg_buf_cb;
2664         struct sk_buff *skb;
2665         dma_addr_t map;
2666         int err;
2667
2668         for (i = 0; i < qdev->num_large_buffers; i++) {
2669                 skb = netdev_alloc_skb(qdev->ndev,
2670                                        qdev->lrg_buffer_len);
2671                 if (unlikely(!skb)) {
2672                         /* Better luck next round */
2673                         printk(KERN_ERR PFX
2674                                "%s: large buff alloc failed, "
2675                                "for %d bytes at index %d.\n",
2676                                qdev->ndev->name,
2677                                qdev->lrg_buffer_len * 2, i);
2678                         ql_free_large_buffers(qdev);
2679                         return -ENOMEM;
2680                 } else {
2681
2682                         lrg_buf_cb = &qdev->lrg_buf[i];
2683                         memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2684                         lrg_buf_cb->index = i;
2685                         lrg_buf_cb->skb = skb;
2686                         /*
2687                          * We save some space to copy the ethhdr from first
2688                          * buffer
2689                          */
2690                         skb_reserve(skb, QL_HEADER_SPACE);
2691                         map = pci_map_single(qdev->pdev,
2692                                              skb->data,
2693                                              qdev->lrg_buffer_len -
2694                                              QL_HEADER_SPACE,
2695                                              PCI_DMA_FROMDEVICE);
2696
2697                         err = pci_dma_mapping_error(map);
2698                         if(err) {
2699                                 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2700                                        qdev->ndev->name, err);
2701                                 ql_free_large_buffers(qdev);
2702                                 return -ENOMEM;
2703                         }
2704
2705                         pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2706                         pci_unmap_len_set(lrg_buf_cb, maplen,
2707                                           qdev->lrg_buffer_len -
2708                                           QL_HEADER_SPACE);
2709                         lrg_buf_cb->buf_phy_addr_low =
2710                             cpu_to_le32(LS_64BITS(map));
2711                         lrg_buf_cb->buf_phy_addr_high =
2712                             cpu_to_le32(MS_64BITS(map));
2713                 }
2714         }
2715         return 0;
2716 }
2717
2718 static void ql_free_send_free_list(struct ql3_adapter *qdev)
2719 {
2720         struct ql_tx_buf_cb *tx_cb;
2721         int i;
2722
2723         tx_cb = &qdev->tx_buf[0];
2724         for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2725                 if (tx_cb->oal) {
2726                         kfree(tx_cb->oal);
2727                         tx_cb->oal = NULL;
2728                 }
2729                 tx_cb++;
2730         }
2731 }
2732
2733 static int ql_create_send_free_list(struct ql3_adapter *qdev)
2734 {
2735         struct ql_tx_buf_cb *tx_cb;
2736         int i;
2737         struct ob_mac_iocb_req *req_q_curr =
2738                                         qdev->req_q_virt_addr;
2739
2740         /* Create free list of transmit buffers */
2741         for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2742
2743                 tx_cb = &qdev->tx_buf[i];
2744                 tx_cb->skb = NULL;
2745                 tx_cb->queue_entry = req_q_curr;
2746                 req_q_curr++;
2747                 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2748                 if (tx_cb->oal == NULL)
2749                         return -1;
2750         }
2751         return 0;
2752 }
2753
2754 static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2755 {
2756         if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
2757                 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
2758                 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
2759         }
2760         else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
2761                 /*
2762                  * Bigger buffers, so less of them.
2763                  */
2764                 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
2765                 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2766         } else {
2767                 printk(KERN_ERR PFX
2768                        "%s: Invalid mtu size.  Only 1500 and 9000 are accepted.\n",
2769                        qdev->ndev->name);
2770                 return -ENOMEM;
2771         }
2772         qdev->num_large_buffers = qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
2773         qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2774         qdev->max_frame_size =
2775             (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2776
2777         /*
2778          * First allocate a page of shared memory and use it for shadow
2779          * locations of Network Request Queue Consumer Address Register and
2780          * Network Completion Queue Producer Index Register
2781          */
2782         qdev->shadow_reg_virt_addr =
2783             pci_alloc_consistent(qdev->pdev,
2784                                  PAGE_SIZE, &qdev->shadow_reg_phy_addr);
2785
2786         if (qdev->shadow_reg_virt_addr != NULL) {
2787                 qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
2788                 qdev->req_consumer_index_phy_addr_high =
2789                     MS_64BITS(qdev->shadow_reg_phy_addr);
2790                 qdev->req_consumer_index_phy_addr_low =
2791                     LS_64BITS(qdev->shadow_reg_phy_addr);
2792
2793                 qdev->prsp_producer_index =
2794                     (u32 *) (((u8 *) qdev->preq_consumer_index) + 8);
2795                 qdev->rsp_producer_index_phy_addr_high =
2796                     qdev->req_consumer_index_phy_addr_high;
2797                 qdev->rsp_producer_index_phy_addr_low =
2798                     qdev->req_consumer_index_phy_addr_low + 8;
2799         } else {
2800                 printk(KERN_ERR PFX
2801                        "%s: shadowReg Alloc failed.\n", qdev->ndev->name);
2802                 return -ENOMEM;
2803         }
2804
2805         if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
2806                 printk(KERN_ERR PFX
2807                        "%s: ql_alloc_net_req_rsp_queues failed.\n",
2808                        qdev->ndev->name);
2809                 goto err_req_rsp;
2810         }
2811
2812         if (ql_alloc_buffer_queues(qdev) != 0) {
2813                 printk(KERN_ERR PFX
2814                        "%s: ql_alloc_buffer_queues failed.\n",
2815                        qdev->ndev->name);
2816                 goto err_buffer_queues;
2817         }
2818
2819         if (ql_alloc_small_buffers(qdev) != 0) {
2820                 printk(KERN_ERR PFX
2821                        "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name);
2822                 goto err_small_buffers;
2823         }
2824
2825         if (ql_alloc_large_buffers(qdev) != 0) {
2826                 printk(KERN_ERR PFX
2827                        "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name);
2828                 goto err_small_buffers;
2829         }
2830
2831         /* Initialize the large buffer queue. */
2832         ql_init_large_buffers(qdev);
2833         if (ql_create_send_free_list(qdev))
2834                 goto err_free_list;
2835
2836         qdev->rsp_current = qdev->rsp_q_virt_addr;
2837
2838         return 0;
2839 err_free_list:
2840         ql_free_send_free_list(qdev);
2841 err_small_buffers:
2842         ql_free_buffer_queues(qdev);
2843 err_buffer_queues:
2844         ql_free_net_req_rsp_queues(qdev);
2845 err_req_rsp:
2846         pci_free_consistent(qdev->pdev,
2847                             PAGE_SIZE,
2848                             qdev->shadow_reg_virt_addr,
2849                             qdev->shadow_reg_phy_addr);
2850
2851         return -ENOMEM;
2852 }
2853
2854 static void ql_free_mem_resources(struct ql3_adapter *qdev)
2855 {
2856         ql_free_send_free_list(qdev);
2857         ql_free_large_buffers(qdev);
2858         ql_free_small_buffers(qdev);
2859         ql_free_buffer_queues(qdev);
2860         ql_free_net_req_rsp_queues(qdev);
2861         if (qdev->shadow_reg_virt_addr != NULL) {
2862                 pci_free_consistent(qdev->pdev,
2863                                     PAGE_SIZE,
2864                                     qdev->shadow_reg_virt_addr,
2865                                     qdev->shadow_reg_phy_addr);
2866                 qdev->shadow_reg_virt_addr = NULL;
2867         }
2868 }
2869
2870 static int ql_init_misc_registers(struct ql3_adapter *qdev)
2871 {
2872         struct ql3xxx_local_ram_registers __iomem *local_ram =
2873             (void __iomem *)qdev->mem_map_registers;
2874
2875         if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
2876                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2877                          2) << 4))
2878                 return -1;
2879
2880         ql_write_page2_reg(qdev,
2881                            &local_ram->bufletSize, qdev->nvram_data.bufletSize);
2882
2883         ql_write_page2_reg(qdev,
2884                            &local_ram->maxBufletCount,
2885                            qdev->nvram_data.bufletCount);
2886
2887         ql_write_page2_reg(qdev,
2888                            &local_ram->freeBufletThresholdLow,
2889                            (qdev->nvram_data.tcpWindowThreshold25 << 16) |
2890                            (qdev->nvram_data.tcpWindowThreshold0));
2891
2892         ql_write_page2_reg(qdev,
2893                            &local_ram->freeBufletThresholdHigh,
2894                            qdev->nvram_data.tcpWindowThreshold50);
2895
2896         ql_write_page2_reg(qdev,
2897                            &local_ram->ipHashTableBase,
2898                            (qdev->nvram_data.ipHashTableBaseHi << 16) |
2899                            qdev->nvram_data.ipHashTableBaseLo);
2900         ql_write_page2_reg(qdev,
2901                            &local_ram->ipHashTableCount,
2902                            qdev->nvram_data.ipHashTableSize);
2903         ql_write_page2_reg(qdev,
2904                            &local_ram->tcpHashTableBase,
2905                            (qdev->nvram_data.tcpHashTableBaseHi << 16) |
2906                            qdev->nvram_data.tcpHashTableBaseLo);
2907         ql_write_page2_reg(qdev,
2908                            &local_ram->tcpHashTableCount,
2909                            qdev->nvram_data.tcpHashTableSize);
2910         ql_write_page2_reg(qdev,
2911                            &local_ram->ncbBase,
2912                            (qdev->nvram_data.ncbTableBaseHi << 16) |
2913                            qdev->nvram_data.ncbTableBaseLo);
2914         ql_write_page2_reg(qdev,
2915                            &local_ram->maxNcbCount,
2916                            qdev->nvram_data.ncbTableSize);
2917         ql_write_page2_reg(qdev,
2918                            &local_ram->drbBase,
2919                            (qdev->nvram_data.drbTableBaseHi << 16) |
2920                            qdev->nvram_data.drbTableBaseLo);
2921         ql_write_page2_reg(qdev,
2922                            &local_ram->maxDrbCount,
2923                            qdev->nvram_data.drbTableSize);
2924         ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
2925         return 0;
2926 }
2927
2928 static int ql_adapter_initialize(struct ql3_adapter *qdev)
2929 {
2930         u32 value;
2931         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2932         struct ql3xxx_host_memory_registers __iomem *hmem_regs =
2933                                                 (void __iomem *)port_regs;
2934         u32 delay = 10;
2935         int status = 0;
2936
2937         if(ql_mii_setup(qdev))
2938                 return -1;
2939
2940         /* Bring out PHY out of reset */
2941         ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2942                             (ISP_SERIAL_PORT_IF_WE |
2943                              (ISP_SERIAL_PORT_IF_WE << 16)));
2944
2945         qdev->port_link_state = LS_DOWN;
2946         netif_carrier_off(qdev->ndev);
2947
2948         /* V2 chip fix for ARS-39168. */
2949         ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2950                             (ISP_SERIAL_PORT_IF_SDE |
2951                              (ISP_SERIAL_PORT_IF_SDE << 16)));
2952
2953         /* Request Queue Registers */
2954         *((u32 *) (qdev->preq_consumer_index)) = 0;
2955         atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES);
2956         qdev->req_producer_index = 0;
2957
2958         ql_write_page1_reg(qdev,
2959                            &hmem_regs->reqConsumerIndexAddrHigh,
2960                            qdev->req_consumer_index_phy_addr_high);
2961         ql_write_page1_reg(qdev,
2962                            &hmem_regs->reqConsumerIndexAddrLow,
2963                            qdev->req_consumer_index_phy_addr_low);
2964
2965         ql_write_page1_reg(qdev,
2966                            &hmem_regs->reqBaseAddrHigh,
2967                            MS_64BITS(qdev->req_q_phy_addr));
2968         ql_write_page1_reg(qdev,
2969                            &hmem_regs->reqBaseAddrLow,
2970                            LS_64BITS(qdev->req_q_phy_addr));
2971         ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
2972
2973         /* Response Queue Registers */
2974         *((u16 *) (qdev->prsp_producer_index)) = 0;
2975         qdev->rsp_consumer_index = 0;
2976         qdev->rsp_current = qdev->rsp_q_virt_addr;
2977
2978         ql_write_page1_reg(qdev,
2979                            &hmem_regs->rspProducerIndexAddrHigh,
2980                            qdev->rsp_producer_index_phy_addr_high);
2981
2982         ql_write_page1_reg(qdev,
2983                            &hmem_regs->rspProducerIndexAddrLow,
2984                            qdev->rsp_producer_index_phy_addr_low);
2985
2986         ql_write_page1_reg(qdev,
2987                            &hmem_regs->rspBaseAddrHigh,
2988                            MS_64BITS(qdev->rsp_q_phy_addr));
2989
2990         ql_write_page1_reg(qdev,
2991                            &hmem_regs->rspBaseAddrLow,
2992                            LS_64BITS(qdev->rsp_q_phy_addr));
2993
2994         ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
2995
2996         /* Large Buffer Queue */
2997         ql_write_page1_reg(qdev,
2998                            &hmem_regs->rxLargeQBaseAddrHigh,
2999                            MS_64BITS(qdev->lrg_buf_q_phy_addr));
3000
3001         ql_write_page1_reg(qdev,
3002                            &hmem_regs->rxLargeQBaseAddrLow,
3003                            LS_64BITS(qdev->lrg_buf_q_phy_addr));
3004
3005         ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, qdev->num_lbufq_entries);
3006
3007         ql_write_page1_reg(qdev,
3008                            &hmem_regs->rxLargeBufferLength,
3009                            qdev->lrg_buffer_len);
3010
3011         /* Small Buffer Queue */
3012         ql_write_page1_reg(qdev,
3013                            &hmem_regs->rxSmallQBaseAddrHigh,
3014                            MS_64BITS(qdev->small_buf_q_phy_addr));
3015
3016         ql_write_page1_reg(qdev,
3017                            &hmem_regs->rxSmallQBaseAddrLow,
3018                            LS_64BITS(qdev->small_buf_q_phy_addr));
3019
3020         ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3021         ql_write_page1_reg(qdev,
3022                            &hmem_regs->rxSmallBufferLength,
3023                            QL_SMALL_BUFFER_SIZE);
3024
3025         qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3026         qdev->small_buf_release_cnt = 8;
3027         qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
3028         qdev->lrg_buf_release_cnt = 8;
3029         qdev->lrg_buf_next_free =
3030             (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
3031         qdev->small_buf_index = 0;
3032         qdev->lrg_buf_index = 0;
3033         qdev->lrg_buf_free_count = 0;
3034         qdev->lrg_buf_free_head = NULL;
3035         qdev->lrg_buf_free_tail = NULL;
3036
3037         ql_write_common_reg(qdev,
3038                             &port_regs->CommonRegs.
3039                             rxSmallQProducerIndex,
3040                             qdev->small_buf_q_producer_index);
3041         ql_write_common_reg(qdev,
3042                             &port_regs->CommonRegs.
3043                             rxLargeQProducerIndex,
3044                             qdev->lrg_buf_q_producer_index);
3045
3046         /*
3047          * Find out if the chip has already been initialized.  If it has, then
3048          * we skip some of the initialization.
3049          */
3050         clear_bit(QL_LINK_MASTER, &qdev->flags);
3051         value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3052         if ((value & PORT_STATUS_IC) == 0) {
3053
3054                 /* Chip has not been configured yet, so let it rip. */
3055                 if(ql_init_misc_registers(qdev)) {
3056                         status = -1;
3057                         goto out;
3058                 }
3059
3060                 value = qdev->nvram_data.tcpMaxWindowSize;
3061                 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3062
3063                 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3064
3065                 if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3066                                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3067                                  * 2) << 13)) {
3068                         status = -1;
3069                         goto out;
3070                 }
3071                 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3072                 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3073                                    (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3074                                      16) | (INTERNAL_CHIP_SD |
3075                                             INTERNAL_CHIP_WE)));
3076                 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3077         }
3078
3079         if (qdev->mac_index)
3080                 ql_write_page0_reg(qdev,
3081                                    &port_regs->mac1MaxFrameLengthReg,
3082                                    qdev->max_frame_size);
3083         else
3084                 ql_write_page0_reg(qdev,
3085                                            &port_regs->mac0MaxFrameLengthReg,
3086                                            qdev->max_frame_size);
3087
3088         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3089                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3090                          2) << 7)) {
3091                 status = -1;
3092                 goto out;
3093         }
3094
3095         ql_init_scan_mode(qdev);
3096         ql_get_phy_owner(qdev);
3097
3098         /* Load the MAC Configuration */
3099
3100         /* Program lower 32 bits of the MAC address */
3101         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3102                            (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3103         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3104                            ((qdev->ndev->dev_addr[2] << 24)
3105                             | (qdev->ndev->dev_addr[3] << 16)
3106                             | (qdev->ndev->dev_addr[4] << 8)
3107                             | qdev->ndev->dev_addr[5]));
3108
3109         /* Program top 16 bits of the MAC address */
3110         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3111                            ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3112         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3113                            ((qdev->ndev->dev_addr[0] << 8)
3114                             | qdev->ndev->dev_addr[1]));
3115
3116         /* Enable Primary MAC */
3117         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3118                            ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3119                             MAC_ADDR_INDIRECT_PTR_REG_PE));
3120
3121         /* Clear Primary and Secondary IP addresses */
3122         ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3123                            ((IP_ADDR_INDEX_REG_MASK << 16) |
3124                             (qdev->mac_index << 2)));
3125         ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3126
3127         ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3128                            ((IP_ADDR_INDEX_REG_MASK << 16) |
3129                             ((qdev->mac_index << 2) + 1)));
3130         ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3131
3132         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3133
3134         /* Indicate Configuration Complete */
3135         ql_write_page0_reg(qdev,
3136                            &port_regs->portControl,
3137                            ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3138
3139         do {
3140                 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3141                 if (value & PORT_STATUS_IC)
3142                         break;
3143                 msleep(500);
3144         } while (--delay);
3145
3146         if (delay == 0) {
3147                 printk(KERN_ERR PFX
3148                        "%s: Hw Initialization timeout.\n", qdev->ndev->name);
3149                 status = -1;
3150                 goto out;
3151         }
3152
3153         /* Enable Ethernet Function */
3154         if (qdev->device_id == QL3032_DEVICE_ID) {
3155                 value =
3156                     (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3157                      QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
3158                         QL3032_PORT_CONTROL_ET);
3159                 ql_write_page0_reg(qdev, &port_regs->functionControl,
3160                                    ((value << 16) | value));
3161         } else {
3162                 value =
3163                     (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3164                      PORT_CONTROL_HH);
3165                 ql_write_page0_reg(qdev, &port_regs->portControl,
3166                                    ((value << 16) | value));
3167         }
3168
3169
3170 out:
3171         return status;
3172 }
3173
3174 /*
3175  * Caller holds hw_lock.
3176  */
3177 static int ql_adapter_reset(struct ql3_adapter *qdev)
3178 {
3179         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3180         int status = 0;
3181         u16 value;
3182         int max_wait_time;
3183
3184         set_bit(QL_RESET_ACTIVE, &qdev->flags);
3185         clear_bit(QL_RESET_DONE, &qdev->flags);
3186
3187         /*
3188          * Issue soft reset to chip.
3189          */
3190         printk(KERN_DEBUG PFX
3191                "%s: Issue soft reset to chip.\n",
3192                qdev->ndev->name);
3193         ql_write_common_reg(qdev,
3194                             &port_regs->CommonRegs.ispControlStatus,
3195                             ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3196
3197         /* Wait 3 seconds for reset to complete. */
3198         printk(KERN_DEBUG PFX
3199                "%s: Wait 10 milliseconds for reset to complete.\n",
3200                qdev->ndev->name);
3201
3202         /* Wait until the firmware tells us the Soft Reset is done */
3203         max_wait_time = 5;
3204         do {
3205                 value =
3206                     ql_read_common_reg(qdev,
3207                                        &port_regs->CommonRegs.ispControlStatus);
3208                 if ((value & ISP_CONTROL_SR) == 0)
3209                         break;
3210
3211                 ssleep(1);
3212         } while ((--max_wait_time));
3213
3214         /*
3215          * Also, make sure that the Network Reset Interrupt bit has been
3216          * cleared after the soft reset has taken place.
3217          */
3218         value =
3219             ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3220         if (value & ISP_CONTROL_RI) {
3221                 printk(KERN_DEBUG PFX
3222                        "ql_adapter_reset: clearing RI after reset.\n");
3223                 ql_write_common_reg(qdev,
3224                                     &port_regs->CommonRegs.
3225                                     ispControlStatus,
3226                                     ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3227         }
3228
3229         if (max_wait_time == 0) {
3230                 /* Issue Force Soft Reset */
3231                 ql_write_common_reg(qdev,
3232                                     &port_regs->CommonRegs.
3233                                     ispControlStatus,
3234                                     ((ISP_CONTROL_FSR << 16) |
3235                                      ISP_CONTROL_FSR));
3236                 /*
3237                  * Wait until the firmware tells us the Force Soft Reset is
3238                  * done
3239                  */
3240                 max_wait_time = 5;
3241                 do {
3242                         value =
3243                             ql_read_common_reg(qdev,
3244                                                &port_regs->CommonRegs.
3245                                                ispControlStatus);
3246                         if ((value & ISP_CONTROL_FSR) == 0) {
3247                                 break;
3248                         }
3249                         ssleep(1);
3250                 } while ((--max_wait_time));
3251         }
3252         if (max_wait_time == 0)
3253                 status = 1;
3254
3255         clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3256         set_bit(QL_RESET_DONE, &qdev->flags);
3257         return status;
3258 }
3259
3260 static void ql_set_mac_info(struct ql3_adapter *qdev)
3261 {
3262         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3263         u32 value, port_status;
3264         u8 func_number;
3265
3266         /* Get the function number */
3267         value =
3268             ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3269         func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3270         port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3271         switch (value & ISP_CONTROL_FN_MASK) {
3272         case ISP_CONTROL_FN0_NET:
3273                 qdev->mac_index = 0;
3274                 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3275                 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3276                 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3277                 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3278                 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3279                 if (port_status & PORT_STATUS_SM0)
3280                         set_bit(QL_LINK_OPTICAL,&qdev->flags);
3281                 else
3282                         clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3283                 break;
3284
3285         case ISP_CONTROL_FN1_NET:
3286                 qdev->mac_index = 1;
3287                 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3288                 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3289                 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3290                 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3291                 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3292                 if (port_status & PORT_STATUS_SM1)
3293                         set_bit(QL_LINK_OPTICAL,&qdev->flags);
3294                 else
3295                         clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3296                 break;
3297
3298         case ISP_CONTROL_FN0_SCSI:
3299         case ISP_CONTROL_FN1_SCSI:
3300         default:
3301                 printk(KERN_DEBUG PFX
3302                        "%s: Invalid function number, ispControlStatus = 0x%x\n",
3303                        qdev->ndev->name,value);
3304                 break;
3305         }
3306         qdev->numPorts = qdev->nvram_data.numPorts;
3307 }
3308
3309 static void ql_display_dev_info(struct net_device *ndev)
3310 {
3311         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3312         struct pci_dev *pdev = qdev->pdev;
3313
3314         printk(KERN_INFO PFX
3315                "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n",
3316                DRV_NAME, qdev->index, qdev->chip_rev_id,
3317                (qdev->device_id == QL3032_DEVICE_ID) ? "QLA3032" : "QLA3022",
3318                qdev->pci_slot);
3319         printk(KERN_INFO PFX
3320                "%s Interface.\n",
3321                test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER");
3322
3323         /*
3324          * Print PCI bus width/type.
3325          */
3326         printk(KERN_INFO PFX
3327                "Bus interface is %s %s.\n",
3328                ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3329                ((qdev->pci_x) ? "PCI-X" : "PCI"));
3330
3331         printk(KERN_INFO PFX
3332                "mem  IO base address adjusted = 0x%p\n",
3333                qdev->mem_map_registers);
3334         printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq);
3335
3336         if (netif_msg_probe(qdev))
3337                 printk(KERN_INFO PFX
3338                        "%s: MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
3339                        ndev->name, ndev->dev_addr[0], ndev->dev_addr[1],
3340                        ndev->dev_addr[2], ndev->dev_addr[3], ndev->dev_addr[4],
3341                        ndev->dev_addr[5]);
3342 }
3343
3344 static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3345 {
3346         struct net_device *ndev = qdev->ndev;
3347         int retval = 0;
3348
3349         netif_stop_queue(ndev);
3350         netif_carrier_off(ndev);
3351
3352         clear_bit(QL_ADAPTER_UP,&qdev->flags);
3353         clear_bit(QL_LINK_MASTER,&qdev->flags);
3354
3355         ql_disable_interrupts(qdev);
3356
3357         free_irq(qdev->pdev->irq, ndev);
3358
3359         if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3360                 printk(KERN_INFO PFX
3361                        "%s: calling pci_disable_msi().\n", qdev->ndev->name);
3362                 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3363                 pci_disable_msi(qdev->pdev);
3364         }
3365
3366         del_timer_sync(&qdev->adapter_timer);
3367
3368         netif_poll_disable(ndev);
3369
3370         if (do_reset) {
3371                 int soft_reset;
3372                 unsigned long hw_flags;
3373
3374                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3375                 if (ql_wait_for_drvr_lock(qdev)) {
3376                         if ((soft_reset = ql_adapter_reset(qdev))) {
3377                                 printk(KERN_ERR PFX
3378                                        "%s: ql_adapter_reset(%d) FAILED!\n",
3379                                        ndev->name, qdev->index);
3380                         }
3381                         printk(KERN_ERR PFX
3382                                 "%s: Releaseing driver lock via chip reset.\n",ndev->name);
3383                 } else {
3384                         printk(KERN_ERR PFX
3385                                "%s: Could not acquire driver lock to do "
3386                                "reset!\n", ndev->name);
3387                         retval = -1;
3388                 }
3389                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3390         }
3391         ql_free_mem_resources(qdev);
3392         return retval;
3393 }
3394
3395 static int ql_adapter_up(struct ql3_adapter *qdev)
3396 {
3397         struct net_device *ndev = qdev->ndev;
3398         int err;
3399         unsigned long irq_flags = IRQF_SAMPLE_RANDOM | IRQF_SHARED;
3400         unsigned long hw_flags;
3401
3402         if (ql_alloc_mem_resources(qdev)) {
3403                 printk(KERN_ERR PFX
3404                        "%s Unable to  allocate buffers.\n", ndev->name);
3405                 return -ENOMEM;
3406         }
3407
3408         if (qdev->msi) {
3409                 if (pci_enable_msi(qdev->pdev)) {
3410                         printk(KERN_ERR PFX
3411                                "%s: User requested MSI, but MSI failed to "
3412                                "initialize.  Continuing without MSI.\n",
3413                                qdev->ndev->name);
3414                         qdev->msi = 0;
3415                 } else {
3416                         printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name);
3417                         set_bit(QL_MSI_ENABLED,&qdev->flags);
3418                         irq_flags &= ~IRQF_SHARED;
3419                 }
3420         }
3421
3422         if ((err = request_irq(qdev->pdev->irq,
3423                                ql3xxx_isr,
3424                                irq_flags, ndev->name, ndev))) {
3425                 printk(KERN_ERR PFX
3426                        "%s: Failed to reserve interrupt %d already in use.\n",
3427                        ndev->name, qdev->pdev->irq);
3428                 goto err_irq;
3429         }
3430
3431         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3432
3433         if ((err = ql_wait_for_drvr_lock(qdev))) {
3434                 if ((err = ql_adapter_initialize(qdev))) {
3435                         printk(KERN_ERR PFX
3436                                "%s: Unable to initialize adapter.\n",
3437                                ndev->name);
3438                         goto err_init;
3439                 }
3440                 printk(KERN_ERR PFX
3441                                 "%s: Releaseing driver lock.\n",ndev->name);
3442                 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3443         } else {
3444                 printk(KERN_ERR PFX
3445                        "%s: Could not aquire driver lock.\n",
3446                        ndev->name);
3447                 goto err_lock;
3448         }
3449
3450         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3451
3452         set_bit(QL_ADAPTER_UP,&qdev->flags);
3453
3454         mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3455
3456         netif_poll_enable(ndev);
3457         ql_enable_interrupts(qdev);
3458         return 0;
3459
3460 err_init:
3461         ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3462 err_lock:
3463         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3464         free_irq(qdev->pdev->irq, ndev);
3465 err_irq:
3466         if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3467                 printk(KERN_INFO PFX
3468                        "%s: calling pci_disable_msi().\n",
3469                        qdev->ndev->name);
3470                 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3471                 pci_disable_msi(qdev->pdev);
3472         }
3473         return err;
3474 }
3475
3476 static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3477 {
3478         if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) {
3479                 printk(KERN_ERR PFX
3480                                 "%s: Driver up/down cycle failed, "
3481                                 "closing device\n",qdev->ndev->name);
3482                 dev_close(qdev->ndev);
3483                 return -1;
3484         }
3485         return 0;
3486 }
3487
3488 static int ql3xxx_close(struct net_device *ndev)
3489 {
3490         struct ql3_adapter *qdev = netdev_priv(ndev);
3491
3492         /*
3493          * Wait for device to recover from a reset.
3494          * (Rarely happens, but possible.)
3495          */
3496         while (!test_bit(QL_ADAPTER_UP,&qdev->flags))
3497                 msleep(50);
3498
3499         ql_adapter_down(qdev,QL_DO_RESET);
3500         return 0;
3501 }
3502
3503 static int ql3xxx_open(struct net_device *ndev)
3504 {
3505         struct ql3_adapter *qdev = netdev_priv(ndev);
3506         return (ql_adapter_up(qdev));
3507 }
3508
3509 static struct net_device_stats *ql3xxx_get_stats(struct net_device *dev)
3510 {
3511         struct ql3_adapter *qdev = (struct ql3_adapter *)dev->priv;
3512         return &qdev->stats;
3513 }
3514
3515 static void ql3xxx_set_multicast_list(struct net_device *ndev)
3516 {
3517         /*
3518          * We are manually parsing the list in the net_device structure.
3519          */
3520         return;
3521 }
3522
3523 static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3524 {
3525         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3526         struct ql3xxx_port_registers __iomem *port_regs =
3527                         qdev->mem_map_registers;
3528         struct sockaddr *addr = p;
3529         unsigned long hw_flags;
3530
3531         if (netif_running(ndev))
3532                 return -EBUSY;
3533
3534         if (!is_valid_ether_addr(addr->sa_data))
3535                 return -EADDRNOTAVAIL;
3536
3537         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3538
3539         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3540         /* Program lower 32 bits of the MAC address */
3541         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3542                            (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3543         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3544                            ((ndev->dev_addr[2] << 24) | (ndev->
3545                                                          dev_addr[3] << 16) |
3546                             (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3547
3548         /* Program top 16 bits of the MAC address */
3549         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3550                            ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3551         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3552                            ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3553         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3554
3555         return 0;
3556 }
3557
3558 static void ql3xxx_tx_timeout(struct net_device *ndev)
3559 {
3560         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3561
3562         printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name);
3563         /*
3564          * Stop the queues, we've got a problem.
3565          */
3566         netif_stop_queue(ndev);
3567
3568         /*
3569          * Wake up the worker to process this event.
3570          */
3571         queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3572 }
3573
3574 static void ql_reset_work(struct work_struct *work)
3575 {
3576         struct ql3_adapter *qdev =
3577                 container_of(work, struct ql3_adapter, reset_work.work);
3578         struct net_device *ndev = qdev->ndev;
3579         u32 value;
3580         struct ql_tx_buf_cb *tx_cb;
3581         int max_wait_time, i;
3582         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3583         unsigned long hw_flags;
3584
3585         if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) {
3586                 clear_bit(QL_LINK_MASTER,&qdev->flags);
3587
3588                 /*
3589                  * Loop through the active list and return the skb.
3590                  */
3591                 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3592                         int j;
3593                         tx_cb = &qdev->tx_buf[i];
3594                         if (tx_cb->skb) {
3595                                 printk(KERN_DEBUG PFX
3596                                        "%s: Freeing lost SKB.\n",
3597                                        qdev->ndev->name);
3598                                 pci_unmap_single(qdev->pdev,
3599                                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
3600                                          pci_unmap_len(&tx_cb->map[0], maplen),
3601                                          PCI_DMA_TODEVICE);
3602                                 for(j=1;j<tx_cb->seg_count;j++) {
3603                                         pci_unmap_page(qdev->pdev,
3604                                                pci_unmap_addr(&tx_cb->map[j],mapaddr),
3605                                                pci_unmap_len(&tx_cb->map[j],maplen),
3606                                                PCI_DMA_TODEVICE);
3607                                 }
3608                                 dev_kfree_skb(tx_cb->skb);
3609                                 tx_cb->skb = NULL;
3610                         }
3611                 }
3612
3613                 printk(KERN_ERR PFX
3614                        "%s: Clearing NRI after reset.\n", qdev->ndev->name);
3615                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3616                 ql_write_common_reg(qdev,
3617                                     &port_regs->CommonRegs.
3618                                     ispControlStatus,
3619                                     ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3620                 /*
3621                  * Wait the for Soft Reset to Complete.
3622                  */
3623                 max_wait_time = 10;
3624                 do {
3625                         value = ql_read_common_reg(qdev,
3626                                                    &port_regs->CommonRegs.
3627
3628                                                    ispControlStatus);
3629                         if ((value & ISP_CONTROL_SR) == 0) {
3630                                 printk(KERN_DEBUG PFX
3631                                        "%s: reset completed.\n",
3632                                        qdev->ndev->name);
3633                                 break;
3634                         }
3635
3636                         if (value & ISP_CONTROL_RI) {
3637                                 printk(KERN_DEBUG PFX
3638                                        "%s: clearing NRI after reset.\n",
3639                                        qdev->ndev->name);
3640                                 ql_write_common_reg(qdev,
3641                                                     &port_regs->
3642                                                     CommonRegs.
3643                                                     ispControlStatus,
3644                                                     ((ISP_CONTROL_RI <<
3645                                                       16) | ISP_CONTROL_RI));
3646                         }
3647
3648                         ssleep(1);
3649                 } while (--max_wait_time);
3650                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3651
3652                 if (value & ISP_CONTROL_SR) {
3653
3654                         /*
3655                          * Set the reset flags and clear the board again.
3656                          * Nothing else to do...
3657                          */
3658                         printk(KERN_ERR PFX
3659                                "%s: Timed out waiting for reset to "
3660                                "complete.\n", ndev->name);
3661                         printk(KERN_ERR PFX
3662                                "%s: Do a reset.\n", ndev->name);
3663                         clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3664                         clear_bit(QL_RESET_START,&qdev->flags);
3665                         ql_cycle_adapter(qdev,QL_DO_RESET);
3666                         return;
3667                 }
3668
3669                 clear_bit(QL_RESET_ACTIVE,&qdev->flags);
3670                 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3671                 clear_bit(QL_RESET_START,&qdev->flags);
3672                 ql_cycle_adapter(qdev,QL_NO_RESET);
3673         }
3674 }
3675
3676 static void ql_tx_timeout_work(struct work_struct *work)
3677 {
3678         struct ql3_adapter *qdev =
3679                 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3680
3681         ql_cycle_adapter(qdev, QL_DO_RESET);
3682 }
3683
3684 static void ql_get_board_info(struct ql3_adapter *qdev)
3685 {
3686         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3687         u32 value;
3688
3689         value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3690
3691         qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3692         if (value & PORT_STATUS_64)
3693                 qdev->pci_width = 64;
3694         else
3695                 qdev->pci_width = 32;
3696         if (value & PORT_STATUS_X)
3697                 qdev->pci_x = 1;
3698         else
3699                 qdev->pci_x = 0;
3700         qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3701 }
3702
3703 static void ql3xxx_timer(unsigned long ptr)
3704 {
3705         struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3706
3707         if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
3708                 printk(KERN_DEBUG PFX
3709                        "%s: Reset in progress.\n",
3710                        qdev->ndev->name);
3711                 goto end;
3712         }
3713
3714         ql_link_state_machine(qdev);
3715
3716         /* Restart timer on 2 second interval. */
3717 end:
3718         mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3719 }
3720
3721 static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3722                                   const struct pci_device_id *pci_entry)
3723 {
3724         struct net_device *ndev = NULL;
3725         struct ql3_adapter *qdev = NULL;
3726         static int cards_found = 0;
3727         int pci_using_dac, err;
3728
3729         err = pci_enable_device(pdev);
3730         if (err) {
3731                 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3732                        pci_name(pdev));
3733                 goto err_out;
3734         }
3735
3736         err = pci_request_regions(pdev, DRV_NAME);
3737         if (err) {
3738                 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3739                        pci_name(pdev));
3740                 goto err_out_disable_pdev;
3741         }
3742
3743         pci_set_master(pdev);
3744
3745         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3746                 pci_using_dac = 1;
3747                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3748         } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3749                 pci_using_dac = 0;
3750                 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3751         }
3752
3753         if (err) {
3754                 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3755                        pci_name(pdev));
3756                 goto err_out_free_regions;
3757         }
3758
3759         ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3760         if (!ndev) {
3761                 printk(KERN_ERR PFX "%s could not alloc etherdev\n",
3762                        pci_name(pdev));
3763                 err = -ENOMEM;
3764                 goto err_out_free_regions;
3765         }
3766
3767         SET_MODULE_OWNER(ndev);
3768         SET_NETDEV_DEV(ndev, &pdev->dev);
3769
3770         pci_set_drvdata(pdev, ndev);
3771
3772         qdev = netdev_priv(ndev);
3773         qdev->index = cards_found;
3774         qdev->ndev = ndev;
3775         qdev->pdev = pdev;
3776         qdev->device_id = pci_entry->device;
3777         qdev->port_link_state = LS_DOWN;
3778         if (msi)
3779                 qdev->msi = 1;
3780
3781         qdev->msg_enable = netif_msg_init(debug, default_msg);
3782
3783         if (pci_using_dac)
3784                 ndev->features |= NETIF_F_HIGHDMA;
3785         if (qdev->device_id == QL3032_DEVICE_ID)
3786                 ndev->features |= (NETIF_F_HW_CSUM | NETIF_F_SG);
3787
3788         qdev->mem_map_registers =
3789             ioremap_nocache(pci_resource_start(pdev, 1),
3790                             pci_resource_len(qdev->pdev, 1));
3791         if (!qdev->mem_map_registers) {
3792                 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3793                        pci_name(pdev));
3794                 err = -EIO;
3795                 goto err_out_free_ndev;
3796         }
3797
3798         spin_lock_init(&qdev->adapter_lock);
3799         spin_lock_init(&qdev->hw_lock);
3800
3801         /* Set driver entry points */
3802         ndev->open = ql3xxx_open;
3803         ndev->hard_start_xmit = ql3xxx_send;
3804         ndev->stop = ql3xxx_close;
3805         ndev->get_stats = ql3xxx_get_stats;
3806         ndev->set_multicast_list = ql3xxx_set_multicast_list;
3807         SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
3808         ndev->set_mac_address = ql3xxx_set_mac_address;
3809         ndev->tx_timeout = ql3xxx_tx_timeout;
3810         ndev->watchdog_timeo = 5 * HZ;
3811
3812         ndev->poll = &ql_poll;
3813         ndev->weight = 64;
3814
3815         ndev->irq = pdev->irq;
3816
3817         /* make sure the EEPROM is good */
3818         if (ql_get_nvram_params(qdev)) {
3819                 printk(KERN_ALERT PFX
3820                        "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
3821                        qdev->index);
3822                 err = -EIO;
3823                 goto err_out_iounmap;
3824         }
3825
3826         ql_set_mac_info(qdev);
3827
3828         /* Validate and set parameters */
3829         if (qdev->mac_index) {
3830                 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
3831                 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn2.macAddress,
3832                        ETH_ALEN);
3833         } else {
3834                 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
3835                 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn0.macAddress,
3836                        ETH_ALEN);
3837         }
3838         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3839
3840         ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
3841
3842         /* Turn off support for multicasting */
3843         ndev->flags &= ~IFF_MULTICAST;
3844
3845         /* Record PCI bus information. */
3846         ql_get_board_info(qdev);
3847
3848         /*
3849          * Set the Maximum Memory Read Byte Count value. We do this to handle
3850          * jumbo frames.
3851          */
3852         if (qdev->pci_x) {
3853                 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
3854         }
3855
3856         err = register_netdev(ndev);
3857         if (err) {
3858                 printk(KERN_ERR PFX "%s: cannot register net device\n",
3859                        pci_name(pdev));
3860                 goto err_out_iounmap;
3861         }
3862
3863         /* we're going to reset, so assume we have no link for now */
3864
3865         netif_carrier_off(ndev);
3866         netif_stop_queue(ndev);
3867
3868         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3869         INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
3870         INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
3871
3872         init_timer(&qdev->adapter_timer);
3873         qdev->adapter_timer.function = ql3xxx_timer;
3874         qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
3875         qdev->adapter_timer.data = (unsigned long)qdev;
3876
3877         if(!cards_found) {
3878                 printk(KERN_ALERT PFX "%s\n", DRV_STRING);
3879                 printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n",
3880                    DRV_NAME, DRV_VERSION);
3881         }
3882         ql_display_dev_info(ndev);
3883
3884         cards_found++;
3885         return 0;
3886
3887 err_out_iounmap:
3888         iounmap(qdev->mem_map_registers);
3889 err_out_free_ndev:
3890         free_netdev(ndev);
3891 err_out_free_regions:
3892         pci_release_regions(pdev);
3893 err_out_disable_pdev:
3894         pci_disable_device(pdev);
3895         pci_set_drvdata(pdev, NULL);
3896 err_out:
3897         return err;
3898 }
3899
3900 static void __devexit ql3xxx_remove(struct pci_dev *pdev)
3901 {
3902         struct net_device *ndev = pci_get_drvdata(pdev);
3903         struct ql3_adapter *qdev = netdev_priv(ndev);
3904
3905         unregister_netdev(ndev);
3906         qdev = netdev_priv(ndev);
3907
3908         ql_disable_interrupts(qdev);
3909
3910         if (qdev->workqueue) {
3911                 cancel_delayed_work(&qdev->reset_work);
3912                 cancel_delayed_work(&qdev->tx_timeout_work);
3913                 destroy_workqueue(qdev->workqueue);
3914                 qdev->workqueue = NULL;
3915         }
3916
3917         iounmap(qdev->mem_map_registers);
3918         pci_release_regions(pdev);
3919         pci_set_drvdata(pdev, NULL);
3920         free_netdev(ndev);
3921 }
3922
3923 static struct pci_driver ql3xxx_driver = {
3924
3925         .name = DRV_NAME,
3926         .id_table = ql3xxx_pci_tbl,
3927         .probe = ql3xxx_probe,
3928         .remove = __devexit_p(ql3xxx_remove),
3929 };
3930
3931 static int __init ql3xxx_init_module(void)
3932 {
3933         return pci_register_driver(&ql3xxx_driver);
3934 }
3935
3936 static void __exit ql3xxx_exit(void)
3937 {
3938         pci_unregister_driver(&ql3xxx_driver);
3939 }
3940
3941 module_init(ql3xxx_init_module);
3942 module_exit(ql3xxx_exit);