qla3xxx: Changed to use netdev_alloc_skb() from dev_alloc_skb
[linux-2.6.git] / drivers / net / qla3xxx.c
1 /*
2  * QLogic QLA3xxx NIC HBA Driver
3  * Copyright (c)  2003-2006 QLogic Corporation
4  *
5  * See LICENSE.qla3xxx for copyright and licensing details.
6  */
7
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
17 #include <linux/dmapool.h>
18 #include <linux/mempool.h>
19 #include <linux/spinlock.h>
20 #include <linux/kthread.h>
21 #include <linux/interrupt.h>
22 #include <linux/errno.h>
23 #include <linux/ioport.h>
24 #include <linux/ip.h>
25 #include <linux/in.h>
26 #include <linux/if_arp.h>
27 #include <linux/if_ether.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/ethtool.h>
31 #include <linux/skbuff.h>
32 #include <linux/rtnetlink.h>
33 #include <linux/if_vlan.h>
34 #include <linux/init.h>
35 #include <linux/delay.h>
36 #include <linux/mm.h>
37
38 #include "qla3xxx.h"
39
40 #define DRV_NAME        "qla3xxx"
41 #define DRV_STRING      "QLogic ISP3XXX Network Driver"
42 #define DRV_VERSION     "v2.02.00-k36"
43 #define PFX             DRV_NAME " "
44
45 static const char ql3xxx_driver_name[] = DRV_NAME;
46 static const char ql3xxx_driver_version[] = DRV_VERSION;
47
48 MODULE_AUTHOR("QLogic Corporation");
49 MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
50 MODULE_LICENSE("GPL");
51 MODULE_VERSION(DRV_VERSION);
52
53 static const u32 default_msg
54     = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
55     | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
56
57 static int debug = -1;          /* defaults above */
58 module_param(debug, int, 0);
59 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
60
61 static int msi;
62 module_param(msi, int, 0);
63 MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
64
65 static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
66         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
67         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
68         /* required last entry */
69         {0,}
70 };
71
72 MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
73
74 /*
75  * Caller must take hw_lock.
76  */
77 static int ql_sem_spinlock(struct ql3_adapter *qdev,
78                             u32 sem_mask, u32 sem_bits)
79 {
80         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
81         u32 value;
82         unsigned int seconds = 3;
83
84         do {
85                 writel((sem_mask | sem_bits),
86                        &port_regs->CommonRegs.semaphoreReg);
87                 value = readl(&port_regs->CommonRegs.semaphoreReg);
88                 if ((value & (sem_mask >> 16)) == sem_bits)
89                         return 0;
90                 ssleep(1);
91         } while(--seconds);
92         return -1;
93 }
94
95 static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
96 {
97         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
98         writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
99         readl(&port_regs->CommonRegs.semaphoreReg);
100 }
101
102 static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
103 {
104         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
105         u32 value;
106
107         writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
108         value = readl(&port_regs->CommonRegs.semaphoreReg);
109         return ((value & (sem_mask >> 16)) == sem_bits);
110 }
111
112 /*
113  * Caller holds hw_lock.
114  */
115 static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
116 {
117         int i = 0;
118
119         while (1) {
120                 if (!ql_sem_lock(qdev,
121                                  QL_DRVR_SEM_MASK,
122                                  (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
123                                   * 2) << 1)) {
124                         if (i < 10) {
125                                 ssleep(1);
126                                 i++;
127                         } else {
128                                 printk(KERN_ERR PFX "%s: Timed out waiting for "
129                                        "driver lock...\n",
130                                        qdev->ndev->name);
131                                 return 0;
132                         }
133                 } else {
134                         printk(KERN_DEBUG PFX
135                                "%s: driver lock acquired.\n",
136                                qdev->ndev->name);
137                         return 1;
138                 }
139         }
140 }
141
142 static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
143 {
144         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
145
146         writel(((ISP_CONTROL_NP_MASK << 16) | page),
147                         &port_regs->CommonRegs.ispControlStatus);
148         readl(&port_regs->CommonRegs.ispControlStatus);
149         qdev->current_page = page;
150 }
151
152 static u32 ql_read_common_reg_l(struct ql3_adapter *qdev,
153                               u32 __iomem * reg)
154 {
155         u32 value;
156         unsigned long hw_flags;
157
158         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
159         value = readl(reg);
160         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
161
162         return value;
163 }
164
165 static u32 ql_read_common_reg(struct ql3_adapter *qdev,
166                               u32 __iomem * reg)
167 {
168         return readl(reg);
169 }
170
171 static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
172 {
173         u32 value;
174         unsigned long hw_flags;
175
176         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
177
178         if (qdev->current_page != 0)
179                 ql_set_register_page(qdev,0);
180         value = readl(reg);
181
182         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
183         return value;
184 }
185
186 static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
187 {
188         if (qdev->current_page != 0)
189                 ql_set_register_page(qdev,0);
190         return readl(reg);
191 }
192
193 static void ql_write_common_reg_l(struct ql3_adapter *qdev,
194                                 u32 __iomem *reg, u32 value)
195 {
196         unsigned long hw_flags;
197
198         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
199         writel(value, reg);
200         readl(reg);
201         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
202         return;
203 }
204
205 static void ql_write_common_reg(struct ql3_adapter *qdev,
206                                 u32 __iomem *reg, u32 value)
207 {
208         writel(value, reg);
209         readl(reg);
210         return;
211 }
212
213 static void ql_write_nvram_reg(struct ql3_adapter *qdev,
214                                 u32 __iomem *reg, u32 value)
215 {
216         writel(value, reg);
217         readl(reg);
218         udelay(1);
219         return;
220 }
221
222 static void ql_write_page0_reg(struct ql3_adapter *qdev,
223                                u32 __iomem *reg, u32 value)
224 {
225         if (qdev->current_page != 0)
226                 ql_set_register_page(qdev,0);
227         writel(value, reg);
228         readl(reg);
229         return;
230 }
231
232 /*
233  * Caller holds hw_lock. Only called during init.
234  */
235 static void ql_write_page1_reg(struct ql3_adapter *qdev,
236                                u32 __iomem *reg, u32 value)
237 {
238         if (qdev->current_page != 1)
239                 ql_set_register_page(qdev,1);
240         writel(value, reg);
241         readl(reg);
242         return;
243 }
244
245 /*
246  * Caller holds hw_lock. Only called during init.
247  */
248 static void ql_write_page2_reg(struct ql3_adapter *qdev,
249                                u32 __iomem *reg, u32 value)
250 {
251         if (qdev->current_page != 2)
252                 ql_set_register_page(qdev,2);
253         writel(value, reg);
254         readl(reg);
255         return;
256 }
257
258 static void ql_disable_interrupts(struct ql3_adapter *qdev)
259 {
260         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
261
262         ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
263                             (ISP_IMR_ENABLE_INT << 16));
264
265 }
266
267 static void ql_enable_interrupts(struct ql3_adapter *qdev)
268 {
269         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
270
271         ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
272                             ((0xff << 16) | ISP_IMR_ENABLE_INT));
273
274 }
275
276 static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
277                                             struct ql_rcv_buf_cb *lrg_buf_cb)
278 {
279         u64 map;
280         lrg_buf_cb->next = NULL;
281
282         if (qdev->lrg_buf_free_tail == NULL) {  /* The list is empty  */
283                 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
284         } else {
285                 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
286                 qdev->lrg_buf_free_tail = lrg_buf_cb;
287         }
288
289         if (!lrg_buf_cb->skb) {
290                 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
291                                                    qdev->lrg_buffer_len);
292                 if (unlikely(!lrg_buf_cb->skb)) {
293                         printk(KERN_ERR PFX "%s: failed netdev_alloc_skb().\n",
294                                qdev->ndev->name);
295                         qdev->lrg_buf_skb_check++;
296                 } else {
297                         /*
298                          * We save some space to copy the ethhdr from first
299                          * buffer
300                          */
301                         skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
302                         map = pci_map_single(qdev->pdev,
303                                              lrg_buf_cb->skb->data,
304                                              qdev->lrg_buffer_len -
305                                              QL_HEADER_SPACE,
306                                              PCI_DMA_FROMDEVICE);
307                         lrg_buf_cb->buf_phy_addr_low =
308                             cpu_to_le32(LS_64BITS(map));
309                         lrg_buf_cb->buf_phy_addr_high =
310                             cpu_to_le32(MS_64BITS(map));
311                         pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
312                         pci_unmap_len_set(lrg_buf_cb, maplen,
313                                           qdev->lrg_buffer_len -
314                                           QL_HEADER_SPACE);
315                 }
316         }
317
318         qdev->lrg_buf_free_count++;
319 }
320
321 static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
322                                                            *qdev)
323 {
324         struct ql_rcv_buf_cb *lrg_buf_cb;
325
326         if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) {
327                 if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL)
328                         qdev->lrg_buf_free_tail = NULL;
329                 qdev->lrg_buf_free_count--;
330         }
331
332         return lrg_buf_cb;
333 }
334
335 static u32 addrBits = EEPROM_NO_ADDR_BITS;
336 static u32 dataBits = EEPROM_NO_DATA_BITS;
337
338 static void fm93c56a_deselect(struct ql3_adapter *qdev);
339 static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
340                             unsigned short *value);
341
342 /*
343  * Caller holds hw_lock.
344  */
345 static void fm93c56a_select(struct ql3_adapter *qdev)
346 {
347         struct ql3xxx_port_registers __iomem *port_regs =
348                         qdev->mem_map_registers;
349
350         qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
351         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
352                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
353         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
354                             ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
355 }
356
357 /*
358  * Caller holds hw_lock.
359  */
360 static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
361 {
362         int i;
363         u32 mask;
364         u32 dataBit;
365         u32 previousBit;
366         struct ql3xxx_port_registers __iomem *port_regs =
367                         qdev->mem_map_registers;
368
369         /* Clock in a zero, then do the start bit */
370         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
371                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
372                             AUBURN_EEPROM_DO_1);
373         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
374                             ISP_NVRAM_MASK | qdev->
375                             eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
376                             AUBURN_EEPROM_CLK_RISE);
377         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
378                             ISP_NVRAM_MASK | qdev->
379                             eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
380                             AUBURN_EEPROM_CLK_FALL);
381
382         mask = 1 << (FM93C56A_CMD_BITS - 1);
383         /* Force the previous data bit to be different */
384         previousBit = 0xffff;
385         for (i = 0; i < FM93C56A_CMD_BITS; i++) {
386                 dataBit =
387                     (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0;
388                 if (previousBit != dataBit) {
389                         /*
390                          * If the bit changed, then change the DO state to
391                          * match
392                          */
393                         ql_write_nvram_reg(qdev,
394                                             &port_regs->CommonRegs.
395                                             serialPortInterfaceReg,
396                                             ISP_NVRAM_MASK | qdev->
397                                             eeprom_cmd_data | dataBit);
398                         previousBit = dataBit;
399                 }
400                 ql_write_nvram_reg(qdev,
401                                     &port_regs->CommonRegs.
402                                     serialPortInterfaceReg,
403                                     ISP_NVRAM_MASK | qdev->
404                                     eeprom_cmd_data | dataBit |
405                                     AUBURN_EEPROM_CLK_RISE);
406                 ql_write_nvram_reg(qdev,
407                                     &port_regs->CommonRegs.
408                                     serialPortInterfaceReg,
409                                     ISP_NVRAM_MASK | qdev->
410                                     eeprom_cmd_data | dataBit |
411                                     AUBURN_EEPROM_CLK_FALL);
412                 cmd = cmd << 1;
413         }
414
415         mask = 1 << (addrBits - 1);
416         /* Force the previous data bit to be different */
417         previousBit = 0xffff;
418         for (i = 0; i < addrBits; i++) {
419                 dataBit =
420                     (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 :
421                     AUBURN_EEPROM_DO_0;
422                 if (previousBit != dataBit) {
423                         /*
424                          * If the bit changed, then change the DO state to
425                          * match
426                          */
427                         ql_write_nvram_reg(qdev,
428                                             &port_regs->CommonRegs.
429                                             serialPortInterfaceReg,
430                                             ISP_NVRAM_MASK | qdev->
431                                             eeprom_cmd_data | dataBit);
432                         previousBit = dataBit;
433                 }
434                 ql_write_nvram_reg(qdev,
435                                     &port_regs->CommonRegs.
436                                     serialPortInterfaceReg,
437                                     ISP_NVRAM_MASK | qdev->
438                                     eeprom_cmd_data | dataBit |
439                                     AUBURN_EEPROM_CLK_RISE);
440                 ql_write_nvram_reg(qdev,
441                                     &port_regs->CommonRegs.
442                                     serialPortInterfaceReg,
443                                     ISP_NVRAM_MASK | qdev->
444                                     eeprom_cmd_data | dataBit |
445                                     AUBURN_EEPROM_CLK_FALL);
446                 eepromAddr = eepromAddr << 1;
447         }
448 }
449
450 /*
451  * Caller holds hw_lock.
452  */
453 static void fm93c56a_deselect(struct ql3_adapter *qdev)
454 {
455         struct ql3xxx_port_registers __iomem *port_regs =
456                         qdev->mem_map_registers;
457         qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
458         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
459                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
460 }
461
462 /*
463  * Caller holds hw_lock.
464  */
465 static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
466 {
467         int i;
468         u32 data = 0;
469         u32 dataBit;
470         struct ql3xxx_port_registers __iomem *port_regs =
471                         qdev->mem_map_registers;
472
473         /* Read the data bits */
474         /* The first bit is a dummy.  Clock right over it. */
475         for (i = 0; i < dataBits; i++) {
476                 ql_write_nvram_reg(qdev,
477                                     &port_regs->CommonRegs.
478                                     serialPortInterfaceReg,
479                                     ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
480                                     AUBURN_EEPROM_CLK_RISE);
481                 ql_write_nvram_reg(qdev,
482                                     &port_regs->CommonRegs.
483                                     serialPortInterfaceReg,
484                                     ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
485                                     AUBURN_EEPROM_CLK_FALL);
486                 dataBit =
487                     (ql_read_common_reg
488                      (qdev,
489                       &port_regs->CommonRegs.
490                       serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0;
491                 data = (data << 1) | dataBit;
492         }
493         *value = (u16) data;
494 }
495
496 /*
497  * Caller holds hw_lock.
498  */
499 static void eeprom_readword(struct ql3_adapter *qdev,
500                             u32 eepromAddr, unsigned short *value)
501 {
502         fm93c56a_select(qdev);
503         fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
504         fm93c56a_datain(qdev, value);
505         fm93c56a_deselect(qdev);
506 }
507
508 static void ql_swap_mac_addr(u8 * macAddress)
509 {
510 #ifdef __BIG_ENDIAN
511         u8 temp;
512         temp = macAddress[0];
513         macAddress[0] = macAddress[1];
514         macAddress[1] = temp;
515         temp = macAddress[2];
516         macAddress[2] = macAddress[3];
517         macAddress[3] = temp;
518         temp = macAddress[4];
519         macAddress[4] = macAddress[5];
520         macAddress[5] = temp;
521 #endif
522 }
523
524 static int ql_get_nvram_params(struct ql3_adapter *qdev)
525 {
526         u16 *pEEPROMData;
527         u16 checksum = 0;
528         u32 index;
529         unsigned long hw_flags;
530
531         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
532
533         pEEPROMData = (u16 *) & qdev->nvram_data;
534         qdev->eeprom_cmd_data = 0;
535         if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
536                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
537                          2) << 10)) {
538                 printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n",
539                         __func__);
540                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
541                 return -1;
542         }
543
544         for (index = 0; index < EEPROM_SIZE; index++) {
545                 eeprom_readword(qdev, index, pEEPROMData);
546                 checksum += *pEEPROMData;
547                 pEEPROMData++;
548         }
549         ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
550
551         if (checksum != 0) {
552                 printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n",
553                        qdev->ndev->name, checksum);
554                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
555                 return -1;
556         }
557
558         /*
559          * We have a problem with endianness for the MAC addresses
560          * and the two 8-bit values version, and numPorts.  We
561          * have to swap them on big endian systems.
562          */
563         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn0.macAddress);
564         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn1.macAddress);
565         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn2.macAddress);
566         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn3.macAddress);
567         pEEPROMData = (u16 *) & qdev->nvram_data.version;
568         *pEEPROMData = le16_to_cpu(*pEEPROMData);
569
570         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
571         return checksum;
572 }
573
574 static const u32 PHYAddr[2] = {
575         PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
576 };
577
578 static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
579 {
580         struct ql3xxx_port_registers __iomem *port_regs =
581                         qdev->mem_map_registers;
582         u32 temp;
583         int count = 1000;
584
585         while (count) {
586                 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
587                 if (!(temp & MAC_MII_STATUS_BSY))
588                         return 0;
589                 udelay(10);
590                 count--;
591         }
592         return -1;
593 }
594
595 static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
596 {
597         struct ql3xxx_port_registers __iomem *port_regs =
598                         qdev->mem_map_registers;
599         u32 scanControl;
600
601         if (qdev->numPorts > 1) {
602                 /* Auto scan will cycle through multiple ports */
603                 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
604         } else {
605                 scanControl = MAC_MII_CONTROL_SC;
606         }
607
608         /*
609          * Scan register 1 of PHY/PETBI,
610          * Set up to scan both devices
611          * The autoscan starts from the first register, completes
612          * the last one before rolling over to the first
613          */
614         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
615                            PHYAddr[0] | MII_SCAN_REGISTER);
616
617         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
618                            (scanControl) |
619                            ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
620 }
621
622 static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
623 {
624         u8 ret;
625         struct ql3xxx_port_registers __iomem *port_regs =
626                                         qdev->mem_map_registers;
627
628         /* See if scan mode is enabled before we turn it off */
629         if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
630             (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
631                 /* Scan is enabled */
632                 ret = 1;
633         } else {
634                 /* Scan is disabled */
635                 ret = 0;
636         }
637
638         /*
639          * When disabling scan mode you must first change the MII register
640          * address
641          */
642         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
643                            PHYAddr[0] | MII_SCAN_REGISTER);
644
645         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
646                            ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
647                              MAC_MII_CONTROL_RC) << 16));
648
649         return ret;
650 }
651
652 static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
653                                u16 regAddr, u16 value, u32 mac_index)
654 {
655         struct ql3xxx_port_registers __iomem *port_regs =
656                         qdev->mem_map_registers;
657         u8 scanWasEnabled;
658
659         scanWasEnabled = ql_mii_disable_scan_mode(qdev);
660
661         if (ql_wait_for_mii_ready(qdev)) {
662                 if (netif_msg_link(qdev))
663                         printk(KERN_WARNING PFX
664                                "%s Timed out waiting for management port to "
665                                "get free before issuing command.\n",
666                                qdev->ndev->name);
667                 return -1;
668         }
669
670         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
671                            PHYAddr[mac_index] | regAddr);
672
673         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
674
675         /* Wait for write to complete 9/10/04 SJP */
676         if (ql_wait_for_mii_ready(qdev)) {
677                 if (netif_msg_link(qdev))
678                         printk(KERN_WARNING PFX
679                                "%s: Timed out waiting for management port to"
680                                "get free before issuing command.\n",
681                                qdev->ndev->name);
682                 return -1;
683         }
684
685         if (scanWasEnabled)
686                 ql_mii_enable_scan_mode(qdev);
687
688         return 0;
689 }
690
691 static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
692                               u16 * value, u32 mac_index)
693 {
694         struct ql3xxx_port_registers __iomem *port_regs =
695                         qdev->mem_map_registers;
696         u8 scanWasEnabled;
697         u32 temp;
698
699         scanWasEnabled = ql_mii_disable_scan_mode(qdev);
700
701         if (ql_wait_for_mii_ready(qdev)) {
702                 if (netif_msg_link(qdev))
703                         printk(KERN_WARNING PFX
704                                "%s: Timed out waiting for management port to "
705                                "get free before issuing command.\n",
706                                qdev->ndev->name);
707                 return -1;
708         }
709
710         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
711                            PHYAddr[mac_index] | regAddr);
712
713         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
714                            (MAC_MII_CONTROL_RC << 16));
715
716         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
717                            (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
718
719         /* Wait for the read to complete */
720         if (ql_wait_for_mii_ready(qdev)) {
721                 if (netif_msg_link(qdev))
722                         printk(KERN_WARNING PFX
723                                "%s: Timed out waiting for management port to "
724                                "get free after issuing command.\n",
725                                qdev->ndev->name);
726                 return -1;
727         }
728
729         temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
730         *value = (u16) temp;
731
732         if (scanWasEnabled)
733                 ql_mii_enable_scan_mode(qdev);
734
735         return 0;
736 }
737
738 static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
739 {
740         struct ql3xxx_port_registers __iomem *port_regs =
741                         qdev->mem_map_registers;
742
743         ql_mii_disable_scan_mode(qdev);
744
745         if (ql_wait_for_mii_ready(qdev)) {
746                 if (netif_msg_link(qdev))
747                         printk(KERN_WARNING PFX
748                                "%s: Timed out waiting for management port to "
749                                "get free before issuing command.\n",
750                                qdev->ndev->name);
751                 return -1;
752         }
753
754         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
755                            qdev->PHYAddr | regAddr);
756
757         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
758
759         /* Wait for write to complete. */
760         if (ql_wait_for_mii_ready(qdev)) {
761                 if (netif_msg_link(qdev))
762                         printk(KERN_WARNING PFX
763                                "%s: Timed out waiting for management port to "
764                                "get free before issuing command.\n",
765                                qdev->ndev->name);
766                 return -1;
767         }
768
769         ql_mii_enable_scan_mode(qdev);
770
771         return 0;
772 }
773
774 static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
775 {
776         u32 temp;
777         struct ql3xxx_port_registers __iomem *port_regs =
778                         qdev->mem_map_registers;
779
780         ql_mii_disable_scan_mode(qdev);
781
782         if (ql_wait_for_mii_ready(qdev)) {
783                 if (netif_msg_link(qdev))
784                         printk(KERN_WARNING PFX
785                                "%s: Timed out waiting for management port to "
786                                "get free before issuing command.\n",
787                                qdev->ndev->name);
788                 return -1;
789         }
790
791         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
792                            qdev->PHYAddr | regAddr);
793
794         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
795                            (MAC_MII_CONTROL_RC << 16));
796
797         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
798                            (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
799
800         /* Wait for the read to complete */
801         if (ql_wait_for_mii_ready(qdev)) {
802                 if (netif_msg_link(qdev))
803                         printk(KERN_WARNING PFX
804                                "%s: Timed out waiting for management port to "
805                                "get free before issuing command.\n",
806                                qdev->ndev->name);
807                 return -1;
808         }
809
810         temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
811         *value = (u16) temp;
812
813         ql_mii_enable_scan_mode(qdev);
814
815         return 0;
816 }
817
818 static void ql_petbi_reset(struct ql3_adapter *qdev)
819 {
820         ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
821 }
822
823 static void ql_petbi_start_neg(struct ql3_adapter *qdev)
824 {
825         u16 reg;
826
827         /* Enable Auto-negotiation sense */
828         ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
829         reg |= PETBI_TBI_AUTO_SENSE;
830         ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
831
832         ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
833                          PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
834
835         ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
836                          PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
837                          PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
838
839 }
840
841 static void ql_petbi_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
842 {
843         ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
844                             mac_index);
845 }
846
847 static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
848 {
849         u16 reg;
850
851         /* Enable Auto-negotiation sense */
852         ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg, mac_index);
853         reg |= PETBI_TBI_AUTO_SENSE;
854         ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg, mac_index);
855
856         ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
857                             PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX, mac_index);
858
859         ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
860                             PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
861                             PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
862                             mac_index);
863 }
864
865 static void ql_petbi_init(struct ql3_adapter *qdev)
866 {
867         ql_petbi_reset(qdev);
868         ql_petbi_start_neg(qdev);
869 }
870
871 static void ql_petbi_init_ex(struct ql3_adapter *qdev, u32 mac_index)
872 {
873         ql_petbi_reset_ex(qdev, mac_index);
874         ql_petbi_start_neg_ex(qdev, mac_index);
875 }
876
877 static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
878 {
879         u16 reg;
880
881         if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
882                 return 0;
883
884         return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
885 }
886
887 static int ql_phy_get_speed(struct ql3_adapter *qdev)
888 {
889         u16 reg;
890
891         if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
892                 return 0;
893
894         reg = (((reg & 0x18) >> 3) & 3);
895
896         if (reg == 2)
897                 return SPEED_1000;
898         else if (reg == 1)
899                 return SPEED_100;
900         else if (reg == 0)
901                 return SPEED_10;
902         else
903                 return -1;
904 }
905
906 static int ql_is_full_dup(struct ql3_adapter *qdev)
907 {
908         u16 reg;
909
910         if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
911                 return 0;
912
913         return (reg & PHY_AUX_DUPLEX_STAT) != 0;
914 }
915
916 static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
917 {
918         u16 reg;
919
920         if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
921                 return 0;
922
923         return (reg & PHY_NEG_PAUSE) != 0;
924 }
925
926 /*
927  * Caller holds hw_lock.
928  */
929 static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
930 {
931         struct ql3xxx_port_registers __iomem *port_regs =
932                         qdev->mem_map_registers;
933         u32 value;
934
935         if (enable)
936                 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
937         else
938                 value = (MAC_CONFIG_REG_PE << 16);
939
940         if (qdev->mac_index)
941                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
942         else
943                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
944 }
945
946 /*
947  * Caller holds hw_lock.
948  */
949 static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
950 {
951         struct ql3xxx_port_registers __iomem *port_regs =
952                         qdev->mem_map_registers;
953         u32 value;
954
955         if (enable)
956                 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
957         else
958                 value = (MAC_CONFIG_REG_SR << 16);
959
960         if (qdev->mac_index)
961                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
962         else
963                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
964 }
965
966 /*
967  * Caller holds hw_lock.
968  */
969 static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
970 {
971         struct ql3xxx_port_registers __iomem *port_regs =
972                         qdev->mem_map_registers;
973         u32 value;
974
975         if (enable)
976                 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
977         else
978                 value = (MAC_CONFIG_REG_GM << 16);
979
980         if (qdev->mac_index)
981                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
982         else
983                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
984 }
985
986 /*
987  * Caller holds hw_lock.
988  */
989 static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
990 {
991         struct ql3xxx_port_registers __iomem *port_regs =
992                         qdev->mem_map_registers;
993         u32 value;
994
995         if (enable)
996                 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
997         else
998                 value = (MAC_CONFIG_REG_FD << 16);
999
1000         if (qdev->mac_index)
1001                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1002         else
1003                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1004 }
1005
1006 /*
1007  * Caller holds hw_lock.
1008  */
1009 static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1010 {
1011         struct ql3xxx_port_registers __iomem *port_regs =
1012                         qdev->mem_map_registers;
1013         u32 value;
1014
1015         if (enable)
1016                 value =
1017                     ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1018                      ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1019         else
1020                 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1021
1022         if (qdev->mac_index)
1023                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1024         else
1025                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1026 }
1027
1028 /*
1029  * Caller holds hw_lock.
1030  */
1031 static int ql_is_fiber(struct ql3_adapter *qdev)
1032 {
1033         struct ql3xxx_port_registers __iomem *port_regs =
1034                         qdev->mem_map_registers;
1035         u32 bitToCheck = 0;
1036         u32 temp;
1037
1038         switch (qdev->mac_index) {
1039         case 0:
1040                 bitToCheck = PORT_STATUS_SM0;
1041                 break;
1042         case 1:
1043                 bitToCheck = PORT_STATUS_SM1;
1044                 break;
1045         }
1046
1047         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1048         return (temp & bitToCheck) != 0;
1049 }
1050
1051 static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1052 {
1053         u16 reg;
1054         ql_mii_read_reg(qdev, 0x00, &reg);
1055         return (reg & 0x1000) != 0;
1056 }
1057
1058 /*
1059  * Caller holds hw_lock.
1060  */
1061 static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1062 {
1063         struct ql3xxx_port_registers __iomem *port_regs =
1064                         qdev->mem_map_registers;
1065         u32 bitToCheck = 0;
1066         u32 temp;
1067
1068         switch (qdev->mac_index) {
1069         case 0:
1070                 bitToCheck = PORT_STATUS_AC0;
1071                 break;
1072         case 1:
1073                 bitToCheck = PORT_STATUS_AC1;
1074                 break;
1075         }
1076
1077         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1078         if (temp & bitToCheck) {
1079                 if (netif_msg_link(qdev))
1080                         printk(KERN_INFO PFX
1081                                "%s: Auto-Negotiate complete.\n",
1082                                qdev->ndev->name);
1083                 return 1;
1084         } else {
1085                 if (netif_msg_link(qdev))
1086                         printk(KERN_WARNING PFX
1087                                "%s: Auto-Negotiate incomplete.\n",
1088                                qdev->ndev->name);
1089                 return 0;
1090         }
1091 }
1092
1093 /*
1094  *  ql_is_neg_pause() returns 1 if pause was negotiated to be on
1095  */
1096 static int ql_is_neg_pause(struct ql3_adapter *qdev)
1097 {
1098         if (ql_is_fiber(qdev))
1099                 return ql_is_petbi_neg_pause(qdev);
1100         else
1101                 return ql_is_phy_neg_pause(qdev);
1102 }
1103
1104 static int ql_auto_neg_error(struct ql3_adapter *qdev)
1105 {
1106         struct ql3xxx_port_registers __iomem *port_regs =
1107                         qdev->mem_map_registers;
1108         u32 bitToCheck = 0;
1109         u32 temp;
1110
1111         switch (qdev->mac_index) {
1112         case 0:
1113                 bitToCheck = PORT_STATUS_AE0;
1114                 break;
1115         case 1:
1116                 bitToCheck = PORT_STATUS_AE1;
1117                 break;
1118         }
1119         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1120         return (temp & bitToCheck) != 0;
1121 }
1122
1123 static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1124 {
1125         if (ql_is_fiber(qdev))
1126                 return SPEED_1000;
1127         else
1128                 return ql_phy_get_speed(qdev);
1129 }
1130
1131 static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1132 {
1133         if (ql_is_fiber(qdev))
1134                 return 1;
1135         else
1136                 return ql_is_full_dup(qdev);
1137 }
1138
1139 /*
1140  * Caller holds hw_lock.
1141  */
1142 static int ql_link_down_detect(struct ql3_adapter *qdev)
1143 {
1144         struct ql3xxx_port_registers __iomem *port_regs =
1145                         qdev->mem_map_registers;
1146         u32 bitToCheck = 0;
1147         u32 temp;
1148
1149         switch (qdev->mac_index) {
1150         case 0:
1151                 bitToCheck = ISP_CONTROL_LINK_DN_0;
1152                 break;
1153         case 1:
1154                 bitToCheck = ISP_CONTROL_LINK_DN_1;
1155                 break;
1156         }
1157
1158         temp =
1159             ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1160         return (temp & bitToCheck) != 0;
1161 }
1162
1163 /*
1164  * Caller holds hw_lock.
1165  */
1166 static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1167 {
1168         struct ql3xxx_port_registers __iomem *port_regs =
1169                         qdev->mem_map_registers;
1170
1171         switch (qdev->mac_index) {
1172         case 0:
1173                 ql_write_common_reg(qdev,
1174                                     &port_regs->CommonRegs.ispControlStatus,
1175                                     (ISP_CONTROL_LINK_DN_0) |
1176                                     (ISP_CONTROL_LINK_DN_0 << 16));
1177                 break;
1178
1179         case 1:
1180                 ql_write_common_reg(qdev,
1181                                     &port_regs->CommonRegs.ispControlStatus,
1182                                     (ISP_CONTROL_LINK_DN_1) |
1183                                     (ISP_CONTROL_LINK_DN_1 << 16));
1184                 break;
1185
1186         default:
1187                 return 1;
1188         }
1189
1190         return 0;
1191 }
1192
1193 /*
1194  * Caller holds hw_lock.
1195  */
1196 static int ql_this_adapter_controls_port(struct ql3_adapter *qdev,
1197                                          u32 mac_index)
1198 {
1199         struct ql3xxx_port_registers __iomem *port_regs =
1200                         qdev->mem_map_registers;
1201         u32 bitToCheck = 0;
1202         u32 temp;
1203
1204         switch (mac_index) {
1205         case 0:
1206                 bitToCheck = PORT_STATUS_F1_ENABLED;
1207                 break;
1208         case 1:
1209                 bitToCheck = PORT_STATUS_F3_ENABLED;
1210                 break;
1211         default:
1212                 break;
1213         }
1214
1215         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1216         if (temp & bitToCheck) {
1217                 if (netif_msg_link(qdev))
1218                         printk(KERN_DEBUG PFX
1219                                "%s: is not link master.\n", qdev->ndev->name);
1220                 return 0;
1221         } else {
1222                 if (netif_msg_link(qdev))
1223                         printk(KERN_DEBUG PFX
1224                                "%s: is link master.\n", qdev->ndev->name);
1225                 return 1;
1226         }
1227 }
1228
1229 static void ql_phy_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
1230 {
1231         ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET, mac_index);
1232 }
1233
1234 static void ql_phy_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
1235 {
1236         u16 reg;
1237
1238         ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER,
1239                             PHY_NEG_PAUSE | PHY_NEG_ADV_SPEED | 1, mac_index);
1240
1241         ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, mac_index);
1242         ql_mii_write_reg_ex(qdev, CONTROL_REG, reg | PHY_CTRL_RESTART_NEG,
1243                             mac_index);
1244 }
1245
1246 static void ql_phy_init_ex(struct ql3_adapter *qdev, u32 mac_index)
1247 {
1248         ql_phy_reset_ex(qdev, mac_index);
1249         ql_phy_start_neg_ex(qdev, mac_index);
1250 }
1251
1252 /*
1253  * Caller holds hw_lock.
1254  */
1255 static u32 ql_get_link_state(struct ql3_adapter *qdev)
1256 {
1257         struct ql3xxx_port_registers __iomem *port_regs =
1258                         qdev->mem_map_registers;
1259         u32 bitToCheck = 0;
1260         u32 temp, linkState;
1261
1262         switch (qdev->mac_index) {
1263         case 0:
1264                 bitToCheck = PORT_STATUS_UP0;
1265                 break;
1266         case 1:
1267                 bitToCheck = PORT_STATUS_UP1;
1268                 break;
1269         }
1270         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1271         if (temp & bitToCheck) {
1272                 linkState = LS_UP;
1273         } else {
1274                 linkState = LS_DOWN;
1275                 if (netif_msg_link(qdev))
1276                         printk(KERN_WARNING PFX
1277                                "%s: Link is down.\n", qdev->ndev->name);
1278         }
1279         return linkState;
1280 }
1281
1282 static int ql_port_start(struct ql3_adapter *qdev)
1283 {
1284         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1285                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1286                          2) << 7))
1287                 return -1;
1288
1289         if (ql_is_fiber(qdev)) {
1290                 ql_petbi_init(qdev);
1291         } else {
1292                 /* Copper port */
1293                 ql_phy_init_ex(qdev, qdev->mac_index);
1294         }
1295
1296         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1297         return 0;
1298 }
1299
1300 static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1301 {
1302
1303         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1304                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1305                          2) << 7))
1306                 return -1;
1307
1308         if (!ql_auto_neg_error(qdev)) {
1309                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1310                         /* configure the MAC */
1311                         if (netif_msg_link(qdev))
1312                                 printk(KERN_DEBUG PFX
1313                                        "%s: Configuring link.\n",
1314                                        qdev->ndev->
1315                                        name);
1316                         ql_mac_cfg_soft_reset(qdev, 1);
1317                         ql_mac_cfg_gig(qdev,
1318                                        (ql_get_link_speed
1319                                         (qdev) ==
1320                                         SPEED_1000));
1321                         ql_mac_cfg_full_dup(qdev,
1322                                             ql_is_link_full_dup
1323                                             (qdev));
1324                         ql_mac_cfg_pause(qdev,
1325                                          ql_is_neg_pause
1326                                          (qdev));
1327                         ql_mac_cfg_soft_reset(qdev, 0);
1328
1329                         /* enable the MAC */
1330                         if (netif_msg_link(qdev))
1331                                 printk(KERN_DEBUG PFX
1332                                        "%s: Enabling mac.\n",
1333                                        qdev->ndev->
1334                                                name);
1335                         ql_mac_enable(qdev, 1);
1336                 }
1337
1338                 if (netif_msg_link(qdev))
1339                         printk(KERN_DEBUG PFX
1340                                "%s: Change port_link_state LS_DOWN to LS_UP.\n",
1341                                qdev->ndev->name);
1342                 qdev->port_link_state = LS_UP;
1343                 netif_start_queue(qdev->ndev);
1344                 netif_carrier_on(qdev->ndev);
1345                 if (netif_msg_link(qdev))
1346                         printk(KERN_INFO PFX
1347                                "%s: Link is up at %d Mbps, %s duplex.\n",
1348                                qdev->ndev->name,
1349                                ql_get_link_speed(qdev),
1350                                ql_is_link_full_dup(qdev)
1351                                ? "full" : "half");
1352
1353         } else {        /* Remote error detected */
1354
1355                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1356                         if (netif_msg_link(qdev))
1357                                 printk(KERN_DEBUG PFX
1358                                        "%s: Remote error detected. "
1359                                        "Calling ql_port_start().\n",
1360                                        qdev->ndev->
1361                                        name);
1362                         /*
1363                          * ql_port_start() is shared code and needs
1364                          * to lock the PHY on it's own.
1365                          */
1366                         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1367                         if(ql_port_start(qdev)) {/* Restart port */
1368                                 return -1;
1369                         } else
1370                                 return 0;
1371                 }
1372         }
1373         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1374         return 0;
1375 }
1376
1377 static void ql_link_state_machine(struct ql3_adapter *qdev)
1378 {
1379         u32 curr_link_state;
1380         unsigned long hw_flags;
1381
1382         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1383
1384         curr_link_state = ql_get_link_state(qdev);
1385
1386         if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
1387                 if (netif_msg_link(qdev))
1388                         printk(KERN_INFO PFX
1389                                "%s: Reset in progress, skip processing link "
1390                                "state.\n", qdev->ndev->name);
1391                 return;
1392         }
1393
1394         switch (qdev->port_link_state) {
1395         default:
1396                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1397                         ql_port_start(qdev);
1398                 }
1399                 qdev->port_link_state = LS_DOWN;
1400                 /* Fall Through */
1401
1402         case LS_DOWN:
1403                 if (netif_msg_link(qdev))
1404                         printk(KERN_DEBUG PFX
1405                                "%s: port_link_state = LS_DOWN.\n",
1406                                qdev->ndev->name);
1407                 if (curr_link_state == LS_UP) {
1408                         if (netif_msg_link(qdev))
1409                                 printk(KERN_DEBUG PFX
1410                                        "%s: curr_link_state = LS_UP.\n",
1411                                        qdev->ndev->name);
1412                         if (ql_is_auto_neg_complete(qdev))
1413                                 ql_finish_auto_neg(qdev);
1414
1415                         if (qdev->port_link_state == LS_UP)
1416                                 ql_link_down_detect_clear(qdev);
1417
1418                 }
1419                 break;
1420
1421         case LS_UP:
1422                 /*
1423                  * See if the link is currently down or went down and came
1424                  * back up
1425                  */
1426                 if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) {
1427                         if (netif_msg_link(qdev))
1428                                 printk(KERN_INFO PFX "%s: Link is down.\n",
1429                                        qdev->ndev->name);
1430                         qdev->port_link_state = LS_DOWN;
1431                 }
1432                 break;
1433         }
1434         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1435 }
1436
1437 /*
1438  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1439  */
1440 static void ql_get_phy_owner(struct ql3_adapter *qdev)
1441 {
1442         if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1443                 set_bit(QL_LINK_MASTER,&qdev->flags);
1444         else
1445                 clear_bit(QL_LINK_MASTER,&qdev->flags);
1446 }
1447
1448 /*
1449  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1450  */
1451 static void ql_init_scan_mode(struct ql3_adapter *qdev)
1452 {
1453         ql_mii_enable_scan_mode(qdev);
1454
1455         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1456                 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1457                         ql_petbi_init_ex(qdev, qdev->mac_index);
1458         } else {
1459                 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1460                         ql_phy_init_ex(qdev, qdev->mac_index);
1461         }
1462 }
1463
1464 /*
1465  * MII_Setup needs to be called before taking the PHY out of reset so that the
1466  * management interface clock speed can be set properly.  It would be better if
1467  * we had a way to disable MDC until after the PHY is out of reset, but we
1468  * don't have that capability.
1469  */
1470 static int ql_mii_setup(struct ql3_adapter *qdev)
1471 {
1472         u32 reg;
1473         struct ql3xxx_port_registers __iomem *port_regs =
1474                         qdev->mem_map_registers;
1475
1476         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1477                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1478                          2) << 7))
1479                 return -1;
1480
1481         if (qdev->device_id == QL3032_DEVICE_ID)
1482                 ql_write_page0_reg(qdev, 
1483                         &port_regs->macMIIMgmtControlReg, 0x0f00000);
1484
1485         /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1486         reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1487
1488         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1489                            reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1490
1491         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1492         return 0;
1493 }
1494
1495 static u32 ql_supported_modes(struct ql3_adapter *qdev)
1496 {
1497         u32 supported;
1498
1499         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1500                 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
1501                     | SUPPORTED_Autoneg;
1502         } else {
1503                 supported = SUPPORTED_10baseT_Half
1504                     | SUPPORTED_10baseT_Full
1505                     | SUPPORTED_100baseT_Half
1506                     | SUPPORTED_100baseT_Full
1507                     | SUPPORTED_1000baseT_Half
1508                     | SUPPORTED_1000baseT_Full
1509                     | SUPPORTED_Autoneg | SUPPORTED_TP;
1510         }
1511
1512         return supported;
1513 }
1514
1515 static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1516 {
1517         int status;
1518         unsigned long hw_flags;
1519         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1520         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1521                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1522                          2) << 7))
1523                 return 0;
1524         status = ql_is_auto_cfg(qdev);
1525         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1526         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1527         return status;
1528 }
1529
1530 static u32 ql_get_speed(struct ql3_adapter *qdev)
1531 {
1532         u32 status;
1533         unsigned long hw_flags;
1534         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1535         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1536                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1537                          2) << 7))
1538                 return 0;
1539         status = ql_get_link_speed(qdev);
1540         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1541         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1542         return status;
1543 }
1544
1545 static int ql_get_full_dup(struct ql3_adapter *qdev)
1546 {
1547         int status;
1548         unsigned long hw_flags;
1549         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1550         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1551                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1552                          2) << 7))
1553                 return 0;
1554         status = ql_is_link_full_dup(qdev);
1555         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1556         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1557         return status;
1558 }
1559
1560
1561 static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1562 {
1563         struct ql3_adapter *qdev = netdev_priv(ndev);
1564
1565         ecmd->transceiver = XCVR_INTERNAL;
1566         ecmd->supported = ql_supported_modes(qdev);
1567
1568         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1569                 ecmd->port = PORT_FIBRE;
1570         } else {
1571                 ecmd->port = PORT_TP;
1572                 ecmd->phy_address = qdev->PHYAddr;
1573         }
1574         ecmd->advertising = ql_supported_modes(qdev);
1575         ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1576         ecmd->speed = ql_get_speed(qdev);
1577         ecmd->duplex = ql_get_full_dup(qdev);
1578         return 0;
1579 }
1580
1581 static void ql_get_drvinfo(struct net_device *ndev,
1582                            struct ethtool_drvinfo *drvinfo)
1583 {
1584         struct ql3_adapter *qdev = netdev_priv(ndev);
1585         strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
1586         strncpy(drvinfo->version, ql3xxx_driver_version, 32);
1587         strncpy(drvinfo->fw_version, "N/A", 32);
1588         strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
1589         drvinfo->n_stats = 0;
1590         drvinfo->testinfo_len = 0;
1591         drvinfo->regdump_len = 0;
1592         drvinfo->eedump_len = 0;
1593 }
1594
1595 static u32 ql_get_msglevel(struct net_device *ndev)
1596 {
1597         struct ql3_adapter *qdev = netdev_priv(ndev);
1598         return qdev->msg_enable;
1599 }
1600
1601 static void ql_set_msglevel(struct net_device *ndev, u32 value)
1602 {
1603         struct ql3_adapter *qdev = netdev_priv(ndev);
1604         qdev->msg_enable = value;
1605 }
1606
1607 static const struct ethtool_ops ql3xxx_ethtool_ops = {
1608         .get_settings = ql_get_settings,
1609         .get_drvinfo = ql_get_drvinfo,
1610         .get_perm_addr = ethtool_op_get_perm_addr,
1611         .get_link = ethtool_op_get_link,
1612         .get_msglevel = ql_get_msglevel,
1613         .set_msglevel = ql_set_msglevel,
1614 };
1615
1616 static int ql_populate_free_queue(struct ql3_adapter *qdev)
1617 {
1618         struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1619         u64 map;
1620
1621         while (lrg_buf_cb) {
1622                 if (!lrg_buf_cb->skb) {
1623                         lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
1624                                                            qdev->lrg_buffer_len);
1625                         if (unlikely(!lrg_buf_cb->skb)) {
1626                                 printk(KERN_DEBUG PFX
1627                                        "%s: Failed netdev_alloc_skb().\n",
1628                                        qdev->ndev->name);
1629                                 break;
1630                         } else {
1631                                 /*
1632                                  * We save some space to copy the ethhdr from
1633                                  * first buffer
1634                                  */
1635                                 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1636                                 map = pci_map_single(qdev->pdev,
1637                                                      lrg_buf_cb->skb->data,
1638                                                      qdev->lrg_buffer_len -
1639                                                      QL_HEADER_SPACE,
1640                                                      PCI_DMA_FROMDEVICE);
1641                                 lrg_buf_cb->buf_phy_addr_low =
1642                                     cpu_to_le32(LS_64BITS(map));
1643                                 lrg_buf_cb->buf_phy_addr_high =
1644                                     cpu_to_le32(MS_64BITS(map));
1645                                 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1646                                 pci_unmap_len_set(lrg_buf_cb, maplen,
1647                                                   qdev->lrg_buffer_len -
1648                                                   QL_HEADER_SPACE);
1649                                 --qdev->lrg_buf_skb_check;
1650                                 if (!qdev->lrg_buf_skb_check)
1651                                         return 1;
1652                         }
1653                 }
1654                 lrg_buf_cb = lrg_buf_cb->next;
1655         }
1656         return 0;
1657 }
1658
1659 /*
1660  * Caller holds hw_lock.
1661  */
1662 static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1663 {
1664         struct bufq_addr_element *lrg_buf_q_ele;
1665         int i;
1666         struct ql_rcv_buf_cb *lrg_buf_cb;
1667         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1668
1669         if ((qdev->lrg_buf_free_count >= 8)
1670             && (qdev->lrg_buf_release_cnt >= 16)) {
1671
1672                 if (qdev->lrg_buf_skb_check)
1673                         if (!ql_populate_free_queue(qdev))
1674                                 return;
1675
1676                 lrg_buf_q_ele = qdev->lrg_buf_next_free;
1677
1678                 while ((qdev->lrg_buf_release_cnt >= 16)
1679                        && (qdev->lrg_buf_free_count >= 8)) {
1680
1681                         for (i = 0; i < 8; i++) {
1682                                 lrg_buf_cb =
1683                                     ql_get_from_lrg_buf_free_list(qdev);
1684                                 lrg_buf_q_ele->addr_high =
1685                                     lrg_buf_cb->buf_phy_addr_high;
1686                                 lrg_buf_q_ele->addr_low =
1687                                     lrg_buf_cb->buf_phy_addr_low;
1688                                 lrg_buf_q_ele++;
1689
1690                                 qdev->lrg_buf_release_cnt--;
1691                         }
1692
1693                         qdev->lrg_buf_q_producer_index++;
1694
1695                         if (qdev->lrg_buf_q_producer_index == NUM_LBUFQ_ENTRIES)
1696                                 qdev->lrg_buf_q_producer_index = 0;
1697
1698                         if (qdev->lrg_buf_q_producer_index ==
1699                             (NUM_LBUFQ_ENTRIES - 1)) {
1700                                 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
1701                         }
1702                 }
1703
1704                 qdev->lrg_buf_next_free = lrg_buf_q_ele;
1705
1706                 ql_write_common_reg(qdev,
1707                                     &port_regs->CommonRegs.
1708                                     rxLargeQProducerIndex,
1709                                     qdev->lrg_buf_q_producer_index);
1710         }
1711 }
1712
1713 static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
1714                                    struct ob_mac_iocb_rsp *mac_rsp)
1715 {
1716         struct ql_tx_buf_cb *tx_cb;
1717         int i;
1718
1719         tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
1720         pci_unmap_single(qdev->pdev,
1721                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
1722                          pci_unmap_len(&tx_cb->map[0], maplen),
1723                          PCI_DMA_TODEVICE);
1724         tx_cb->seg_count--;
1725         if (tx_cb->seg_count) {
1726                 for (i = 1; i < tx_cb->seg_count; i++) {
1727                         pci_unmap_page(qdev->pdev,
1728                                        pci_unmap_addr(&tx_cb->map[i],
1729                                                       mapaddr),
1730                                        pci_unmap_len(&tx_cb->map[i], maplen),
1731                                        PCI_DMA_TODEVICE);
1732                 }
1733         }
1734         qdev->stats.tx_packets++;
1735         qdev->stats.tx_bytes += tx_cb->skb->len;
1736         dev_kfree_skb_irq(tx_cb->skb);
1737         tx_cb->skb = NULL;
1738         atomic_inc(&qdev->tx_count);
1739 }
1740
1741 /*
1742  * The difference between 3022 and 3032 for inbound completions:
1743  * 3022 uses two buffers per completion.  The first buffer contains 
1744  * (some) header info, the second the remainder of the headers plus 
1745  * the data.  For this chip we reserve some space at the top of the 
1746  * receive buffer so that the header info in buffer one can be 
1747  * prepended to the buffer two.  Buffer two is the sent up while 
1748  * buffer one is returned to the hardware to be reused.
1749  * 3032 receives all of it's data and headers in one buffer for a 
1750  * simpler process.  3032 also supports checksum verification as
1751  * can be seen in ql_process_macip_rx_intr().
1752  */
1753 static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
1754                                    struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
1755 {
1756         long int offset;
1757         u32 lrg_buf_phy_addr_low = 0;
1758         struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1759         struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
1760         u32 *curr_ial_ptr;
1761         struct sk_buff *skb;
1762         u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
1763
1764         /*
1765          * Get the inbound address list (small buffer).
1766          */
1767         offset = qdev->small_buf_index * QL_SMALL_BUFFER_SIZE;
1768         if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1769                 qdev->small_buf_index = 0;
1770
1771         curr_ial_ptr = (u32 *) (qdev->small_buf_virt_addr + offset);
1772         qdev->last_rsp_offset = qdev->small_buf_phy_addr_low + offset;
1773         qdev->small_buf_release_cnt++;
1774
1775         if (qdev->device_id == QL3022_DEVICE_ID) {
1776                 /* start of first buffer (3022 only) */
1777                 lrg_buf_phy_addr_low = le32_to_cpu(*curr_ial_ptr);
1778                 lrg_buf_cb1 = &qdev->lrg_buf[qdev->lrg_buf_index];
1779                 qdev->lrg_buf_release_cnt++;
1780                 if (++qdev->lrg_buf_index == NUM_LARGE_BUFFERS) {
1781                         qdev->lrg_buf_index = 0;
1782                 }
1783                 curr_ial_ptr++; /* 64-bit pointers require two incs. */
1784                 curr_ial_ptr++;
1785         }
1786
1787         /* start of second buffer */
1788         lrg_buf_phy_addr_low = le32_to_cpu(*curr_ial_ptr);
1789         lrg_buf_cb2 = &qdev->lrg_buf[qdev->lrg_buf_index];
1790
1791         /*
1792          * Second buffer gets sent up the stack.
1793          */
1794         qdev->lrg_buf_release_cnt++;
1795         if (++qdev->lrg_buf_index == NUM_LARGE_BUFFERS)
1796                 qdev->lrg_buf_index = 0;
1797         skb = lrg_buf_cb2->skb;
1798
1799         qdev->stats.rx_packets++;
1800         qdev->stats.rx_bytes += length;
1801
1802         skb_put(skb, length);
1803         pci_unmap_single(qdev->pdev,
1804                          pci_unmap_addr(lrg_buf_cb2, mapaddr),
1805                          pci_unmap_len(lrg_buf_cb2, maplen),
1806                          PCI_DMA_FROMDEVICE);
1807         prefetch(skb->data);
1808         skb->dev = qdev->ndev;
1809         skb->ip_summed = CHECKSUM_NONE;
1810         skb->protocol = eth_type_trans(skb, qdev->ndev);
1811
1812         netif_receive_skb(skb);
1813         qdev->ndev->last_rx = jiffies;
1814         lrg_buf_cb2->skb = NULL;
1815
1816         if (qdev->device_id == QL3022_DEVICE_ID)
1817                 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
1818         ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1819 }
1820
1821 static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
1822                                      struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
1823 {
1824         long int offset;
1825         u32 lrg_buf_phy_addr_low = 0;
1826         struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1827         struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
1828         u32 *curr_ial_ptr;
1829         struct sk_buff *skb1 = NULL, *skb2;
1830         struct net_device *ndev = qdev->ndev;
1831         u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
1832         u16 size = 0;
1833
1834         /*
1835          * Get the inbound address list (small buffer).
1836          */
1837
1838         offset = qdev->small_buf_index * QL_SMALL_BUFFER_SIZE;
1839         if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1840                 qdev->small_buf_index = 0;
1841         curr_ial_ptr = (u32 *) (qdev->small_buf_virt_addr + offset);
1842         qdev->last_rsp_offset = qdev->small_buf_phy_addr_low + offset;
1843         qdev->small_buf_release_cnt++;
1844
1845         if (qdev->device_id == QL3022_DEVICE_ID) {
1846                 /* start of first buffer on 3022 */
1847                 lrg_buf_phy_addr_low = le32_to_cpu(*curr_ial_ptr);
1848                 lrg_buf_cb1 = &qdev->lrg_buf[qdev->lrg_buf_index];
1849                 qdev->lrg_buf_release_cnt++;
1850                 if (++qdev->lrg_buf_index == NUM_LARGE_BUFFERS)
1851                         qdev->lrg_buf_index = 0;
1852                 skb1 = lrg_buf_cb1->skb;
1853                 curr_ial_ptr++; /* 64-bit pointers require two incs. */
1854                 curr_ial_ptr++;
1855                 size = ETH_HLEN;
1856                 if (*((u16 *) skb1->data) != 0xFFFF)
1857                         size += VLAN_ETH_HLEN - ETH_HLEN;
1858         }
1859
1860         /* start of second buffer */
1861         lrg_buf_phy_addr_low = le32_to_cpu(*curr_ial_ptr);
1862         lrg_buf_cb2 = &qdev->lrg_buf[qdev->lrg_buf_index];
1863         skb2 = lrg_buf_cb2->skb;
1864         qdev->lrg_buf_release_cnt++;
1865         if (++qdev->lrg_buf_index == NUM_LARGE_BUFFERS)
1866                 qdev->lrg_buf_index = 0;
1867
1868         skb_put(skb2, length);  /* Just the second buffer length here. */
1869         pci_unmap_single(qdev->pdev,
1870                          pci_unmap_addr(lrg_buf_cb2, mapaddr),
1871                          pci_unmap_len(lrg_buf_cb2, maplen),
1872                          PCI_DMA_FROMDEVICE);
1873         prefetch(skb2->data);
1874
1875         skb2->ip_summed = CHECKSUM_NONE;
1876         if (qdev->device_id == QL3022_DEVICE_ID) {
1877                 /*
1878                  * Copy the ethhdr from first buffer to second. This
1879                  * is necessary for 3022 IP completions.
1880                  */
1881                 memcpy(skb_push(skb2, size), skb1->data + VLAN_ID_LEN, size);
1882         } else {
1883                 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
1884                 if (checksum & 
1885                         (IB_IP_IOCB_RSP_3032_ICE | 
1886                          IB_IP_IOCB_RSP_3032_CE | 
1887                          IB_IP_IOCB_RSP_3032_NUC)) {
1888                         printk(KERN_ERR
1889                                "%s: Bad checksum for this %s packet, checksum = %x.\n",
1890                                __func__,
1891                                ((checksum & 
1892                                 IB_IP_IOCB_RSP_3032_TCP) ? "TCP" :
1893                                 "UDP"),checksum);
1894                 } else if (checksum & IB_IP_IOCB_RSP_3032_TCP) {
1895                         skb2->ip_summed = CHECKSUM_UNNECESSARY;
1896                 } 
1897         }
1898         skb2->dev = qdev->ndev;
1899         skb2->protocol = eth_type_trans(skb2, qdev->ndev);
1900
1901         netif_receive_skb(skb2);
1902         qdev->stats.rx_packets++;
1903         qdev->stats.rx_bytes += length;
1904         ndev->last_rx = jiffies;
1905         lrg_buf_cb2->skb = NULL;
1906
1907         if (qdev->device_id == QL3022_DEVICE_ID)
1908                 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
1909         ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1910 }
1911
1912 static int ql_tx_rx_clean(struct ql3_adapter *qdev,
1913                           int *tx_cleaned, int *rx_cleaned, int work_to_do)
1914 {
1915         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1916         struct net_rsp_iocb *net_rsp;
1917         struct net_device *ndev = qdev->ndev;
1918         unsigned long hw_flags;
1919
1920         /* While there are entries in the completion queue. */
1921         while ((cpu_to_le32(*(qdev->prsp_producer_index)) !=
1922                 qdev->rsp_consumer_index) && (*rx_cleaned < work_to_do)) {
1923
1924                 net_rsp = qdev->rsp_current;
1925                 switch (net_rsp->opcode) {
1926
1927                 case OPCODE_OB_MAC_IOCB_FN0:
1928                 case OPCODE_OB_MAC_IOCB_FN2:
1929                         ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
1930                                                net_rsp);
1931                         (*tx_cleaned)++;
1932                         break;
1933
1934                 case OPCODE_IB_MAC_IOCB:
1935                 case OPCODE_IB_3032_MAC_IOCB:
1936                         ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
1937                                                net_rsp);
1938                         (*rx_cleaned)++;
1939                         break;
1940
1941                 case OPCODE_IB_IP_IOCB:
1942                 case OPCODE_IB_3032_IP_IOCB:
1943                         ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
1944                                                  net_rsp);
1945                         (*rx_cleaned)++;
1946                         break;
1947                 default:
1948                         {
1949                                 u32 *tmp = (u32 *) net_rsp;
1950                                 printk(KERN_ERR PFX
1951                                        "%s: Hit default case, not "
1952                                        "handled!\n"
1953                                        "        dropping the packet, opcode = "
1954                                        "%x.\n",
1955                                        ndev->name, net_rsp->opcode);
1956                                 printk(KERN_ERR PFX
1957                                        "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
1958                                        (unsigned long int)tmp[0],
1959                                        (unsigned long int)tmp[1],
1960                                        (unsigned long int)tmp[2],
1961                                        (unsigned long int)tmp[3]);
1962                         }
1963                 }
1964
1965                 qdev->rsp_consumer_index++;
1966
1967                 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
1968                         qdev->rsp_consumer_index = 0;
1969                         qdev->rsp_current = qdev->rsp_q_virt_addr;
1970                 } else {
1971                         qdev->rsp_current++;
1972                 }
1973         }
1974
1975         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1976
1977         ql_update_lrg_bufq_prod_index(qdev);
1978
1979         if (qdev->small_buf_release_cnt >= 16) {
1980                 while (qdev->small_buf_release_cnt >= 16) {
1981                         qdev->small_buf_q_producer_index++;
1982
1983                         if (qdev->small_buf_q_producer_index ==
1984                             NUM_SBUFQ_ENTRIES)
1985                                 qdev->small_buf_q_producer_index = 0;
1986                         qdev->small_buf_release_cnt -= 8;
1987                 }
1988
1989                 ql_write_common_reg(qdev,
1990                                     &port_regs->CommonRegs.
1991                                     rxSmallQProducerIndex,
1992                                     qdev->small_buf_q_producer_index);
1993         }
1994
1995         ql_write_common_reg(qdev,
1996                             &port_regs->CommonRegs.rspQConsumerIndex,
1997                             qdev->rsp_consumer_index);
1998         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1999
2000         if (unlikely(netif_queue_stopped(qdev->ndev))) {
2001                 if (netif_queue_stopped(qdev->ndev) &&
2002                     (atomic_read(&qdev->tx_count) > (NUM_REQ_Q_ENTRIES / 4)))
2003                         netif_wake_queue(qdev->ndev);
2004         }
2005
2006         return *tx_cleaned + *rx_cleaned;
2007 }
2008
2009 static int ql_poll(struct net_device *ndev, int *budget)
2010 {
2011         struct ql3_adapter *qdev = netdev_priv(ndev);
2012         int work_to_do = min(*budget, ndev->quota);
2013         int rx_cleaned = 0, tx_cleaned = 0;
2014
2015         if (!netif_carrier_ok(ndev))
2016                 goto quit_polling;
2017
2018         ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, work_to_do);
2019         *budget -= rx_cleaned;
2020         ndev->quota -= rx_cleaned;
2021
2022         if ((!tx_cleaned && !rx_cleaned) || !netif_running(ndev)) {
2023 quit_polling:
2024                 netif_rx_complete(ndev);
2025                 ql_enable_interrupts(qdev);
2026                 return 0;
2027         }
2028         return 1;
2029 }
2030
2031 static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2032 {
2033
2034         struct net_device *ndev = dev_id;
2035         struct ql3_adapter *qdev = netdev_priv(ndev);
2036         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2037         u32 value;
2038         int handled = 1;
2039         u32 var;
2040
2041         port_regs = qdev->mem_map_registers;
2042
2043         value =
2044             ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
2045
2046         if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2047                 spin_lock(&qdev->adapter_lock);
2048                 netif_stop_queue(qdev->ndev);
2049                 netif_carrier_off(qdev->ndev);
2050                 ql_disable_interrupts(qdev);
2051                 qdev->port_link_state = LS_DOWN;
2052                 set_bit(QL_RESET_ACTIVE,&qdev->flags) ;
2053
2054                 if (value & ISP_CONTROL_FE) {
2055                         /*
2056                          * Chip Fatal Error.
2057                          */
2058                         var =
2059                             ql_read_page0_reg_l(qdev,
2060                                               &port_regs->PortFatalErrStatus);
2061                         printk(KERN_WARNING PFX
2062                                "%s: Resetting chip. PortFatalErrStatus "
2063                                "register = 0x%x\n", ndev->name, var);
2064                         set_bit(QL_RESET_START,&qdev->flags) ;
2065                 } else {
2066                         /*
2067                          * Soft Reset Requested.
2068                          */
2069                         set_bit(QL_RESET_PER_SCSI,&qdev->flags) ;
2070                         printk(KERN_ERR PFX
2071                                "%s: Another function issued a reset to the "
2072                                "chip. ISR value = %x.\n", ndev->name, value);
2073                 }
2074                 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2075                 spin_unlock(&qdev->adapter_lock);
2076         } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2077                 ql_disable_interrupts(qdev);
2078                 if (likely(netif_rx_schedule_prep(ndev)))
2079                         __netif_rx_schedule(ndev);
2080                 else
2081                         ql_enable_interrupts(qdev);
2082         } else {
2083                 return IRQ_NONE;
2084         }
2085
2086         return IRQ_RETVAL(handled);
2087 }
2088
2089 /*
2090  * Get the total number of segments needed for the 
2091  * given number of fragments.  This is necessary because
2092  * outbound address lists (OAL) will be used when more than
2093  * two frags are given.  Each address list has 5 addr/len 
2094  * pairs.  The 5th pair in each AOL is used to  point to
2095  * the next AOL if more frags are coming.  
2096  * That is why the frags:segment count  ratio is not linear.
2097  */
2098 static int ql_get_seg_count(unsigned short frags)
2099 {
2100         switch(frags) {
2101         case 0: return 1;       /* just the skb->data seg */
2102         case 1: return 2;       /* skb->data + 1 frag */
2103         case 2: return 3;       /* skb->data + 2 frags */
2104         case 3: return 5;       /* skb->data + 1 frag + 1 AOL containting 2 frags */
2105         case 4: return 6;
2106         case 5: return 7;
2107         case 6: return 8;
2108         case 7: return 10;
2109         case 8: return 11;
2110         case 9: return 12;
2111         case 10: return 13;
2112         case 11: return 15;
2113         case 12: return 16;
2114         case 13: return 17;
2115         case 14: return 18;
2116         case 15: return 20;
2117         case 16: return 21;
2118         case 17: return 22;
2119         case 18: return 23;
2120         }
2121         return -1;
2122 }
2123
2124 static void ql_hw_csum_setup(struct sk_buff *skb,
2125                              struct ob_mac_iocb_req *mac_iocb_ptr)
2126 {
2127         struct ethhdr *eth;
2128         struct iphdr *ip = NULL;
2129         u8 offset = ETH_HLEN;
2130
2131         eth = (struct ethhdr *)(skb->data);
2132
2133         if (eth->h_proto == __constant_htons(ETH_P_IP)) {
2134                 ip = (struct iphdr *)&skb->data[ETH_HLEN];
2135         } else if (eth->h_proto == htons(ETH_P_8021Q) &&
2136                    ((struct vlan_ethhdr *)skb->data)->
2137                    h_vlan_encapsulated_proto == __constant_htons(ETH_P_IP)) {
2138                 ip = (struct iphdr *)&skb->data[VLAN_ETH_HLEN];
2139                 offset = VLAN_ETH_HLEN;
2140         }
2141
2142         if (ip) {
2143                 if (ip->protocol == IPPROTO_TCP) {
2144                         mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC;
2145                         mac_iocb_ptr->ip_hdr_off = offset;
2146                         mac_iocb_ptr->ip_hdr_len = ip->ihl;
2147                 } else if (ip->protocol == IPPROTO_UDP) {
2148                         mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC;
2149                         mac_iocb_ptr->ip_hdr_off = offset;
2150                         mac_iocb_ptr->ip_hdr_len = ip->ihl;
2151                 }
2152         }
2153 }
2154
2155 /*
2156  * The difference between 3022 and 3032 sends:
2157  * 3022 only supports a simple single segment transmission.
2158  * 3032 supports checksumming and scatter/gather lists (fragments).
2159  * The 3032 supports sglists by using the 3 addr/len pairs (ALP) 
2160  * in the IOCB plus a chain of outbound address lists (OAL) that 
2161  * each contain 5 ALPs.  The last ALP of the IOCB (3rd) or OAL (5th) 
2162  * will used to point to an OAL when more ALP entries are required.  
2163  * The IOCB is always the top of the chain followed by one or more 
2164  * OALs (when necessary).
2165  */
2166 static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev)
2167 {
2168         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
2169         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2170         struct ql_tx_buf_cb *tx_cb;
2171         u32 tot_len = skb->len;
2172         struct oal *oal;
2173         struct oal_entry *oal_entry;
2174         int len;
2175         struct ob_mac_iocb_req *mac_iocb_ptr;
2176         u64 map;
2177         int seg_cnt, seg = 0;
2178         int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2179
2180         if (unlikely(atomic_read(&qdev->tx_count) < 2)) {
2181                 if (!netif_queue_stopped(ndev))
2182                         netif_stop_queue(ndev);
2183                 return NETDEV_TX_BUSY;
2184         }
2185         tx_cb = &qdev->tx_buf[qdev->req_producer_index] ;
2186         seg_cnt = tx_cb->seg_count = ql_get_seg_count((skb_shinfo(skb)->nr_frags));
2187         if(seg_cnt == -1) {
2188                 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2189                 return NETDEV_TX_OK;
2190
2191         }
2192         mac_iocb_ptr = tx_cb->queue_entry;
2193         mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2194         mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2195         mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2196         mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2197         tx_cb->skb = skb;
2198         if (skb->ip_summed == CHECKSUM_PARTIAL)
2199                 ql_hw_csum_setup(skb, mac_iocb_ptr);
2200         len = skb_headlen(skb);
2201         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
2202         oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2203         oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2204         oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2205         oal_entry->len = cpu_to_le32(len);
2206         pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2207         pci_unmap_len_set(&tx_cb->map[seg], maplen, len);
2208         seg++;
2209
2210         if (!skb_shinfo(skb)->nr_frags) {
2211                 /* Terminate the last segment. */
2212                 oal_entry->len =
2213                     cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2214         } else {
2215                 int i;
2216                 oal = tx_cb->oal;
2217                 for (i=0; i<frag_cnt; i++,seg++) {
2218                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2219                         oal_entry++;
2220                         if ((seg == 2 && seg_cnt > 3) ||        /* Check for continuation */
2221                             (seg == 7 && seg_cnt > 8) ||        /* requirements. It's strange */
2222                             (seg == 12 && seg_cnt > 13) ||      /* but necessary. */
2223                             (seg == 17 && seg_cnt > 18)) {
2224                                 /* Continuation entry points to outbound address list. */
2225                                 map = pci_map_single(qdev->pdev, oal,
2226                                                      sizeof(struct oal),
2227                                                      PCI_DMA_TODEVICE);
2228                                 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2229                                 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2230                                 oal_entry->len =
2231                                     cpu_to_le32(sizeof(struct oal) |
2232                                                 OAL_CONT_ENTRY);
2233                                 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr,
2234                                                    map);
2235                                 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2236                                                   len);
2237                                 oal_entry = (struct oal_entry *)oal;
2238                                 oal++;
2239                                 seg++;
2240                         }
2241
2242                         map =
2243                             pci_map_page(qdev->pdev, frag->page,
2244                                          frag->page_offset, frag->size,
2245                                          PCI_DMA_TODEVICE);
2246                         oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2247                         oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2248                         oal_entry->len = cpu_to_le32(frag->size);
2249                         pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2250                         pci_unmap_len_set(&tx_cb->map[seg], maplen,
2251                                           frag->size);
2252                 }
2253                 /* Terminate the last segment. */
2254                 oal_entry->len =
2255                     cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2256         }
2257         wmb();
2258         qdev->req_producer_index++;
2259         if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2260                 qdev->req_producer_index = 0;
2261         wmb();
2262         ql_write_common_reg_l(qdev,
2263                             &port_regs->CommonRegs.reqQProducerIndex,
2264                             qdev->req_producer_index);
2265
2266         ndev->trans_start = jiffies;
2267         if (netif_msg_tx_queued(qdev))
2268                 printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n",
2269                        ndev->name, qdev->req_producer_index, skb->len);
2270
2271         atomic_dec(&qdev->tx_count);
2272         return NETDEV_TX_OK;
2273 }
2274
2275 static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2276 {
2277         qdev->req_q_size =
2278             (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2279
2280         qdev->req_q_virt_addr =
2281             pci_alloc_consistent(qdev->pdev,
2282                                  (size_t) qdev->req_q_size,
2283                                  &qdev->req_q_phy_addr);
2284
2285         if ((qdev->req_q_virt_addr == NULL) ||
2286             LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2287                 printk(KERN_ERR PFX "%s: reqQ failed.\n",
2288                        qdev->ndev->name);
2289                 return -ENOMEM;
2290         }
2291
2292         qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2293
2294         qdev->rsp_q_virt_addr =
2295             pci_alloc_consistent(qdev->pdev,
2296                                  (size_t) qdev->rsp_q_size,
2297                                  &qdev->rsp_q_phy_addr);
2298
2299         if ((qdev->rsp_q_virt_addr == NULL) ||
2300             LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2301                 printk(KERN_ERR PFX
2302                        "%s: rspQ allocation failed\n",
2303                        qdev->ndev->name);
2304                 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2305                                     qdev->req_q_virt_addr,
2306                                     qdev->req_q_phy_addr);
2307                 return -ENOMEM;
2308         }
2309
2310         set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2311
2312         return 0;
2313 }
2314
2315 static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2316 {
2317         if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) {
2318                 printk(KERN_INFO PFX
2319                        "%s: Already done.\n", qdev->ndev->name);
2320                 return;
2321         }
2322
2323         pci_free_consistent(qdev->pdev,
2324                             qdev->req_q_size,
2325                             qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2326
2327         qdev->req_q_virt_addr = NULL;
2328
2329         pci_free_consistent(qdev->pdev,
2330                             qdev->rsp_q_size,
2331                             qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2332
2333         qdev->rsp_q_virt_addr = NULL;
2334
2335         clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2336 }
2337
2338 static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2339 {
2340         /* Create Large Buffer Queue */
2341         qdev->lrg_buf_q_size =
2342             NUM_LBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2343         if (qdev->lrg_buf_q_size < PAGE_SIZE)
2344                 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2345         else
2346                 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2347
2348         qdev->lrg_buf_q_alloc_virt_addr =
2349             pci_alloc_consistent(qdev->pdev,
2350                                  qdev->lrg_buf_q_alloc_size,
2351                                  &qdev->lrg_buf_q_alloc_phy_addr);
2352
2353         if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2354                 printk(KERN_ERR PFX
2355                        "%s: lBufQ failed\n", qdev->ndev->name);
2356                 return -ENOMEM;
2357         }
2358         qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2359         qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2360
2361         /* Create Small Buffer Queue */
2362         qdev->small_buf_q_size =
2363             NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2364         if (qdev->small_buf_q_size < PAGE_SIZE)
2365                 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2366         else
2367                 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2368
2369         qdev->small_buf_q_alloc_virt_addr =
2370             pci_alloc_consistent(qdev->pdev,
2371                                  qdev->small_buf_q_alloc_size,
2372                                  &qdev->small_buf_q_alloc_phy_addr);
2373
2374         if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2375                 printk(KERN_ERR PFX
2376                        "%s: Small Buffer Queue allocation failed.\n",
2377                        qdev->ndev->name);
2378                 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2379                                     qdev->lrg_buf_q_alloc_virt_addr,
2380                                     qdev->lrg_buf_q_alloc_phy_addr);
2381                 return -ENOMEM;
2382         }
2383
2384         qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2385         qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2386         set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2387         return 0;
2388 }
2389
2390 static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2391 {
2392         if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) {
2393                 printk(KERN_INFO PFX
2394                        "%s: Already done.\n", qdev->ndev->name);
2395                 return;
2396         }
2397
2398         pci_free_consistent(qdev->pdev,
2399                             qdev->lrg_buf_q_alloc_size,
2400                             qdev->lrg_buf_q_alloc_virt_addr,
2401                             qdev->lrg_buf_q_alloc_phy_addr);
2402
2403         qdev->lrg_buf_q_virt_addr = NULL;
2404
2405         pci_free_consistent(qdev->pdev,
2406                             qdev->small_buf_q_alloc_size,
2407                             qdev->small_buf_q_alloc_virt_addr,
2408                             qdev->small_buf_q_alloc_phy_addr);
2409
2410         qdev->small_buf_q_virt_addr = NULL;
2411
2412         clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2413 }
2414
2415 static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2416 {
2417         int i;
2418         struct bufq_addr_element *small_buf_q_entry;
2419
2420         /* Currently we allocate on one of memory and use it for smallbuffers */
2421         qdev->small_buf_total_size =
2422             (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2423              QL_SMALL_BUFFER_SIZE);
2424
2425         qdev->small_buf_virt_addr =
2426             pci_alloc_consistent(qdev->pdev,
2427                                  qdev->small_buf_total_size,
2428                                  &qdev->small_buf_phy_addr);
2429
2430         if (qdev->small_buf_virt_addr == NULL) {
2431                 printk(KERN_ERR PFX
2432                        "%s: Failed to get small buffer memory.\n",
2433                        qdev->ndev->name);
2434                 return -ENOMEM;
2435         }
2436
2437         qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2438         qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2439
2440         small_buf_q_entry = qdev->small_buf_q_virt_addr;
2441
2442         qdev->last_rsp_offset = qdev->small_buf_phy_addr_low;
2443
2444         /* Initialize the small buffer queue. */
2445         for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2446                 small_buf_q_entry->addr_high =
2447                     cpu_to_le32(qdev->small_buf_phy_addr_high);
2448                 small_buf_q_entry->addr_low =
2449                     cpu_to_le32(qdev->small_buf_phy_addr_low +
2450                                 (i * QL_SMALL_BUFFER_SIZE));
2451                 small_buf_q_entry++;
2452         }
2453         qdev->small_buf_index = 0;
2454         set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags);
2455         return 0;
2456 }
2457
2458 static void ql_free_small_buffers(struct ql3_adapter *qdev)
2459 {
2460         if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) {
2461                 printk(KERN_INFO PFX
2462                        "%s: Already done.\n", qdev->ndev->name);
2463                 return;
2464         }
2465         if (qdev->small_buf_virt_addr != NULL) {
2466                 pci_free_consistent(qdev->pdev,
2467                                     qdev->small_buf_total_size,
2468                                     qdev->small_buf_virt_addr,
2469                                     qdev->small_buf_phy_addr);
2470
2471                 qdev->small_buf_virt_addr = NULL;
2472         }
2473 }
2474
2475 static void ql_free_large_buffers(struct ql3_adapter *qdev)
2476 {
2477         int i = 0;
2478         struct ql_rcv_buf_cb *lrg_buf_cb;
2479
2480         for (i = 0; i < NUM_LARGE_BUFFERS; i++) {
2481                 lrg_buf_cb = &qdev->lrg_buf[i];
2482                 if (lrg_buf_cb->skb) {
2483                         dev_kfree_skb(lrg_buf_cb->skb);
2484                         pci_unmap_single(qdev->pdev,
2485                                          pci_unmap_addr(lrg_buf_cb, mapaddr),
2486                                          pci_unmap_len(lrg_buf_cb, maplen),
2487                                          PCI_DMA_FROMDEVICE);
2488                         memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2489                 } else {
2490                         break;
2491                 }
2492         }
2493 }
2494
2495 static void ql_init_large_buffers(struct ql3_adapter *qdev)
2496 {
2497         int i;
2498         struct ql_rcv_buf_cb *lrg_buf_cb;
2499         struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2500
2501         for (i = 0; i < NUM_LARGE_BUFFERS; i++) {
2502                 lrg_buf_cb = &qdev->lrg_buf[i];
2503                 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2504                 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2505                 buf_addr_ele++;
2506         }
2507         qdev->lrg_buf_index = 0;
2508         qdev->lrg_buf_skb_check = 0;
2509 }
2510
2511 static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2512 {
2513         int i;
2514         struct ql_rcv_buf_cb *lrg_buf_cb;
2515         struct sk_buff *skb;
2516         u64 map;
2517
2518         for (i = 0; i < NUM_LARGE_BUFFERS; i++) {
2519                 skb = netdev_alloc_skb(qdev->ndev,
2520                                        qdev->lrg_buffer_len);
2521                 if (unlikely(!skb)) {
2522                         /* Better luck next round */
2523                         printk(KERN_ERR PFX
2524                                "%s: large buff alloc failed, "
2525                                "for %d bytes at index %d.\n",
2526                                qdev->ndev->name,
2527                                qdev->lrg_buffer_len * 2, i);
2528                         ql_free_large_buffers(qdev);
2529                         return -ENOMEM;
2530                 } else {
2531
2532                         lrg_buf_cb = &qdev->lrg_buf[i];
2533                         memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2534                         lrg_buf_cb->index = i;
2535                         lrg_buf_cb->skb = skb;
2536                         /*
2537                          * We save some space to copy the ethhdr from first
2538                          * buffer
2539                          */
2540                         skb_reserve(skb, QL_HEADER_SPACE);
2541                         map = pci_map_single(qdev->pdev,
2542                                              skb->data,
2543                                              qdev->lrg_buffer_len -
2544                                              QL_HEADER_SPACE,
2545                                              PCI_DMA_FROMDEVICE);
2546                         pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2547                         pci_unmap_len_set(lrg_buf_cb, maplen,
2548                                           qdev->lrg_buffer_len -
2549                                           QL_HEADER_SPACE);
2550                         lrg_buf_cb->buf_phy_addr_low =
2551                             cpu_to_le32(LS_64BITS(map));
2552                         lrg_buf_cb->buf_phy_addr_high =
2553                             cpu_to_le32(MS_64BITS(map));
2554                 }
2555         }
2556         return 0;
2557 }
2558
2559 static void ql_free_send_free_list(struct ql3_adapter *qdev)
2560 {
2561         struct ql_tx_buf_cb *tx_cb;
2562         int i;
2563
2564         tx_cb = &qdev->tx_buf[0];
2565         for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2566                 if (tx_cb->oal) {
2567                         kfree(tx_cb->oal);
2568                         tx_cb->oal = NULL;
2569                 }
2570                 tx_cb++;
2571         }
2572 }
2573
2574 static int ql_create_send_free_list(struct ql3_adapter *qdev)
2575 {
2576         struct ql_tx_buf_cb *tx_cb;
2577         int i;
2578         struct ob_mac_iocb_req *req_q_curr =
2579                                         qdev->req_q_virt_addr;
2580
2581         /* Create free list of transmit buffers */
2582         for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2583
2584                 tx_cb = &qdev->tx_buf[i];
2585                 tx_cb->skb = NULL;
2586                 tx_cb->queue_entry = req_q_curr;
2587                 req_q_curr++;
2588                 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2589                 if (tx_cb->oal == NULL)
2590                         return -1;
2591         }
2592         return 0;
2593 }
2594
2595 static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2596 {
2597         if (qdev->ndev->mtu == NORMAL_MTU_SIZE)
2598                 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
2599         else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
2600                 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2601         } else {
2602                 printk(KERN_ERR PFX
2603                        "%s: Invalid mtu size.  Only 1500 and 9000 are accepted.\n",
2604                        qdev->ndev->name);
2605                 return -ENOMEM;
2606         }
2607         qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2608         qdev->max_frame_size =
2609             (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2610
2611         /*
2612          * First allocate a page of shared memory and use it for shadow
2613          * locations of Network Request Queue Consumer Address Register and
2614          * Network Completion Queue Producer Index Register
2615          */
2616         qdev->shadow_reg_virt_addr =
2617             pci_alloc_consistent(qdev->pdev,
2618                                  PAGE_SIZE, &qdev->shadow_reg_phy_addr);
2619
2620         if (qdev->shadow_reg_virt_addr != NULL) {
2621                 qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
2622                 qdev->req_consumer_index_phy_addr_high =
2623                     MS_64BITS(qdev->shadow_reg_phy_addr);
2624                 qdev->req_consumer_index_phy_addr_low =
2625                     LS_64BITS(qdev->shadow_reg_phy_addr);
2626
2627                 qdev->prsp_producer_index =
2628                     (u32 *) (((u8 *) qdev->preq_consumer_index) + 8);
2629                 qdev->rsp_producer_index_phy_addr_high =
2630                     qdev->req_consumer_index_phy_addr_high;
2631                 qdev->rsp_producer_index_phy_addr_low =
2632                     qdev->req_consumer_index_phy_addr_low + 8;
2633         } else {
2634                 printk(KERN_ERR PFX
2635                        "%s: shadowReg Alloc failed.\n", qdev->ndev->name);
2636                 return -ENOMEM;
2637         }
2638
2639         if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
2640                 printk(KERN_ERR PFX
2641                        "%s: ql_alloc_net_req_rsp_queues failed.\n",
2642                        qdev->ndev->name);
2643                 goto err_req_rsp;
2644         }
2645
2646         if (ql_alloc_buffer_queues(qdev) != 0) {
2647                 printk(KERN_ERR PFX
2648                        "%s: ql_alloc_buffer_queues failed.\n",
2649                        qdev->ndev->name);
2650                 goto err_buffer_queues;
2651         }
2652
2653         if (ql_alloc_small_buffers(qdev) != 0) {
2654                 printk(KERN_ERR PFX
2655                        "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name);
2656                 goto err_small_buffers;
2657         }
2658
2659         if (ql_alloc_large_buffers(qdev) != 0) {
2660                 printk(KERN_ERR PFX
2661                        "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name);
2662                 goto err_small_buffers;
2663         }
2664
2665         /* Initialize the large buffer queue. */
2666         ql_init_large_buffers(qdev);
2667         if (ql_create_send_free_list(qdev))
2668                 goto err_free_list;
2669
2670         qdev->rsp_current = qdev->rsp_q_virt_addr;
2671
2672         return 0;
2673 err_free_list:
2674         ql_free_send_free_list(qdev);
2675 err_small_buffers:
2676         ql_free_buffer_queues(qdev);
2677 err_buffer_queues:
2678         ql_free_net_req_rsp_queues(qdev);
2679 err_req_rsp:
2680         pci_free_consistent(qdev->pdev,
2681                             PAGE_SIZE,
2682                             qdev->shadow_reg_virt_addr,
2683                             qdev->shadow_reg_phy_addr);
2684
2685         return -ENOMEM;
2686 }
2687
2688 static void ql_free_mem_resources(struct ql3_adapter *qdev)
2689 {
2690         ql_free_send_free_list(qdev);
2691         ql_free_large_buffers(qdev);
2692         ql_free_small_buffers(qdev);
2693         ql_free_buffer_queues(qdev);
2694         ql_free_net_req_rsp_queues(qdev);
2695         if (qdev->shadow_reg_virt_addr != NULL) {
2696                 pci_free_consistent(qdev->pdev,
2697                                     PAGE_SIZE,
2698                                     qdev->shadow_reg_virt_addr,
2699                                     qdev->shadow_reg_phy_addr);
2700                 qdev->shadow_reg_virt_addr = NULL;
2701         }
2702 }
2703
2704 static int ql_init_misc_registers(struct ql3_adapter *qdev)
2705 {
2706         struct ql3xxx_local_ram_registers __iomem *local_ram =
2707             (void __iomem *)qdev->mem_map_registers;
2708
2709         if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
2710                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2711                          2) << 4))
2712                 return -1;
2713
2714         ql_write_page2_reg(qdev,
2715                            &local_ram->bufletSize, qdev->nvram_data.bufletSize);
2716
2717         ql_write_page2_reg(qdev,
2718                            &local_ram->maxBufletCount,
2719                            qdev->nvram_data.bufletCount);
2720
2721         ql_write_page2_reg(qdev,
2722                            &local_ram->freeBufletThresholdLow,
2723                            (qdev->nvram_data.tcpWindowThreshold25 << 16) |
2724                            (qdev->nvram_data.tcpWindowThreshold0));
2725
2726         ql_write_page2_reg(qdev,
2727                            &local_ram->freeBufletThresholdHigh,
2728                            qdev->nvram_data.tcpWindowThreshold50);
2729
2730         ql_write_page2_reg(qdev,
2731                            &local_ram->ipHashTableBase,
2732                            (qdev->nvram_data.ipHashTableBaseHi << 16) |
2733                            qdev->nvram_data.ipHashTableBaseLo);
2734         ql_write_page2_reg(qdev,
2735                            &local_ram->ipHashTableCount,
2736                            qdev->nvram_data.ipHashTableSize);
2737         ql_write_page2_reg(qdev,
2738                            &local_ram->tcpHashTableBase,
2739                            (qdev->nvram_data.tcpHashTableBaseHi << 16) |
2740                            qdev->nvram_data.tcpHashTableBaseLo);
2741         ql_write_page2_reg(qdev,
2742                            &local_ram->tcpHashTableCount,
2743                            qdev->nvram_data.tcpHashTableSize);
2744         ql_write_page2_reg(qdev,
2745                            &local_ram->ncbBase,
2746                            (qdev->nvram_data.ncbTableBaseHi << 16) |
2747                            qdev->nvram_data.ncbTableBaseLo);
2748         ql_write_page2_reg(qdev,
2749                            &local_ram->maxNcbCount,
2750                            qdev->nvram_data.ncbTableSize);
2751         ql_write_page2_reg(qdev,
2752                            &local_ram->drbBase,
2753                            (qdev->nvram_data.drbTableBaseHi << 16) |
2754                            qdev->nvram_data.drbTableBaseLo);
2755         ql_write_page2_reg(qdev,
2756                            &local_ram->maxDrbCount,
2757                            qdev->nvram_data.drbTableSize);
2758         ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
2759         return 0;
2760 }
2761
2762 static int ql_adapter_initialize(struct ql3_adapter *qdev)
2763 {
2764         u32 value;
2765         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2766         struct ql3xxx_host_memory_registers __iomem *hmem_regs =
2767                                                 (void __iomem *)port_regs;
2768         u32 delay = 10;
2769         int status = 0;
2770
2771         if(ql_mii_setup(qdev))
2772                 return -1;
2773
2774         /* Bring out PHY out of reset */
2775         ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2776                             (ISP_SERIAL_PORT_IF_WE |
2777                              (ISP_SERIAL_PORT_IF_WE << 16)));
2778
2779         qdev->port_link_state = LS_DOWN;
2780         netif_carrier_off(qdev->ndev);
2781
2782         /* V2 chip fix for ARS-39168. */
2783         ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2784                             (ISP_SERIAL_PORT_IF_SDE |
2785                              (ISP_SERIAL_PORT_IF_SDE << 16)));
2786
2787         /* Request Queue Registers */
2788         *((u32 *) (qdev->preq_consumer_index)) = 0;
2789         atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES);
2790         qdev->req_producer_index = 0;
2791
2792         ql_write_page1_reg(qdev,
2793                            &hmem_regs->reqConsumerIndexAddrHigh,
2794                            qdev->req_consumer_index_phy_addr_high);
2795         ql_write_page1_reg(qdev,
2796                            &hmem_regs->reqConsumerIndexAddrLow,
2797                            qdev->req_consumer_index_phy_addr_low);
2798
2799         ql_write_page1_reg(qdev,
2800                            &hmem_regs->reqBaseAddrHigh,
2801                            MS_64BITS(qdev->req_q_phy_addr));
2802         ql_write_page1_reg(qdev,
2803                            &hmem_regs->reqBaseAddrLow,
2804                            LS_64BITS(qdev->req_q_phy_addr));
2805         ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
2806
2807         /* Response Queue Registers */
2808         *((u16 *) (qdev->prsp_producer_index)) = 0;
2809         qdev->rsp_consumer_index = 0;
2810         qdev->rsp_current = qdev->rsp_q_virt_addr;
2811
2812         ql_write_page1_reg(qdev,
2813                            &hmem_regs->rspProducerIndexAddrHigh,
2814                            qdev->rsp_producer_index_phy_addr_high);
2815
2816         ql_write_page1_reg(qdev,
2817                            &hmem_regs->rspProducerIndexAddrLow,
2818                            qdev->rsp_producer_index_phy_addr_low);
2819
2820         ql_write_page1_reg(qdev,
2821                            &hmem_regs->rspBaseAddrHigh,
2822                            MS_64BITS(qdev->rsp_q_phy_addr));
2823
2824         ql_write_page1_reg(qdev,
2825                            &hmem_regs->rspBaseAddrLow,
2826                            LS_64BITS(qdev->rsp_q_phy_addr));
2827
2828         ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
2829
2830         /* Large Buffer Queue */
2831         ql_write_page1_reg(qdev,
2832                            &hmem_regs->rxLargeQBaseAddrHigh,
2833                            MS_64BITS(qdev->lrg_buf_q_phy_addr));
2834
2835         ql_write_page1_reg(qdev,
2836                            &hmem_regs->rxLargeQBaseAddrLow,
2837                            LS_64BITS(qdev->lrg_buf_q_phy_addr));
2838
2839         ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, NUM_LBUFQ_ENTRIES);
2840
2841         ql_write_page1_reg(qdev,
2842                            &hmem_regs->rxLargeBufferLength,
2843                            qdev->lrg_buffer_len);
2844
2845         /* Small Buffer Queue */
2846         ql_write_page1_reg(qdev,
2847                            &hmem_regs->rxSmallQBaseAddrHigh,
2848                            MS_64BITS(qdev->small_buf_q_phy_addr));
2849
2850         ql_write_page1_reg(qdev,
2851                            &hmem_regs->rxSmallQBaseAddrLow,
2852                            LS_64BITS(qdev->small_buf_q_phy_addr));
2853
2854         ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
2855         ql_write_page1_reg(qdev,
2856                            &hmem_regs->rxSmallBufferLength,
2857                            QL_SMALL_BUFFER_SIZE);
2858
2859         qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
2860         qdev->small_buf_release_cnt = 8;
2861         qdev->lrg_buf_q_producer_index = NUM_LBUFQ_ENTRIES - 1;
2862         qdev->lrg_buf_release_cnt = 8;
2863         qdev->lrg_buf_next_free =
2864             (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
2865         qdev->small_buf_index = 0;
2866         qdev->lrg_buf_index = 0;
2867         qdev->lrg_buf_free_count = 0;
2868         qdev->lrg_buf_free_head = NULL;
2869         qdev->lrg_buf_free_tail = NULL;
2870
2871         ql_write_common_reg(qdev,
2872                             &port_regs->CommonRegs.
2873                             rxSmallQProducerIndex,
2874                             qdev->small_buf_q_producer_index);
2875         ql_write_common_reg(qdev,
2876                             &port_regs->CommonRegs.
2877                             rxLargeQProducerIndex,
2878                             qdev->lrg_buf_q_producer_index);
2879
2880         /*
2881          * Find out if the chip has already been initialized.  If it has, then
2882          * we skip some of the initialization.
2883          */
2884         clear_bit(QL_LINK_MASTER, &qdev->flags);
2885         value = ql_read_page0_reg(qdev, &port_regs->portStatus);
2886         if ((value & PORT_STATUS_IC) == 0) {
2887
2888                 /* Chip has not been configured yet, so let it rip. */
2889                 if(ql_init_misc_registers(qdev)) {
2890                         status = -1;
2891                         goto out;
2892                 }
2893
2894                 if (qdev->mac_index)
2895                         ql_write_page0_reg(qdev,
2896                                            &port_regs->mac1MaxFrameLengthReg,
2897                                            qdev->max_frame_size);
2898                 else
2899                         ql_write_page0_reg(qdev,
2900                                            &port_regs->mac0MaxFrameLengthReg,
2901                                            qdev->max_frame_size);
2902
2903                 value = qdev->nvram_data.tcpMaxWindowSize;
2904                 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
2905
2906                 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
2907
2908                 if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
2909                                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
2910                                  * 2) << 13)) {
2911                         status = -1;
2912                         goto out;
2913                 }
2914                 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
2915                 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
2916                                    (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
2917                                      16) | (INTERNAL_CHIP_SD |
2918                                             INTERNAL_CHIP_WE)));
2919                 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
2920         }
2921
2922
2923         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
2924                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2925                          2) << 7)) {
2926                 status = -1;
2927                 goto out;
2928         }
2929
2930         ql_init_scan_mode(qdev);
2931         ql_get_phy_owner(qdev);
2932
2933         /* Load the MAC Configuration */
2934
2935         /* Program lower 32 bits of the MAC address */
2936         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
2937                            (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
2938         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
2939                            ((qdev->ndev->dev_addr[2] << 24)
2940                             | (qdev->ndev->dev_addr[3] << 16)
2941                             | (qdev->ndev->dev_addr[4] << 8)
2942                             | qdev->ndev->dev_addr[5]));
2943
2944         /* Program top 16 bits of the MAC address */
2945         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
2946                            ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
2947         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
2948                            ((qdev->ndev->dev_addr[0] << 8)
2949                             | qdev->ndev->dev_addr[1]));
2950
2951         /* Enable Primary MAC */
2952         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
2953                            ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
2954                             MAC_ADDR_INDIRECT_PTR_REG_PE));
2955
2956         /* Clear Primary and Secondary IP addresses */
2957         ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
2958                            ((IP_ADDR_INDEX_REG_MASK << 16) |
2959                             (qdev->mac_index << 2)));
2960         ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
2961
2962         ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
2963                            ((IP_ADDR_INDEX_REG_MASK << 16) |
2964                             ((qdev->mac_index << 2) + 1)));
2965         ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
2966
2967         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
2968
2969         /* Indicate Configuration Complete */
2970         ql_write_page0_reg(qdev,
2971                            &port_regs->portControl,
2972                            ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
2973
2974         do {
2975                 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
2976                 if (value & PORT_STATUS_IC)
2977                         break;
2978                 msleep(500);
2979         } while (--delay);
2980
2981         if (delay == 0) {
2982                 printk(KERN_ERR PFX
2983                        "%s: Hw Initialization timeout.\n", qdev->ndev->name);
2984                 status = -1;
2985                 goto out;
2986         }
2987
2988         /* Enable Ethernet Function */
2989         if (qdev->device_id == QL3032_DEVICE_ID) {
2990                 value =
2991                     (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
2992                      QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4);
2993                 ql_write_page0_reg(qdev, &port_regs->functionControl,
2994                                    ((value << 16) | value));
2995         } else {
2996                 value =
2997                     (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
2998                      PORT_CONTROL_HH);
2999                 ql_write_page0_reg(qdev, &port_regs->portControl,
3000                                    ((value << 16) | value));
3001         }
3002
3003
3004 out:
3005         return status;
3006 }
3007
3008 /*
3009  * Caller holds hw_lock.
3010  */
3011 static int ql_adapter_reset(struct ql3_adapter *qdev)
3012 {
3013         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3014         int status = 0;
3015         u16 value;
3016         int max_wait_time;
3017
3018         set_bit(QL_RESET_ACTIVE, &qdev->flags);
3019         clear_bit(QL_RESET_DONE, &qdev->flags);
3020
3021         /*
3022          * Issue soft reset to chip.
3023          */
3024         printk(KERN_DEBUG PFX
3025                "%s: Issue soft reset to chip.\n",
3026                qdev->ndev->name);
3027         ql_write_common_reg(qdev,
3028                             &port_regs->CommonRegs.ispControlStatus,
3029                             ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3030
3031         /* Wait 3 seconds for reset to complete. */
3032         printk(KERN_DEBUG PFX
3033                "%s: Wait 10 milliseconds for reset to complete.\n",
3034                qdev->ndev->name);
3035
3036         /* Wait until the firmware tells us the Soft Reset is done */
3037         max_wait_time = 5;
3038         do {
3039                 value =
3040                     ql_read_common_reg(qdev,
3041                                        &port_regs->CommonRegs.ispControlStatus);
3042                 if ((value & ISP_CONTROL_SR) == 0)
3043                         break;
3044
3045                 ssleep(1);
3046         } while ((--max_wait_time));
3047
3048         /*
3049          * Also, make sure that the Network Reset Interrupt bit has been
3050          * cleared after the soft reset has taken place.
3051          */
3052         value =
3053             ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3054         if (value & ISP_CONTROL_RI) {
3055                 printk(KERN_DEBUG PFX
3056                        "ql_adapter_reset: clearing RI after reset.\n");
3057                 ql_write_common_reg(qdev,
3058                                     &port_regs->CommonRegs.
3059                                     ispControlStatus,
3060                                     ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3061         }
3062
3063         if (max_wait_time == 0) {
3064                 /* Issue Force Soft Reset */
3065                 ql_write_common_reg(qdev,
3066                                     &port_regs->CommonRegs.
3067                                     ispControlStatus,
3068                                     ((ISP_CONTROL_FSR << 16) |
3069                                      ISP_CONTROL_FSR));
3070                 /*
3071                  * Wait until the firmware tells us the Force Soft Reset is
3072                  * done
3073                  */
3074                 max_wait_time = 5;
3075                 do {
3076                         value =
3077                             ql_read_common_reg(qdev,
3078                                                &port_regs->CommonRegs.
3079                                                ispControlStatus);
3080                         if ((value & ISP_CONTROL_FSR) == 0) {
3081                                 break;
3082                         }
3083                         ssleep(1);
3084                 } while ((--max_wait_time));
3085         }
3086         if (max_wait_time == 0)
3087                 status = 1;
3088
3089         clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3090         set_bit(QL_RESET_DONE, &qdev->flags);
3091         return status;
3092 }
3093
3094 static void ql_set_mac_info(struct ql3_adapter *qdev)
3095 {
3096         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3097         u32 value, port_status;
3098         u8 func_number;
3099
3100         /* Get the function number */
3101         value =
3102             ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3103         func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3104         port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3105         switch (value & ISP_CONTROL_FN_MASK) {
3106         case ISP_CONTROL_FN0_NET:
3107                 qdev->mac_index = 0;
3108                 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3109                 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3110                 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3111                 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3112                 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3113                 if (port_status & PORT_STATUS_SM0)
3114                         set_bit(QL_LINK_OPTICAL,&qdev->flags);
3115                 else
3116                         clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3117                 break;
3118
3119         case ISP_CONTROL_FN1_NET:
3120                 qdev->mac_index = 1;
3121                 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3122                 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3123                 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3124                 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3125                 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3126                 if (port_status & PORT_STATUS_SM1)
3127                         set_bit(QL_LINK_OPTICAL,&qdev->flags);
3128                 else
3129                         clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3130                 break;
3131
3132         case ISP_CONTROL_FN0_SCSI:
3133         case ISP_CONTROL_FN1_SCSI:
3134         default:
3135                 printk(KERN_DEBUG PFX
3136                        "%s: Invalid function number, ispControlStatus = 0x%x\n",
3137                        qdev->ndev->name,value);
3138                 break;
3139         }
3140         qdev->numPorts = qdev->nvram_data.numPorts;
3141 }
3142
3143 static void ql_display_dev_info(struct net_device *ndev)
3144 {
3145         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3146         struct pci_dev *pdev = qdev->pdev;
3147
3148         printk(KERN_INFO PFX
3149                "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n",
3150                DRV_NAME, qdev->index, qdev->chip_rev_id,
3151                (qdev->device_id == QL3032_DEVICE_ID) ? "QLA3032" : "QLA3022",
3152                qdev->pci_slot);
3153         printk(KERN_INFO PFX
3154                "%s Interface.\n",
3155                test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER");
3156
3157         /*
3158          * Print PCI bus width/type.
3159          */
3160         printk(KERN_INFO PFX
3161                "Bus interface is %s %s.\n",
3162                ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3163                ((qdev->pci_x) ? "PCI-X" : "PCI"));
3164
3165         printk(KERN_INFO PFX
3166                "mem  IO base address adjusted = 0x%p\n",
3167                qdev->mem_map_registers);
3168         printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq);
3169
3170         if (netif_msg_probe(qdev))
3171                 printk(KERN_INFO PFX
3172                        "%s: MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
3173                        ndev->name, ndev->dev_addr[0], ndev->dev_addr[1],
3174                        ndev->dev_addr[2], ndev->dev_addr[3], ndev->dev_addr[4],
3175                        ndev->dev_addr[5]);
3176 }
3177
3178 static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3179 {
3180         struct net_device *ndev = qdev->ndev;
3181         int retval = 0;
3182
3183         netif_stop_queue(ndev);
3184         netif_carrier_off(ndev);
3185
3186         clear_bit(QL_ADAPTER_UP,&qdev->flags);
3187         clear_bit(QL_LINK_MASTER,&qdev->flags);
3188
3189         ql_disable_interrupts(qdev);
3190
3191         free_irq(qdev->pdev->irq, ndev);
3192
3193         if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3194                 printk(KERN_INFO PFX
3195                        "%s: calling pci_disable_msi().\n", qdev->ndev->name);
3196                 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3197                 pci_disable_msi(qdev->pdev);
3198         }
3199
3200         del_timer_sync(&qdev->adapter_timer);
3201
3202         netif_poll_disable(ndev);
3203
3204         if (do_reset) {
3205                 int soft_reset;
3206                 unsigned long hw_flags;
3207
3208                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3209                 if (ql_wait_for_drvr_lock(qdev)) {
3210                         if ((soft_reset = ql_adapter_reset(qdev))) {
3211                                 printk(KERN_ERR PFX
3212                                        "%s: ql_adapter_reset(%d) FAILED!\n",
3213                                        ndev->name, qdev->index);
3214                         }
3215                         printk(KERN_ERR PFX
3216                                 "%s: Releaseing driver lock via chip reset.\n",ndev->name);
3217                 } else {
3218                         printk(KERN_ERR PFX
3219                                "%s: Could not acquire driver lock to do "
3220                                "reset!\n", ndev->name);
3221                         retval = -1;
3222                 }
3223                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3224         }
3225         ql_free_mem_resources(qdev);
3226         return retval;
3227 }
3228
3229 static int ql_adapter_up(struct ql3_adapter *qdev)
3230 {
3231         struct net_device *ndev = qdev->ndev;
3232         int err;
3233         unsigned long irq_flags = IRQF_SAMPLE_RANDOM | IRQF_SHARED;
3234         unsigned long hw_flags;
3235
3236         if (ql_alloc_mem_resources(qdev)) {
3237                 printk(KERN_ERR PFX
3238                        "%s Unable to  allocate buffers.\n", ndev->name);
3239                 return -ENOMEM;
3240         }
3241
3242         if (qdev->msi) {
3243                 if (pci_enable_msi(qdev->pdev)) {
3244                         printk(KERN_ERR PFX
3245                                "%s: User requested MSI, but MSI failed to "
3246                                "initialize.  Continuing without MSI.\n",
3247                                qdev->ndev->name);
3248                         qdev->msi = 0;
3249                 } else {
3250                         printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name);
3251                         set_bit(QL_MSI_ENABLED,&qdev->flags);
3252                         irq_flags &= ~IRQF_SHARED;
3253                 }
3254         }
3255
3256         if ((err = request_irq(qdev->pdev->irq,
3257                                ql3xxx_isr,
3258                                irq_flags, ndev->name, ndev))) {
3259                 printk(KERN_ERR PFX
3260                        "%s: Failed to reserve interrupt %d already in use.\n",
3261                        ndev->name, qdev->pdev->irq);
3262                 goto err_irq;
3263         }
3264
3265         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3266
3267         if ((err = ql_wait_for_drvr_lock(qdev))) {
3268                 if ((err = ql_adapter_initialize(qdev))) {
3269                         printk(KERN_ERR PFX
3270                                "%s: Unable to initialize adapter.\n",
3271                                ndev->name);
3272                         goto err_init;
3273                 }
3274                 printk(KERN_ERR PFX
3275                                 "%s: Releaseing driver lock.\n",ndev->name);
3276                 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3277         } else {
3278                 printk(KERN_ERR PFX
3279                        "%s: Could not aquire driver lock.\n",
3280                        ndev->name);
3281                 goto err_lock;
3282         }
3283
3284         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3285
3286         set_bit(QL_ADAPTER_UP,&qdev->flags);
3287
3288         mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3289
3290         netif_poll_enable(ndev);
3291         ql_enable_interrupts(qdev);
3292         return 0;
3293
3294 err_init:
3295         ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3296 err_lock:
3297         free_irq(qdev->pdev->irq, ndev);
3298 err_irq:
3299         if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3300                 printk(KERN_INFO PFX
3301                        "%s: calling pci_disable_msi().\n",
3302                        qdev->ndev->name);
3303                 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3304                 pci_disable_msi(qdev->pdev);
3305         }
3306         return err;
3307 }
3308
3309 static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3310 {
3311         if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) {
3312                 printk(KERN_ERR PFX
3313                                 "%s: Driver up/down cycle failed, "
3314                                 "closing device\n",qdev->ndev->name);
3315                 dev_close(qdev->ndev);
3316                 return -1;
3317         }
3318         return 0;
3319 }
3320
3321 static int ql3xxx_close(struct net_device *ndev)
3322 {
3323         struct ql3_adapter *qdev = netdev_priv(ndev);
3324
3325         /*
3326          * Wait for device to recover from a reset.
3327          * (Rarely happens, but possible.)
3328          */
3329         while (!test_bit(QL_ADAPTER_UP,&qdev->flags))
3330                 msleep(50);
3331
3332         ql_adapter_down(qdev,QL_DO_RESET);
3333         return 0;
3334 }
3335
3336 static int ql3xxx_open(struct net_device *ndev)
3337 {
3338         struct ql3_adapter *qdev = netdev_priv(ndev);
3339         return (ql_adapter_up(qdev));
3340 }
3341
3342 static struct net_device_stats *ql3xxx_get_stats(struct net_device *dev)
3343 {
3344         struct ql3_adapter *qdev = (struct ql3_adapter *)dev->priv;
3345         return &qdev->stats;
3346 }
3347
3348 static int ql3xxx_change_mtu(struct net_device *ndev, int new_mtu)
3349 {
3350         struct ql3_adapter *qdev = netdev_priv(ndev);
3351         printk(KERN_ERR PFX "%s:  new mtu size = %d.\n", ndev->name, new_mtu);
3352         if (new_mtu != NORMAL_MTU_SIZE && new_mtu != JUMBO_MTU_SIZE) {
3353                 printk(KERN_ERR PFX
3354                        "%s: mtu size of %d is not valid.  Use exactly %d or "
3355                        "%d.\n", ndev->name, new_mtu, NORMAL_MTU_SIZE,
3356                        JUMBO_MTU_SIZE);
3357                 return -EINVAL;
3358         }
3359
3360         if (!netif_running(ndev)) {
3361                 ndev->mtu = new_mtu;
3362                 return 0;
3363         }
3364
3365         ndev->mtu = new_mtu;
3366         return ql_cycle_adapter(qdev,QL_DO_RESET);
3367 }
3368
3369 static void ql3xxx_set_multicast_list(struct net_device *ndev)
3370 {
3371         /*
3372          * We are manually parsing the list in the net_device structure.
3373          */
3374         return;
3375 }
3376
3377 static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3378 {
3379         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3380         struct ql3xxx_port_registers __iomem *port_regs =
3381                         qdev->mem_map_registers;
3382         struct sockaddr *addr = p;
3383         unsigned long hw_flags;
3384
3385         if (netif_running(ndev))
3386                 return -EBUSY;
3387
3388         if (!is_valid_ether_addr(addr->sa_data))
3389                 return -EADDRNOTAVAIL;
3390
3391         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3392
3393         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3394         /* Program lower 32 bits of the MAC address */
3395         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3396                            (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3397         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3398                            ((ndev->dev_addr[2] << 24) | (ndev->
3399                                                          dev_addr[3] << 16) |
3400                             (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3401
3402         /* Program top 16 bits of the MAC address */
3403         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3404                            ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3405         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3406                            ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3407         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3408
3409         return 0;
3410 }
3411
3412 static void ql3xxx_tx_timeout(struct net_device *ndev)
3413 {
3414         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3415
3416         printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name);
3417         /*
3418          * Stop the queues, we've got a problem.
3419          */
3420         netif_stop_queue(ndev);
3421
3422         /*
3423          * Wake up the worker to process this event.
3424          */
3425         queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3426 }
3427
3428 static void ql_reset_work(struct work_struct *work)
3429 {
3430         struct ql3_adapter *qdev =
3431                 container_of(work, struct ql3_adapter, reset_work.work);
3432         struct net_device *ndev = qdev->ndev;
3433         u32 value;
3434         struct ql_tx_buf_cb *tx_cb;
3435         int max_wait_time, i;
3436         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3437         unsigned long hw_flags;
3438
3439         if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) {
3440                 clear_bit(QL_LINK_MASTER,&qdev->flags);
3441
3442                 /*
3443                  * Loop through the active list and return the skb.
3444                  */
3445                 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3446                         int j;
3447                         tx_cb = &qdev->tx_buf[i];
3448                         if (tx_cb->skb) {
3449                                 printk(KERN_DEBUG PFX
3450                                        "%s: Freeing lost SKB.\n",
3451                                        qdev->ndev->name);
3452                                 pci_unmap_single(qdev->pdev,
3453                                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
3454                                          pci_unmap_len(&tx_cb->map[0], maplen),
3455                                          PCI_DMA_TODEVICE);
3456                                 for(j=1;j<tx_cb->seg_count;j++) {
3457                                         pci_unmap_page(qdev->pdev,
3458                                                pci_unmap_addr(&tx_cb->map[j],mapaddr),
3459                                                pci_unmap_len(&tx_cb->map[j],maplen),
3460                                                PCI_DMA_TODEVICE);
3461                                 }
3462                                 dev_kfree_skb(tx_cb->skb);
3463                                 tx_cb->skb = NULL;
3464                         }
3465                 }
3466
3467                 printk(KERN_ERR PFX
3468                        "%s: Clearing NRI after reset.\n", qdev->ndev->name);
3469                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3470                 ql_write_common_reg(qdev,
3471                                     &port_regs->CommonRegs.
3472                                     ispControlStatus,
3473                                     ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3474                 /*
3475                  * Wait the for Soft Reset to Complete.
3476                  */
3477                 max_wait_time = 10;
3478                 do {
3479                         value = ql_read_common_reg(qdev,
3480                                                    &port_regs->CommonRegs.
3481
3482                                                    ispControlStatus);
3483                         if ((value & ISP_CONTROL_SR) == 0) {
3484                                 printk(KERN_DEBUG PFX
3485                                        "%s: reset completed.\n",
3486                                        qdev->ndev->name);
3487                                 break;
3488                         }
3489
3490                         if (value & ISP_CONTROL_RI) {
3491                                 printk(KERN_DEBUG PFX
3492                                        "%s: clearing NRI after reset.\n",
3493                                        qdev->ndev->name);
3494                                 ql_write_common_reg(qdev,
3495                                                     &port_regs->
3496                                                     CommonRegs.
3497                                                     ispControlStatus,
3498                                                     ((ISP_CONTROL_RI <<
3499                                                       16) | ISP_CONTROL_RI));
3500                         }
3501
3502                         ssleep(1);
3503                 } while (--max_wait_time);
3504                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3505
3506                 if (value & ISP_CONTROL_SR) {
3507
3508                         /*
3509                          * Set the reset flags and clear the board again.
3510                          * Nothing else to do...
3511                          */
3512                         printk(KERN_ERR PFX
3513                                "%s: Timed out waiting for reset to "
3514                                "complete.\n", ndev->name);
3515                         printk(KERN_ERR PFX
3516                                "%s: Do a reset.\n", ndev->name);
3517                         clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3518                         clear_bit(QL_RESET_START,&qdev->flags);
3519                         ql_cycle_adapter(qdev,QL_DO_RESET);
3520                         return;
3521                 }
3522
3523                 clear_bit(QL_RESET_ACTIVE,&qdev->flags);
3524                 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3525                 clear_bit(QL_RESET_START,&qdev->flags);
3526                 ql_cycle_adapter(qdev,QL_NO_RESET);
3527         }
3528 }
3529
3530 static void ql_tx_timeout_work(struct work_struct *work)
3531 {
3532         struct ql3_adapter *qdev =
3533                 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3534
3535         ql_cycle_adapter(qdev, QL_DO_RESET);
3536 }
3537
3538 static void ql_get_board_info(struct ql3_adapter *qdev)
3539 {
3540         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3541         u32 value;
3542
3543         value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3544
3545         qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3546         if (value & PORT_STATUS_64)
3547                 qdev->pci_width = 64;
3548         else
3549                 qdev->pci_width = 32;
3550         if (value & PORT_STATUS_X)
3551                 qdev->pci_x = 1;
3552         else
3553                 qdev->pci_x = 0;
3554         qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3555 }
3556
3557 static void ql3xxx_timer(unsigned long ptr)
3558 {
3559         struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3560
3561         if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
3562                 printk(KERN_DEBUG PFX
3563                        "%s: Reset in progress.\n",
3564                        qdev->ndev->name);
3565                 goto end;
3566         }
3567
3568         ql_link_state_machine(qdev);
3569
3570         /* Restart timer on 2 second interval. */
3571 end:
3572         mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3573 }
3574
3575 static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3576                                   const struct pci_device_id *pci_entry)
3577 {
3578         struct net_device *ndev = NULL;
3579         struct ql3_adapter *qdev = NULL;
3580         static int cards_found = 0;
3581         int pci_using_dac, err;
3582
3583         err = pci_enable_device(pdev);
3584         if (err) {
3585                 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3586                        pci_name(pdev));
3587                 goto err_out;
3588         }
3589
3590         err = pci_request_regions(pdev, DRV_NAME);
3591         if (err) {
3592                 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3593                        pci_name(pdev));
3594                 goto err_out_disable_pdev;
3595         }
3596
3597         pci_set_master(pdev);
3598
3599         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3600                 pci_using_dac = 1;
3601                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3602         } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3603                 pci_using_dac = 0;
3604                 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3605         }
3606
3607         if (err) {
3608                 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3609                        pci_name(pdev));
3610                 goto err_out_free_regions;
3611         }
3612
3613         ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3614         if (!ndev) {
3615                 printk(KERN_ERR PFX "%s could not alloc etherdev\n",
3616                        pci_name(pdev));
3617                 err = -ENOMEM;
3618                 goto err_out_free_regions;
3619         }
3620
3621         SET_MODULE_OWNER(ndev);
3622         SET_NETDEV_DEV(ndev, &pdev->dev);
3623
3624         pci_set_drvdata(pdev, ndev);
3625
3626         qdev = netdev_priv(ndev);
3627         qdev->index = cards_found;
3628         qdev->ndev = ndev;
3629         qdev->pdev = pdev;
3630         qdev->device_id = pci_entry->device;
3631         qdev->port_link_state = LS_DOWN;
3632         if (msi)
3633                 qdev->msi = 1;
3634
3635         qdev->msg_enable = netif_msg_init(debug, default_msg);
3636
3637         if (pci_using_dac)
3638                 ndev->features |= NETIF_F_HIGHDMA;
3639         if (qdev->device_id == QL3032_DEVICE_ID)
3640                 ndev->features |= (NETIF_F_HW_CSUM | NETIF_F_SG);
3641
3642         qdev->mem_map_registers =
3643             ioremap_nocache(pci_resource_start(pdev, 1),
3644                             pci_resource_len(qdev->pdev, 1));
3645         if (!qdev->mem_map_registers) {
3646                 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3647                        pci_name(pdev));
3648                 err = -EIO;
3649                 goto err_out_free_ndev;
3650         }
3651
3652         spin_lock_init(&qdev->adapter_lock);
3653         spin_lock_init(&qdev->hw_lock);
3654
3655         /* Set driver entry points */
3656         ndev->open = ql3xxx_open;
3657         ndev->hard_start_xmit = ql3xxx_send;
3658         ndev->stop = ql3xxx_close;
3659         ndev->get_stats = ql3xxx_get_stats;
3660         ndev->change_mtu = ql3xxx_change_mtu;
3661         ndev->set_multicast_list = ql3xxx_set_multicast_list;
3662         SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
3663         ndev->set_mac_address = ql3xxx_set_mac_address;
3664         ndev->tx_timeout = ql3xxx_tx_timeout;
3665         ndev->watchdog_timeo = 5 * HZ;
3666
3667         ndev->poll = &ql_poll;
3668         ndev->weight = 64;
3669
3670         ndev->irq = pdev->irq;
3671
3672         /* make sure the EEPROM is good */
3673         if (ql_get_nvram_params(qdev)) {
3674                 printk(KERN_ALERT PFX
3675                        "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
3676                        qdev->index);
3677                 err = -EIO;
3678                 goto err_out_iounmap;
3679         }
3680
3681         ql_set_mac_info(qdev);
3682
3683         /* Validate and set parameters */
3684         if (qdev->mac_index) {
3685                 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn2.macAddress,
3686                        ETH_ALEN);
3687         } else {
3688                 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn0.macAddress,
3689                        ETH_ALEN);
3690         }
3691         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3692
3693         ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
3694
3695         /* Turn off support for multicasting */
3696         ndev->flags &= ~IFF_MULTICAST;
3697
3698         /* Record PCI bus information. */
3699         ql_get_board_info(qdev);
3700
3701         /*
3702          * Set the Maximum Memory Read Byte Count value. We do this to handle
3703          * jumbo frames.
3704          */
3705         if (qdev->pci_x) {
3706                 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
3707         }
3708
3709         err = register_netdev(ndev);
3710         if (err) {
3711                 printk(KERN_ERR PFX "%s: cannot register net device\n",
3712                        pci_name(pdev));
3713                 goto err_out_iounmap;
3714         }
3715
3716         /* we're going to reset, so assume we have no link for now */
3717
3718         netif_carrier_off(ndev);
3719         netif_stop_queue(ndev);
3720
3721         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3722         INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
3723         INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
3724
3725         init_timer(&qdev->adapter_timer);
3726         qdev->adapter_timer.function = ql3xxx_timer;
3727         qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
3728         qdev->adapter_timer.data = (unsigned long)qdev;
3729
3730         if(!cards_found) {
3731                 printk(KERN_ALERT PFX "%s\n", DRV_STRING);
3732                 printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n",
3733                    DRV_NAME, DRV_VERSION);
3734         }
3735         ql_display_dev_info(ndev);
3736
3737         cards_found++;
3738         return 0;
3739
3740 err_out_iounmap:
3741         iounmap(qdev->mem_map_registers);
3742 err_out_free_ndev:
3743         free_netdev(ndev);
3744 err_out_free_regions:
3745         pci_release_regions(pdev);
3746 err_out_disable_pdev:
3747         pci_disable_device(pdev);
3748         pci_set_drvdata(pdev, NULL);
3749 err_out:
3750         return err;
3751 }
3752
3753 static void __devexit ql3xxx_remove(struct pci_dev *pdev)
3754 {
3755         struct net_device *ndev = pci_get_drvdata(pdev);
3756         struct ql3_adapter *qdev = netdev_priv(ndev);
3757
3758         unregister_netdev(ndev);
3759         qdev = netdev_priv(ndev);
3760
3761         ql_disable_interrupts(qdev);
3762
3763         if (qdev->workqueue) {
3764                 cancel_delayed_work(&qdev->reset_work);
3765                 cancel_delayed_work(&qdev->tx_timeout_work);
3766                 destroy_workqueue(qdev->workqueue);
3767                 qdev->workqueue = NULL;
3768         }
3769
3770         iounmap(qdev->mem_map_registers);
3771         pci_release_regions(pdev);
3772         pci_set_drvdata(pdev, NULL);
3773         free_netdev(ndev);
3774 }
3775
3776 static struct pci_driver ql3xxx_driver = {
3777
3778         .name = DRV_NAME,
3779         .id_table = ql3xxx_pci_tbl,
3780         .probe = ql3xxx_probe,
3781         .remove = __devexit_p(ql3xxx_remove),
3782 };
3783
3784 static int __init ql3xxx_init_module(void)
3785 {
3786         return pci_register_driver(&ql3xxx_driver);
3787 }
3788
3789 static void __exit ql3xxx_exit(void)
3790 {
3791         pci_unregister_driver(&ql3xxx_driver);
3792 }
3793
3794 module_init(ql3xxx_init_module);
3795 module_exit(ql3xxx_exit);