[NET]: Make NAPI polling independent of struct net_device objects.
[linux-2.6.git] / drivers / net / qla3xxx.c
1 /*
2  * QLogic QLA3xxx NIC HBA Driver
3  * Copyright (c)  2003-2006 QLogic Corporation
4  *
5  * See LICENSE.qla3xxx for copyright and licensing details.
6  */
7
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
17 #include <linux/dmapool.h>
18 #include <linux/mempool.h>
19 #include <linux/spinlock.h>
20 #include <linux/kthread.h>
21 #include <linux/interrupt.h>
22 #include <linux/errno.h>
23 #include <linux/ioport.h>
24 #include <linux/ip.h>
25 #include <linux/in.h>
26 #include <linux/if_arp.h>
27 #include <linux/if_ether.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/ethtool.h>
31 #include <linux/skbuff.h>
32 #include <linux/rtnetlink.h>
33 #include <linux/if_vlan.h>
34 #include <linux/init.h>
35 #include <linux/delay.h>
36 #include <linux/mm.h>
37
38 #include "qla3xxx.h"
39
40 #define DRV_NAME        "qla3xxx"
41 #define DRV_STRING      "QLogic ISP3XXX Network Driver"
42 #define DRV_VERSION     "v2.03.00-k4"
43 #define PFX             DRV_NAME " "
44
45 static const char ql3xxx_driver_name[] = DRV_NAME;
46 static const char ql3xxx_driver_version[] = DRV_VERSION;
47
48 MODULE_AUTHOR("QLogic Corporation");
49 MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
50 MODULE_LICENSE("GPL");
51 MODULE_VERSION(DRV_VERSION);
52
53 static const u32 default_msg
54     = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
55     | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
56
57 static int debug = -1;          /* defaults above */
58 module_param(debug, int, 0);
59 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
60
61 static int msi;
62 module_param(msi, int, 0);
63 MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
64
65 static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
66         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
67         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
68         /* required last entry */
69         {0,}
70 };
71
72 MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
73
74 /*
75  *  These are the known PHY's which are used
76  */
77 typedef enum {
78    PHY_TYPE_UNKNOWN   = 0,
79    PHY_VITESSE_VSC8211,
80    PHY_AGERE_ET1011C,
81    MAX_PHY_DEV_TYPES
82 } PHY_DEVICE_et;
83
84 typedef struct {
85         PHY_DEVICE_et phyDevice; 
86         u32             phyIdOUI;
87         u16             phyIdModel;
88         char            *name;
89 } PHY_DEVICE_INFO_t;
90
91 static const PHY_DEVICE_INFO_t PHY_DEVICES[] =
92         {{PHY_TYPE_UNKNOWN,    0x000000, 0x0, "PHY_TYPE_UNKNOWN"},
93          {PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"},
94          {PHY_AGERE_ET1011C,   0x00a0bc, 0x1, "PHY_AGERE_ET1011C"},
95 };
96
97
98 /*
99  * Caller must take hw_lock.
100  */
101 static int ql_sem_spinlock(struct ql3_adapter *qdev,
102                             u32 sem_mask, u32 sem_bits)
103 {
104         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
105         u32 value;
106         unsigned int seconds = 3;
107
108         do {
109                 writel((sem_mask | sem_bits),
110                        &port_regs->CommonRegs.semaphoreReg);
111                 value = readl(&port_regs->CommonRegs.semaphoreReg);
112                 if ((value & (sem_mask >> 16)) == sem_bits)
113                         return 0;
114                 ssleep(1);
115         } while(--seconds);
116         return -1;
117 }
118
119 static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
120 {
121         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
122         writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
123         readl(&port_regs->CommonRegs.semaphoreReg);
124 }
125
126 static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
127 {
128         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
129         u32 value;
130
131         writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
132         value = readl(&port_regs->CommonRegs.semaphoreReg);
133         return ((value & (sem_mask >> 16)) == sem_bits);
134 }
135
136 /*
137  * Caller holds hw_lock.
138  */
139 static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
140 {
141         int i = 0;
142
143         while (1) {
144                 if (!ql_sem_lock(qdev,
145                                  QL_DRVR_SEM_MASK,
146                                  (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
147                                   * 2) << 1)) {
148                         if (i < 10) {
149                                 ssleep(1);
150                                 i++;
151                         } else {
152                                 printk(KERN_ERR PFX "%s: Timed out waiting for "
153                                        "driver lock...\n",
154                                        qdev->ndev->name);
155                                 return 0;
156                         }
157                 } else {
158                         printk(KERN_DEBUG PFX
159                                "%s: driver lock acquired.\n",
160                                qdev->ndev->name);
161                         return 1;
162                 }
163         }
164 }
165
166 static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
167 {
168         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
169
170         writel(((ISP_CONTROL_NP_MASK << 16) | page),
171                         &port_regs->CommonRegs.ispControlStatus);
172         readl(&port_regs->CommonRegs.ispControlStatus);
173         qdev->current_page = page;
174 }
175
176 static u32 ql_read_common_reg_l(struct ql3_adapter *qdev,
177                               u32 __iomem * reg)
178 {
179         u32 value;
180         unsigned long hw_flags;
181
182         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
183         value = readl(reg);
184         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
185
186         return value;
187 }
188
189 static u32 ql_read_common_reg(struct ql3_adapter *qdev,
190                               u32 __iomem * reg)
191 {
192         return readl(reg);
193 }
194
195 static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
196 {
197         u32 value;
198         unsigned long hw_flags;
199
200         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
201
202         if (qdev->current_page != 0)
203                 ql_set_register_page(qdev,0);
204         value = readl(reg);
205
206         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
207         return value;
208 }
209
210 static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
211 {
212         if (qdev->current_page != 0)
213                 ql_set_register_page(qdev,0);
214         return readl(reg);
215 }
216
217 static void ql_write_common_reg_l(struct ql3_adapter *qdev,
218                                 u32 __iomem *reg, u32 value)
219 {
220         unsigned long hw_flags;
221
222         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
223         writel(value, reg);
224         readl(reg);
225         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
226         return;
227 }
228
229 static void ql_write_common_reg(struct ql3_adapter *qdev,
230                                 u32 __iomem *reg, u32 value)
231 {
232         writel(value, reg);
233         readl(reg);
234         return;
235 }
236
237 static void ql_write_nvram_reg(struct ql3_adapter *qdev,
238                                 u32 __iomem *reg, u32 value)
239 {
240         writel(value, reg);
241         readl(reg);
242         udelay(1);
243         return;
244 }
245
246 static void ql_write_page0_reg(struct ql3_adapter *qdev,
247                                u32 __iomem *reg, u32 value)
248 {
249         if (qdev->current_page != 0)
250                 ql_set_register_page(qdev,0);
251         writel(value, reg);
252         readl(reg);
253         return;
254 }
255
256 /*
257  * Caller holds hw_lock. Only called during init.
258  */
259 static void ql_write_page1_reg(struct ql3_adapter *qdev,
260                                u32 __iomem *reg, u32 value)
261 {
262         if (qdev->current_page != 1)
263                 ql_set_register_page(qdev,1);
264         writel(value, reg);
265         readl(reg);
266         return;
267 }
268
269 /*
270  * Caller holds hw_lock. Only called during init.
271  */
272 static void ql_write_page2_reg(struct ql3_adapter *qdev,
273                                u32 __iomem *reg, u32 value)
274 {
275         if (qdev->current_page != 2)
276                 ql_set_register_page(qdev,2);
277         writel(value, reg);
278         readl(reg);
279         return;
280 }
281
282 static void ql_disable_interrupts(struct ql3_adapter *qdev)
283 {
284         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
285
286         ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
287                             (ISP_IMR_ENABLE_INT << 16));
288
289 }
290
291 static void ql_enable_interrupts(struct ql3_adapter *qdev)
292 {
293         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
294
295         ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
296                             ((0xff << 16) | ISP_IMR_ENABLE_INT));
297
298 }
299
300 static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
301                                             struct ql_rcv_buf_cb *lrg_buf_cb)
302 {
303         dma_addr_t map;
304         int err;
305         lrg_buf_cb->next = NULL;
306
307         if (qdev->lrg_buf_free_tail == NULL) {  /* The list is empty  */
308                 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
309         } else {
310                 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
311                 qdev->lrg_buf_free_tail = lrg_buf_cb;
312         }
313
314         if (!lrg_buf_cb->skb) {
315                 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
316                                                    qdev->lrg_buffer_len);
317                 if (unlikely(!lrg_buf_cb->skb)) {
318                         printk(KERN_ERR PFX "%s: failed netdev_alloc_skb().\n",
319                                qdev->ndev->name);
320                         qdev->lrg_buf_skb_check++;
321                 } else {
322                         /*
323                          * We save some space to copy the ethhdr from first
324                          * buffer
325                          */
326                         skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
327                         map = pci_map_single(qdev->pdev,
328                                              lrg_buf_cb->skb->data,
329                                              qdev->lrg_buffer_len -
330                                              QL_HEADER_SPACE,
331                                              PCI_DMA_FROMDEVICE);
332                         err = pci_dma_mapping_error(map);
333                         if(err) {
334                                 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n", 
335                                        qdev->ndev->name, err);
336                                 dev_kfree_skb(lrg_buf_cb->skb);
337                                 lrg_buf_cb->skb = NULL;
338
339                                 qdev->lrg_buf_skb_check++;
340                                 return;
341                         }
342
343                         lrg_buf_cb->buf_phy_addr_low =
344                             cpu_to_le32(LS_64BITS(map));
345                         lrg_buf_cb->buf_phy_addr_high =
346                             cpu_to_le32(MS_64BITS(map));
347                         pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
348                         pci_unmap_len_set(lrg_buf_cb, maplen,
349                                           qdev->lrg_buffer_len -
350                                           QL_HEADER_SPACE);
351                 }
352         }
353
354         qdev->lrg_buf_free_count++;
355 }
356
357 static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
358                                                            *qdev)
359 {
360         struct ql_rcv_buf_cb *lrg_buf_cb;
361
362         if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) {
363                 if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL)
364                         qdev->lrg_buf_free_tail = NULL;
365                 qdev->lrg_buf_free_count--;
366         }
367
368         return lrg_buf_cb;
369 }
370
371 static u32 addrBits = EEPROM_NO_ADDR_BITS;
372 static u32 dataBits = EEPROM_NO_DATA_BITS;
373
374 static void fm93c56a_deselect(struct ql3_adapter *qdev);
375 static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
376                             unsigned short *value);
377
378 /*
379  * Caller holds hw_lock.
380  */
381 static void fm93c56a_select(struct ql3_adapter *qdev)
382 {
383         struct ql3xxx_port_registers __iomem *port_regs =
384                         qdev->mem_map_registers;
385
386         qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
387         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
388                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
389         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
390                             ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
391 }
392
393 /*
394  * Caller holds hw_lock.
395  */
396 static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
397 {
398         int i;
399         u32 mask;
400         u32 dataBit;
401         u32 previousBit;
402         struct ql3xxx_port_registers __iomem *port_regs =
403                         qdev->mem_map_registers;
404
405         /* Clock in a zero, then do the start bit */
406         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
407                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
408                             AUBURN_EEPROM_DO_1);
409         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
410                             ISP_NVRAM_MASK | qdev->
411                             eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
412                             AUBURN_EEPROM_CLK_RISE);
413         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
414                             ISP_NVRAM_MASK | qdev->
415                             eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
416                             AUBURN_EEPROM_CLK_FALL);
417
418         mask = 1 << (FM93C56A_CMD_BITS - 1);
419         /* Force the previous data bit to be different */
420         previousBit = 0xffff;
421         for (i = 0; i < FM93C56A_CMD_BITS; i++) {
422                 dataBit =
423                     (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0;
424                 if (previousBit != dataBit) {
425                         /*
426                          * If the bit changed, then change the DO state to
427                          * match
428                          */
429                         ql_write_nvram_reg(qdev,
430                                             &port_regs->CommonRegs.
431                                             serialPortInterfaceReg,
432                                             ISP_NVRAM_MASK | qdev->
433                                             eeprom_cmd_data | dataBit);
434                         previousBit = dataBit;
435                 }
436                 ql_write_nvram_reg(qdev,
437                                     &port_regs->CommonRegs.
438                                     serialPortInterfaceReg,
439                                     ISP_NVRAM_MASK | qdev->
440                                     eeprom_cmd_data | dataBit |
441                                     AUBURN_EEPROM_CLK_RISE);
442                 ql_write_nvram_reg(qdev,
443                                     &port_regs->CommonRegs.
444                                     serialPortInterfaceReg,
445                                     ISP_NVRAM_MASK | qdev->
446                                     eeprom_cmd_data | dataBit |
447                                     AUBURN_EEPROM_CLK_FALL);
448                 cmd = cmd << 1;
449         }
450
451         mask = 1 << (addrBits - 1);
452         /* Force the previous data bit to be different */
453         previousBit = 0xffff;
454         for (i = 0; i < addrBits; i++) {
455                 dataBit =
456                     (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 :
457                     AUBURN_EEPROM_DO_0;
458                 if (previousBit != dataBit) {
459                         /*
460                          * If the bit changed, then change the DO state to
461                          * match
462                          */
463                         ql_write_nvram_reg(qdev,
464                                             &port_regs->CommonRegs.
465                                             serialPortInterfaceReg,
466                                             ISP_NVRAM_MASK | qdev->
467                                             eeprom_cmd_data | dataBit);
468                         previousBit = dataBit;
469                 }
470                 ql_write_nvram_reg(qdev,
471                                     &port_regs->CommonRegs.
472                                     serialPortInterfaceReg,
473                                     ISP_NVRAM_MASK | qdev->
474                                     eeprom_cmd_data | dataBit |
475                                     AUBURN_EEPROM_CLK_RISE);
476                 ql_write_nvram_reg(qdev,
477                                     &port_regs->CommonRegs.
478                                     serialPortInterfaceReg,
479                                     ISP_NVRAM_MASK | qdev->
480                                     eeprom_cmd_data | dataBit |
481                                     AUBURN_EEPROM_CLK_FALL);
482                 eepromAddr = eepromAddr << 1;
483         }
484 }
485
486 /*
487  * Caller holds hw_lock.
488  */
489 static void fm93c56a_deselect(struct ql3_adapter *qdev)
490 {
491         struct ql3xxx_port_registers __iomem *port_regs =
492                         qdev->mem_map_registers;
493         qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
494         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
495                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
496 }
497
498 /*
499  * Caller holds hw_lock.
500  */
501 static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
502 {
503         int i;
504         u32 data = 0;
505         u32 dataBit;
506         struct ql3xxx_port_registers __iomem *port_regs =
507                         qdev->mem_map_registers;
508
509         /* Read the data bits */
510         /* The first bit is a dummy.  Clock right over it. */
511         for (i = 0; i < dataBits; i++) {
512                 ql_write_nvram_reg(qdev,
513                                     &port_regs->CommonRegs.
514                                     serialPortInterfaceReg,
515                                     ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
516                                     AUBURN_EEPROM_CLK_RISE);
517                 ql_write_nvram_reg(qdev,
518                                     &port_regs->CommonRegs.
519                                     serialPortInterfaceReg,
520                                     ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
521                                     AUBURN_EEPROM_CLK_FALL);
522                 dataBit =
523                     (ql_read_common_reg
524                      (qdev,
525                       &port_regs->CommonRegs.
526                       serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0;
527                 data = (data << 1) | dataBit;
528         }
529         *value = (u16) data;
530 }
531
532 /*
533  * Caller holds hw_lock.
534  */
535 static void eeprom_readword(struct ql3_adapter *qdev,
536                             u32 eepromAddr, unsigned short *value)
537 {
538         fm93c56a_select(qdev);
539         fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
540         fm93c56a_datain(qdev, value);
541         fm93c56a_deselect(qdev);
542 }
543
544 static void ql_swap_mac_addr(u8 * macAddress)
545 {
546 #ifdef __BIG_ENDIAN
547         u8 temp;
548         temp = macAddress[0];
549         macAddress[0] = macAddress[1];
550         macAddress[1] = temp;
551         temp = macAddress[2];
552         macAddress[2] = macAddress[3];
553         macAddress[3] = temp;
554         temp = macAddress[4];
555         macAddress[4] = macAddress[5];
556         macAddress[5] = temp;
557 #endif
558 }
559
560 static int ql_get_nvram_params(struct ql3_adapter *qdev)
561 {
562         u16 *pEEPROMData;
563         u16 checksum = 0;
564         u32 index;
565         unsigned long hw_flags;
566
567         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
568
569         pEEPROMData = (u16 *) & qdev->nvram_data;
570         qdev->eeprom_cmd_data = 0;
571         if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
572                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
573                          2) << 10)) {
574                 printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n",
575                         __func__);
576                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
577                 return -1;
578         }
579
580         for (index = 0; index < EEPROM_SIZE; index++) {
581                 eeprom_readword(qdev, index, pEEPROMData);
582                 checksum += *pEEPROMData;
583                 pEEPROMData++;
584         }
585         ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
586
587         if (checksum != 0) {
588                 printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n",
589                        qdev->ndev->name, checksum);
590                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
591                 return -1;
592         }
593
594         /*
595          * We have a problem with endianness for the MAC addresses
596          * and the two 8-bit values version, and numPorts.  We
597          * have to swap them on big endian systems.
598          */
599         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn0.macAddress);
600         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn1.macAddress);
601         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn2.macAddress);
602         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn3.macAddress);
603         pEEPROMData = (u16 *) & qdev->nvram_data.version;
604         *pEEPROMData = le16_to_cpu(*pEEPROMData);
605
606         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
607         return checksum;
608 }
609
610 static const u32 PHYAddr[2] = {
611         PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
612 };
613
614 static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
615 {
616         struct ql3xxx_port_registers __iomem *port_regs =
617                         qdev->mem_map_registers;
618         u32 temp;
619         int count = 1000;
620
621         while (count) {
622                 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
623                 if (!(temp & MAC_MII_STATUS_BSY))
624                         return 0;
625                 udelay(10);
626                 count--;
627         }
628         return -1;
629 }
630
631 static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
632 {
633         struct ql3xxx_port_registers __iomem *port_regs =
634                         qdev->mem_map_registers;
635         u32 scanControl;
636
637         if (qdev->numPorts > 1) {
638                 /* Auto scan will cycle through multiple ports */
639                 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
640         } else {
641                 scanControl = MAC_MII_CONTROL_SC;
642         }
643
644         /*
645          * Scan register 1 of PHY/PETBI,
646          * Set up to scan both devices
647          * The autoscan starts from the first register, completes
648          * the last one before rolling over to the first
649          */
650         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
651                            PHYAddr[0] | MII_SCAN_REGISTER);
652
653         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
654                            (scanControl) |
655                            ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
656 }
657
658 static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
659 {
660         u8 ret;
661         struct ql3xxx_port_registers __iomem *port_regs =
662                                         qdev->mem_map_registers;
663
664         /* See if scan mode is enabled before we turn it off */
665         if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
666             (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
667                 /* Scan is enabled */
668                 ret = 1;
669         } else {
670                 /* Scan is disabled */
671                 ret = 0;
672         }
673
674         /*
675          * When disabling scan mode you must first change the MII register
676          * address
677          */
678         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
679                            PHYAddr[0] | MII_SCAN_REGISTER);
680
681         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
682                            ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
683                              MAC_MII_CONTROL_RC) << 16));
684
685         return ret;
686 }
687
688 static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
689                                u16 regAddr, u16 value, u32 phyAddr)
690 {
691         struct ql3xxx_port_registers __iomem *port_regs =
692                         qdev->mem_map_registers;
693         u8 scanWasEnabled;
694
695         scanWasEnabled = ql_mii_disable_scan_mode(qdev);
696
697         if (ql_wait_for_mii_ready(qdev)) {
698                 if (netif_msg_link(qdev))
699                         printk(KERN_WARNING PFX
700                                "%s Timed out waiting for management port to "
701                                "get free before issuing command.\n",
702                                qdev->ndev->name);
703                 return -1;
704         }
705
706         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
707                            phyAddr | regAddr);
708
709         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
710
711         /* Wait for write to complete 9/10/04 SJP */
712         if (ql_wait_for_mii_ready(qdev)) {
713                 if (netif_msg_link(qdev))
714                         printk(KERN_WARNING PFX
715                                "%s: Timed out waiting for management port to"
716                                "get free before issuing command.\n",
717                                qdev->ndev->name);
718                 return -1;
719         }
720
721         if (scanWasEnabled)
722                 ql_mii_enable_scan_mode(qdev);
723
724         return 0;
725 }
726
727 static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
728                               u16 * value, u32 phyAddr)
729 {
730         struct ql3xxx_port_registers __iomem *port_regs =
731                         qdev->mem_map_registers;
732         u8 scanWasEnabled;
733         u32 temp;
734
735         scanWasEnabled = ql_mii_disable_scan_mode(qdev);
736
737         if (ql_wait_for_mii_ready(qdev)) {
738                 if (netif_msg_link(qdev))
739                         printk(KERN_WARNING PFX
740                                "%s: Timed out waiting for management port to "
741                                "get free before issuing command.\n",
742                                qdev->ndev->name);
743                 return -1;
744         }
745
746         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
747                            phyAddr | regAddr);
748
749         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
750                            (MAC_MII_CONTROL_RC << 16));
751
752         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
753                            (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
754
755         /* Wait for the read to complete */
756         if (ql_wait_for_mii_ready(qdev)) {
757                 if (netif_msg_link(qdev))
758                         printk(KERN_WARNING PFX
759                                "%s: Timed out waiting for management port to "
760                                "get free after issuing command.\n",
761                                qdev->ndev->name);
762                 return -1;
763         }
764
765         temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
766         *value = (u16) temp;
767
768         if (scanWasEnabled)
769                 ql_mii_enable_scan_mode(qdev);
770
771         return 0;
772 }
773
774 static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
775 {
776         struct ql3xxx_port_registers __iomem *port_regs =
777                         qdev->mem_map_registers;
778
779         ql_mii_disable_scan_mode(qdev);
780
781         if (ql_wait_for_mii_ready(qdev)) {
782                 if (netif_msg_link(qdev))
783                         printk(KERN_WARNING PFX
784                                "%s: Timed out waiting for management port to "
785                                "get free before issuing command.\n",
786                                qdev->ndev->name);
787                 return -1;
788         }
789
790         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
791                            qdev->PHYAddr | regAddr);
792
793         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
794
795         /* Wait for write to complete. */
796         if (ql_wait_for_mii_ready(qdev)) {
797                 if (netif_msg_link(qdev))
798                         printk(KERN_WARNING PFX
799                                "%s: Timed out waiting for management port to "
800                                "get free before issuing command.\n",
801                                qdev->ndev->name);
802                 return -1;
803         }
804
805         ql_mii_enable_scan_mode(qdev);
806
807         return 0;
808 }
809
810 static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
811 {
812         u32 temp;
813         struct ql3xxx_port_registers __iomem *port_regs =
814                         qdev->mem_map_registers;
815
816         ql_mii_disable_scan_mode(qdev);
817
818         if (ql_wait_for_mii_ready(qdev)) {
819                 if (netif_msg_link(qdev))
820                         printk(KERN_WARNING PFX
821                                "%s: Timed out waiting for management port to "
822                                "get free before issuing command.\n",
823                                qdev->ndev->name);
824                 return -1;
825         }
826
827         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
828                            qdev->PHYAddr | regAddr);
829
830         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
831                            (MAC_MII_CONTROL_RC << 16));
832
833         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
834                            (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
835
836         /* Wait for the read to complete */
837         if (ql_wait_for_mii_ready(qdev)) {
838                 if (netif_msg_link(qdev))
839                         printk(KERN_WARNING PFX
840                                "%s: Timed out waiting for management port to "
841                                "get free before issuing command.\n",
842                                qdev->ndev->name);
843                 return -1;
844         }
845
846         temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
847         *value = (u16) temp;
848
849         ql_mii_enable_scan_mode(qdev);
850
851         return 0;
852 }
853
854 static void ql_petbi_reset(struct ql3_adapter *qdev)
855 {
856         ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
857 }
858
859 static void ql_petbi_start_neg(struct ql3_adapter *qdev)
860 {
861         u16 reg;
862
863         /* Enable Auto-negotiation sense */
864         ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
865         reg |= PETBI_TBI_AUTO_SENSE;
866         ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
867
868         ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
869                          PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
870
871         ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
872                          PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
873                          PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
874
875 }
876
877 static void ql_petbi_reset_ex(struct ql3_adapter *qdev)
878 {
879         ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
880                             PHYAddr[qdev->mac_index]);
881 }
882
883 static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev)
884 {
885         u16 reg;
886
887         /* Enable Auto-negotiation sense */
888         ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg, 
889                            PHYAddr[qdev->mac_index]);
890         reg |= PETBI_TBI_AUTO_SENSE;
891         ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg, 
892                             PHYAddr[qdev->mac_index]);
893
894         ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
895                             PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX, 
896                             PHYAddr[qdev->mac_index]);
897
898         ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
899                             PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
900                             PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
901                             PHYAddr[qdev->mac_index]);
902 }
903
904 static void ql_petbi_init(struct ql3_adapter *qdev)
905 {
906         ql_petbi_reset(qdev);
907         ql_petbi_start_neg(qdev);
908 }
909
910 static void ql_petbi_init_ex(struct ql3_adapter *qdev)
911 {
912         ql_petbi_reset_ex(qdev);
913         ql_petbi_start_neg_ex(qdev);
914 }
915
916 static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
917 {
918         u16 reg;
919
920         if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
921                 return 0;
922
923         return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
924 }
925
926 static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)
927 {
928         printk(KERN_INFO "%s: enabling Agere specific PHY\n", qdev->ndev->name);
929         /* power down device bit 11 = 1 */
930         ql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr);
931         /* enable diagnostic mode bit 2 = 1 */
932         ql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr);
933         /* 1000MB amplitude adjust (see Agere errata) */
934         ql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr);
935         /* 1000MB amplitude adjust (see Agere errata) */
936         ql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr);
937         /* 100MB amplitude adjust (see Agere errata) */
938         ql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr);
939         /* 100MB amplitude adjust (see Agere errata) */
940         ql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr);
941         /* 10MB amplitude adjust (see Agere errata) */
942         ql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr);
943         /* 10MB amplitude adjust (see Agere errata) */
944         ql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr);
945         /* point to hidden reg 0x2806 */
946         ql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr);
947         /* Write new PHYAD w/bit 5 set */
948         ql_mii_write_reg_ex(qdev, 0x11, 0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr);
949         /* 
950          * Disable diagnostic mode bit 2 = 0
951          * Power up device bit 11 = 0
952          * Link up (on) and activity (blink)
953          */
954         ql_mii_write_reg(qdev, 0x12, 0x840a);
955         ql_mii_write_reg(qdev, 0x00, 0x1140);
956         ql_mii_write_reg(qdev, 0x1c, 0xfaf0);
957 }
958
959 static PHY_DEVICE_et getPhyType (struct ql3_adapter *qdev, 
960                                  u16 phyIdReg0, u16 phyIdReg1)
961 {
962         PHY_DEVICE_et result = PHY_TYPE_UNKNOWN;
963         u32   oui;     
964         u16   model;
965         int i;   
966
967         if (phyIdReg0 == 0xffff) {
968                 return result;
969         }
970    
971         if (phyIdReg1 == 0xffff) {
972                 return result;
973         }
974
975         /* oui is split between two registers */
976         oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10);
977
978         model = (phyIdReg1 & PHY_MODEL_MASK) >> 4;
979
980         /* Scan table for this PHY */
981         for(i = 0; i < MAX_PHY_DEV_TYPES; i++) {
982                 if ((oui == PHY_DEVICES[i].phyIdOUI) && (model == PHY_DEVICES[i].phyIdModel))
983                 {
984                         result = PHY_DEVICES[i].phyDevice;
985
986                         printk(KERN_INFO "%s: Phy: %s\n",
987                                 qdev->ndev->name, PHY_DEVICES[i].name);
988                         
989                         break;
990                 }
991         }
992
993         return result;
994 }
995
996 static int ql_phy_get_speed(struct ql3_adapter *qdev)
997 {
998         u16 reg;
999
1000         switch(qdev->phyType) {
1001         case PHY_AGERE_ET1011C:
1002         {
1003                 if (ql_mii_read_reg(qdev, 0x1A, &reg) < 0)
1004                         return 0;
1005
1006                 reg = (reg >> 8) & 3;
1007                 break;
1008         }
1009         default:
1010         if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
1011                 return 0;
1012
1013         reg = (((reg & 0x18) >> 3) & 3);
1014         }
1015
1016         switch(reg) {
1017                 case 2:
1018                 return SPEED_1000;
1019                 case 1:
1020                 return SPEED_100;
1021                 case 0:
1022                 return SPEED_10;
1023                 default:
1024                 return -1;
1025         }
1026 }
1027
1028 static int ql_is_full_dup(struct ql3_adapter *qdev)
1029 {
1030         u16 reg;
1031
1032         switch(qdev->phyType) {
1033         case PHY_AGERE_ET1011C:
1034         {
1035                 if (ql_mii_read_reg(qdev, 0x1A, &reg))
1036                         return 0;
1037                         
1038                 return ((reg & 0x0080) && (reg & 0x1000)) != 0;
1039         }
1040         case PHY_VITESSE_VSC8211:
1041         default:
1042         {
1043                 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
1044                         return 0;
1045                 return (reg & PHY_AUX_DUPLEX_STAT) != 0;
1046         }
1047         }
1048 }
1049
1050 static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
1051 {
1052         u16 reg;
1053
1054         if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
1055                 return 0;
1056
1057         return (reg & PHY_NEG_PAUSE) != 0;
1058 }
1059
1060 static int PHY_Setup(struct ql3_adapter *qdev)
1061 {
1062         u16   reg1;
1063         u16   reg2;
1064         bool  agereAddrChangeNeeded = false;
1065         u32 miiAddr = 0;
1066         int err;
1067
1068         /*  Determine the PHY we are using by reading the ID's */
1069         err = ql_mii_read_reg(qdev, PHY_ID_0_REG, &reg1);
1070         if(err != 0) {
1071                 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n",
1072                        qdev->ndev->name);
1073                 return err;
1074         }
1075
1076         err = ql_mii_read_reg(qdev, PHY_ID_1_REG, &reg2);
1077         if(err != 0) {
1078                 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n",
1079                        qdev->ndev->name);
1080                 return err;
1081         }
1082
1083         /*  Check if we have a Agere PHY */
1084         if ((reg1 == 0xffff) || (reg2 == 0xffff)) {
1085
1086                 /* Determine which MII address we should be using 
1087                    determined by the index of the card */
1088                 if (qdev->mac_index == 0) {
1089                         miiAddr = MII_AGERE_ADDR_1;
1090                 } else {
1091                         miiAddr = MII_AGERE_ADDR_2;
1092                 }
1093       
1094                 err =ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, &reg1, miiAddr);
1095                 if(err != 0) {
1096                         printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n",
1097                                qdev->ndev->name);
1098                         return err; 
1099                 }
1100
1101                 err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, &reg2, miiAddr);
1102                 if(err != 0) {
1103                         printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n",
1104                                qdev->ndev->name);
1105                         return err;
1106                 }
1107    
1108                 /*  We need to remember to initialize the Agere PHY */
1109                 agereAddrChangeNeeded = true; 
1110         }
1111
1112         /*  Determine the particular PHY we have on board to apply
1113             PHY specific initializations */
1114         qdev->phyType = getPhyType(qdev, reg1, reg2);
1115
1116         if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) {
1117                 /* need this here so address gets changed */
1118                 phyAgereSpecificInit(qdev, miiAddr);  
1119         } else if (qdev->phyType == PHY_TYPE_UNKNOWN) {
1120                 printk(KERN_ERR "%s: PHY is unknown\n", qdev->ndev->name);
1121                 return -EIO;
1122         }
1123
1124         return 0;
1125 }
1126
1127 /*
1128  * Caller holds hw_lock.
1129  */
1130 static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
1131 {
1132         struct ql3xxx_port_registers __iomem *port_regs =
1133                         qdev->mem_map_registers;
1134         u32 value;
1135
1136         if (enable)
1137                 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
1138         else
1139                 value = (MAC_CONFIG_REG_PE << 16);
1140
1141         if (qdev->mac_index)
1142                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1143         else
1144                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1145 }
1146
1147 /*
1148  * Caller holds hw_lock.
1149  */
1150 static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
1151 {
1152         struct ql3xxx_port_registers __iomem *port_regs =
1153                         qdev->mem_map_registers;
1154         u32 value;
1155
1156         if (enable)
1157                 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
1158         else
1159                 value = (MAC_CONFIG_REG_SR << 16);
1160
1161         if (qdev->mac_index)
1162                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1163         else
1164                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1165 }
1166
1167 /*
1168  * Caller holds hw_lock.
1169  */
1170 static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
1171 {
1172         struct ql3xxx_port_registers __iomem *port_regs =
1173                         qdev->mem_map_registers;
1174         u32 value;
1175
1176         if (enable)
1177                 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
1178         else
1179                 value = (MAC_CONFIG_REG_GM << 16);
1180
1181         if (qdev->mac_index)
1182                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1183         else
1184                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1185 }
1186
1187 /*
1188  * Caller holds hw_lock.
1189  */
1190 static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1191 {
1192         struct ql3xxx_port_registers __iomem *port_regs =
1193                         qdev->mem_map_registers;
1194         u32 value;
1195
1196         if (enable)
1197                 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1198         else
1199                 value = (MAC_CONFIG_REG_FD << 16);
1200
1201         if (qdev->mac_index)
1202                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1203         else
1204                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1205 }
1206
1207 /*
1208  * Caller holds hw_lock.
1209  */
1210 static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1211 {
1212         struct ql3xxx_port_registers __iomem *port_regs =
1213                         qdev->mem_map_registers;
1214         u32 value;
1215
1216         if (enable)
1217                 value =
1218                     ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1219                      ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1220         else
1221                 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1222
1223         if (qdev->mac_index)
1224                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1225         else
1226                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1227 }
1228
1229 /*
1230  * Caller holds hw_lock.
1231  */
1232 static int ql_is_fiber(struct ql3_adapter *qdev)
1233 {
1234         struct ql3xxx_port_registers __iomem *port_regs =
1235                         qdev->mem_map_registers;
1236         u32 bitToCheck = 0;
1237         u32 temp;
1238
1239         switch (qdev->mac_index) {
1240         case 0:
1241                 bitToCheck = PORT_STATUS_SM0;
1242                 break;
1243         case 1:
1244                 bitToCheck = PORT_STATUS_SM1;
1245                 break;
1246         }
1247
1248         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1249         return (temp & bitToCheck) != 0;
1250 }
1251
1252 static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1253 {
1254         u16 reg;
1255         ql_mii_read_reg(qdev, 0x00, &reg);
1256         return (reg & 0x1000) != 0;
1257 }
1258
1259 /*
1260  * Caller holds hw_lock.
1261  */
1262 static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1263 {
1264         struct ql3xxx_port_registers __iomem *port_regs =
1265                         qdev->mem_map_registers;
1266         u32 bitToCheck = 0;
1267         u32 temp;
1268
1269         switch (qdev->mac_index) {
1270         case 0:
1271                 bitToCheck = PORT_STATUS_AC0;
1272                 break;
1273         case 1:
1274                 bitToCheck = PORT_STATUS_AC1;
1275                 break;
1276         }
1277
1278         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1279         if (temp & bitToCheck) {
1280                 if (netif_msg_link(qdev))
1281                         printk(KERN_INFO PFX
1282                                "%s: Auto-Negotiate complete.\n",
1283                                qdev->ndev->name);
1284                 return 1;
1285         } else {
1286                 if (netif_msg_link(qdev))
1287                         printk(KERN_WARNING PFX
1288                                "%s: Auto-Negotiate incomplete.\n",
1289                                qdev->ndev->name);
1290                 return 0;
1291         }
1292 }
1293
1294 /*
1295  *  ql_is_neg_pause() returns 1 if pause was negotiated to be on
1296  */
1297 static int ql_is_neg_pause(struct ql3_adapter *qdev)
1298 {
1299         if (ql_is_fiber(qdev))
1300                 return ql_is_petbi_neg_pause(qdev);
1301         else
1302                 return ql_is_phy_neg_pause(qdev);
1303 }
1304
1305 static int ql_auto_neg_error(struct ql3_adapter *qdev)
1306 {
1307         struct ql3xxx_port_registers __iomem *port_regs =
1308                         qdev->mem_map_registers;
1309         u32 bitToCheck = 0;
1310         u32 temp;
1311
1312         switch (qdev->mac_index) {
1313         case 0:
1314                 bitToCheck = PORT_STATUS_AE0;
1315                 break;
1316         case 1:
1317                 bitToCheck = PORT_STATUS_AE1;
1318                 break;
1319         }
1320         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1321         return (temp & bitToCheck) != 0;
1322 }
1323
1324 static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1325 {
1326         if (ql_is_fiber(qdev))
1327                 return SPEED_1000;
1328         else
1329                 return ql_phy_get_speed(qdev);
1330 }
1331
1332 static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1333 {
1334         if (ql_is_fiber(qdev))
1335                 return 1;
1336         else
1337                 return ql_is_full_dup(qdev);
1338 }
1339
1340 /*
1341  * Caller holds hw_lock.
1342  */
1343 static int ql_link_down_detect(struct ql3_adapter *qdev)
1344 {
1345         struct ql3xxx_port_registers __iomem *port_regs =
1346                         qdev->mem_map_registers;
1347         u32 bitToCheck = 0;
1348         u32 temp;
1349
1350         switch (qdev->mac_index) {
1351         case 0:
1352                 bitToCheck = ISP_CONTROL_LINK_DN_0;
1353                 break;
1354         case 1:
1355                 bitToCheck = ISP_CONTROL_LINK_DN_1;
1356                 break;
1357         }
1358
1359         temp =
1360             ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1361         return (temp & bitToCheck) != 0;
1362 }
1363
1364 /*
1365  * Caller holds hw_lock.
1366  */
1367 static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1368 {
1369         struct ql3xxx_port_registers __iomem *port_regs =
1370                         qdev->mem_map_registers;
1371
1372         switch (qdev->mac_index) {
1373         case 0:
1374                 ql_write_common_reg(qdev,
1375                                     &port_regs->CommonRegs.ispControlStatus,
1376                                     (ISP_CONTROL_LINK_DN_0) |
1377                                     (ISP_CONTROL_LINK_DN_0 << 16));
1378                 break;
1379
1380         case 1:
1381                 ql_write_common_reg(qdev,
1382                                     &port_regs->CommonRegs.ispControlStatus,
1383                                     (ISP_CONTROL_LINK_DN_1) |
1384                                     (ISP_CONTROL_LINK_DN_1 << 16));
1385                 break;
1386
1387         default:
1388                 return 1;
1389         }
1390
1391         return 0;
1392 }
1393
1394 /*
1395  * Caller holds hw_lock.
1396  */
1397 static int ql_this_adapter_controls_port(struct ql3_adapter *qdev)
1398 {
1399         struct ql3xxx_port_registers __iomem *port_regs =
1400                         qdev->mem_map_registers;
1401         u32 bitToCheck = 0;
1402         u32 temp;
1403
1404         switch (qdev->mac_index) {
1405         case 0:
1406                 bitToCheck = PORT_STATUS_F1_ENABLED;
1407                 break;
1408         case 1:
1409                 bitToCheck = PORT_STATUS_F3_ENABLED;
1410                 break;
1411         default:
1412                 break;
1413         }
1414
1415         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1416         if (temp & bitToCheck) {
1417                 if (netif_msg_link(qdev))
1418                         printk(KERN_DEBUG PFX
1419                                "%s: is not link master.\n", qdev->ndev->name);
1420                 return 0;
1421         } else {
1422                 if (netif_msg_link(qdev))
1423                         printk(KERN_DEBUG PFX
1424                                "%s: is link master.\n", qdev->ndev->name);
1425                 return 1;
1426         }
1427 }
1428
1429 static void ql_phy_reset_ex(struct ql3_adapter *qdev)
1430 {
1431         ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET, 
1432                             PHYAddr[qdev->mac_index]);
1433 }
1434
1435 static void ql_phy_start_neg_ex(struct ql3_adapter *qdev)
1436 {
1437         u16 reg;
1438         u16 portConfiguration;
1439
1440         if(qdev->phyType == PHY_AGERE_ET1011C) {
1441                 /* turn off external loopback */
1442                 ql_mii_write_reg(qdev, 0x13, 0x0000); 
1443         }
1444
1445         if(qdev->mac_index == 0)
1446                 portConfiguration = qdev->nvram_data.macCfg_port0.portConfiguration;
1447         else
1448                 portConfiguration = qdev->nvram_data.macCfg_port1.portConfiguration;
1449
1450         /*  Some HBA's in the field are set to 0 and they need to
1451             be reinterpreted with a default value */
1452         if(portConfiguration == 0)
1453                 portConfiguration = PORT_CONFIG_DEFAULT;
1454
1455         /* Set the 1000 advertisements */
1456         ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, &reg, 
1457                            PHYAddr[qdev->mac_index]);
1458         reg &= ~PHY_GIG_ALL_PARAMS;
1459
1460         if(portConfiguration & 
1461            PORT_CONFIG_FULL_DUPLEX_ENABLED &
1462            PORT_CONFIG_1000MB_SPEED) {
1463                 reg |= PHY_GIG_ADV_1000F;
1464         }
1465          
1466         if(portConfiguration & 
1467            PORT_CONFIG_HALF_DUPLEX_ENABLED &
1468            PORT_CONFIG_1000MB_SPEED) {
1469                 reg |= PHY_GIG_ADV_1000H;
1470         }
1471
1472         ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg, 
1473                             PHYAddr[qdev->mac_index]);
1474
1475         /* Set the 10/100 & pause negotiation advertisements */
1476         ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, &reg,
1477                            PHYAddr[qdev->mac_index]);
1478         reg &= ~PHY_NEG_ALL_PARAMS;
1479
1480         if(portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED)
1481                 reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE;
1482
1483         if(portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) {
1484                 if(portConfiguration & PORT_CONFIG_100MB_SPEED)
1485                         reg |= PHY_NEG_ADV_100F;
1486                 
1487                 if(portConfiguration & PORT_CONFIG_10MB_SPEED)
1488                         reg |= PHY_NEG_ADV_10F;
1489         }
1490
1491         if(portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) {
1492                 if(portConfiguration & PORT_CONFIG_100MB_SPEED)
1493                         reg |= PHY_NEG_ADV_100H;
1494                 
1495                 if(portConfiguration & PORT_CONFIG_10MB_SPEED)
1496                         reg |= PHY_NEG_ADV_10H;
1497         }
1498
1499         if(portConfiguration &
1500            PORT_CONFIG_1000MB_SPEED) {
1501                 reg |= 1;       
1502         }
1503
1504         ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg, 
1505                             PHYAddr[qdev->mac_index]);
1506
1507         ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, PHYAddr[qdev->mac_index]);
1508         
1509         ql_mii_write_reg_ex(qdev, CONTROL_REG, 
1510                             reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG,
1511                             PHYAddr[qdev->mac_index]);
1512 }
1513
1514 static void ql_phy_init_ex(struct ql3_adapter *qdev)
1515 {
1516         ql_phy_reset_ex(qdev);
1517         PHY_Setup(qdev);
1518         ql_phy_start_neg_ex(qdev);
1519 }
1520
1521 /*
1522  * Caller holds hw_lock.
1523  */
1524 static u32 ql_get_link_state(struct ql3_adapter *qdev)
1525 {
1526         struct ql3xxx_port_registers __iomem *port_regs =
1527                         qdev->mem_map_registers;
1528         u32 bitToCheck = 0;
1529         u32 temp, linkState;
1530
1531         switch (qdev->mac_index) {
1532         case 0:
1533                 bitToCheck = PORT_STATUS_UP0;
1534                 break;
1535         case 1:
1536                 bitToCheck = PORT_STATUS_UP1;
1537                 break;
1538         }
1539         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1540         if (temp & bitToCheck) {
1541                 linkState = LS_UP;
1542         } else {
1543                 linkState = LS_DOWN;
1544                 if (netif_msg_link(qdev))
1545                         printk(KERN_WARNING PFX
1546                                "%s: Link is down.\n", qdev->ndev->name);
1547         }
1548         return linkState;
1549 }
1550
1551 static int ql_port_start(struct ql3_adapter *qdev)
1552 {
1553         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1554                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1555                          2) << 7)) {
1556                 printk(KERN_ERR "%s: Could not get hw lock for GIO\n",
1557                        qdev->ndev->name);
1558                 return -1;
1559         }
1560
1561         if (ql_is_fiber(qdev)) {
1562                 ql_petbi_init(qdev);
1563         } else {
1564                 /* Copper port */
1565                 ql_phy_init_ex(qdev);
1566         }
1567
1568         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1569         return 0;
1570 }
1571
1572 static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1573 {
1574
1575         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1576                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1577                          2) << 7))
1578                 return -1;
1579
1580         if (!ql_auto_neg_error(qdev)) {
1581                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1582                         /* configure the MAC */
1583                         if (netif_msg_link(qdev))
1584                                 printk(KERN_DEBUG PFX
1585                                        "%s: Configuring link.\n",
1586                                        qdev->ndev->
1587                                        name);
1588                         ql_mac_cfg_soft_reset(qdev, 1);
1589                         ql_mac_cfg_gig(qdev,
1590                                        (ql_get_link_speed
1591                                         (qdev) ==
1592                                         SPEED_1000));
1593                         ql_mac_cfg_full_dup(qdev,
1594                                             ql_is_link_full_dup
1595                                             (qdev));
1596                         ql_mac_cfg_pause(qdev,
1597                                          ql_is_neg_pause
1598                                          (qdev));
1599                         ql_mac_cfg_soft_reset(qdev, 0);
1600
1601                         /* enable the MAC */
1602                         if (netif_msg_link(qdev))
1603                                 printk(KERN_DEBUG PFX
1604                                        "%s: Enabling mac.\n",
1605                                        qdev->ndev->
1606                                                name);
1607                         ql_mac_enable(qdev, 1);
1608                 }
1609
1610                 if (netif_msg_link(qdev))
1611                         printk(KERN_DEBUG PFX
1612                                "%s: Change port_link_state LS_DOWN to LS_UP.\n",
1613                                qdev->ndev->name);
1614                 qdev->port_link_state = LS_UP;
1615                 netif_start_queue(qdev->ndev);
1616                 netif_carrier_on(qdev->ndev);
1617                 if (netif_msg_link(qdev))
1618                         printk(KERN_INFO PFX
1619                                "%s: Link is up at %d Mbps, %s duplex.\n",
1620                                qdev->ndev->name,
1621                                ql_get_link_speed(qdev),
1622                                ql_is_link_full_dup(qdev)
1623                                ? "full" : "half");
1624
1625         } else {        /* Remote error detected */
1626
1627                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1628                         if (netif_msg_link(qdev))
1629                                 printk(KERN_DEBUG PFX
1630                                        "%s: Remote error detected. "
1631                                        "Calling ql_port_start().\n",
1632                                        qdev->ndev->
1633                                        name);
1634                         /*
1635                          * ql_port_start() is shared code and needs
1636                          * to lock the PHY on it's own.
1637                          */
1638                         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1639                         if(ql_port_start(qdev)) {/* Restart port */
1640                                 return -1;
1641                         } else
1642                                 return 0;
1643                 }
1644         }
1645         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1646         return 0;
1647 }
1648
1649 static void ql_link_state_machine(struct ql3_adapter *qdev)
1650 {
1651         u32 curr_link_state;
1652         unsigned long hw_flags;
1653
1654         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1655
1656         curr_link_state = ql_get_link_state(qdev);
1657
1658         if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
1659                 if (netif_msg_link(qdev))
1660                         printk(KERN_INFO PFX
1661                                "%s: Reset in progress, skip processing link "
1662                                "state.\n", qdev->ndev->name);
1663
1664                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);               
1665                 return;
1666         }
1667
1668         switch (qdev->port_link_state) {
1669         default:
1670                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1671                         ql_port_start(qdev);
1672                 }
1673                 qdev->port_link_state = LS_DOWN;
1674                 /* Fall Through */
1675
1676         case LS_DOWN:
1677                 if (netif_msg_link(qdev))
1678                         printk(KERN_DEBUG PFX
1679                                "%s: port_link_state = LS_DOWN.\n",
1680                                qdev->ndev->name);
1681                 if (curr_link_state == LS_UP) {
1682                         if (netif_msg_link(qdev))
1683                                 printk(KERN_DEBUG PFX
1684                                        "%s: curr_link_state = LS_UP.\n",
1685                                        qdev->ndev->name);
1686                         if (ql_is_auto_neg_complete(qdev))
1687                                 ql_finish_auto_neg(qdev);
1688
1689                         if (qdev->port_link_state == LS_UP)
1690                                 ql_link_down_detect_clear(qdev);
1691
1692                 }
1693                 break;
1694
1695         case LS_UP:
1696                 /*
1697                  * See if the link is currently down or went down and came
1698                  * back up
1699                  */
1700                 if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) {
1701                         if (netif_msg_link(qdev))
1702                                 printk(KERN_INFO PFX "%s: Link is down.\n",
1703                                        qdev->ndev->name);
1704                         qdev->port_link_state = LS_DOWN;
1705                 }
1706                 break;
1707         }
1708         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1709 }
1710
1711 /*
1712  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1713  */
1714 static void ql_get_phy_owner(struct ql3_adapter *qdev)
1715 {
1716         if (ql_this_adapter_controls_port(qdev))
1717                 set_bit(QL_LINK_MASTER,&qdev->flags);
1718         else
1719                 clear_bit(QL_LINK_MASTER,&qdev->flags);
1720 }
1721
1722 /*
1723  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1724  */
1725 static void ql_init_scan_mode(struct ql3_adapter *qdev)
1726 {
1727         ql_mii_enable_scan_mode(qdev);
1728
1729         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1730                 if (ql_this_adapter_controls_port(qdev))
1731                         ql_petbi_init_ex(qdev);
1732         } else {
1733                 if (ql_this_adapter_controls_port(qdev))
1734                         ql_phy_init_ex(qdev);
1735         }
1736 }
1737
1738 /*
1739  * MII_Setup needs to be called before taking the PHY out of reset so that the
1740  * management interface clock speed can be set properly.  It would be better if
1741  * we had a way to disable MDC until after the PHY is out of reset, but we
1742  * don't have that capability.
1743  */
1744 static int ql_mii_setup(struct ql3_adapter *qdev)
1745 {
1746         u32 reg;
1747         struct ql3xxx_port_registers __iomem *port_regs =
1748                         qdev->mem_map_registers;
1749
1750         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1751                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1752                          2) << 7))
1753                 return -1;
1754
1755         if (qdev->device_id == QL3032_DEVICE_ID)
1756                 ql_write_page0_reg(qdev, 
1757                         &port_regs->macMIIMgmtControlReg, 0x0f00000);
1758
1759         /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1760         reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1761
1762         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1763                            reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1764
1765         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1766         return 0;
1767 }
1768
1769 static u32 ql_supported_modes(struct ql3_adapter *qdev)
1770 {
1771         u32 supported;
1772
1773         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1774                 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
1775                     | SUPPORTED_Autoneg;
1776         } else {
1777                 supported = SUPPORTED_10baseT_Half
1778                     | SUPPORTED_10baseT_Full
1779                     | SUPPORTED_100baseT_Half
1780                     | SUPPORTED_100baseT_Full
1781                     | SUPPORTED_1000baseT_Half
1782                     | SUPPORTED_1000baseT_Full
1783                     | SUPPORTED_Autoneg | SUPPORTED_TP;
1784         }
1785
1786         return supported;
1787 }
1788
1789 static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1790 {
1791         int status;
1792         unsigned long hw_flags;
1793         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1794         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1795                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1796                          2) << 7)) {
1797                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1798                 return 0;
1799         }
1800         status = ql_is_auto_cfg(qdev);
1801         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1802         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1803         return status;
1804 }
1805
1806 static u32 ql_get_speed(struct ql3_adapter *qdev)
1807 {
1808         u32 status;
1809         unsigned long hw_flags;
1810         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1811         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1812                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1813                          2) << 7)) {
1814                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1815                 return 0;
1816         }
1817         status = ql_get_link_speed(qdev);
1818         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1819         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1820         return status;
1821 }
1822
1823 static int ql_get_full_dup(struct ql3_adapter *qdev)
1824 {
1825         int status;
1826         unsigned long hw_flags;
1827         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1828         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1829                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1830                          2) << 7)) {
1831                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1832                 return 0;
1833         }
1834         status = ql_is_link_full_dup(qdev);
1835         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1836         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1837         return status;
1838 }
1839
1840
1841 static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1842 {
1843         struct ql3_adapter *qdev = netdev_priv(ndev);
1844
1845         ecmd->transceiver = XCVR_INTERNAL;
1846         ecmd->supported = ql_supported_modes(qdev);
1847
1848         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1849                 ecmd->port = PORT_FIBRE;
1850         } else {
1851                 ecmd->port = PORT_TP;
1852                 ecmd->phy_address = qdev->PHYAddr;
1853         }
1854         ecmd->advertising = ql_supported_modes(qdev);
1855         ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1856         ecmd->speed = ql_get_speed(qdev);
1857         ecmd->duplex = ql_get_full_dup(qdev);
1858         return 0;
1859 }
1860
1861 static void ql_get_drvinfo(struct net_device *ndev,
1862                            struct ethtool_drvinfo *drvinfo)
1863 {
1864         struct ql3_adapter *qdev = netdev_priv(ndev);
1865         strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
1866         strncpy(drvinfo->version, ql3xxx_driver_version, 32);
1867         strncpy(drvinfo->fw_version, "N/A", 32);
1868         strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
1869         drvinfo->n_stats = 0;
1870         drvinfo->testinfo_len = 0;
1871         drvinfo->regdump_len = 0;
1872         drvinfo->eedump_len = 0;
1873 }
1874
1875 static u32 ql_get_msglevel(struct net_device *ndev)
1876 {
1877         struct ql3_adapter *qdev = netdev_priv(ndev);
1878         return qdev->msg_enable;
1879 }
1880
1881 static void ql_set_msglevel(struct net_device *ndev, u32 value)
1882 {
1883         struct ql3_adapter *qdev = netdev_priv(ndev);
1884         qdev->msg_enable = value;
1885 }
1886
1887 static void ql_get_pauseparam(struct net_device *ndev,
1888                               struct ethtool_pauseparam *pause)
1889 {
1890         struct ql3_adapter *qdev = netdev_priv(ndev);
1891         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1892
1893         u32 reg;
1894         if(qdev->mac_index == 0)
1895                 reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg);
1896         else
1897                 reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg);
1898
1899         pause->autoneg  = ql_get_auto_cfg_status(qdev);
1900         pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2;
1901         pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1;
1902 }
1903
1904 static const struct ethtool_ops ql3xxx_ethtool_ops = {
1905         .get_settings = ql_get_settings,
1906         .get_drvinfo = ql_get_drvinfo,
1907         .get_link = ethtool_op_get_link,
1908         .get_msglevel = ql_get_msglevel,
1909         .set_msglevel = ql_set_msglevel,
1910         .get_pauseparam = ql_get_pauseparam,
1911 };
1912
1913 static int ql_populate_free_queue(struct ql3_adapter *qdev)
1914 {
1915         struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1916         dma_addr_t map;
1917         int err;
1918
1919         while (lrg_buf_cb) {
1920                 if (!lrg_buf_cb->skb) {
1921                         lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
1922                                                            qdev->lrg_buffer_len);
1923                         if (unlikely(!lrg_buf_cb->skb)) {
1924                                 printk(KERN_DEBUG PFX
1925                                        "%s: Failed netdev_alloc_skb().\n",
1926                                        qdev->ndev->name);
1927                                 break;
1928                         } else {
1929                                 /*
1930                                  * We save some space to copy the ethhdr from
1931                                  * first buffer
1932                                  */
1933                                 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1934                                 map = pci_map_single(qdev->pdev,
1935                                                      lrg_buf_cb->skb->data,
1936                                                      qdev->lrg_buffer_len -
1937                                                      QL_HEADER_SPACE,
1938                                                      PCI_DMA_FROMDEVICE);
1939
1940                                 err = pci_dma_mapping_error(map);
1941                                 if(err) {
1942                                         printk(KERN_ERR "%s: PCI mapping failed with error: %d\n", 
1943                                                qdev->ndev->name, err);
1944                                         dev_kfree_skb(lrg_buf_cb->skb);
1945                                         lrg_buf_cb->skb = NULL;
1946                                         break;
1947                                 }
1948
1949
1950                                 lrg_buf_cb->buf_phy_addr_low =
1951                                     cpu_to_le32(LS_64BITS(map));
1952                                 lrg_buf_cb->buf_phy_addr_high =
1953                                     cpu_to_le32(MS_64BITS(map));
1954                                 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1955                                 pci_unmap_len_set(lrg_buf_cb, maplen,
1956                                                   qdev->lrg_buffer_len -
1957                                                   QL_HEADER_SPACE);
1958                                 --qdev->lrg_buf_skb_check;
1959                                 if (!qdev->lrg_buf_skb_check)
1960                                         return 1;
1961                         }
1962                 }
1963                 lrg_buf_cb = lrg_buf_cb->next;
1964         }
1965         return 0;
1966 }
1967
1968 /*
1969  * Caller holds hw_lock.
1970  */
1971 static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
1972 {
1973         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1974         if (qdev->small_buf_release_cnt >= 16) {
1975                 while (qdev->small_buf_release_cnt >= 16) {
1976                         qdev->small_buf_q_producer_index++;
1977
1978                         if (qdev->small_buf_q_producer_index ==
1979                             NUM_SBUFQ_ENTRIES)
1980                                 qdev->small_buf_q_producer_index = 0;
1981                         qdev->small_buf_release_cnt -= 8;
1982                 }
1983                 wmb();
1984                 writel(qdev->small_buf_q_producer_index,
1985                         &port_regs->CommonRegs.rxSmallQProducerIndex);
1986         }
1987 }
1988
1989 /*
1990  * Caller holds hw_lock.
1991  */
1992 static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1993 {
1994         struct bufq_addr_element *lrg_buf_q_ele;
1995         int i;
1996         struct ql_rcv_buf_cb *lrg_buf_cb;
1997         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1998
1999         if ((qdev->lrg_buf_free_count >= 8)
2000             && (qdev->lrg_buf_release_cnt >= 16)) {
2001
2002                 if (qdev->lrg_buf_skb_check)
2003                         if (!ql_populate_free_queue(qdev))
2004                                 return;
2005
2006                 lrg_buf_q_ele = qdev->lrg_buf_next_free;
2007
2008                 while ((qdev->lrg_buf_release_cnt >= 16)
2009                        && (qdev->lrg_buf_free_count >= 8)) {
2010
2011                         for (i = 0; i < 8; i++) {
2012                                 lrg_buf_cb =
2013                                     ql_get_from_lrg_buf_free_list(qdev);
2014                                 lrg_buf_q_ele->addr_high =
2015                                     lrg_buf_cb->buf_phy_addr_high;
2016                                 lrg_buf_q_ele->addr_low =
2017                                     lrg_buf_cb->buf_phy_addr_low;
2018                                 lrg_buf_q_ele++;
2019
2020                                 qdev->lrg_buf_release_cnt--;
2021                         }
2022
2023                         qdev->lrg_buf_q_producer_index++;
2024
2025                         if (qdev->lrg_buf_q_producer_index == qdev->num_lbufq_entries)
2026                                 qdev->lrg_buf_q_producer_index = 0;
2027
2028                         if (qdev->lrg_buf_q_producer_index ==
2029                             (qdev->num_lbufq_entries - 1)) {
2030                                 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
2031                         }
2032                 }
2033                 wmb();
2034                 qdev->lrg_buf_next_free = lrg_buf_q_ele;
2035                 writel(qdev->lrg_buf_q_producer_index,
2036                         &port_regs->CommonRegs.rxLargeQProducerIndex);
2037         }
2038 }
2039
2040 static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
2041                                    struct ob_mac_iocb_rsp *mac_rsp)
2042 {
2043         struct ql_tx_buf_cb *tx_cb;
2044         int i;
2045         int retval = 0;
2046
2047         if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
2048                 printk(KERN_WARNING "Frame short but, frame was padded and sent.\n");
2049         }
2050         
2051         tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
2052
2053         /*  Check the transmit response flags for any errors */
2054         if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
2055                 printk(KERN_ERR "Frame too short to be legal, frame not sent.\n");
2056
2057                 qdev->stats.tx_errors++;
2058                 retval = -EIO;
2059                 goto frame_not_sent;
2060         }
2061
2062         if(tx_cb->seg_count == 0) {
2063                 printk(KERN_ERR "tx_cb->seg_count == 0: %d\n", mac_rsp->transaction_id);
2064
2065                 qdev->stats.tx_errors++;
2066                 retval = -EIO;
2067                 goto invalid_seg_count;
2068         }
2069
2070         pci_unmap_single(qdev->pdev,
2071                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
2072                          pci_unmap_len(&tx_cb->map[0], maplen),
2073                          PCI_DMA_TODEVICE);
2074         tx_cb->seg_count--;
2075         if (tx_cb->seg_count) {
2076                 for (i = 1; i < tx_cb->seg_count; i++) {
2077                         pci_unmap_page(qdev->pdev,
2078                                        pci_unmap_addr(&tx_cb->map[i],
2079                                                       mapaddr),
2080                                        pci_unmap_len(&tx_cb->map[i], maplen),
2081                                        PCI_DMA_TODEVICE);
2082                 }
2083         }
2084         qdev->stats.tx_packets++;
2085         qdev->stats.tx_bytes += tx_cb->skb->len;
2086
2087 frame_not_sent:
2088         dev_kfree_skb_irq(tx_cb->skb);
2089         tx_cb->skb = NULL;
2090
2091 invalid_seg_count:
2092         atomic_inc(&qdev->tx_count);
2093 }
2094
2095 static void ql_get_sbuf(struct ql3_adapter *qdev)
2096 {
2097         if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
2098                 qdev->small_buf_index = 0;
2099         qdev->small_buf_release_cnt++;
2100 }
2101
2102 static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
2103 {
2104         struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
2105         lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
2106         qdev->lrg_buf_release_cnt++;
2107         if (++qdev->lrg_buf_index == qdev->num_large_buffers)
2108                 qdev->lrg_buf_index = 0;
2109         return(lrg_buf_cb);
2110 }
2111
2112 /*
2113  * The difference between 3022 and 3032 for inbound completions:
2114  * 3022 uses two buffers per completion.  The first buffer contains 
2115  * (some) header info, the second the remainder of the headers plus 
2116  * the data.  For this chip we reserve some space at the top of the 
2117  * receive buffer so that the header info in buffer one can be 
2118  * prepended to the buffer two.  Buffer two is the sent up while 
2119  * buffer one is returned to the hardware to be reused.
2120  * 3032 receives all of it's data and headers in one buffer for a 
2121  * simpler process.  3032 also supports checksum verification as
2122  * can be seen in ql_process_macip_rx_intr().
2123  */
2124 static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
2125                                    struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
2126 {
2127         struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2128         struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2129         struct sk_buff *skb;
2130         u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
2131
2132         /*
2133          * Get the inbound address list (small buffer).
2134          */
2135         ql_get_sbuf(qdev);
2136
2137         if (qdev->device_id == QL3022_DEVICE_ID)
2138                 lrg_buf_cb1 = ql_get_lbuf(qdev);
2139
2140         /* start of second buffer */
2141         lrg_buf_cb2 = ql_get_lbuf(qdev);
2142         skb = lrg_buf_cb2->skb;
2143
2144         qdev->stats.rx_packets++;
2145         qdev->stats.rx_bytes += length;
2146
2147         skb_put(skb, length);
2148         pci_unmap_single(qdev->pdev,
2149                          pci_unmap_addr(lrg_buf_cb2, mapaddr),
2150                          pci_unmap_len(lrg_buf_cb2, maplen),
2151                          PCI_DMA_FROMDEVICE);
2152         prefetch(skb->data);
2153         skb->ip_summed = CHECKSUM_NONE;
2154         skb->protocol = eth_type_trans(skb, qdev->ndev);
2155
2156         netif_receive_skb(skb);
2157         qdev->ndev->last_rx = jiffies;
2158         lrg_buf_cb2->skb = NULL;
2159
2160         if (qdev->device_id == QL3022_DEVICE_ID)
2161                 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2162         ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2163 }
2164
2165 static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
2166                                      struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
2167 {
2168         struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2169         struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2170         struct sk_buff *skb1 = NULL, *skb2;
2171         struct net_device *ndev = qdev->ndev;
2172         u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
2173         u16 size = 0;
2174
2175         /*
2176          * Get the inbound address list (small buffer).
2177          */
2178
2179         ql_get_sbuf(qdev);
2180
2181         if (qdev->device_id == QL3022_DEVICE_ID) {
2182                 /* start of first buffer on 3022 */
2183                 lrg_buf_cb1 = ql_get_lbuf(qdev);
2184                 skb1 = lrg_buf_cb1->skb;
2185                 size = ETH_HLEN;
2186                 if (*((u16 *) skb1->data) != 0xFFFF)
2187                         size += VLAN_ETH_HLEN - ETH_HLEN;
2188         }
2189
2190         /* start of second buffer */
2191         lrg_buf_cb2 = ql_get_lbuf(qdev);
2192         skb2 = lrg_buf_cb2->skb;
2193
2194         skb_put(skb2, length);  /* Just the second buffer length here. */
2195         pci_unmap_single(qdev->pdev,
2196                          pci_unmap_addr(lrg_buf_cb2, mapaddr),
2197                          pci_unmap_len(lrg_buf_cb2, maplen),
2198                          PCI_DMA_FROMDEVICE);
2199         prefetch(skb2->data);
2200
2201         skb2->ip_summed = CHECKSUM_NONE;
2202         if (qdev->device_id == QL3022_DEVICE_ID) {
2203                 /*
2204                  * Copy the ethhdr from first buffer to second. This
2205                  * is necessary for 3022 IP completions.
2206                  */
2207                 skb_copy_from_linear_data_offset(skb1, VLAN_ID_LEN,
2208                                                  skb_push(skb2, size), size);
2209         } else {
2210                 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
2211                 if (checksum & 
2212                         (IB_IP_IOCB_RSP_3032_ICE | 
2213                          IB_IP_IOCB_RSP_3032_CE)) { 
2214                         printk(KERN_ERR
2215                                "%s: Bad checksum for this %s packet, checksum = %x.\n",
2216                                __func__,
2217                                ((checksum & 
2218                                 IB_IP_IOCB_RSP_3032_TCP) ? "TCP" :
2219                                 "UDP"),checksum);
2220                 } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
2221                                 (checksum & IB_IP_IOCB_RSP_3032_UDP &&
2222                                 !(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
2223                         skb2->ip_summed = CHECKSUM_UNNECESSARY;
2224                 }
2225         }
2226         skb2->protocol = eth_type_trans(skb2, qdev->ndev);
2227
2228         netif_receive_skb(skb2);
2229         qdev->stats.rx_packets++;
2230         qdev->stats.rx_bytes += length;
2231         ndev->last_rx = jiffies;
2232         lrg_buf_cb2->skb = NULL;
2233
2234         if (qdev->device_id == QL3022_DEVICE_ID)
2235                 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2236         ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2237 }
2238
2239 static int ql_tx_rx_clean(struct ql3_adapter *qdev,
2240                           int *tx_cleaned, int *rx_cleaned, int work_to_do)
2241 {
2242         struct net_rsp_iocb *net_rsp;
2243         struct net_device *ndev = qdev->ndev;
2244         int work_done = 0;
2245
2246         /* While there are entries in the completion queue. */
2247         while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
2248                 qdev->rsp_consumer_index) && (work_done < work_to_do)) {
2249
2250                 net_rsp = qdev->rsp_current;
2251                 rmb();
2252                 /*
2253                  * Fix 4032 chipe undocumented "feature" where bit-8 is set if the
2254                  * inbound completion is for a VLAN.
2255                  */
2256                 if (qdev->device_id == QL3032_DEVICE_ID)
2257                         net_rsp->opcode &= 0x7f;
2258                 switch (net_rsp->opcode) {
2259
2260                 case OPCODE_OB_MAC_IOCB_FN0:
2261                 case OPCODE_OB_MAC_IOCB_FN2:
2262                         ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
2263                                                net_rsp);
2264                         (*tx_cleaned)++;
2265                         break;
2266
2267                 case OPCODE_IB_MAC_IOCB:
2268                 case OPCODE_IB_3032_MAC_IOCB:
2269                         ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
2270                                                net_rsp);
2271                         (*rx_cleaned)++;
2272                         break;
2273
2274                 case OPCODE_IB_IP_IOCB:
2275                 case OPCODE_IB_3032_IP_IOCB:
2276                         ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
2277                                                  net_rsp);
2278                         (*rx_cleaned)++;
2279                         break;
2280                 default:
2281                         {
2282                                 u32 *tmp = (u32 *) net_rsp;
2283                                 printk(KERN_ERR PFX
2284                                        "%s: Hit default case, not "
2285                                        "handled!\n"
2286                                        "        dropping the packet, opcode = "
2287                                        "%x.\n",
2288                                        ndev->name, net_rsp->opcode);
2289                                 printk(KERN_ERR PFX
2290                                        "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
2291                                        (unsigned long int)tmp[0],
2292                                        (unsigned long int)tmp[1],
2293                                        (unsigned long int)tmp[2],
2294                                        (unsigned long int)tmp[3]);
2295                         }
2296                 }
2297
2298                 qdev->rsp_consumer_index++;
2299
2300                 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2301                         qdev->rsp_consumer_index = 0;
2302                         qdev->rsp_current = qdev->rsp_q_virt_addr;
2303                 } else {
2304                         qdev->rsp_current++;
2305                 }
2306
2307                 work_done = *tx_cleaned + *rx_cleaned;
2308         }
2309
2310         return work_done;
2311 }
2312
2313 static int ql_poll(struct napi_struct *napi, int budget)
2314 {
2315         struct ql3_adapter *qdev = container_of(napi, struct ql3_adapter, napi);
2316         struct net_device *ndev = qdev->ndev;
2317         int rx_cleaned = 0, tx_cleaned = 0;
2318         unsigned long hw_flags;
2319         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2320
2321         if (!netif_carrier_ok(ndev))
2322                 goto quit_polling;
2323
2324         ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, budget);
2325
2326         if (tx_cleaned + rx_cleaned != budget ||
2327             !netif_running(ndev)) {
2328 quit_polling:
2329                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
2330                 __netif_rx_complete(ndev, napi);
2331                 ql_update_small_bufq_prod_index(qdev);
2332                 ql_update_lrg_bufq_prod_index(qdev);
2333                 writel(qdev->rsp_consumer_index,
2334                             &port_regs->CommonRegs.rspQConsumerIndex);
2335                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2336
2337                 ql_enable_interrupts(qdev);
2338         }
2339         return tx_cleaned + rx_cleaned;
2340 }
2341
2342 static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2343 {
2344
2345         struct net_device *ndev = dev_id;
2346         struct ql3_adapter *qdev = netdev_priv(ndev);
2347         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2348         u32 value;
2349         int handled = 1;
2350         u32 var;
2351
2352         port_regs = qdev->mem_map_registers;
2353
2354         value =
2355             ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
2356
2357         if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2358                 spin_lock(&qdev->adapter_lock);
2359                 netif_stop_queue(qdev->ndev);
2360                 netif_carrier_off(qdev->ndev);
2361                 ql_disable_interrupts(qdev);
2362                 qdev->port_link_state = LS_DOWN;
2363                 set_bit(QL_RESET_ACTIVE,&qdev->flags) ;
2364
2365                 if (value & ISP_CONTROL_FE) {
2366                         /*
2367                          * Chip Fatal Error.
2368                          */
2369                         var =
2370                             ql_read_page0_reg_l(qdev,
2371                                               &port_regs->PortFatalErrStatus);
2372                         printk(KERN_WARNING PFX
2373                                "%s: Resetting chip. PortFatalErrStatus "
2374                                "register = 0x%x\n", ndev->name, var);
2375                         set_bit(QL_RESET_START,&qdev->flags) ;
2376                 } else {
2377                         /*
2378                          * Soft Reset Requested.
2379                          */
2380                         set_bit(QL_RESET_PER_SCSI,&qdev->flags) ;
2381                         printk(KERN_ERR PFX
2382                                "%s: Another function issued a reset to the "
2383                                "chip. ISR value = %x.\n", ndev->name, value);
2384                 }
2385                 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2386                 spin_unlock(&qdev->adapter_lock);
2387         } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2388                 ql_disable_interrupts(qdev);
2389                 if (likely(netif_rx_schedule_prep(ndev, &qdev->napi))) {
2390                         __netif_rx_schedule(ndev, &qdev->napi);
2391                 }
2392         } else {
2393                 return IRQ_NONE;
2394         }
2395
2396         return IRQ_RETVAL(handled);
2397 }
2398
2399 /*
2400  * Get the total number of segments needed for the 
2401  * given number of fragments.  This is necessary because
2402  * outbound address lists (OAL) will be used when more than
2403  * two frags are given.  Each address list has 5 addr/len 
2404  * pairs.  The 5th pair in each AOL is used to  point to
2405  * the next AOL if more frags are coming.  
2406  * That is why the frags:segment count  ratio is not linear.
2407  */
2408 static int ql_get_seg_count(struct ql3_adapter *qdev,
2409                             unsigned short frags)
2410 {
2411         if (qdev->device_id == QL3022_DEVICE_ID)
2412                 return 1;
2413
2414         switch(frags) {
2415         case 0: return 1;       /* just the skb->data seg */
2416         case 1: return 2;       /* skb->data + 1 frag */
2417         case 2: return 3;       /* skb->data + 2 frags */
2418         case 3: return 5;       /* skb->data + 1 frag + 1 AOL containting 2 frags */
2419         case 4: return 6;
2420         case 5: return 7;
2421         case 6: return 8;
2422         case 7: return 10;
2423         case 8: return 11;
2424         case 9: return 12;
2425         case 10: return 13;
2426         case 11: return 15;
2427         case 12: return 16;
2428         case 13: return 17;
2429         case 14: return 18;
2430         case 15: return 20;
2431         case 16: return 21;
2432         case 17: return 22;
2433         case 18: return 23;
2434         }
2435         return -1;
2436 }
2437
2438 static void ql_hw_csum_setup(const struct sk_buff *skb,
2439                              struct ob_mac_iocb_req *mac_iocb_ptr)
2440 {
2441         const struct iphdr *ip = ip_hdr(skb);
2442
2443         mac_iocb_ptr->ip_hdr_off = skb_network_offset(skb);
2444         mac_iocb_ptr->ip_hdr_len = ip->ihl;
2445
2446         if (ip->protocol == IPPROTO_TCP) {
2447                 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
2448                         OB_3032MAC_IOCB_REQ_IC;
2449         } else {
2450                 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
2451                         OB_3032MAC_IOCB_REQ_IC;
2452         }
2453
2454 }
2455
2456 /*
2457  * Map the buffers for this transmit.  This will return
2458  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
2459  */
2460 static int ql_send_map(struct ql3_adapter *qdev,
2461                                 struct ob_mac_iocb_req *mac_iocb_ptr,
2462                                 struct ql_tx_buf_cb *tx_cb,
2463                                 struct sk_buff *skb)
2464 {
2465         struct oal *oal;
2466         struct oal_entry *oal_entry;
2467         int len = skb_headlen(skb);
2468         dma_addr_t map;
2469         int err;
2470         int completed_segs, i;
2471         int seg_cnt, seg = 0;
2472         int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2473
2474         seg_cnt = tx_cb->seg_count;
2475         /*
2476          * Map the skb buffer first.
2477          */
2478         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
2479
2480         err = pci_dma_mapping_error(map);
2481         if(err) {
2482                 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n", 
2483                        qdev->ndev->name, err);
2484
2485                 return NETDEV_TX_BUSY;
2486         }
2487         
2488         oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2489         oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2490         oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2491         oal_entry->len = cpu_to_le32(len);
2492         pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2493         pci_unmap_len_set(&tx_cb->map[seg], maplen, len);
2494         seg++;
2495
2496         if (seg_cnt == 1) {
2497                 /* Terminate the last segment. */
2498                 oal_entry->len =
2499                     cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2500         } else {
2501                 oal = tx_cb->oal;
2502                 for (completed_segs=0; completed_segs<frag_cnt; completed_segs++,seg++) {
2503                         skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
2504                         oal_entry++;
2505                         if ((seg == 2 && seg_cnt > 3) ||        /* Check for continuation */
2506                             (seg == 7 && seg_cnt > 8) ||        /* requirements. It's strange */
2507                             (seg == 12 && seg_cnt > 13) ||      /* but necessary. */
2508                             (seg == 17 && seg_cnt > 18)) {
2509                                 /* Continuation entry points to outbound address list. */
2510                                 map = pci_map_single(qdev->pdev, oal,
2511                                                      sizeof(struct oal),
2512                                                      PCI_DMA_TODEVICE);
2513
2514                                 err = pci_dma_mapping_error(map);
2515                                 if(err) {
2516
2517                                         printk(KERN_ERR "%s: PCI mapping outbound address list with error: %d\n", 
2518                                                qdev->ndev->name, err);
2519                                         goto map_error;
2520                                 }
2521
2522                                 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2523                                 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2524                                 oal_entry->len =
2525                                     cpu_to_le32(sizeof(struct oal) |
2526                                                 OAL_CONT_ENTRY);
2527                                 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr,
2528                                                    map);
2529                                 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2530                                                   sizeof(struct oal));
2531                                 oal_entry = (struct oal_entry *)oal;
2532                                 oal++;
2533                                 seg++;
2534                         }
2535
2536                         map =
2537                             pci_map_page(qdev->pdev, frag->page,
2538                                          frag->page_offset, frag->size,
2539                                          PCI_DMA_TODEVICE);
2540
2541                         err = pci_dma_mapping_error(map);
2542                         if(err) {
2543                                 printk(KERN_ERR "%s: PCI mapping frags failed with error: %d\n", 
2544                                        qdev->ndev->name, err);
2545                                 goto map_error;
2546                         }
2547
2548                         oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2549                         oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2550                         oal_entry->len = cpu_to_le32(frag->size);
2551                         pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2552                         pci_unmap_len_set(&tx_cb->map[seg], maplen,
2553                                           frag->size);
2554                 }
2555                 /* Terminate the last segment. */
2556                 oal_entry->len =
2557                     cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2558         }
2559
2560         return NETDEV_TX_OK;
2561
2562 map_error:
2563         /* A PCI mapping failed and now we will need to back out
2564          * We need to traverse through the oal's and associated pages which 
2565          * have been mapped and now we must unmap them to clean up properly
2566          */
2567         
2568         seg = 1;
2569         oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2570         oal = tx_cb->oal;
2571         for (i=0; i<completed_segs; i++,seg++) {
2572                 oal_entry++;
2573
2574                 if((seg == 2 && seg_cnt > 3) ||        /* Check for continuation */
2575                    (seg == 7 && seg_cnt > 8) ||        /* requirements. It's strange */
2576                    (seg == 12 && seg_cnt > 13) ||      /* but necessary. */
2577                    (seg == 17 && seg_cnt > 18)) {
2578                         pci_unmap_single(qdev->pdev,
2579                                 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2580                                 pci_unmap_len(&tx_cb->map[seg], maplen),
2581                                  PCI_DMA_TODEVICE);
2582                         oal++;
2583                         seg++;
2584                 }
2585
2586                 pci_unmap_page(qdev->pdev,
2587                                pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2588                                pci_unmap_len(&tx_cb->map[seg], maplen),
2589                                PCI_DMA_TODEVICE);
2590         }
2591
2592         pci_unmap_single(qdev->pdev,
2593                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
2594                          pci_unmap_addr(&tx_cb->map[0], maplen),
2595                          PCI_DMA_TODEVICE);
2596
2597         return NETDEV_TX_BUSY;
2598
2599 }
2600
2601 /*
2602  * The difference between 3022 and 3032 sends:
2603  * 3022 only supports a simple single segment transmission.
2604  * 3032 supports checksumming and scatter/gather lists (fragments).
2605  * The 3032 supports sglists by using the 3 addr/len pairs (ALP) 
2606  * in the IOCB plus a chain of outbound address lists (OAL) that 
2607  * each contain 5 ALPs.  The last ALP of the IOCB (3rd) or OAL (5th) 
2608  * will used to point to an OAL when more ALP entries are required.  
2609  * The IOCB is always the top of the chain followed by one or more 
2610  * OALs (when necessary).
2611  */
2612 static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev)
2613 {
2614         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
2615         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2616         struct ql_tx_buf_cb *tx_cb;
2617         u32 tot_len = skb->len;
2618         struct ob_mac_iocb_req *mac_iocb_ptr;
2619
2620         if (unlikely(atomic_read(&qdev->tx_count) < 2)) {
2621                 return NETDEV_TX_BUSY;
2622         }
2623         
2624         tx_cb = &qdev->tx_buf[qdev->req_producer_index] ;
2625         if((tx_cb->seg_count = ql_get_seg_count(qdev,
2626                                                 (skb_shinfo(skb)->nr_frags))) == -1) {
2627                 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2628                 return NETDEV_TX_OK;
2629         }
2630         
2631         mac_iocb_ptr = tx_cb->queue_entry;
2632         memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
2633         mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2634         mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2635         mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2636         mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2637         mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2638         tx_cb->skb = skb;
2639         if (qdev->device_id == QL3032_DEVICE_ID &&
2640             skb->ip_summed == CHECKSUM_PARTIAL)
2641                 ql_hw_csum_setup(skb, mac_iocb_ptr);
2642         
2643         if(ql_send_map(qdev,mac_iocb_ptr,tx_cb,skb) != NETDEV_TX_OK) {
2644                 printk(KERN_ERR PFX"%s: Could not map the segments!\n",__func__);
2645                 return NETDEV_TX_BUSY;
2646         }
2647         
2648         wmb();
2649         qdev->req_producer_index++;
2650         if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2651                 qdev->req_producer_index = 0;
2652         wmb();
2653         ql_write_common_reg_l(qdev,
2654                             &port_regs->CommonRegs.reqQProducerIndex,
2655                             qdev->req_producer_index);
2656
2657         ndev->trans_start = jiffies;
2658         if (netif_msg_tx_queued(qdev))
2659                 printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n",
2660                        ndev->name, qdev->req_producer_index, skb->len);
2661
2662         atomic_dec(&qdev->tx_count);
2663         return NETDEV_TX_OK;
2664 }
2665
2666 static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2667 {
2668         qdev->req_q_size =
2669             (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2670
2671         qdev->req_q_virt_addr =
2672             pci_alloc_consistent(qdev->pdev,
2673                                  (size_t) qdev->req_q_size,
2674                                  &qdev->req_q_phy_addr);
2675
2676         if ((qdev->req_q_virt_addr == NULL) ||
2677             LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2678                 printk(KERN_ERR PFX "%s: reqQ failed.\n",
2679                        qdev->ndev->name);
2680                 return -ENOMEM;
2681         }
2682
2683         qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2684
2685         qdev->rsp_q_virt_addr =
2686             pci_alloc_consistent(qdev->pdev,
2687                                  (size_t) qdev->rsp_q_size,
2688                                  &qdev->rsp_q_phy_addr);
2689
2690         if ((qdev->rsp_q_virt_addr == NULL) ||
2691             LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2692                 printk(KERN_ERR PFX
2693                        "%s: rspQ allocation failed\n",
2694                        qdev->ndev->name);
2695                 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2696                                     qdev->req_q_virt_addr,
2697                                     qdev->req_q_phy_addr);
2698                 return -ENOMEM;
2699         }
2700
2701         set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2702
2703         return 0;
2704 }
2705
2706 static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2707 {
2708         if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) {
2709                 printk(KERN_INFO PFX
2710                        "%s: Already done.\n", qdev->ndev->name);
2711                 return;
2712         }
2713
2714         pci_free_consistent(qdev->pdev,
2715                             qdev->req_q_size,
2716                             qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2717
2718         qdev->req_q_virt_addr = NULL;
2719
2720         pci_free_consistent(qdev->pdev,
2721                             qdev->rsp_q_size,
2722                             qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2723
2724         qdev->rsp_q_virt_addr = NULL;
2725
2726         clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2727 }
2728
2729 static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2730 {
2731         /* Create Large Buffer Queue */
2732         qdev->lrg_buf_q_size =
2733             qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2734         if (qdev->lrg_buf_q_size < PAGE_SIZE)
2735                 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2736         else
2737                 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2738
2739         qdev->lrg_buf = kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),GFP_KERNEL);
2740         if (qdev->lrg_buf == NULL) {
2741                 printk(KERN_ERR PFX
2742                        "%s: qdev->lrg_buf alloc failed.\n", qdev->ndev->name);
2743                 return -ENOMEM;
2744         }
2745         
2746         qdev->lrg_buf_q_alloc_virt_addr =
2747             pci_alloc_consistent(qdev->pdev,
2748                                  qdev->lrg_buf_q_alloc_size,
2749                                  &qdev->lrg_buf_q_alloc_phy_addr);
2750
2751         if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2752                 printk(KERN_ERR PFX
2753                        "%s: lBufQ failed\n", qdev->ndev->name);
2754                 return -ENOMEM;
2755         }
2756         qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2757         qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2758
2759         /* Create Small Buffer Queue */
2760         qdev->small_buf_q_size =
2761             NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2762         if (qdev->small_buf_q_size < PAGE_SIZE)
2763                 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2764         else
2765                 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2766
2767         qdev->small_buf_q_alloc_virt_addr =
2768             pci_alloc_consistent(qdev->pdev,
2769                                  qdev->small_buf_q_alloc_size,
2770                                  &qdev->small_buf_q_alloc_phy_addr);
2771
2772         if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2773                 printk(KERN_ERR PFX
2774                        "%s: Small Buffer Queue allocation failed.\n",
2775                        qdev->ndev->name);
2776                 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2777                                     qdev->lrg_buf_q_alloc_virt_addr,
2778                                     qdev->lrg_buf_q_alloc_phy_addr);
2779                 return -ENOMEM;
2780         }
2781
2782         qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2783         qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2784         set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2785         return 0;
2786 }
2787
2788 static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2789 {
2790         if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) {
2791                 printk(KERN_INFO PFX
2792                        "%s: Already done.\n", qdev->ndev->name);
2793                 return;
2794         }
2795         if(qdev->lrg_buf) kfree(qdev->lrg_buf);
2796         pci_free_consistent(qdev->pdev,
2797                             qdev->lrg_buf_q_alloc_size,
2798                             qdev->lrg_buf_q_alloc_virt_addr,
2799                             qdev->lrg_buf_q_alloc_phy_addr);
2800
2801         qdev->lrg_buf_q_virt_addr = NULL;
2802
2803         pci_free_consistent(qdev->pdev,
2804                             qdev->small_buf_q_alloc_size,
2805                             qdev->small_buf_q_alloc_virt_addr,
2806                             qdev->small_buf_q_alloc_phy_addr);
2807
2808         qdev->small_buf_q_virt_addr = NULL;
2809
2810         clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2811 }
2812
2813 static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2814 {
2815         int i;
2816         struct bufq_addr_element *small_buf_q_entry;
2817
2818         /* Currently we allocate on one of memory and use it for smallbuffers */
2819         qdev->small_buf_total_size =
2820             (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2821              QL_SMALL_BUFFER_SIZE);
2822
2823         qdev->small_buf_virt_addr =
2824             pci_alloc_consistent(qdev->pdev,
2825                                  qdev->small_buf_total_size,
2826                                  &qdev->small_buf_phy_addr);
2827
2828         if (qdev->small_buf_virt_addr == NULL) {
2829                 printk(KERN_ERR PFX
2830                        "%s: Failed to get small buffer memory.\n",
2831                        qdev->ndev->name);
2832                 return -ENOMEM;
2833         }
2834
2835         qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2836         qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2837
2838         small_buf_q_entry = qdev->small_buf_q_virt_addr;
2839
2840         /* Initialize the small buffer queue. */
2841         for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2842                 small_buf_q_entry->addr_high =
2843                     cpu_to_le32(qdev->small_buf_phy_addr_high);
2844                 small_buf_q_entry->addr_low =
2845                     cpu_to_le32(qdev->small_buf_phy_addr_low +
2846                                 (i * QL_SMALL_BUFFER_SIZE));
2847                 small_buf_q_entry++;
2848         }
2849         qdev->small_buf_index = 0;
2850         set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags);
2851         return 0;
2852 }
2853
2854 static void ql_free_small_buffers(struct ql3_adapter *qdev)
2855 {
2856         if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) {
2857                 printk(KERN_INFO PFX
2858                        "%s: Already done.\n", qdev->ndev->name);
2859                 return;
2860         }
2861         if (qdev->small_buf_virt_addr != NULL) {
2862                 pci_free_consistent(qdev->pdev,
2863                                     qdev->small_buf_total_size,
2864                                     qdev->small_buf_virt_addr,
2865                                     qdev->small_buf_phy_addr);
2866
2867                 qdev->small_buf_virt_addr = NULL;
2868         }
2869 }
2870
2871 static void ql_free_large_buffers(struct ql3_adapter *qdev)
2872 {
2873         int i = 0;
2874         struct ql_rcv_buf_cb *lrg_buf_cb;
2875
2876         for (i = 0; i < qdev->num_large_buffers; i++) {
2877                 lrg_buf_cb = &qdev->lrg_buf[i];
2878                 if (lrg_buf_cb->skb) {
2879                         dev_kfree_skb(lrg_buf_cb->skb);
2880                         pci_unmap_single(qdev->pdev,
2881                                          pci_unmap_addr(lrg_buf_cb, mapaddr),
2882                                          pci_unmap_len(lrg_buf_cb, maplen),
2883                                          PCI_DMA_FROMDEVICE);
2884                         memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2885                 } else {
2886                         break;
2887                 }
2888         }
2889 }
2890
2891 static void ql_init_large_buffers(struct ql3_adapter *qdev)
2892 {
2893         int i;
2894         struct ql_rcv_buf_cb *lrg_buf_cb;
2895         struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2896
2897         for (i = 0; i < qdev->num_large_buffers; i++) {
2898                 lrg_buf_cb = &qdev->lrg_buf[i];
2899                 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2900                 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2901                 buf_addr_ele++;
2902         }
2903         qdev->lrg_buf_index = 0;
2904         qdev->lrg_buf_skb_check = 0;
2905 }
2906
2907 static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2908 {
2909         int i;
2910         struct ql_rcv_buf_cb *lrg_buf_cb;
2911         struct sk_buff *skb;
2912         dma_addr_t map;
2913         int err;
2914
2915         for (i = 0; i < qdev->num_large_buffers; i++) {
2916                 skb = netdev_alloc_skb(qdev->ndev,
2917                                        qdev->lrg_buffer_len);
2918                 if (unlikely(!skb)) {
2919                         /* Better luck next round */
2920                         printk(KERN_ERR PFX
2921                                "%s: large buff alloc failed, "
2922                                "for %d bytes at index %d.\n",
2923                                qdev->ndev->name,
2924                                qdev->lrg_buffer_len * 2, i);
2925                         ql_free_large_buffers(qdev);
2926                         return -ENOMEM;
2927                 } else {
2928
2929                         lrg_buf_cb = &qdev->lrg_buf[i];
2930                         memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2931                         lrg_buf_cb->index = i;
2932                         lrg_buf_cb->skb = skb;
2933                         /*
2934                          * We save some space to copy the ethhdr from first
2935                          * buffer
2936                          */
2937                         skb_reserve(skb, QL_HEADER_SPACE);
2938                         map = pci_map_single(qdev->pdev,
2939                                              skb->data,
2940                                              qdev->lrg_buffer_len -
2941                                              QL_HEADER_SPACE,
2942                                              PCI_DMA_FROMDEVICE);
2943
2944                         err = pci_dma_mapping_error(map);
2945                         if(err) {
2946                                 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2947                                        qdev->ndev->name, err);
2948                                 ql_free_large_buffers(qdev);
2949                                 return -ENOMEM;
2950                         }
2951
2952                         pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2953                         pci_unmap_len_set(lrg_buf_cb, maplen,
2954                                           qdev->lrg_buffer_len -
2955                                           QL_HEADER_SPACE);
2956                         lrg_buf_cb->buf_phy_addr_low =
2957                             cpu_to_le32(LS_64BITS(map));
2958                         lrg_buf_cb->buf_phy_addr_high =
2959                             cpu_to_le32(MS_64BITS(map));
2960                 }
2961         }
2962         return 0;
2963 }
2964
2965 static void ql_free_send_free_list(struct ql3_adapter *qdev)
2966 {
2967         struct ql_tx_buf_cb *tx_cb;
2968         int i;
2969
2970         tx_cb = &qdev->tx_buf[0];
2971         for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2972                 if (tx_cb->oal) {
2973                         kfree(tx_cb->oal);
2974                         tx_cb->oal = NULL;
2975                 }
2976                 tx_cb++;
2977         }
2978 }
2979
2980 static int ql_create_send_free_list(struct ql3_adapter *qdev)
2981 {
2982         struct ql_tx_buf_cb *tx_cb;
2983         int i;
2984         struct ob_mac_iocb_req *req_q_curr =
2985                                         qdev->req_q_virt_addr;
2986
2987         /* Create free list of transmit buffers */
2988         for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2989
2990                 tx_cb = &qdev->tx_buf[i];
2991                 tx_cb->skb = NULL;
2992                 tx_cb->queue_entry = req_q_curr;
2993                 req_q_curr++;
2994                 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2995                 if (tx_cb->oal == NULL)
2996                         return -1;
2997         }
2998         return 0;
2999 }
3000
3001 static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
3002 {
3003         if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
3004                 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
3005                 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
3006         }
3007         else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
3008                 /*
3009                  * Bigger buffers, so less of them.
3010                  */
3011                 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
3012                 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
3013         } else {
3014                 printk(KERN_ERR PFX
3015                        "%s: Invalid mtu size.  Only 1500 and 9000 are accepted.\n",
3016                        qdev->ndev->name);
3017                 return -ENOMEM;
3018         }
3019         qdev->num_large_buffers = qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
3020         qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
3021         qdev->max_frame_size =
3022             (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
3023
3024         /*
3025          * First allocate a page of shared memory and use it for shadow
3026          * locations of Network Request Queue Consumer Address Register and
3027          * Network Completion Queue Producer Index Register
3028          */
3029         qdev->shadow_reg_virt_addr =
3030             pci_alloc_consistent(qdev->pdev,
3031                                  PAGE_SIZE, &qdev->shadow_reg_phy_addr);
3032
3033         if (qdev->shadow_reg_virt_addr != NULL) {
3034                 qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
3035                 qdev->req_consumer_index_phy_addr_high =
3036                     MS_64BITS(qdev->shadow_reg_phy_addr);
3037                 qdev->req_consumer_index_phy_addr_low =
3038                     LS_64BITS(qdev->shadow_reg_phy_addr);
3039
3040                 qdev->prsp_producer_index =
3041                     (u32 *) (((u8 *) qdev->preq_consumer_index) + 8);
3042                 qdev->rsp_producer_index_phy_addr_high =
3043                     qdev->req_consumer_index_phy_addr_high;
3044                 qdev->rsp_producer_index_phy_addr_low =
3045                     qdev->req_consumer_index_phy_addr_low + 8;
3046         } else {
3047                 printk(KERN_ERR PFX
3048                        "%s: shadowReg Alloc failed.\n", qdev->ndev->name);
3049                 return -ENOMEM;
3050         }
3051
3052         if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
3053                 printk(KERN_ERR PFX
3054                        "%s: ql_alloc_net_req_rsp_queues failed.\n",
3055                        qdev->ndev->name);
3056                 goto err_req_rsp;
3057         }
3058
3059         if (ql_alloc_buffer_queues(qdev) != 0) {
3060                 printk(KERN_ERR PFX
3061                        "%s: ql_alloc_buffer_queues failed.\n",
3062                        qdev->ndev->name);
3063                 goto err_buffer_queues;
3064         }
3065
3066         if (ql_alloc_small_buffers(qdev) != 0) {
3067                 printk(KERN_ERR PFX
3068                        "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name);
3069                 goto err_small_buffers;
3070         }
3071
3072         if (ql_alloc_large_buffers(qdev) != 0) {
3073                 printk(KERN_ERR PFX
3074                        "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name);
3075                 goto err_small_buffers;
3076         }
3077
3078         /* Initialize the large buffer queue. */
3079         ql_init_large_buffers(qdev);
3080         if (ql_create_send_free_list(qdev))
3081                 goto err_free_list;
3082
3083         qdev->rsp_current = qdev->rsp_q_virt_addr;
3084
3085         return 0;
3086 err_free_list:
3087         ql_free_send_free_list(qdev);
3088 err_small_buffers:
3089         ql_free_buffer_queues(qdev);
3090 err_buffer_queues:
3091         ql_free_net_req_rsp_queues(qdev);
3092 err_req_rsp:
3093         pci_free_consistent(qdev->pdev,
3094                             PAGE_SIZE,
3095                             qdev->shadow_reg_virt_addr,
3096                             qdev->shadow_reg_phy_addr);
3097
3098         return -ENOMEM;
3099 }
3100
3101 static void ql_free_mem_resources(struct ql3_adapter *qdev)
3102 {
3103         ql_free_send_free_list(qdev);
3104         ql_free_large_buffers(qdev);
3105         ql_free_small_buffers(qdev);
3106         ql_free_buffer_queues(qdev);
3107         ql_free_net_req_rsp_queues(qdev);
3108         if (qdev->shadow_reg_virt_addr != NULL) {
3109                 pci_free_consistent(qdev->pdev,
3110                                     PAGE_SIZE,
3111                                     qdev->shadow_reg_virt_addr,
3112                                     qdev->shadow_reg_phy_addr);
3113                 qdev->shadow_reg_virt_addr = NULL;
3114         }
3115 }
3116
3117 static int ql_init_misc_registers(struct ql3_adapter *qdev)
3118 {
3119         struct ql3xxx_local_ram_registers __iomem *local_ram =
3120             (void __iomem *)qdev->mem_map_registers;
3121
3122         if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
3123                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3124                          2) << 4))
3125                 return -1;
3126
3127         ql_write_page2_reg(qdev,
3128                            &local_ram->bufletSize, qdev->nvram_data.bufletSize);
3129
3130         ql_write_page2_reg(qdev,
3131                            &local_ram->maxBufletCount,
3132                            qdev->nvram_data.bufletCount);
3133
3134         ql_write_page2_reg(qdev,
3135                            &local_ram->freeBufletThresholdLow,
3136                            (qdev->nvram_data.tcpWindowThreshold25 << 16) |
3137                            (qdev->nvram_data.tcpWindowThreshold0));
3138
3139         ql_write_page2_reg(qdev,
3140                            &local_ram->freeBufletThresholdHigh,
3141                            qdev->nvram_data.tcpWindowThreshold50);
3142
3143         ql_write_page2_reg(qdev,
3144                            &local_ram->ipHashTableBase,
3145                            (qdev->nvram_data.ipHashTableBaseHi << 16) |
3146                            qdev->nvram_data.ipHashTableBaseLo);
3147         ql_write_page2_reg(qdev,
3148                            &local_ram->ipHashTableCount,
3149                            qdev->nvram_data.ipHashTableSize);
3150         ql_write_page2_reg(qdev,
3151                            &local_ram->tcpHashTableBase,
3152                            (qdev->nvram_data.tcpHashTableBaseHi << 16) |
3153                            qdev->nvram_data.tcpHashTableBaseLo);
3154         ql_write_page2_reg(qdev,
3155                            &local_ram->tcpHashTableCount,
3156                            qdev->nvram_data.tcpHashTableSize);
3157         ql_write_page2_reg(qdev,
3158                            &local_ram->ncbBase,
3159                            (qdev->nvram_data.ncbTableBaseHi << 16) |
3160                            qdev->nvram_data.ncbTableBaseLo);
3161         ql_write_page2_reg(qdev,
3162                            &local_ram->maxNcbCount,
3163                            qdev->nvram_data.ncbTableSize);
3164         ql_write_page2_reg(qdev,
3165                            &local_ram->drbBase,
3166                            (qdev->nvram_data.drbTableBaseHi << 16) |
3167                            qdev->nvram_data.drbTableBaseLo);
3168         ql_write_page2_reg(qdev,
3169                            &local_ram->maxDrbCount,
3170                            qdev->nvram_data.drbTableSize);
3171         ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
3172         return 0;
3173 }
3174
3175 static int ql_adapter_initialize(struct ql3_adapter *qdev)
3176 {
3177         u32 value;
3178         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3179         struct ql3xxx_host_memory_registers __iomem *hmem_regs =
3180                                                 (void __iomem *)port_regs;
3181         u32 delay = 10;
3182         int status = 0;
3183
3184         if(ql_mii_setup(qdev))
3185                 return -1;
3186
3187         /* Bring out PHY out of reset */
3188         ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
3189                             (ISP_SERIAL_PORT_IF_WE |
3190                              (ISP_SERIAL_PORT_IF_WE << 16)));
3191
3192         qdev->port_link_state = LS_DOWN;
3193         netif_carrier_off(qdev->ndev);
3194
3195         /* V2 chip fix for ARS-39168. */
3196         ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
3197                             (ISP_SERIAL_PORT_IF_SDE |
3198                              (ISP_SERIAL_PORT_IF_SDE << 16)));
3199
3200         /* Request Queue Registers */
3201         *((u32 *) (qdev->preq_consumer_index)) = 0;
3202         atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES);
3203         qdev->req_producer_index = 0;
3204
3205         ql_write_page1_reg(qdev,
3206                            &hmem_regs->reqConsumerIndexAddrHigh,
3207                            qdev->req_consumer_index_phy_addr_high);
3208         ql_write_page1_reg(qdev,
3209                            &hmem_regs->reqConsumerIndexAddrLow,
3210                            qdev->req_consumer_index_phy_addr_low);
3211
3212         ql_write_page1_reg(qdev,
3213                            &hmem_regs->reqBaseAddrHigh,
3214                            MS_64BITS(qdev->req_q_phy_addr));
3215         ql_write_page1_reg(qdev,
3216                            &hmem_regs->reqBaseAddrLow,
3217                            LS_64BITS(qdev->req_q_phy_addr));
3218         ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
3219
3220         /* Response Queue Registers */
3221         *((u16 *) (qdev->prsp_producer_index)) = 0;
3222         qdev->rsp_consumer_index = 0;
3223         qdev->rsp_current = qdev->rsp_q_virt_addr;
3224
3225         ql_write_page1_reg(qdev,
3226                            &hmem_regs->rspProducerIndexAddrHigh,
3227                            qdev->rsp_producer_index_phy_addr_high);
3228
3229         ql_write_page1_reg(qdev,
3230                            &hmem_regs->rspProducerIndexAddrLow,
3231                            qdev->rsp_producer_index_phy_addr_low);
3232
3233         ql_write_page1_reg(qdev,
3234                            &hmem_regs->rspBaseAddrHigh,
3235                            MS_64BITS(qdev->rsp_q_phy_addr));
3236
3237         ql_write_page1_reg(qdev,
3238                            &hmem_regs->rspBaseAddrLow,
3239                            LS_64BITS(qdev->rsp_q_phy_addr));
3240
3241         ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
3242
3243         /* Large Buffer Queue */
3244         ql_write_page1_reg(qdev,
3245                            &hmem_regs->rxLargeQBaseAddrHigh,
3246                            MS_64BITS(qdev->lrg_buf_q_phy_addr));
3247
3248         ql_write_page1_reg(qdev,
3249                            &hmem_regs->rxLargeQBaseAddrLow,
3250                            LS_64BITS(qdev->lrg_buf_q_phy_addr));
3251
3252         ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, qdev->num_lbufq_entries);
3253
3254         ql_write_page1_reg(qdev,
3255                            &hmem_regs->rxLargeBufferLength,
3256                            qdev->lrg_buffer_len);
3257
3258         /* Small Buffer Queue */
3259         ql_write_page1_reg(qdev,
3260                            &hmem_regs->rxSmallQBaseAddrHigh,
3261                            MS_64BITS(qdev->small_buf_q_phy_addr));
3262
3263         ql_write_page1_reg(qdev,
3264                            &hmem_regs->rxSmallQBaseAddrLow,
3265                            LS_64BITS(qdev->small_buf_q_phy_addr));
3266
3267         ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3268         ql_write_page1_reg(qdev,
3269                            &hmem_regs->rxSmallBufferLength,
3270                            QL_SMALL_BUFFER_SIZE);
3271
3272         qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3273         qdev->small_buf_release_cnt = 8;
3274         qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
3275         qdev->lrg_buf_release_cnt = 8;
3276         qdev->lrg_buf_next_free =
3277             (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
3278         qdev->small_buf_index = 0;
3279         qdev->lrg_buf_index = 0;
3280         qdev->lrg_buf_free_count = 0;
3281         qdev->lrg_buf_free_head = NULL;
3282         qdev->lrg_buf_free_tail = NULL;
3283
3284         ql_write_common_reg(qdev,
3285                             &port_regs->CommonRegs.
3286                             rxSmallQProducerIndex,
3287                             qdev->small_buf_q_producer_index);
3288         ql_write_common_reg(qdev,
3289                             &port_regs->CommonRegs.
3290                             rxLargeQProducerIndex,
3291                             qdev->lrg_buf_q_producer_index);
3292
3293         /*
3294          * Find out if the chip has already been initialized.  If it has, then
3295          * we skip some of the initialization.
3296          */
3297         clear_bit(QL_LINK_MASTER, &qdev->flags);
3298         value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3299         if ((value & PORT_STATUS_IC) == 0) {
3300
3301                 /* Chip has not been configured yet, so let it rip. */
3302                 if(ql_init_misc_registers(qdev)) {
3303                         status = -1;
3304                         goto out;
3305                 }
3306
3307                 value = qdev->nvram_data.tcpMaxWindowSize;
3308                 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3309
3310                 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3311
3312                 if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3313                                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3314                                  * 2) << 13)) {
3315                         status = -1;
3316                         goto out;
3317                 }
3318                 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3319                 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3320                                    (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3321                                      16) | (INTERNAL_CHIP_SD |
3322                                             INTERNAL_CHIP_WE)));
3323                 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3324         }
3325
3326         if (qdev->mac_index)
3327                 ql_write_page0_reg(qdev,
3328                                    &port_regs->mac1MaxFrameLengthReg,
3329                                    qdev->max_frame_size);
3330         else
3331                 ql_write_page0_reg(qdev,
3332                                            &port_regs->mac0MaxFrameLengthReg,
3333                                            qdev->max_frame_size);
3334
3335         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3336                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3337                          2) << 7)) {
3338                 status = -1;
3339                 goto out;
3340         }
3341
3342         PHY_Setup(qdev);
3343         ql_init_scan_mode(qdev);
3344         ql_get_phy_owner(qdev);
3345
3346         /* Load the MAC Configuration */
3347
3348         /* Program lower 32 bits of the MAC address */
3349         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3350                            (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3351         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3352                            ((qdev->ndev->dev_addr[2] << 24)
3353                             | (qdev->ndev->dev_addr[3] << 16)
3354                             | (qdev->ndev->dev_addr[4] << 8)
3355                             | qdev->ndev->dev_addr[5]));
3356
3357         /* Program top 16 bits of the MAC address */
3358         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3359                            ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3360         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3361                            ((qdev->ndev->dev_addr[0] << 8)
3362                             | qdev->ndev->dev_addr[1]));
3363
3364         /* Enable Primary MAC */
3365         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3366                            ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3367                             MAC_ADDR_INDIRECT_PTR_REG_PE));
3368
3369         /* Clear Primary and Secondary IP addresses */
3370         ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3371                            ((IP_ADDR_INDEX_REG_MASK << 16) |
3372                             (qdev->mac_index << 2)));
3373         ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3374
3375         ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3376                            ((IP_ADDR_INDEX_REG_MASK << 16) |
3377                             ((qdev->mac_index << 2) + 1)));
3378         ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3379
3380         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3381
3382         /* Indicate Configuration Complete */
3383         ql_write_page0_reg(qdev,
3384                            &port_regs->portControl,
3385                            ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3386
3387         do {
3388                 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3389                 if (value & PORT_STATUS_IC)
3390                         break;
3391                 msleep(500);
3392         } while (--delay);
3393
3394         if (delay == 0) {
3395                 printk(KERN_ERR PFX
3396                        "%s: Hw Initialization timeout.\n", qdev->ndev->name);
3397                 status = -1;
3398                 goto out;
3399         }
3400
3401         /* Enable Ethernet Function */
3402         if (qdev->device_id == QL3032_DEVICE_ID) {
3403                 value =
3404                     (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3405                      QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
3406                         QL3032_PORT_CONTROL_ET);
3407                 ql_write_page0_reg(qdev, &port_regs->functionControl,
3408                                    ((value << 16) | value));
3409         } else {
3410                 value =
3411                     (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3412                      PORT_CONTROL_HH);
3413                 ql_write_page0_reg(qdev, &port_regs->portControl,
3414                                    ((value << 16) | value));
3415         }
3416
3417
3418 out:
3419         return status;
3420 }
3421
3422 /*
3423  * Caller holds hw_lock.
3424  */
3425 static int ql_adapter_reset(struct ql3_adapter *qdev)
3426 {
3427         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3428         int status = 0;
3429         u16 value;
3430         int max_wait_time;
3431
3432         set_bit(QL_RESET_ACTIVE, &qdev->flags);
3433         clear_bit(QL_RESET_DONE, &qdev->flags);
3434
3435         /*
3436          * Issue soft reset to chip.
3437          */
3438         printk(KERN_DEBUG PFX
3439                "%s: Issue soft reset to chip.\n",
3440                qdev->ndev->name);
3441         ql_write_common_reg(qdev,
3442                             &port_regs->CommonRegs.ispControlStatus,
3443                             ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3444
3445         /* Wait 3 seconds for reset to complete. */
3446         printk(KERN_DEBUG PFX
3447                "%s: Wait 10 milliseconds for reset to complete.\n",
3448                qdev->ndev->name);
3449
3450         /* Wait until the firmware tells us the Soft Reset is done */
3451         max_wait_time = 5;
3452         do {
3453                 value =
3454                     ql_read_common_reg(qdev,
3455                                        &port_regs->CommonRegs.ispControlStatus);
3456                 if ((value & ISP_CONTROL_SR) == 0)
3457                         break;
3458
3459                 ssleep(1);
3460         } while ((--max_wait_time));
3461
3462         /*
3463          * Also, make sure that the Network Reset Interrupt bit has been
3464          * cleared after the soft reset has taken place.
3465          */
3466         value =
3467             ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3468         if (value & ISP_CONTROL_RI) {
3469                 printk(KERN_DEBUG PFX
3470                        "ql_adapter_reset: clearing RI after reset.\n");
3471                 ql_write_common_reg(qdev,
3472                                     &port_regs->CommonRegs.
3473                                     ispControlStatus,
3474                                     ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3475         }
3476
3477         if (max_wait_time == 0) {
3478                 /* Issue Force Soft Reset */
3479                 ql_write_common_reg(qdev,
3480                                     &port_regs->CommonRegs.
3481                                     ispControlStatus,
3482                                     ((ISP_CONTROL_FSR << 16) |
3483                                      ISP_CONTROL_FSR));
3484                 /*
3485                  * Wait until the firmware tells us the Force Soft Reset is
3486                  * done
3487                  */
3488                 max_wait_time = 5;
3489                 do {
3490                         value =
3491                             ql_read_common_reg(qdev,
3492                                                &port_regs->CommonRegs.
3493                                                ispControlStatus);
3494                         if ((value & ISP_CONTROL_FSR) == 0) {
3495                                 break;
3496                         }
3497                         ssleep(1);
3498                 } while ((--max_wait_time));
3499         }
3500         if (max_wait_time == 0)
3501                 status = 1;
3502
3503         clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3504         set_bit(QL_RESET_DONE, &qdev->flags);
3505         return status;
3506 }
3507
3508 static void ql_set_mac_info(struct ql3_adapter *qdev)
3509 {
3510         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3511         u32 value, port_status;
3512         u8 func_number;
3513
3514         /* Get the function number */
3515         value =
3516             ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3517         func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3518         port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3519         switch (value & ISP_CONTROL_FN_MASK) {
3520         case ISP_CONTROL_FN0_NET:
3521                 qdev->mac_index = 0;
3522                 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3523                 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3524                 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3525                 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3526                 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3527                 if (port_status & PORT_STATUS_SM0)
3528                         set_bit(QL_LINK_OPTICAL,&qdev->flags);
3529                 else
3530                         clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3531                 break;
3532
3533         case ISP_CONTROL_FN1_NET:
3534                 qdev->mac_index = 1;
3535                 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3536                 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3537                 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3538                 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3539                 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3540                 if (port_status & PORT_STATUS_SM1)
3541                         set_bit(QL_LINK_OPTICAL,&qdev->flags);
3542                 else
3543                         clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3544                 break;
3545
3546         case ISP_CONTROL_FN0_SCSI:
3547         case ISP_CONTROL_FN1_SCSI:
3548         default:
3549                 printk(KERN_DEBUG PFX
3550                        "%s: Invalid function number, ispControlStatus = 0x%x\n",
3551                        qdev->ndev->name,value);
3552                 break;
3553         }
3554         qdev->numPorts = qdev->nvram_data.numPorts;
3555 }
3556
3557 static void ql_display_dev_info(struct net_device *ndev)
3558 {
3559         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3560         struct pci_dev *pdev = qdev->pdev;
3561
3562         printk(KERN_INFO PFX
3563                "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n",
3564                DRV_NAME, qdev->index, qdev->chip_rev_id,
3565                (qdev->device_id == QL3032_DEVICE_ID) ? "QLA3032" : "QLA3022",
3566                qdev->pci_slot);
3567         printk(KERN_INFO PFX
3568                "%s Interface.\n",
3569                test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER");
3570
3571         /*
3572          * Print PCI bus width/type.
3573          */
3574         printk(KERN_INFO PFX
3575                "Bus interface is %s %s.\n",
3576                ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3577                ((qdev->pci_x) ? "PCI-X" : "PCI"));
3578
3579         printk(KERN_INFO PFX
3580                "mem  IO base address adjusted = 0x%p\n",
3581                qdev->mem_map_registers);
3582         printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq);
3583
3584         if (netif_msg_probe(qdev))
3585                 printk(KERN_INFO PFX
3586                        "%s: MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
3587                        ndev->name, ndev->dev_addr[0], ndev->dev_addr[1],
3588                        ndev->dev_addr[2], ndev->dev_addr[3], ndev->dev_addr[4],
3589                        ndev->dev_addr[5]);
3590 }
3591
3592 static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3593 {
3594         struct net_device *ndev = qdev->ndev;
3595         int retval = 0;
3596
3597         netif_stop_queue(ndev);
3598         netif_carrier_off(ndev);
3599
3600         clear_bit(QL_ADAPTER_UP,&qdev->flags);
3601         clear_bit(QL_LINK_MASTER,&qdev->flags);
3602
3603         ql_disable_interrupts(qdev);
3604
3605         free_irq(qdev->pdev->irq, ndev);
3606
3607         if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3608                 printk(KERN_INFO PFX
3609                        "%s: calling pci_disable_msi().\n", qdev->ndev->name);
3610                 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3611                 pci_disable_msi(qdev->pdev);
3612         }
3613
3614         del_timer_sync(&qdev->adapter_timer);
3615
3616         napi_disable(&qdev->napi);
3617
3618         if (do_reset) {
3619                 int soft_reset;
3620                 unsigned long hw_flags;
3621
3622                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3623                 if (ql_wait_for_drvr_lock(qdev)) {
3624                         if ((soft_reset = ql_adapter_reset(qdev))) {
3625                                 printk(KERN_ERR PFX
3626                                        "%s: ql_adapter_reset(%d) FAILED!\n",
3627                                        ndev->name, qdev->index);
3628                         }
3629                         printk(KERN_ERR PFX
3630                                 "%s: Releaseing driver lock via chip reset.\n",ndev->name);
3631                 } else {
3632                         printk(KERN_ERR PFX
3633                                "%s: Could not acquire driver lock to do "
3634                                "reset!\n", ndev->name);
3635                         retval = -1;
3636                 }
3637                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3638         }
3639         ql_free_mem_resources(qdev);
3640         return retval;
3641 }
3642
3643 static int ql_adapter_up(struct ql3_adapter *qdev)
3644 {
3645         struct net_device *ndev = qdev->ndev;
3646         int err;
3647         unsigned long irq_flags = IRQF_SAMPLE_RANDOM | IRQF_SHARED;
3648         unsigned long hw_flags;
3649
3650         if (ql_alloc_mem_resources(qdev)) {
3651                 printk(KERN_ERR PFX
3652                        "%s Unable to  allocate buffers.\n", ndev->name);
3653                 return -ENOMEM;
3654         }
3655
3656         if (qdev->msi) {
3657                 if (pci_enable_msi(qdev->pdev)) {
3658                         printk(KERN_ERR PFX
3659                                "%s: User requested MSI, but MSI failed to "
3660                                "initialize.  Continuing without MSI.\n",
3661                                qdev->ndev->name);
3662                         qdev->msi = 0;
3663                 } else {
3664                         printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name);
3665                         set_bit(QL_MSI_ENABLED,&qdev->flags);
3666                         irq_flags &= ~IRQF_SHARED;
3667                 }
3668         }
3669
3670         if ((err = request_irq(qdev->pdev->irq,
3671                                ql3xxx_isr,
3672                                irq_flags, ndev->name, ndev))) {
3673                 printk(KERN_ERR PFX
3674                        "%s: Failed to reserve interrupt %d already in use.\n",
3675                        ndev->name, qdev->pdev->irq);
3676                 goto err_irq;
3677         }
3678
3679         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3680
3681         if ((err = ql_wait_for_drvr_lock(qdev))) {
3682                 if ((err = ql_adapter_initialize(qdev))) {
3683                         printk(KERN_ERR PFX
3684                                "%s: Unable to initialize adapter.\n",
3685                                ndev->name);
3686                         goto err_init;
3687                 }
3688                 printk(KERN_ERR PFX
3689                                 "%s: Releaseing driver lock.\n",ndev->name);
3690                 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3691         } else {
3692                 printk(KERN_ERR PFX
3693                        "%s: Could not aquire driver lock.\n",
3694                        ndev->name);
3695                 goto err_lock;
3696         }
3697
3698         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3699
3700         set_bit(QL_ADAPTER_UP,&qdev->flags);
3701
3702         mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3703
3704         napi_enable(&qdev->napi);
3705         ql_enable_interrupts(qdev);
3706         return 0;
3707
3708 err_init:
3709         ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3710 err_lock:
3711         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3712         free_irq(qdev->pdev->irq, ndev);
3713 err_irq:
3714         if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3715                 printk(KERN_INFO PFX
3716                        "%s: calling pci_disable_msi().\n",
3717                        qdev->ndev->name);
3718                 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3719                 pci_disable_msi(qdev->pdev);
3720         }
3721         return err;
3722 }
3723
3724 static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3725 {
3726         if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) {
3727                 printk(KERN_ERR PFX
3728                                 "%s: Driver up/down cycle failed, "
3729                                 "closing device\n",qdev->ndev->name);
3730                 dev_close(qdev->ndev);
3731                 return -1;
3732         }
3733         return 0;
3734 }
3735
3736 static int ql3xxx_close(struct net_device *ndev)
3737 {
3738         struct ql3_adapter *qdev = netdev_priv(ndev);
3739
3740         /*
3741          * Wait for device to recover from a reset.
3742          * (Rarely happens, but possible.)
3743          */
3744         while (!test_bit(QL_ADAPTER_UP,&qdev->flags))
3745                 msleep(50);
3746
3747         ql_adapter_down(qdev,QL_DO_RESET);
3748         return 0;
3749 }
3750
3751 static int ql3xxx_open(struct net_device *ndev)
3752 {
3753         struct ql3_adapter *qdev = netdev_priv(ndev);
3754         return (ql_adapter_up(qdev));
3755 }
3756
3757 static struct net_device_stats *ql3xxx_get_stats(struct net_device *dev)
3758 {
3759         struct ql3_adapter *qdev = (struct ql3_adapter *)dev->priv;
3760         return &qdev->stats;
3761 }
3762
3763 static void ql3xxx_set_multicast_list(struct net_device *ndev)
3764 {
3765         /*
3766          * We are manually parsing the list in the net_device structure.
3767          */
3768         return;
3769 }
3770
3771 static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3772 {
3773         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3774         struct ql3xxx_port_registers __iomem *port_regs =
3775                         qdev->mem_map_registers;
3776         struct sockaddr *addr = p;
3777         unsigned long hw_flags;
3778
3779         if (netif_running(ndev))
3780                 return -EBUSY;
3781
3782         if (!is_valid_ether_addr(addr->sa_data))
3783                 return -EADDRNOTAVAIL;
3784
3785         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3786
3787         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3788         /* Program lower 32 bits of the MAC address */
3789         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3790                            (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3791         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3792                            ((ndev->dev_addr[2] << 24) | (ndev->
3793                                                          dev_addr[3] << 16) |
3794                             (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3795
3796         /* Program top 16 bits of the MAC address */
3797         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3798                            ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3799         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3800                            ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3801         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3802
3803         return 0;
3804 }
3805
3806 static void ql3xxx_tx_timeout(struct net_device *ndev)
3807 {
3808         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3809
3810         printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name);
3811         /*
3812          * Stop the queues, we've got a problem.
3813          */
3814         netif_stop_queue(ndev);
3815
3816         /*
3817          * Wake up the worker to process this event.
3818          */
3819         queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3820 }
3821
3822 static void ql_reset_work(struct work_struct *work)
3823 {
3824         struct ql3_adapter *qdev =
3825                 container_of(work, struct ql3_adapter, reset_work.work);
3826         struct net_device *ndev = qdev->ndev;
3827         u32 value;
3828         struct ql_tx_buf_cb *tx_cb;
3829         int max_wait_time, i;
3830         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3831         unsigned long hw_flags;
3832
3833         if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) {
3834                 clear_bit(QL_LINK_MASTER,&qdev->flags);
3835
3836                 /*
3837                  * Loop through the active list and return the skb.
3838                  */
3839                 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3840                         int j;
3841                         tx_cb = &qdev->tx_buf[i];
3842                         if (tx_cb->skb) {
3843                                 printk(KERN_DEBUG PFX
3844                                        "%s: Freeing lost SKB.\n",
3845                                        qdev->ndev->name);
3846                                 pci_unmap_single(qdev->pdev,
3847                                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
3848                                          pci_unmap_len(&tx_cb->map[0], maplen),
3849                                          PCI_DMA_TODEVICE);
3850                                 for(j=1;j<tx_cb->seg_count;j++) {
3851                                         pci_unmap_page(qdev->pdev,
3852                                                pci_unmap_addr(&tx_cb->map[j],mapaddr),
3853                                                pci_unmap_len(&tx_cb->map[j],maplen),
3854                                                PCI_DMA_TODEVICE);
3855                                 }
3856                                 dev_kfree_skb(tx_cb->skb);
3857                                 tx_cb->skb = NULL;
3858                         }
3859                 }
3860
3861                 printk(KERN_ERR PFX
3862                        "%s: Clearing NRI after reset.\n", qdev->ndev->name);
3863                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3864                 ql_write_common_reg(qdev,
3865                                     &port_regs->CommonRegs.
3866                                     ispControlStatus,
3867                                     ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3868                 /*
3869                  * Wait the for Soft Reset to Complete.
3870                  */
3871                 max_wait_time = 10;
3872                 do {
3873                         value = ql_read_common_reg(qdev,
3874                                                    &port_regs->CommonRegs.
3875
3876                                                    ispControlStatus);
3877                         if ((value & ISP_CONTROL_SR) == 0) {
3878                                 printk(KERN_DEBUG PFX
3879                                        "%s: reset completed.\n",
3880                                        qdev->ndev->name);
3881                                 break;
3882                         }
3883
3884                         if (value & ISP_CONTROL_RI) {
3885                                 printk(KERN_DEBUG PFX
3886                                        "%s: clearing NRI after reset.\n",
3887                                        qdev->ndev->name);
3888                                 ql_write_common_reg(qdev,
3889                                                     &port_regs->
3890                                                     CommonRegs.
3891                                                     ispControlStatus,
3892                                                     ((ISP_CONTROL_RI <<
3893                                                       16) | ISP_CONTROL_RI));
3894                         }
3895
3896                         ssleep(1);
3897                 } while (--max_wait_time);
3898                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3899
3900                 if (value & ISP_CONTROL_SR) {
3901
3902                         /*
3903                          * Set the reset flags and clear the board again.
3904                          * Nothing else to do...
3905                          */
3906                         printk(KERN_ERR PFX
3907                                "%s: Timed out waiting for reset to "
3908                                "complete.\n", ndev->name);
3909                         printk(KERN_ERR PFX
3910                                "%s: Do a reset.\n", ndev->name);
3911                         clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3912                         clear_bit(QL_RESET_START,&qdev->flags);
3913                         ql_cycle_adapter(qdev,QL_DO_RESET);
3914                         return;
3915                 }
3916
3917                 clear_bit(QL_RESET_ACTIVE,&qdev->flags);
3918                 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3919                 clear_bit(QL_RESET_START,&qdev->flags);
3920                 ql_cycle_adapter(qdev,QL_NO_RESET);
3921         }
3922 }
3923
3924 static void ql_tx_timeout_work(struct work_struct *work)
3925 {
3926         struct ql3_adapter *qdev =
3927                 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3928
3929         ql_cycle_adapter(qdev, QL_DO_RESET);
3930 }
3931
3932 static void ql_get_board_info(struct ql3_adapter *qdev)
3933 {
3934         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3935         u32 value;
3936
3937         value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3938
3939         qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3940         if (value & PORT_STATUS_64)
3941                 qdev->pci_width = 64;
3942         else
3943                 qdev->pci_width = 32;
3944         if (value & PORT_STATUS_X)
3945                 qdev->pci_x = 1;
3946         else
3947                 qdev->pci_x = 0;
3948         qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3949 }
3950
3951 static void ql3xxx_timer(unsigned long ptr)
3952 {
3953         struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3954
3955         if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
3956                 printk(KERN_DEBUG PFX
3957                        "%s: Reset in progress.\n",
3958                        qdev->ndev->name);
3959                 goto end;
3960         }
3961
3962         ql_link_state_machine(qdev);
3963
3964         /* Restart timer on 2 second interval. */
3965 end:
3966         mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3967 }
3968
3969 static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3970                                   const struct pci_device_id *pci_entry)
3971 {
3972         struct net_device *ndev = NULL;
3973         struct ql3_adapter *qdev = NULL;
3974         static int cards_found = 0;
3975         int pci_using_dac, err;
3976
3977         err = pci_enable_device(pdev);
3978         if (err) {
3979                 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3980                        pci_name(pdev));
3981                 goto err_out;
3982         }
3983
3984         err = pci_request_regions(pdev, DRV_NAME);
3985         if (err) {
3986                 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3987                        pci_name(pdev));
3988                 goto err_out_disable_pdev;
3989         }
3990
3991         pci_set_master(pdev);
3992
3993         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3994                 pci_using_dac = 1;
3995                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3996         } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3997                 pci_using_dac = 0;
3998                 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3999         }
4000
4001         if (err) {
4002                 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
4003                        pci_name(pdev));
4004                 goto err_out_free_regions;
4005         }
4006
4007         ndev = alloc_etherdev(sizeof(struct ql3_adapter));
4008         if (!ndev) {
4009                 printk(KERN_ERR PFX "%s could not alloc etherdev\n",
4010                        pci_name(pdev));
4011                 err = -ENOMEM;
4012                 goto err_out_free_regions;
4013         }
4014
4015         SET_MODULE_OWNER(ndev);
4016         SET_NETDEV_DEV(ndev, &pdev->dev);
4017
4018         pci_set_drvdata(pdev, ndev);
4019
4020         qdev = netdev_priv(ndev);
4021         qdev->index = cards_found;
4022         qdev->ndev = ndev;
4023         qdev->pdev = pdev;
4024         qdev->device_id = pci_entry->device;
4025         qdev->port_link_state = LS_DOWN;
4026         if (msi)
4027                 qdev->msi = 1;
4028
4029         qdev->msg_enable = netif_msg_init(debug, default_msg);
4030
4031         if (pci_using_dac)
4032                 ndev->features |= NETIF_F_HIGHDMA;
4033         if (qdev->device_id == QL3032_DEVICE_ID)
4034                 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
4035
4036         qdev->mem_map_registers =
4037             ioremap_nocache(pci_resource_start(pdev, 1),
4038                             pci_resource_len(qdev->pdev, 1));
4039         if (!qdev->mem_map_registers) {
4040                 printk(KERN_ERR PFX "%s: cannot map device registers\n",
4041                        pci_name(pdev));
4042                 err = -EIO;
4043                 goto err_out_free_ndev;
4044         }
4045
4046         spin_lock_init(&qdev->adapter_lock);
4047         spin_lock_init(&qdev->hw_lock);
4048
4049         /* Set driver entry points */
4050         ndev->open = ql3xxx_open;
4051         ndev->hard_start_xmit = ql3xxx_send;
4052         ndev->stop = ql3xxx_close;
4053         ndev->get_stats = ql3xxx_get_stats;
4054         ndev->set_multicast_list = ql3xxx_set_multicast_list;
4055         SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
4056         ndev->set_mac_address = ql3xxx_set_mac_address;
4057         ndev->tx_timeout = ql3xxx_tx_timeout;
4058         ndev->watchdog_timeo = 5 * HZ;
4059
4060         netif_napi_add(ndev, &qdev->napi, ql_poll, 64);
4061
4062         ndev->irq = pdev->irq;
4063
4064         /* make sure the EEPROM is good */
4065         if (ql_get_nvram_params(qdev)) {
4066                 printk(KERN_ALERT PFX
4067                        "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
4068                        qdev->index);
4069                 err = -EIO;
4070                 goto err_out_iounmap;
4071         }
4072
4073         ql_set_mac_info(qdev);
4074
4075         /* Validate and set parameters */
4076         if (qdev->mac_index) {
4077                 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
4078                 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn2.macAddress,
4079                        ETH_ALEN);
4080         } else {
4081                 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
4082                 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn0.macAddress,
4083                        ETH_ALEN);
4084         }
4085         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
4086
4087         ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
4088
4089         /* Turn off support for multicasting */
4090         ndev->flags &= ~IFF_MULTICAST;
4091
4092         /* Record PCI bus information. */
4093         ql_get_board_info(qdev);
4094
4095         /*
4096          * Set the Maximum Memory Read Byte Count value. We do this to handle
4097          * jumbo frames.
4098          */
4099         if (qdev->pci_x) {
4100                 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
4101         }
4102
4103         err = register_netdev(ndev);
4104         if (err) {
4105                 printk(KERN_ERR PFX "%s: cannot register net device\n",
4106                        pci_name(pdev));
4107                 goto err_out_iounmap;
4108         }
4109
4110         /* we're going to reset, so assume we have no link for now */
4111
4112         netif_carrier_off(ndev);
4113         netif_stop_queue(ndev);
4114
4115         qdev->workqueue = create_singlethread_workqueue(ndev->name);
4116         INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
4117         INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
4118
4119         init_timer(&qdev->adapter_timer);
4120         qdev->adapter_timer.function = ql3xxx_timer;
4121         qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
4122         qdev->adapter_timer.data = (unsigned long)qdev;
4123
4124         if(!cards_found) {
4125                 printk(KERN_ALERT PFX "%s\n", DRV_STRING);
4126                 printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n",
4127                    DRV_NAME, DRV_VERSION);
4128         }
4129         ql_display_dev_info(ndev);
4130
4131         cards_found++;
4132         return 0;
4133
4134 err_out_iounmap:
4135         iounmap(qdev->mem_map_registers);
4136 err_out_free_ndev:
4137         free_netdev(ndev);
4138 err_out_free_regions:
4139         pci_release_regions(pdev);
4140 err_out_disable_pdev:
4141         pci_disable_device(pdev);
4142         pci_set_drvdata(pdev, NULL);
4143 err_out:
4144         return err;
4145 }
4146
4147 static void __devexit ql3xxx_remove(struct pci_dev *pdev)
4148 {
4149         struct net_device *ndev = pci_get_drvdata(pdev);
4150         struct ql3_adapter *qdev = netdev_priv(ndev);
4151
4152         unregister_netdev(ndev);
4153         qdev = netdev_priv(ndev);
4154
4155         ql_disable_interrupts(qdev);
4156
4157         if (qdev->workqueue) {
4158                 cancel_delayed_work(&qdev->reset_work);
4159                 cancel_delayed_work(&qdev->tx_timeout_work);
4160                 destroy_workqueue(qdev->workqueue);
4161                 qdev->workqueue = NULL;
4162         }
4163
4164         iounmap(qdev->mem_map_registers);
4165         pci_release_regions(pdev);
4166         pci_set_drvdata(pdev, NULL);
4167         free_netdev(ndev);
4168 }
4169
4170 static struct pci_driver ql3xxx_driver = {
4171
4172         .name = DRV_NAME,
4173         .id_table = ql3xxx_pci_tbl,
4174         .probe = ql3xxx_probe,
4175         .remove = __devexit_p(ql3xxx_remove),
4176 };
4177
4178 static int __init ql3xxx_init_module(void)
4179 {
4180         return pci_register_driver(&ql3xxx_driver);
4181 }
4182
4183 static void __exit ql3xxx_exit(void)
4184 {
4185         pci_unregister_driver(&ql3xxx_driver);
4186 }
4187
4188 module_init(ql3xxx_init_module);
4189 module_exit(ql3xxx_exit);