tg3 / broadcom: Add PHY_BRCM_CLEAR_RGMII_MODE flag
[linux-2.6.git] / drivers / net / phy / broadcom.c
1 /*
2  *      drivers/net/phy/broadcom.c
3  *
4  *      Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
5  *      transceivers.
6  *
7  *      Copyright (c) 2006  Maciej W. Rozycki
8  *
9  *      Inspired by code written by Amy Fong.
10  *
11  *      This program is free software; you can redistribute it and/or
12  *      modify it under the terms of the GNU General Public License
13  *      as published by the Free Software Foundation; either version
14  *      2 of the License, or (at your option) any later version.
15  */
16
17 #include <linux/module.h>
18 #include <linux/phy.h>
19 #include <linux/brcmphy.h>
20
21 #define PHY_ID_BCM50610         0x0143bd60
22 #define PHY_ID_BCM50610M        0x0143bd70
23 #define PHY_ID_BCM57780         0x03625d90
24
25 #define BRCM_PHY_MODEL(phydev) \
26         ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
27
28
29 #define MII_BCM54XX_ECR         0x10    /* BCM54xx extended control register */
30 #define MII_BCM54XX_ECR_IM      0x1000  /* Interrupt mask */
31 #define MII_BCM54XX_ECR_IF      0x0800  /* Interrupt force */
32
33 #define MII_BCM54XX_ESR         0x11    /* BCM54xx extended status register */
34 #define MII_BCM54XX_ESR_IS      0x1000  /* Interrupt status */
35
36 #define MII_BCM54XX_EXP_DATA    0x15    /* Expansion register data */
37 #define MII_BCM54XX_EXP_SEL     0x17    /* Expansion register select */
38 #define MII_BCM54XX_EXP_SEL_SSD 0x0e00  /* Secondary SerDes select */
39 #define MII_BCM54XX_EXP_SEL_ER  0x0f00  /* Expansion register select */
40
41 #define MII_BCM54XX_AUX_CTL     0x18    /* Auxiliary control register */
42 #define MII_BCM54XX_ISR         0x1a    /* BCM54xx interrupt status register */
43 #define MII_BCM54XX_IMR         0x1b    /* BCM54xx interrupt mask register */
44 #define MII_BCM54XX_INT_CRCERR  0x0001  /* CRC error */
45 #define MII_BCM54XX_INT_LINK    0x0002  /* Link status changed */
46 #define MII_BCM54XX_INT_SPEED   0x0004  /* Link speed change */
47 #define MII_BCM54XX_INT_DUPLEX  0x0008  /* Duplex mode changed */
48 #define MII_BCM54XX_INT_LRS     0x0010  /* Local receiver status changed */
49 #define MII_BCM54XX_INT_RRS     0x0020  /* Remote receiver status changed */
50 #define MII_BCM54XX_INT_SSERR   0x0040  /* Scrambler synchronization error */
51 #define MII_BCM54XX_INT_UHCD    0x0080  /* Unsupported HCD negotiated */
52 #define MII_BCM54XX_INT_NHCD    0x0100  /* No HCD */
53 #define MII_BCM54XX_INT_NHCDL   0x0200  /* No HCD link */
54 #define MII_BCM54XX_INT_ANPR    0x0400  /* Auto-negotiation page received */
55 #define MII_BCM54XX_INT_LC      0x0800  /* All counters below 128 */
56 #define MII_BCM54XX_INT_HC      0x1000  /* Counter above 32768 */
57 #define MII_BCM54XX_INT_MDIX    0x2000  /* MDIX status change */
58 #define MII_BCM54XX_INT_PSERR   0x4000  /* Pair swap error */
59
60 #define MII_BCM54XX_SHD         0x1c    /* 0x1c shadow registers */
61 #define MII_BCM54XX_SHD_WRITE   0x8000
62 #define MII_BCM54XX_SHD_VAL(x)  ((x & 0x1f) << 10)
63 #define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
64
65 /*
66  * AUXILIARY CONTROL SHADOW ACCESS REGISTERS.  (PHY REG 0x18)
67  */
68 #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL       0x0000
69 #define MII_BCM54XX_AUXCTL_ACTL_TX_6DB          0x0400
70 #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA       0x0800
71
72 #define MII_BCM54XX_AUXCTL_MISC_WREN    0x8000
73 #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX     0x0200
74 #define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC      0x7000
75 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
76
77 #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL       0x0000
78
79
80 /*
81  * Broadcom LED source encodings.  These are used in BCM5461, BCM5481,
82  * BCM5482, and possibly some others.
83  */
84 #define BCM_LED_SRC_LINKSPD1    0x0
85 #define BCM_LED_SRC_LINKSPD2    0x1
86 #define BCM_LED_SRC_XMITLED     0x2
87 #define BCM_LED_SRC_ACTIVITYLED 0x3
88 #define BCM_LED_SRC_FDXLED      0x4
89 #define BCM_LED_SRC_SLAVE       0x5
90 #define BCM_LED_SRC_INTR        0x6
91 #define BCM_LED_SRC_QUALITY     0x7
92 #define BCM_LED_SRC_RCVLED      0x8
93 #define BCM_LED_SRC_MULTICOLOR1 0xa
94 #define BCM_LED_SRC_OPENSHORT   0xb
95 #define BCM_LED_SRC_OFF         0xe     /* Tied high */
96 #define BCM_LED_SRC_ON          0xf     /* Tied low */
97
98 /*
99  * BCM5482: Shadow registers
100  * Shadow values go into bits [14:10] of register 0x1c to select a shadow
101  * register to access.
102  */
103 #define BCM5482_SHD_LEDS1       0x0d    /* 01101: LED Selector 1 */
104                                         /* LED3 / ~LINKSPD[2] selector */
105 #define BCM5482_SHD_LEDS1_LED3(src)     ((src & 0xf) << 4)
106                                         /* LED1 / ~LINKSPD[1] selector */
107 #define BCM5482_SHD_LEDS1_LED1(src)     ((src & 0xf) << 0)
108 #define BCM54XX_SHD_RGMII_MODE  0x0b    /* 01011: RGMII Mode Selector */
109 #define BCM5482_SHD_SSD         0x14    /* 10100: Secondary SerDes control */
110 #define BCM5482_SHD_SSD_LEDM    0x0008  /* SSD LED Mode enable */
111 #define BCM5482_SHD_SSD_EN      0x0001  /* SSD enable */
112 #define BCM5482_SHD_MODE        0x1f    /* 11111: Mode Control Register */
113 #define BCM5482_SHD_MODE_1000BX 0x0001  /* Enable 1000BASE-X registers */
114
115 /*
116  * EXPANSION SHADOW ACCESS REGISTERS.  (PHY REG 0x15, 0x16, and 0x17)
117  */
118 #define MII_BCM54XX_EXP_AADJ1CH0                0x001f
119 #define  MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN  0x0200
120 #define  MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF    0x0100
121 #define MII_BCM54XX_EXP_AADJ1CH3                0x601f
122 #define  MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ      0x0002
123 #define MII_BCM54XX_EXP_EXP08                   0x0F08
124 #define  MII_BCM54XX_EXP_EXP08_RJCT_2MHZ        0x0001
125 #define  MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE   0x0200
126 #define MII_BCM54XX_EXP_EXP75                   0x0f75
127 #define  MII_BCM54XX_EXP_EXP75_VDACCTRL         0x003c
128 #define  MII_BCM54XX_EXP_EXP75_CM_OSC           0x0001
129 #define MII_BCM54XX_EXP_EXP96                   0x0f96
130 #define  MII_BCM54XX_EXP_EXP96_MYST             0x0010
131 #define MII_BCM54XX_EXP_EXP97                   0x0f97
132 #define  MII_BCM54XX_EXP_EXP97_MYST             0x0c0c
133
134 /*
135  * BCM5482: Secondary SerDes registers
136  */
137 #define BCM5482_SSD_1000BX_CTL          0x00    /* 1000BASE-X Control */
138 #define BCM5482_SSD_1000BX_CTL_PWRDOWN  0x0800  /* Power-down SSD */
139 #define BCM5482_SSD_SGMII_SLAVE         0x15    /* SGMII Slave Register */
140 #define BCM5482_SSD_SGMII_SLAVE_EN      0x0002  /* Slave mode enable */
141 #define BCM5482_SSD_SGMII_SLAVE_AD      0x0001  /* Slave auto-detection */
142
143
144 /*****************************************************************************/
145 /* Fast Ethernet Transceiver definitions. */
146 /*****************************************************************************/
147
148 #define MII_BRCM_FET_INTREG             0x1a    /* Interrupt register */
149 #define MII_BRCM_FET_IR_MASK            0x0100  /* Mask all interrupts */
150 #define MII_BRCM_FET_IR_LINK_EN         0x0200  /* Link status change enable */
151 #define MII_BRCM_FET_IR_SPEED_EN        0x0400  /* Link speed change enable */
152 #define MII_BRCM_FET_IR_DUPLEX_EN       0x0800  /* Duplex mode change enable */
153 #define MII_BRCM_FET_IR_ENABLE          0x4000  /* Interrupt enable */
154
155 #define MII_BRCM_FET_BRCMTEST           0x1f    /* Brcm test register */
156 #define MII_BRCM_FET_BT_SRE             0x0080  /* Shadow register enable */
157
158
159 /*** Shadow register definitions ***/
160
161 #define MII_BRCM_FET_SHDW_MISCCTRL      0x10    /* Shadow misc ctrl */
162 #define MII_BRCM_FET_SHDW_MC_FAME       0x4000  /* Force Auto MDIX enable */
163
164 #define MII_BRCM_FET_SHDW_AUXMODE4      0x1a    /* Auxiliary mode 4 */
165 #define MII_BRCM_FET_SHDW_AM4_LED_MASK  0x0003
166 #define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001
167
168 #define MII_BRCM_FET_SHDW_AUXSTAT2      0x1b    /* Auxiliary status 2 */
169 #define MII_BRCM_FET_SHDW_AS2_APDE      0x0020  /* Auto power down enable */
170
171
172 MODULE_DESCRIPTION("Broadcom PHY driver");
173 MODULE_AUTHOR("Maciej W. Rozycki");
174 MODULE_LICENSE("GPL");
175
176 /*
177  * Indirect register access functions for the 1000BASE-T/100BASE-TX/10BASE-T
178  * 0x1c shadow registers.
179  */
180 static int bcm54xx_shadow_read(struct phy_device *phydev, u16 shadow)
181 {
182         phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
183         return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD));
184 }
185
186 static int bcm54xx_shadow_write(struct phy_device *phydev, u16 shadow, u16 val)
187 {
188         return phy_write(phydev, MII_BCM54XX_SHD,
189                          MII_BCM54XX_SHD_WRITE |
190                          MII_BCM54XX_SHD_VAL(shadow) |
191                          MII_BCM54XX_SHD_DATA(val));
192 }
193
194 /* Indirect register access functions for the Expansion Registers */
195 static int bcm54xx_exp_read(struct phy_device *phydev, u16 regnum)
196 {
197         int val;
198
199         val = phy_write(phydev, MII_BCM54XX_EXP_SEL, regnum);
200         if (val < 0)
201                 return val;
202
203         val = phy_read(phydev, MII_BCM54XX_EXP_DATA);
204
205         /* Restore default value.  It's O.K. if this write fails. */
206         phy_write(phydev, MII_BCM54XX_EXP_SEL, 0);
207
208         return val;
209 }
210
211 static int bcm54xx_exp_write(struct phy_device *phydev, u16 regnum, u16 val)
212 {
213         int ret;
214
215         ret = phy_write(phydev, MII_BCM54XX_EXP_SEL, regnum);
216         if (ret < 0)
217                 return ret;
218
219         ret = phy_write(phydev, MII_BCM54XX_EXP_DATA, val);
220
221         /* Restore default value.  It's O.K. if this write fails. */
222         phy_write(phydev, MII_BCM54XX_EXP_SEL, 0);
223
224         return ret;
225 }
226
227 static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
228 {
229         return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
230 }
231
232 /* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
233 static int bcm50610_a0_workaround(struct phy_device *phydev)
234 {
235         int err;
236
237         err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_AADJ1CH0,
238                                 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
239                                 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
240         if (err < 0)
241                 return err;
242
243         err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_AADJ1CH3,
244                                         MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
245         if (err < 0)
246                 return err;
247
248         err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP75,
249                                 MII_BCM54XX_EXP_EXP75_VDACCTRL);
250         if (err < 0)
251                 return err;
252
253         err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP96,
254                                 MII_BCM54XX_EXP_EXP96_MYST);
255         if (err < 0)
256                 return err;
257
258         err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP97,
259                                 MII_BCM54XX_EXP_EXP97_MYST);
260
261         return err;
262 }
263
264 static int bcm54xx_phydsp_config(struct phy_device *phydev)
265 {
266         int err, err2;
267
268         /* Enable the SMDSP clock */
269         err = bcm54xx_auxctl_write(phydev,
270                                    MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
271                                    MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
272                                    MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
273         if (err < 0)
274                 return err;
275
276         if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
277             BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
278                 /* Clear bit 9 to fix a phy interop issue. */
279                 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP08,
280                                         MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
281                 if (err < 0)
282                         goto error;
283
284                 if (phydev->drv->phy_id == PHY_ID_BCM50610) {
285                         err = bcm50610_a0_workaround(phydev);
286                         if (err < 0)
287                                 goto error;
288                 }
289         }
290
291         if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
292                 int val;
293
294                 val = bcm54xx_exp_read(phydev, MII_BCM54XX_EXP_EXP75);
295                 if (val < 0)
296                         goto error;
297
298                 val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
299                 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP75, val);
300         }
301
302 error:
303         /* Disable the SMDSP clock */
304         err2 = bcm54xx_auxctl_write(phydev,
305                                     MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
306                                     MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
307
308         /* Return the first error reported. */
309         return err ? err : err2;
310 }
311
312 static int bcm54xx_config_init(struct phy_device *phydev)
313 {
314         int reg, err;
315
316         reg = phy_read(phydev, MII_BCM54XX_ECR);
317         if (reg < 0)
318                 return reg;
319
320         /* Mask interrupts globally.  */
321         reg |= MII_BCM54XX_ECR_IM;
322         err = phy_write(phydev, MII_BCM54XX_ECR, reg);
323         if (err < 0)
324                 return err;
325
326         /* Unmask events we are interested in.  */
327         reg = ~(MII_BCM54XX_INT_DUPLEX |
328                 MII_BCM54XX_INT_SPEED |
329                 MII_BCM54XX_INT_LINK);
330         err = phy_write(phydev, MII_BCM54XX_IMR, reg);
331         if (err < 0)
332                 return err;
333
334         if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
335              BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
336             (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
337                 bcm54xx_shadow_write(phydev, BCM54XX_SHD_RGMII_MODE, 0);
338
339         bcm54xx_phydsp_config(phydev);
340
341         return 0;
342 }
343
344 static int bcm5482_config_init(struct phy_device *phydev)
345 {
346         int err, reg;
347
348         err = bcm54xx_config_init(phydev);
349
350         if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
351                 /*
352                  * Enable secondary SerDes and its use as an LED source
353                  */
354                 reg = bcm54xx_shadow_read(phydev, BCM5482_SHD_SSD);
355                 bcm54xx_shadow_write(phydev, BCM5482_SHD_SSD,
356                                      reg |
357                                      BCM5482_SHD_SSD_LEDM |
358                                      BCM5482_SHD_SSD_EN);
359
360                 /*
361                  * Enable SGMII slave mode and auto-detection
362                  */
363                 reg = BCM5482_SSD_SGMII_SLAVE | MII_BCM54XX_EXP_SEL_SSD;
364                 err = bcm54xx_exp_read(phydev, reg);
365                 if (err < 0)
366                         return err;
367                 err = bcm54xx_exp_write(phydev, reg, err |
368                                         BCM5482_SSD_SGMII_SLAVE_EN |
369                                         BCM5482_SSD_SGMII_SLAVE_AD);
370                 if (err < 0)
371                         return err;
372
373                 /*
374                  * Disable secondary SerDes powerdown
375                  */
376                 reg = BCM5482_SSD_1000BX_CTL | MII_BCM54XX_EXP_SEL_SSD;
377                 err = bcm54xx_exp_read(phydev, reg);
378                 if (err < 0)
379                         return err;
380                 err = bcm54xx_exp_write(phydev, reg,
381                                         err & ~BCM5482_SSD_1000BX_CTL_PWRDOWN);
382                 if (err < 0)
383                         return err;
384
385                 /*
386                  * Select 1000BASE-X register set (primary SerDes)
387                  */
388                 reg = bcm54xx_shadow_read(phydev, BCM5482_SHD_MODE);
389                 bcm54xx_shadow_write(phydev, BCM5482_SHD_MODE,
390                                      reg | BCM5482_SHD_MODE_1000BX);
391
392                 /*
393                  * LED1=ACTIVITYLED, LED3=LINKSPD[2]
394                  * (Use LED1 as secondary SerDes ACTIVITY LED)
395                  */
396                 bcm54xx_shadow_write(phydev, BCM5482_SHD_LEDS1,
397                         BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_ACTIVITYLED) |
398                         BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_LINKSPD2));
399
400                 /*
401                  * Auto-negotiation doesn't seem to work quite right
402                  * in this mode, so we disable it and force it to the
403                  * right speed/duplex setting.  Only 'link status'
404                  * is important.
405                  */
406                 phydev->autoneg = AUTONEG_DISABLE;
407                 phydev->speed = SPEED_1000;
408                 phydev->duplex = DUPLEX_FULL;
409         }
410
411         return err;
412 }
413
414 static int bcm5482_read_status(struct phy_device *phydev)
415 {
416         int err;
417
418         err = genphy_read_status(phydev);
419
420         if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
421                 /*
422                  * Only link status matters for 1000Base-X mode, so force
423                  * 1000 Mbit/s full-duplex status
424                  */
425                 if (phydev->link) {
426                         phydev->speed = SPEED_1000;
427                         phydev->duplex = DUPLEX_FULL;
428                 }
429         }
430
431         return err;
432 }
433
434 static int bcm54xx_ack_interrupt(struct phy_device *phydev)
435 {
436         int reg;
437
438         /* Clear pending interrupts.  */
439         reg = phy_read(phydev, MII_BCM54XX_ISR);
440         if (reg < 0)
441                 return reg;
442
443         return 0;
444 }
445
446 static int bcm54xx_config_intr(struct phy_device *phydev)
447 {
448         int reg, err;
449
450         reg = phy_read(phydev, MII_BCM54XX_ECR);
451         if (reg < 0)
452                 return reg;
453
454         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
455                 reg &= ~MII_BCM54XX_ECR_IM;
456         else
457                 reg |= MII_BCM54XX_ECR_IM;
458
459         err = phy_write(phydev, MII_BCM54XX_ECR, reg);
460         return err;
461 }
462
463 static int bcm5481_config_aneg(struct phy_device *phydev)
464 {
465         int ret;
466
467         /* Aneg firsly. */
468         ret = genphy_config_aneg(phydev);
469
470         /* Then we can set up the delay. */
471         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
472                 u16 reg;
473
474                 /*
475                  * There is no BCM5481 specification available, so down
476                  * here is everything we know about "register 0x18". This
477                  * at least helps BCM5481 to successfuly receive packets
478                  * on MPC8360E-RDK board. Peter Barada <peterb@logicpd.com>
479                  * says: "This sets delay between the RXD and RXC signals
480                  * instead of using trace lengths to achieve timing".
481                  */
482
483                 /* Set RDX clk delay. */
484                 reg = 0x7 | (0x7 << 12);
485                 phy_write(phydev, 0x18, reg);
486
487                 reg = phy_read(phydev, 0x18);
488                 /* Set RDX-RXC skew. */
489                 reg |= (1 << 8);
490                 /* Write bits 14:0. */
491                 reg |= (1 << 15);
492                 phy_write(phydev, 0x18, reg);
493         }
494
495         return ret;
496 }
497
498 static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
499 {
500         int val;
501
502         val = phy_read(phydev, reg);
503         if (val < 0)
504                 return val;
505
506         return phy_write(phydev, reg, val | set);
507 }
508
509 static int brcm_fet_config_init(struct phy_device *phydev)
510 {
511         int reg, err, err2, brcmtest;
512
513         /* Reset the PHY to bring it to a known state. */
514         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
515         if (err < 0)
516                 return err;
517
518         reg = phy_read(phydev, MII_BRCM_FET_INTREG);
519         if (reg < 0)
520                 return reg;
521
522         /* Unmask events we are interested in and mask interrupts globally. */
523         reg = MII_BRCM_FET_IR_DUPLEX_EN |
524               MII_BRCM_FET_IR_SPEED_EN |
525               MII_BRCM_FET_IR_LINK_EN |
526               MII_BRCM_FET_IR_ENABLE |
527               MII_BRCM_FET_IR_MASK;
528
529         err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
530         if (err < 0)
531                 return err;
532
533         /* Enable shadow register access */
534         brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
535         if (brcmtest < 0)
536                 return brcmtest;
537
538         reg = brcmtest | MII_BRCM_FET_BT_SRE;
539
540         err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
541         if (err < 0)
542                 return err;
543
544         /* Set the LED mode */
545         reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
546         if (reg < 0) {
547                 err = reg;
548                 goto done;
549         }
550
551         reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
552         reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
553
554         err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
555         if (err < 0)
556                 goto done;
557
558         /* Enable auto MDIX */
559         err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
560                                        MII_BRCM_FET_SHDW_MC_FAME);
561         if (err < 0)
562                 goto done;
563
564         /* Enable auto power down */
565         err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
566                                        MII_BRCM_FET_SHDW_AS2_APDE);
567
568 done:
569         /* Disable shadow register access */
570         err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
571         if (!err)
572                 err = err2;
573
574         return err;
575 }
576
577 static int brcm_fet_ack_interrupt(struct phy_device *phydev)
578 {
579         int reg;
580
581         /* Clear pending interrupts.  */
582         reg = phy_read(phydev, MII_BRCM_FET_INTREG);
583         if (reg < 0)
584                 return reg;
585
586         return 0;
587 }
588
589 static int brcm_fet_config_intr(struct phy_device *phydev)
590 {
591         int reg, err;
592
593         reg = phy_read(phydev, MII_BRCM_FET_INTREG);
594         if (reg < 0)
595                 return reg;
596
597         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
598                 reg &= ~MII_BRCM_FET_IR_MASK;
599         else
600                 reg |= MII_BRCM_FET_IR_MASK;
601
602         err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
603         return err;
604 }
605
606 static struct phy_driver bcm5411_driver = {
607         .phy_id         = 0x00206070,
608         .phy_id_mask    = 0xfffffff0,
609         .name           = "Broadcom BCM5411",
610         .features       = PHY_GBIT_FEATURES |
611                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
612         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
613         .config_init    = bcm54xx_config_init,
614         .config_aneg    = genphy_config_aneg,
615         .read_status    = genphy_read_status,
616         .ack_interrupt  = bcm54xx_ack_interrupt,
617         .config_intr    = bcm54xx_config_intr,
618         .driver         = { .owner = THIS_MODULE },
619 };
620
621 static struct phy_driver bcm5421_driver = {
622         .phy_id         = 0x002060e0,
623         .phy_id_mask    = 0xfffffff0,
624         .name           = "Broadcom BCM5421",
625         .features       = PHY_GBIT_FEATURES |
626                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
627         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
628         .config_init    = bcm54xx_config_init,
629         .config_aneg    = genphy_config_aneg,
630         .read_status    = genphy_read_status,
631         .ack_interrupt  = bcm54xx_ack_interrupt,
632         .config_intr    = bcm54xx_config_intr,
633         .driver         = { .owner = THIS_MODULE },
634 };
635
636 static struct phy_driver bcm5461_driver = {
637         .phy_id         = 0x002060c0,
638         .phy_id_mask    = 0xfffffff0,
639         .name           = "Broadcom BCM5461",
640         .features       = PHY_GBIT_FEATURES |
641                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
642         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
643         .config_init    = bcm54xx_config_init,
644         .config_aneg    = genphy_config_aneg,
645         .read_status    = genphy_read_status,
646         .ack_interrupt  = bcm54xx_ack_interrupt,
647         .config_intr    = bcm54xx_config_intr,
648         .driver         = { .owner = THIS_MODULE },
649 };
650
651 static struct phy_driver bcm5464_driver = {
652         .phy_id         = 0x002060b0,
653         .phy_id_mask    = 0xfffffff0,
654         .name           = "Broadcom BCM5464",
655         .features       = PHY_GBIT_FEATURES |
656                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
657         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
658         .config_init    = bcm54xx_config_init,
659         .config_aneg    = genphy_config_aneg,
660         .read_status    = genphy_read_status,
661         .ack_interrupt  = bcm54xx_ack_interrupt,
662         .config_intr    = bcm54xx_config_intr,
663         .driver         = { .owner = THIS_MODULE },
664 };
665
666 static struct phy_driver bcm5481_driver = {
667         .phy_id         = 0x0143bca0,
668         .phy_id_mask    = 0xfffffff0,
669         .name           = "Broadcom BCM5481",
670         .features       = PHY_GBIT_FEATURES |
671                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
672         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
673         .config_init    = bcm54xx_config_init,
674         .config_aneg    = bcm5481_config_aneg,
675         .read_status    = genphy_read_status,
676         .ack_interrupt  = bcm54xx_ack_interrupt,
677         .config_intr    = bcm54xx_config_intr,
678         .driver         = { .owner = THIS_MODULE },
679 };
680
681 static struct phy_driver bcm5482_driver = {
682         .phy_id         = 0x0143bcb0,
683         .phy_id_mask    = 0xfffffff0,
684         .name           = "Broadcom BCM5482",
685         .features       = PHY_GBIT_FEATURES |
686                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
687         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
688         .config_init    = bcm5482_config_init,
689         .config_aneg    = genphy_config_aneg,
690         .read_status    = bcm5482_read_status,
691         .ack_interrupt  = bcm54xx_ack_interrupt,
692         .config_intr    = bcm54xx_config_intr,
693         .driver         = { .owner = THIS_MODULE },
694 };
695
696 static struct phy_driver bcm50610_driver = {
697         .phy_id         = PHY_ID_BCM50610,
698         .phy_id_mask    = 0xfffffff0,
699         .name           = "Broadcom BCM50610",
700         .features       = PHY_GBIT_FEATURES |
701                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
702         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
703         .config_init    = bcm54xx_config_init,
704         .config_aneg    = genphy_config_aneg,
705         .read_status    = genphy_read_status,
706         .ack_interrupt  = bcm54xx_ack_interrupt,
707         .config_intr    = bcm54xx_config_intr,
708         .driver         = { .owner = THIS_MODULE },
709 };
710
711 static struct phy_driver bcm50610m_driver = {
712         .phy_id         = PHY_ID_BCM50610M,
713         .phy_id_mask    = 0xfffffff0,
714         .name           = "Broadcom BCM50610M",
715         .features       = PHY_GBIT_FEATURES |
716                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
717         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
718         .config_init    = bcm54xx_config_init,
719         .config_aneg    = genphy_config_aneg,
720         .read_status    = genphy_read_status,
721         .ack_interrupt  = bcm54xx_ack_interrupt,
722         .config_intr    = bcm54xx_config_intr,
723         .driver         = { .owner = THIS_MODULE },
724 };
725
726 static struct phy_driver bcm57780_driver = {
727         .phy_id         = PHY_ID_BCM57780,
728         .phy_id_mask    = 0xfffffff0,
729         .name           = "Broadcom BCM57780",
730         .features       = PHY_GBIT_FEATURES |
731                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
732         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
733         .config_init    = bcm54xx_config_init,
734         .config_aneg    = genphy_config_aneg,
735         .read_status    = genphy_read_status,
736         .ack_interrupt  = bcm54xx_ack_interrupt,
737         .config_intr    = bcm54xx_config_intr,
738         .driver         = { .owner = THIS_MODULE },
739 };
740
741 static struct phy_driver bcmac131_driver = {
742         .phy_id         = 0x0143bc70,
743         .phy_id_mask    = 0xfffffff0,
744         .name           = "Broadcom BCMAC131",
745         .features       = PHY_BASIC_FEATURES |
746                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
747         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
748         .config_init    = brcm_fet_config_init,
749         .config_aneg    = genphy_config_aneg,
750         .read_status    = genphy_read_status,
751         .ack_interrupt  = brcm_fet_ack_interrupt,
752         .config_intr    = brcm_fet_config_intr,
753         .driver         = { .owner = THIS_MODULE },
754 };
755
756 static int __init broadcom_init(void)
757 {
758         int ret;
759
760         ret = phy_driver_register(&bcm5411_driver);
761         if (ret)
762                 goto out_5411;
763         ret = phy_driver_register(&bcm5421_driver);
764         if (ret)
765                 goto out_5421;
766         ret = phy_driver_register(&bcm5461_driver);
767         if (ret)
768                 goto out_5461;
769         ret = phy_driver_register(&bcm5464_driver);
770         if (ret)
771                 goto out_5464;
772         ret = phy_driver_register(&bcm5481_driver);
773         if (ret)
774                 goto out_5481;
775         ret = phy_driver_register(&bcm5482_driver);
776         if (ret)
777                 goto out_5482;
778         ret = phy_driver_register(&bcm50610_driver);
779         if (ret)
780                 goto out_50610;
781         ret = phy_driver_register(&bcm50610m_driver);
782         if (ret)
783                 goto out_50610m;
784         ret = phy_driver_register(&bcm57780_driver);
785         if (ret)
786                 goto out_57780;
787         ret = phy_driver_register(&bcmac131_driver);
788         if (ret)
789                 goto out_ac131;
790         return ret;
791
792 out_ac131:
793         phy_driver_unregister(&bcm57780_driver);
794 out_57780:
795         phy_driver_unregister(&bcm50610m_driver);
796 out_50610m:
797         phy_driver_unregister(&bcm50610_driver);
798 out_50610:
799         phy_driver_unregister(&bcm5482_driver);
800 out_5482:
801         phy_driver_unregister(&bcm5481_driver);
802 out_5481:
803         phy_driver_unregister(&bcm5464_driver);
804 out_5464:
805         phy_driver_unregister(&bcm5461_driver);
806 out_5461:
807         phy_driver_unregister(&bcm5421_driver);
808 out_5421:
809         phy_driver_unregister(&bcm5411_driver);
810 out_5411:
811         return ret;
812 }
813
814 static void __exit broadcom_exit(void)
815 {
816         phy_driver_unregister(&bcmac131_driver);
817         phy_driver_unregister(&bcm57780_driver);
818         phy_driver_unregister(&bcm50610m_driver);
819         phy_driver_unregister(&bcm50610_driver);
820         phy_driver_unregister(&bcm5482_driver);
821         phy_driver_unregister(&bcm5481_driver);
822         phy_driver_unregister(&bcm5464_driver);
823         phy_driver_unregister(&bcm5461_driver);
824         phy_driver_unregister(&bcm5421_driver);
825         phy_driver_unregister(&bcm5411_driver);
826 }
827
828 module_init(broadcom_init);
829 module_exit(broadcom_exit);