niu: Determine the # of ports from the card's VPD data
[linux-2.6.git] / drivers / net / niu.h
1 /* niu.h: Definitions for Neptune ethernet driver.
2  *
3  * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
4  */
5
6 #ifndef _NIU_H
7 #define _NIU_H
8
9 #define PIO                     0x000000UL
10 #define FZC_PIO                 0x080000UL
11 #define FZC_MAC                 0x180000UL
12 #define FZC_IPP                 0x280000UL
13 #define FFLP                    0x300000UL
14 #define FZC_FFLP                0x380000UL
15 #define PIO_VADDR               0x400000UL
16 #define ZCP                     0x500000UL
17 #define FZC_ZCP                 0x580000UL
18 #define DMC                     0x600000UL
19 #define FZC_DMC                 0x680000UL
20 #define TXC                     0x700000UL
21 #define FZC_TXC                 0x780000UL
22 #define PIO_LDSV                0x800000UL
23 #define PIO_PIO_LDGIM           0x900000UL
24 #define PIO_IMASK0              0xa00000UL
25 #define PIO_IMASK1              0xb00000UL
26 #define FZC_PROM                0xc80000UL
27 #define FZC_PIM                 0xd80000UL
28
29 #define LDSV0(LDG)              (PIO_LDSV + 0x00000UL + (LDG) * 0x2000UL)
30 #define LDSV1(LDG)              (PIO_LDSV + 0x00008UL + (LDG) * 0x2000UL)
31 #define LDSV2(LDG)              (PIO_LDSV + 0x00010UL + (LDG) * 0x2000UL)
32
33 #define LDG_IMGMT(LDG)          (PIO_LDSV + 0x00018UL + (LDG) * 0x2000UL)
34 #define  LDG_IMGMT_ARM          0x0000000080000000ULL
35 #define  LDG_IMGMT_TIMER        0x000000000000003fULL
36
37 #define LD_IM0(IDX)             (PIO_IMASK0 + 0x00000UL + (IDX) * 0x2000UL)
38 #define  LD_IM0_MASK            0x0000000000000003ULL
39
40 #define LD_IM1(IDX)             (PIO_IMASK1 + 0x00000UL + (IDX) * 0x2000UL)
41 #define  LD_IM1_MASK            0x0000000000000003ULL
42
43 #define LDG_TIMER_RES           (FZC_PIO + 0x00008UL)
44 #define  LDG_TIMER_RES_VAL      0x00000000000fffffULL
45
46 #define DIRTY_TID_CTL           (FZC_PIO + 0x00010UL)
47 #define  DIRTY_TID_CTL_NPTHRED  0x00000000003f0000ULL
48 #define  DIRTY_TID_CTL_RDTHRED  0x00000000000003f0ULL
49 #define  DIRTY_TID_CTL_DTIDCLR  0x0000000000000002ULL
50 #define  DIRTY_TID_CTL_DTIDENAB 0x0000000000000001ULL
51
52 #define DIRTY_TID_STAT          (FZC_PIO + 0x00018UL)
53 #define  DIRTY_TID_STAT_NPWSTAT 0x0000000000003f00ULL
54 #define  DIRTY_TID_STAT_RDSTAT  0x000000000000003fULL
55
56 #define RST_CTL                 (FZC_PIO + 0x00038UL)
57 #define  RST_CTL_MAC_RST3       0x0000000000400000ULL
58 #define  RST_CTL_MAC_RST2       0x0000000000200000ULL
59 #define  RST_CTL_MAC_RST1       0x0000000000100000ULL
60 #define  RST_CTL_MAC_RST0       0x0000000000080000ULL
61 #define  RST_CTL_ACK_TO_EN      0x0000000000000800ULL
62 #define  RST_CTL_ACK_TO_VAL     0x00000000000007feULL
63
64 #define SMX_CFIG_DAT            (FZC_PIO + 0x00040UL)
65 #define  SMX_CFIG_DAT_RAS_DET   0x0000000080000000ULL
66 #define  SMX_CFIG_DAT_RAS_INJ   0x0000000040000000ULL
67 #define  SMX_CFIG_DAT_XACT_TO   0x000000000fffffffULL
68
69 #define SMX_INT_STAT            (FZC_PIO + 0x00048UL)
70 #define  SMX_INT_STAT_STAT      0x00000000ffffffffULL
71
72 #define SMX_CTL                 (FZC_PIO + 0x00050UL)
73 #define  SMX_CTL_CTL            0x00000000ffffffffULL
74
75 #define SMX_DBG_VEC             (FZC_PIO + 0x00058UL)
76 #define  SMX_DBG_VEC_VEC        0x00000000ffffffffULL
77
78 #define PIO_DBG_SEL             (FZC_PIO + 0x00060UL)
79 #define  PIO_DBG_SEL_SEL        0x000000000000003fULL
80
81 #define PIO_TRAIN_VEC           (FZC_PIO + 0x00068UL)
82 #define  PIO_TRAIN_VEC_VEC      0x00000000ffffffffULL
83
84 #define PIO_ARB_CTL             (FZC_PIO + 0x00070UL)
85 #define  PIO_ARB_CTL_CTL        0x00000000ffffffffULL
86
87 #define PIO_ARB_DBG_VEC         (FZC_PIO + 0x00078UL)
88 #define  PIO_ARB_DBG_VEC_VEC    0x00000000ffffffffULL
89
90 #define SYS_ERR_MASK            (FZC_PIO + 0x00090UL)
91 #define  SYS_ERR_MASK_META2     0x0000000000000400ULL
92 #define  SYS_ERR_MASK_META1     0x0000000000000200ULL
93 #define  SYS_ERR_MASK_PEU       0x0000000000000100ULL
94 #define  SYS_ERR_MASK_TXC       0x0000000000000080ULL
95 #define  SYS_ERR_MASK_RDMC      0x0000000000000040ULL
96 #define  SYS_ERR_MASK_TDMC      0x0000000000000020ULL
97 #define  SYS_ERR_MASK_ZCP       0x0000000000000010ULL
98 #define  SYS_ERR_MASK_FFLP      0x0000000000000008ULL
99 #define  SYS_ERR_MASK_IPP       0x0000000000000004ULL
100 #define  SYS_ERR_MASK_MAC       0x0000000000000002ULL
101 #define  SYS_ERR_MASK_SMX       0x0000000000000001ULL
102
103 #define SYS_ERR_STAT                    (FZC_PIO + 0x00098UL)
104 #define  SYS_ERR_STAT_META2             0x0000000000000400ULL
105 #define  SYS_ERR_STAT_META1             0x0000000000000200ULL
106 #define  SYS_ERR_STAT_PEU               0x0000000000000100ULL
107 #define  SYS_ERR_STAT_TXC               0x0000000000000080ULL
108 #define  SYS_ERR_STAT_RDMC              0x0000000000000040ULL
109 #define  SYS_ERR_STAT_TDMC              0x0000000000000020ULL
110 #define  SYS_ERR_STAT_ZCP               0x0000000000000010ULL
111 #define  SYS_ERR_STAT_FFLP              0x0000000000000008ULL
112 #define  SYS_ERR_STAT_IPP               0x0000000000000004ULL
113 #define  SYS_ERR_STAT_MAC               0x0000000000000002ULL
114 #define  SYS_ERR_STAT_SMX               0x0000000000000001ULL
115
116 #define SID(LDG)                        (FZC_PIO + 0x10200UL + (LDG) * 8UL)
117 #define  SID_FUNC                       0x0000000000000060ULL
118 #define  SID_FUNC_SHIFT                 5
119 #define  SID_VECTOR                     0x000000000000001fULL
120 #define  SID_VECTOR_SHIFT               0
121
122 #define LDG_NUM(LDN)                    (FZC_PIO + 0x20000UL + (LDN) * 8UL)
123
124 #define XMAC_PORT0_OFF                  (FZC_MAC + 0x000000)
125 #define XMAC_PORT1_OFF                  (FZC_MAC + 0x006000)
126 #define BMAC_PORT2_OFF                  (FZC_MAC + 0x00c000)
127 #define BMAC_PORT3_OFF                  (FZC_MAC + 0x010000)
128
129 /* XMAC registers, offset from np->mac_regs  */
130
131 #define XTXMAC_SW_RST                   0x00000UL
132 #define  XTXMAC_SW_RST_REG_RS           0x0000000000000002ULL
133 #define  XTXMAC_SW_RST_SOFT_RST         0x0000000000000001ULL
134
135 #define XRXMAC_SW_RST                   0x00008UL
136 #define  XRXMAC_SW_RST_REG_RS           0x0000000000000002ULL
137 #define  XRXMAC_SW_RST_SOFT_RST         0x0000000000000001ULL
138
139 #define XTXMAC_STATUS                   0x00020UL
140 #define  XTXMAC_STATUS_FRAME_CNT_EXP    0x0000000000000800ULL
141 #define  XTXMAC_STATUS_BYTE_CNT_EXP     0x0000000000000400ULL
142 #define  XTXMAC_STATUS_TXFIFO_XFR_ERR   0x0000000000000010ULL
143 #define  XTXMAC_STATUS_TXMAC_OFLOW      0x0000000000000008ULL
144 #define  XTXMAC_STATUS_MAX_PSIZE_ERR    0x0000000000000004ULL
145 #define  XTXMAC_STATUS_TXMAC_UFLOW      0x0000000000000002ULL
146 #define  XTXMAC_STATUS_FRAME_XMITED     0x0000000000000001ULL
147
148 #define XRXMAC_STATUS                   0x00028UL
149 #define  XRXMAC_STATUS_RXHIST7_CNT_EXP  0x0000000000100000ULL
150 #define  XRXMAC_STATUS_LCL_FLT_STATUS   0x0000000000080000ULL
151 #define  XRXMAC_STATUS_RFLT_DET         0x0000000000040000ULL
152 #define  XRXMAC_STATUS_LFLT_CNT_EXP     0x0000000000020000ULL
153 #define  XRXMAC_STATUS_PHY_MDINT        0x0000000000010000ULL
154 #define  XRXMAC_STATUS_ALIGNERR_CNT_EXP 0x0000000000010000ULL
155 #define  XRXMAC_STATUS_RXFRAG_CNT_EXP   0x0000000000008000ULL
156 #define  XRXMAC_STATUS_RXMULTF_CNT_EXP  0x0000000000004000ULL
157 #define  XRXMAC_STATUS_RXBCAST_CNT_EXP  0x0000000000002000ULL
158 #define  XRXMAC_STATUS_RXHIST6_CNT_EXP  0x0000000000001000ULL
159 #define  XRXMAC_STATUS_RXHIST5_CNT_EXP  0x0000000000000800ULL
160 #define  XRXMAC_STATUS_RXHIST4_CNT_EXP  0x0000000000000400ULL
161 #define  XRXMAC_STATUS_RXHIST3_CNT_EXP  0x0000000000000200ULL
162 #define  XRXMAC_STATUS_RXHIST2_CNT_EXP  0x0000000000000100ULL
163 #define  XRXMAC_STATUS_RXHIST1_CNT_EXP  0x0000000000000080ULL
164 #define  XRXMAC_STATUS_RXOCTET_CNT_EXP  0x0000000000000040ULL
165 #define  XRXMAC_STATUS_CVIOLERR_CNT_EXP 0x0000000000000020ULL
166 #define  XRXMAC_STATUS_LENERR_CNT_EXP   0x0000000000000010ULL
167 #define  XRXMAC_STATUS_CRCERR_CNT_EXP   0x0000000000000008ULL
168 #define  XRXMAC_STATUS_RXUFLOW          0x0000000000000004ULL
169 #define  XRXMAC_STATUS_RXOFLOW          0x0000000000000002ULL
170 #define  XRXMAC_STATUS_FRAME_RCVD       0x0000000000000001ULL
171
172 #define XMAC_FC_STAT                    0x00030UL
173 #define  XMAC_FC_STAT_RX_RCV_PAUSE_TIME 0x00000000ffff0000ULL
174 #define  XMAC_FC_STAT_TX_MAC_NPAUSE     0x0000000000000004ULL
175 #define  XMAC_FC_STAT_TX_MAC_PAUSE      0x0000000000000002ULL
176 #define  XMAC_FC_STAT_RX_MAC_RPAUSE     0x0000000000000001ULL
177
178 #define XTXMAC_STAT_MSK                 0x00040UL
179 #define  XTXMAC_STAT_MSK_FRAME_CNT_EXP  0x0000000000000800ULL
180 #define  XTXMAC_STAT_MSK_BYTE_CNT_EXP   0x0000000000000400ULL
181 #define  XTXMAC_STAT_MSK_TXFIFO_XFR_ERR 0x0000000000000010ULL
182 #define  XTXMAC_STAT_MSK_TXMAC_OFLOW    0x0000000000000008ULL
183 #define  XTXMAC_STAT_MSK_MAX_PSIZE_ERR  0x0000000000000004ULL
184 #define  XTXMAC_STAT_MSK_TXMAC_UFLOW    0x0000000000000002ULL
185 #define  XTXMAC_STAT_MSK_FRAME_XMITED   0x0000000000000001ULL
186
187 #define XRXMAC_STAT_MSK                         0x00048UL
188 #define  XRXMAC_STAT_MSK_LCL_FLT_STAT_MSK       0x0000000000080000ULL
189 #define  XRXMAC_STAT_MSK_RFLT_DET               0x0000000000040000ULL
190 #define  XRXMAC_STAT_MSK_LFLT_CNT_EXP           0x0000000000020000ULL
191 #define  XRXMAC_STAT_MSK_PHY_MDINT              0x0000000000010000ULL
192 #define  XRXMAC_STAT_MSK_RXFRAG_CNT_EXP         0x0000000000008000ULL
193 #define  XRXMAC_STAT_MSK_RXMULTF_CNT_EXP        0x0000000000004000ULL
194 #define  XRXMAC_STAT_MSK_RXBCAST_CNT_EXP        0x0000000000002000ULL
195 #define  XRXMAC_STAT_MSK_RXHIST6_CNT_EXP        0x0000000000001000ULL
196 #define  XRXMAC_STAT_MSK_RXHIST5_CNT_EXP        0x0000000000000800ULL
197 #define  XRXMAC_STAT_MSK_RXHIST4_CNT_EXP        0x0000000000000400ULL
198 #define  XRXMAC_STAT_MSK_RXHIST3_CNT_EXP        0x0000000000000200ULL
199 #define  XRXMAC_STAT_MSK_RXHIST2_CNT_EXP        0x0000000000000100ULL
200 #define  XRXMAC_STAT_MSK_RXHIST1_CNT_EXP        0x0000000000000080ULL
201 #define  XRXMAC_STAT_MSK_RXOCTET_CNT_EXP        0x0000000000000040ULL
202 #define  XRXMAC_STAT_MSK_CVIOLERR_CNT_EXP       0x0000000000000020ULL
203 #define  XRXMAC_STAT_MSK_LENERR_CNT_EXP         0x0000000000000010ULL
204 #define  XRXMAC_STAT_MSK_CRCERR_CNT_EXP         0x0000000000000008ULL
205 #define  XRXMAC_STAT_MSK_RXUFLOW_CNT_EXP        0x0000000000000004ULL
206 #define  XRXMAC_STAT_MSK_RXOFLOW_CNT_EXP        0x0000000000000002ULL
207 #define  XRXMAC_STAT_MSK_FRAME_RCVD             0x0000000000000001ULL
208
209 #define XMAC_FC_MSK                     0x00050UL
210 #define  XMAC_FC_MSK_TX_MAC_NPAUSE      0x0000000000000004ULL
211 #define  XMAC_FC_MSK_TX_MAC_PAUSE       0x0000000000000002ULL
212 #define  XMAC_FC_MSK_RX_MAC_RPAUSE      0x0000000000000001ULL
213
214 #define XMAC_CONFIG                     0x00060UL
215 #define  XMAC_CONFIG_SEL_CLK_25MHZ      0x0000000080000000ULL
216 #define  XMAC_CONFIG_1G_PCS_BYPASS      0x0000000040000000ULL
217 #define  XMAC_CONFIG_10G_XPCS_BYPASS    0x0000000020000000ULL
218 #define  XMAC_CONFIG_MODE_MASK          0x0000000018000000ULL
219 #define  XMAC_CONFIG_MODE_XGMII         0x0000000000000000ULL
220 #define  XMAC_CONFIG_MODE_GMII          0x0000000008000000ULL
221 #define  XMAC_CONFIG_MODE_MII           0x0000000010000000ULL
222 #define  XMAC_CONFIG_LFS_DISABLE        0x0000000004000000ULL
223 #define  XMAC_CONFIG_LOOPBACK           0x0000000002000000ULL
224 #define  XMAC_CONFIG_TX_OUTPUT_EN       0x0000000001000000ULL
225 #define  XMAC_CONFIG_SEL_POR_CLK_SRC    0x0000000000800000ULL
226 #define  XMAC_CONFIG_LED_POLARITY       0x0000000000400000ULL
227 #define  XMAC_CONFIG_FORCE_LED_ON       0x0000000000200000ULL
228 #define  XMAC_CONFIG_PASS_FLOW_CTRL     0x0000000000100000ULL
229 #define  XMAC_CONFIG_RCV_PAUSE_ENABLE   0x0000000000080000ULL
230 #define  XMAC_CONFIG_MAC2IPP_PKT_CNT_EN 0x0000000000040000ULL
231 #define  XMAC_CONFIG_STRIP_CRC          0x0000000000020000ULL
232 #define  XMAC_CONFIG_ADDR_FILTER_EN     0x0000000000010000ULL
233 #define  XMAC_CONFIG_HASH_FILTER_EN     0x0000000000008000ULL
234 #define  XMAC_CONFIG_RX_CODEV_CHK_DIS   0x0000000000004000ULL
235 #define  XMAC_CONFIG_RESERVED_MULTICAST 0x0000000000002000ULL
236 #define  XMAC_CONFIG_RX_CRC_CHK_DIS     0x0000000000001000ULL
237 #define  XMAC_CONFIG_ERR_CHK_DIS        0x0000000000000800ULL
238 #define  XMAC_CONFIG_PROMISC_GROUP      0x0000000000000400ULL
239 #define  XMAC_CONFIG_PROMISCUOUS        0x0000000000000200ULL
240 #define  XMAC_CONFIG_RX_MAC_ENABLE      0x0000000000000100ULL
241 #define  XMAC_CONFIG_WARNING_MSG_EN     0x0000000000000080ULL
242 #define  XMAC_CONFIG_ALWAYS_NO_CRC      0x0000000000000008ULL
243 #define  XMAC_CONFIG_VAR_MIN_IPG_EN     0x0000000000000004ULL
244 #define  XMAC_CONFIG_STRETCH_MODE       0x0000000000000002ULL
245 #define  XMAC_CONFIG_TX_ENABLE          0x0000000000000001ULL
246
247 #define XMAC_IPG                        0x00080UL
248 #define  XMAC_IPG_STRETCH_CONST         0x0000000000e00000ULL
249 #define  XMAC_IPG_STRETCH_CONST_SHIFT   21
250 #define  XMAC_IPG_STRETCH_RATIO         0x00000000001f0000ULL
251 #define  XMAC_IPG_STRETCH_RATIO_SHIFT   16
252 #define  XMAC_IPG_IPG_MII_GMII          0x000000000000ff00ULL
253 #define  XMAC_IPG_IPG_MII_GMII_SHIFT    8
254 #define  XMAC_IPG_IPG_XGMII             0x0000000000000007ULL
255 #define  XMAC_IPG_IPG_XGMII_SHIFT       0
256
257 #define IPG_12_15_XGMII                 3
258 #define IPG_16_19_XGMII                 4
259 #define IPG_20_23_XGMII                 5
260 #define IPG_12_MII_GMII                 10
261 #define IPG_13_MII_GMII                 11
262 #define IPG_14_MII_GMII                 12
263 #define IPG_15_MII_GMII                 13
264 #define IPG_16_MII_GMII                 14
265
266 #define XMAC_MIN                        0x00088UL
267 #define  XMAC_MIN_RX_MIN_PKT_SIZE       0x000000003ff00000ULL
268 #define  XMAC_MIN_RX_MIN_PKT_SIZE_SHFT  20
269 #define  XMAC_MIN_SLOT_TIME             0x000000000003fc00ULL
270 #define  XMAC_MIN_SLOT_TIME_SHFT        10
271 #define  XMAC_MIN_TX_MIN_PKT_SIZE       0x00000000000003ffULL
272 #define  XMAC_MIN_TX_MIN_PKT_SIZE_SHFT  0
273
274 #define XMAC_MAX                        0x00090UL
275 #define  XMAC_MAX_FRAME_SIZE            0x0000000000003fffULL
276 #define  XMAC_MAX_FRAME_SIZE_SHFT       0
277
278 #define XMAC_ADDR0                      0x000a0UL
279 #define  XMAC_ADDR0_ADDR0               0x000000000000ffffULL
280
281 #define XMAC_ADDR1                      0x000a8UL
282 #define  XMAC_ADDR1_ADDR1               0x000000000000ffffULL
283
284 #define XMAC_ADDR2                      0x000b0UL 
285 #define  XMAC_ADDR2_ADDR2               0x000000000000ffffULL
286
287 #define XMAC_ADDR_CMPEN                 0x00208UL
288 #define  XMAC_ADDR_CMPEN_EN15           0x0000000000008000ULL
289 #define  XMAC_ADDR_CMPEN_EN14           0x0000000000004000ULL
290 #define  XMAC_ADDR_CMPEN_EN13           0x0000000000002000ULL
291 #define  XMAC_ADDR_CMPEN_EN12           0x0000000000001000ULL
292 #define  XMAC_ADDR_CMPEN_EN11           0x0000000000000800ULL
293 #define  XMAC_ADDR_CMPEN_EN10           0x0000000000000400ULL
294 #define  XMAC_ADDR_CMPEN_EN9            0x0000000000000200ULL
295 #define  XMAC_ADDR_CMPEN_EN8            0x0000000000000100ULL
296 #define  XMAC_ADDR_CMPEN_EN7            0x0000000000000080ULL
297 #define  XMAC_ADDR_CMPEN_EN6            0x0000000000000040ULL
298 #define  XMAC_ADDR_CMPEN_EN5            0x0000000000000020ULL
299 #define  XMAC_ADDR_CMPEN_EN4            0x0000000000000010ULL
300 #define  XMAC_ADDR_CMPEN_EN3            0x0000000000000008ULL
301 #define  XMAC_ADDR_CMPEN_EN2            0x0000000000000004ULL
302 #define  XMAC_ADDR_CMPEN_EN1            0x0000000000000002ULL
303 #define  XMAC_ADDR_CMPEN_EN0            0x0000000000000001ULL
304
305 #define XMAC_NUM_ALT_ADDR               16
306
307 #define XMAC_ALT_ADDR0(NUM)             (0x00218UL + (NUM)*0x18UL)
308 #define  XMAC_ALT_ADDR0_ADDR0           0x000000000000ffffULL
309
310 #define XMAC_ALT_ADDR1(NUM)             (0x00220UL + (NUM)*0x18UL)
311 #define  XMAC_ALT_ADDR1_ADDR1           0x000000000000ffffULL
312
313 #define XMAC_ALT_ADDR2(NUM)             (0x00228UL + (NUM)*0x18UL)
314 #define  XMAC_ALT_ADDR2_ADDR2           0x000000000000ffffULL
315
316 #define XMAC_ADD_FILT0                  0x00818UL
317 #define  XMAC_ADD_FILT0_FILT0           0x000000000000ffffULL
318
319 #define XMAC_ADD_FILT1                  0x00820UL
320 #define  XMAC_ADD_FILT1_FILT1           0x000000000000ffffULL
321
322 #define XMAC_ADD_FILT2                  0x00828UL
323 #define  XMAC_ADD_FILT2_FILT2           0x000000000000ffffULL
324
325 #define XMAC_ADD_FILT12_MASK            0x00830UL
326 #define  XMAC_ADD_FILT12_MASK_VAL       0x00000000000000ffULL
327
328 #define XMAC_ADD_FILT00_MASK            0x00838UL
329 #define  XMAC_ADD_FILT00_MASK_VAL       0x000000000000ffffULL
330
331 #define XMAC_HASH_TBL(NUM)              (0x00840UL + (NUM) * 0x8UL)
332 #define XMAC_HASH_TBL_VAL               0x000000000000ffffULL
333
334 #define XMAC_NUM_HOST_INFO              20
335
336 #define XMAC_HOST_INFO(NUM)             (0x00900UL + (NUM) * 0x8UL)
337
338 #define XMAC_PA_DATA0                   0x00b80UL
339 #define XMAC_PA_DATA0_VAL               0x00000000ffffffffULL
340
341 #define XMAC_PA_DATA1                   0x00b88UL
342 #define XMAC_PA_DATA1_VAL               0x00000000ffffffffULL
343
344 #define XMAC_DEBUG_SEL                  0x00b90UL
345 #define  XMAC_DEBUG_SEL_XMAC            0x0000000000000078ULL
346 #define  XMAC_DEBUG_SEL_MAC             0x0000000000000007ULL
347
348 #define XMAC_TRAIN_VEC                  0x00b98UL
349 #define  XMAC_TRAIN_VEC_VAL             0x00000000ffffffffULL
350
351 #define RXMAC_BT_CNT                    0x00100UL
352 #define  RXMAC_BT_CNT_COUNT             0x00000000ffffffffULL
353
354 #define RXMAC_BC_FRM_CNT                0x00108UL
355 #define  RXMAC_BC_FRM_CNT_COUNT         0x00000000001fffffULL
356
357 #define RXMAC_MC_FRM_CNT                0x00110UL
358 #define  RXMAC_MC_FRM_CNT_COUNT         0x00000000001fffffULL
359
360 #define RXMAC_FRAG_CNT                  0x00118UL
361 #define  RXMAC_FRAG_CNT_COUNT           0x00000000001fffffULL
362
363 #define RXMAC_HIST_CNT1                 0x00120UL
364 #define  RXMAC_HIST_CNT1_COUNT          0x00000000001fffffULL
365
366 #define RXMAC_HIST_CNT2                 0x00128UL
367 #define  RXMAC_HIST_CNT2_COUNT          0x00000000001fffffULL
368
369 #define RXMAC_HIST_CNT3                 0x00130UL
370 #define  RXMAC_HIST_CNT3_COUNT          0x00000000000fffffULL
371
372 #define RXMAC_HIST_CNT4                 0x00138UL
373 #define  RXMAC_HIST_CNT4_COUNT          0x000000000007ffffULL
374
375 #define RXMAC_HIST_CNT5                 0x00140UL
376 #define  RXMAC_HIST_CNT5_COUNT          0x000000000003ffffULL
377
378 #define RXMAC_HIST_CNT6                 0x00148UL
379 #define  RXMAC_HIST_CNT6_COUNT          0x000000000000ffffULL
380
381 #define RXMAC_MPSZER_CNT                0x00150UL
382 #define  RXMAC_MPSZER_CNT_COUNT         0x00000000000000ffULL
383
384 #define RXMAC_CRC_ER_CNT                0x00158UL
385 #define  RXMAC_CRC_ER_CNT_COUNT         0x00000000000000ffULL
386
387 #define RXMAC_CD_VIO_CNT                0x00160UL
388 #define  RXMAC_CD_VIO_CNT_COUNT         0x00000000000000ffULL
389
390 #define RXMAC_ALIGN_ERR_CNT             0x00168UL
391 #define  RXMAC_ALIGN_ERR_CNT_COUNT      0x00000000000000ffULL
392
393 #define TXMAC_FRM_CNT                   0x00170UL
394 #define  TXMAC_FRM_CNT_COUNT            0x00000000ffffffffULL
395
396 #define TXMAC_BYTE_CNT                  0x00178UL
397 #define  TXMAC_BYTE_CNT_COUNT           0x00000000ffffffffULL
398
399 #define LINK_FAULT_CNT                  0x00180UL
400 #define  LINK_FAULT_CNT_COUNT           0x00000000000000ffULL
401
402 #define RXMAC_HIST_CNT7                 0x00188UL
403 #define  RXMAC_HIST_CNT7_COUNT          0x0000000007ffffffULL
404
405 #define XMAC_SM_REG                     0x001a8UL
406 #define  XMAC_SM_REG_STATE              0x00000000ffffffffULL
407
408 #define XMAC_INTER1                     0x001b0UL
409 #define  XMAC_INTERN1_SIGNALS1          0x00000000ffffffffULL
410
411 #define XMAC_INTER2                     0x001b8UL
412 #define  XMAC_INTERN2_SIGNALS2          0x00000000ffffffffULL
413
414 /* BMAC registers, offset from np->mac_regs  */
415
416 #define BTXMAC_SW_RST                   0x00000UL
417 #define  BTXMAC_SW_RST_RESET            0x0000000000000001ULL
418
419 #define BRXMAC_SW_RST                   0x00008UL
420 #define  BRXMAC_SW_RST_RESET            0x0000000000000001ULL
421
422 #define BMAC_SEND_PAUSE                 0x00010UL
423 #define  BMAC_SEND_PAUSE_SEND           0x0000000000010000ULL
424 #define  BMAC_SEND_PAUSE_TIME           0x000000000000ffffULL
425
426 #define BTXMAC_STATUS                   0x00020UL
427 #define  BTXMAC_STATUS_XMIT             0x0000000000000001ULL
428 #define  BTXMAC_STATUS_UNDERRUN         0x0000000000000002ULL
429 #define  BTXMAC_STATUS_MAX_PKT_ERR      0x0000000000000004ULL
430 #define  BTXMAC_STATUS_BYTE_CNT_EXP     0x0000000000000400ULL
431 #define  BTXMAC_STATUS_FRAME_CNT_EXP    0x0000000000000800ULL
432
433 #define BRXMAC_STATUS                   0x00028UL
434 #define  BRXMAC_STATUS_RX_PKT           0x0000000000000001ULL
435 #define  BRXMAC_STATUS_OVERFLOW         0x0000000000000002ULL
436 #define  BRXMAC_STATUS_FRAME_CNT_EXP    0x0000000000000004ULL
437 #define  BRXMAC_STATUS_ALIGN_ERR_EXP    0x0000000000000008ULL
438 #define  BRXMAC_STATUS_CRC_ERR_EXP      0x0000000000000010ULL
439 #define  BRXMAC_STATUS_LEN_ERR_EXP      0x0000000000000020ULL
440
441 #define BMAC_CTRL_STATUS                0x00030UL
442 #define  BMAC_CTRL_STATUS_PAUSE_RECV    0x0000000000000001ULL
443 #define  BMAC_CTRL_STATUS_PAUSE         0x0000000000000002ULL
444 #define  BMAC_CTRL_STATUS_NOPAUSE       0x0000000000000004ULL
445 #define  BMAC_CTRL_STATUS_TIME          0x00000000ffff0000ULL
446 #define  BMAC_CTRL_STATUS_TIME_SHIFT    16
447
448 #define BTXMAC_STATUS_MASK              0x00040UL
449 #define BRXMAC_STATUS_MASK              0x00048UL
450 #define BMAC_CTRL_STATUS_MASK           0x00050UL
451
452 #define BTXMAC_CONFIG                   0x00060UL
453 #define  BTXMAC_CONFIG_ENABLE           0x0000000000000001ULL
454 #define  BTXMAC_CONFIG_FCS_DISABLE      0x0000000000000002ULL
455
456 #define BRXMAC_CONFIG                   0x00068UL
457 #define  BRXMAC_CONFIG_DISCARD_DIS      0x0000000000000080ULL
458 #define  BRXMAC_CONFIG_ADDR_FILT_EN     0x0000000000000040ULL
459 #define  BRXMAC_CONFIG_HASH_FILT_EN     0x0000000000000020ULL
460 #define  BRXMAC_CONFIG_PROMISC_GRP      0x0000000000000010ULL
461 #define  BRXMAC_CONFIG_PROMISC          0x0000000000000008ULL
462 #define  BRXMAC_CONFIG_STRIP_FCS        0x0000000000000004ULL
463 #define  BRXMAC_CONFIG_STRIP_PAD        0x0000000000000002ULL
464 #define  BRXMAC_CONFIG_ENABLE           0x0000000000000001ULL
465
466 #define BMAC_CTRL_CONFIG                0x00070UL
467 #define  BMAC_CTRL_CONFIG_TX_PAUSE_EN   0x0000000000000001ULL
468 #define  BMAC_CTRL_CONFIG_RX_PAUSE_EN   0x0000000000000002ULL
469 #define  BMAC_CTRL_CONFIG_PASS_CTRL     0x0000000000000004ULL
470
471 #define BMAC_XIF_CONFIG                 0x00078UL
472 #define  BMAC_XIF_CONFIG_TX_OUTPUT_EN   0x0000000000000001ULL
473 #define  BMAC_XIF_CONFIG_MII_LOOPBACK   0x0000000000000002ULL
474 #define  BMAC_XIF_CONFIG_GMII_MODE      0x0000000000000008ULL
475 #define  BMAC_XIF_CONFIG_LINK_LED       0x0000000000000020ULL
476 #define  BMAC_XIF_CONFIG_LED_POLARITY   0x0000000000000040ULL
477 #define  BMAC_XIF_CONFIG_25MHZ_CLOCK    0x0000000000000080ULL
478
479 #define BMAC_MIN_FRAME                  0x000a0UL
480 #define  BMAC_MIN_FRAME_VAL             0x00000000000003ffULL
481
482 #define BMAC_MAX_FRAME                  0x000a8UL
483 #define  BMAC_MAX_FRAME_MAX_BURST       0x000000003fff0000ULL
484 #define  BMAC_MAX_FRAME_MAX_BURST_SHIFT 16
485 #define  BMAC_MAX_FRAME_MAX_FRAME       0x0000000000003fffULL
486 #define  BMAC_MAX_FRAME_MAX_FRAME_SHIFT 0
487
488 #define BMAC_PREAMBLE_SIZE              0x000b0UL
489 #define  BMAC_PREAMBLE_SIZE_VAL         0x00000000000003ffULL
490
491 #define BMAC_CTRL_TYPE                  0x000c8UL
492
493 #define BMAC_ADDR0                      0x00100UL
494 #define  BMAC_ADDR0_ADDR0               0x000000000000ffffULL
495
496 #define BMAC_ADDR1                      0x00108UL
497 #define  BMAC_ADDR1_ADDR1               0x000000000000ffffULL
498
499 #define BMAC_ADDR2                      0x00110UL
500 #define  BMAC_ADDR2_ADDR2               0x000000000000ffffULL
501
502 #define BMAC_NUM_ALT_ADDR               6
503
504 #define BMAC_ALT_ADDR0(NUM)             (0x00118UL + (NUM)*0x18UL)
505 #define  BMAC_ALT_ADDR0_ADDR0           0x000000000000ffffULL
506
507 #define BMAC_ALT_ADDR1(NUM)             (0x00120UL + (NUM)*0x18UL)
508 #define  BMAC_ALT_ADDR1_ADDR1           0x000000000000ffffULL
509
510 #define BMAC_ALT_ADDR2(NUM)             (0x00128UL + (NUM)*0x18UL)
511 #define  BMAC_ALT_ADDR2_ADDR2           0x000000000000ffffULL
512
513 #define BMAC_FC_ADDR0                   0x00268UL
514 #define  BMAC_FC_ADDR0_ADDR0            0x000000000000ffffULL
515
516 #define BMAC_FC_ADDR1                   0x00270UL
517 #define  BMAC_FC_ADDR1_ADDR1            0x000000000000ffffULL
518
519 #define BMAC_FC_ADDR2                   0x00278UL
520 #define  BMAC_FC_ADDR2_ADDR2            0x000000000000ffffULL
521
522 #define BMAC_ADD_FILT0                  0x00298UL
523 #define  BMAC_ADD_FILT0_FILT0           0x000000000000ffffULL
524
525 #define BMAC_ADD_FILT1                  0x002a0UL
526 #define  BMAC_ADD_FILT1_FILT1           0x000000000000ffffULL
527
528 #define BMAC_ADD_FILT2                  0x002a8UL
529 #define  BMAC_ADD_FILT2_FILT2           0x000000000000ffffULL
530
531 #define BMAC_ADD_FILT12_MASK            0x002b0UL
532 #define  BMAC_ADD_FILT12_MASK_VAL       0x00000000000000ffULL
533
534 #define BMAC_ADD_FILT00_MASK            0x002b8UL
535 #define  BMAC_ADD_FILT00_MASK_VAL       0x000000000000ffffULL
536
537 #define BMAC_HASH_TBL(NUM)              (0x002c0UL + (NUM) * 0x8UL)
538 #define BMAC_HASH_TBL_VAL               0x000000000000ffffULL
539
540 #define BRXMAC_FRAME_CNT                0x00370
541 #define  BRXMAC_FRAME_CNT_COUNT         0x000000000000ffffULL
542
543 #define BRXMAC_MAX_LEN_ERR_CNT          0x00378
544
545 #define BRXMAC_ALIGN_ERR_CNT            0x00380
546 #define  BRXMAC_ALIGN_ERR_CNT_COUNT     0x000000000000ffffULL
547
548 #define BRXMAC_CRC_ERR_CNT              0x00388
549 #define  BRXMAC_ALIGN_ERR_CNT_COUNT     0x000000000000ffffULL
550
551 #define BRXMAC_CODE_VIOL_ERR_CNT        0x00390
552 #define  BRXMAC_CODE_VIOL_ERR_CNT_COUNT 0x000000000000ffffULL
553
554 #define BMAC_STATE_MACHINE              0x003a0
555
556 #define BMAC_ADDR_CMPEN                 0x003f8UL
557 #define  BMAC_ADDR_CMPEN_EN15           0x0000000000008000ULL
558 #define  BMAC_ADDR_CMPEN_EN14           0x0000000000004000ULL
559 #define  BMAC_ADDR_CMPEN_EN13           0x0000000000002000ULL
560 #define  BMAC_ADDR_CMPEN_EN12           0x0000000000001000ULL
561 #define  BMAC_ADDR_CMPEN_EN11           0x0000000000000800ULL
562 #define  BMAC_ADDR_CMPEN_EN10           0x0000000000000400ULL
563 #define  BMAC_ADDR_CMPEN_EN9            0x0000000000000200ULL
564 #define  BMAC_ADDR_CMPEN_EN8            0x0000000000000100ULL
565 #define  BMAC_ADDR_CMPEN_EN7            0x0000000000000080ULL
566 #define  BMAC_ADDR_CMPEN_EN6            0x0000000000000040ULL
567 #define  BMAC_ADDR_CMPEN_EN5            0x0000000000000020ULL
568 #define  BMAC_ADDR_CMPEN_EN4            0x0000000000000010ULL
569 #define  BMAC_ADDR_CMPEN_EN3            0x0000000000000008ULL
570 #define  BMAC_ADDR_CMPEN_EN2            0x0000000000000004ULL
571 #define  BMAC_ADDR_CMPEN_EN1            0x0000000000000002ULL
572 #define  BMAC_ADDR_CMPEN_EN0            0x0000000000000001ULL
573
574 #define BMAC_NUM_HOST_INFO              9
575
576 #define BMAC_HOST_INFO(NUM)             (0x00400UL + (NUM) * 0x8UL)
577
578 #define BTXMAC_BYTE_CNT                 0x00448UL
579 #define  BTXMAC_BYTE_CNT_COUNT          0x00000000ffffffffULL
580
581 #define BTXMAC_FRM_CNT                  0x00450UL
582 #define  BTXMAC_FRM_CNT_COUNT           0x00000000ffffffffULL
583
584 #define BRXMAC_BYTE_CNT                 0x00458UL
585 #define  BRXMAC_BYTE_CNT_COUNT          0x00000000ffffffffULL
586
587 #define HOST_INFO_MPR                   0x0000000000000100ULL
588 #define HOST_INFO_MACRDCTBLN            0x0000000000000007ULL
589
590 /* XPCS registers, offset from np->regs + np->xpcs_off  */
591
592 #define XPCS_CONTROL1                   (FZC_MAC + 0x00000UL)
593 #define  XPCS_CONTROL1_RESET            0x0000000000008000ULL
594 #define  XPCS_CONTROL1_LOOPBACK         0x0000000000004000ULL
595 #define  XPCS_CONTROL1_SPEED_SELECT3    0x0000000000002000ULL
596 #define  XPCS_CONTROL1_CSR_LOW_PWR      0x0000000000000800ULL
597 #define  XPCS_CONTROL1_CSR_SPEED1       0x0000000000000040ULL
598 #define  XPCS_CONTROL1_CSR_SPEED0       0x000000000000003cULL
599
600 #define XPCS_STATUS1                    (FZC_MAC + 0x00008UL)
601 #define  XPCS_STATUS1_CSR_FAULT         0x0000000000000080ULL
602 #define  XPCS_STATUS1_CSR_RXLNK_STAT    0x0000000000000004ULL
603 #define  XPCS_STATUS1_CSR_LPWR_ABLE     0x0000000000000002ULL
604
605 #define XPCS_DEVICE_IDENTIFIER          (FZC_MAC + 0x00010UL)
606 #define  XPCS_DEVICE_IDENTIFIER_VAL     0x00000000ffffffffULL
607
608 #define XPCS_SPEED_ABILITY              (FZC_MAC + 0x00018UL)
609 #define  XPCS_SPEED_ABILITY_10GIG       0x0000000000000001ULL
610
611 #define XPCS_DEV_IN_PKG                 (FZC_MAC + 0x00020UL)
612 #define  XPCS_DEV_IN_PKG_CSR_VEND2      0x0000000080000000ULL
613 #define  XPCS_DEV_IN_PKG_CSR_VEND1      0x0000000040000000ULL
614 #define  XPCS_DEV_IN_PKG_DTE_XS         0x0000000000000020ULL
615 #define  XPCS_DEV_IN_PKG_PHY_XS         0x0000000000000010ULL
616 #define  XPCS_DEV_IN_PKG_PCS            0x0000000000000008ULL
617 #define  XPCS_DEV_IN_PKG_WIS            0x0000000000000004ULL
618 #define  XPCS_DEV_IN_PKG_PMD_PMA        0x0000000000000002ULL
619 #define  XPCS_DEV_IN_PKG_CLS22          0x0000000000000001ULL
620
621 #define XPCS_CONTROL2                   (FZC_MAC + 0x00028UL)
622 #define  XPCS_CONTROL2_CSR_PSC_SEL      0x0000000000000003ULL
623
624 #define XPCS_STATUS2                    (FZC_MAC + 0x00030UL)
625 #define  XPCS_STATUS2_CSR_DEV_PRES      0x000000000000c000ULL
626 #define  XPCS_STATUS2_CSR_TX_FAULT      0x0000000000000800ULL
627 #define  XPCS_STATUS2_CSR_RCV_FAULT     0x0000000000000400ULL
628 #define  XPCS_STATUS2_TEN_GBASE_W       0x0000000000000004ULL
629 #define  XPCS_STATUS2_TEN_GBASE_X       0x0000000000000002ULL
630 #define  XPCS_STATUS2_TEN_GBASE_R       0x0000000000000001ULL
631
632 #define XPCS_PKG_ID                     (FZC_MAC + 0x00038UL)
633 #define  XPCS_PKG_ID_VAL                0x00000000ffffffffULL
634
635 #define XPCS_STATUS(IDX)                (FZC_MAC + 0x00040UL)
636 #define  XPCS_STATUS_CSR_LANE_ALIGN     0x0000000000001000ULL
637 #define  XPCS_STATUS_CSR_PATTEST_CAP    0x0000000000000800ULL
638 #define  XPCS_STATUS_CSR_LANE3_SYNC     0x0000000000000008ULL
639 #define  XPCS_STATUS_CSR_LANE2_SYNC     0x0000000000000004ULL
640 #define  XPCS_STATUS_CSR_LANE1_SYNC     0x0000000000000002ULL
641 #define  XPCS_STATUS_CSR_LANE0_SYNC     0x0000000000000001ULL
642
643 #define XPCS_TEST_CONTROL               (FZC_MAC + 0x00048UL)
644 #define  XPCS_TEST_CONTROL_TXTST_EN     0x0000000000000004ULL
645 #define  XPCS_TEST_CONTROL_TPAT_SEL     0x0000000000000003ULL
646
647 #define XPCS_CFG_VENDOR1                (FZC_MAC + 0x00050UL)
648 #define  XPCS_CFG_VENDOR1_DBG_IOTST     0x0000000000000080ULL
649 #define  XPCS_CFG_VENDOR1_DBG_SEL       0x0000000000000078ULL
650 #define  XPCS_CFG_VENDOR1_BYPASS_DET    0x0000000000000004ULL
651 #define  XPCS_CFG_VENDOR1_TXBUF_EN      0x0000000000000002ULL
652 #define  XPCS_CFG_VENDOR1_XPCS_EN       0x0000000000000001ULL
653
654 #define XPCS_DIAG_VENDOR2               (FZC_MAC + 0x00058UL)
655 #define  XPCS_DIAG_VENDOR2_SSM_LANE3    0x0000000001e00000ULL
656 #define  XPCS_DIAG_VENDOR2_SSM_LANE2    0x00000000001e0000ULL
657 #define  XPCS_DIAG_VENDOR2_SSM_LANE1    0x000000000001e000ULL
658 #define  XPCS_DIAG_VENDOR2_SSM_LANE0    0x0000000000001e00ULL
659 #define  XPCS_DIAG_VENDOR2_EBUF_SM      0x00000000000001feULL
660 #define  XPCS_DIAG_VENDOR2_RCV_SM       0x0000000000000001ULL
661
662 #define XPCS_MASK1                      (FZC_MAC + 0x00060UL)
663 #define  XPCS_MASK1_FAULT_MASK          0x0000000000000080ULL
664 #define  XPCS_MASK1_RXALIGN_STAT_MSK    0x0000000000000004ULL
665
666 #define XPCS_PKT_COUNT                  (FZC_MAC + 0x00068UL)
667 #define  XPCS_PKT_COUNT_TX              0x00000000ffff0000ULL
668 #define  XPCS_PKT_COUNT_RX              0x000000000000ffffULL
669
670 #define XPCS_TX_SM                      (FZC_MAC + 0x00070UL)
671 #define  XPCS_TX_SM_VAL                 0x000000000000000fULL
672
673 #define XPCS_DESKEW_ERR_CNT             (FZC_MAC + 0x00078UL)
674 #define  XPCS_DESKEW_ERR_CNT_VAL        0x00000000000000ffULL
675
676 #define XPCS_SYMERR_CNT01               (FZC_MAC + 0x00080UL)
677 #define  XPCS_SYMERR_CNT01_LANE1        0x00000000ffff0000ULL
678 #define  XPCS_SYMERR_CNT01_LANE0        0x000000000000ffffULL
679
680 #define XPCS_SYMERR_CNT23               (FZC_MAC + 0x00088UL)
681 #define  XPCS_SYMERR_CNT23_LANE3        0x00000000ffff0000ULL
682 #define  XPCS_SYMERR_CNT23_LANE2        0x000000000000ffffULL
683
684 #define XPCS_TRAINING_VECTOR            (FZC_MAC + 0x00090UL)
685 #define  XPCS_TRAINING_VECTOR_VAL       0x00000000ffffffffULL
686
687 /* PCS registers, offset from np->regs + np->pcs_off  */
688
689 #define PCS_MII_CTL                     (FZC_MAC + 0x00000UL)
690 #define  PCS_MII_CTL_RST                0x0000000000008000ULL
691 #define  PCS_MII_CTL_10_100_SPEED       0x0000000000002000ULL
692 #define  PCS_MII_AUTONEG_EN             0x0000000000001000ULL
693 #define  PCS_MII_PWR_DOWN               0x0000000000000800ULL
694 #define  PCS_MII_ISOLATE                0x0000000000000400ULL
695 #define  PCS_MII_AUTONEG_RESTART        0x0000000000000200ULL
696 #define  PCS_MII_DUPLEX                 0x0000000000000100ULL
697 #define  PCS_MII_COLL_TEST              0x0000000000000080ULL
698 #define  PCS_MII_1000MB_SPEED           0x0000000000000040ULL
699
700 #define PCS_MII_STAT                    (FZC_MAC + 0x00008UL)
701 #define  PCS_MII_STAT_EXT_STATUS        0x0000000000000100ULL
702 #define  PCS_MII_STAT_AUTONEG_DONE      0x0000000000000020ULL
703 #define  PCS_MII_STAT_REMOTE_FAULT      0x0000000000000010ULL
704 #define  PCS_MII_STAT_AUTONEG_ABLE      0x0000000000000008ULL
705 #define  PCS_MII_STAT_LINK_STATUS       0x0000000000000004ULL
706 #define  PCS_MII_STAT_JABBER_DET        0x0000000000000002ULL
707 #define  PCS_MII_STAT_EXT_CAP           0x0000000000000001ULL
708
709 #define PCS_MII_ADV                     (FZC_MAC + 0x00010UL)
710 #define  PCS_MII_ADV_NEXT_PAGE          0x0000000000008000ULL
711 #define  PCS_MII_ADV_ACK                0x0000000000004000ULL
712 #define  PCS_MII_ADV_REMOTE_FAULT       0x0000000000003000ULL
713 #define  PCS_MII_ADV_ASM_DIR            0x0000000000000100ULL
714 #define  PCS_MII_ADV_PAUSE              0x0000000000000080ULL
715 #define  PCS_MII_ADV_HALF_DUPLEX        0x0000000000000040ULL
716 #define  PCS_MII_ADV_FULL_DUPLEX        0x0000000000000020ULL
717
718 #define PCS_MII_PARTNER                 (FZC_MAC + 0x00018UL)
719 #define  PCS_MII_PARTNER_NEXT_PAGE      0x0000000000008000ULL
720 #define  PCS_MII_PARTNER_ACK            0x0000000000004000ULL
721 #define  PCS_MII_PARTNER_REMOTE_FAULT   0x0000000000002000ULL
722 #define  PCS_MII_PARTNER_PAUSE          0x0000000000000180ULL
723 #define  PCS_MII_PARTNER_HALF_DUPLEX    0x0000000000000040ULL
724 #define  PCS_MII_PARTNER_FULL_DUPLEX    0x0000000000000020ULL
725
726 #define PCS_CONF                        (FZC_MAC + 0x00020UL)
727 #define  PCS_CONF_MASK                  0x0000000000000040ULL
728 #define  PCS_CONF_10MS_TMR_OVERRIDE     0x0000000000000020ULL
729 #define  PCS_CONF_JITTER_STUDY          0x0000000000000018ULL
730 #define  PCS_CONF_SIGDET_ACTIVE_LOW     0x0000000000000004ULL
731 #define  PCS_CONF_SIGDET_OVERRIDE       0x0000000000000002ULL
732 #define  PCS_CONF_ENABLE                0x0000000000000001ULL
733
734 #define PCS_STATE                       (FZC_MAC + 0x00028UL)
735 #define  PCS_STATE_D_PARTNER_FAIL       0x0000000020000000ULL
736 #define  PCS_STATE_D_WAIT_C_CODES_ACK   0x0000000010000000ULL
737 #define  PCS_STATE_D_SYNC_LOSS          0x0000000008000000ULL
738 #define  PCS_STATE_D_NO_GOOD_C_CODES    0x0000000004000000ULL
739 #define  PCS_STATE_D_SERDES             0x0000000002000000ULL
740 #define  PCS_STATE_D_BREAKLINK_C_CODES  0x0000000001000000ULL
741 #define  PCS_STATE_L_SIGDET             0x0000000000400000ULL
742 #define  PCS_STATE_L_SYNC_LOSS          0x0000000000200000ULL
743 #define  PCS_STATE_L_C_CODES            0x0000000000100000ULL
744 #define  PCS_STATE_LINK_CFG_STATE       0x000000000001e000ULL
745 #define  PCS_STATE_SEQ_DET_STATE        0x0000000000001800ULL
746 #define  PCS_STATE_WORD_SYNC_STATE      0x0000000000000700ULL
747 #define  PCS_STATE_NO_IDLE              0x000000000000000fULL
748
749 #define PCS_INTERRUPT                   (FZC_MAC + 0x00030UL)
750 #define  PCS_INTERRUPT_LSTATUS          0x0000000000000004ULL
751
752 #define PCS_DPATH_MODE                  (FZC_MAC + 0x000a0UL)
753 #define  PCS_DPATH_MODE_PCS             0x0000000000000000ULL
754 #define  PCS_DPATH_MODE_MII             0x0000000000000002ULL
755 #define  PCS_DPATH_MODE_LINKUP_F_ENAB   0x0000000000000001ULL
756
757 #define PCS_PKT_CNT                     (FZC_MAC + 0x000c0UL)
758 #define  PCS_PKT_CNT_RX                 0x0000000007ff0000ULL
759 #define  PCS_PKT_CNT_TX                 0x00000000000007ffULL
760
761 #define MIF_BB_MDC                      (FZC_MAC + 0x16000UL)
762 #define  MIF_BB_MDC_CLK                 0x0000000000000001ULL
763
764 #define MIF_BB_MDO                      (FZC_MAC + 0x16008UL)
765 #define  MIF_BB_MDO_DAT                 0x0000000000000001ULL
766
767 #define MIF_BB_MDO_EN                   (FZC_MAC + 0x16010UL)
768 #define  MIF_BB_MDO_EN_VAL              0x0000000000000001ULL
769
770 #define MIF_FRAME_OUTPUT                (FZC_MAC + 0x16018UL)
771 #define  MIF_FRAME_OUTPUT_ST            0x00000000c0000000ULL
772 #define  MIF_FRAME_OUTPUT_ST_SHIFT      30
773 #define  MIF_FRAME_OUTPUT_OP_ADDR       0x0000000000000000ULL
774 #define  MIF_FRAME_OUTPUT_OP_WRITE      0x0000000010000000ULL
775 #define  MIF_FRAME_OUTPUT_OP_READ_INC   0x0000000020000000ULL
776 #define  MIF_FRAME_OUTPUT_OP_READ       0x0000000030000000ULL
777 #define  MIF_FRAME_OUTPUT_OP_SHIFT      28
778 #define  MIF_FRAME_OUTPUT_PORT          0x000000000f800000ULL
779 #define  MIF_FRAME_OUTPUT_PORT_SHIFT    23
780 #define  MIF_FRAME_OUTPUT_REG           0x00000000007c0000ULL
781 #define  MIF_FRAME_OUTPUT_REG_SHIFT     18
782 #define  MIF_FRAME_OUTPUT_TA            0x0000000000030000ULL
783 #define  MIF_FRAME_OUTPUT_TA_SHIFT      16
784 #define  MIF_FRAME_OUTPUT_DATA          0x000000000000ffffULL
785 #define  MIF_FRAME_OUTPUT_DATA_SHIFT    0
786
787 #define MDIO_ADDR_OP(port, dev, reg) \
788         ((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
789          MIF_FRAME_OUTPUT_OP_ADDR | \
790          (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
791          (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \
792          (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \
793          (reg << MIF_FRAME_OUTPUT_DATA_SHIFT))
794
795 #define MDIO_READ_OP(port, dev) \
796         ((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
797          MIF_FRAME_OUTPUT_OP_READ | \
798          (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
799          (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \
800          (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT))
801
802 #define MDIO_WRITE_OP(port, dev, data) \
803         ((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
804          MIF_FRAME_OUTPUT_OP_WRITE | \
805          (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
806          (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \
807          (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \
808          (data << MIF_FRAME_OUTPUT_DATA_SHIFT))
809
810 #define MII_READ_OP(port, reg) \
811         ((1 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
812          (2 << MIF_FRAME_OUTPUT_OP_SHIFT) | \
813          (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
814          (reg << MIF_FRAME_OUTPUT_REG_SHIFT) | \
815          (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT))
816
817 #define MII_WRITE_OP(port, reg, data) \
818         ((1 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
819          (1 << MIF_FRAME_OUTPUT_OP_SHIFT) | \
820          (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
821          (reg << MIF_FRAME_OUTPUT_REG_SHIFT) | \
822          (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \
823          (data << MIF_FRAME_OUTPUT_DATA_SHIFT))
824
825 #define MIF_CONFIG                      (FZC_MAC + 0x16020UL)
826 #define  MIF_CONFIG_ATCA_GE             0x0000000000010000ULL
827 #define  MIF_CONFIG_INDIRECT_MODE       0x0000000000008000ULL
828 #define  MIF_CONFIG_POLL_PRT_PHYADDR    0x0000000000003c00ULL
829 #define  MIF_CONFIG_POLL_DEV_REG_ADDR   0x00000000000003e0ULL
830 #define  MIF_CONFIG_BB_MODE             0x0000000000000010ULL
831 #define  MIF_CONFIG_POLL_EN             0x0000000000000008ULL
832 #define  MIF_CONFIG_BB_SER_SEL          0x0000000000000006ULL
833 #define  MIF_CONFIG_MANUAL_MODE         0x0000000000000001ULL
834
835 #define MIF_POLL_STATUS                 (FZC_MAC + 0x16028UL)
836 #define  MIF_POLL_STATUS_DATA           0x00000000ffff0000ULL
837 #define  MIF_POLL_STATUS_STAT           0x000000000000ffffULL
838
839 #define MIF_POLL_MASK                   (FZC_MAC + 0x16030UL)
840 #define  MIF_POLL_MASK_VAL              0x000000000000ffffULL
841
842 #define MIF_SM                          (FZC_MAC + 0x16038UL)
843 #define  MIF_SM_PORT_ADDR               0x00000000001f0000ULL
844 #define  MIF_SM_MDI_1                   0x0000000000004000ULL
845 #define  MIF_SM_MDI_0                   0x0000000000002400ULL
846 #define  MIF_SM_MDCLK                   0x0000000000001000ULL
847 #define  MIF_SM_MDO_EN                  0x0000000000000800ULL
848 #define  MIF_SM_MDO                     0x0000000000000400ULL
849 #define  MIF_SM_MDI                     0x0000000000000200ULL
850 #define  MIF_SM_CTL                     0x00000000000001c0ULL
851 #define  MIF_SM_EX                      0x000000000000003fULL
852
853 #define MIF_STATUS                      (FZC_MAC + 0x16040UL)
854 #define  MIF_STATUS_MDINT1              0x0000000000000020ULL
855 #define  MIF_STATUS_MDINT0              0x0000000000000010ULL
856
857 #define MIF_MASK                        (FZC_MAC + 0x16048UL)
858 #define  MIF_MASK_MDINT1                0x0000000000000020ULL
859 #define  MIF_MASK_MDINT0                0x0000000000000010ULL
860 #define  MIF_MASK_PEU_ERR               0x0000000000000008ULL
861 #define  MIF_MASK_YC                    0x0000000000000004ULL
862 #define  MIF_MASK_XGE_ERR0              0x0000000000000002ULL
863 #define  MIF_MASK_MIF_INIT_DONE         0x0000000000000001ULL
864
865 #define ENET_SERDES_RESET               (FZC_MAC + 0x14000UL)
866 #define  ENET_SERDES_RESET_1            0x0000000000000002ULL
867 #define  ENET_SERDES_RESET_0            0x0000000000000001ULL
868
869 #define ENET_SERDES_CFG                 (FZC_MAC + 0x14008UL)
870 #define  ENET_SERDES_BE_LOOPBACK        0x0000000000000002ULL
871 #define  ENET_SERDES_CFG_FORCE_RDY      0x0000000000000001ULL
872
873 #define ENET_SERDES_0_PLL_CFG           (FZC_MAC + 0x14010UL)
874 #define  ENET_SERDES_PLL_FBDIV0         0x0000000000000001ULL
875 #define  ENET_SERDES_PLL_FBDIV1         0x0000000000000002ULL
876 #define  ENET_SERDES_PLL_FBDIV2         0x0000000000000004ULL
877 #define  ENET_SERDES_PLL_HRATE0         0x0000000000000008ULL
878 #define  ENET_SERDES_PLL_HRATE1         0x0000000000000010ULL
879 #define  ENET_SERDES_PLL_HRATE2         0x0000000000000020ULL
880 #define  ENET_SERDES_PLL_HRATE3         0x0000000000000040ULL
881
882 #define ENET_SERDES_0_CTRL_CFG          (FZC_MAC + 0x14018UL)
883 #define  ENET_SERDES_CTRL_SDET_0        0x0000000000000001ULL
884 #define  ENET_SERDES_CTRL_SDET_1        0x0000000000000002ULL
885 #define  ENET_SERDES_CTRL_SDET_2        0x0000000000000004ULL
886 #define  ENET_SERDES_CTRL_SDET_3        0x0000000000000008ULL
887 #define  ENET_SERDES_CTRL_EMPH_0        0x0000000000000070ULL
888 #define  ENET_SERDES_CTRL_EMPH_0_SHIFT  4
889 #define  ENET_SERDES_CTRL_EMPH_1        0x0000000000000380ULL
890 #define  ENET_SERDES_CTRL_EMPH_1_SHIFT  7
891 #define  ENET_SERDES_CTRL_EMPH_2        0x0000000000001c00ULL
892 #define  ENET_SERDES_CTRL_EMPH_2_SHIFT  10
893 #define  ENET_SERDES_CTRL_EMPH_3        0x000000000000e000ULL
894 #define  ENET_SERDES_CTRL_EMPH_3_SHIFT  13
895 #define  ENET_SERDES_CTRL_LADJ_0        0x0000000000070000ULL
896 #define  ENET_SERDES_CTRL_LADJ_0_SHIFT  16
897 #define  ENET_SERDES_CTRL_LADJ_1        0x0000000000380000ULL
898 #define  ENET_SERDES_CTRL_LADJ_1_SHIFT  19
899 #define  ENET_SERDES_CTRL_LADJ_2        0x0000000001c00000ULL
900 #define  ENET_SERDES_CTRL_LADJ_2_SHIFT  22
901 #define  ENET_SERDES_CTRL_LADJ_3        0x000000000e000000ULL
902 #define  ENET_SERDES_CTRL_LADJ_3_SHIFT  25
903 #define  ENET_SERDES_CTRL_RXITERM_0     0x0000000010000000ULL
904 #define  ENET_SERDES_CTRL_RXITERM_1     0x0000000020000000ULL
905 #define  ENET_SERDES_CTRL_RXITERM_2     0x0000000040000000ULL
906 #define  ENET_SERDES_CTRL_RXITERM_3     0x0000000080000000ULL
907
908 #define ENET_SERDES_0_TEST_CFG          (FZC_MAC + 0x14020UL)
909 #define  ENET_SERDES_TEST_MD_0          0x0000000000000003ULL
910 #define  ENET_SERDES_TEST_MD_0_SHIFT    0
911 #define  ENET_SERDES_TEST_MD_1          0x000000000000000cULL
912 #define  ENET_SERDES_TEST_MD_1_SHIFT    2
913 #define  ENET_SERDES_TEST_MD_2          0x0000000000000030ULL
914 #define  ENET_SERDES_TEST_MD_2_SHIFT    4
915 #define  ENET_SERDES_TEST_MD_3          0x00000000000000c0ULL
916 #define  ENET_SERDES_TEST_MD_3_SHIFT    6
917
918 #define ENET_TEST_MD_NO_LOOPBACK        0x0
919 #define ENET_TEST_MD_EWRAP              0x1
920 #define ENET_TEST_MD_PAD_LOOPBACK       0x2
921 #define ENET_TEST_MD_REV_LOOPBACK       0x3
922
923 #define ENET_SERDES_1_PLL_CFG           (FZC_MAC + 0x14028UL)
924 #define ENET_SERDES_1_CTRL_CFG          (FZC_MAC + 0x14030UL)
925 #define ENET_SERDES_1_TEST_CFG          (FZC_MAC + 0x14038UL)
926
927 #define ENET_RGMII_CFG_REG              (FZC_MAC + 0x14040UL)
928
929 #define ESR_INT_SIGNALS                 (FZC_MAC + 0x14800UL)
930 #define  ESR_INT_SIGNALS_ALL            0x00000000ffffffffULL
931 #define  ESR_INT_SIGNALS_P0_BITS        0x0000000033e0000fULL
932 #define  ESR_INT_SIGNALS_P1_BITS        0x000000000c1f00f0ULL
933 #define  ESR_INT_SRDY0_P0               0x0000000020000000ULL
934 #define  ESR_INT_DET0_P0                0x0000000010000000ULL
935 #define  ESR_INT_SRDY0_P1               0x0000000008000000ULL
936 #define  ESR_INT_DET0_P1                0x0000000004000000ULL
937 #define  ESR_INT_XSRDY_P0               0x0000000002000000ULL
938 #define  ESR_INT_XDP_P0_CH3             0x0000000001000000ULL
939 #define  ESR_INT_XDP_P0_CH2             0x0000000000800000ULL
940 #define  ESR_INT_XDP_P0_CH1             0x0000000000400000ULL
941 #define  ESR_INT_XDP_P0_CH0             0x0000000000200000ULL
942 #define  ESR_INT_XSRDY_P1               0x0000000000100000ULL
943 #define  ESR_INT_XDP_P1_CH3             0x0000000000080000ULL
944 #define  ESR_INT_XDP_P1_CH2             0x0000000000040000ULL
945 #define  ESR_INT_XDP_P1_CH1             0x0000000000020000ULL
946 #define  ESR_INT_XDP_P1_CH0             0x0000000000010000ULL
947 #define  ESR_INT_SLOSS_P1_CH3           0x0000000000000080ULL
948 #define  ESR_INT_SLOSS_P1_CH2           0x0000000000000040ULL
949 #define  ESR_INT_SLOSS_P1_CH1           0x0000000000000020ULL
950 #define  ESR_INT_SLOSS_P1_CH0           0x0000000000000010ULL
951 #define  ESR_INT_SLOSS_P0_CH3           0x0000000000000008ULL
952 #define  ESR_INT_SLOSS_P0_CH2           0x0000000000000004ULL
953 #define  ESR_INT_SLOSS_P0_CH1           0x0000000000000002ULL
954 #define  ESR_INT_SLOSS_P0_CH0           0x0000000000000001ULL
955
956 #define ESR_DEBUG_SEL                   (FZC_MAC + 0x14808UL)
957 #define  ESR_DEBUG_SEL_VAL              0x000000000000003fULL
958
959 /* SerDes registers behind MIF */
960 #define NIU_ESR_DEV_ADDR                0x1e
961 #define ESR_BASE                        0x0000
962
963 #define ESR_RXTX_COMM_CTRL_L            (ESR_BASE + 0x0000)
964 #define ESR_RXTX_COMM_CTRL_H            (ESR_BASE + 0x0001)
965
966 #define ESR_RXTX_RESET_CTRL_L           (ESR_BASE + 0x0002)
967 #define ESR_RXTX_RESET_CTRL_H           (ESR_BASE + 0x0003)
968
969 #define ESR_RX_POWER_CTRL_L             (ESR_BASE + 0x0004)
970 #define ESR_RX_POWER_CTRL_H             (ESR_BASE + 0x0005)
971
972 #define ESR_TX_POWER_CTRL_L             (ESR_BASE + 0x0006)
973 #define ESR_TX_POWER_CTRL_H             (ESR_BASE + 0x0007)
974
975 #define ESR_MISC_POWER_CTRL_L           (ESR_BASE + 0x0008)
976 #define ESR_MISC_POWER_CTRL_H           (ESR_BASE + 0x0009)
977
978 #define ESR_RXTX_CTRL_L(CHAN)           (ESR_BASE + 0x0080 + (CHAN) * 0x10)
979 #define ESR_RXTX_CTRL_H(CHAN)           (ESR_BASE + 0x0081 + (CHAN) * 0x10)
980 #define  ESR_RXTX_CTRL_BIASCNTL         0x80000000
981 #define  ESR_RXTX_CTRL_RESV1            0x7c000000
982 #define  ESR_RXTX_CTRL_TDENFIFO         0x02000000
983 #define  ESR_RXTX_CTRL_TDWS20           0x01000000
984 #define  ESR_RXTX_CTRL_VMUXLO           0x00c00000
985 #define  ESR_RXTX_CTRL_VMUXLO_SHIFT     22
986 #define  ESR_RXTX_CTRL_VPULSELO         0x00300000
987 #define  ESR_RXTX_CTRL_VPULSELO_SHIFT   20
988 #define  ESR_RXTX_CTRL_RESV2            0x000f0000
989 #define  ESR_RXTX_CTRL_RESV3            0x0000c000
990 #define  ESR_RXTX_CTRL_RXPRESWIN        0x00003000
991 #define  ESR_RXTX_CTRL_RXPRESWIN_SHIFT  12
992 #define  ESR_RXTX_CTRL_RESV4            0x00000800
993 #define  ESR_RXTX_CTRL_RISEFALL         0x00000700
994 #define  ESR_RXTX_CTRL_RISEFALL_SHIFT   8
995 #define  ESR_RXTX_CTRL_RESV5            0x000000fe
996 #define  ESR_RXTX_CTRL_ENSTRETCH        0x00000001
997
998 #define ESR_RXTX_TUNING_L(CHAN)         (ESR_BASE + 0x0082 + (CHAN) * 0x10)
999 #define ESR_RXTX_TUNING_H(CHAN)         (ESR_BASE + 0x0083 + (CHAN) * 0x10)
1000
1001 #define ESR_RX_SYNCCHAR_L(CHAN)         (ESR_BASE + 0x0084 + (CHAN) * 0x10)
1002 #define ESR_RX_SYNCCHAR_H(CHAN)         (ESR_BASE + 0x0085 + (CHAN) * 0x10)
1003
1004 #define ESR_RXTX_TEST_L(CHAN)           (ESR_BASE + 0x0086 + (CHAN) * 0x10)
1005 #define ESR_RXTX_TEST_H(CHAN)           (ESR_BASE + 0x0087 + (CHAN) * 0x10)
1006
1007 #define ESR_GLUE_CTRL0_L(CHAN)          (ESR_BASE + 0x0088 + (CHAN) * 0x10)
1008 #define ESR_GLUE_CTRL0_H(CHAN)          (ESR_BASE + 0x0089 + (CHAN) * 0x10)
1009 #define  ESR_GLUE_CTRL0_RESV1           0xf8000000
1010 #define  ESR_GLUE_CTRL0_BLTIME          0x07000000
1011 #define  ESR_GLUE_CTRL0_BLTIME_SHIFT    24
1012 #define  ESR_GLUE_CTRL0_RESV2           0x00ff0000
1013 #define  ESR_GLUE_CTRL0_RXLOS_TEST      0x00008000
1014 #define  ESR_GLUE_CTRL0_RESV3           0x00004000
1015 #define  ESR_GLUE_CTRL0_RXLOSENAB       0x00002000
1016 #define  ESR_GLUE_CTRL0_FASTRESYNC      0x00001000
1017 #define  ESR_GLUE_CTRL0_SRATE           0x00000f00
1018 #define  ESR_GLUE_CTRL0_SRATE_SHIFT     8
1019 #define  ESR_GLUE_CTRL0_THCNT           0x000000ff
1020 #define  ESR_GLUE_CTRL0_THCNT_SHIFT     0
1021
1022 #define BLTIME_64_CYCLES                0
1023 #define BLTIME_128_CYCLES               1
1024 #define BLTIME_256_CYCLES               2
1025 #define BLTIME_300_CYCLES               3
1026 #define BLTIME_384_CYCLES               4
1027 #define BLTIME_512_CYCLES               5
1028 #define BLTIME_1024_CYCLES              6
1029 #define BLTIME_2048_CYCLES              7
1030
1031 #define ESR_GLUE_CTRL1_L(CHAN)          (ESR_BASE + 0x008a + (CHAN) * 0x10)
1032 #define ESR_GLUE_CTRL1_H(CHAN)          (ESR_BASE + 0x008b + (CHAN) * 0x10)
1033 #define ESR_RXTX_TUNING1_L(CHAN)        (ESR_BASE + 0x00c2 + (CHAN) * 0x10)
1034 #define ESR_RXTX_TUNING1_H(CHAN)        (ESR_BASE + 0x00c2 + (CHAN) * 0x10)
1035 #define ESR_RXTX_TUNING2_L(CHAN)        (ESR_BASE + 0x0102 + (CHAN) * 0x10)
1036 #define ESR_RXTX_TUNING2_H(CHAN)        (ESR_BASE + 0x0102 + (CHAN) * 0x10)
1037 #define ESR_RXTX_TUNING3_L(CHAN)        (ESR_BASE + 0x0142 + (CHAN) * 0x10)
1038 #define ESR_RXTX_TUNING3_H(CHAN)        (ESR_BASE + 0x0142 + (CHAN) * 0x10)
1039
1040 #define NIU_ESR2_DEV_ADDR               0x1e
1041 #define ESR2_BASE                       0x8000
1042
1043 #define ESR2_TI_PLL_CFG_L               (ESR2_BASE + 0x000)
1044 #define ESR2_TI_PLL_CFG_H               (ESR2_BASE + 0x001)
1045 #define  PLL_CFG_STD                    0x00000c00
1046 #define  PLL_CFG_STD_SHIFT              10
1047 #define  PLL_CFG_LD                     0x00000300
1048 #define  PLL_CFG_LD_SHIFT               8
1049 #define  PLL_CFG_MPY                    0x0000001e
1050 #define  PLL_CFG_MPY_SHIFT              1
1051 #define  PLL_CFG_ENPLL                  0x00000001
1052
1053 #define ESR2_TI_PLL_STS_L               (ESR2_BASE + 0x002)
1054 #define ESR2_TI_PLL_STS_H               (ESR2_BASE + 0x003)
1055 #define  PLL_STS_LOCK                   0x00000001
1056
1057 #define ESR2_TI_PLL_TEST_CFG_L          (ESR2_BASE + 0x004)
1058 #define ESR2_TI_PLL_TEST_CFG_H          (ESR2_BASE + 0x005)
1059 #define  PLL_TEST_INVPATT               0x00004000
1060 #define  PLL_TEST_RATE                  0x00003000
1061 #define  PLL_TEST_RATE_SHIFT            12
1062 #define  PLL_TEST_CFG_ENBSAC            0x00000400
1063 #define  PLL_TEST_CFG_ENBSRX            0x00000200
1064 #define  PLL_TEST_CFG_ENBSTX            0x00000100
1065 #define  PLL_TEST_CFG_LOOPBACK_PAD      0x00000040
1066 #define  PLL_TEST_CFG_LOOPBACK_CML_DIS  0x00000080
1067 #define  PLL_TEST_CFG_LOOPBACK_CML_EN   0x000000c0
1068 #define  PLL_TEST_CFG_CLKBYP            0x00000030
1069 #define  PLL_TEST_CFG_CLKBYP_SHIFT      4
1070 #define  PLL_TEST_CFG_EN_RXPATT         0x00000008
1071 #define  PLL_TEST_CFG_EN_TXPATT         0x00000004
1072 #define  PLL_TEST_CFG_TPATT             0x00000003
1073 #define  PLL_TEST_CFG_TPATT_SHIFT       0
1074
1075 #define ESR2_TI_PLL_TX_CFG_L(CHAN)      (ESR2_BASE + 0x100 + (CHAN) * 4)
1076 #define ESR2_TI_PLL_TX_CFG_H(CHAN)      (ESR2_BASE + 0x101 + (CHAN) * 4)
1077 #define  PLL_TX_CFG_RDTCT               0x00600000
1078 #define  PLL_TX_CFG_RDTCT_SHIFT         21
1079 #define  PLL_TX_CFG_ENIDL               0x00100000
1080 #define  PLL_TX_CFG_BSTX                0x00020000
1081 #define  PLL_TX_CFG_ENFTP               0x00010000
1082 #define  PLL_TX_CFG_DE                  0x0000f000
1083 #define  PLL_TX_CFG_DE_SHIFT            12
1084 #define  PLL_TX_CFG_SWING_125MV         0x00000000
1085 #define  PLL_TX_CFG_SWING_250MV         0x00000200
1086 #define  PLL_TX_CFG_SWING_500MV         0x00000400
1087 #define  PLL_TX_CFG_SWING_625MV         0x00000600
1088 #define  PLL_TX_CFG_SWING_750MV         0x00000800
1089 #define  PLL_TX_CFG_SWING_1000MV        0x00000a00
1090 #define  PLL_TX_CFG_SWING_1250MV        0x00000c00
1091 #define  PLL_TX_CFG_SWING_1375MV        0x00000e00
1092 #define  PLL_TX_CFG_CM                  0x00000100
1093 #define  PLL_TX_CFG_INVPAIR             0x00000080
1094 #define  PLL_TX_CFG_RATE                0x00000060
1095 #define  PLL_TX_CFG_RATE_SHIFT          5
1096 #define  PLL_TX_CFG_BUSWIDTH            0x0000001c
1097 #define  PLL_TX_CFG_BUSWIDTH_SHIFT      2
1098 #define  PLL_TX_CFG_ENTEST              0x00000002
1099 #define  PLL_TX_CFG_ENTX                0x00000001
1100
1101 #define ESR2_TI_PLL_TX_STS_L(CHAN)      (ESR2_BASE + 0x102 + (CHAN) * 4)
1102 #define ESR2_TI_PLL_TX_STS_H(CHAN)      (ESR2_BASE + 0x103 + (CHAN) * 4)
1103 #define  PLL_TX_STS_RDTCTIP             0x00000002
1104 #define  PLL_TX_STS_TESTFAIL            0x00000001
1105
1106 #define ESR2_TI_PLL_RX_CFG_L(CHAN)      (ESR2_BASE + 0x120 + (CHAN) * 4)
1107 #define ESR2_TI_PLL_RX_CFG_H(CHAN)      (ESR2_BASE + 0x121 + (CHAN) * 4)
1108 #define  PLL_RX_CFG_BSINRXN             0x02000000
1109 #define  PLL_RX_CFG_BSINRXP             0x01000000
1110 #define  PLL_RX_CFG_EQ_MAX_LF           0x00000000
1111 #define  PLL_RX_CFG_EQ_LP_ADAPTIVE      0x00080000
1112 #define  PLL_RX_CFG_EQ_LP_1084MHZ       0x00400000
1113 #define  PLL_RX_CFG_EQ_LP_805MHZ        0x00480000
1114 #define  PLL_RX_CFG_EQ_LP_573MHZ        0x00500000
1115 #define  PLL_RX_CFG_EQ_LP_402MHZ        0x00580000
1116 #define  PLL_RX_CFG_EQ_LP_304MHZ        0x00600000
1117 #define  PLL_RX_CFG_EQ_LP_216MHZ        0x00680000
1118 #define  PLL_RX_CFG_EQ_LP_156MHZ        0x00700000
1119 #define  PLL_RX_CFG_EQ_LP_135MHZ        0x00780000
1120 #define  PLL_RX_CFG_EQ_SHIFT            19
1121 #define  PLL_RX_CFG_CDR                 0x00070000
1122 #define  PLL_RX_CFG_CDR_SHIFT           16
1123 #define  PLL_RX_CFG_LOS_DIS             0x00000000
1124 #define  PLL_RX_CFG_LOS_HTHRESH         0x00004000
1125 #define  PLL_RX_CFG_LOS_LTHRESH         0x00008000
1126 #define  PLL_RX_CFG_ALIGN_DIS           0x00000000
1127 #define  PLL_RX_CFG_ALIGN_ENA           0x00001000
1128 #define  PLL_RX_CFG_ALIGN_JOG           0x00002000
1129 #define  PLL_RX_CFG_TERM_VDDT           0x00000000
1130 #define  PLL_RX_CFG_TERM_0P8VDDT        0x00000100
1131 #define  PLL_RX_CFG_TERM_FLOAT          0x00000300
1132 #define  PLL_RX_CFG_INVPAIR             0x00000080
1133 #define  PLL_RX_CFG_RATE                0x00000060
1134 #define  PLL_RX_CFG_RATE_SHIFT          5
1135 #define  PLL_RX_CFG_BUSWIDTH            0x0000001c
1136 #define  PLL_RX_CFG_BUSWIDTH_SHIFT      2
1137 #define  PLL_RX_CFG_ENTEST              0x00000002
1138 #define  PLL_RX_CFG_ENRX                0x00000001
1139
1140 #define ESR2_TI_PLL_RX_STS_L(CHAN)      (ESR2_BASE + 0x122 + (CHAN) * 4)
1141 #define ESR2_TI_PLL_RX_STS_H(CHAN)      (ESR2_BASE + 0x123 + (CHAN) * 4)
1142 #define  PLL_RX_STS_CRCIDTCT            0x00000200
1143 #define  PLL_RX_STS_CWDTCT              0x00000100
1144 #define  PLL_RX_STS_BSRXN               0x00000020
1145 #define  PLL_RX_STS_BSRXP               0x00000010
1146 #define  PLL_RX_STS_LOSDTCT             0x00000008
1147 #define  PLL_RX_STS_ODDCG               0x00000004
1148 #define  PLL_RX_STS_SYNC                0x00000002
1149 #define  PLL_RX_STS_TESTFAIL            0x00000001
1150
1151 #define ENET_VLAN_TBL(IDX)              (FZC_FFLP + 0x00000UL + (IDX) * 8UL)
1152 #define  ENET_VLAN_TBL_PARITY1          0x0000000000020000ULL
1153 #define  ENET_VLAN_TBL_PARITY0          0x0000000000010000ULL
1154 #define  ENET_VLAN_TBL_VPR              0x0000000000000008ULL
1155 #define  ENET_VLAN_TBL_VLANRDCTBLN      0x0000000000000007ULL
1156 #define  ENET_VLAN_TBL_SHIFT(PORT)      ((PORT) * 4)
1157
1158 #define ENET_VLAN_TBL_NUM_ENTRIES       4096
1159
1160 #define FFLP_VLAN_PAR_ERR               (FZC_FFLP + 0x0800UL)
1161 #define  FFLP_VLAN_PAR_ERR_ERR          0x0000000080000000ULL
1162 #define  FFLP_VLAN_PAR_ERR_M_ERR        0x0000000040000000ULL
1163 #define  FFLP_VLAN_PAR_ERR_ADDR         0x000000003ffc0000ULL
1164 #define  FFLP_VLAN_PAR_ERR_DATA         0x000000000003ffffULL
1165
1166 #define L2_CLS(IDX)                     (FZC_FFLP + 0x20000UL + (IDX) * 8UL)
1167 #define  L2_CLS_VLD                     0x0000000000010000ULL
1168 #define  L2_CLS_ETYPE                   0x000000000000ffffULL
1169 #define  L2_CLS_ETYPE_SHIFT             0
1170
1171 #define L3_CLS(IDX)                     (FZC_FFLP + 0x20010UL + (IDX) * 8UL)
1172 #define  L3_CLS_VALID                   0x0000000002000000ULL
1173 #define  L3_CLS_IPVER                   0x0000000001000000ULL
1174 #define  L3_CLS_PID                     0x0000000000ff0000ULL
1175 #define  L3_CLS_PID_SHIFT               16
1176 #define  L3_CLS_TOSMASK                 0x000000000000ff00ULL
1177 #define  L3_CLS_TOSMASK_SHIFT           8
1178 #define  L3_CLS_TOS                     0x00000000000000ffULL
1179 #define  L3_CLS_TOS_SHIFT               0
1180
1181 #define TCAM_KEY(IDX)                   (FZC_FFLP + 0x20030UL + (IDX) * 8UL)
1182 #define  TCAM_KEY_DISC                  0x0000000000000008ULL
1183 #define  TCAM_KEY_TSEL                  0x0000000000000004ULL
1184 #define  TCAM_KEY_IPADDR                0x0000000000000001ULL
1185
1186 #define TCAM_KEY_0                      (FZC_FFLP + 0x20090UL)
1187 #define  TCAM_KEY_0_KEY                 0x00000000000000ffULL /* bits 192-199 */
1188
1189 #define TCAM_KEY_1                      (FZC_FFLP + 0x20098UL)
1190 #define  TCAM_KEY_1_KEY                 0xffffffffffffffffULL /* bits 128-191 */
1191
1192 #define TCAM_KEY_2                      (FZC_FFLP + 0x200a0UL)
1193 #define  TCAM_KEY_2_KEY                 0xffffffffffffffffULL /* bits 64-127 */
1194
1195 #define TCAM_KEY_3                      (FZC_FFLP + 0x200a8UL)
1196 #define  TCAM_KEY_3_KEY                 0xffffffffffffffffULL /* bits 0-63 */
1197
1198 #define TCAM_KEY_MASK_0                 (FZC_FFLP + 0x200b0UL)
1199 #define  TCAM_KEY_MASK_0_KEY_SEL        0x00000000000000ffULL /* bits 192-199 */
1200
1201 #define TCAM_KEY_MASK_1                 (FZC_FFLP + 0x200b8UL)
1202 #define  TCAM_KEY_MASK_1_KEY_SEL        0xffffffffffffffffULL /* bits 128-191 */
1203
1204 #define TCAM_KEY_MASK_2                 (FZC_FFLP + 0x200c0UL)
1205 #define  TCAM_KEY_MASK_2_KEY_SEL        0xffffffffffffffffULL /* bits 64-127 */
1206
1207 #define TCAM_KEY_MASK_3                 (FZC_FFLP + 0x200c8UL)
1208 #define  TCAM_KEY_MASK_3_KEY_SEL        0xffffffffffffffffULL /* bits 0-63 */
1209
1210 #define TCAM_CTL                        (FZC_FFLP + 0x200d0UL)
1211 #define  TCAM_CTL_RWC                   0x00000000001c0000ULL
1212 #define  TCAM_CTL_RWC_TCAM_WRITE        0x0000000000000000ULL
1213 #define  TCAM_CTL_RWC_TCAM_READ         0x0000000000040000ULL
1214 #define  TCAM_CTL_RWC_TCAM_COMPARE      0x0000000000080000ULL
1215 #define  TCAM_CTL_RWC_RAM_WRITE         0x0000000000100000ULL
1216 #define  TCAM_CTL_RWC_RAM_READ          0x0000000000140000ULL
1217 #define  TCAM_CTL_STAT                  0x0000000000020000ULL
1218 #define  TCAM_CTL_MATCH                 0x0000000000010000ULL
1219 #define  TCAM_CTL_LOC                   0x00000000000003ffULL
1220
1221 #define TCAM_ERR                        (FZC_FFLP + 0x200d8UL)
1222 #define  TCAM_ERR_ERR                   0x0000000080000000ULL
1223 #define  TCAM_ERR_P_ECC                 0x0000000040000000ULL
1224 #define  TCAM_ERR_MULT                  0x0000000020000000ULL
1225 #define  TCAM_ERR_ADDR                  0x0000000000ff0000ULL
1226 #define  TCAM_ERR_SYNDROME              0x000000000000ffffULL
1227
1228 #define HASH_LOOKUP_ERR_LOG1            (FZC_FFLP + 0x200e0UL)
1229 #define  HASH_LOOKUP_ERR_LOG1_ERR       0x0000000000000008ULL
1230 #define  HASH_LOOKUP_ERR_LOG1_MULT_LK   0x0000000000000004ULL
1231 #define  HASH_LOOKUP_ERR_LOG1_CU        0x0000000000000002ULL
1232 #define  HASH_LOOKUP_ERR_LOG1_MULT_BIT  0x0000000000000001ULL
1233
1234 #define HASH_LOOKUP_ERR_LOG2            (FZC_FFLP + 0x200e8UL)
1235 #define  HASH_LOOKUP_ERR_LOG2_H1        0x000000007ffff800ULL
1236 #define  HASH_LOOKUP_ERR_LOG2_SUBAREA   0x0000000000000700ULL
1237 #define  HASH_LOOKUP_ERR_LOG2_SYNDROME  0x00000000000000ffULL
1238
1239 #define FFLP_CFG_1                      (FZC_FFLP + 0x20100UL)
1240 #define  FFLP_CFG_1_TCAM_DIS            0x0000000004000000ULL
1241 #define  FFLP_CFG_1_PIO_DBG_SEL         0x0000000003800000ULL
1242 #define  FFLP_CFG_1_PIO_FIO_RST         0x0000000000400000ULL
1243 #define  FFLP_CFG_1_PIO_FIO_LAT         0x0000000000300000ULL
1244 #define  FFLP_CFG_1_CAMLAT              0x00000000000f0000ULL
1245 #define  FFLP_CFG_1_CAMLAT_SHIFT        16
1246 #define  FFLP_CFG_1_CAMRATIO            0x000000000000f000ULL
1247 #define  FFLP_CFG_1_CAMRATIO_SHIFT      12
1248 #define  FFLP_CFG_1_FCRAMRATIO          0x0000000000000f00ULL
1249 #define  FFLP_CFG_1_FCRAMRATIO_SHIFT    8
1250 #define  FFLP_CFG_1_FCRAMOUTDR_MASK     0x00000000000000f0ULL
1251 #define  FFLP_CFG_1_FCRAMOUTDR_NORMAL   0x0000000000000000ULL
1252 #define  FFLP_CFG_1_FCRAMOUTDR_STRONG   0x0000000000000050ULL
1253 #define  FFLP_CFG_1_FCRAMOUTDR_WEAK     0x00000000000000a0ULL
1254 #define  FFLP_CFG_1_FCRAMQS             0x0000000000000008ULL
1255 #define  FFLP_CFG_1_ERRORDIS            0x0000000000000004ULL
1256 #define  FFLP_CFG_1_FFLPINITDONE        0x0000000000000002ULL
1257 #define  FFLP_CFG_1_LLCSNAP             0x0000000000000001ULL
1258
1259 #define DEFAULT_FCRAMRATIO              10
1260
1261 #define DEFAULT_TCAM_LATENCY            4
1262 #define DEFAULT_TCAM_ACCESS_RATIO       10
1263
1264 #define TCP_CFLAG_MSK                   (FZC_FFLP + 0x20108UL)
1265 #define  TCP_CFLAG_MSK_MASK             0x0000000000000fffULL
1266
1267 #define FCRAM_REF_TMR                   (FZC_FFLP + 0x20110UL)
1268 #define  FCRAM_REF_TMR_MAX              0x00000000ffff0000ULL
1269 #define  FCRAM_REF_TMR_MAX_SHIFT        16
1270 #define  FCRAM_REF_TMR_MIN              0x000000000000ffffULL
1271 #define  FCRAM_REF_TMR_MIN_SHIFT        0
1272
1273 #define DEFAULT_FCRAM_REFRESH_MAX       512
1274 #define DEFAULT_FCRAM_REFRESH_MIN       512
1275
1276 #define FCRAM_FIO_ADDR                  (FZC_FFLP + 0x20118UL)
1277 #define  FCRAM_FIO_ADDR_ADDR            0x00000000000000ffULL
1278
1279 #define FCRAM_FIO_DAT                   (FZC_FFLP + 0x20120UL)
1280 #define  FCRAM_FIO_DAT_DATA             0x000000000000ffffULL
1281
1282 #define FCRAM_ERR_TST0                  (FZC_FFLP + 0x20128UL)
1283 #define  FCRAM_ERR_TST0_SYND            0x00000000000000ffULL
1284
1285 #define FCRAM_ERR_TST1                  (FZC_FFLP + 0x20130UL)
1286 #define  FCRAM_ERR_TST1_DAT             0x00000000ffffffffULL
1287
1288 #define FCRAM_ERR_TST2                  (FZC_FFLP + 0x20138UL)
1289 #define  FCRAM_ERR_TST2_DAT             0x00000000ffffffffULL
1290
1291 #define FFLP_ERR_MASK                   (FZC_FFLP + 0x20140UL)
1292 #define  FFLP_ERR_MASK_HSH_TBL_DAT      0x00000000000007f8ULL
1293 #define  FFLP_ERR_MASK_HSH_TBL_LKUP     0x0000000000000004ULL
1294 #define  FFLP_ERR_MASK_TCAM             0x0000000000000002ULL
1295 #define  FFLP_ERR_MASK_VLAN             0x0000000000000001ULL
1296
1297 #define FFLP_DBG_TRAIN_VCT              (FZC_FFLP + 0x20148UL)
1298 #define  FFLP_DBG_TRAIN_VCT_VECTOR      0x00000000ffffffffULL
1299
1300 #define FCRAM_PHY_RD_LAT                (FZC_FFLP + 0x20150UL)
1301 #define  FCRAM_PHY_RD_LAT_LAT           0x00000000000000ffULL
1302
1303 /* Ethernet TCAM format */
1304 #define TCAM_ETHKEY0_RESV1              0xffffffffffffff00ULL
1305 #define TCAM_ETHKEY0_CLASS_CODE         0x00000000000000f8ULL
1306 #define TCAM_ETHKEY0_CLASS_CODE_SHIFT   3
1307 #define TCAM_ETHKEY0_RESV2              0x0000000000000007ULL
1308 #define TCAM_ETHKEY1_FRAME_BYTE0_7(NUM) (0xff << ((7 - NUM) * 8))
1309 #define TCAM_ETHKEY2_FRAME_BYTE8        0xff00000000000000ULL
1310 #define TCAM_ETHKEY2_FRAME_BYTE8_SHIFT  56
1311 #define TCAM_ETHKEY2_FRAME_BYTE9        0x00ff000000000000ULL
1312 #define TCAM_ETHKEY2_FRAME_BYTE9_SHIFT  48
1313 #define TCAM_ETHKEY2_FRAME_BYTE10       0x0000ff0000000000ULL
1314 #define TCAM_ETHKEY2_FRAME_BYTE10_SHIFT 40
1315 #define TCAM_ETHKEY2_FRAME_RESV         0x000000ffffffffffULL
1316 #define TCAM_ETHKEY3_FRAME_RESV         0xffffffffffffffffULL
1317
1318 /* IPV4 TCAM format */
1319 #define TCAM_V4KEY0_RESV1               0xffffffffffffff00ULL
1320 #define TCAM_V4KEY0_CLASS_CODE          0x00000000000000f8ULL
1321 #define TCAM_V4KEY0_CLASS_CODE_SHIFT    3
1322 #define TCAM_V4KEY0_RESV2               0x0000000000000007ULL
1323 #define TCAM_V4KEY1_L2RDCNUM            0xf800000000000000ULL
1324 #define TCAM_V4KEY1_L2RDCNUM_SHIFT      59
1325 #define TCAM_V4KEY1_NOPORT              0x0400000000000000ULL
1326 #define TCAM_V4KEY1_RESV                0x03ffffffffffffffULL
1327 #define TCAM_V4KEY2_RESV                0xffff000000000000ULL
1328 #define TCAM_V4KEY2_TOS                 0x0000ff0000000000ULL
1329 #define TCAM_V4KEY2_TOS_SHIFT           40
1330 #define TCAM_V4KEY2_PROTO               0x000000ff00000000ULL
1331 #define TCAM_V4KEY2_PROTO_SHIFT         32
1332 #define TCAM_V4KEY2_PORT_SPI            0x00000000ffffffffULL
1333 #define TCAM_V4KEY2_PORT_SPI_SHIFT      0
1334 #define TCAM_V4KEY3_SADDR               0xffffffff00000000ULL
1335 #define TCAM_V4KEY3_SADDR_SHIFT         32
1336 #define TCAM_V4KEY3_DADDR               0x00000000ffffffffULL
1337 #define TCAM_V4KEY3_DADDR_SHIFT         0
1338
1339 /* IPV6 TCAM format */
1340 #define TCAM_V6KEY0_RESV1               0xffffffffffffff00ULL
1341 #define TCAM_V6KEY0_CLASS_CODE          0x00000000000000f8ULL
1342 #define TCAM_V6KEY0_CLASS_CODE_SHIFT    3
1343 #define TCAM_V6KEY0_RESV2               0x0000000000000007ULL
1344 #define TCAM_V6KEY1_L2RDCNUM            0xf800000000000000ULL
1345 #define TCAM_V6KEY1_L2RDCNUM_SHIFT      59
1346 #define TCAM_V6KEY1_NOPORT              0x0400000000000000ULL
1347 #define TCAM_V6KEY1_RESV                0x03ff000000000000ULL
1348 #define TCAM_V6KEY1_TOS                 0x0000ff0000000000ULL
1349 #define TCAM_V6KEY1_TOS_SHIFT           40
1350 #define TCAM_V6KEY1_NEXT_HDR            0x000000ff00000000ULL
1351 #define TCAM_V6KEY1_NEXT_HDR_SHIFT      32
1352 #define TCAM_V6KEY1_PORT_SPI            0x00000000ffffffffULL
1353 #define TCAM_V6KEY1_PORT_SPI_SHIFT      0
1354 #define TCAM_V6KEY2_ADDR_HIGH           0xffffffffffffffffULL
1355 #define TCAM_V6KEY3_ADDR_LOW            0xffffffffffffffffULL
1356
1357 #define TCAM_ASSOCDATA_SYNDROME         0x000003fffc000000ULL
1358 #define TCAM_ASSOCDATA_SYNDROME_SHIFT   26
1359 #define TCAM_ASSOCDATA_ZFID             0x0000000003ffc000ULL
1360 #define TCAM_ASSOCDATA_ZFID_SHIFT       14
1361 #define TCAM_ASSOCDATA_V4_ECC_OK        0x0000000000002000ULL
1362 #define TCAM_ASSOCDATA_DISC             0x0000000000001000ULL
1363 #define TCAM_ASSOCDATA_TRES_MASK        0x0000000000000c00ULL
1364 #define TCAM_ASSOCDATA_TRES_USE_L2RDC   0x0000000000000000ULL
1365 #define TCAM_ASSOCDATA_TRES_USE_OFFSET  0x0000000000000400ULL
1366 #define TCAM_ASSOCDATA_TRES_OVR_RDC     0x0000000000000800ULL
1367 #define TCAM_ASSOCDATA_TRES_OVR_RDC_OFF 0x0000000000000c00ULL
1368 #define TCAM_ASSOCDATA_RDCTBL           0x0000000000000380ULL
1369 #define TCAM_ASSOCDATA_RDCTBL_SHIFT     7
1370 #define TCAM_ASSOCDATA_OFFSET           0x000000000000007cULL
1371 #define TCAM_ASSOCDATA_OFFSET_SHIFT     2
1372 #define TCAM_ASSOCDATA_ZFVLD            0x0000000000000002ULL
1373 #define TCAM_ASSOCDATA_AGE              0x0000000000000001ULL
1374
1375 #define FLOW_KEY(IDX)                   (FZC_FFLP + 0x40000UL + (IDX) * 8UL)
1376 #define  FLOW_KEY_PORT                  0x0000000000000200ULL
1377 #define  FLOW_KEY_L2DA                  0x0000000000000100ULL
1378 #define  FLOW_KEY_VLAN                  0x0000000000000080ULL
1379 #define  FLOW_KEY_IPSA                  0x0000000000000040ULL
1380 #define  FLOW_KEY_IPDA                  0x0000000000000020ULL
1381 #define  FLOW_KEY_PROTO                 0x0000000000000010ULL
1382 #define  FLOW_KEY_L4_0                  0x000000000000000cULL
1383 #define  FLOW_KEY_L4_0_SHIFT            2
1384 #define  FLOW_KEY_L4_1                  0x0000000000000003ULL
1385 #define  FLOW_KEY_L4_1_SHIFT            0
1386
1387 #define  FLOW_KEY_L4_NONE               0x0
1388 #define  FLOW_KEY_L4_RESV               0x1
1389 #define  FLOW_KEY_L4_BYTE12             0x2
1390 #define  FLOW_KEY_L4_BYTE56             0x3
1391
1392 #define H1POLY                          (FZC_FFLP + 0x40060UL)
1393 #define  H1POLY_INITVAL                 0x00000000ffffffffULL
1394
1395 #define H2POLY                          (FZC_FFLP + 0x40068UL)
1396 #define  H2POLY_INITVAL                 0x000000000000ffffULL
1397
1398 #define FLW_PRT_SEL(IDX)                (FZC_FFLP + 0x40070UL + (IDX) * 8UL)
1399 #define  FLW_PRT_SEL_EXT                0x0000000000010000ULL
1400 #define  FLW_PRT_SEL_MASK               0x0000000000001f00ULL
1401 #define  FLW_PRT_SEL_MASK_SHIFT         8
1402 #define  FLW_PRT_SEL_BASE               0x000000000000001fULL
1403 #define  FLW_PRT_SEL_BASE_SHIFT         0
1404
1405 #define HASH_TBL_ADDR(IDX)              (FFLP + 0x00000UL + (IDX) * 8192UL)
1406 #define  HASH_TBL_ADDR_AUTOINC          0x0000000000800000ULL
1407 #define  HASH_TBL_ADDR_ADDR             0x00000000007fffffULL
1408
1409 #define HASH_TBL_DATA(IDX)              (FFLP + 0x00008UL + (IDX) * 8192UL)
1410 #define  HASH_TBL_DATA_DATA             0xffffffffffffffffULL
1411
1412 /* FCRAM hash table entries are up to 8 64-bit words in size.
1413  * The layout of each entry is determined by the settings in the
1414  * first word, which is the header.
1415  *
1416  * The indexing is controllable per partition (there is one partition
1417  * per RDC group, thus a total of eight) using the BASE and MASK fields
1418  * of FLW_PRT_SEL above.
1419  */
1420 #define FCRAM_SIZE                      0x800000
1421 #define FCRAM_NUM_PARTITIONS            8
1422
1423 /* Generic HASH entry header, used for all non-optimized formats.  */
1424 #define HASH_HEADER_FMT                 0x8000000000000000ULL
1425 #define HASH_HEADER_EXT                 0x4000000000000000ULL
1426 #define HASH_HEADER_VALID               0x2000000000000000ULL
1427 #define HASH_HEADER_RESVD               0x1000000000000000ULL
1428 #define HASH_HEADER_L2_DADDR            0x0ffffffffffff000ULL
1429 #define HASH_HEADER_L2_DADDR_SHIFT      12
1430 #define HASH_HEADER_VLAN                0x0000000000000fffULL
1431 #define HASH_HEADER_VLAN_SHIFT          0
1432
1433 /* Optimized format, just a header with a special layout defined below.
1434  * Set FMT and EXT both to zero to indicate this layout is being used.
1435  */
1436 #define HASH_OPT_HEADER_FMT             0x8000000000000000ULL
1437 #define HASH_OPT_HEADER_EXT             0x4000000000000000ULL
1438 #define HASH_OPT_HEADER_VALID           0x2000000000000000ULL
1439 #define HASH_OPT_HEADER_RDCOFF          0x1f00000000000000ULL
1440 #define HASH_OPT_HEADER_RDCOFF_SHIFT    56
1441 #define HASH_OPT_HEADER_HASH2           0x00ffff0000000000ULL
1442 #define HASH_OPT_HEADER_HASH2_SHIFT     40
1443 #define HASH_OPT_HEADER_RESVD           0x000000ff00000000ULL
1444 #define HASH_OPT_HEADER_USERINFO        0x00000000ffffffffULL
1445 #define HASH_OPT_HEADER_USERINFO_SHIFT  0
1446
1447 /* Port and protocol word used for ipv4 and ipv6 layouts.  */
1448 #define HASH_PORT_DPORT                 0xffff000000000000ULL
1449 #define HASH_PORT_DPORT_SHIFT           48
1450 #define HASH_PORT_SPORT                 0x0000ffff00000000ULL
1451 #define HASH_PORT_SPORT_SHIFT           32
1452 #define HASH_PORT_PROTO                 0x00000000ff000000ULL
1453 #define HASH_PORT_PROTO_SHIFT           24
1454 #define HASH_PORT_PORT_OFF              0x0000000000c00000ULL
1455 #define HASH_PORT_PORT_OFF_SHIFT        22
1456 #define HASH_PORT_PORT_RESV             0x00000000003fffffULL
1457
1458 /* Action word used for ipv4 and ipv6 layouts.  */
1459 #define HASH_ACTION_RESV1               0xe000000000000000ULL
1460 #define HASH_ACTION_RDCOFF              0x1f00000000000000ULL
1461 #define HASH_ACTION_RDCOFF_SHIFT        56
1462 #define HASH_ACTION_ZFVALID             0x0080000000000000ULL
1463 #define HASH_ACTION_RESV2               0x0070000000000000ULL
1464 #define HASH_ACTION_ZFID                0x000fff0000000000ULL
1465 #define HASH_ACTION_ZFID_SHIFT          40
1466 #define HASH_ACTION_RESV3               0x000000ff00000000ULL
1467 #define HASH_ACTION_USERINFO            0x00000000ffffffffULL
1468 #define HASH_ACTION_USERINFO_SHIFT      0
1469
1470 /* IPV4 address word.  Addresses are in network endian. */
1471 #define HASH_IP4ADDR_SADDR              0xffffffff00000000ULL
1472 #define HASH_IP4ADDR_SADDR_SHIFT        32
1473 #define HASH_IP4ADDR_DADDR              0x00000000ffffffffULL
1474 #define HASH_IP4ADDR_DADDR_SHIFT        0
1475
1476 /* IPV6 address layout is 4 words, first two are saddr, next two
1477  * are daddr.  Addresses are in network endian.
1478  */
1479
1480 struct fcram_hash_opt {
1481         u64     header;
1482 };
1483
1484 /* EXT=1, FMT=0 */
1485 struct fcram_hash_ipv4 {
1486         u64     header;
1487         u64     addrs;
1488         u64     ports;
1489         u64     action;
1490 };
1491
1492 /* EXT=1, FMT=1 */
1493 struct fcram_hash_ipv6 {
1494         u64     header;
1495         u64     addrs[4];
1496         u64     ports;
1497         u64     action;
1498 };
1499
1500 #define HASH_TBL_DATA_LOG(IDX)          (FFLP + 0x00010UL + (IDX) * 8192UL)
1501 #define  HASH_TBL_DATA_LOG_ERR          0x0000000080000000ULL
1502 #define  HASH_TBL_DATA_LOG_ADDR         0x000000007fffff00ULL
1503 #define  HASH_TBL_DATA_LOG_SYNDROME     0x00000000000000ffULL
1504
1505 #define RX_DMA_CK_DIV                   (FZC_DMC + 0x00000UL)
1506 #define  RX_DMA_CK_DIV_CNT              0x000000000000ffffULL
1507
1508 #define DEF_RDC(IDX)                    (FZC_DMC + 0x00008UL + (IDX) * 0x8UL)
1509 #define  DEF_RDC_VAL                    0x000000000000001fULL
1510
1511 #define PT_DRR_WT(IDX)                  (FZC_DMC + 0x00028UL + (IDX) * 0x8UL)
1512 #define  PT_DRR_WT_VAL                  0x000000000000ffffULL
1513
1514 #define PT_DRR_WEIGHT_DEFAULT_10G       0x0400
1515 #define PT_DRR_WEIGHT_DEFAULT_1G        0x0066
1516
1517 #define PT_USE(IDX)                     (FZC_DMC + 0x00048UL + (IDX) * 0x8UL)
1518 #define  PT_USE_CNT                     0x00000000000fffffULL
1519
1520 #define RED_RAN_INIT                    (FZC_DMC + 0x00068UL)
1521 #define  RED_RAN_INIT_OPMODE            0x0000000000010000ULL
1522 #define  RED_RAN_INIT_VAL               0x000000000000ffffULL
1523
1524 #define RX_ADDR_MD                      (FZC_DMC + 0x00070UL)
1525 #define  RX_ADDR_MD_DBG_PT_MUX_SEL      0x000000000000000cULL
1526 #define  RX_ADDR_MD_RAM_ACC             0x0000000000000002ULL
1527 #define  RX_ADDR_MD_MODE32              0x0000000000000001ULL
1528
1529 #define RDMC_PRE_PAR_ERR                (FZC_DMC + 0x00078UL)
1530 #define  RDMC_PRE_PAR_ERR_ERR           0x0000000000008000ULL
1531 #define  RDMC_PRE_PAR_ERR_MERR          0x0000000000004000ULL
1532 #define  RDMC_PRE_PAR_ERR_ADDR          0x00000000000000ffULL
1533
1534 #define RDMC_SHA_PAR_ERR                (FZC_DMC + 0x00080UL)
1535 #define  RDMC_SHA_PAR_ERR_ERR           0x0000000000008000ULL
1536 #define  RDMC_SHA_PAR_ERR_MERR          0x0000000000004000ULL
1537 #define  RDMC_SHA_PAR_ERR_ADDR          0x00000000000000ffULL
1538
1539 #define RDMC_MEM_ADDR                   (FZC_DMC + 0x00088UL)
1540 #define  RDMC_MEM_ADDR_PRE_SHAD         0x0000000000000100ULL
1541 #define  RDMC_MEM_ADDR_ADDR             0x00000000000000ffULL
1542
1543 #define RDMC_MEM_DAT0                   (FZC_DMC + 0x00090UL)
1544 #define  RDMC_MEM_DAT0_DATA             0x00000000ffffffffULL /* bits 31:0 */
1545
1546 #define RDMC_MEM_DAT1                   (FZC_DMC + 0x00098UL)
1547 #define  RDMC_MEM_DAT1_DATA             0x00000000ffffffffULL /* bits 63:32 */
1548
1549 #define RDMC_MEM_DAT2                   (FZC_DMC + 0x000a0UL)
1550 #define  RDMC_MEM_DAT2_DATA             0x00000000ffffffffULL /* bits 95:64 */
1551
1552 #define RDMC_MEM_DAT3                   (FZC_DMC + 0x000a8UL)
1553 #define  RDMC_MEM_DAT3_DATA             0x00000000ffffffffULL /* bits 127:96 */
1554
1555 #define RDMC_MEM_DAT4                   (FZC_DMC + 0x000b0UL)
1556 #define  RDMC_MEM_DAT4_DATA             0x00000000000fffffULL /* bits 147:128 */
1557
1558 #define RX_CTL_DAT_FIFO_STAT                    (FZC_DMC + 0x000b8UL)
1559 #define  RX_CTL_DAT_FIFO_STAT_ID_MISMATCH       0x0000000000000100ULL
1560 #define  RX_CTL_DAT_FIFO_STAT_ZCP_EOP_ERR       0x00000000000000f0ULL
1561 #define  RX_CTL_DAT_FIFO_STAT_IPP_EOP_ERR       0x000000000000000fULL
1562
1563 #define RX_CTL_DAT_FIFO_MASK                    (FZC_DMC + 0x000c0UL)
1564 #define  RX_CTL_DAT_FIFO_MASK_ID_MISMATCH       0x0000000000000100ULL
1565 #define  RX_CTL_DAT_FIFO_MASK_ZCP_EOP_ERR       0x00000000000000f0ULL
1566 #define  RX_CTL_DAT_FIFO_MASK_IPP_EOP_ERR       0x000000000000000fULL
1567
1568 #define RDMC_TRAINING_VECTOR                    (FZC_DMC + 0x000c8UL)
1569 #define  RDMC_TRAINING_VECTOR_TRAINING_VECTOR   0x00000000ffffffffULL
1570
1571 #define RX_CTL_DAT_FIFO_STAT_DBG                (FZC_DMC + 0x000d0UL)
1572 #define  RX_CTL_DAT_FIFO_STAT_DBG_ID_MISMATCH   0x0000000000000100ULL
1573 #define  RX_CTL_DAT_FIFO_STAT_DBG_ZCP_EOP_ERR   0x00000000000000f0ULL
1574 #define  RX_CTL_DAT_FIFO_STAT_DBG_IPP_EOP_ERR   0x000000000000000fULL
1575
1576 #define RDC_TBL(TBL,SLOT)               (FZC_ZCP + 0x10000UL + \
1577                                          (TBL) * (8UL * 16UL) + \
1578                                          (SLOT) * 8UL)
1579 #define  RDC_TBL_RDC                    0x000000000000000fULL
1580
1581 #define RX_LOG_PAGE_VLD(IDX)            (FZC_DMC + 0x20000UL + (IDX) * 0x40UL)
1582 #define  RX_LOG_PAGE_VLD_FUNC           0x000000000000000cULL
1583 #define  RX_LOG_PAGE_VLD_FUNC_SHIFT     2
1584 #define  RX_LOG_PAGE_VLD_PAGE1          0x0000000000000002ULL
1585 #define  RX_LOG_PAGE_VLD_PAGE0          0x0000000000000001ULL
1586
1587 #define RX_LOG_MASK1(IDX)               (FZC_DMC + 0x20008UL + (IDX) * 0x40UL)
1588 #define  RX_LOG_MASK1_MASK              0x00000000ffffffffULL
1589
1590 #define RX_LOG_VAL1(IDX)                (FZC_DMC + 0x20010UL + (IDX) * 0x40UL)
1591 #define  RX_LOG_VAL1_VALUE              0x00000000ffffffffULL
1592
1593 #define RX_LOG_MASK2(IDX)               (FZC_DMC + 0x20018UL + (IDX) * 0x40UL)
1594 #define  RX_LOG_MASK2_MASK              0x00000000ffffffffULL
1595
1596 #define RX_LOG_VAL2(IDX)                (FZC_DMC + 0x20020UL + (IDX) * 0x40UL)
1597 #define  RX_LOG_VAL2_VALUE              0x00000000ffffffffULL
1598
1599 #define RX_LOG_PAGE_RELO1(IDX)          (FZC_DMC + 0x20028UL + (IDX) * 0x40UL)
1600 #define  RX_LOG_PAGE_RELO1_RELO         0x00000000ffffffffULL
1601
1602 #define RX_LOG_PAGE_RELO2(IDX)          (FZC_DMC + 0x20030UL + (IDX) * 0x40UL)
1603 #define  RX_LOG_PAGE_RELO2_RELO         0x00000000ffffffffULL
1604
1605 #define RX_LOG_PAGE_HDL(IDX)            (FZC_DMC + 0x20038UL + (IDX) * 0x40UL)
1606 #define  RX_LOG_PAGE_HDL_HANDLE         0x00000000000fffffULL
1607
1608 #define TX_LOG_PAGE_VLD(IDX)            (FZC_DMC + 0x40000UL + (IDX) * 0x200UL)
1609 #define  TX_LOG_PAGE_VLD_FUNC           0x000000000000000cULL
1610 #define  TX_LOG_PAGE_VLD_FUNC_SHIFT     2
1611 #define  TX_LOG_PAGE_VLD_PAGE1          0x0000000000000002ULL
1612 #define  TX_LOG_PAGE_VLD_PAGE0          0x0000000000000001ULL
1613
1614 #define TX_LOG_MASK1(IDX)               (FZC_DMC + 0x40008UL + (IDX) * 0x200UL)
1615 #define  TX_LOG_MASK1_MASK              0x00000000ffffffffULL
1616
1617 #define TX_LOG_VAL1(IDX)                (FZC_DMC + 0x40010UL + (IDX) * 0x200UL)
1618 #define  TX_LOG_VAL1_VALUE              0x00000000ffffffffULL
1619
1620 #define TX_LOG_MASK2(IDX)               (FZC_DMC + 0x40018UL + (IDX) * 0x200UL)
1621 #define  TX_LOG_MASK2_MASK              0x00000000ffffffffULL
1622
1623 #define TX_LOG_VAL2(IDX)                (FZC_DMC + 0x40020UL + (IDX) * 0x200UL)
1624 #define  TX_LOG_VAL2_VALUE              0x00000000ffffffffULL
1625
1626 #define TX_LOG_PAGE_RELO1(IDX)          (FZC_DMC + 0x40028UL + (IDX) * 0x200UL)
1627 #define  TX_LOG_PAGE_RELO1_RELO         0x00000000ffffffffULL
1628
1629 #define TX_LOG_PAGE_RELO2(IDX)          (FZC_DMC + 0x40030UL + (IDX) * 0x200UL)
1630 #define  TX_LOG_PAGE_RELO2_RELO         0x00000000ffffffffULL
1631
1632 #define TX_LOG_PAGE_HDL(IDX)            (FZC_DMC + 0x40038UL + (IDX) * 0x200UL)
1633 #define  TX_LOG_PAGE_HDL_HANDLE         0x00000000000fffffULL
1634
1635 #define TX_ADDR_MD                      (FZC_DMC + 0x45000UL)
1636 #define  TX_ADDR_MD_MODE32              0x0000000000000001ULL
1637
1638 #define RDC_RED_PARA(IDX)               (FZC_DMC + 0x30000UL + (IDX) * 0x40UL)
1639 #define  RDC_RED_PARA_THRE_SYN          0x00000000fff00000ULL
1640 #define  RDC_RED_PARA_THRE_SYN_SHIFT    20
1641 #define  RDC_RED_PARA_WIN_SYN           0x00000000000f0000ULL
1642 #define  RDC_RED_PARA_WIN_SYN_SHIFT     16
1643 #define  RDC_RED_PARA_THRE              0x000000000000fff0ULL
1644 #define  RDC_RED_PARA_THRE_SHIFT        4
1645 #define  RDC_RED_PARA_WIN               0x000000000000000fULL
1646 #define  RDC_RED_PARA_WIN_SHIFT         0
1647
1648 #define RED_DIS_CNT(IDX)                (FZC_DMC + 0x30008UL + (IDX) * 0x40UL)
1649 #define  RED_DIS_CNT_OFLOW              0x0000000000010000ULL
1650 #define  RED_DIS_CNT_COUNT              0x000000000000ffffULL
1651
1652 #define IPP_CFIG                        (FZC_IPP + 0x00000UL)
1653 #define  IPP_CFIG_SOFT_RST              0x0000000080000000ULL
1654 #define  IPP_CFIG_IP_MAX_PKT            0x0000000001ffff00ULL
1655 #define  IPP_CFIG_IP_MAX_PKT_SHIFT      8
1656 #define  IPP_CFIG_FFLP_CS_PIO_W         0x0000000000000080ULL
1657 #define  IPP_CFIG_PFIFO_PIO_W           0x0000000000000040ULL
1658 #define  IPP_CFIG_DFIFO_PIO_W           0x0000000000000020ULL
1659 #define  IPP_CFIG_CKSUM_EN              0x0000000000000010ULL
1660 #define  IPP_CFIG_DROP_BAD_CRC          0x0000000000000008ULL
1661 #define  IPP_CFIG_DFIFO_ECC_EN          0x0000000000000004ULL
1662 #define  IPP_CFIG_DEBUG_BUS_OUT_EN      0x0000000000000002ULL
1663 #define  IPP_CFIG_IPP_ENABLE            0x0000000000000001ULL
1664
1665 #define IPP_PKT_DIS                     (FZC_IPP + 0x00020UL)
1666 #define  IPP_PKT_DIS_COUNT              0x0000000000003fffULL
1667
1668 #define IPP_BAD_CS_CNT                  (FZC_IPP + 0x00028UL)
1669 #define  IPP_BAD_CS_CNT_COUNT           0x0000000000003fffULL
1670
1671 #define IPP_ECC                         (FZC_IPP + 0x00030UL)
1672 #define  IPP_ECC_COUNT                  0x00000000000000ffULL
1673
1674 #define IPP_INT_STAT                    (FZC_IPP + 0x00040UL)
1675 #define  IPP_INT_STAT_SOP_MISS          0x0000000080000000ULL
1676 #define  IPP_INT_STAT_EOP_MISS          0x0000000040000000ULL
1677 #define  IPP_INT_STAT_DFIFO_UE          0x0000000030000000ULL
1678 #define  IPP_INT_STAT_DFIFO_CE          0x000000000c000000ULL
1679 #define  IPP_INT_STAT_DFIFO_ECC         0x0000000003000000ULL
1680 #define  IPP_INT_STAT_DFIFO_ECC_IDX     0x00000000007ff000ULL
1681 #define  IPP_INT_STAT_PFIFO_PERR        0x0000000000000800ULL
1682 #define  IPP_INT_STAT_ECC_ERR_MAX       0x0000000000000400ULL
1683 #define  IPP_INT_STAT_PFIFO_ERR_IDX     0x00000000000003f0ULL
1684 #define  IPP_INT_STAT_PFIFO_OVER        0x0000000000000008ULL
1685 #define  IPP_INT_STAT_PFIFO_UND         0x0000000000000004ULL
1686 #define  IPP_INT_STAT_BAD_CS_MX         0x0000000000000002ULL
1687 #define  IPP_INT_STAT_PKT_DIS_MX        0x0000000000000001ULL
1688 #define  IPP_INT_STAT_ALL               0x00000000ff7fffffULL
1689
1690 #define IPP_MSK                         (FZC_IPP + 0x00048UL)
1691 #define  IPP_MSK_ECC_ERR_MX             0x0000000000000080ULL
1692 #define  IPP_MSK_DFIFO_EOP_SOP          0x0000000000000040ULL
1693 #define  IPP_MSK_DFIFO_UC               0x0000000000000020ULL
1694 #define  IPP_MSK_PFIFO_PAR              0x0000000000000010ULL
1695 #define  IPP_MSK_PFIFO_OVER             0x0000000000000008ULL
1696 #define  IPP_MSK_PFIFO_UND              0x0000000000000004ULL
1697 #define  IPP_MSK_BAD_CS                 0x0000000000000002ULL
1698 #define  IPP_MSK_PKT_DIS_CNT            0x0000000000000001ULL
1699 #define  IPP_MSK_ALL                    0x00000000000000ffULL
1700
1701 #define IPP_PFIFO_RD0                   (FZC_IPP + 0x00060UL)
1702 #define  IPP_PFIFO_RD0_DATA             0x00000000ffffffffULL /* bits 31:0 */
1703
1704 #define IPP_PFIFO_RD1                   (FZC_IPP + 0x00068UL)
1705 #define  IPP_PFIFO_RD1_DATA             0x00000000ffffffffULL /* bits 63:32 */
1706
1707 #define IPP_PFIFO_RD2                   (FZC_IPP + 0x00070UL)
1708 #define  IPP_PFIFO_RD2_DATA             0x00000000ffffffffULL /* bits 95:64 */
1709
1710 #define IPP_PFIFO_RD3                   (FZC_IPP + 0x00078UL)
1711 #define  IPP_PFIFO_RD3_DATA             0x00000000ffffffffULL /* bits 127:96 */
1712
1713 #define IPP_PFIFO_RD4                   (FZC_IPP + 0x00080UL)
1714 #define  IPP_PFIFO_RD4_DATA             0x00000000ffffffffULL /* bits 145:128 */
1715
1716 #define IPP_PFIFO_WR0                   (FZC_IPP + 0x00088UL)
1717 #define  IPP_PFIFO_WR0_DATA             0x00000000ffffffffULL /* bits 31:0 */
1718
1719 #define IPP_PFIFO_WR1                   (FZC_IPP + 0x00090UL)
1720 #define  IPP_PFIFO_WR1_DATA             0x00000000ffffffffULL /* bits 63:32 */
1721
1722 #define IPP_PFIFO_WR2                   (FZC_IPP + 0x00098UL)
1723 #define  IPP_PFIFO_WR2_DATA             0x00000000ffffffffULL /* bits 95:64 */
1724
1725 #define IPP_PFIFO_WR3                   (FZC_IPP + 0x000a0UL)
1726 #define  IPP_PFIFO_WR3_DATA             0x00000000ffffffffULL /* bits 127:96 */
1727
1728 #define IPP_PFIFO_WR4                   (FZC_IPP + 0x000a8UL)
1729 #define  IPP_PFIFO_WR4_DATA             0x00000000ffffffffULL /* bits 145:128 */
1730
1731 #define IPP_PFIFO_RD_PTR                (FZC_IPP + 0x000b0UL)
1732 #define  IPP_PFIFO_RD_PTR_PTR           0x000000000000003fULL
1733
1734 #define IPP_PFIFO_WR_PTR                (FZC_IPP + 0x000b8UL)
1735 #define  IPP_PFIFO_WR_PTR_PTR           0x000000000000007fULL
1736
1737 #define IPP_DFIFO_RD0                   (FZC_IPP + 0x000c0UL)
1738 #define  IPP_DFIFO_RD0_DATA             0x00000000ffffffffULL /* bits 31:0 */
1739
1740 #define IPP_DFIFO_RD1                   (FZC_IPP + 0x000c8UL)
1741 #define  IPP_DFIFO_RD1_DATA             0x00000000ffffffffULL /* bits 63:32 */
1742
1743 #define IPP_DFIFO_RD2                   (FZC_IPP + 0x000d0UL)
1744 #define  IPP_DFIFO_RD2_DATA             0x00000000ffffffffULL /* bits 95:64 */
1745
1746 #define IPP_DFIFO_RD3                   (FZC_IPP + 0x000d8UL)
1747 #define  IPP_DFIFO_RD3_DATA             0x00000000ffffffffULL /* bits 127:96 */
1748
1749 #define IPP_DFIFO_RD4                   (FZC_IPP + 0x000e0UL)
1750 #define  IPP_DFIFO_RD4_DATA             0x00000000ffffffffULL /* bits 145:128 */
1751
1752 #define IPP_DFIFO_WR0                   (FZC_IPP + 0x000e8UL)
1753 #define  IPP_DFIFO_WR0_DATA             0x00000000ffffffffULL /* bits 31:0 */
1754
1755 #define IPP_DFIFO_WR1                   (FZC_IPP + 0x000f0UL)
1756 #define  IPP_DFIFO_WR1_DATA             0x00000000ffffffffULL /* bits 63:32 */
1757
1758 #define IPP_DFIFO_WR2                   (FZC_IPP + 0x000f8UL)
1759 #define  IPP_DFIFO_WR2_DATA             0x00000000ffffffffULL /* bits 95:64 */
1760
1761 #define IPP_DFIFO_WR3                   (FZC_IPP + 0x00100UL)
1762 #define  IPP_DFIFO_WR3_DATA             0x00000000ffffffffULL /* bits 127:96 */
1763
1764 #define IPP_DFIFO_WR4                   (FZC_IPP + 0x00108UL)
1765 #define  IPP_DFIFO_WR4_DATA             0x00000000ffffffffULL /* bits 145:128 */
1766
1767 #define IPP_DFIFO_RD_PTR                (FZC_IPP + 0x00110UL)
1768 #define  IPP_DFIFO_RD_PTR_PTR           0x0000000000000fffULL
1769
1770 #define IPP_DFIFO_WR_PTR                (FZC_IPP + 0x00118UL)
1771 #define  IPP_DFIFO_WR_PTR_PTR           0x0000000000000fffULL
1772
1773 #define IPP_SM                          (FZC_IPP + 0x00120UL)
1774 #define  IPP_SM_SM                      0x00000000ffffffffULL
1775
1776 #define IPP_CS_STAT                     (FZC_IPP + 0x00128UL)
1777 #define  IPP_CS_STAT_BCYC_CNT           0x00000000ff000000ULL
1778 #define  IPP_CS_STAT_IP_LEN             0x0000000000fff000ULL
1779 #define  IPP_CS_STAT_CS_FAIL            0x0000000000000800ULL
1780 #define  IPP_CS_STAT_TERM               0x0000000000000400ULL
1781 #define  IPP_CS_STAT_BAD_NUM            0x0000000000000200ULL
1782 #define  IPP_CS_STAT_CS_STATE           0x00000000000001ffULL
1783
1784 #define IPP_FFLP_CS_INFO                (FZC_IPP + 0x00130UL)
1785 #define  IPP_FFLP_CS_INFO_PKT_ID        0x0000000000003c00ULL
1786 #define  IPP_FFLP_CS_INFO_L4_PROTO      0x0000000000000300ULL
1787 #define  IPP_FFLP_CS_INFO_V4_HD_LEN     0x00000000000000f0ULL
1788 #define  IPP_FFLP_CS_INFO_L3_VER        0x000000000000000cULL
1789 #define  IPP_FFLP_CS_INFO_L2_OP         0x0000000000000003ULL
1790
1791 #define IPP_DBG_SEL                     (FZC_IPP + 0x00138UL)
1792 #define  IPP_DBG_SEL_SEL                0x000000000000000fULL
1793
1794 #define IPP_DFIFO_ECC_SYND              (FZC_IPP + 0x00140UL)
1795 #define  IPP_DFIFO_ECC_SYND_SYND        0x000000000000ffffULL
1796
1797 #define IPP_DFIFO_EOP_RD_PTR            (FZC_IPP + 0x00148UL)
1798 #define  IPP_DFIFO_EOP_RD_PTR_PTR       0x0000000000000fffULL
1799
1800 #define IPP_ECC_CTL                     (FZC_IPP + 0x00150UL)
1801 #define  IPP_ECC_CTL_DIS_DBL            0x0000000080000000ULL
1802 #define  IPP_ECC_CTL_COR_DBL            0x0000000000020000ULL
1803 #define  IPP_ECC_CTL_COR_SNG            0x0000000000010000ULL
1804 #define  IPP_ECC_CTL_COR_ALL            0x0000000000000400ULL
1805 #define  IPP_ECC_CTL_COR_1              0x0000000000000100ULL
1806 #define  IPP_ECC_CTL_COR_LST            0x0000000000000004ULL
1807 #define  IPP_ECC_CTL_COR_SND            0x0000000000000002ULL
1808 #define  IPP_ECC_CTL_COR_FSR            0x0000000000000001ULL
1809
1810 #define NIU_DFIFO_ENTRIES               1024
1811 #define ATLAS_P0_P1_DFIFO_ENTRIES       2048
1812 #define ATLAS_P2_P3_DFIFO_ENTRIES       1024
1813
1814 #define ZCP_CFIG                        (FZC_ZCP + 0x00000UL)
1815 #define  ZCP_CFIG_ZCP_32BIT_MODE        0x0000000001000000ULL
1816 #define  ZCP_CFIG_ZCP_DEBUG_SEL         0x0000000000ff0000ULL
1817 #define  ZCP_CFIG_DMA_TH                0x000000000000ffe0ULL
1818 #define  ZCP_CFIG_ECC_CHK_DIS           0x0000000000000010ULL
1819 #define  ZCP_CFIG_PAR_CHK_DIS           0x0000000000000008ULL
1820 #define  ZCP_CFIG_DIS_BUFF_RSP_IF       0x0000000000000004ULL
1821 #define  ZCP_CFIG_DIS_BUFF_REQ_IF       0x0000000000000002ULL
1822 #define  ZCP_CFIG_ZC_ENABLE             0x0000000000000001ULL
1823
1824 #define ZCP_INT_STAT                    (FZC_ZCP + 0x00008UL)
1825 #define  ZCP_INT_STAT_RRFIFO_UNDERRUN   0x0000000000008000ULL
1826 #define  ZCP_INT_STAT_RRFIFO_OVERRUN    0x0000000000004000ULL
1827 #define  ZCP_INT_STAT_RSPFIFO_UNCOR_ERR 0x0000000000001000ULL
1828 #define  ZCP_INT_STAT_BUFFER_OVERFLOW   0x0000000000000800ULL
1829 #define  ZCP_INT_STAT_STAT_TBL_PERR     0x0000000000000400ULL
1830 #define  ZCP_INT_STAT_DYN_TBL_PERR      0x0000000000000200ULL
1831 #define  ZCP_INT_STAT_BUF_TBL_PERR      0x0000000000000100ULL
1832 #define  ZCP_INT_STAT_TT_PROGRAM_ERR    0x0000000000000080ULL
1833 #define  ZCP_INT_STAT_RSP_TT_INDEX_ERR  0x0000000000000040ULL
1834 #define  ZCP_INT_STAT_SLV_TT_INDEX_ERR  0x0000000000000020ULL
1835 #define  ZCP_INT_STAT_ZCP_TT_INDEX_ERR  0x0000000000000010ULL
1836 #define  ZCP_INT_STAT_CFIFO_ECC3        0x0000000000000008ULL
1837 #define  ZCP_INT_STAT_CFIFO_ECC2        0x0000000000000004ULL
1838 #define  ZCP_INT_STAT_CFIFO_ECC1        0x0000000000000002ULL
1839 #define  ZCP_INT_STAT_CFIFO_ECC0        0x0000000000000001ULL
1840 #define  ZCP_INT_STAT_ALL               0x000000000000ffffULL
1841
1842 #define ZCP_INT_MASK                    (FZC_ZCP + 0x00010UL)
1843 #define  ZCP_INT_MASK_RRFIFO_UNDERRUN   0x0000000000008000ULL
1844 #define  ZCP_INT_MASK_RRFIFO_OVERRUN    0x0000000000004000ULL
1845 #define  ZCP_INT_MASK_LOJ               0x0000000000002000ULL
1846 #define  ZCP_INT_MASK_RSPFIFO_UNCOR_ERR 0x0000000000001000ULL
1847 #define  ZCP_INT_MASK_BUFFER_OVERFLOW   0x0000000000000800ULL
1848 #define  ZCP_INT_MASK_STAT_TBL_PERR     0x0000000000000400ULL
1849 #define  ZCP_INT_MASK_DYN_TBL_PERR      0x0000000000000200ULL
1850 #define  ZCP_INT_MASK_BUF_TBL_PERR      0x0000000000000100ULL
1851 #define  ZCP_INT_MASK_TT_PROGRAM_ERR    0x0000000000000080ULL
1852 #define  ZCP_INT_MASK_RSP_TT_INDEX_ERR  0x0000000000000040ULL
1853 #define  ZCP_INT_MASK_SLV_TT_INDEX_ERR  0x0000000000000020ULL
1854 #define  ZCP_INT_MASK_ZCP_TT_INDEX_ERR  0x0000000000000010ULL
1855 #define  ZCP_INT_MASK_CFIFO_ECC3        0x0000000000000008ULL
1856 #define  ZCP_INT_MASK_CFIFO_ECC2        0x0000000000000004ULL
1857 #define  ZCP_INT_MASK_CFIFO_ECC1        0x0000000000000002ULL
1858 #define  ZCP_INT_MASK_CFIFO_ECC0        0x0000000000000001ULL
1859 #define  ZCP_INT_MASK_ALL               0x000000000000ffffULL
1860
1861 #define BAM4BUF                         (FZC_ZCP + 0x00018UL)
1862 #define  BAM4BUF_LOJ                    0x0000000080000000ULL
1863 #define  BAM4BUF_EN_CK                  0x0000000040000000ULL
1864 #define  BAM4BUF_IDX_END0               0x000000003ff00000ULL
1865 #define  BAM4BUF_IDX_ST0                0x00000000000ffc00ULL
1866 #define  BAM4BUF_OFFSET0                0x00000000000003ffULL
1867
1868 #define BAM8BUF                         (FZC_ZCP + 0x00020UL)
1869 #define  BAM8BUF_LOJ                    0x0000000080000000ULL
1870 #define  BAM8BUF_EN_CK                  0x0000000040000000ULL
1871 #define  BAM8BUF_IDX_END1               0x000000003ff00000ULL
1872 #define  BAM8BUF_IDX_ST1                0x00000000000ffc00ULL
1873 #define  BAM8BUF_OFFSET1                0x00000000000003ffULL
1874
1875 #define BAM16BUF                        (FZC_ZCP + 0x00028UL)
1876 #define  BAM16BUF_LOJ                   0x0000000080000000ULL
1877 #define  BAM16BUF_EN_CK                 0x0000000040000000ULL
1878 #define  BAM16BUF_IDX_END2              0x000000003ff00000ULL
1879 #define  BAM16BUF_IDX_ST2               0x00000000000ffc00ULL
1880 #define  BAM16BUF_OFFSET2               0x00000000000003ffULL
1881
1882 #define BAM32BUF                        (FZC_ZCP + 0x00030UL)
1883 #define  BAM32BUF_LOJ                   0x0000000080000000ULL
1884 #define  BAM32BUF_EN_CK                 0x0000000040000000ULL
1885 #define  BAM32BUF_IDX_END3              0x000000003ff00000ULL
1886 #define  BAM32BUF_IDX_ST3               0x00000000000ffc00ULL
1887 #define  BAM32BUF_OFFSET3               0x00000000000003ffULL
1888
1889 #define DST4BUF                         (FZC_ZCP + 0x00038UL)
1890 #define  DST4BUF_DS_OFFSET0             0x00000000000003ffULL
1891
1892 #define DST8BUF                         (FZC_ZCP + 0x00040UL)
1893 #define  DST8BUF_DS_OFFSET1             0x00000000000003ffULL
1894
1895 #define DST16BUF                        (FZC_ZCP + 0x00048UL)
1896 #define  DST16BUF_DS_OFFSET2            0x00000000000003ffULL
1897
1898 #define DST32BUF                        (FZC_ZCP + 0x00050UL)
1899 #define  DST32BUF_DS_OFFSET3            0x00000000000003ffULL
1900
1901 #define ZCP_RAM_DATA0                   (FZC_ZCP + 0x00058UL)
1902 #define  ZCP_RAM_DATA0_DAT0             0x00000000ffffffffULL
1903
1904 #define ZCP_RAM_DATA1                   (FZC_ZCP + 0x00060UL)
1905 #define  ZCP_RAM_DAT10_DAT1             0x00000000ffffffffULL
1906
1907 #define ZCP_RAM_DATA2                   (FZC_ZCP + 0x00068UL)
1908 #define  ZCP_RAM_DATA2_DAT2             0x00000000ffffffffULL
1909
1910 #define ZCP_RAM_DATA3                   (FZC_ZCP + 0x00070UL)
1911 #define  ZCP_RAM_DATA3_DAT3             0x00000000ffffffffULL
1912
1913 #define ZCP_RAM_DATA4                   (FZC_ZCP + 0x00078UL)
1914 #define  ZCP_RAM_DATA4_DAT4             0x00000000000000ffULL
1915
1916 #define ZCP_RAM_BE                      (FZC_ZCP + 0x00080UL)
1917 #define  ZCP_RAM_BE_VAL                 0x000000000001ffffULL
1918
1919 #define ZCP_RAM_ACC                     (FZC_ZCP + 0x00088UL)
1920 #define  ZCP_RAM_ACC_BUSY               0x0000000080000000ULL
1921 #define  ZCP_RAM_ACC_READ               0x0000000040000000ULL
1922 #define  ZCP_RAM_ACC_WRITE              0x0000000000000000ULL
1923 #define  ZCP_RAM_ACC_LOJ                0x0000000020000000ULL
1924 #define  ZCP_RAM_ACC_ZFCID              0x000000001ffe0000ULL
1925 #define  ZCP_RAM_ACC_ZFCID_SHIFT        17
1926 #define  ZCP_RAM_ACC_RAM_SEL            0x000000000001f000ULL
1927 #define  ZCP_RAM_ACC_RAM_SEL_SHIFT      12
1928 #define  ZCP_RAM_ACC_CFIFOADDR          0x0000000000000fffULL
1929 #define  ZCP_RAM_ACC_CFIFOADDR_SHIFT    0
1930
1931 #define ZCP_RAM_SEL_BAM(INDEX)          (0x00 + (INDEX))
1932 #define ZCP_RAM_SEL_TT_STATIC           0x08
1933 #define ZCP_RAM_SEL_TT_DYNAMIC          0x09
1934 #define ZCP_RAM_SEL_CFIFO(PORT)         (0x10 + (PORT))
1935
1936 #define NIU_CFIFO_ENTRIES               1024
1937 #define ATLAS_P0_P1_CFIFO_ENTRIES       2048
1938 #define ATLAS_P2_P3_CFIFO_ENTRIES       1024
1939
1940 #define CHK_BIT_DATA                    (FZC_ZCP + 0x00090UL)
1941 #define  CHK_BIT_DATA_DATA              0x000000000000ffffULL
1942
1943 #define RESET_CFIFO                     (FZC_ZCP + 0x00098UL)
1944 #define  RESET_CFIFO_RST(PORT)          (0x1 << (PORT))
1945
1946 #define CFIFO_ECC(PORT)                 (FZC_ZCP + 0x000a0UL + (PORT) * 8UL)
1947 #define  CFIFO_ECC_DIS_DBLBIT_ERR       0x0000000080000000ULL
1948 #define  CFIFO_ECC_DBLBIT_ERR           0x0000000000020000ULL
1949 #define  CFIFO_ECC_SINGLEBIT_ERR        0x0000000000010000ULL
1950 #define  CFIFO_ECC_ALL_PKT              0x0000000000000400ULL
1951 #define  CFIFO_ECC_LAST_LINE            0x0000000000000004ULL
1952 #define  CFIFO_ECC_2ND_LINE             0x0000000000000002ULL
1953 #define  CFIFO_ECC_1ST_LINE             0x0000000000000001ULL
1954
1955 #define ZCP_TRAINING_VECTOR             (FZC_ZCP + 0x000c0UL)
1956 #define  ZCP_TRAINING_VECTOR_VECTOR     0x00000000ffffffffULL
1957
1958 #define ZCP_STATE_MACHINE               (FZC_ZCP + 0x000c8UL)
1959 #define  ZCP_STATE_MACHINE_SM           0x00000000ffffffffULL
1960
1961 /* Same bits as ZCP_INT_STAT */
1962 #define ZCP_INT_STAT_TEST               (FZC_ZCP + 0x00108UL)
1963
1964 #define RXDMA_CFIG1(IDX)                (DMC + 0x00000UL + (IDX) * 0x200UL)
1965 #define  RXDMA_CFIG1_EN                 0x0000000080000000ULL
1966 #define  RXDMA_CFIG1_RST                0x0000000040000000ULL
1967 #define  RXDMA_CFIG1_QST                0x0000000020000000ULL
1968 #define  RXDMA_CFIG1_MBADDR_H           0x0000000000000fffULL /* mboxaddr 43:32 */
1969
1970 #define RXDMA_CFIG2(IDX)                (DMC + 0x00008UL + (IDX) * 0x200UL)
1971 #define  RXDMA_CFIG2_MBADDR_L           0x00000000ffffffc0ULL /* mboxaddr 31:6 */
1972 #define  RXDMA_CFIG2_OFFSET             0x0000000000000006ULL
1973 #define  RXDMA_CFIG2_OFFSET_SHIFT       1
1974 #define  RXDMA_CFIG2_FULL_HDR           0x0000000000000001ULL
1975
1976 #define RBR_CFIG_A(IDX)                 (DMC + 0x00010UL + (IDX) * 0x200UL)
1977 #define  RBR_CFIG_A_LEN                 0xffff000000000000ULL
1978 #define  RBR_CFIG_A_LEN_SHIFT           48
1979 #define  RBR_CFIG_A_STADDR_BASE         0x00000ffffffc0000ULL
1980 #define  RBR_CFIG_A_STADDR              0x000000000003ffc0ULL
1981
1982 #define RBR_CFIG_B(IDX)                 (DMC + 0x00018UL + (IDX) * 0x200UL)
1983 #define  RBR_CFIG_B_BLKSIZE             0x0000000003000000ULL
1984 #define  RBR_CFIG_B_BLKSIZE_SHIFT       24
1985 #define  RBR_CFIG_B_VLD2                0x0000000000800000ULL
1986 #define  RBR_CFIG_B_BUFSZ2              0x0000000000030000ULL
1987 #define  RBR_CFIG_B_BUFSZ2_SHIFT        16
1988 #define  RBR_CFIG_B_VLD1                0x0000000000008000ULL
1989 #define  RBR_CFIG_B_BUFSZ1              0x0000000000000300ULL
1990 #define  RBR_CFIG_B_BUFSZ1_SHIFT        8
1991 #define  RBR_CFIG_B_VLD0                0x0000000000000080ULL
1992 #define  RBR_CFIG_B_BUFSZ0              0x0000000000000003ULL
1993 #define  RBR_CFIG_B_BUFSZ0_SHIFT        0
1994
1995 #define RBR_BLKSIZE_4K                  0x0
1996 #define RBR_BLKSIZE_8K                  0x1
1997 #define RBR_BLKSIZE_16K                 0x2
1998 #define RBR_BLKSIZE_32K                 0x3
1999 #define RBR_BUFSZ2_2K                   0x0
2000 #define RBR_BUFSZ2_4K                   0x1
2001 #define RBR_BUFSZ2_8K                   0x2
2002 #define RBR_BUFSZ2_16K                  0x3
2003 #define RBR_BUFSZ1_1K                   0x0
2004 #define RBR_BUFSZ1_2K                   0x1
2005 #define RBR_BUFSZ1_4K                   0x2
2006 #define RBR_BUFSZ1_8K                   0x3
2007 #define RBR_BUFSZ0_256                  0x0
2008 #define RBR_BUFSZ0_512                  0x1
2009 #define RBR_BUFSZ0_1K                   0x2
2010 #define RBR_BUFSZ0_2K                   0x3
2011
2012 #define RBR_KICK(IDX)                   (DMC + 0x00020UL + (IDX) * 0x200UL)
2013 #define  RBR_KICK_BKADD                 0x000000000000ffffULL
2014
2015 #define RBR_STAT(IDX)                   (DMC + 0x00028UL + (IDX) * 0x200UL)
2016 #define  RBR_STAT_QLEN                  0x000000000000ffffULL
2017
2018 #define RBR_HDH(IDX)                    (DMC + 0x00030UL + (IDX) * 0x200UL)
2019 #define  RBR_HDH_HEAD_H                 0x0000000000000fffULL
2020
2021 #define RBR_HDL(IDX)                    (DMC + 0x00038UL + (IDX) * 0x200UL)
2022 #define  RBR_HDL_HEAD_L                 0x00000000fffffffcULL
2023
2024 #define RCRCFIG_A(IDX)                  (DMC + 0x00040UL + (IDX) * 0x200UL)
2025 #define  RCRCFIG_A_LEN                  0xffff000000000000ULL
2026 #define  RCRCFIG_A_LEN_SHIFT            48
2027 #define  RCRCFIG_A_STADDR_BASE          0x00000ffffff80000ULL
2028 #define  RCRCFIG_A_STADDR               0x000000000007ffc0ULL
2029
2030 #define RCRCFIG_B(IDX)                  (DMC + 0x00048UL + (IDX) * 0x200UL)
2031 #define  RCRCFIG_B_PTHRES               0x00000000ffff0000ULL
2032 #define  RCRCFIG_B_PTHRES_SHIFT         16
2033 #define  RCRCFIG_B_ENTOUT               0x0000000000008000ULL
2034 #define  RCRCFIG_B_TIMEOUT              0x000000000000003fULL
2035 #define  RCRCFIG_B_TIMEOUT_SHIFT        0
2036
2037 #define RCRSTAT_A(IDX)                  (DMC + 0x00050UL + (IDX) * 0x200UL)
2038 #define  RCRSTAT_A_QLEN                 0x000000000000ffffULL
2039
2040 #define RCRSTAT_B(IDX)                  (DMC + 0x00058UL + (IDX) * 0x200UL)
2041 #define  RCRSTAT_B_TIPTR_H              0x0000000000000fffULL
2042
2043 #define RCRSTAT_C(IDX)                  (DMC + 0x00060UL + (IDX) * 0x200UL)
2044 #define  RCRSTAT_C_TIPTR_L              0x00000000fffffff8ULL
2045
2046 #define RX_DMA_CTL_STAT(IDX)            (DMC + 0x00070UL + (IDX) * 0x200UL)
2047 #define  RX_DMA_CTL_STAT_RBR_TMOUT      0x0020000000000000ULL
2048 #define  RX_DMA_CTL_STAT_RSP_CNT_ERR    0x0010000000000000ULL
2049 #define  RX_DMA_CTL_STAT_BYTE_EN_BUS    0x0008000000000000ULL
2050 #define  RX_DMA_CTL_STAT_RSP_DAT_ERR    0x0004000000000000ULL
2051 #define  RX_DMA_CTL_STAT_RCR_ACK_ERR    0x0002000000000000ULL
2052 #define  RX_DMA_CTL_STAT_DC_FIFO_ERR    0x0001000000000000ULL
2053 #define  RX_DMA_CTL_STAT_MEX            0x0000800000000000ULL
2054 #define  RX_DMA_CTL_STAT_RCRTHRES       0x0000400000000000ULL
2055 #define  RX_DMA_CTL_STAT_RCRTO          0x0000200000000000ULL
2056 #define  RX_DMA_CTL_STAT_RCR_SHA_PAR    0x0000100000000000ULL
2057 #define  RX_DMA_CTL_STAT_RBR_PRE_PAR    0x0000080000000000ULL
2058 #define  RX_DMA_CTL_STAT_PORT_DROP_PKT  0x0000040000000000ULL
2059 #define  RX_DMA_CTL_STAT_WRED_DROP      0x0000020000000000ULL
2060 #define  RX_DMA_CTL_STAT_RBR_PRE_EMTY   0x0000010000000000ULL
2061 #define  RX_DMA_CTL_STAT_RCRSHADOW_FULL 0x0000008000000000ULL
2062 #define  RX_DMA_CTL_STAT_CONFIG_ERR     0x0000004000000000ULL
2063 #define  RX_DMA_CTL_STAT_RCRINCON       0x0000002000000000ULL
2064 #define  RX_DMA_CTL_STAT_RCRFULL        0x0000001000000000ULL
2065 #define  RX_DMA_CTL_STAT_RBR_EMPTY      0x0000000800000000ULL
2066 #define  RX_DMA_CTL_STAT_RBRFULL        0x0000000400000000ULL
2067 #define  RX_DMA_CTL_STAT_RBRLOGPAGE     0x0000000200000000ULL
2068 #define  RX_DMA_CTL_STAT_CFIGLOGPAGE    0x0000000100000000ULL
2069 #define  RX_DMA_CTL_STAT_PTRREAD        0x00000000ffff0000ULL
2070 #define  RX_DMA_CTL_STAT_PTRREAD_SHIFT  16
2071 #define  RX_DMA_CTL_STAT_PKTREAD        0x000000000000ffffULL
2072 #define  RX_DMA_CTL_STAT_PKTREAD_SHIFT  0
2073
2074 #define  RX_DMA_CTL_STAT_CHAN_FATAL     (RX_DMA_CTL_STAT_RBR_TMOUT | \
2075                                          RX_DMA_CTL_STAT_RSP_CNT_ERR | \
2076                                          RX_DMA_CTL_STAT_BYTE_EN_BUS | \
2077                                          RX_DMA_CTL_STAT_RSP_DAT_ERR | \
2078                                          RX_DMA_CTL_STAT_RCR_ACK_ERR | \
2079                                          RX_DMA_CTL_STAT_RCR_SHA_PAR | \
2080                                          RX_DMA_CTL_STAT_RBR_PRE_PAR | \
2081                                          RX_DMA_CTL_STAT_CONFIG_ERR | \
2082                                          RX_DMA_CTL_STAT_RCRINCON | \
2083                                          RX_DMA_CTL_STAT_RCRFULL | \
2084                                          RX_DMA_CTL_STAT_RBRFULL | \
2085                                          RX_DMA_CTL_STAT_RBRLOGPAGE | \
2086                                          RX_DMA_CTL_STAT_CFIGLOGPAGE)
2087
2088 #define RX_DMA_CTL_STAT_PORT_FATAL      (RX_DMA_CTL_STAT_DC_FIFO_ERR)
2089
2090 #define RX_DMA_CTL_WRITE_CLEAR_ERRS     (RX_DMA_CTL_STAT_RBR_EMPTY | \
2091                                          RX_DMA_CTL_STAT_RCRSHADOW_FULL | \
2092                                          RX_DMA_CTL_STAT_RBR_PRE_EMTY | \
2093                                          RX_DMA_CTL_STAT_WRED_DROP | \
2094                                          RX_DMA_CTL_STAT_PORT_DROP_PKT | \
2095                                          RX_DMA_CTL_STAT_RCRTO | \
2096                                          RX_DMA_CTL_STAT_RCRTHRES | \
2097                                          RX_DMA_CTL_STAT_DC_FIFO_ERR)
2098
2099 #define RCR_FLSH(IDX)                   (DMC + 0x00078UL + (IDX) * 0x200UL)
2100 #define  RCR_FLSH_FLSH                  0x0000000000000001ULL
2101
2102 #define RXMISC(IDX)                     (DMC + 0x00090UL + (IDX) * 0x200UL)
2103 #define  RXMISC_OFLOW                   0x0000000000010000ULL
2104 #define  RXMISC_COUNT                   0x000000000000ffffULL
2105
2106 #define RX_DMA_CTL_STAT_DBG(IDX)        (DMC + 0x00098UL + (IDX) * 0x200UL)
2107 #define  RX_DMA_CTL_STAT_DBG_RBR_TMOUT          0x0020000000000000ULL
2108 #define  RX_DMA_CTL_STAT_DBG_RSP_CNT_ERR        0x0010000000000000ULL
2109 #define  RX_DMA_CTL_STAT_DBG_BYTE_EN_BUS        0x0008000000000000ULL
2110 #define  RX_DMA_CTL_STAT_DBG_RSP_DAT_ERR        0x0004000000000000ULL
2111 #define  RX_DMA_CTL_STAT_DBG_RCR_ACK_ERR        0x0002000000000000ULL
2112 #define  RX_DMA_CTL_STAT_DBG_DC_FIFO_ERR        0x0001000000000000ULL
2113 #define  RX_DMA_CTL_STAT_DBG_MEX                0x0000800000000000ULL
2114 #define  RX_DMA_CTL_STAT_DBG_RCRTHRES           0x0000400000000000ULL
2115 #define  RX_DMA_CTL_STAT_DBG_RCRTO              0x0000200000000000ULL
2116 #define  RX_DMA_CTL_STAT_DBG_RCR_SHA_PAR        0x0000100000000000ULL
2117 #define  RX_DMA_CTL_STAT_DBG_RBR_PRE_PAR        0x0000080000000000ULL
2118 #define  RX_DMA_CTL_STAT_DBG_PORT_DROP_PKT      0x0000040000000000ULL
2119 #define  RX_DMA_CTL_STAT_DBG_WRED_DROP          0x0000020000000000ULL
2120 #define  RX_DMA_CTL_STAT_DBG_RBR_PRE_EMTY       0x0000010000000000ULL
2121 #define  RX_DMA_CTL_STAT_DBG_RCRSHADOW_FULL     0x0000008000000000ULL
2122 #define  RX_DMA_CTL_STAT_DBG_CONFIG_ERR         0x0000004000000000ULL
2123 #define  RX_DMA_CTL_STAT_DBG_RCRINCON           0x0000002000000000ULL
2124 #define  RX_DMA_CTL_STAT_DBG_RCRFULL            0x0000001000000000ULL
2125 #define  RX_DMA_CTL_STAT_DBG_RBR_EMPTY          0x0000000800000000ULL
2126 #define  RX_DMA_CTL_STAT_DBG_RBRFULL            0x0000000400000000ULL
2127 #define  RX_DMA_CTL_STAT_DBG_RBRLOGPAGE         0x0000000200000000ULL
2128 #define  RX_DMA_CTL_STAT_DBG_CFIGLOGPAGE        0x0000000100000000ULL
2129 #define  RX_DMA_CTL_STAT_DBG_PTRREAD            0x00000000ffff0000ULL
2130 #define  RX_DMA_CTL_STAT_DBG_PKTREAD            0x000000000000ffffULL
2131
2132 #define RX_DMA_ENT_MSK(IDX)             (DMC + 0x00068UL + (IDX) * 0x200UL)
2133 #define  RX_DMA_ENT_MSK_RBR_TMOUT       0x0000000000200000ULL
2134 #define  RX_DMA_ENT_MSK_RSP_CNT_ERR     0x0000000000100000ULL
2135 #define  RX_DMA_ENT_MSK_BYTE_EN_BUS     0x0000000000080000ULL
2136 #define  RX_DMA_ENT_MSK_RSP_DAT_ERR     0x0000000000040000ULL
2137 #define  RX_DMA_ENT_MSK_RCR_ACK_ERR     0x0000000000020000ULL
2138 #define  RX_DMA_ENT_MSK_DC_FIFO_ERR     0x0000000000010000ULL
2139 #define  RX_DMA_ENT_MSK_RCRTHRES        0x0000000000004000ULL
2140 #define  RX_DMA_ENT_MSK_RCRTO           0x0000000000002000ULL
2141 #define  RX_DMA_ENT_MSK_RCR_SHA_PAR     0x0000000000001000ULL
2142 #define  RX_DMA_ENT_MSK_RBR_PRE_PAR     0x0000000000000800ULL
2143 #define  RX_DMA_ENT_MSK_PORT_DROP_PKT   0x0000000000000400ULL
2144 #define  RX_DMA_ENT_MSK_WRED_DROP       0x0000000000000200ULL
2145 #define  RX_DMA_ENT_MSK_RBR_PRE_EMTY    0x0000000000000100ULL
2146 #define  RX_DMA_ENT_MSK_RCR_SHADOW_FULL 0x0000000000000080ULL
2147 #define  RX_DMA_ENT_MSK_CONFIG_ERR      0x0000000000000040ULL
2148 #define  RX_DMA_ENT_MSK_RCRINCON        0x0000000000000020ULL
2149 #define  RX_DMA_ENT_MSK_RCRFULL         0x0000000000000010ULL
2150 #define  RX_DMA_ENT_MSK_RBR_EMPTY       0x0000000000000008ULL
2151 #define  RX_DMA_ENT_MSK_RBRFULL         0x0000000000000004ULL
2152 #define  RX_DMA_ENT_MSK_RBRLOGPAGE      0x0000000000000002ULL
2153 #define  RX_DMA_ENT_MSK_CFIGLOGPAGE     0x0000000000000001ULL
2154 #define  RX_DMA_ENT_MSK_ALL             0x00000000003f7fffULL
2155
2156 #define TX_RNG_CFIG(IDX)                (DMC + 0x40000UL + (IDX) * 0x200UL)
2157 #define  TX_RNG_CFIG_LEN                0x1fff000000000000ULL
2158 #define  TX_RNG_CFIG_LEN_SHIFT          48
2159 #define  TX_RNG_CFIG_STADDR_BASE        0x00000ffffff80000ULL
2160 #define  TX_RNG_CFIG_STADDR             0x000000000007ffc0ULL
2161
2162 #define TX_RING_HDL(IDX)                (DMC + 0x40010UL + (IDX) * 0x200UL)
2163 #define  TX_RING_HDL_WRAP               0x0000000000080000ULL
2164 #define  TX_RING_HDL_HEAD               0x000000000007fff8ULL
2165 #define  TX_RING_HDL_HEAD_SHIFT         3
2166
2167 #define TX_RING_KICK(IDX)               (DMC + 0x40018UL + (IDX) * 0x200UL)
2168 #define  TX_RING_KICK_WRAP              0x0000000000080000ULL
2169 #define  TX_RING_KICK_TAIL              0x000000000007fff8ULL
2170
2171 #define TX_ENT_MSK(IDX)                 (DMC + 0x40020UL + (IDX) * 0x200UL)
2172 #define  TX_ENT_MSK_MK                  0x0000000000008000ULL
2173 #define  TX_ENT_MSK_MBOX_ERR            0x0000000000000080ULL
2174 #define  TX_ENT_MSK_PKT_SIZE_ERR        0x0000000000000040ULL
2175 #define  TX_ENT_MSK_TX_RING_OFLOW       0x0000000000000020ULL
2176 #define  TX_ENT_MSK_PREF_BUF_ECC_ERR    0x0000000000000010ULL
2177 #define  TX_ENT_MSK_NACK_PREF           0x0000000000000008ULL
2178 #define  TX_ENT_MSK_NACK_PKT_RD         0x0000000000000004ULL
2179 #define  TX_ENT_MSK_CONF_PART_ERR       0x0000000000000002ULL
2180 #define  TX_ENT_MSK_PKT_PRT_ERR         0x0000000000000001ULL
2181
2182 #define TX_CS(IDX)                      (DMC + 0x40028UL + (IDX)*0x200UL)
2183 #define  TX_CS_PKT_CNT                  0x0fff000000000000ULL
2184 #define  TX_CS_PKT_CNT_SHIFT            48
2185 #define  TX_CS_LASTMARK                 0x00000fff00000000ULL
2186 #define  TX_CS_LASTMARK_SHIFT           32
2187 #define  TX_CS_RST                      0x0000000080000000ULL
2188 #define  TX_CS_RST_STATE                0x0000000040000000ULL
2189 #define  TX_CS_MB                       0x0000000020000000ULL
2190 #define  TX_CS_STOP_N_GO                0x0000000010000000ULL
2191 #define  TX_CS_SNG_STATE                0x0000000008000000ULL
2192 #define  TX_CS_MK                       0x0000000000008000ULL
2193 #define  TX_CS_MMK                      0x0000000000004000ULL
2194 #define  TX_CS_MBOX_ERR                 0x0000000000000080ULL
2195 #define  TX_CS_PKT_SIZE_ERR             0x0000000000000040ULL
2196 #define  TX_CS_TX_RING_OFLOW            0x0000000000000020ULL
2197 #define  TX_CS_PREF_BUF_PAR_ERR         0x0000000000000010ULL
2198 #define  TX_CS_NACK_PREF                0x0000000000000008ULL
2199 #define  TX_CS_NACK_PKT_RD              0x0000000000000004ULL
2200 #define  TX_CS_CONF_PART_ERR            0x0000000000000002ULL
2201 #define  TX_CS_PKT_PRT_ERR              0x0000000000000001ULL
2202
2203 #define TXDMA_MBH(IDX)                  (DMC + 0x40030UL + (IDX) * 0x200UL)
2204 #define  TXDMA_MBH_MBADDR               0x0000000000000fffULL
2205
2206 #define TXDMA_MBL(IDX)                  (DMC + 0x40038UL + (IDX) * 0x200UL)
2207 #define  TXDMA_MBL_MBADDR               0x00000000ffffffc0ULL
2208
2209 #define TX_DMA_PRE_ST(IDX)              (DMC + 0x40040UL + (IDX) * 0x200UL)
2210 #define  TX_DMA_PRE_ST_SHADOW_HD        0x000000000007ffffULL
2211
2212 #define TX_RNG_ERR_LOGH(IDX)            (DMC + 0x40048UL + (IDX) * 0x200UL)
2213 #define  TX_RNG_ERR_LOGH_ERR            0x0000000080000000ULL
2214 #define  TX_RNG_ERR_LOGH_MERR           0x0000000040000000ULL
2215 #define  TX_RNG_ERR_LOGH_ERRCODE        0x0000000038000000ULL
2216 #define  TX_RNG_ERR_LOGH_ERRADDR        0x0000000000000fffULL
2217
2218 #define TX_RNG_ERR_LOGL(IDX)            (DMC + 0x40050UL + (IDX) * 0x200UL)
2219 #define  TX_RNG_ERR_LOGL_ERRADDR        0x00000000ffffffffULL
2220
2221 #define TDMC_INTR_DBG(IDX)              (DMC + 0x40060UL + (IDX) * 0x200UL)
2222 #define  TDMC_INTR_DBG_MK               0x0000000000008000ULL
2223 #define  TDMC_INTR_DBG_MBOX_ERR         0x0000000000000080ULL
2224 #define  TDMC_INTR_DBG_PKT_SIZE_ERR     0x0000000000000040ULL
2225 #define  TDMC_INTR_DBG_TX_RING_OFLOW    0x0000000000000020ULL
2226 #define  TDMC_INTR_DBG_PREF_BUF_PAR_ERR 0x0000000000000010ULL
2227 #define  TDMC_INTR_DBG_NACK_PREF        0x0000000000000008ULL
2228 #define  TDMC_INTR_DBG_NACK_PKT_RD      0x0000000000000004ULL
2229 #define  TDMC_INTR_DBG_CONF_PART_ERR    0x0000000000000002ULL
2230 #define  TDMC_INTR_DBG_PKT_PART_ERR     0x0000000000000001ULL
2231
2232 #define TX_CS_DBG(IDX)                  (DMC + 0x40068UL + (IDX) * 0x200UL)
2233 #define  TX_CS_DBG_PKT_CNT              0x0fff000000000000ULL
2234
2235 #define TDMC_INJ_PAR_ERR(IDX)           (DMC + 0x45040UL + (IDX) * 0x200UL)
2236 #define  TDMC_INJ_PAR_ERR_VAL           0x000000000000ffffULL
2237
2238 #define TDMC_DBG_SEL(IDX)               (DMC + 0x45080UL + (IDX) * 0x200UL)
2239 #define  TDMC_DBG_SEL_DBG_SEL           0x000000000000003fULL
2240
2241 #define TDMC_TRAINING_VECTOR(IDX)       (DMC + 0x45088UL + (IDX) * 0x200UL)
2242 #define  TDMC_TRAINING_VECTOR_VEC       0x00000000ffffffffULL
2243
2244 #define TXC_DMA_MAX(CHAN)               (FZC_TXC + 0x00000UL + (CHAN)*0x1000UL)
2245 #define TXC_DMA_MAX_LEN(CHAN)           (FZC_TXC + 0x00008UL + (CHAN)*0x1000UL)
2246
2247 #define TXC_CONTROL                     (FZC_TXC + 0x20000UL)
2248 #define  TXC_CONTROL_ENABLE             0x0000000000000010ULL
2249 #define  TXC_CONTROL_PORT_ENABLE(X)     (1 << (X))
2250
2251 #define TXC_TRAINING_VEC                (FZC_TXC + 0x20008UL)
2252 #define  TXC_TRAINING_VEC_MASK          0x00000000ffffffffULL
2253
2254 #define TXC_DEBUG                       (FZC_TXC + 0x20010UL)
2255 #define  TXC_DEBUG_SELECT               0x000000000000003fULL
2256
2257 #define TXC_MAX_REORDER                 (FZC_TXC + 0x20018UL)
2258 #define  TXC_MAX_REORDER_PORT3          0x000000000f000000ULL
2259 #define  TXC_MAX_REORDER_PORT2          0x00000000000f0000ULL
2260 #define  TXC_MAX_REORDER_PORT1          0x0000000000000f00ULL
2261 #define  TXC_MAX_REORDER_PORT0          0x000000000000000fULL
2262
2263 #define TXC_PORT_CTL(PORT)              (FZC_TXC + 0x20020UL + (PORT)*0x100UL)
2264 #define  TXC_PORT_CTL_CLR_ALL_STAT      0x0000000000000001ULL
2265
2266 #define TXC_PKT_STUFFED(PORT)           (FZC_TXC + 0x20030UL + (PORT)*0x100UL)
2267 #define  TXC_PKT_STUFFED_PP_REORDER     0x00000000ffff0000ULL
2268 #define  TXC_PKT_STUFFED_PP_PACKETASSY  0x000000000000ffffULL
2269
2270 #define TXC_PKT_XMIT(PORT)              (FZC_TXC + 0x20038UL + (PORT)*0x100UL)
2271 #define  TXC_PKT_XMIT_BYTES             0x00000000ffff0000ULL
2272 #define  TXC_PKT_XMIT_PKTS              0x000000000000ffffULL
2273
2274 #define TXC_ROECC_CTL(PORT)             (FZC_TXC + 0x20040UL + (PORT)*0x100UL)
2275 #define  TXC_ROECC_CTL_DISABLE_UE       0x0000000080000000ULL
2276 #define  TXC_ROECC_CTL_DBL_BIT_ERR      0x0000000000020000ULL
2277 #define  TXC_ROECC_CTL_SNGL_BIT_ERR     0x0000000000010000ULL
2278 #define  TXC_ROECC_CTL_ALL_PKTS         0x0000000000000400ULL
2279 #define  TXC_ROECC_CTL_ALT_PKTS         0x0000000000000200ULL
2280 #define  TXC_ROECC_CTL_ONE_PKT_ONLY     0x0000000000000100ULL
2281 #define  TXC_ROECC_CTL_LST_PKT_LINE     0x0000000000000004ULL
2282 #define  TXC_ROECC_CTL_2ND_PKT_LINE     0x0000000000000002ULL
2283 #define  TXC_ROECC_CTL_1ST_PKT_LINE     0x0000000000000001ULL
2284
2285 #define TXC_ROECC_ST(PORT)              (FZC_TXC + 0x20048UL + (PORT)*0x100UL)
2286 #define  TXC_ROECC_CLR_ST               0x0000000080000000ULL
2287 #define  TXC_ROECC_CE                   0x0000000000020000ULL
2288 #define  TXC_ROECC_UE                   0x0000000000010000ULL
2289 #define  TXC_ROECC_ST_ECC_ADDR          0x00000000000003ffULL
2290
2291 #define TXC_RO_DATA0(PORT)              (FZC_TXC + 0x20050UL + (PORT)*0x100UL)
2292 #define  TXC_RO_DATA0_DATA0             0x00000000ffffffffULL /* bits 31:0 */
2293
2294 #define TXC_RO_DATA1(PORT)              (FZC_TXC + 0x20058UL + (PORT)*0x100UL)
2295 #define  TXC_RO_DATA1_DATA1             0x00000000ffffffffULL /* bits 63:32 */
2296
2297 #define TXC_RO_DATA2(PORT)              (FZC_TXC + 0x20060UL + (PORT)*0x100UL)
2298 #define  TXC_RO_DATA2_DATA2             0x00000000ffffffffULL /* bits 95:64 */
2299
2300 #define TXC_RO_DATA3(PORT)              (FZC_TXC + 0x20068UL + (PORT)*0x100UL)
2301 #define  TXC_RO_DATA3_DATA3             0x00000000ffffffffULL /* bits 127:96 */
2302
2303 #define TXC_RO_DATA4(PORT)              (FZC_TXC + 0x20070UL + (PORT)*0x100UL)
2304 #define  TXC_RO_DATA4_DATA4             0x0000000000ffffffULL /* bits 151:128 */
2305
2306 #define TXC_SFECC_CTL(PORT)             (FZC_TXC + 0x20078UL + (PORT)*0x100UL)
2307 #define  TXC_SFECC_CTL_DISABLE_UE       0x0000000080000000ULL
2308 #define  TXC_SFECC_CTL_DBL_BIT_ERR      0x0000000000020000ULL
2309 #define  TXC_SFECC_CTL_SNGL_BIT_ERR     0x0000000000010000ULL
2310 #define  TXC_SFECC_CTL_ALL_PKTS         0x0000000000000400ULL
2311 #define  TXC_SFECC_CTL_ALT_PKTS         0x0000000000000200ULL
2312 #define  TXC_SFECC_CTL_ONE_PKT_ONLY     0x0000000000000100ULL
2313 #define  TXC_SFECC_CTL_LST_PKT_LINE     0x0000000000000004ULL
2314 #define  TXC_SFECC_CTL_2ND_PKT_LINE     0x0000000000000002ULL
2315 #define  TXC_SFECC_CTL_1ST_PKT_LINE     0x0000000000000001ULL
2316
2317 #define TXC_SFECC_ST(PORT)              (FZC_TXC + 0x20080UL + (PORT)*0x100UL)
2318 #define  TXC_SFECC_ST_CLR_ST            0x0000000080000000ULL
2319 #define  TXC_SFECC_ST_CE                0x0000000000020000ULL
2320 #define  TXC_SFECC_ST_UE                0x0000000000010000ULL
2321 #define  TXC_SFECC_ST_ECC_ADDR          0x00000000000003ffULL
2322
2323 #define TXC_SF_DATA0(PORT)              (FZC_TXC + 0x20088UL + (PORT)*0x100UL)
2324 #define  TXC_SF_DATA0_DATA0             0x00000000ffffffffULL /* bits 31:0 */
2325
2326 #define TXC_SF_DATA1(PORT)              (FZC_TXC + 0x20090UL + (PORT)*0x100UL)
2327 #define  TXC_SF_DATA1_DATA1             0x00000000ffffffffULL /* bits 63:32 */
2328
2329 #define TXC_SF_DATA2(PORT)              (FZC_TXC + 0x20098UL + (PORT)*0x100UL)
2330 #define  TXC_SF_DATA2_DATA2             0x00000000ffffffffULL /* bits 95:64 */
2331
2332 #define TXC_SF_DATA3(PORT)              (FZC_TXC + 0x200a0UL + (PORT)*0x100UL)
2333 #define  TXC_SF_DATA3_DATA3             0x00000000ffffffffULL /* bits 127:96 */
2334
2335 #define TXC_SF_DATA4(PORT)              (FZC_TXC + 0x200a8UL + (PORT)*0x100UL)
2336 #define  TXC_SF_DATA4_DATA4             0x0000000000ffffffULL /* bits 151:128 */
2337
2338 #define TXC_RO_TIDS(PORT)               (FZC_TXC + 0x200b0UL + (PORT)*0x100UL)
2339 #define  TXC_RO_TIDS_IN_USE             0x00000000ffffffffULL
2340
2341 #define TXC_RO_STATE0(PORT)             (FZC_TXC + 0x200b8UL + (PORT)*0x100UL)
2342 #define  TXC_RO_STATE0_DUPLICATE_TID    0x00000000ffffffffULL
2343
2344 #define TXC_RO_STATE1(PORT)             (FZC_TXC + 0x200c0UL + (PORT)*0x100UL)
2345 #define  TXC_RO_STATE1_UNUSED_TID       0x00000000ffffffffULL
2346
2347 #define TXC_RO_STATE2(PORT)             (FZC_TXC + 0x200c8UL + (PORT)*0x100UL)
2348 #define  TXC_RO_STATE2_TRANS_TIMEOUT    0x00000000ffffffffULL
2349
2350 #define TXC_RO_STATE3(PORT)             (FZC_TXC + 0x200d0UL + (PORT)*0x100UL)
2351 #define  TXC_RO_STATE3_ENAB_SPC_WMARK   0x0000000080000000ULL
2352 #define  TXC_RO_STATE3_RO_SPC_WMARK     0x000000007fe00000ULL
2353 #define  TXC_RO_STATE3_ROFIFO_SPC_AVAIL 0x00000000001ff800ULL
2354 #define  TXC_RO_STATE3_ENAB_RO_WMARK    0x0000000000000100ULL
2355 #define  TXC_RO_STATE3_HIGH_RO_USED     0x00000000000000f0ULL
2356 #define  TXC_RO_STATE3_NUM_RO_USED      0x000000000000000fULL
2357
2358 #define TXC_RO_CTL(PORT)                (FZC_TXC + 0x200d8UL + (PORT)*0x100UL)
2359 #define  TXC_RO_CTL_CLR_FAIL_STATE      0x0000000080000000ULL
2360 #define  TXC_RO_CTL_RO_ADDR             0x000000000f000000ULL
2361 #define  TXC_RO_CTL_ADDR_FAILED         0x0000000000400000ULL
2362 #define  TXC_RO_CTL_DMA_FAILED          0x0000000000200000ULL
2363 #define  TXC_RO_CTL_LEN_FAILED          0x0000000000100000ULL
2364 #define  TXC_RO_CTL_CAPT_ADDR_FAILED    0x0000000000040000ULL
2365 #define  TXC_RO_CTL_CAPT_DMA_FAILED     0x0000000000020000ULL
2366 #define  TXC_RO_CTL_CAPT_LEN_FAILED     0x0000000000010000ULL
2367 #define  TXC_RO_CTL_RO_STATE_RD_DONE    0x0000000000000080ULL
2368 #define  TXC_RO_CTL_RO_STATE_WR_DONE    0x0000000000000040ULL
2369 #define  TXC_RO_CTL_RO_STATE_RD         0x0000000000000020ULL
2370 #define  TXC_RO_CTL_RO_STATE_WR         0x0000000000000010ULL
2371 #define  TXC_RO_CTL_RO_STATE_ADDR       0x000000000000000fULL
2372
2373 #define TXC_RO_ST_DATA0(PORT)           (FZC_TXC + 0x200e0UL + (PORT)*0x100UL)
2374 #define  TXC_RO_ST_DATA0_DATA0          0x00000000ffffffffULL
2375
2376 #define TXC_RO_ST_DATA1(PORT)           (FZC_TXC + 0x200e8UL + (PORT)*0x100UL)
2377 #define  TXC_RO_ST_DATA1_DATA1          0x00000000ffffffffULL
2378
2379 #define TXC_RO_ST_DATA2(PORT)           (FZC_TXC + 0x200f0UL + (PORT)*0x100UL)
2380 #define  TXC_RO_ST_DATA2_DATA2          0x00000000ffffffffULL
2381
2382 #define TXC_RO_ST_DATA3(PORT)           (FZC_TXC + 0x200f8UL + (PORT)*0x100UL)
2383 #define  TXC_RO_ST_DATA3_DATA3          0x00000000ffffffffULL
2384
2385 #define TXC_PORT_PACKET_REQ(PORT)       (FZC_TXC + 0x20100UL + (PORT)*0x100UL)
2386 #define  TXC_PORT_PACKET_REQ_GATHER_REQ 0x00000000f0000000ULL
2387 #define  TXC_PORT_PACKET_REQ_PKT_REQ    0x000000000fff0000ULL
2388 #define  TXC_PORT_PACKET_REQ_PERR_ABRT  0x000000000000ffffULL
2389
2390         /* bits are same as TXC_INT_STAT */
2391 #define TXC_INT_STAT_DBG                (FZC_TXC + 0x20420UL)
2392
2393 #define TXC_INT_STAT                    (FZC_TXC + 0x20428UL)
2394 #define  TXC_INT_STAT_VAL_SHIFT(PORT)   ((PORT) * 8)
2395 #define  TXC_INT_STAT_VAL(PORT)         (0x3f << TXC_INT_STAT_VAL_SHIFT(PORT))
2396 #define  TXC_INT_STAT_SF_CE(PORT)       (0x01 << TXC_INT_STAT_VAL_SHIFT(PORT))
2397 #define  TXC_INT_STAT_SF_UE(PORT)       (0x02 << TXC_INT_STAT_VAL_SHIFT(PORT))
2398 #define  TXC_INT_STAT_RO_CE(PORT)       (0x04 << TXC_INT_STAT_VAL_SHIFT(PORT))
2399 #define  TXC_INT_STAT_RO_UE(PORT)       (0x08 << TXC_INT_STAT_VAL_SHIFT(PORT))
2400 #define  TXC_INT_STAT_REORDER_ERR(PORT) (0x10 << TXC_INT_STAT_VAL_SHIFT(PORT))
2401 #define  TXC_INT_STAT_PKTASM_DEAD(PORT) (0x20 << TXC_INT_STAT_VAL_SHIFT(PORT))
2402
2403 #define TXC_INT_MASK                    (FZC_TXC + 0x20430UL)
2404 #define  TXC_INT_MASK_VAL_SHIFT(PORT)   ((PORT) * 8)
2405 #define  TXC_INT_MASK_VAL(PORT)         (0x3f << TXC_INT_STAT_VAL_SHIFT(PORT))
2406
2407 #define TXC_INT_MASK_SF_CE              0x01
2408 #define TXC_INT_MASK_SF_UE              0x02
2409 #define TXC_INT_MASK_RO_CE              0x04
2410 #define TXC_INT_MASK_RO_UE              0x08
2411 #define TXC_INT_MASK_REORDER_ERR        0x10
2412 #define TXC_INT_MASK_PKTASM_DEAD        0x20
2413 #define TXC_INT_MASK_ALL                0x3f
2414
2415 #define TXC_PORT_DMA(IDX)               (FZC_TXC + 0x20028UL + (IDX)*0x100UL)
2416
2417 #define ESPC_PIO_EN                     (FZC_PROM + 0x40000UL)
2418 #define  ESPC_PIO_EN_ENABLE             0x0000000000000001ULL
2419
2420 #define ESPC_PIO_STAT                   (FZC_PROM + 0x40008UL)
2421 #define  ESPC_PIO_STAT_READ_START       0x0000000080000000ULL
2422 #define  ESPC_PIO_STAT_READ_END         0x0000000040000000ULL
2423 #define  ESPC_PIO_STAT_WRITE_INIT       0x0000000020000000ULL
2424 #define  ESPC_PIO_STAT_WRITE_END        0x0000000010000000ULL
2425 #define  ESPC_PIO_STAT_ADDR             0x0000000003ffff00ULL
2426 #define  ESPC_PIO_STAT_ADDR_SHIFT       8
2427 #define  ESPC_PIO_STAT_DATA             0x00000000000000ffULL
2428 #define  ESPC_PIO_STAT_DATA_SHIFT       0
2429
2430 #define ESPC_NCR(IDX)                   (FZC_PROM + 0x40020UL + (IDX)*0x8UL)
2431 #define  ESPC_NCR_VAL                   0x00000000ffffffffULL
2432
2433 #define ESPC_MAC_ADDR0                  ESPC_NCR(0)
2434 #define ESPC_MAC_ADDR1                  ESPC_NCR(1)
2435 #define ESPC_NUM_PORTS_MACS             ESPC_NCR(2)
2436 #define  ESPC_NUM_PORTS_MACS_VAL        0x00000000000000ffULL
2437 #define ESPC_MOD_STR_LEN                ESPC_NCR(4)
2438 #define ESPC_MOD_STR_1                  ESPC_NCR(5)
2439 #define ESPC_MOD_STR_2                  ESPC_NCR(6)
2440 #define ESPC_MOD_STR_3                  ESPC_NCR(7)
2441 #define ESPC_MOD_STR_4                  ESPC_NCR(8)
2442 #define ESPC_MOD_STR_5                  ESPC_NCR(9)
2443 #define ESPC_MOD_STR_6                  ESPC_NCR(10)
2444 #define ESPC_MOD_STR_7                  ESPC_NCR(11)
2445 #define ESPC_MOD_STR_8                  ESPC_NCR(12)
2446 #define ESPC_BD_MOD_STR_LEN             ESPC_NCR(13)
2447 #define ESPC_BD_MOD_STR_1               ESPC_NCR(14)
2448 #define ESPC_BD_MOD_STR_2               ESPC_NCR(15)
2449 #define ESPC_BD_MOD_STR_3               ESPC_NCR(16)
2450 #define ESPC_BD_MOD_STR_4               ESPC_NCR(17)
2451
2452 #define ESPC_PHY_TYPE                   ESPC_NCR(18)
2453 #define  ESPC_PHY_TYPE_PORT0            0x00000000ff000000ULL
2454 #define  ESPC_PHY_TYPE_PORT0_SHIFT      24
2455 #define  ESPC_PHY_TYPE_PORT1            0x0000000000ff0000ULL
2456 #define  ESPC_PHY_TYPE_PORT1_SHIFT      16
2457 #define  ESPC_PHY_TYPE_PORT2            0x000000000000ff00ULL
2458 #define  ESPC_PHY_TYPE_PORT2_SHIFT      8
2459 #define  ESPC_PHY_TYPE_PORT3            0x00000000000000ffULL
2460 #define  ESPC_PHY_TYPE_PORT3_SHIFT      0
2461
2462 #define  ESPC_PHY_TYPE_1G_COPPER        3
2463 #define  ESPC_PHY_TYPE_1G_FIBER         2
2464 #define  ESPC_PHY_TYPE_10G_COPPER       1
2465 #define  ESPC_PHY_TYPE_10G_FIBER        0
2466
2467 #define ESPC_MAX_FM_SZ                  ESPC_NCR(19)
2468
2469 #define ESPC_INTR_NUM                   ESPC_NCR(20)
2470 #define  ESPC_INTR_NUM_PORT0            0x00000000ff000000ULL
2471 #define  ESPC_INTR_NUM_PORT1            0x0000000000ff0000ULL
2472 #define  ESPC_INTR_NUM_PORT2            0x000000000000ff00ULL
2473 #define  ESPC_INTR_NUM_PORT3            0x00000000000000ffULL
2474
2475 #define ESPC_VER_IMGSZ                  ESPC_NCR(21)
2476 #define  ESPC_VER_IMGSZ_IMGSZ           0x00000000ffff0000ULL
2477 #define  ESPC_VER_IMGSZ_IMGSZ_SHIFT     16
2478 #define  ESPC_VER_IMGSZ_VER             0x000000000000ffffULL
2479 #define  ESPC_VER_IMGSZ_VER_SHIFT       0
2480
2481 #define ESPC_CHKSUM                     ESPC_NCR(22)
2482 #define  ESPC_CHKSUM_SUM                0x00000000000000ffULL
2483
2484 #define ESPC_EEPROM_SIZE                0x100000
2485
2486 #define CLASS_CODE_UNRECOG              0x00
2487 #define CLASS_CODE_DUMMY1               0x01
2488 #define CLASS_CODE_ETHERTYPE1           0x02
2489 #define CLASS_CODE_ETHERTYPE2           0x03
2490 #define CLASS_CODE_USER_PROG1           0x04
2491 #define CLASS_CODE_USER_PROG2           0x05
2492 #define CLASS_CODE_USER_PROG3           0x06
2493 #define CLASS_CODE_USER_PROG4           0x07
2494 #define CLASS_CODE_TCP_IPV4             0x08
2495 #define CLASS_CODE_UDP_IPV4             0x09
2496 #define CLASS_CODE_AH_ESP_IPV4          0x0a
2497 #define CLASS_CODE_SCTP_IPV4            0x0b
2498 #define CLASS_CODE_TCP_IPV6             0x0c
2499 #define CLASS_CODE_UDP_IPV6             0x0d
2500 #define CLASS_CODE_AH_ESP_IPV6          0x0e
2501 #define CLASS_CODE_SCTP_IPV6            0x0f
2502 #define CLASS_CODE_ARP                  0x10
2503 #define CLASS_CODE_RARP                 0x11
2504 #define CLASS_CODE_DUMMY2               0x12
2505 #define CLASS_CODE_DUMMY3               0x13
2506 #define CLASS_CODE_DUMMY4               0x14
2507 #define CLASS_CODE_DUMMY5               0x15
2508 #define CLASS_CODE_DUMMY6               0x16
2509 #define CLASS_CODE_DUMMY7               0x17
2510 #define CLASS_CODE_DUMMY8               0x18
2511 #define CLASS_CODE_DUMMY9               0x19
2512 #define CLASS_CODE_DUMMY10              0x1a
2513 #define CLASS_CODE_DUMMY11              0x1b
2514 #define CLASS_CODE_DUMMY12              0x1c
2515 #define CLASS_CODE_DUMMY13              0x1d
2516 #define CLASS_CODE_DUMMY14              0x1e
2517 #define CLASS_CODE_DUMMY15              0x1f
2518
2519 /* Logical devices and device groups */
2520 #define LDN_RXDMA(CHAN)                 (0 + (CHAN))
2521 #define LDN_RESV1(OFF)                  (16 + (OFF))
2522 #define LDN_TXDMA(CHAN)                 (32 + (CHAN))
2523 #define LDN_RESV2(OFF)                  (56 + (OFF))
2524 #define LDN_MIF                         63
2525 #define LDN_MAC(PORT)                   (64 + (PORT))
2526 #define LDN_DEVICE_ERROR                68
2527 #define LDN_MAX                         LDN_DEVICE_ERROR
2528
2529 #define NIU_LDG_MIN                     0
2530 #define NIU_LDG_MAX                     63
2531 #define NIU_NUM_LDG                     64
2532 #define LDG_INVALID                     0xff
2533
2534 /* PHY stuff */
2535 #define NIU_PMA_PMD_DEV_ADDR            1
2536 #define NIU_PCS_DEV_ADDR                3
2537
2538 #define NIU_PHY_ID_MASK                 0xfffff0f0
2539 #define NIU_PHY_ID_BCM8704              0x00206030
2540 #define NIU_PHY_ID_BCM8706              0x00206035
2541 #define NIU_PHY_ID_BCM5464R             0x002060b0
2542 #define NIU_PHY_ID_MRVL88X2011          0x01410020
2543
2544 /* MRVL88X2011 register addresses */
2545 #define MRVL88X2011_USER_DEV1_ADDR      1
2546 #define MRVL88X2011_USER_DEV2_ADDR      2
2547 #define MRVL88X2011_USER_DEV3_ADDR      3
2548 #define MRVL88X2011_USER_DEV4_ADDR      4
2549 #define MRVL88X2011_PMA_PMD_CTL_1       0x0000
2550 #define MRVL88X2011_PMA_PMD_STATUS_1    0x0001
2551 #define MRVL88X2011_10G_PMD_STATUS_2    0x0008
2552 #define MRVL88X2011_10G_PMD_TX_DIS      0x0009
2553 #define MRVL88X2011_10G_XGXS_LANE_STAT  0x0018
2554 #define MRVL88X2011_GENERAL_CTL         0x8300
2555 #define MRVL88X2011_LED_BLINK_CTL       0x8303
2556 #define MRVL88X2011_LED_8_TO_11_CTL     0x8306
2557
2558 /* MRVL88X2011 register control */
2559 #define MRVL88X2011_ENA_XFPREFCLK       0x0001
2560 #define MRVL88X2011_ENA_PMDTX           0x0000
2561 #define MRVL88X2011_LOOPBACK            0x1
2562 #define MRVL88X2011_LED_ACT             0x1
2563 #define MRVL88X2011_LNK_STATUS_OK       0x4
2564 #define MRVL88X2011_LED_BLKRATE_MASK    0x70
2565 #define MRVL88X2011_LED_BLKRATE_034MS   0x0
2566 #define MRVL88X2011_LED_BLKRATE_067MS   0x1
2567 #define MRVL88X2011_LED_BLKRATE_134MS   0x2
2568 #define MRVL88X2011_LED_BLKRATE_269MS   0x3
2569 #define MRVL88X2011_LED_BLKRATE_538MS   0x4
2570 #define MRVL88X2011_LED_CTL_OFF         0x0
2571 #define MRVL88X2011_LED_CTL_PCS_ACT     0x5
2572 #define MRVL88X2011_LED_CTL_MASK        0x7
2573 #define MRVL88X2011_LED(n,v)            ((v)<<((n)*4))
2574 #define MRVL88X2011_LED_STAT(n,v)       ((v)>>((n)*4))
2575
2576 #define BCM8704_PMA_PMD_DEV_ADDR        1
2577 #define BCM8704_PCS_DEV_ADDR            2
2578 #define BCM8704_USER_DEV3_ADDR          3
2579 #define BCM8704_PHYXS_DEV_ADDR          4
2580 #define BCM8704_USER_DEV4_ADDR          4
2581
2582 #define BCM8704_PMD_RCV_SIGDET          0x000a
2583 #define  PMD_RCV_SIGDET_LANE3           0x0010
2584 #define  PMD_RCV_SIGDET_LANE2           0x0008
2585 #define  PMD_RCV_SIGDET_LANE1           0x0004
2586 #define  PMD_RCV_SIGDET_LANE0           0x0002
2587 #define  PMD_RCV_SIGDET_GLOBAL          0x0001
2588
2589 #define BCM8704_PCS_10G_R_STATUS        0x0020
2590 #define  PCS_10G_R_STATUS_LINKSTAT      0x1000
2591 #define  PCS_10G_R_STATUS_PRBS31_ABLE   0x0004
2592 #define  PCS_10G_R_STATUS_HI_BER        0x0002
2593 #define  PCS_10G_R_STATUS_BLK_LOCK      0x0001
2594
2595 #define BCM8704_USER_CONTROL            0xc800
2596 #define  USER_CONTROL_OPTXENB_LVL       0x8000
2597 #define  USER_CONTROL_OPTXRST_LVL       0x4000
2598 #define  USER_CONTROL_OPBIASFLT_LVL     0x2000
2599 #define  USER_CONTROL_OBTMPFLT_LVL      0x1000
2600 #define  USER_CONTROL_OPPRFLT_LVL       0x0800
2601 #define  USER_CONTROL_OPTXFLT_LVL       0x0400
2602 #define  USER_CONTROL_OPRXLOS_LVL       0x0200
2603 #define  USER_CONTROL_OPRXFLT_LVL       0x0100
2604 #define  USER_CONTROL_OPTXON_LVL        0x0080
2605 #define  USER_CONTROL_RES1              0x007f
2606 #define  USER_CONTROL_RES1_SHIFT        0
2607
2608 #define BCM8704_USER_ANALOG_CLK         0xc801
2609 #define BCM8704_USER_PMD_RX_CONTROL     0xc802
2610
2611 #define BCM8704_USER_PMD_TX_CONTROL     0xc803
2612 #define  USER_PMD_TX_CTL_RES1           0xfe00
2613 #define  USER_PMD_TX_CTL_XFP_CLKEN      0x0100
2614 #define  USER_PMD_TX_CTL_TX_DAC_TXD     0x00c0
2615 #define  USER_PMD_TX_CTL_TX_DAC_TXD_SH  6
2616 #define  USER_PMD_TX_CTL_TX_DAC_TXCK    0x0030
2617 #define  USER_PMD_TX_CTL_TX_DAC_TXCK_SH 4
2618 #define  USER_PMD_TX_CTL_TSD_LPWREN     0x0008
2619 #define  USER_PMD_TX_CTL_TSCK_LPWREN    0x0004
2620 #define  USER_PMD_TX_CTL_CMU_LPWREN     0x0002
2621 #define  USER_PMD_TX_CTL_SFIFORST       0x0001
2622
2623 #define BCM8704_USER_ANALOG_STATUS0     0xc804
2624 #define BCM8704_USER_OPT_DIGITAL_CTRL   0xc808
2625 #define BCM8704_USER_TX_ALARM_STATUS    0x9004
2626
2627 #define  USER_ODIG_CTRL_FMODE           0x8000
2628 #define  USER_ODIG_CTRL_TX_PDOWN        0x4000
2629 #define  USER_ODIG_CTRL_RX_PDOWN        0x2000
2630 #define  USER_ODIG_CTRL_EFILT_EN        0x1000
2631 #define  USER_ODIG_CTRL_OPT_RST         0x0800
2632 #define  USER_ODIG_CTRL_PCS_TIB         0x0400
2633 #define  USER_ODIG_CTRL_PCS_RI          0x0200
2634 #define  USER_ODIG_CTRL_RESV1           0x0180
2635 #define  USER_ODIG_CTRL_GPIOS           0x0060
2636 #define  USER_ODIG_CTRL_GPIOS_SHIFT     5
2637 #define  USER_ODIG_CTRL_RESV2           0x0010
2638 #define  USER_ODIG_CTRL_LB_ERR_DIS      0x0008
2639 #define  USER_ODIG_CTRL_RESV3           0x0006
2640 #define  USER_ODIG_CTRL_TXONOFF_PD_DIS  0x0001
2641
2642 #define BCM8704_PHYXS_XGXS_LANE_STAT    0x0018
2643 #define  PHYXS_XGXS_LANE_STAT_ALINGED   0x1000
2644 #define  PHYXS_XGXS_LANE_STAT_PATTEST   0x0800
2645 #define  PHYXS_XGXS_LANE_STAT_MAGIC     0x0400
2646 #define  PHYXS_XGXS_LANE_STAT_LANE3     0x0008
2647 #define  PHYXS_XGXS_LANE_STAT_LANE2     0x0004
2648 #define  PHYXS_XGXS_LANE_STAT_LANE1     0x0002
2649 #define  PHYXS_XGXS_LANE_STAT_LANE0     0x0001
2650
2651 #define BCM5464R_AUX_CTL                24
2652 #define  BCM5464R_AUX_CTL_EXT_LB        0x8000
2653 #define  BCM5464R_AUX_CTL_EXT_PLEN      0x4000
2654 #define  BCM5464R_AUX_CTL_ER1000        0x3000
2655 #define  BCM5464R_AUX_CTL_ER1000_SHIFT  12
2656 #define  BCM5464R_AUX_CTL_RESV1         0x0800
2657 #define  BCM5464R_AUX_CTL_WRITE_1       0x0400
2658 #define  BCM5464R_AUX_CTL_RESV2         0x0300
2659 #define  BCM5464R_AUX_CTL_PRESP_DIS     0x0080
2660 #define  BCM5464R_AUX_CTL_RESV3         0x0040
2661 #define  BCM5464R_AUX_CTL_ER100         0x0030
2662 #define  BCM5464R_AUX_CTL_ER100_SHIFT   4
2663 #define  BCM5464R_AUX_CTL_DIAG_MODE     0x0008
2664 #define  BCM5464R_AUX_CTL_SR_SEL        0x0007
2665 #define  BCM5464R_AUX_CTL_SR_SEL_SHIFT  0
2666
2667 #define  BCM5464R_CTRL1000_AS_MASTER            0x0800
2668 #define  BCM5464R_CTRL1000_ENABLE_AS_MASTER     0x1000
2669
2670 #define RCR_ENTRY_MULTI                 0x8000000000000000ULL
2671 #define RCR_ENTRY_PKT_TYPE              0x6000000000000000ULL
2672 #define RCR_ENTRY_PKT_TYPE_SHIFT        61
2673 #define RCR_ENTRY_ZERO_COPY             0x1000000000000000ULL
2674 #define RCR_ENTRY_NOPORT                0x0800000000000000ULL
2675 #define RCR_ENTRY_PROMISC               0x0400000000000000ULL
2676 #define RCR_ENTRY_ERROR                 0x0380000000000000ULL
2677 #define RCR_ENTRY_DCF_ERR               0x0040000000000000ULL
2678 #define RCR_ENTRY_L2_LEN                0x003fff0000000000ULL
2679 #define RCR_ENTRY_L2_LEN_SHIFT          40
2680 #define RCR_ENTRY_PKTBUFSZ              0x000000c000000000ULL
2681 #define RCR_ENTRY_PKTBUFSZ_SHIFT        38
2682 #define RCR_ENTRY_PKT_BUF_ADDR          0x0000003fffffffffULL /* bits 43:6 */
2683 #define RCR_ENTRY_PKT_BUF_ADDR_SHIFT    6
2684
2685 #define RCR_PKT_TYPE_OTHER              0x0
2686 #define RCR_PKT_TYPE_TCP                0x1
2687 #define RCR_PKT_TYPE_UDP                0x2
2688 #define RCR_PKT_TYPE_SCTP               0x3
2689
2690 #define NIU_RXPULL_MAX                  ETH_HLEN
2691
2692 struct rx_pkt_hdr0 {
2693 #if defined(__LITTLE_ENDIAN_BITFIELD)
2694         u8      inputport:2,
2695                 maccheck:1,
2696                 class:4;
2697         u8      vlan:1,
2698                 llcsnap:1,
2699                 noport:1,
2700                 badip:1,
2701                 tcamhit:1,
2702                 tres:2,
2703                 tzfvld:1;
2704 #elif defined(__BIG_ENDIAN_BITFIELD)
2705         u8      class:4,
2706                 maccheck:1,
2707                 inputport:2;
2708         u8      tzfvld:1,
2709                 tres:2,
2710                 tcamhit:1,
2711                 badip:1,
2712                 noport:1,
2713                 llcsnap:1,
2714                 vlan:1;
2715 #endif
2716 };
2717
2718 struct rx_pkt_hdr1 {
2719         u8      hwrsvd1;
2720         u8      tcammatch;
2721 #if defined(__LITTLE_ENDIAN_BITFIELD)
2722         u8      hwrsvd2:2,
2723                 hashit:1,
2724                 exact:1,
2725                 hzfvld:1,
2726                 hashsidx:3;
2727 #elif defined(__BIG_ENDIAN_BITFIELD)
2728         u8      hashsidx:3,
2729                 hzfvld:1,
2730                 exact:1,
2731                 hashit:1,
2732                 hwrsvd2:2;
2733 #endif
2734         u8      zcrsvd;
2735
2736         /* Bits 11:8 of zero copy flow ID.  */
2737 #if defined(__LITTLE_ENDIAN_BITFIELD)
2738         u8      hwrsvd3:4, zflowid0:4;
2739 #elif defined(__BIG_ENDIAN_BITFIELD)
2740         u8      zflowid0:4, hwrsvd3:4;
2741 #endif
2742
2743         /* Bits 7:0 of zero copy flow ID.  */
2744         u8      zflowid1;
2745
2746         /* Bits 15:8 of hash value, H2.  */
2747         u8      hashval2_0;
2748
2749         /* Bits 7:0 of hash value, H2.  */
2750         u8      hashval2_1;
2751
2752         /* Bits 19:16 of hash value, H1.  */
2753 #if defined(__LITTLE_ENDIAN_BITFIELD)
2754         u8      hwrsvd4:4, hashval1_0:4;
2755 #elif defined(__BIG_ENDIAN_BITFIELD)
2756         u8      hashval1_0:4, hwrsvd4:4;
2757 #endif
2758
2759         /* Bits 15:8 of hash value, H1.  */
2760         u8      hashval1_1;
2761
2762         /* Bits 7:0 of hash value, H1.  */
2763         u8      hashval1_2;
2764
2765         u8      usrdata_0;      /* Bits 39:32 of user data.  */
2766         u8      usrdata_1;      /* Bits 31:24 of user data.  */
2767         u8      usrdata_2;      /* Bits 23:16 of user data.  */
2768         u8      usrdata_3;      /* Bits 15:8 of user data.  */
2769         u8      usrdata_4;      /* Bits 7:0 of user data.  */
2770 };
2771
2772 struct tx_dma_mbox {
2773         u64     tx_dma_pre_st;
2774         u64     tx_cs;
2775         u64     tx_ring_kick;
2776         u64     tx_ring_hdl;
2777         u64     resv1;
2778         u32     tx_rng_err_logl;
2779         u32     tx_rng_err_logh;
2780         u64     resv2;
2781         u64     resv3;
2782 };
2783
2784 struct tx_pkt_hdr {
2785         __le64  flags;
2786 #define TXHDR_PAD               0x0000000000000007ULL
2787 #define  TXHDR_PAD_SHIFT        0
2788 #define TXHDR_LEN               0x000000003fff0000ULL
2789 #define  TXHDR_LEN_SHIFT        16
2790 #define TXHDR_L4STUFF           0x0000003f00000000ULL
2791 #define  TXHDR_L4STUFF_SHIFT    32
2792 #define TXHDR_L4START           0x00003f0000000000ULL
2793 #define  TXHDR_L4START_SHIFT    40
2794 #define TXHDR_L3START           0x000f000000000000ULL
2795 #define  TXHDR_L3START_SHIFT    48
2796 #define TXHDR_IHL               0x00f0000000000000ULL
2797 #define  TXHDR_IHL_SHIFT        52
2798 #define TXHDR_VLAN              0x0100000000000000ULL
2799 #define TXHDR_LLC               0x0200000000000000ULL
2800 #define TXHDR_IP_VER            0x2000000000000000ULL
2801 #define TXHDR_CSUM_NONE         0x0000000000000000ULL
2802 #define TXHDR_CSUM_TCP          0x4000000000000000ULL
2803 #define TXHDR_CSUM_UDP          0x8000000000000000ULL
2804 #define TXHDR_CSUM_SCTP         0xc000000000000000ULL
2805         __le64  resv;
2806 };
2807
2808 #define TX_DESC_SOP             0x8000000000000000ULL
2809 #define TX_DESC_MARK            0x4000000000000000ULL
2810 #define TX_DESC_NUM_PTR         0x3c00000000000000ULL
2811 #define TX_DESC_NUM_PTR_SHIFT   58
2812 #define TX_DESC_TR_LEN          0x01fff00000000000ULL
2813 #define TX_DESC_TR_LEN_SHIFT    44
2814 #define TX_DESC_SAD             0x00000fffffffffffULL
2815 #define TX_DESC_SAD_SHIFT       0
2816
2817 struct tx_buff_info {
2818         struct sk_buff *skb;
2819         u64 mapping;
2820 };
2821
2822 struct txdma_mailbox {
2823         __le64  tx_dma_pre_st;
2824         __le64  tx_cs;
2825         __le64  tx_ring_kick;
2826         __le64  tx_ring_hdl;
2827         __le64  resv1;
2828         __le32  tx_rng_err_logl;
2829         __le32  tx_rng_err_logh;
2830         __le64  resv2[2];
2831 } __attribute__((aligned(64)));
2832
2833 #define MAX_TX_RING_SIZE        256
2834 #define MAX_TX_DESC_LEN         4076
2835
2836 struct tx_ring_info {
2837         struct tx_buff_info     tx_buffs[MAX_TX_RING_SIZE];
2838         struct niu              *np;
2839         u64                     tx_cs;
2840         int                     pending;
2841         int                     prod;
2842         int                     cons;
2843         int                     wrap_bit;
2844         u16                     last_pkt_cnt;
2845         u16                     tx_channel;
2846         u16                     mark_counter;
2847         u16                     mark_freq;
2848         u16                     mark_pending;
2849         u16                     __pad;
2850         struct txdma_mailbox    *mbox;
2851         __le64                  *descr;
2852
2853         u64                     tx_packets;
2854         u64                     tx_bytes;
2855         u64                     tx_errors;
2856
2857         u64                     mbox_dma;
2858         u64                     descr_dma;
2859         int                     max_burst;
2860 };
2861
2862 #define NEXT_TX(tp, index) \
2863         (((index) + 1) < (tp)->pending ? ((index) + 1) : 0)
2864
2865 static inline u32 niu_tx_avail(struct tx_ring_info *tp)
2866 {
2867         return (tp->pending -
2868                 ((tp->prod - tp->cons) & (MAX_TX_RING_SIZE - 1)));
2869 }
2870
2871 struct rxdma_mailbox {
2872         __le64  rx_dma_ctl_stat;
2873         __le64  rbr_stat;
2874         __le32  rbr_hdl;
2875         __le32  rbr_hdh;
2876         __le64  resv1;
2877         __le32  rcrstat_c;
2878         __le32  rcrstat_b;
2879         __le64  rcrstat_a;
2880         __le64  resv2[2];
2881 } __attribute__((aligned(64)));
2882
2883 #define MAX_RBR_RING_SIZE       128
2884 #define MAX_RCR_RING_SIZE       (MAX_RBR_RING_SIZE * 2)
2885
2886 #define RBR_REFILL_MIN          16
2887
2888 #define RX_SKB_ALLOC_SIZE       128 + NET_IP_ALIGN
2889
2890 struct rx_ring_info {
2891         struct niu              *np;
2892         int                     rx_channel;
2893         u16                     rbr_block_size;
2894         u16                     rbr_blocks_per_page;
2895         u16                     rbr_sizes[4];
2896         unsigned int            rcr_index;
2897         unsigned int            rcr_table_size;
2898         unsigned int            rbr_index;
2899         unsigned int            rbr_pending;
2900         unsigned int            rbr_refill_pending;
2901         unsigned int            rbr_kick_thresh;
2902         unsigned int            rbr_table_size;
2903         struct page             **rxhash;
2904         struct rxdma_mailbox    *mbox;
2905         __le64                  *rcr;
2906         __le32                  *rbr;
2907 #define RBR_DESCR_ADDR_SHIFT    12
2908
2909         u64                     rx_packets;
2910         u64                     rx_bytes;
2911         u64                     rx_dropped;
2912         u64                     rx_errors;
2913
2914         u64                     mbox_dma;
2915         u64                     rcr_dma;
2916         u64                     rbr_dma;
2917
2918         /* WRED */
2919         int                     nonsyn_window;
2920         int                     nonsyn_threshold;
2921         int                     syn_window;
2922         int                     syn_threshold;
2923
2924         /* interrupt mitigation */
2925         int                     rcr_pkt_threshold;
2926         int                     rcr_timeout;
2927 };
2928
2929 #define NEXT_RCR(rp, index) \
2930         (((index) + 1) < (rp)->rcr_table_size ? ((index) + 1) : 0)
2931 #define NEXT_RBR(rp, index) \
2932         (((index) + 1) < (rp)->rbr_table_size ? ((index) + 1) : 0)
2933
2934 #define NIU_MAX_PORTS           4
2935 #define NIU_NUM_RXCHAN          16
2936 #define NIU_NUM_TXCHAN          24
2937 #define MAC_NUM_HASH            16
2938
2939 #define NIU_MAX_MTU             9216
2940
2941 /* VPD strings */
2942 #define NIU_QGC_LP_BM_STR       "501-7606"
2943 #define NIU_2XGF_LP_BM_STR      "501-7283"
2944 #define NIU_QGC_PEM_BM_STR      "501-7765"
2945 #define NIU_2XGF_PEM_BM_STR     "501-7626"
2946 #define NIU_ALONSO_BM_STR       "373-0202"
2947 #define NIU_FOXXY_BM_STR        "501-7961"
2948 #define NIU_2XGF_MRVL_BM_STR    "SK-6E82"
2949 #define NIU_QGC_LP_MDL_STR      "SUNW,pcie-qgc"
2950 #define NIU_2XGF_LP_MDL_STR     "SUNW,pcie-2xgf"
2951 #define NIU_QGC_PEM_MDL_STR     "SUNW,pcie-qgc-pem"
2952 #define NIU_2XGF_PEM_MDL_STR    "SUNW,pcie-2xgf-pem"
2953 #define NIU_ALONSO_MDL_STR      "SUNW,CP3220"
2954 #define NIU_KIMI_MDL_STR        "SUNW,CP3260"
2955 #define NIU_MARAMBA_MDL_STR     "SUNW,pcie-neptune"
2956 #define NIU_FOXXY_MDL_STR       "SUNW,pcie-rfem"
2957 #define NIU_2XGF_MRVL_MDL_STR   "SysKonnect,pcie-2xgf"
2958
2959 #define NIU_VPD_MIN_MAJOR       3
2960 #define NIU_VPD_MIN_MINOR       4
2961
2962 #define NIU_VPD_MODEL_MAX       32
2963 #define NIU_VPD_BD_MODEL_MAX    16
2964 #define NIU_VPD_VERSION_MAX     64
2965 #define NIU_VPD_PHY_TYPE_MAX    8
2966
2967 struct niu_vpd {
2968         char                    model[NIU_VPD_MODEL_MAX];
2969         char                    board_model[NIU_VPD_BD_MODEL_MAX];
2970         char                    version[NIU_VPD_VERSION_MAX];
2971         char                    phy_type[NIU_VPD_PHY_TYPE_MAX];
2972         u8                      mac_num;
2973         u8                      __pad;
2974         u8                      local_mac[6];
2975         int                     fcode_major;
2976         int                     fcode_minor;
2977 };
2978
2979 struct niu_altmac_rdc {
2980         u8                      alt_mac_num;
2981         u8                      rdc_num;
2982         u8                      mac_pref;
2983 };
2984
2985 struct niu_vlan_rdc {
2986         u8                      rdc_num;
2987         u8                      vlan_pref;
2988 };
2989
2990 struct niu_classifier {
2991         struct niu_altmac_rdc   alt_mac_mappings[16];
2992         struct niu_vlan_rdc     vlan_mappings[ENET_VLAN_TBL_NUM_ENTRIES];
2993
2994         u16                     tcam_index;
2995         u16                     num_alt_mac_mappings;
2996
2997         u32                     h1_init;
2998         u16                     h2_init;
2999 };
3000
3001 #define NIU_NUM_RDC_TABLES      8
3002 #define NIU_RDC_TABLE_SLOTS     16
3003
3004 struct rdc_table {
3005         u8                      rxdma_channel[NIU_RDC_TABLE_SLOTS];
3006 };
3007
3008 struct niu_rdc_tables {
3009         struct rdc_table        tables[NIU_NUM_RDC_TABLES];
3010         int                     first_table_num;
3011         int                     num_tables;
3012 };
3013
3014 #define PHY_TYPE_PMA_PMD        0
3015 #define PHY_TYPE_PCS            1
3016 #define PHY_TYPE_MII            2
3017 #define PHY_TYPE_MAX            3
3018
3019 struct phy_probe_info {
3020         u32     phy_id[PHY_TYPE_MAX][NIU_MAX_PORTS];
3021         u8      phy_port[PHY_TYPE_MAX][NIU_MAX_PORTS];
3022         u8      cur[PHY_TYPE_MAX];
3023
3024         struct device_attribute phy_port_attrs[PHY_TYPE_MAX * NIU_MAX_PORTS];
3025         struct device_attribute phy_type_attrs[PHY_TYPE_MAX * NIU_MAX_PORTS];
3026         struct device_attribute phy_id_attrs[PHY_TYPE_MAX * NIU_MAX_PORTS];
3027 };
3028
3029 struct niu_tcam_entry {
3030         u64                     key[4];
3031         u64                     key_mask[4];
3032         u64                     assoc_data;
3033 };
3034
3035 struct device_node;
3036 union niu_parent_id {
3037         struct {
3038                 int             domain;
3039                 int             bus;
3040                 int             device;
3041         } pci;
3042         struct device_node      *of;
3043 };
3044
3045 struct niu;
3046 struct niu_parent {
3047         struct platform_device  *plat_dev;
3048         int                     index;
3049
3050         union niu_parent_id     id;
3051
3052         struct niu              *ports[NIU_MAX_PORTS];
3053
3054         atomic_t                refcnt;
3055         struct list_head        list;
3056
3057         spinlock_t              lock;
3058
3059         u32                     flags;
3060 #define PARENT_FLGS_CLS_HWINIT  0x00000001
3061
3062         u32                     port_phy;
3063 #define PORT_PHY_UNKNOWN        0x00000000
3064 #define PORT_PHY_INVALID        0xffffffff
3065 #define PORT_TYPE_10G           0x01
3066 #define PORT_TYPE_1G            0x02
3067 #define PORT_TYPE_MASK          0x03
3068
3069         u8                      rxchan_per_port[NIU_MAX_PORTS];
3070         u8                      txchan_per_port[NIU_MAX_PORTS];
3071
3072         struct niu_rdc_tables   rdc_group_cfg[NIU_MAX_PORTS];
3073         u8                      rdc_default[NIU_MAX_PORTS];
3074
3075         u8                      ldg_map[LDN_MAX + 1];
3076
3077         u8                      plat_type;
3078 #define PLAT_TYPE_INVALID       0x00
3079 #define PLAT_TYPE_ATLAS         0x01
3080 #define PLAT_TYPE_NIU           0x02
3081 #define PLAT_TYPE_VF_P0         0x03
3082 #define PLAT_TYPE_VF_P1         0x04
3083 #define PLAT_TYPE_ATCA_CP3220   0x08
3084
3085         u8                      num_ports;
3086
3087         u16                     tcam_num_entries;
3088 #define NIU_PCI_TCAM_ENTRIES    256
3089 #define NIU_NONPCI_TCAM_ENTRIES 128
3090 #define NIU_TCAM_ENTRIES_MAX    256
3091
3092         int                     rxdma_clock_divider;
3093
3094         struct phy_probe_info   phy_probe_info;
3095
3096         struct niu_tcam_entry   tcam[NIU_TCAM_ENTRIES_MAX];
3097         u64                     l2_cls[2];
3098         u64                     l3_cls[4];
3099         u64                     tcam_key[12];
3100         u64                     flow_key[12];
3101 };
3102
3103 struct niu_ops {
3104         void *(*alloc_coherent)(struct device *dev, size_t size,
3105                                 u64 *handle, gfp_t flag);
3106         void (*free_coherent)(struct device *dev, size_t size,
3107                               void *cpu_addr, u64 handle);
3108         u64 (*map_page)(struct device *dev, struct page *page,
3109                         unsigned long offset, size_t size,
3110                         enum dma_data_direction direction);
3111         void (*unmap_page)(struct device *dev, u64 dma_address,
3112                            size_t size, enum dma_data_direction direction);
3113         u64 (*map_single)(struct device *dev, void *cpu_addr,
3114                           size_t size,
3115                           enum dma_data_direction direction);
3116         void (*unmap_single)(struct device *dev, u64 dma_address,
3117                              size_t size, enum dma_data_direction direction);
3118 };
3119
3120 struct niu_link_config {
3121         /* Describes what we're trying to get. */
3122         u32                             advertising;
3123         u32                             supported;
3124         u16                             speed;
3125         u8                              duplex;
3126         u8                              autoneg;
3127
3128         /* Describes what we actually have. */
3129         u16                             active_speed;
3130         u8                              active_duplex;
3131 #define SPEED_INVALID           0xffff
3132 #define DUPLEX_INVALID          0xff
3133 #define AUTONEG_INVALID         0xff
3134
3135         u8                              loopback_mode;
3136 #define LOOPBACK_DISABLED       0x00
3137 #define LOOPBACK_PHY            0x01
3138 #define LOOPBACK_MAC            0x02
3139 };
3140
3141 struct niu_ldg {
3142         struct napi_struct      napi;
3143         struct niu      *np;
3144         u8              ldg_num;
3145         u8              timer;
3146         u64             v0, v1, v2;
3147         unsigned int    irq;
3148 };
3149
3150 struct niu_xmac_stats {
3151         u64     tx_frames;
3152         u64     tx_bytes;
3153         u64     tx_fifo_errors;
3154         u64     tx_overflow_errors;
3155         u64     tx_max_pkt_size_errors;
3156         u64     tx_underflow_errors;
3157
3158         u64     rx_local_faults;
3159         u64     rx_remote_faults;
3160         u64     rx_link_faults;
3161         u64     rx_align_errors;
3162         u64     rx_frags;
3163         u64     rx_mcasts;
3164         u64     rx_bcasts;
3165         u64     rx_hist_cnt1;
3166         u64     rx_hist_cnt2;
3167         u64     rx_hist_cnt3;
3168         u64     rx_hist_cnt4;
3169         u64     rx_hist_cnt5;
3170         u64     rx_hist_cnt6;
3171         u64     rx_hist_cnt7;
3172         u64     rx_octets;
3173         u64     rx_code_violations;
3174         u64     rx_len_errors;
3175         u64     rx_crc_errors;
3176         u64     rx_underflows;
3177         u64     rx_overflows;
3178
3179         u64     pause_off_state;
3180         u64     pause_on_state;
3181         u64     pause_received;
3182 };
3183
3184 struct niu_bmac_stats {
3185         u64     tx_underflow_errors;
3186         u64     tx_max_pkt_size_errors;
3187         u64     tx_bytes;
3188         u64     tx_frames;
3189
3190         u64     rx_overflows;
3191         u64     rx_frames;
3192         u64     rx_align_errors;
3193         u64     rx_crc_errors;
3194         u64     rx_len_errors;
3195
3196         u64     pause_off_state;
3197         u64     pause_on_state;
3198         u64     pause_received;
3199 };
3200
3201 union niu_mac_stats {
3202         struct niu_xmac_stats   xmac;
3203         struct niu_bmac_stats   bmac;
3204 };
3205
3206 struct niu_phy_ops {
3207         int (*serdes_init)(struct niu *np);
3208         int (*xcvr_init)(struct niu *np);
3209         int (*link_status)(struct niu *np, int *);
3210 };
3211
3212 struct of_device;
3213 struct niu {
3214         void __iomem                    *regs;
3215         struct net_device               *dev;
3216         struct pci_dev                  *pdev;
3217         struct device                   *device;
3218         struct niu_parent               *parent;
3219
3220         u32                             flags;
3221 #define NIU_FLAGS_HOTPLUG_PHY_PRESENT   0x02000000 /* Removebale PHY detected*/
3222 #define NIU_FLAGS_HOTPLUG_PHY           0x01000000 /* Removebale PHY */
3223 #define NIU_FLAGS_VPD_VALID             0x00800000 /* VPD has valid version */
3224 #define NIU_FLAGS_MSIX                  0x00400000 /* MSI-X in use */
3225 #define NIU_FLAGS_MCAST                 0x00200000 /* multicast filter enabled */
3226 #define NIU_FLAGS_PROMISC               0x00100000 /* PROMISC enabled */
3227 #define NIU_FLAGS_XCVR_SERDES           0x00080000 /* 0=PHY 1=SERDES */
3228 #define NIU_FLAGS_10G                   0x00040000 /* 0=1G 1=10G */
3229 #define NIU_FLAGS_FIBER                 0x00020000 /* 0=COPPER 1=FIBER */
3230 #define NIU_FLAGS_XMAC                  0x00010000 /* 0=BMAC 1=XMAC */
3231
3232         u32                             msg_enable;
3233
3234         /* Protects hw programming, and ring state.  */
3235         spinlock_t                      lock;
3236
3237         const struct niu_ops            *ops;
3238         struct net_device_stats         net_stats;
3239         union niu_mac_stats             mac_stats;
3240
3241         struct rx_ring_info             *rx_rings;
3242         struct tx_ring_info             *tx_rings;
3243         int                             num_rx_rings;
3244         int                             num_tx_rings;
3245
3246         struct niu_ldg                  ldg[NIU_NUM_LDG];
3247         int                             num_ldg;
3248
3249         void __iomem                    *mac_regs;
3250         unsigned long                   ipp_off;
3251         unsigned long                   pcs_off;
3252         unsigned long                   xpcs_off;
3253
3254         struct timer_list               timer;
3255         const struct niu_phy_ops        *phy_ops;
3256         int                             phy_addr;
3257
3258         struct niu_link_config          link_config;
3259
3260         struct work_struct              reset_task;
3261
3262         u8                              port;
3263         u8                              mac_xcvr;
3264 #define MAC_XCVR_MII                    1
3265 #define MAC_XCVR_PCS                    2
3266 #define MAC_XCVR_XPCS                   3
3267
3268         struct niu_classifier           clas;
3269
3270         struct niu_vpd                  vpd;
3271         u32                             eeprom_len;
3272
3273         struct of_device                *op;
3274         void __iomem                    *vir_regs_1;
3275         void __iomem                    *vir_regs_2;
3276 };
3277
3278 #endif /* _NIU_H */