niu: BUG on inability to find page in rx page hashes.
[linux-2.6.git] / drivers / net / niu.c
1 /* niu.c: Neptune ethernet driver.
2  *
3  * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
4  */
5
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/netdevice.h>
13 #include <linux/ethtool.h>
14 #include <linux/etherdevice.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/bitops.h>
18 #include <linux/mii.h>
19 #include <linux/if_ether.h>
20 #include <linux/if_vlan.h>
21 #include <linux/ip.h>
22 #include <linux/in.h>
23 #include <linux/ipv6.h>
24 #include <linux/log2.h>
25 #include <linux/jiffies.h>
26 #include <linux/crc32.h>
27 #include <linux/list.h>
28 #include <linux/slab.h>
29
30 #include <linux/io.h>
31
32 #ifdef CONFIG_SPARC64
33 #include <linux/of_device.h>
34 #endif
35
36 #include "niu.h"
37
38 #define DRV_MODULE_NAME         "niu"
39 #define DRV_MODULE_VERSION      "1.1"
40 #define DRV_MODULE_RELDATE      "Apr 22, 2010"
41
42 static char version[] __devinitdata =
43         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
44
45 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
46 MODULE_DESCRIPTION("NIU ethernet driver");
47 MODULE_LICENSE("GPL");
48 MODULE_VERSION(DRV_MODULE_VERSION);
49
50 #ifndef readq
51 static u64 readq(void __iomem *reg)
52 {
53         return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
54 }
55
56 static void writeq(u64 val, void __iomem *reg)
57 {
58         writel(val & 0xffffffff, reg);
59         writel(val >> 32, reg + 0x4UL);
60 }
61 #endif
62
63 static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl) = {
64         {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
65         {}
66 };
67
68 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
69
70 #define NIU_TX_TIMEOUT                  (5 * HZ)
71
72 #define nr64(reg)               readq(np->regs + (reg))
73 #define nw64(reg, val)          writeq((val), np->regs + (reg))
74
75 #define nr64_mac(reg)           readq(np->mac_regs + (reg))
76 #define nw64_mac(reg, val)      writeq((val), np->mac_regs + (reg))
77
78 #define nr64_ipp(reg)           readq(np->regs + np->ipp_off + (reg))
79 #define nw64_ipp(reg, val)      writeq((val), np->regs + np->ipp_off + (reg))
80
81 #define nr64_pcs(reg)           readq(np->regs + np->pcs_off + (reg))
82 #define nw64_pcs(reg, val)      writeq((val), np->regs + np->pcs_off + (reg))
83
84 #define nr64_xpcs(reg)          readq(np->regs + np->xpcs_off + (reg))
85 #define nw64_xpcs(reg, val)     writeq((val), np->regs + np->xpcs_off + (reg))
86
87 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
88
89 static int niu_debug;
90 static int debug = -1;
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "NIU debug level");
93
94 #define niu_lock_parent(np, flags) \
95         spin_lock_irqsave(&np->parent->lock, flags)
96 #define niu_unlock_parent(np, flags) \
97         spin_unlock_irqrestore(&np->parent->lock, flags)
98
99 static int serdes_init_10g_serdes(struct niu *np);
100
101 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
102                                      u64 bits, int limit, int delay)
103 {
104         while (--limit >= 0) {
105                 u64 val = nr64_mac(reg);
106
107                 if (!(val & bits))
108                         break;
109                 udelay(delay);
110         }
111         if (limit < 0)
112                 return -ENODEV;
113         return 0;
114 }
115
116 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
117                                         u64 bits, int limit, int delay,
118                                         const char *reg_name)
119 {
120         int err;
121
122         nw64_mac(reg, bits);
123         err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
124         if (err)
125                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
126                            (unsigned long long)bits, reg_name,
127                            (unsigned long long)nr64_mac(reg));
128         return err;
129 }
130
131 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
132 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
133         __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
134 })
135
136 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
137                                      u64 bits, int limit, int delay)
138 {
139         while (--limit >= 0) {
140                 u64 val = nr64_ipp(reg);
141
142                 if (!(val & bits))
143                         break;
144                 udelay(delay);
145         }
146         if (limit < 0)
147                 return -ENODEV;
148         return 0;
149 }
150
151 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
152                                         u64 bits, int limit, int delay,
153                                         const char *reg_name)
154 {
155         int err;
156         u64 val;
157
158         val = nr64_ipp(reg);
159         val |= bits;
160         nw64_ipp(reg, val);
161
162         err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
163         if (err)
164                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
165                            (unsigned long long)bits, reg_name,
166                            (unsigned long long)nr64_ipp(reg));
167         return err;
168 }
169
170 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
171 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
172         __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
173 })
174
175 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
176                                  u64 bits, int limit, int delay)
177 {
178         while (--limit >= 0) {
179                 u64 val = nr64(reg);
180
181                 if (!(val & bits))
182                         break;
183                 udelay(delay);
184         }
185         if (limit < 0)
186                 return -ENODEV;
187         return 0;
188 }
189
190 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
191 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
192         __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
193 })
194
195 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
196                                     u64 bits, int limit, int delay,
197                                     const char *reg_name)
198 {
199         int err;
200
201         nw64(reg, bits);
202         err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
203         if (err)
204                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
205                            (unsigned long long)bits, reg_name,
206                            (unsigned long long)nr64(reg));
207         return err;
208 }
209
210 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
211 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
212         __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
213 })
214
215 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
216 {
217         u64 val = (u64) lp->timer;
218
219         if (on)
220                 val |= LDG_IMGMT_ARM;
221
222         nw64(LDG_IMGMT(lp->ldg_num), val);
223 }
224
225 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
226 {
227         unsigned long mask_reg, bits;
228         u64 val;
229
230         if (ldn < 0 || ldn > LDN_MAX)
231                 return -EINVAL;
232
233         if (ldn < 64) {
234                 mask_reg = LD_IM0(ldn);
235                 bits = LD_IM0_MASK;
236         } else {
237                 mask_reg = LD_IM1(ldn - 64);
238                 bits = LD_IM1_MASK;
239         }
240
241         val = nr64(mask_reg);
242         if (on)
243                 val &= ~bits;
244         else
245                 val |= bits;
246         nw64(mask_reg, val);
247
248         return 0;
249 }
250
251 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
252 {
253         struct niu_parent *parent = np->parent;
254         int i;
255
256         for (i = 0; i <= LDN_MAX; i++) {
257                 int err;
258
259                 if (parent->ldg_map[i] != lp->ldg_num)
260                         continue;
261
262                 err = niu_ldn_irq_enable(np, i, on);
263                 if (err)
264                         return err;
265         }
266         return 0;
267 }
268
269 static int niu_enable_interrupts(struct niu *np, int on)
270 {
271         int i;
272
273         for (i = 0; i < np->num_ldg; i++) {
274                 struct niu_ldg *lp = &np->ldg[i];
275                 int err;
276
277                 err = niu_enable_ldn_in_ldg(np, lp, on);
278                 if (err)
279                         return err;
280         }
281         for (i = 0; i < np->num_ldg; i++)
282                 niu_ldg_rearm(np, &np->ldg[i], on);
283
284         return 0;
285 }
286
287 static u32 phy_encode(u32 type, int port)
288 {
289         return (type << (port * 2));
290 }
291
292 static u32 phy_decode(u32 val, int port)
293 {
294         return (val >> (port * 2)) & PORT_TYPE_MASK;
295 }
296
297 static int mdio_wait(struct niu *np)
298 {
299         int limit = 1000;
300         u64 val;
301
302         while (--limit > 0) {
303                 val = nr64(MIF_FRAME_OUTPUT);
304                 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
305                         return val & MIF_FRAME_OUTPUT_DATA;
306
307                 udelay(10);
308         }
309
310         return -ENODEV;
311 }
312
313 static int mdio_read(struct niu *np, int port, int dev, int reg)
314 {
315         int err;
316
317         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
318         err = mdio_wait(np);
319         if (err < 0)
320                 return err;
321
322         nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
323         return mdio_wait(np);
324 }
325
326 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
327 {
328         int err;
329
330         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
331         err = mdio_wait(np);
332         if (err < 0)
333                 return err;
334
335         nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
336         err = mdio_wait(np);
337         if (err < 0)
338                 return err;
339
340         return 0;
341 }
342
343 static int mii_read(struct niu *np, int port, int reg)
344 {
345         nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
346         return mdio_wait(np);
347 }
348
349 static int mii_write(struct niu *np, int port, int reg, int data)
350 {
351         int err;
352
353         nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
354         err = mdio_wait(np);
355         if (err < 0)
356                 return err;
357
358         return 0;
359 }
360
361 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
362 {
363         int err;
364
365         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
366                          ESR2_TI_PLL_TX_CFG_L(channel),
367                          val & 0xffff);
368         if (!err)
369                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
370                                  ESR2_TI_PLL_TX_CFG_H(channel),
371                                  val >> 16);
372         return err;
373 }
374
375 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
376 {
377         int err;
378
379         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
380                          ESR2_TI_PLL_RX_CFG_L(channel),
381                          val & 0xffff);
382         if (!err)
383                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
384                                  ESR2_TI_PLL_RX_CFG_H(channel),
385                                  val >> 16);
386         return err;
387 }
388
389 /* Mode is always 10G fiber.  */
390 static int serdes_init_niu_10g_fiber(struct niu *np)
391 {
392         struct niu_link_config *lp = &np->link_config;
393         u32 tx_cfg, rx_cfg;
394         unsigned long i;
395
396         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
397         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
398                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
399                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
400
401         if (lp->loopback_mode == LOOPBACK_PHY) {
402                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
403
404                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
405                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
406
407                 tx_cfg |= PLL_TX_CFG_ENTEST;
408                 rx_cfg |= PLL_RX_CFG_ENTEST;
409         }
410
411         /* Initialize all 4 lanes of the SERDES.  */
412         for (i = 0; i < 4; i++) {
413                 int err = esr2_set_tx_cfg(np, i, tx_cfg);
414                 if (err)
415                         return err;
416         }
417
418         for (i = 0; i < 4; i++) {
419                 int err = esr2_set_rx_cfg(np, i, rx_cfg);
420                 if (err)
421                         return err;
422         }
423
424         return 0;
425 }
426
427 static int serdes_init_niu_1g_serdes(struct niu *np)
428 {
429         struct niu_link_config *lp = &np->link_config;
430         u16 pll_cfg, pll_sts;
431         int max_retry = 100;
432         u64 uninitialized_var(sig), mask, val;
433         u32 tx_cfg, rx_cfg;
434         unsigned long i;
435         int err;
436
437         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
438                   PLL_TX_CFG_RATE_HALF);
439         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
440                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
441                   PLL_RX_CFG_RATE_HALF);
442
443         if (np->port == 0)
444                 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
445
446         if (lp->loopback_mode == LOOPBACK_PHY) {
447                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
448
449                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
450                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
451
452                 tx_cfg |= PLL_TX_CFG_ENTEST;
453                 rx_cfg |= PLL_RX_CFG_ENTEST;
454         }
455
456         /* Initialize PLL for 1G */
457         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
458
459         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
460                          ESR2_TI_PLL_CFG_L, pll_cfg);
461         if (err) {
462                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
463                            np->port, __func__);
464                 return err;
465         }
466
467         pll_sts = PLL_CFG_ENPLL;
468
469         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
470                          ESR2_TI_PLL_STS_L, pll_sts);
471         if (err) {
472                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
473                            np->port, __func__);
474                 return err;
475         }
476
477         udelay(200);
478
479         /* Initialize all 4 lanes of the SERDES.  */
480         for (i = 0; i < 4; i++) {
481                 err = esr2_set_tx_cfg(np, i, tx_cfg);
482                 if (err)
483                         return err;
484         }
485
486         for (i = 0; i < 4; i++) {
487                 err = esr2_set_rx_cfg(np, i, rx_cfg);
488                 if (err)
489                         return err;
490         }
491
492         switch (np->port) {
493         case 0:
494                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
495                 mask = val;
496                 break;
497
498         case 1:
499                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
500                 mask = val;
501                 break;
502
503         default:
504                 return -EINVAL;
505         }
506
507         while (max_retry--) {
508                 sig = nr64(ESR_INT_SIGNALS);
509                 if ((sig & mask) == val)
510                         break;
511
512                 mdelay(500);
513         }
514
515         if ((sig & mask) != val) {
516                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
517                            np->port, (int)(sig & mask), (int)val);
518                 return -ENODEV;
519         }
520
521         return 0;
522 }
523
524 static int serdes_init_niu_10g_serdes(struct niu *np)
525 {
526         struct niu_link_config *lp = &np->link_config;
527         u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
528         int max_retry = 100;
529         u64 uninitialized_var(sig), mask, val;
530         unsigned long i;
531         int err;
532
533         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
534         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
535                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
536                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
537
538         if (lp->loopback_mode == LOOPBACK_PHY) {
539                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
540
541                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
542                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
543
544                 tx_cfg |= PLL_TX_CFG_ENTEST;
545                 rx_cfg |= PLL_RX_CFG_ENTEST;
546         }
547
548         /* Initialize PLL for 10G */
549         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
550
551         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
552                          ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
553         if (err) {
554                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
555                            np->port, __func__);
556                 return err;
557         }
558
559         pll_sts = PLL_CFG_ENPLL;
560
561         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
562                          ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
563         if (err) {
564                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
565                            np->port, __func__);
566                 return err;
567         }
568
569         udelay(200);
570
571         /* Initialize all 4 lanes of the SERDES.  */
572         for (i = 0; i < 4; i++) {
573                 err = esr2_set_tx_cfg(np, i, tx_cfg);
574                 if (err)
575                         return err;
576         }
577
578         for (i = 0; i < 4; i++) {
579                 err = esr2_set_rx_cfg(np, i, rx_cfg);
580                 if (err)
581                         return err;
582         }
583
584         /* check if serdes is ready */
585
586         switch (np->port) {
587         case 0:
588                 mask = ESR_INT_SIGNALS_P0_BITS;
589                 val = (ESR_INT_SRDY0_P0 |
590                        ESR_INT_DET0_P0 |
591                        ESR_INT_XSRDY_P0 |
592                        ESR_INT_XDP_P0_CH3 |
593                        ESR_INT_XDP_P0_CH2 |
594                        ESR_INT_XDP_P0_CH1 |
595                        ESR_INT_XDP_P0_CH0);
596                 break;
597
598         case 1:
599                 mask = ESR_INT_SIGNALS_P1_BITS;
600                 val = (ESR_INT_SRDY0_P1 |
601                        ESR_INT_DET0_P1 |
602                        ESR_INT_XSRDY_P1 |
603                        ESR_INT_XDP_P1_CH3 |
604                        ESR_INT_XDP_P1_CH2 |
605                        ESR_INT_XDP_P1_CH1 |
606                        ESR_INT_XDP_P1_CH0);
607                 break;
608
609         default:
610                 return -EINVAL;
611         }
612
613         while (max_retry--) {
614                 sig = nr64(ESR_INT_SIGNALS);
615                 if ((sig & mask) == val)
616                         break;
617
618                 mdelay(500);
619         }
620
621         if ((sig & mask) != val) {
622                 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
623                         np->port, (int)(sig & mask), (int)val);
624
625                 /* 10G failed, try initializing at 1G */
626                 err = serdes_init_niu_1g_serdes(np);
627                 if (!err) {
628                         np->flags &= ~NIU_FLAGS_10G;
629                         np->mac_xcvr = MAC_XCVR_PCS;
630                 }  else {
631                         netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
632                                    np->port);
633                         return -ENODEV;
634                 }
635         }
636         return 0;
637 }
638
639 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
640 {
641         int err;
642
643         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
644         if (err >= 0) {
645                 *val = (err & 0xffff);
646                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
647                                 ESR_RXTX_CTRL_H(chan));
648                 if (err >= 0)
649                         *val |= ((err & 0xffff) << 16);
650                 err = 0;
651         }
652         return err;
653 }
654
655 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
656 {
657         int err;
658
659         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
660                         ESR_GLUE_CTRL0_L(chan));
661         if (err >= 0) {
662                 *val = (err & 0xffff);
663                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
664                                 ESR_GLUE_CTRL0_H(chan));
665                 if (err >= 0) {
666                         *val |= ((err & 0xffff) << 16);
667                         err = 0;
668                 }
669         }
670         return err;
671 }
672
673 static int esr_read_reset(struct niu *np, u32 *val)
674 {
675         int err;
676
677         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
678                         ESR_RXTX_RESET_CTRL_L);
679         if (err >= 0) {
680                 *val = (err & 0xffff);
681                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
682                                 ESR_RXTX_RESET_CTRL_H);
683                 if (err >= 0) {
684                         *val |= ((err & 0xffff) << 16);
685                         err = 0;
686                 }
687         }
688         return err;
689 }
690
691 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
692 {
693         int err;
694
695         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
696                          ESR_RXTX_CTRL_L(chan), val & 0xffff);
697         if (!err)
698                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
699                                  ESR_RXTX_CTRL_H(chan), (val >> 16));
700         return err;
701 }
702
703 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
704 {
705         int err;
706
707         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
708                         ESR_GLUE_CTRL0_L(chan), val & 0xffff);
709         if (!err)
710                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
711                                  ESR_GLUE_CTRL0_H(chan), (val >> 16));
712         return err;
713 }
714
715 static int esr_reset(struct niu *np)
716 {
717         u32 uninitialized_var(reset);
718         int err;
719
720         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
721                          ESR_RXTX_RESET_CTRL_L, 0x0000);
722         if (err)
723                 return err;
724         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
725                          ESR_RXTX_RESET_CTRL_H, 0xffff);
726         if (err)
727                 return err;
728         udelay(200);
729
730         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
731                          ESR_RXTX_RESET_CTRL_L, 0xffff);
732         if (err)
733                 return err;
734         udelay(200);
735
736         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
737                          ESR_RXTX_RESET_CTRL_H, 0x0000);
738         if (err)
739                 return err;
740         udelay(200);
741
742         err = esr_read_reset(np, &reset);
743         if (err)
744                 return err;
745         if (reset != 0) {
746                 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
747                            np->port, reset);
748                 return -ENODEV;
749         }
750
751         return 0;
752 }
753
754 static int serdes_init_10g(struct niu *np)
755 {
756         struct niu_link_config *lp = &np->link_config;
757         unsigned long ctrl_reg, test_cfg_reg, i;
758         u64 ctrl_val, test_cfg_val, sig, mask, val;
759         int err;
760
761         switch (np->port) {
762         case 0:
763                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
764                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
765                 break;
766         case 1:
767                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
768                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
769                 break;
770
771         default:
772                 return -EINVAL;
773         }
774         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
775                     ENET_SERDES_CTRL_SDET_1 |
776                     ENET_SERDES_CTRL_SDET_2 |
777                     ENET_SERDES_CTRL_SDET_3 |
778                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
779                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
780                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
781                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
782                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
783                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
784                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
785                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
786         test_cfg_val = 0;
787
788         if (lp->loopback_mode == LOOPBACK_PHY) {
789                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
790                                   ENET_SERDES_TEST_MD_0_SHIFT) |
791                                  (ENET_TEST_MD_PAD_LOOPBACK <<
792                                   ENET_SERDES_TEST_MD_1_SHIFT) |
793                                  (ENET_TEST_MD_PAD_LOOPBACK <<
794                                   ENET_SERDES_TEST_MD_2_SHIFT) |
795                                  (ENET_TEST_MD_PAD_LOOPBACK <<
796                                   ENET_SERDES_TEST_MD_3_SHIFT));
797         }
798
799         nw64(ctrl_reg, ctrl_val);
800         nw64(test_cfg_reg, test_cfg_val);
801
802         /* Initialize all 4 lanes of the SERDES.  */
803         for (i = 0; i < 4; i++) {
804                 u32 rxtx_ctrl, glue0;
805
806                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
807                 if (err)
808                         return err;
809                 err = esr_read_glue0(np, i, &glue0);
810                 if (err)
811                         return err;
812
813                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
814                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
815                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
816
817                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
818                            ESR_GLUE_CTRL0_THCNT |
819                            ESR_GLUE_CTRL0_BLTIME);
820                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
821                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
822                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
823                           (BLTIME_300_CYCLES <<
824                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
825
826                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
827                 if (err)
828                         return err;
829                 err = esr_write_glue0(np, i, glue0);
830                 if (err)
831                         return err;
832         }
833
834         err = esr_reset(np);
835         if (err)
836                 return err;
837
838         sig = nr64(ESR_INT_SIGNALS);
839         switch (np->port) {
840         case 0:
841                 mask = ESR_INT_SIGNALS_P0_BITS;
842                 val = (ESR_INT_SRDY0_P0 |
843                        ESR_INT_DET0_P0 |
844                        ESR_INT_XSRDY_P0 |
845                        ESR_INT_XDP_P0_CH3 |
846                        ESR_INT_XDP_P0_CH2 |
847                        ESR_INT_XDP_P0_CH1 |
848                        ESR_INT_XDP_P0_CH0);
849                 break;
850
851         case 1:
852                 mask = ESR_INT_SIGNALS_P1_BITS;
853                 val = (ESR_INT_SRDY0_P1 |
854                        ESR_INT_DET0_P1 |
855                        ESR_INT_XSRDY_P1 |
856                        ESR_INT_XDP_P1_CH3 |
857                        ESR_INT_XDP_P1_CH2 |
858                        ESR_INT_XDP_P1_CH1 |
859                        ESR_INT_XDP_P1_CH0);
860                 break;
861
862         default:
863                 return -EINVAL;
864         }
865
866         if ((sig & mask) != val) {
867                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
868                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
869                         return 0;
870                 }
871                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
872                            np->port, (int)(sig & mask), (int)val);
873                 return -ENODEV;
874         }
875         if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
876                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
877         return 0;
878 }
879
880 static int serdes_init_1g(struct niu *np)
881 {
882         u64 val;
883
884         val = nr64(ENET_SERDES_1_PLL_CFG);
885         val &= ~ENET_SERDES_PLL_FBDIV2;
886         switch (np->port) {
887         case 0:
888                 val |= ENET_SERDES_PLL_HRATE0;
889                 break;
890         case 1:
891                 val |= ENET_SERDES_PLL_HRATE1;
892                 break;
893         case 2:
894                 val |= ENET_SERDES_PLL_HRATE2;
895                 break;
896         case 3:
897                 val |= ENET_SERDES_PLL_HRATE3;
898                 break;
899         default:
900                 return -EINVAL;
901         }
902         nw64(ENET_SERDES_1_PLL_CFG, val);
903
904         return 0;
905 }
906
907 static int serdes_init_1g_serdes(struct niu *np)
908 {
909         struct niu_link_config *lp = &np->link_config;
910         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
911         u64 ctrl_val, test_cfg_val, sig, mask, val;
912         int err;
913         u64 reset_val, val_rd;
914
915         val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
916                 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
917                 ENET_SERDES_PLL_FBDIV0;
918         switch (np->port) {
919         case 0:
920                 reset_val =  ENET_SERDES_RESET_0;
921                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
922                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
923                 pll_cfg = ENET_SERDES_0_PLL_CFG;
924                 break;
925         case 1:
926                 reset_val =  ENET_SERDES_RESET_1;
927                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
928                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
929                 pll_cfg = ENET_SERDES_1_PLL_CFG;
930                 break;
931
932         default:
933                 return -EINVAL;
934         }
935         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
936                     ENET_SERDES_CTRL_SDET_1 |
937                     ENET_SERDES_CTRL_SDET_2 |
938                     ENET_SERDES_CTRL_SDET_3 |
939                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
940                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
941                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
942                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
943                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
944                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
945                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
946                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
947         test_cfg_val = 0;
948
949         if (lp->loopback_mode == LOOPBACK_PHY) {
950                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
951                                   ENET_SERDES_TEST_MD_0_SHIFT) |
952                                  (ENET_TEST_MD_PAD_LOOPBACK <<
953                                   ENET_SERDES_TEST_MD_1_SHIFT) |
954                                  (ENET_TEST_MD_PAD_LOOPBACK <<
955                                   ENET_SERDES_TEST_MD_2_SHIFT) |
956                                  (ENET_TEST_MD_PAD_LOOPBACK <<
957                                   ENET_SERDES_TEST_MD_3_SHIFT));
958         }
959
960         nw64(ENET_SERDES_RESET, reset_val);
961         mdelay(20);
962         val_rd = nr64(ENET_SERDES_RESET);
963         val_rd &= ~reset_val;
964         nw64(pll_cfg, val);
965         nw64(ctrl_reg, ctrl_val);
966         nw64(test_cfg_reg, test_cfg_val);
967         nw64(ENET_SERDES_RESET, val_rd);
968         mdelay(2000);
969
970         /* Initialize all 4 lanes of the SERDES.  */
971         for (i = 0; i < 4; i++) {
972                 u32 rxtx_ctrl, glue0;
973
974                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
975                 if (err)
976                         return err;
977                 err = esr_read_glue0(np, i, &glue0);
978                 if (err)
979                         return err;
980
981                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
982                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
983                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
984
985                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
986                            ESR_GLUE_CTRL0_THCNT |
987                            ESR_GLUE_CTRL0_BLTIME);
988                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
989                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
990                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
991                           (BLTIME_300_CYCLES <<
992                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
993
994                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
995                 if (err)
996                         return err;
997                 err = esr_write_glue0(np, i, glue0);
998                 if (err)
999                         return err;
1000         }
1001
1002
1003         sig = nr64(ESR_INT_SIGNALS);
1004         switch (np->port) {
1005         case 0:
1006                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1007                 mask = val;
1008                 break;
1009
1010         case 1:
1011                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1012                 mask = val;
1013                 break;
1014
1015         default:
1016                 return -EINVAL;
1017         }
1018
1019         if ((sig & mask) != val) {
1020                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1021                            np->port, (int)(sig & mask), (int)val);
1022                 return -ENODEV;
1023         }
1024
1025         return 0;
1026 }
1027
1028 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1029 {
1030         struct niu_link_config *lp = &np->link_config;
1031         int link_up;
1032         u64 val;
1033         u16 current_speed;
1034         unsigned long flags;
1035         u8 current_duplex;
1036
1037         link_up = 0;
1038         current_speed = SPEED_INVALID;
1039         current_duplex = DUPLEX_INVALID;
1040
1041         spin_lock_irqsave(&np->lock, flags);
1042
1043         val = nr64_pcs(PCS_MII_STAT);
1044
1045         if (val & PCS_MII_STAT_LINK_STATUS) {
1046                 link_up = 1;
1047                 current_speed = SPEED_1000;
1048                 current_duplex = DUPLEX_FULL;
1049         }
1050
1051         lp->active_speed = current_speed;
1052         lp->active_duplex = current_duplex;
1053         spin_unlock_irqrestore(&np->lock, flags);
1054
1055         *link_up_p = link_up;
1056         return 0;
1057 }
1058
1059 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1060 {
1061         unsigned long flags;
1062         struct niu_link_config *lp = &np->link_config;
1063         int link_up = 0;
1064         int link_ok = 1;
1065         u64 val, val2;
1066         u16 current_speed;
1067         u8 current_duplex;
1068
1069         if (!(np->flags & NIU_FLAGS_10G))
1070                 return link_status_1g_serdes(np, link_up_p);
1071
1072         current_speed = SPEED_INVALID;
1073         current_duplex = DUPLEX_INVALID;
1074         spin_lock_irqsave(&np->lock, flags);
1075
1076         val = nr64_xpcs(XPCS_STATUS(0));
1077         val2 = nr64_mac(XMAC_INTER2);
1078         if (val2 & 0x01000000)
1079                 link_ok = 0;
1080
1081         if ((val & 0x1000ULL) && link_ok) {
1082                 link_up = 1;
1083                 current_speed = SPEED_10000;
1084                 current_duplex = DUPLEX_FULL;
1085         }
1086         lp->active_speed = current_speed;
1087         lp->active_duplex = current_duplex;
1088         spin_unlock_irqrestore(&np->lock, flags);
1089         *link_up_p = link_up;
1090         return 0;
1091 }
1092
1093 static int link_status_mii(struct niu *np, int *link_up_p)
1094 {
1095         struct niu_link_config *lp = &np->link_config;
1096         int err;
1097         int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1098         int supported, advertising, active_speed, active_duplex;
1099
1100         err = mii_read(np, np->phy_addr, MII_BMCR);
1101         if (unlikely(err < 0))
1102                 return err;
1103         bmcr = err;
1104
1105         err = mii_read(np, np->phy_addr, MII_BMSR);
1106         if (unlikely(err < 0))
1107                 return err;
1108         bmsr = err;
1109
1110         err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1111         if (unlikely(err < 0))
1112                 return err;
1113         advert = err;
1114
1115         err = mii_read(np, np->phy_addr, MII_LPA);
1116         if (unlikely(err < 0))
1117                 return err;
1118         lpa = err;
1119
1120         if (likely(bmsr & BMSR_ESTATEN)) {
1121                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1122                 if (unlikely(err < 0))
1123                         return err;
1124                 estatus = err;
1125
1126                 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1127                 if (unlikely(err < 0))
1128                         return err;
1129                 ctrl1000 = err;
1130
1131                 err = mii_read(np, np->phy_addr, MII_STAT1000);
1132                 if (unlikely(err < 0))
1133                         return err;
1134                 stat1000 = err;
1135         } else
1136                 estatus = ctrl1000 = stat1000 = 0;
1137
1138         supported = 0;
1139         if (bmsr & BMSR_ANEGCAPABLE)
1140                 supported |= SUPPORTED_Autoneg;
1141         if (bmsr & BMSR_10HALF)
1142                 supported |= SUPPORTED_10baseT_Half;
1143         if (bmsr & BMSR_10FULL)
1144                 supported |= SUPPORTED_10baseT_Full;
1145         if (bmsr & BMSR_100HALF)
1146                 supported |= SUPPORTED_100baseT_Half;
1147         if (bmsr & BMSR_100FULL)
1148                 supported |= SUPPORTED_100baseT_Full;
1149         if (estatus & ESTATUS_1000_THALF)
1150                 supported |= SUPPORTED_1000baseT_Half;
1151         if (estatus & ESTATUS_1000_TFULL)
1152                 supported |= SUPPORTED_1000baseT_Full;
1153         lp->supported = supported;
1154
1155         advertising = 0;
1156         if (advert & ADVERTISE_10HALF)
1157                 advertising |= ADVERTISED_10baseT_Half;
1158         if (advert & ADVERTISE_10FULL)
1159                 advertising |= ADVERTISED_10baseT_Full;
1160         if (advert & ADVERTISE_100HALF)
1161                 advertising |= ADVERTISED_100baseT_Half;
1162         if (advert & ADVERTISE_100FULL)
1163                 advertising |= ADVERTISED_100baseT_Full;
1164         if (ctrl1000 & ADVERTISE_1000HALF)
1165                 advertising |= ADVERTISED_1000baseT_Half;
1166         if (ctrl1000 & ADVERTISE_1000FULL)
1167                 advertising |= ADVERTISED_1000baseT_Full;
1168
1169         if (bmcr & BMCR_ANENABLE) {
1170                 int neg, neg1000;
1171
1172                 lp->active_autoneg = 1;
1173                 advertising |= ADVERTISED_Autoneg;
1174
1175                 neg = advert & lpa;
1176                 neg1000 = (ctrl1000 << 2) & stat1000;
1177
1178                 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1179                         active_speed = SPEED_1000;
1180                 else if (neg & LPA_100)
1181                         active_speed = SPEED_100;
1182                 else if (neg & (LPA_10HALF | LPA_10FULL))
1183                         active_speed = SPEED_10;
1184                 else
1185                         active_speed = SPEED_INVALID;
1186
1187                 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1188                         active_duplex = DUPLEX_FULL;
1189                 else if (active_speed != SPEED_INVALID)
1190                         active_duplex = DUPLEX_HALF;
1191                 else
1192                         active_duplex = DUPLEX_INVALID;
1193         } else {
1194                 lp->active_autoneg = 0;
1195
1196                 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1197                         active_speed = SPEED_1000;
1198                 else if (bmcr & BMCR_SPEED100)
1199                         active_speed = SPEED_100;
1200                 else
1201                         active_speed = SPEED_10;
1202
1203                 if (bmcr & BMCR_FULLDPLX)
1204                         active_duplex = DUPLEX_FULL;
1205                 else
1206                         active_duplex = DUPLEX_HALF;
1207         }
1208
1209         lp->active_advertising = advertising;
1210         lp->active_speed = active_speed;
1211         lp->active_duplex = active_duplex;
1212         *link_up_p = !!(bmsr & BMSR_LSTATUS);
1213
1214         return 0;
1215 }
1216
1217 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1218 {
1219         struct niu_link_config *lp = &np->link_config;
1220         u16 current_speed, bmsr;
1221         unsigned long flags;
1222         u8 current_duplex;
1223         int err, link_up;
1224
1225         link_up = 0;
1226         current_speed = SPEED_INVALID;
1227         current_duplex = DUPLEX_INVALID;
1228
1229         spin_lock_irqsave(&np->lock, flags);
1230
1231         err = -EINVAL;
1232
1233         err = mii_read(np, np->phy_addr, MII_BMSR);
1234         if (err < 0)
1235                 goto out;
1236
1237         bmsr = err;
1238         if (bmsr & BMSR_LSTATUS) {
1239                 u16 adv, lpa, common, estat;
1240
1241                 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1242                 if (err < 0)
1243                         goto out;
1244                 adv = err;
1245
1246                 err = mii_read(np, np->phy_addr, MII_LPA);
1247                 if (err < 0)
1248                         goto out;
1249                 lpa = err;
1250
1251                 common = adv & lpa;
1252
1253                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1254                 if (err < 0)
1255                         goto out;
1256                 estat = err;
1257                 link_up = 1;
1258                 current_speed = SPEED_1000;
1259                 current_duplex = DUPLEX_FULL;
1260
1261         }
1262         lp->active_speed = current_speed;
1263         lp->active_duplex = current_duplex;
1264         err = 0;
1265
1266 out:
1267         spin_unlock_irqrestore(&np->lock, flags);
1268
1269         *link_up_p = link_up;
1270         return err;
1271 }
1272
1273 static int link_status_1g(struct niu *np, int *link_up_p)
1274 {
1275         struct niu_link_config *lp = &np->link_config;
1276         unsigned long flags;
1277         int err;
1278
1279         spin_lock_irqsave(&np->lock, flags);
1280
1281         err = link_status_mii(np, link_up_p);
1282         lp->supported |= SUPPORTED_TP;
1283         lp->active_advertising |= ADVERTISED_TP;
1284
1285         spin_unlock_irqrestore(&np->lock, flags);
1286         return err;
1287 }
1288
1289 static int bcm8704_reset(struct niu *np)
1290 {
1291         int err, limit;
1292
1293         err = mdio_read(np, np->phy_addr,
1294                         BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1295         if (err < 0 || err == 0xffff)
1296                 return err;
1297         err |= BMCR_RESET;
1298         err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1299                          MII_BMCR, err);
1300         if (err)
1301                 return err;
1302
1303         limit = 1000;
1304         while (--limit >= 0) {
1305                 err = mdio_read(np, np->phy_addr,
1306                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1307                 if (err < 0)
1308                         return err;
1309                 if (!(err & BMCR_RESET))
1310                         break;
1311         }
1312         if (limit < 0) {
1313                 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1314                            np->port, (err & 0xffff));
1315                 return -ENODEV;
1316         }
1317         return 0;
1318 }
1319
1320 /* When written, certain PHY registers need to be read back twice
1321  * in order for the bits to settle properly.
1322  */
1323 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1324 {
1325         int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1326         if (err < 0)
1327                 return err;
1328         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1329         if (err < 0)
1330                 return err;
1331         return 0;
1332 }
1333
1334 static int bcm8706_init_user_dev3(struct niu *np)
1335 {
1336         int err;
1337
1338
1339         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1340                         BCM8704_USER_OPT_DIGITAL_CTRL);
1341         if (err < 0)
1342                 return err;
1343         err &= ~USER_ODIG_CTRL_GPIOS;
1344         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1345         err |=  USER_ODIG_CTRL_RESV2;
1346         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1347                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1348         if (err)
1349                 return err;
1350
1351         mdelay(1000);
1352
1353         return 0;
1354 }
1355
1356 static int bcm8704_init_user_dev3(struct niu *np)
1357 {
1358         int err;
1359
1360         err = mdio_write(np, np->phy_addr,
1361                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1362                          (USER_CONTROL_OPTXRST_LVL |
1363                           USER_CONTROL_OPBIASFLT_LVL |
1364                           USER_CONTROL_OBTMPFLT_LVL |
1365                           USER_CONTROL_OPPRFLT_LVL |
1366                           USER_CONTROL_OPTXFLT_LVL |
1367                           USER_CONTROL_OPRXLOS_LVL |
1368                           USER_CONTROL_OPRXFLT_LVL |
1369                           USER_CONTROL_OPTXON_LVL |
1370                           (0x3f << USER_CONTROL_RES1_SHIFT)));
1371         if (err)
1372                 return err;
1373
1374         err = mdio_write(np, np->phy_addr,
1375                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1376                          (USER_PMD_TX_CTL_XFP_CLKEN |
1377                           (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1378                           (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1379                           USER_PMD_TX_CTL_TSCK_LPWREN));
1380         if (err)
1381                 return err;
1382
1383         err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1384         if (err)
1385                 return err;
1386         err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1387         if (err)
1388                 return err;
1389
1390         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1391                         BCM8704_USER_OPT_DIGITAL_CTRL);
1392         if (err < 0)
1393                 return err;
1394         err &= ~USER_ODIG_CTRL_GPIOS;
1395         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1396         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1397                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1398         if (err)
1399                 return err;
1400
1401         mdelay(1000);
1402
1403         return 0;
1404 }
1405
1406 static int mrvl88x2011_act_led(struct niu *np, int val)
1407 {
1408         int     err;
1409
1410         err  = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1411                 MRVL88X2011_LED_8_TO_11_CTL);
1412         if (err < 0)
1413                 return err;
1414
1415         err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1416         err |=  MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1417
1418         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1419                           MRVL88X2011_LED_8_TO_11_CTL, err);
1420 }
1421
1422 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1423 {
1424         int     err;
1425
1426         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1427                         MRVL88X2011_LED_BLINK_CTL);
1428         if (err >= 0) {
1429                 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1430                 err |= (rate << 4);
1431
1432                 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1433                                  MRVL88X2011_LED_BLINK_CTL, err);
1434         }
1435
1436         return err;
1437 }
1438
1439 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1440 {
1441         int     err;
1442
1443         /* Set LED functions */
1444         err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1445         if (err)
1446                 return err;
1447
1448         /* led activity */
1449         err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1450         if (err)
1451                 return err;
1452
1453         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1454                         MRVL88X2011_GENERAL_CTL);
1455         if (err < 0)
1456                 return err;
1457
1458         err |= MRVL88X2011_ENA_XFPREFCLK;
1459
1460         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1461                          MRVL88X2011_GENERAL_CTL, err);
1462         if (err < 0)
1463                 return err;
1464
1465         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1466                         MRVL88X2011_PMA_PMD_CTL_1);
1467         if (err < 0)
1468                 return err;
1469
1470         if (np->link_config.loopback_mode == LOOPBACK_MAC)
1471                 err |= MRVL88X2011_LOOPBACK;
1472         else
1473                 err &= ~MRVL88X2011_LOOPBACK;
1474
1475         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1476                          MRVL88X2011_PMA_PMD_CTL_1, err);
1477         if (err < 0)
1478                 return err;
1479
1480         /* Enable PMD  */
1481         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1482                           MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1483 }
1484
1485
1486 static int xcvr_diag_bcm870x(struct niu *np)
1487 {
1488         u16 analog_stat0, tx_alarm_status;
1489         int err = 0;
1490
1491 #if 1
1492         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1493                         MII_STAT1000);
1494         if (err < 0)
1495                 return err;
1496         pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
1497
1498         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1499         if (err < 0)
1500                 return err;
1501         pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
1502
1503         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1504                         MII_NWAYTEST);
1505         if (err < 0)
1506                 return err;
1507         pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
1508 #endif
1509
1510         /* XXX dig this out it might not be so useful XXX */
1511         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1512                         BCM8704_USER_ANALOG_STATUS0);
1513         if (err < 0)
1514                 return err;
1515         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1516                         BCM8704_USER_ANALOG_STATUS0);
1517         if (err < 0)
1518                 return err;
1519         analog_stat0 = err;
1520
1521         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1522                         BCM8704_USER_TX_ALARM_STATUS);
1523         if (err < 0)
1524                 return err;
1525         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1526                         BCM8704_USER_TX_ALARM_STATUS);
1527         if (err < 0)
1528                 return err;
1529         tx_alarm_status = err;
1530
1531         if (analog_stat0 != 0x03fc) {
1532                 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1533                         pr_info("Port %u cable not connected or bad cable\n",
1534                                 np->port);
1535                 } else if (analog_stat0 == 0x639c) {
1536                         pr_info("Port %u optical module is bad or missing\n",
1537                                 np->port);
1538                 }
1539         }
1540
1541         return 0;
1542 }
1543
1544 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1545 {
1546         struct niu_link_config *lp = &np->link_config;
1547         int err;
1548
1549         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1550                         MII_BMCR);
1551         if (err < 0)
1552                 return err;
1553
1554         err &= ~BMCR_LOOPBACK;
1555
1556         if (lp->loopback_mode == LOOPBACK_MAC)
1557                 err |= BMCR_LOOPBACK;
1558
1559         err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1560                          MII_BMCR, err);
1561         if (err)
1562                 return err;
1563
1564         return 0;
1565 }
1566
1567 static int xcvr_init_10g_bcm8706(struct niu *np)
1568 {
1569         int err = 0;
1570         u64 val;
1571
1572         if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1573             (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1574                         return err;
1575
1576         val = nr64_mac(XMAC_CONFIG);
1577         val &= ~XMAC_CONFIG_LED_POLARITY;
1578         val |= XMAC_CONFIG_FORCE_LED_ON;
1579         nw64_mac(XMAC_CONFIG, val);
1580
1581         val = nr64(MIF_CONFIG);
1582         val |= MIF_CONFIG_INDIRECT_MODE;
1583         nw64(MIF_CONFIG, val);
1584
1585         err = bcm8704_reset(np);
1586         if (err)
1587                 return err;
1588
1589         err = xcvr_10g_set_lb_bcm870x(np);
1590         if (err)
1591                 return err;
1592
1593         err = bcm8706_init_user_dev3(np);
1594         if (err)
1595                 return err;
1596
1597         err = xcvr_diag_bcm870x(np);
1598         if (err)
1599                 return err;
1600
1601         return 0;
1602 }
1603
1604 static int xcvr_init_10g_bcm8704(struct niu *np)
1605 {
1606         int err;
1607
1608         err = bcm8704_reset(np);
1609         if (err)
1610                 return err;
1611
1612         err = bcm8704_init_user_dev3(np);
1613         if (err)
1614                 return err;
1615
1616         err = xcvr_10g_set_lb_bcm870x(np);
1617         if (err)
1618                 return err;
1619
1620         err =  xcvr_diag_bcm870x(np);
1621         if (err)
1622                 return err;
1623
1624         return 0;
1625 }
1626
1627 static int xcvr_init_10g(struct niu *np)
1628 {
1629         int phy_id, err;
1630         u64 val;
1631
1632         val = nr64_mac(XMAC_CONFIG);
1633         val &= ~XMAC_CONFIG_LED_POLARITY;
1634         val |= XMAC_CONFIG_FORCE_LED_ON;
1635         nw64_mac(XMAC_CONFIG, val);
1636
1637         /* XXX shared resource, lock parent XXX */
1638         val = nr64(MIF_CONFIG);
1639         val |= MIF_CONFIG_INDIRECT_MODE;
1640         nw64(MIF_CONFIG, val);
1641
1642         phy_id = phy_decode(np->parent->port_phy, np->port);
1643         phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1644
1645         /* handle different phy types */
1646         switch (phy_id & NIU_PHY_ID_MASK) {
1647         case NIU_PHY_ID_MRVL88X2011:
1648                 err = xcvr_init_10g_mrvl88x2011(np);
1649                 break;
1650
1651         default: /* bcom 8704 */
1652                 err = xcvr_init_10g_bcm8704(np);
1653                 break;
1654         }
1655
1656         return 0;
1657 }
1658
1659 static int mii_reset(struct niu *np)
1660 {
1661         int limit, err;
1662
1663         err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1664         if (err)
1665                 return err;
1666
1667         limit = 1000;
1668         while (--limit >= 0) {
1669                 udelay(500);
1670                 err = mii_read(np, np->phy_addr, MII_BMCR);
1671                 if (err < 0)
1672                         return err;
1673                 if (!(err & BMCR_RESET))
1674                         break;
1675         }
1676         if (limit < 0) {
1677                 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1678                            np->port, err);
1679                 return -ENODEV;
1680         }
1681
1682         return 0;
1683 }
1684
1685 static int xcvr_init_1g_rgmii(struct niu *np)
1686 {
1687         int err;
1688         u64 val;
1689         u16 bmcr, bmsr, estat;
1690
1691         val = nr64(MIF_CONFIG);
1692         val &= ~MIF_CONFIG_INDIRECT_MODE;
1693         nw64(MIF_CONFIG, val);
1694
1695         err = mii_reset(np);
1696         if (err)
1697                 return err;
1698
1699         err = mii_read(np, np->phy_addr, MII_BMSR);
1700         if (err < 0)
1701                 return err;
1702         bmsr = err;
1703
1704         estat = 0;
1705         if (bmsr & BMSR_ESTATEN) {
1706                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1707                 if (err < 0)
1708                         return err;
1709                 estat = err;
1710         }
1711
1712         bmcr = 0;
1713         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1714         if (err)
1715                 return err;
1716
1717         if (bmsr & BMSR_ESTATEN) {
1718                 u16 ctrl1000 = 0;
1719
1720                 if (estat & ESTATUS_1000_TFULL)
1721                         ctrl1000 |= ADVERTISE_1000FULL;
1722                 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1723                 if (err)
1724                         return err;
1725         }
1726
1727         bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1728
1729         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1730         if (err)
1731                 return err;
1732
1733         err = mii_read(np, np->phy_addr, MII_BMCR);
1734         if (err < 0)
1735                 return err;
1736         bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1737
1738         err = mii_read(np, np->phy_addr, MII_BMSR);
1739         if (err < 0)
1740                 return err;
1741
1742         return 0;
1743 }
1744
1745 static int mii_init_common(struct niu *np)
1746 {
1747         struct niu_link_config *lp = &np->link_config;
1748         u16 bmcr, bmsr, adv, estat;
1749         int err;
1750
1751         err = mii_reset(np);
1752         if (err)
1753                 return err;
1754
1755         err = mii_read(np, np->phy_addr, MII_BMSR);
1756         if (err < 0)
1757                 return err;
1758         bmsr = err;
1759
1760         estat = 0;
1761         if (bmsr & BMSR_ESTATEN) {
1762                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1763                 if (err < 0)
1764                         return err;
1765                 estat = err;
1766         }
1767
1768         bmcr = 0;
1769         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1770         if (err)
1771                 return err;
1772
1773         if (lp->loopback_mode == LOOPBACK_MAC) {
1774                 bmcr |= BMCR_LOOPBACK;
1775                 if (lp->active_speed == SPEED_1000)
1776                         bmcr |= BMCR_SPEED1000;
1777                 if (lp->active_duplex == DUPLEX_FULL)
1778                         bmcr |= BMCR_FULLDPLX;
1779         }
1780
1781         if (lp->loopback_mode == LOOPBACK_PHY) {
1782                 u16 aux;
1783
1784                 aux = (BCM5464R_AUX_CTL_EXT_LB |
1785                        BCM5464R_AUX_CTL_WRITE_1);
1786                 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1787                 if (err)
1788                         return err;
1789         }
1790
1791         if (lp->autoneg) {
1792                 u16 ctrl1000;
1793
1794                 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1795                 if ((bmsr & BMSR_10HALF) &&
1796                         (lp->advertising & ADVERTISED_10baseT_Half))
1797                         adv |= ADVERTISE_10HALF;
1798                 if ((bmsr & BMSR_10FULL) &&
1799                         (lp->advertising & ADVERTISED_10baseT_Full))
1800                         adv |= ADVERTISE_10FULL;
1801                 if ((bmsr & BMSR_100HALF) &&
1802                         (lp->advertising & ADVERTISED_100baseT_Half))
1803                         adv |= ADVERTISE_100HALF;
1804                 if ((bmsr & BMSR_100FULL) &&
1805                         (lp->advertising & ADVERTISED_100baseT_Full))
1806                         adv |= ADVERTISE_100FULL;
1807                 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1808                 if (err)
1809                         return err;
1810
1811                 if (likely(bmsr & BMSR_ESTATEN)) {
1812                         ctrl1000 = 0;
1813                         if ((estat & ESTATUS_1000_THALF) &&
1814                                 (lp->advertising & ADVERTISED_1000baseT_Half))
1815                                 ctrl1000 |= ADVERTISE_1000HALF;
1816                         if ((estat & ESTATUS_1000_TFULL) &&
1817                                 (lp->advertising & ADVERTISED_1000baseT_Full))
1818                                 ctrl1000 |= ADVERTISE_1000FULL;
1819                         err = mii_write(np, np->phy_addr,
1820                                         MII_CTRL1000, ctrl1000);
1821                         if (err)
1822                                 return err;
1823                 }
1824
1825                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1826         } else {
1827                 /* !lp->autoneg */
1828                 int fulldpx;
1829
1830                 if (lp->duplex == DUPLEX_FULL) {
1831                         bmcr |= BMCR_FULLDPLX;
1832                         fulldpx = 1;
1833                 } else if (lp->duplex == DUPLEX_HALF)
1834                         fulldpx = 0;
1835                 else
1836                         return -EINVAL;
1837
1838                 if (lp->speed == SPEED_1000) {
1839                         /* if X-full requested while not supported, or
1840                            X-half requested while not supported... */
1841                         if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1842                                 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1843                                 return -EINVAL;
1844                         bmcr |= BMCR_SPEED1000;
1845                 } else if (lp->speed == SPEED_100) {
1846                         if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1847                                 (!fulldpx && !(bmsr & BMSR_100HALF)))
1848                                 return -EINVAL;
1849                         bmcr |= BMCR_SPEED100;
1850                 } else if (lp->speed == SPEED_10) {
1851                         if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1852                                 (!fulldpx && !(bmsr & BMSR_10HALF)))
1853                                 return -EINVAL;
1854                 } else
1855                         return -EINVAL;
1856         }
1857
1858         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1859         if (err)
1860                 return err;
1861
1862 #if 0
1863         err = mii_read(np, np->phy_addr, MII_BMCR);
1864         if (err < 0)
1865                 return err;
1866         bmcr = err;
1867
1868         err = mii_read(np, np->phy_addr, MII_BMSR);
1869         if (err < 0)
1870                 return err;
1871         bmsr = err;
1872
1873         pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1874                 np->port, bmcr, bmsr);
1875 #endif
1876
1877         return 0;
1878 }
1879
1880 static int xcvr_init_1g(struct niu *np)
1881 {
1882         u64 val;
1883
1884         /* XXX shared resource, lock parent XXX */
1885         val = nr64(MIF_CONFIG);
1886         val &= ~MIF_CONFIG_INDIRECT_MODE;
1887         nw64(MIF_CONFIG, val);
1888
1889         return mii_init_common(np);
1890 }
1891
1892 static int niu_xcvr_init(struct niu *np)
1893 {
1894         const struct niu_phy_ops *ops = np->phy_ops;
1895         int err;
1896
1897         err = 0;
1898         if (ops->xcvr_init)
1899                 err = ops->xcvr_init(np);
1900
1901         return err;
1902 }
1903
1904 static int niu_serdes_init(struct niu *np)
1905 {
1906         const struct niu_phy_ops *ops = np->phy_ops;
1907         int err;
1908
1909         err = 0;
1910         if (ops->serdes_init)
1911                 err = ops->serdes_init(np);
1912
1913         return err;
1914 }
1915
1916 static void niu_init_xif(struct niu *);
1917 static void niu_handle_led(struct niu *, int status);
1918
1919 static int niu_link_status_common(struct niu *np, int link_up)
1920 {
1921         struct niu_link_config *lp = &np->link_config;
1922         struct net_device *dev = np->dev;
1923         unsigned long flags;
1924
1925         if (!netif_carrier_ok(dev) && link_up) {
1926                 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1927                            lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1928                            lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1929                            lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1930                            "10Mbit/sec",
1931                            lp->active_duplex == DUPLEX_FULL ? "full" : "half");
1932
1933                 spin_lock_irqsave(&np->lock, flags);
1934                 niu_init_xif(np);
1935                 niu_handle_led(np, 1);
1936                 spin_unlock_irqrestore(&np->lock, flags);
1937
1938                 netif_carrier_on(dev);
1939         } else if (netif_carrier_ok(dev) && !link_up) {
1940                 netif_warn(np, link, dev, "Link is down\n");
1941                 spin_lock_irqsave(&np->lock, flags);
1942                 niu_handle_led(np, 0);
1943                 spin_unlock_irqrestore(&np->lock, flags);
1944                 netif_carrier_off(dev);
1945         }
1946
1947         return 0;
1948 }
1949
1950 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1951 {
1952         int err, link_up, pma_status, pcs_status;
1953
1954         link_up = 0;
1955
1956         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1957                         MRVL88X2011_10G_PMD_STATUS_2);
1958         if (err < 0)
1959                 goto out;
1960
1961         /* Check PMA/PMD Register: 1.0001.2 == 1 */
1962         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1963                         MRVL88X2011_PMA_PMD_STATUS_1);
1964         if (err < 0)
1965                 goto out;
1966
1967         pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1968
1969         /* Check PMC Register : 3.0001.2 == 1: read twice */
1970         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1971                         MRVL88X2011_PMA_PMD_STATUS_1);
1972         if (err < 0)
1973                 goto out;
1974
1975         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1976                         MRVL88X2011_PMA_PMD_STATUS_1);
1977         if (err < 0)
1978                 goto out;
1979
1980         pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1981
1982         /* Check XGXS Register : 4.0018.[0-3,12] */
1983         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1984                         MRVL88X2011_10G_XGXS_LANE_STAT);
1985         if (err < 0)
1986                 goto out;
1987
1988         if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1989                     PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1990                     PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1991                     0x800))
1992                 link_up = (pma_status && pcs_status) ? 1 : 0;
1993
1994         np->link_config.active_speed = SPEED_10000;
1995         np->link_config.active_duplex = DUPLEX_FULL;
1996         err = 0;
1997 out:
1998         mrvl88x2011_act_led(np, (link_up ?
1999                                  MRVL88X2011_LED_CTL_PCS_ACT :
2000                                  MRVL88X2011_LED_CTL_OFF));
2001
2002         *link_up_p = link_up;
2003         return err;
2004 }
2005
2006 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2007 {
2008         int err, link_up;
2009         link_up = 0;
2010
2011         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2012                         BCM8704_PMD_RCV_SIGDET);
2013         if (err < 0 || err == 0xffff)
2014                 goto out;
2015         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2016                 err = 0;
2017                 goto out;
2018         }
2019
2020         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2021                         BCM8704_PCS_10G_R_STATUS);
2022         if (err < 0)
2023                 goto out;
2024
2025         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2026                 err = 0;
2027                 goto out;
2028         }
2029
2030         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2031                         BCM8704_PHYXS_XGXS_LANE_STAT);
2032         if (err < 0)
2033                 goto out;
2034         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2035                     PHYXS_XGXS_LANE_STAT_MAGIC |
2036                     PHYXS_XGXS_LANE_STAT_PATTEST |
2037                     PHYXS_XGXS_LANE_STAT_LANE3 |
2038                     PHYXS_XGXS_LANE_STAT_LANE2 |
2039                     PHYXS_XGXS_LANE_STAT_LANE1 |
2040                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2041                 err = 0;
2042                 np->link_config.active_speed = SPEED_INVALID;
2043                 np->link_config.active_duplex = DUPLEX_INVALID;
2044                 goto out;
2045         }
2046
2047         link_up = 1;
2048         np->link_config.active_speed = SPEED_10000;
2049         np->link_config.active_duplex = DUPLEX_FULL;
2050         err = 0;
2051
2052 out:
2053         *link_up_p = link_up;
2054         return err;
2055 }
2056
2057 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2058 {
2059         int err, link_up;
2060
2061         link_up = 0;
2062
2063         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2064                         BCM8704_PMD_RCV_SIGDET);
2065         if (err < 0)
2066                 goto out;
2067         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2068                 err = 0;
2069                 goto out;
2070         }
2071
2072         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2073                         BCM8704_PCS_10G_R_STATUS);
2074         if (err < 0)
2075                 goto out;
2076         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2077                 err = 0;
2078                 goto out;
2079         }
2080
2081         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2082                         BCM8704_PHYXS_XGXS_LANE_STAT);
2083         if (err < 0)
2084                 goto out;
2085
2086         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2087                     PHYXS_XGXS_LANE_STAT_MAGIC |
2088                     PHYXS_XGXS_LANE_STAT_LANE3 |
2089                     PHYXS_XGXS_LANE_STAT_LANE2 |
2090                     PHYXS_XGXS_LANE_STAT_LANE1 |
2091                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2092                 err = 0;
2093                 goto out;
2094         }
2095
2096         link_up = 1;
2097         np->link_config.active_speed = SPEED_10000;
2098         np->link_config.active_duplex = DUPLEX_FULL;
2099         err = 0;
2100
2101 out:
2102         *link_up_p = link_up;
2103         return err;
2104 }
2105
2106 static int link_status_10g(struct niu *np, int *link_up_p)
2107 {
2108         unsigned long flags;
2109         int err = -EINVAL;
2110
2111         spin_lock_irqsave(&np->lock, flags);
2112
2113         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2114                 int phy_id;
2115
2116                 phy_id = phy_decode(np->parent->port_phy, np->port);
2117                 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2118
2119                 /* handle different phy types */
2120                 switch (phy_id & NIU_PHY_ID_MASK) {
2121                 case NIU_PHY_ID_MRVL88X2011:
2122                         err = link_status_10g_mrvl(np, link_up_p);
2123                         break;
2124
2125                 default: /* bcom 8704 */
2126                         err = link_status_10g_bcom(np, link_up_p);
2127                         break;
2128                 }
2129         }
2130
2131         spin_unlock_irqrestore(&np->lock, flags);
2132
2133         return err;
2134 }
2135
2136 static int niu_10g_phy_present(struct niu *np)
2137 {
2138         u64 sig, mask, val;
2139
2140         sig = nr64(ESR_INT_SIGNALS);
2141         switch (np->port) {
2142         case 0:
2143                 mask = ESR_INT_SIGNALS_P0_BITS;
2144                 val = (ESR_INT_SRDY0_P0 |
2145                        ESR_INT_DET0_P0 |
2146                        ESR_INT_XSRDY_P0 |
2147                        ESR_INT_XDP_P0_CH3 |
2148                        ESR_INT_XDP_P0_CH2 |
2149                        ESR_INT_XDP_P0_CH1 |
2150                        ESR_INT_XDP_P0_CH0);
2151                 break;
2152
2153         case 1:
2154                 mask = ESR_INT_SIGNALS_P1_BITS;
2155                 val = (ESR_INT_SRDY0_P1 |
2156                        ESR_INT_DET0_P1 |
2157                        ESR_INT_XSRDY_P1 |
2158                        ESR_INT_XDP_P1_CH3 |
2159                        ESR_INT_XDP_P1_CH2 |
2160                        ESR_INT_XDP_P1_CH1 |
2161                        ESR_INT_XDP_P1_CH0);
2162                 break;
2163
2164         default:
2165                 return 0;
2166         }
2167
2168         if ((sig & mask) != val)
2169                 return 0;
2170         return 1;
2171 }
2172
2173 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2174 {
2175         unsigned long flags;
2176         int err = 0;
2177         int phy_present;
2178         int phy_present_prev;
2179
2180         spin_lock_irqsave(&np->lock, flags);
2181
2182         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2183                 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2184                         1 : 0;
2185                 phy_present = niu_10g_phy_present(np);
2186                 if (phy_present != phy_present_prev) {
2187                         /* state change */
2188                         if (phy_present) {
2189                                 /* A NEM was just plugged in */
2190                                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2191                                 if (np->phy_ops->xcvr_init)
2192                                         err = np->phy_ops->xcvr_init(np);
2193                                 if (err) {
2194                                         err = mdio_read(np, np->phy_addr,
2195                                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2196                                         if (err == 0xffff) {
2197                                                 /* No mdio, back-to-back XAUI */
2198                                                 goto out;
2199                                         }
2200                                         /* debounce */
2201                                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2202                                 }
2203                         } else {
2204                                 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2205                                 *link_up_p = 0;
2206                                 netif_warn(np, link, np->dev,
2207                                            "Hotplug PHY Removed\n");
2208                         }
2209                 }
2210 out:
2211                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
2212                         err = link_status_10g_bcm8706(np, link_up_p);
2213                         if (err == 0xffff) {
2214                                 /* No mdio, back-to-back XAUI: it is C10NEM */
2215                                 *link_up_p = 1;
2216                                 np->link_config.active_speed = SPEED_10000;
2217                                 np->link_config.active_duplex = DUPLEX_FULL;
2218                         }
2219                 }
2220         }
2221
2222         spin_unlock_irqrestore(&np->lock, flags);
2223
2224         return 0;
2225 }
2226
2227 static int niu_link_status(struct niu *np, int *link_up_p)
2228 {
2229         const struct niu_phy_ops *ops = np->phy_ops;
2230         int err;
2231
2232         err = 0;
2233         if (ops->link_status)
2234                 err = ops->link_status(np, link_up_p);
2235
2236         return err;
2237 }
2238
2239 static void niu_timer(unsigned long __opaque)
2240 {
2241         struct niu *np = (struct niu *) __opaque;
2242         unsigned long off;
2243         int err, link_up;
2244
2245         err = niu_link_status(np, &link_up);
2246         if (!err)
2247                 niu_link_status_common(np, link_up);
2248
2249         if (netif_carrier_ok(np->dev))
2250                 off = 5 * HZ;
2251         else
2252                 off = 1 * HZ;
2253         np->timer.expires = jiffies + off;
2254
2255         add_timer(&np->timer);
2256 }
2257
2258 static const struct niu_phy_ops phy_ops_10g_serdes = {
2259         .serdes_init            = serdes_init_10g_serdes,
2260         .link_status            = link_status_10g_serdes,
2261 };
2262
2263 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2264         .serdes_init            = serdes_init_niu_10g_serdes,
2265         .link_status            = link_status_10g_serdes,
2266 };
2267
2268 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2269         .serdes_init            = serdes_init_niu_1g_serdes,
2270         .link_status            = link_status_1g_serdes,
2271 };
2272
2273 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2274         .xcvr_init              = xcvr_init_1g_rgmii,
2275         .link_status            = link_status_1g_rgmii,
2276 };
2277
2278 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2279         .serdes_init            = serdes_init_niu_10g_fiber,
2280         .xcvr_init              = xcvr_init_10g,
2281         .link_status            = link_status_10g,
2282 };
2283
2284 static const struct niu_phy_ops phy_ops_10g_fiber = {
2285         .serdes_init            = serdes_init_10g,
2286         .xcvr_init              = xcvr_init_10g,
2287         .link_status            = link_status_10g,
2288 };
2289
2290 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2291         .serdes_init            = serdes_init_10g,
2292         .xcvr_init              = xcvr_init_10g_bcm8706,
2293         .link_status            = link_status_10g_hotplug,
2294 };
2295
2296 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2297         .serdes_init            = serdes_init_niu_10g_fiber,
2298         .xcvr_init              = xcvr_init_10g_bcm8706,
2299         .link_status            = link_status_10g_hotplug,
2300 };
2301
2302 static const struct niu_phy_ops phy_ops_10g_copper = {
2303         .serdes_init            = serdes_init_10g,
2304         .link_status            = link_status_10g, /* XXX */
2305 };
2306
2307 static const struct niu_phy_ops phy_ops_1g_fiber = {
2308         .serdes_init            = serdes_init_1g,
2309         .xcvr_init              = xcvr_init_1g,
2310         .link_status            = link_status_1g,
2311 };
2312
2313 static const struct niu_phy_ops phy_ops_1g_copper = {
2314         .xcvr_init              = xcvr_init_1g,
2315         .link_status            = link_status_1g,
2316 };
2317
2318 struct niu_phy_template {
2319         const struct niu_phy_ops        *ops;
2320         u32                             phy_addr_base;
2321 };
2322
2323 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2324         .ops            = &phy_ops_10g_fiber_niu,
2325         .phy_addr_base  = 16,
2326 };
2327
2328 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2329         .ops            = &phy_ops_10g_serdes_niu,
2330         .phy_addr_base  = 0,
2331 };
2332
2333 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2334         .ops            = &phy_ops_1g_serdes_niu,
2335         .phy_addr_base  = 0,
2336 };
2337
2338 static const struct niu_phy_template phy_template_10g_fiber = {
2339         .ops            = &phy_ops_10g_fiber,
2340         .phy_addr_base  = 8,
2341 };
2342
2343 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2344         .ops            = &phy_ops_10g_fiber_hotplug,
2345         .phy_addr_base  = 8,
2346 };
2347
2348 static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2349         .ops            = &phy_ops_niu_10g_hotplug,
2350         .phy_addr_base  = 8,
2351 };
2352
2353 static const struct niu_phy_template phy_template_10g_copper = {
2354         .ops            = &phy_ops_10g_copper,
2355         .phy_addr_base  = 10,
2356 };
2357
2358 static const struct niu_phy_template phy_template_1g_fiber = {
2359         .ops            = &phy_ops_1g_fiber,
2360         .phy_addr_base  = 0,
2361 };
2362
2363 static const struct niu_phy_template phy_template_1g_copper = {
2364         .ops            = &phy_ops_1g_copper,
2365         .phy_addr_base  = 0,
2366 };
2367
2368 static const struct niu_phy_template phy_template_1g_rgmii = {
2369         .ops            = &phy_ops_1g_rgmii,
2370         .phy_addr_base  = 0,
2371 };
2372
2373 static const struct niu_phy_template phy_template_10g_serdes = {
2374         .ops            = &phy_ops_10g_serdes,
2375         .phy_addr_base  = 0,
2376 };
2377
2378 static int niu_atca_port_num[4] = {
2379         0, 0,  11, 10
2380 };
2381
2382 static int serdes_init_10g_serdes(struct niu *np)
2383 {
2384         struct niu_link_config *lp = &np->link_config;
2385         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2386         u64 ctrl_val, test_cfg_val, sig, mask, val;
2387         u64 reset_val;
2388
2389         switch (np->port) {
2390         case 0:
2391                 reset_val =  ENET_SERDES_RESET_0;
2392                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2393                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2394                 pll_cfg = ENET_SERDES_0_PLL_CFG;
2395                 break;
2396         case 1:
2397                 reset_val =  ENET_SERDES_RESET_1;
2398                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2399                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2400                 pll_cfg = ENET_SERDES_1_PLL_CFG;
2401                 break;
2402
2403         default:
2404                 return -EINVAL;
2405         }
2406         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2407                     ENET_SERDES_CTRL_SDET_1 |
2408                     ENET_SERDES_CTRL_SDET_2 |
2409                     ENET_SERDES_CTRL_SDET_3 |
2410                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2411                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2412                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2413                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2414                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2415                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2416                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2417                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2418         test_cfg_val = 0;
2419
2420         if (lp->loopback_mode == LOOPBACK_PHY) {
2421                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2422                                   ENET_SERDES_TEST_MD_0_SHIFT) |
2423                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2424                                   ENET_SERDES_TEST_MD_1_SHIFT) |
2425                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2426                                   ENET_SERDES_TEST_MD_2_SHIFT) |
2427                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2428                                   ENET_SERDES_TEST_MD_3_SHIFT));
2429         }
2430
2431         esr_reset(np);
2432         nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2433         nw64(ctrl_reg, ctrl_val);
2434         nw64(test_cfg_reg, test_cfg_val);
2435
2436         /* Initialize all 4 lanes of the SERDES.  */
2437         for (i = 0; i < 4; i++) {
2438                 u32 rxtx_ctrl, glue0;
2439                 int err;
2440
2441                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2442                 if (err)
2443                         return err;
2444                 err = esr_read_glue0(np, i, &glue0);
2445                 if (err)
2446                         return err;
2447
2448                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2449                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2450                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2451
2452                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2453                            ESR_GLUE_CTRL0_THCNT |
2454                            ESR_GLUE_CTRL0_BLTIME);
2455                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2456                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2457                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2458                           (BLTIME_300_CYCLES <<
2459                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
2460
2461                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2462                 if (err)
2463                         return err;
2464                 err = esr_write_glue0(np, i, glue0);
2465                 if (err)
2466                         return err;
2467         }
2468
2469
2470         sig = nr64(ESR_INT_SIGNALS);
2471         switch (np->port) {
2472         case 0:
2473                 mask = ESR_INT_SIGNALS_P0_BITS;
2474                 val = (ESR_INT_SRDY0_P0 |
2475                        ESR_INT_DET0_P0 |
2476                        ESR_INT_XSRDY_P0 |
2477                        ESR_INT_XDP_P0_CH3 |
2478                        ESR_INT_XDP_P0_CH2 |
2479                        ESR_INT_XDP_P0_CH1 |
2480                        ESR_INT_XDP_P0_CH0);
2481                 break;
2482
2483         case 1:
2484                 mask = ESR_INT_SIGNALS_P1_BITS;
2485                 val = (ESR_INT_SRDY0_P1 |
2486                        ESR_INT_DET0_P1 |
2487                        ESR_INT_XSRDY_P1 |
2488                        ESR_INT_XDP_P1_CH3 |
2489                        ESR_INT_XDP_P1_CH2 |
2490                        ESR_INT_XDP_P1_CH1 |
2491                        ESR_INT_XDP_P1_CH0);
2492                 break;
2493
2494         default:
2495                 return -EINVAL;
2496         }
2497
2498         if ((sig & mask) != val) {
2499                 int err;
2500                 err = serdes_init_1g_serdes(np);
2501                 if (!err) {
2502                         np->flags &= ~NIU_FLAGS_10G;
2503                         np->mac_xcvr = MAC_XCVR_PCS;
2504                 }  else {
2505                         netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2506                                    np->port);
2507                         return -ENODEV;
2508                 }
2509         }
2510
2511         return 0;
2512 }
2513
2514 static int niu_determine_phy_disposition(struct niu *np)
2515 {
2516         struct niu_parent *parent = np->parent;
2517         u8 plat_type = parent->plat_type;
2518         const struct niu_phy_template *tp;
2519         u32 phy_addr_off = 0;
2520
2521         if (plat_type == PLAT_TYPE_NIU) {
2522                 switch (np->flags &
2523                         (NIU_FLAGS_10G |
2524                          NIU_FLAGS_FIBER |
2525                          NIU_FLAGS_XCVR_SERDES)) {
2526                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2527                         /* 10G Serdes */
2528                         tp = &phy_template_niu_10g_serdes;
2529                         break;
2530                 case NIU_FLAGS_XCVR_SERDES:
2531                         /* 1G Serdes */
2532                         tp = &phy_template_niu_1g_serdes;
2533                         break;
2534                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2535                         /* 10G Fiber */
2536                 default:
2537                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2538                                 tp = &phy_template_niu_10g_hotplug;
2539                                 if (np->port == 0)
2540                                         phy_addr_off = 8;
2541                                 if (np->port == 1)
2542                                         phy_addr_off = 12;
2543                         } else {
2544                                 tp = &phy_template_niu_10g_fiber;
2545                                 phy_addr_off += np->port;
2546                         }
2547                         break;
2548                 }
2549         } else {
2550                 switch (np->flags &
2551                         (NIU_FLAGS_10G |
2552                          NIU_FLAGS_FIBER |
2553                          NIU_FLAGS_XCVR_SERDES)) {
2554                 case 0:
2555                         /* 1G copper */
2556                         tp = &phy_template_1g_copper;
2557                         if (plat_type == PLAT_TYPE_VF_P0)
2558                                 phy_addr_off = 10;
2559                         else if (plat_type == PLAT_TYPE_VF_P1)
2560                                 phy_addr_off = 26;
2561
2562                         phy_addr_off += (np->port ^ 0x3);
2563                         break;
2564
2565                 case NIU_FLAGS_10G:
2566                         /* 10G copper */
2567                         tp = &phy_template_10g_copper;
2568                         break;
2569
2570                 case NIU_FLAGS_FIBER:
2571                         /* 1G fiber */
2572                         tp = &phy_template_1g_fiber;
2573                         break;
2574
2575                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2576                         /* 10G fiber */
2577                         tp = &phy_template_10g_fiber;
2578                         if (plat_type == PLAT_TYPE_VF_P0 ||
2579                             plat_type == PLAT_TYPE_VF_P1)
2580                                 phy_addr_off = 8;
2581                         phy_addr_off += np->port;
2582                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2583                                 tp = &phy_template_10g_fiber_hotplug;
2584                                 if (np->port == 0)
2585                                         phy_addr_off = 8;
2586                                 if (np->port == 1)
2587                                         phy_addr_off = 12;
2588                         }
2589                         break;
2590
2591                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2592                 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2593                 case NIU_FLAGS_XCVR_SERDES:
2594                         switch(np->port) {
2595                         case 0:
2596                         case 1:
2597                                 tp = &phy_template_10g_serdes;
2598                                 break;
2599                         case 2:
2600                         case 3:
2601                                 tp = &phy_template_1g_rgmii;
2602                                 break;
2603                         default:
2604                                 return -EINVAL;
2605                                 break;
2606                         }
2607                         phy_addr_off = niu_atca_port_num[np->port];
2608                         break;
2609
2610                 default:
2611                         return -EINVAL;
2612                 }
2613         }
2614
2615         np->phy_ops = tp->ops;
2616         np->phy_addr = tp->phy_addr_base + phy_addr_off;
2617
2618         return 0;
2619 }
2620
2621 static int niu_init_link(struct niu *np)
2622 {
2623         struct niu_parent *parent = np->parent;
2624         int err, ignore;
2625
2626         if (parent->plat_type == PLAT_TYPE_NIU) {
2627                 err = niu_xcvr_init(np);
2628                 if (err)
2629                         return err;
2630                 msleep(200);
2631         }
2632         err = niu_serdes_init(np);
2633         if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
2634                 return err;
2635         msleep(200);
2636         err = niu_xcvr_init(np);
2637         if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
2638                 niu_link_status(np, &ignore);
2639         return 0;
2640 }
2641
2642 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2643 {
2644         u16 reg0 = addr[4] << 8 | addr[5];
2645         u16 reg1 = addr[2] << 8 | addr[3];
2646         u16 reg2 = addr[0] << 8 | addr[1];
2647
2648         if (np->flags & NIU_FLAGS_XMAC) {
2649                 nw64_mac(XMAC_ADDR0, reg0);
2650                 nw64_mac(XMAC_ADDR1, reg1);
2651                 nw64_mac(XMAC_ADDR2, reg2);
2652         } else {
2653                 nw64_mac(BMAC_ADDR0, reg0);
2654                 nw64_mac(BMAC_ADDR1, reg1);
2655                 nw64_mac(BMAC_ADDR2, reg2);
2656         }
2657 }
2658
2659 static int niu_num_alt_addr(struct niu *np)
2660 {
2661         if (np->flags & NIU_FLAGS_XMAC)
2662                 return XMAC_NUM_ALT_ADDR;
2663         else
2664                 return BMAC_NUM_ALT_ADDR;
2665 }
2666
2667 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2668 {
2669         u16 reg0 = addr[4] << 8 | addr[5];
2670         u16 reg1 = addr[2] << 8 | addr[3];
2671         u16 reg2 = addr[0] << 8 | addr[1];
2672
2673         if (index >= niu_num_alt_addr(np))
2674                 return -EINVAL;
2675
2676         if (np->flags & NIU_FLAGS_XMAC) {
2677                 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2678                 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2679                 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2680         } else {
2681                 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2682                 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2683                 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2684         }
2685
2686         return 0;
2687 }
2688
2689 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2690 {
2691         unsigned long reg;
2692         u64 val, mask;
2693
2694         if (index >= niu_num_alt_addr(np))
2695                 return -EINVAL;
2696
2697         if (np->flags & NIU_FLAGS_XMAC) {
2698                 reg = XMAC_ADDR_CMPEN;
2699                 mask = 1 << index;
2700         } else {
2701                 reg = BMAC_ADDR_CMPEN;
2702                 mask = 1 << (index + 1);
2703         }
2704
2705         val = nr64_mac(reg);
2706         if (on)
2707                 val |= mask;
2708         else
2709                 val &= ~mask;
2710         nw64_mac(reg, val);
2711
2712         return 0;
2713 }
2714
2715 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2716                                    int num, int mac_pref)
2717 {
2718         u64 val = nr64_mac(reg);
2719         val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2720         val |= num;
2721         if (mac_pref)
2722                 val |= HOST_INFO_MPR;
2723         nw64_mac(reg, val);
2724 }
2725
2726 static int __set_rdc_table_num(struct niu *np,
2727                                int xmac_index, int bmac_index,
2728                                int rdc_table_num, int mac_pref)
2729 {
2730         unsigned long reg;
2731
2732         if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2733                 return -EINVAL;
2734         if (np->flags & NIU_FLAGS_XMAC)
2735                 reg = XMAC_HOST_INFO(xmac_index);
2736         else
2737                 reg = BMAC_HOST_INFO(bmac_index);
2738         __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2739         return 0;
2740 }
2741
2742 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2743                                          int mac_pref)
2744 {
2745         return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2746 }
2747
2748 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2749                                            int mac_pref)
2750 {
2751         return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2752 }
2753
2754 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2755                                      int table_num, int mac_pref)
2756 {
2757         if (idx >= niu_num_alt_addr(np))
2758                 return -EINVAL;
2759         return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2760 }
2761
2762 static u64 vlan_entry_set_parity(u64 reg_val)
2763 {
2764         u64 port01_mask;
2765         u64 port23_mask;
2766
2767         port01_mask = 0x00ff;
2768         port23_mask = 0xff00;
2769
2770         if (hweight64(reg_val & port01_mask) & 1)
2771                 reg_val |= ENET_VLAN_TBL_PARITY0;
2772         else
2773                 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2774
2775         if (hweight64(reg_val & port23_mask) & 1)
2776                 reg_val |= ENET_VLAN_TBL_PARITY1;
2777         else
2778                 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2779
2780         return reg_val;
2781 }
2782
2783 static void vlan_tbl_write(struct niu *np, unsigned long index,
2784                            int port, int vpr, int rdc_table)
2785 {
2786         u64 reg_val = nr64(ENET_VLAN_TBL(index));
2787
2788         reg_val &= ~((ENET_VLAN_TBL_VPR |
2789                       ENET_VLAN_TBL_VLANRDCTBLN) <<
2790                      ENET_VLAN_TBL_SHIFT(port));
2791         if (vpr)
2792                 reg_val |= (ENET_VLAN_TBL_VPR <<
2793                             ENET_VLAN_TBL_SHIFT(port));
2794         reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2795
2796         reg_val = vlan_entry_set_parity(reg_val);
2797
2798         nw64(ENET_VLAN_TBL(index), reg_val);
2799 }
2800
2801 static void vlan_tbl_clear(struct niu *np)
2802 {
2803         int i;
2804
2805         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2806                 nw64(ENET_VLAN_TBL(i), 0);
2807 }
2808
2809 static int tcam_wait_bit(struct niu *np, u64 bit)
2810 {
2811         int limit = 1000;
2812
2813         while (--limit > 0) {
2814                 if (nr64(TCAM_CTL) & bit)
2815                         break;
2816                 udelay(1);
2817         }
2818         if (limit <= 0)
2819                 return -ENODEV;
2820
2821         return 0;
2822 }
2823
2824 static int tcam_flush(struct niu *np, int index)
2825 {
2826         nw64(TCAM_KEY_0, 0x00);
2827         nw64(TCAM_KEY_MASK_0, 0xff);
2828         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2829
2830         return tcam_wait_bit(np, TCAM_CTL_STAT);
2831 }
2832
2833 #if 0
2834 static int tcam_read(struct niu *np, int index,
2835                      u64 *key, u64 *mask)
2836 {
2837         int err;
2838
2839         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2840         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2841         if (!err) {
2842                 key[0] = nr64(TCAM_KEY_0);
2843                 key[1] = nr64(TCAM_KEY_1);
2844                 key[2] = nr64(TCAM_KEY_2);
2845                 key[3] = nr64(TCAM_KEY_3);
2846                 mask[0] = nr64(TCAM_KEY_MASK_0);
2847                 mask[1] = nr64(TCAM_KEY_MASK_1);
2848                 mask[2] = nr64(TCAM_KEY_MASK_2);
2849                 mask[3] = nr64(TCAM_KEY_MASK_3);
2850         }
2851         return err;
2852 }
2853 #endif
2854
2855 static int tcam_write(struct niu *np, int index,
2856                       u64 *key, u64 *mask)
2857 {
2858         nw64(TCAM_KEY_0, key[0]);
2859         nw64(TCAM_KEY_1, key[1]);
2860         nw64(TCAM_KEY_2, key[2]);
2861         nw64(TCAM_KEY_3, key[3]);
2862         nw64(TCAM_KEY_MASK_0, mask[0]);
2863         nw64(TCAM_KEY_MASK_1, mask[1]);
2864         nw64(TCAM_KEY_MASK_2, mask[2]);
2865         nw64(TCAM_KEY_MASK_3, mask[3]);
2866         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2867
2868         return tcam_wait_bit(np, TCAM_CTL_STAT);
2869 }
2870
2871 #if 0
2872 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2873 {
2874         int err;
2875
2876         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2877         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2878         if (!err)
2879                 *data = nr64(TCAM_KEY_1);
2880
2881         return err;
2882 }
2883 #endif
2884
2885 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2886 {
2887         nw64(TCAM_KEY_1, assoc_data);
2888         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2889
2890         return tcam_wait_bit(np, TCAM_CTL_STAT);
2891 }
2892
2893 static void tcam_enable(struct niu *np, int on)
2894 {
2895         u64 val = nr64(FFLP_CFG_1);
2896
2897         if (on)
2898                 val &= ~FFLP_CFG_1_TCAM_DIS;
2899         else
2900                 val |= FFLP_CFG_1_TCAM_DIS;
2901         nw64(FFLP_CFG_1, val);
2902 }
2903
2904 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2905 {
2906         u64 val = nr64(FFLP_CFG_1);
2907
2908         val &= ~(FFLP_CFG_1_FFLPINITDONE |
2909                  FFLP_CFG_1_CAMLAT |
2910                  FFLP_CFG_1_CAMRATIO);
2911         val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2912         val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2913         nw64(FFLP_CFG_1, val);
2914
2915         val = nr64(FFLP_CFG_1);
2916         val |= FFLP_CFG_1_FFLPINITDONE;
2917         nw64(FFLP_CFG_1, val);
2918 }
2919
2920 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2921                                       int on)
2922 {
2923         unsigned long reg;
2924         u64 val;
2925
2926         if (class < CLASS_CODE_ETHERTYPE1 ||
2927             class > CLASS_CODE_ETHERTYPE2)
2928                 return -EINVAL;
2929
2930         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2931         val = nr64(reg);
2932         if (on)
2933                 val |= L2_CLS_VLD;
2934         else
2935                 val &= ~L2_CLS_VLD;
2936         nw64(reg, val);
2937
2938         return 0;
2939 }
2940
2941 #if 0
2942 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2943                                    u64 ether_type)
2944 {
2945         unsigned long reg;
2946         u64 val;
2947
2948         if (class < CLASS_CODE_ETHERTYPE1 ||
2949             class > CLASS_CODE_ETHERTYPE2 ||
2950             (ether_type & ~(u64)0xffff) != 0)
2951                 return -EINVAL;
2952
2953         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2954         val = nr64(reg);
2955         val &= ~L2_CLS_ETYPE;
2956         val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2957         nw64(reg, val);
2958
2959         return 0;
2960 }
2961 #endif
2962
2963 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2964                                      int on)
2965 {
2966         unsigned long reg;
2967         u64 val;
2968
2969         if (class < CLASS_CODE_USER_PROG1 ||
2970             class > CLASS_CODE_USER_PROG4)
2971                 return -EINVAL;
2972
2973         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2974         val = nr64(reg);
2975         if (on)
2976                 val |= L3_CLS_VALID;
2977         else
2978                 val &= ~L3_CLS_VALID;
2979         nw64(reg, val);
2980
2981         return 0;
2982 }
2983
2984 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2985                                   int ipv6, u64 protocol_id,
2986                                   u64 tos_mask, u64 tos_val)
2987 {
2988         unsigned long reg;
2989         u64 val;
2990
2991         if (class < CLASS_CODE_USER_PROG1 ||
2992             class > CLASS_CODE_USER_PROG4 ||
2993             (protocol_id & ~(u64)0xff) != 0 ||
2994             (tos_mask & ~(u64)0xff) != 0 ||
2995             (tos_val & ~(u64)0xff) != 0)
2996                 return -EINVAL;
2997
2998         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2999         val = nr64(reg);
3000         val &= ~(L3_CLS_IPVER | L3_CLS_PID |
3001                  L3_CLS_TOSMASK | L3_CLS_TOS);
3002         if (ipv6)
3003                 val |= L3_CLS_IPVER;
3004         val |= (protocol_id << L3_CLS_PID_SHIFT);
3005         val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
3006         val |= (tos_val << L3_CLS_TOS_SHIFT);
3007         nw64(reg, val);
3008
3009         return 0;
3010 }
3011
3012 static int tcam_early_init(struct niu *np)
3013 {
3014         unsigned long i;
3015         int err;
3016
3017         tcam_enable(np, 0);
3018         tcam_set_lat_and_ratio(np,
3019                                DEFAULT_TCAM_LATENCY,
3020                                DEFAULT_TCAM_ACCESS_RATIO);
3021         for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3022                 err = tcam_user_eth_class_enable(np, i, 0);
3023                 if (err)
3024                         return err;
3025         }
3026         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3027                 err = tcam_user_ip_class_enable(np, i, 0);
3028                 if (err)
3029                         return err;
3030         }
3031
3032         return 0;
3033 }
3034
3035 static int tcam_flush_all(struct niu *np)
3036 {
3037         unsigned long i;
3038
3039         for (i = 0; i < np->parent->tcam_num_entries; i++) {
3040                 int err = tcam_flush(np, i);
3041                 if (err)
3042                         return err;
3043         }
3044         return 0;
3045 }
3046
3047 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3048 {
3049         return ((u64)index | (num_entries == 1 ?
3050                               HASH_TBL_ADDR_AUTOINC : 0));
3051 }
3052
3053 #if 0
3054 static int hash_read(struct niu *np, unsigned long partition,
3055                      unsigned long index, unsigned long num_entries,
3056                      u64 *data)
3057 {
3058         u64 val = hash_addr_regval(index, num_entries);
3059         unsigned long i;
3060
3061         if (partition >= FCRAM_NUM_PARTITIONS ||
3062             index + num_entries > FCRAM_SIZE)
3063                 return -EINVAL;
3064
3065         nw64(HASH_TBL_ADDR(partition), val);
3066         for (i = 0; i < num_entries; i++)
3067                 data[i] = nr64(HASH_TBL_DATA(partition));
3068
3069         return 0;
3070 }
3071 #endif
3072
3073 static int hash_write(struct niu *np, unsigned long partition,
3074                       unsigned long index, unsigned long num_entries,
3075                       u64 *data)
3076 {
3077         u64 val = hash_addr_regval(index, num_entries);
3078         unsigned long i;
3079
3080         if (partition >= FCRAM_NUM_PARTITIONS ||
3081             index + (num_entries * 8) > FCRAM_SIZE)
3082                 return -EINVAL;
3083
3084         nw64(HASH_TBL_ADDR(partition), val);
3085         for (i = 0; i < num_entries; i++)
3086                 nw64(HASH_TBL_DATA(partition), data[i]);
3087
3088         return 0;
3089 }
3090
3091 static void fflp_reset(struct niu *np)
3092 {
3093         u64 val;
3094
3095         nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3096         udelay(10);
3097         nw64(FFLP_CFG_1, 0);
3098
3099         val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3100         nw64(FFLP_CFG_1, val);
3101 }
3102
3103 static void fflp_set_timings(struct niu *np)
3104 {
3105         u64 val = nr64(FFLP_CFG_1);
3106
3107         val &= ~FFLP_CFG_1_FFLPINITDONE;
3108         val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3109         nw64(FFLP_CFG_1, val);
3110
3111         val = nr64(FFLP_CFG_1);
3112         val |= FFLP_CFG_1_FFLPINITDONE;
3113         nw64(FFLP_CFG_1, val);
3114
3115         val = nr64(FCRAM_REF_TMR);
3116         val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3117         val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3118         val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3119         nw64(FCRAM_REF_TMR, val);
3120 }
3121
3122 static int fflp_set_partition(struct niu *np, u64 partition,
3123                               u64 mask, u64 base, int enable)
3124 {
3125         unsigned long reg;
3126         u64 val;
3127
3128         if (partition >= FCRAM_NUM_PARTITIONS ||
3129             (mask & ~(u64)0x1f) != 0 ||
3130             (base & ~(u64)0x1f) != 0)
3131                 return -EINVAL;
3132
3133         reg = FLW_PRT_SEL(partition);
3134
3135         val = nr64(reg);
3136         val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3137         val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3138         val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3139         if (enable)
3140                 val |= FLW_PRT_SEL_EXT;
3141         nw64(reg, val);
3142
3143         return 0;
3144 }
3145
3146 static int fflp_disable_all_partitions(struct niu *np)
3147 {
3148         unsigned long i;
3149
3150         for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3151                 int err = fflp_set_partition(np, 0, 0, 0, 0);
3152                 if (err)
3153                         return err;
3154         }
3155         return 0;
3156 }
3157
3158 static void fflp_llcsnap_enable(struct niu *np, int on)
3159 {
3160         u64 val = nr64(FFLP_CFG_1);
3161
3162         if (on)
3163                 val |= FFLP_CFG_1_LLCSNAP;
3164         else
3165                 val &= ~FFLP_CFG_1_LLCSNAP;
3166         nw64(FFLP_CFG_1, val);
3167 }
3168
3169 static void fflp_errors_enable(struct niu *np, int on)
3170 {
3171         u64 val = nr64(FFLP_CFG_1);
3172
3173         if (on)
3174                 val &= ~FFLP_CFG_1_ERRORDIS;
3175         else
3176                 val |= FFLP_CFG_1_ERRORDIS;
3177         nw64(FFLP_CFG_1, val);
3178 }
3179
3180 static int fflp_hash_clear(struct niu *np)
3181 {
3182         struct fcram_hash_ipv4 ent;
3183         unsigned long i;
3184
3185         /* IPV4 hash entry with valid bit clear, rest is don't care.  */
3186         memset(&ent, 0, sizeof(ent));
3187         ent.header = HASH_HEADER_EXT;
3188
3189         for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3190                 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3191                 if (err)
3192                         return err;
3193         }
3194         return 0;
3195 }
3196
3197 static int fflp_early_init(struct niu *np)
3198 {
3199         struct niu_parent *parent;
3200         unsigned long flags;
3201         int err;
3202
3203         niu_lock_parent(np, flags);
3204
3205         parent = np->parent;
3206         err = 0;
3207         if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3208                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3209                         fflp_reset(np);
3210                         fflp_set_timings(np);
3211                         err = fflp_disable_all_partitions(np);
3212                         if (err) {
3213                                 netif_printk(np, probe, KERN_DEBUG, np->dev,
3214                                              "fflp_disable_all_partitions failed, err=%d\n",
3215                                              err);
3216                                 goto out;
3217                         }
3218                 }
3219
3220                 err = tcam_early_init(np);
3221                 if (err) {
3222                         netif_printk(np, probe, KERN_DEBUG, np->dev,
3223                                      "tcam_early_init failed, err=%d\n", err);
3224                         goto out;
3225                 }
3226                 fflp_llcsnap_enable(np, 1);
3227                 fflp_errors_enable(np, 0);
3228                 nw64(H1POLY, 0);
3229                 nw64(H2POLY, 0);
3230
3231                 err = tcam_flush_all(np);
3232                 if (err) {
3233                         netif_printk(np, probe, KERN_DEBUG, np->dev,
3234                                      "tcam_flush_all failed, err=%d\n", err);
3235                         goto out;
3236                 }
3237                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3238                         err = fflp_hash_clear(np);
3239                         if (err) {
3240                                 netif_printk(np, probe, KERN_DEBUG, np->dev,
3241                                              "fflp_hash_clear failed, err=%d\n",
3242                                              err);
3243                                 goto out;
3244                         }
3245                 }
3246
3247                 vlan_tbl_clear(np);
3248
3249                 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3250         }
3251 out:
3252         niu_unlock_parent(np, flags);
3253         return err;
3254 }
3255
3256 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3257 {
3258         if (class_code < CLASS_CODE_USER_PROG1 ||
3259             class_code > CLASS_CODE_SCTP_IPV6)
3260                 return -EINVAL;
3261
3262         nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3263         return 0;
3264 }
3265
3266 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3267 {
3268         if (class_code < CLASS_CODE_USER_PROG1 ||
3269             class_code > CLASS_CODE_SCTP_IPV6)
3270                 return -EINVAL;
3271
3272         nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3273         return 0;
3274 }
3275
3276 /* Entries for the ports are interleaved in the TCAM */
3277 static u16 tcam_get_index(struct niu *np, u16 idx)
3278 {
3279         /* One entry reserved for IP fragment rule */
3280         if (idx >= (np->clas.tcam_sz - 1))
3281                 idx = 0;
3282         return (np->clas.tcam_top + ((idx+1) * np->parent->num_ports));
3283 }
3284
3285 static u16 tcam_get_size(struct niu *np)
3286 {
3287         /* One entry reserved for IP fragment rule */
3288         return np->clas.tcam_sz - 1;
3289 }
3290
3291 static u16 tcam_get_valid_entry_cnt(struct niu *np)
3292 {
3293         /* One entry reserved for IP fragment rule */
3294         return np->clas.tcam_valid_entries - 1;
3295 }
3296
3297 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3298                               u32 offset, u32 size)
3299 {
3300         int i = skb_shinfo(skb)->nr_frags;
3301         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3302
3303         frag->page = page;
3304         frag->page_offset = offset;
3305         frag->size = size;
3306
3307         skb->len += size;
3308         skb->data_len += size;
3309         skb->truesize += size;
3310
3311         skb_shinfo(skb)->nr_frags = i + 1;
3312 }
3313
3314 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3315 {
3316         a >>= PAGE_SHIFT;
3317         a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3318
3319         return (a & (MAX_RBR_RING_SIZE - 1));
3320 }
3321
3322 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3323                                     struct page ***link)
3324 {
3325         unsigned int h = niu_hash_rxaddr(rp, addr);
3326         struct page *p, **pp;
3327
3328         addr &= PAGE_MASK;
3329         pp = &rp->rxhash[h];
3330         for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3331                 if (p->index == addr) {
3332                         *link = pp;
3333                         goto found;
3334                 }
3335         }
3336         BUG();
3337
3338 found:
3339         return p;
3340 }
3341
3342 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3343 {
3344         unsigned int h = niu_hash_rxaddr(rp, base);
3345
3346         page->index = base;
3347         page->mapping = (struct address_space *) rp->rxhash[h];
3348         rp->rxhash[h] = page;
3349 }
3350
3351 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3352                             gfp_t mask, int start_index)
3353 {
3354         struct page *page;
3355         u64 addr;
3356         int i;
3357
3358         page = alloc_page(mask);
3359         if (!page)
3360                 return -ENOMEM;
3361
3362         addr = np->ops->map_page(np->device, page, 0,
3363                                  PAGE_SIZE, DMA_FROM_DEVICE);
3364
3365         niu_hash_page(rp, page, addr);
3366         if (rp->rbr_blocks_per_page > 1)
3367                 atomic_add(rp->rbr_blocks_per_page - 1,
3368                            &compound_head(page)->_count);
3369
3370         for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3371                 __le32 *rbr = &rp->rbr[start_index + i];
3372
3373                 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3374                 addr += rp->rbr_block_size;
3375         }
3376
3377         return 0;
3378 }
3379
3380 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3381 {
3382         int index = rp->rbr_index;
3383
3384         rp->rbr_pending++;
3385         if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3386                 int err = niu_rbr_add_page(np, rp, mask, index);
3387
3388                 if (unlikely(err)) {
3389                         rp->rbr_pending--;
3390                         return;
3391                 }
3392
3393                 rp->rbr_index += rp->rbr_blocks_per_page;
3394                 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3395                 if (rp->rbr_index == rp->rbr_table_size)
3396                         rp->rbr_index = 0;
3397
3398                 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3399                         nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3400                         rp->rbr_pending = 0;
3401                 }
3402         }
3403 }
3404
3405 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3406 {
3407         unsigned int index = rp->rcr_index;
3408         int num_rcr = 0;
3409
3410         rp->rx_dropped++;
3411         while (1) {
3412                 struct page *page, **link;
3413                 u64 addr, val;
3414                 u32 rcr_size;
3415
3416                 num_rcr++;
3417
3418                 val = le64_to_cpup(&rp->rcr[index]);
3419                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3420                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3421                 page = niu_find_rxpage(rp, addr, &link);
3422
3423                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3424                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3425                 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3426                         *link = (struct page *) page->mapping;
3427                         np->ops->unmap_page(np->device, page->index,
3428                                             PAGE_SIZE, DMA_FROM_DEVICE);
3429                         page->index = 0;
3430                         page->mapping = NULL;
3431                         __free_page(page);
3432                         rp->rbr_refill_pending++;
3433                 }
3434
3435                 index = NEXT_RCR(rp, index);
3436                 if (!(val & RCR_ENTRY_MULTI))
3437                         break;
3438
3439         }
3440         rp->rcr_index = index;
3441
3442         return num_rcr;
3443 }
3444
3445 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3446                               struct rx_ring_info *rp)
3447 {
3448         unsigned int index = rp->rcr_index;
3449         struct rx_pkt_hdr1 *rh;
3450         struct sk_buff *skb;
3451         int len, num_rcr;
3452
3453         skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3454         if (unlikely(!skb))
3455                 return niu_rx_pkt_ignore(np, rp);
3456
3457         num_rcr = 0;
3458         while (1) {
3459                 struct page *page, **link;
3460                 u32 rcr_size, append_size;
3461                 u64 addr, val, off;
3462
3463                 num_rcr++;
3464
3465                 val = le64_to_cpup(&rp->rcr[index]);
3466
3467                 len = (val & RCR_ENTRY_L2_LEN) >>
3468                         RCR_ENTRY_L2_LEN_SHIFT;
3469                 len -= ETH_FCS_LEN;
3470
3471                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3472                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3473                 page = niu_find_rxpage(rp, addr, &link);
3474
3475                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3476                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3477
3478                 off = addr & ~PAGE_MASK;
3479                 append_size = rcr_size;
3480                 if (num_rcr == 1) {
3481                         int ptype;
3482
3483                         ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3484                         if ((ptype == RCR_PKT_TYPE_TCP ||
3485                              ptype == RCR_PKT_TYPE_UDP) &&
3486                             !(val & (RCR_ENTRY_NOPORT |
3487                                      RCR_ENTRY_ERROR)))
3488                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3489                         else
3490                                 skb->ip_summed = CHECKSUM_NONE;
3491                 } else if (!(val & RCR_ENTRY_MULTI))
3492                         append_size = len - skb->len;
3493
3494                 niu_rx_skb_append(skb, page, off, append_size);
3495                 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3496                         *link = (struct page *) page->mapping;
3497                         np->ops->unmap_page(np->device, page->index,
3498                                             PAGE_SIZE, DMA_FROM_DEVICE);
3499                         page->index = 0;
3500                         page->mapping = NULL;
3501                         rp->rbr_refill_pending++;
3502                 } else
3503                         get_page(page);
3504
3505                 index = NEXT_RCR(rp, index);
3506                 if (!(val & RCR_ENTRY_MULTI))
3507                         break;
3508
3509         }
3510         rp->rcr_index = index;
3511
3512         len += sizeof(*rh);
3513         len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN);
3514         __pskb_pull_tail(skb, len);
3515
3516         rh = (struct rx_pkt_hdr1 *) skb->data;
3517         if (np->dev->features & NETIF_F_RXHASH)
3518                 skb->rxhash = ((u32)rh->hashval2_0 << 24 |
3519                                (u32)rh->hashval2_1 << 16 |
3520                                (u32)rh->hashval1_1 << 8 |
3521                                (u32)rh->hashval1_2 << 0);
3522         skb_pull(skb, sizeof(*rh));
3523
3524         rp->rx_packets++;
3525         rp->rx_bytes += skb->len;
3526
3527         skb->protocol = eth_type_trans(skb, np->dev);
3528         skb_record_rx_queue(skb, rp->rx_channel);
3529         napi_gro_receive(napi, skb);
3530
3531         return num_rcr;
3532 }
3533
3534 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3535 {
3536         int blocks_per_page = rp->rbr_blocks_per_page;
3537         int err, index = rp->rbr_index;
3538
3539         err = 0;
3540         while (index < (rp->rbr_table_size - blocks_per_page)) {
3541                 err = niu_rbr_add_page(np, rp, mask, index);
3542                 if (err)
3543                         break;
3544
3545                 index += blocks_per_page;
3546         }
3547
3548         rp->rbr_index = index;
3549         return err;
3550 }
3551
3552 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3553 {
3554         int i;
3555
3556         for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3557                 struct page *page;
3558
3559                 page = rp->rxhash[i];
3560                 while (page) {
3561                         struct page *next = (struct page *) page->mapping;
3562                         u64 base = page->index;
3563
3564                         np->ops->unmap_page(np->device, base, PAGE_SIZE,
3565                                             DMA_FROM_DEVICE);
3566                         page->index = 0;
3567                         page->mapping = NULL;
3568
3569                         __free_page(page);
3570
3571                         page = next;
3572                 }
3573         }
3574
3575         for (i = 0; i < rp->rbr_table_size; i++)
3576                 rp->rbr[i] = cpu_to_le32(0);
3577         rp->rbr_index = 0;
3578 }
3579
3580 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3581 {
3582         struct tx_buff_info *tb = &rp->tx_buffs[idx];
3583         struct sk_buff *skb = tb->skb;
3584         struct tx_pkt_hdr *tp;
3585         u64 tx_flags;
3586         int i, len;
3587
3588         tp = (struct tx_pkt_hdr *) skb->data;
3589         tx_flags = le64_to_cpup(&tp->flags);
3590
3591         rp->tx_packets++;
3592         rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3593                          ((tx_flags & TXHDR_PAD) / 2));
3594
3595         len = skb_headlen(skb);
3596         np->ops->unmap_single(np->device, tb->mapping,
3597                               len, DMA_TO_DEVICE);
3598
3599         if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3600                 rp->mark_pending--;
3601
3602         tb->skb = NULL;
3603         do {
3604                 idx = NEXT_TX(rp, idx);
3605                 len -= MAX_TX_DESC_LEN;
3606         } while (len > 0);
3607
3608         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3609                 tb = &rp->tx_buffs[idx];
3610                 BUG_ON(tb->skb != NULL);
3611                 np->ops->unmap_page(np->device, tb->mapping,
3612                                     skb_shinfo(skb)->frags[i].size,
3613                                     DMA_TO_DEVICE);
3614                 idx = NEXT_TX(rp, idx);
3615         }
3616
3617         dev_kfree_skb(skb);
3618
3619         return idx;
3620 }
3621
3622 #define NIU_TX_WAKEUP_THRESH(rp)                ((rp)->pending / 4)
3623
3624 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3625 {
3626         struct netdev_queue *txq;
3627         u16 pkt_cnt, tmp;
3628         int cons, index;
3629         u64 cs;
3630
3631         index = (rp - np->tx_rings);
3632         txq = netdev_get_tx_queue(np->dev, index);
3633
3634         cs = rp->tx_cs;
3635         if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3636                 goto out;
3637
3638         tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3639         pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3640                 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3641
3642         rp->last_pkt_cnt = tmp;
3643
3644         cons = rp->cons;
3645
3646         netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3647                      "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
3648
3649         while (pkt_cnt--)
3650                 cons = release_tx_packet(np, rp, cons);
3651
3652         rp->cons = cons;
3653         smp_mb();
3654
3655 out:
3656         if (unlikely(netif_tx_queue_stopped(txq) &&
3657                      (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3658                 __netif_tx_lock(txq, smp_processor_id());
3659                 if (netif_tx_queue_stopped(txq) &&
3660                     (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3661                         netif_tx_wake_queue(txq);
3662                 __netif_tx_unlock(txq);
3663         }
3664 }
3665
3666 static inline void niu_sync_rx_discard_stats(struct niu *np,
3667                                              struct rx_ring_info *rp,
3668                                              const int limit)
3669 {
3670         /* This elaborate scheme is needed for reading the RX discard
3671          * counters, as they are only 16-bit and can overflow quickly,
3672          * and because the overflow indication bit is not usable as
3673          * the counter value does not wrap, but remains at max value
3674          * 0xFFFF.
3675          *
3676          * In theory and in practice counters can be lost in between
3677          * reading nr64() and clearing the counter nw64().  For this
3678          * reason, the number of counter clearings nw64() is
3679          * limited/reduced though the limit parameter.
3680          */
3681         int rx_channel = rp->rx_channel;
3682         u32 misc, wred;
3683
3684         /* RXMISC (Receive Miscellaneous Discard Count), covers the
3685          * following discard events: IPP (Input Port Process),
3686          * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3687          * Block Ring) prefetch buffer is empty.
3688          */
3689         misc = nr64(RXMISC(rx_channel));
3690         if (unlikely((misc & RXMISC_COUNT) > limit)) {
3691                 nw64(RXMISC(rx_channel), 0);
3692                 rp->rx_errors += misc & RXMISC_COUNT;
3693
3694                 if (unlikely(misc & RXMISC_OFLOW))
3695                         dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3696                                 rx_channel);
3697
3698                 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3699                              "rx-%d: MISC drop=%u over=%u\n",
3700                              rx_channel, misc, misc-limit);
3701         }
3702
3703         /* WRED (Weighted Random Early Discard) by hardware */
3704         wred = nr64(RED_DIS_CNT(rx_channel));
3705         if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3706                 nw64(RED_DIS_CNT(rx_channel), 0);
3707                 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3708
3709                 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3710                         dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
3711
3712                 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3713                              "rx-%d: WRED drop=%u over=%u\n",
3714                              rx_channel, wred, wred-limit);
3715         }
3716 }
3717
3718 static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3719                        struct rx_ring_info *rp, int budget)
3720 {
3721         int qlen, rcr_done = 0, work_done = 0;
3722         struct rxdma_mailbox *mbox = rp->mbox;
3723         u64 stat;
3724
3725 #if 1
3726         stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3727         qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3728 #else
3729         stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3730         qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3731 #endif
3732         mbox->rx_dma_ctl_stat = 0;
3733         mbox->rcrstat_a = 0;
3734
3735         netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3736                      "%s(chan[%d]), stat[%llx] qlen=%d\n",
3737                      __func__, rp->rx_channel, (unsigned long long)stat, qlen);
3738
3739         rcr_done = work_done = 0;
3740         qlen = min(qlen, budget);
3741         while (work_done < qlen) {
3742                 rcr_done += niu_process_rx_pkt(napi, np, rp);
3743                 work_done++;
3744         }
3745
3746         if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3747                 unsigned int i;
3748
3749                 for (i = 0; i < rp->rbr_refill_pending; i++)
3750                         niu_rbr_refill(np, rp, GFP_ATOMIC);
3751                 rp->rbr_refill_pending = 0;
3752         }
3753
3754         stat = (RX_DMA_CTL_STAT_MEX |
3755                 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3756                 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3757
3758         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3759
3760         /* Only sync discards stats when qlen indicate potential for drops */
3761         if (qlen > 10)
3762                 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3763
3764         return work_done;
3765 }
3766
3767 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3768 {
3769         u64 v0 = lp->v0;
3770         u32 tx_vec = (v0 >> 32);
3771         u32 rx_vec = (v0 & 0xffffffff);
3772         int i, work_done = 0;
3773
3774         netif_printk(np, intr, KERN_DEBUG, np->dev,
3775                      "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
3776
3777         for (i = 0; i < np->num_tx_rings; i++) {
3778                 struct tx_ring_info *rp = &np->tx_rings[i];
3779                 if (tx_vec & (1 << rp->tx_channel))
3780                         niu_tx_work(np, rp);
3781                 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3782         }
3783
3784         for (i = 0; i < np->num_rx_rings; i++) {
3785                 struct rx_ring_info *rp = &np->rx_rings[i];
3786
3787                 if (rx_vec & (1 << rp->rx_channel)) {
3788                         int this_work_done;
3789
3790                         this_work_done = niu_rx_work(&lp->napi, np, rp,
3791                                                      budget);
3792
3793                         budget -= this_work_done;
3794                         work_done += this_work_done;
3795                 }
3796                 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3797         }
3798
3799         return work_done;
3800 }
3801
3802 static int niu_poll(struct napi_struct *napi, int budget)
3803 {
3804         struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3805         struct niu *np = lp->np;
3806         int work_done;
3807
3808         work_done = niu_poll_core(np, lp, budget);
3809
3810         if (work_done < budget) {
3811                 napi_complete(napi);
3812                 niu_ldg_rearm(np, lp, 1);
3813         }
3814         return work_done;
3815 }
3816
3817 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3818                                   u64 stat)
3819 {
3820         netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
3821
3822         if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3823                 pr_cont("RBR_TMOUT ");
3824         if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3825                 pr_cont("RSP_CNT ");
3826         if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3827                 pr_cont("BYTE_EN_BUS ");
3828         if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3829                 pr_cont("RSP_DAT ");
3830         if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3831                 pr_cont("RCR_ACK ");
3832         if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3833                 pr_cont("RCR_SHA_PAR ");
3834         if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3835                 pr_cont("RBR_PRE_PAR ");
3836         if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3837                 pr_cont("CONFIG ");
3838         if (stat & RX_DMA_CTL_STAT_RCRINCON)
3839                 pr_cont("RCRINCON ");
3840         if (stat & RX_DMA_CTL_STAT_RCRFULL)
3841                 pr_cont("RCRFULL ");
3842         if (stat & RX_DMA_CTL_STAT_RBRFULL)
3843                 pr_cont("RBRFULL ");
3844         if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3845                 pr_cont("RBRLOGPAGE ");
3846         if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3847                 pr_cont("CFIGLOGPAGE ");
3848         if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3849                 pr_cont("DC_FIDO ");
3850
3851         pr_cont(")\n");
3852 }
3853
3854 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3855 {
3856         u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3857         int err = 0;
3858
3859
3860         if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3861                     RX_DMA_CTL_STAT_PORT_FATAL))
3862                 err = -EINVAL;
3863
3864         if (err) {
3865                 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3866                            rp->rx_channel,
3867                            (unsigned long long) stat);
3868
3869                 niu_log_rxchan_errors(np, rp, stat);
3870         }
3871
3872         nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3873              stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3874
3875         return err;
3876 }
3877
3878 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3879                                   u64 cs)
3880 {
3881         netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
3882
3883         if (cs & TX_CS_MBOX_ERR)
3884                 pr_cont("MBOX ");
3885         if (cs & TX_CS_PKT_SIZE_ERR)
3886                 pr_cont("PKT_SIZE ");
3887         if (cs & TX_CS_TX_RING_OFLOW)
3888                 pr_cont("TX_RING_OFLOW ");
3889         if (cs & TX_CS_PREF_BUF_PAR_ERR)
3890                 pr_cont("PREF_BUF_PAR ");
3891         if (cs & TX_CS_NACK_PREF)
3892                 pr_cont("NACK_PREF ");
3893         if (cs & TX_CS_NACK_PKT_RD)
3894                 pr_cont("NACK_PKT_RD ");
3895         if (cs & TX_CS_CONF_PART_ERR)
3896                 pr_cont("CONF_PART ");
3897         if (cs & TX_CS_PKT_PRT_ERR)
3898                 pr_cont("PKT_PTR ");
3899
3900         pr_cont(")\n");
3901 }
3902
3903 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3904 {
3905         u64 cs, logh, logl;
3906
3907         cs = nr64(TX_CS(rp->tx_channel));
3908         logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3909         logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3910
3911         netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3912                    rp->tx_channel,
3913                    (unsigned long long)cs,
3914                    (unsigned long long)logh,
3915                    (unsigned long long)logl);
3916
3917         niu_log_txchan_errors(np, rp, cs);
3918
3919         return -ENODEV;
3920 }
3921
3922 static int niu_mif_interrupt(struct niu *np)
3923 {
3924         u64 mif_status = nr64(MIF_STATUS);
3925         int phy_mdint = 0;
3926
3927         if (np->flags & NIU_FLAGS_XMAC) {
3928                 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3929
3930                 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3931                         phy_mdint = 1;
3932         }
3933
3934         netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3935                    (unsigned long long)mif_status, phy_mdint);
3936
3937         return -ENODEV;
3938 }
3939
3940 static void niu_xmac_interrupt(struct niu *np)
3941 {
3942         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3943         u64 val;
3944
3945         val = nr64_mac(XTXMAC_STATUS);
3946         if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3947                 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3948         if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3949                 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3950         if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3951                 mp->tx_fifo_errors++;
3952         if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3953                 mp->tx_overflow_errors++;
3954         if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3955                 mp->tx_max_pkt_size_errors++;
3956         if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3957                 mp->tx_underflow_errors++;
3958
3959         val = nr64_mac(XRXMAC_STATUS);
3960         if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3961                 mp->rx_local_faults++;
3962         if (val & XRXMAC_STATUS_RFLT_DET)
3963                 mp->rx_remote_faults++;
3964         if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3965                 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3966         if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3967                 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3968         if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3969                 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3970         if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3971                 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3972         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3973                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3974         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3975                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3976         if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3977                 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3978         if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3979                 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3980         if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3981                 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3982         if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3983                 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3984         if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3985                 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3986         if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3987                 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3988         if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3989                 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3990         if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
3991                 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3992         if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3993                 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3994         if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3995                 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3996         if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3997                 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3998         if (val & XRXMAC_STATUS_RXUFLOW)
3999                 mp->rx_underflows++;
4000         if (val & XRXMAC_STATUS_RXOFLOW)
4001                 mp->rx_overflows++;
4002
4003         val = nr64_mac(XMAC_FC_STAT);
4004         if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
4005                 mp->pause_off_state++;
4006         if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
4007                 mp->pause_on_state++;
4008         if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
4009                 mp->pause_received++;
4010 }
4011
4012 static void niu_bmac_interrupt(struct niu *np)
4013 {
4014         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4015         u64 val;
4016
4017         val = nr64_mac(BTXMAC_STATUS);
4018         if (val & BTXMAC_STATUS_UNDERRUN)
4019                 mp->tx_underflow_errors++;
4020         if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4021                 mp->tx_max_pkt_size_errors++;
4022         if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4023                 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4024         if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4025                 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4026
4027         val = nr64_mac(BRXMAC_STATUS);
4028         if (val & BRXMAC_STATUS_OVERFLOW)
4029                 mp->rx_overflows++;
4030         if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4031                 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4032         if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4033                 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4034         if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4035                 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4036         if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4037                 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4038
4039         val = nr64_mac(BMAC_CTRL_STATUS);
4040         if (val & BMAC_CTRL_STATUS_NOPAUSE)
4041                 mp->pause_off_state++;
4042         if (val & BMAC_CTRL_STATUS_PAUSE)
4043                 mp->pause_on_state++;
4044         if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4045                 mp->pause_received++;
4046 }
4047
4048 static int niu_mac_interrupt(struct niu *np)
4049 {
4050         if (np->flags & NIU_FLAGS_XMAC)
4051                 niu_xmac_interrupt(np);
4052         else
4053                 niu_bmac_interrupt(np);
4054
4055         return 0;
4056 }
4057
4058 static void niu_log_device_error(struct niu *np, u64 stat)
4059 {
4060         netdev_err(np->dev, "Core device errors ( ");
4061
4062         if (stat & SYS_ERR_MASK_META2)
4063                 pr_cont("META2 ");
4064         if (stat & SYS_ERR_MASK_META1)
4065                 pr_cont("META1 ");
4066         if (stat & SYS_ERR_MASK_PEU)
4067                 pr_cont("PEU ");
4068         if (stat & SYS_ERR_MASK_TXC)
4069                 pr_cont("TXC ");
4070         if (stat & SYS_ERR_MASK_RDMC)
4071                 pr_cont("RDMC ");
4072         if (stat & SYS_ERR_MASK_TDMC)
4073                 pr_cont("TDMC ");
4074         if (stat & SYS_ERR_MASK_ZCP)
4075                 pr_cont("ZCP ");
4076         if (stat & SYS_ERR_MASK_FFLP)
4077                 pr_cont("FFLP ");
4078         if (stat & SYS_ERR_MASK_IPP)
4079                 pr_cont("IPP ");
4080         if (stat & SYS_ERR_MASK_MAC)
4081                 pr_cont("MAC ");
4082         if (stat & SYS_ERR_MASK_SMX)
4083                 pr_cont("SMX ");
4084
4085         pr_cont(")\n");
4086 }
4087
4088 static int niu_device_error(struct niu *np)
4089 {
4090         u64 stat = nr64(SYS_ERR_STAT);
4091
4092         netdev_err(np->dev, "Core device error, stat[%llx]\n",
4093                    (unsigned long long)stat);
4094
4095         niu_log_device_error(np, stat);
4096
4097         return -ENODEV;
4098 }
4099
4100 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4101                               u64 v0, u64 v1, u64 v2)
4102 {
4103
4104         int i, err = 0;
4105
4106         lp->v0 = v0;
4107         lp->v1 = v1;
4108         lp->v2 = v2;
4109
4110         if (v1 & 0x00000000ffffffffULL) {
4111                 u32 rx_vec = (v1 & 0xffffffff);
4112
4113                 for (i = 0; i < np->num_rx_rings; i++) {
4114                         struct rx_ring_info *rp = &np->rx_rings[i];
4115
4116                         if (rx_vec & (1 << rp->rx_channel)) {
4117                                 int r = niu_rx_error(np, rp);
4118                                 if (r) {
4119                                         err = r;
4120                                 } else {
4121                                         if (!v0)
4122                                                 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4123                                                      RX_DMA_CTL_STAT_MEX);
4124                                 }
4125                         }
4126                 }
4127         }
4128         if (v1 & 0x7fffffff00000000ULL) {
4129                 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4130
4131                 for (i = 0; i < np->num_tx_rings; i++) {
4132                         struct tx_ring_info *rp = &np->tx_rings[i];
4133
4134                         if (tx_vec & (1 << rp->tx_channel)) {
4135                                 int r = niu_tx_error(np, rp);
4136                                 if (r)
4137                                         err = r;
4138                         }
4139                 }
4140         }
4141         if ((v0 | v1) & 0x8000000000000000ULL) {
4142                 int r = niu_mif_interrupt(np);
4143                 if (r)
4144                         err = r;
4145         }
4146         if (v2) {
4147                 if (v2 & 0x01ef) {
4148                         int r = niu_mac_interrupt(np);
4149                         if (r)
4150                                 err = r;
4151                 }
4152                 if (v2 & 0x0210) {
4153                         int r = niu_device_error(np);
4154                         if (r)
4155                                 err = r;
4156                 }
4157         }
4158
4159         if (err)
4160                 niu_enable_interrupts(np, 0);
4161
4162         return err;
4163 }
4164
4165 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4166                             int ldn)
4167 {
4168         struct rxdma_mailbox *mbox = rp->mbox;
4169         u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4170
4171         stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4172                       RX_DMA_CTL_STAT_RCRTO);
4173         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4174
4175         netif_printk(np, intr, KERN_DEBUG, np->dev,
4176                      "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
4177 }
4178
4179 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4180                             int ldn)
4181 {
4182         rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4183
4184         netif_printk(np, intr, KERN_DEBUG, np->dev,
4185                      "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
4186 }
4187
4188 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4189 {
4190         struct niu_parent *parent = np->parent;
4191         u32 rx_vec, tx_vec;
4192         int i;
4193
4194         tx_vec = (v0 >> 32);
4195         rx_vec = (v0 & 0xffffffff);
4196
4197         for (i = 0; i < np->num_rx_rings; i++) {
4198                 struct rx_ring_info *rp = &np->rx_rings[i];
4199                 int ldn = LDN_RXDMA(rp->rx_channel);
4200
4201                 if (parent->ldg_map[ldn] != ldg)
4202                         continue;
4203
4204                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4205                 if (rx_vec & (1 << rp->rx_channel))
4206                         niu_rxchan_intr(np, rp, ldn);
4207         }
4208
4209         for (i = 0; i < np->num_tx_rings; i++) {
4210                 struct tx_ring_info *rp = &np->tx_rings[i];
4211                 int ldn = LDN_TXDMA(rp->tx_channel);
4212
4213                 if (parent->ldg_map[ldn] != ldg)
4214                         continue;
4215
4216                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4217                 if (tx_vec & (1 << rp->tx_channel))
4218                         niu_txchan_intr(np, rp, ldn);
4219         }
4220 }
4221
4222 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4223                               u64 v0, u64 v1, u64 v2)
4224 {
4225         if (likely(napi_schedule_prep(&lp->napi))) {
4226                 lp->v0 = v0;
4227                 lp->v1 = v1;
4228                 lp->v2 = v2;
4229                 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4230                 __napi_schedule(&lp->napi);
4231         }
4232 }
4233
4234 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4235 {
4236         struct niu_ldg *lp = dev_id;
4237         struct niu *np = lp->np;
4238         int ldg = lp->ldg_num;
4239         unsigned long flags;
4240         u64 v0, v1, v2;
4241
4242         if (netif_msg_intr(np))
4243                 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4244                        __func__, lp, ldg);
4245
4246         spin_lock_irqsave(&np->lock, flags);
4247
4248         v0 = nr64(LDSV0(ldg));
4249         v1 = nr64(LDSV1(ldg));
4250         v2 = nr64(LDSV2(ldg));
4251
4252         if (netif_msg_intr(np))
4253                 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
4254                        (unsigned long long) v0,
4255                        (unsigned long long) v1,
4256                        (unsigned long long) v2);
4257
4258         if (unlikely(!v0 && !v1 && !v2)) {
4259                 spin_unlock_irqrestore(&np->lock, flags);
4260                 return IRQ_NONE;
4261         }
4262
4263         if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4264                 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4265                 if (err)
4266                         goto out;
4267         }
4268         if (likely(v0 & ~((u64)1 << LDN_MIF)))
4269                 niu_schedule_napi(np, lp, v0, v1, v2);
4270         else
4271                 niu_ldg_rearm(np, lp, 1);
4272 out:
4273         spin_unlock_irqrestore(&np->lock, flags);
4274
4275         return IRQ_HANDLED;
4276 }
4277
4278 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4279 {
4280         if (rp->mbox) {
4281                 np->ops->free_coherent(np->device,
4282                                        sizeof(struct rxdma_mailbox),
4283                                        rp->mbox, rp->mbox_dma);
4284                 rp->mbox = NULL;
4285         }
4286         if (rp->rcr) {
4287                 np->ops->free_coherent(np->device,
4288                                        MAX_RCR_RING_SIZE * sizeof(__le64),
4289                                        rp->rcr, rp->rcr_dma);
4290                 rp->rcr = NULL;
4291                 rp->rcr_table_size = 0;
4292                 rp->rcr_index = 0;
4293         }
4294         if (rp->rbr) {
4295                 niu_rbr_free(np, rp);
4296
4297                 np->ops->free_coherent(np->device,
4298                                        MAX_RBR_RING_SIZE * sizeof(__le32),
4299                                        rp->rbr, rp->rbr_dma);
4300                 rp->rbr = NULL;
4301                 rp->rbr_table_size = 0;
4302                 rp->rbr_index = 0;
4303         }
4304         kfree(rp->rxhash);
4305         rp->rxhash = NULL;
4306 }
4307
4308 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4309 {
4310         if (rp->mbox) {
4311                 np->ops->free_coherent(np->device,
4312                                        sizeof(struct txdma_mailbox),
4313                                        rp->mbox, rp->mbox_dma);
4314                 rp->mbox = NULL;
4315         }
4316         if (rp->descr) {
4317                 int i;
4318
4319                 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4320                         if (rp->tx_buffs[i].skb)
4321                                 (void) release_tx_packet(np, rp, i);
4322                 }
4323
4324                 np->ops->free_coherent(np->device,
4325                                        MAX_TX_RING_SIZE * sizeof(__le64),
4326                                        rp->descr, rp->descr_dma);
4327                 rp->descr = NULL;
4328                 rp->pending = 0;
4329                 rp->prod = 0;
4330                 rp->cons = 0;
4331                 rp->wrap_bit = 0;
4332         }
4333 }
4334
4335 static void niu_free_channels(struct niu *np)
4336 {
4337         int i;
4338
4339         if (np->rx_rings) {
4340                 for (i = 0; i < np->num_rx_rings; i++) {
4341                         struct rx_ring_info *rp = &np->rx_rings[i];
4342
4343                         niu_free_rx_ring_info(np, rp);
4344                 }
4345                 kfree(np->rx_rings);
4346                 np->rx_rings = NULL;
4347                 np->num_rx_rings = 0;
4348         }
4349
4350         if (np->tx_rings) {
4351                 for (i = 0; i < np->num_tx_rings; i++) {
4352                         struct tx_ring_info *rp = &np->tx_rings[i];
4353
4354                         niu_free_tx_ring_info(np, rp);
4355                 }
4356                 kfree(np->tx_rings);
4357                 np->tx_rings = NULL;
4358                 np->num_tx_rings = 0;
4359         }
4360 }
4361
4362 static int niu_alloc_rx_ring_info(struct niu *np,
4363                                   struct rx_ring_info *rp)
4364 {
4365         BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4366
4367         rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4368                              GFP_KERNEL);
4369         if (!rp->rxhash)
4370                 return -ENOMEM;
4371
4372         rp->mbox = np->ops->alloc_coherent(np->device,
4373                                            sizeof(struct rxdma_mailbox),
4374                                            &rp->mbox_dma, GFP_KERNEL);
4375         if (!rp->mbox)
4376                 return -ENOMEM;
4377         if ((unsigned long)rp->mbox & (64UL - 1)) {
4378                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4379                            rp->mbox);
4380                 return -EINVAL;
4381         }
4382
4383         rp->rcr = np->ops->alloc_coherent(np->device,
4384                                           MAX_RCR_RING_SIZE * sizeof(__le64),
4385                                           &rp->rcr_dma, GFP_KERNEL);
4386         if (!rp->rcr)
4387                 return -ENOMEM;
4388         if ((unsigned long)rp->rcr & (64UL - 1)) {
4389                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4390                            rp->rcr);
4391                 return -EINVAL;
4392         }
4393         rp->rcr_table_size = MAX_RCR_RING_SIZE;
4394         rp->rcr_index = 0;
4395
4396         rp->rbr = np->ops->alloc_coherent(np->device,
4397                                           MAX_RBR_RING_SIZE * sizeof(__le32),
4398                                           &rp->rbr_dma, GFP_KERNEL);
4399         if (!rp->rbr)
4400                 return -ENOMEM;
4401         if ((unsigned long)rp->rbr & (64UL - 1)) {
4402                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4403                            rp->rbr);
4404                 return -EINVAL;
4405         }
4406         rp->rbr_table_size = MAX_RBR_RING_SIZE;
4407         rp->rbr_index = 0;
4408         rp->rbr_pending = 0;
4409
4410         return 0;
4411 }
4412
4413 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4414 {
4415         int mtu = np->dev->mtu;
4416
4417         /* These values are recommended by the HW designers for fair
4418          * utilization of DRR amongst the rings.
4419          */
4420         rp->max_burst = mtu + 32;
4421         if (rp->max_burst > 4096)
4422                 rp->max_burst = 4096;
4423 }
4424
4425 static int niu_alloc_tx_ring_info(struct niu *np,
4426                                   struct tx_ring_info *rp)
4427 {
4428         BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4429
4430         rp->mbox = np->ops->alloc_coherent(np->device,
4431                                            sizeof(struct txdma_mailbox),
4432                                            &rp->mbox_dma, GFP_KERNEL);
4433         if (!rp->mbox)
4434                 return -ENOMEM;
4435         if ((unsigned long)rp->mbox & (64UL - 1)) {
4436                 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4437                            rp->mbox);
4438                 return -EINVAL;
4439         }
4440
4441         rp->descr = np->ops->alloc_coherent(np->device,
4442                                             MAX_TX_RING_SIZE * sizeof(__le64),
4443                                             &rp->descr_dma, GFP_KERNEL);
4444         if (!rp->descr)
4445                 return -ENOMEM;
4446         if ((unsigned long)rp->descr & (64UL - 1)) {
4447                 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4448                            rp->descr);
4449                 return -EINVAL;
4450         }
4451
4452         rp->pending = MAX_TX_RING_SIZE;
4453         rp->prod = 0;
4454         rp->cons = 0;
4455         rp->wrap_bit = 0;
4456
4457         /* XXX make these configurable... XXX */
4458         rp->mark_freq = rp->pending / 4;
4459
4460         niu_set_max_burst(np, rp);
4461
4462         return 0;
4463 }
4464
4465 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4466 {
4467         u16 bss;
4468
4469         bss = min(PAGE_SHIFT, 15);
4470
4471         rp->rbr_block_size = 1 << bss;
4472         rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4473
4474         rp->rbr_sizes[0] = 256;
4475         rp->rbr_sizes[1] = 1024;
4476         if (np->dev->mtu > ETH_DATA_LEN) {
4477                 switch (PAGE_SIZE) {
4478                 case 4 * 1024:
4479                         rp->rbr_sizes[2] = 4096;
4480                         break;
4481
4482                 default:
4483                         rp->rbr_sizes[2] = 8192;
4484                         break;
4485                 }
4486         } else {
4487                 rp->rbr_sizes[2] = 2048;
4488         }
4489         rp->rbr_sizes[3] = rp->rbr_block_size;
4490 }
4491
4492 static int niu_alloc_channels(struct niu *np)
4493 {
4494         struct niu_parent *parent = np->parent;
4495         int first_rx_channel, first_tx_channel;
4496         int i, port, err;
4497
4498         port = np->port;
4499         first_rx_channel = first_tx_channel = 0;
4500         for (i = 0; i < port; i++) {
4501                 first_rx_channel += parent->rxchan_per_port[i];
4502                 first_tx_channel += parent->txchan_per_port[i];
4503         }
4504
4505         np->num_rx_rings = parent->rxchan_per_port[port];
4506         np->num_tx_rings = parent->txchan_per_port[port];
4507
4508         np->dev->real_num_tx_queues = np->num_tx_rings;
4509
4510         np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4511                                GFP_KERNEL);
4512         err = -ENOMEM;
4513         if (!np->rx_rings)
4514                 goto out_err;
4515
4516         for (i = 0; i < np->num_rx_rings; i++) {
4517                 struct rx_ring_info *rp = &np->rx_rings[i];
4518
4519                 rp->np = np;
4520                 rp->rx_channel = first_rx_channel + i;
4521
4522                 err = niu_alloc_rx_ring_info(np, rp);
4523                 if (err)
4524                         goto out_err;
4525
4526                 niu_size_rbr(np, rp);
4527
4528                 /* XXX better defaults, configurable, etc... XXX */
4529                 rp->nonsyn_window = 64;
4530                 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4531                 rp->syn_window = 64;
4532                 rp->syn_threshold = rp->rcr_table_size - 64;
4533                 rp->rcr_pkt_threshold = 16;
4534                 rp->rcr_timeout = 8;
4535                 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4536                 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4537                         rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4538
4539                 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4540                 if (err)
4541                         return err;
4542         }
4543
4544         np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
4545                                GFP_KERNEL);
4546         err = -ENOMEM;
4547         if (!np->tx_rings)
4548                 goto out_err;
4549
4550         for (i = 0; i < np->num_tx_rings; i++) {
4551                 struct tx_ring_info *rp = &np->tx_rings[i];
4552
4553                 rp->np = np;
4554                 rp->tx_channel = first_tx_channel + i;
4555
4556                 err = niu_alloc_tx_ring_info(np, rp);
4557                 if (err)
4558                         goto out_err;
4559         }
4560
4561         return 0;
4562
4563 out_err:
4564         niu_free_channels(np);
4565         return err;
4566 }
4567
4568 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4569 {
4570         int limit = 1000;
4571
4572         while (--limit > 0) {
4573                 u64 val = nr64(TX_CS(channel));
4574                 if (val & TX_CS_SNG_STATE)
4575                         return 0;
4576         }
4577         return -ENODEV;
4578 }
4579
4580 static int niu_tx_channel_stop(struct niu *np, int channel)
4581 {
4582         u64 val = nr64(TX_CS(channel));
4583
4584         val |= TX_CS_STOP_N_GO;
4585         nw64(TX_CS(channel), val);
4586
4587         return niu_tx_cs_sng_poll(np, channel);
4588 }
4589
4590 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4591 {
4592         int limit = 1000;
4593
4594         while (--limit > 0) {
4595                 u64 val = nr64(TX_CS(channel));
4596                 if (!(val & TX_CS_RST))
4597                         return 0;
4598         }
4599         return -ENODEV;
4600 }
4601
4602 static int niu_tx_channel_reset(struct niu *np, int channel)
4603 {
4604         u64 val = nr64(TX_CS(channel));
4605         int err;
4606
4607         val |= TX_CS_RST;
4608         nw64(TX_CS(channel), val);
4609
4610         err = niu_tx_cs_reset_poll(np, channel);
4611         if (!err)
4612                 nw64(TX_RING_KICK(channel), 0);
4613
4614         return err;
4615 }
4616
4617 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4618 {
4619         u64 val;
4620
4621         nw64(TX_LOG_MASK1(channel), 0);
4622         nw64(TX_LOG_VAL1(channel), 0);
4623         nw64(TX_LOG_MASK2(channel), 0);
4624         nw64(TX_LOG_VAL2(channel), 0);
4625         nw64(TX_LOG_PAGE_RELO1(channel), 0);
4626         nw64(TX_LOG_PAGE_RELO2(channel), 0);
4627         nw64(TX_LOG_PAGE_HDL(channel), 0);
4628
4629         val  = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4630         val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4631         nw64(TX_LOG_PAGE_VLD(channel), val);
4632
4633         /* XXX TXDMA 32bit mode? XXX */
4634
4635         return 0;
4636 }
4637
4638 static void niu_txc_enable_port(struct niu *np, int on)
4639 {
4640         unsigned long flags;
4641         u64 val, mask;
4642
4643         niu_lock_parent(np, flags);
4644         val = nr64(TXC_CONTROL);
4645         mask = (u64)1 << np->port;
4646         if (on) {
4647                 val |= TXC_CONTROL_ENABLE | mask;
4648         } else {
4649                 val &= ~mask;
4650                 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4651                         val &= ~TXC_CONTROL_ENABLE;
4652         }
4653         nw64(TXC_CONTROL, val);
4654         niu_unlock_parent(np, flags);
4655 }
4656
4657 static void niu_txc_set_imask(struct niu *np, u64 imask)
4658 {
4659         unsigned long flags;
4660         u64 val;
4661
4662         niu_lock_parent(np, flags);
4663         val = nr64(TXC_INT_MASK);
4664         val &= ~TXC_INT_MASK_VAL(np->port);
4665         val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4666         niu_unlock_parent(np, flags);
4667 }
4668
4669 static void niu_txc_port_dma_enable(struct niu *np, int on)
4670 {
4671         u64 val = 0;
4672
4673         if (on) {
4674                 int i;
4675
4676                 for (i = 0; i < np->num_tx_rings; i++)
4677                         val |= (1 << np->tx_rings[i].tx_channel);
4678         }
4679         nw64(TXC_PORT_DMA(np->port), val);
4680 }
4681
4682 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4683 {
4684         int err, channel = rp->tx_channel;
4685         u64 val, ring_len;
4686
4687         err = niu_tx_channel_stop(np, channel);
4688         if (err)
4689                 return err;
4690
4691         err = niu_tx_channel_reset(np, channel);
4692         if (err)
4693                 return err;
4694
4695         err = niu_tx_channel_lpage_init(np, channel);
4696         if (err)
4697                 return err;
4698
4699         nw64(TXC_DMA_MAX(channel), rp->max_burst);
4700         nw64(TX_ENT_MSK(channel), 0);
4701
4702         if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4703                               TX_RNG_CFIG_STADDR)) {
4704                 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4705                            channel, (unsigned long long)rp->descr_dma);
4706                 return -EINVAL;
4707         }
4708
4709         /* The length field in TX_RNG_CFIG is measured in 64-byte
4710          * blocks.  rp->pending is the number of TX descriptors in
4711          * our ring, 8 bytes each, thus we divide by 8 bytes more
4712          * to get the proper value the chip wants.
4713          */
4714         ring_len = (rp->pending / 8);
4715
4716         val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4717                rp->descr_dma);
4718         nw64(TX_RNG_CFIG(channel), val);
4719
4720         if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4721             ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4722                 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4723                             channel, (unsigned long long)rp->mbox_dma);
4724                 return -EINVAL;
4725         }
4726         nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4727         nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4728
4729         nw64(TX_CS(channel), 0);
4730
4731         rp->last_pkt_cnt = 0;
4732
4733         return 0;
4734 }
4735
4736 static void niu_init_rdc_groups(struct niu *np)
4737 {
4738         struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4739         int i, first_table_num = tp->first_table_num;
4740
4741         for (i = 0; i < tp->num_tables; i++) {
4742                 struct rdc_table *tbl = &tp->tables[i];
4743                 int this_table = first_table_num + i;
4744                 int slot;
4745
4746                 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4747                         nw64(RDC_TBL(this_table, slot),
4748                              tbl->rxdma_channel[slot]);
4749         }
4750
4751         nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4752 }
4753
4754 static void niu_init_drr_weight(struct niu *np)
4755 {
4756         int type = phy_decode(np->parent->port_phy, np->port);
4757         u64 val;
4758
4759         switch (type) {
4760         case PORT_TYPE_10G:
4761                 val = PT_DRR_WEIGHT_DEFAULT_10G;
4762                 break;
4763
4764         case PORT_TYPE_1G:
4765         default:
4766                 val = PT_DRR_WEIGHT_DEFAULT_1G;
4767                 break;
4768         }
4769         nw64(PT_DRR_WT(np->port), val);
4770 }
4771
4772 static int niu_init_hostinfo(struct niu *np)
4773 {
4774         struct niu_parent *parent = np->parent;
4775         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4776         int i, err, num_alt = niu_num_alt_addr(np);
4777         int first_rdc_table = tp->first_table_num;
4778
4779         err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4780         if (err)
4781                 return err;
4782
4783         err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4784         if (err)
4785                 return err;
4786
4787         for (i = 0; i < num_alt; i++) {
4788                 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4789                 if (err)
4790                         return err;
4791         }
4792
4793         return 0;
4794 }
4795
4796 static int niu_rx_channel_reset(struct niu *np, int channel)
4797 {
4798         return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4799                                       RXDMA_CFIG1_RST, 1000, 10,
4800                                       "RXDMA_CFIG1");
4801 }
4802
4803 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4804 {
4805         u64 val;
4806
4807         nw64(RX_LOG_MASK1(channel), 0);
4808         nw64(RX_LOG_VAL1(channel), 0);
4809         nw64(RX_LOG_MASK2(channel), 0);
4810         nw64(RX_LOG_VAL2(channel), 0);
4811         nw64(RX_LOG_PAGE_RELO1(channel), 0);
4812         nw64(RX_LOG_PAGE_RELO2(channel), 0);
4813         nw64(RX_LOG_PAGE_HDL(channel), 0);
4814
4815         val  = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4816         val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4817         nw64(RX_LOG_PAGE_VLD(channel), val);
4818
4819         return 0;
4820 }
4821
4822 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4823 {
4824         u64 val;
4825
4826         val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4827                ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4828                ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4829                ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4830         nw64(RDC_RED_PARA(rp->rx_channel), val);
4831 }
4832
4833 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4834 {
4835         u64 val = 0;
4836
4837         *ret = 0;
4838         switch (rp->rbr_block_size) {
4839         case 4 * 1024:
4840                 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4841                 break;
4842         case 8 * 1024:
4843                 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4844                 break;
4845         case 16 * 1024:
4846                 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4847                 break;
4848         case 32 * 1024:
4849                 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4850                 break;
4851         default:
4852                 return -EINVAL;
4853         }
4854         val |= RBR_CFIG_B_VLD2;
4855         switch (rp->rbr_sizes[2]) {
4856         case 2 * 1024:
4857                 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4858                 break;
4859         case 4 * 1024:
4860                 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4861                 break;
4862         case 8 * 1024:
4863                 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4864                 break;
4865         case 16 * 1024:
4866                 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4867                 break;
4868
4869         default:
4870                 return -EINVAL;
4871         }
4872         val |= RBR_CFIG_B_VLD1;
4873         switch (rp->rbr_sizes[1]) {
4874         case 1 * 1024:
4875                 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4876                 break;
4877         case 2 * 1024:
4878                 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4879                 break;
4880         case 4 * 1024:
4881                 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4882                 break;
4883         case 8 * 1024:
4884                 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4885                 break;
4886
4887         default:
4888                 return -EINVAL;
4889         }
4890         val |= RBR_CFIG_B_VLD0;
4891         switch (rp->rbr_sizes[0]) {
4892         case 256:
4893                 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4894                 break;
4895         case 512:
4896                 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4897                 break;
4898         case 1 * 1024:
4899                 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4900                 break;
4901         case 2 * 1024:
4902                 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4903                 break;
4904
4905         default:
4906                 return -EINVAL;
4907         }
4908
4909         *ret = val;
4910         return 0;
4911 }
4912
4913 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4914 {
4915         u64 val = nr64(RXDMA_CFIG1(channel));
4916         int limit;
4917
4918         if (on)
4919                 val |= RXDMA_CFIG1_EN;
4920         else
4921                 val &= ~RXDMA_CFIG1_EN;
4922         nw64(RXDMA_CFIG1(channel), val);
4923
4924         limit = 1000;
4925         while (--limit > 0) {
4926                 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4927                         break;
4928                 udelay(10);
4929         }
4930         if (limit <= 0)
4931                 return -ENODEV;
4932         return 0;
4933 }
4934
4935 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4936 {
4937         int err, channel = rp->rx_channel;
4938         u64 val;
4939
4940         err = niu_rx_channel_reset(np, channel);
4941         if (err)
4942                 return err;
4943
4944         err = niu_rx_channel_lpage_init(np, channel);
4945         if (err)
4946                 return err;
4947
4948         niu_rx_channel_wred_init(np, rp);
4949
4950         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4951         nw64(RX_DMA_CTL_STAT(channel),
4952              (RX_DMA_CTL_STAT_MEX |
4953               RX_DMA_CTL_STAT_RCRTHRES |
4954               RX_DMA_CTL_STAT_RCRTO |
4955               RX_DMA_CTL_STAT_RBR_EMPTY));
4956         nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4957         nw64(RXDMA_CFIG2(channel),
4958              ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) |
4959               RXDMA_CFIG2_FULL_HDR));
4960         nw64(RBR_CFIG_A(channel),
4961              ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4962              (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4963         err = niu_compute_rbr_cfig_b(rp, &val);
4964         if (err)
4965                 return err;
4966         nw64(RBR_CFIG_B(channel), val);
4967         nw64(RCRCFIG_A(channel),
4968              ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4969              (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4970         nw64(RCRCFIG_B(channel),
4971              ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4972              RCRCFIG_B_ENTOUT |
4973              ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4974
4975         err = niu_enable_rx_channel(np, channel, 1);
4976         if (err)
4977                 return err;
4978
4979         nw64(RBR_KICK(channel), rp->rbr_index);
4980
4981         val = nr64(RX_DMA_CTL_STAT(channel));
4982         val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4983         nw64(RX_DMA_CTL_STAT(channel), val);
4984
4985         return 0;
4986 }
4987
4988 static int niu_init_rx_channels(struct niu *np)
4989 {
4990         unsigned long flags;
4991         u64 seed = jiffies_64;
4992         int err, i;
4993
4994         niu_lock_parent(np, flags);
4995         nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4996         nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4997         niu_unlock_parent(np, flags);
4998
4999         /* XXX RXDMA 32bit mode? XXX */
5000
5001         niu_init_rdc_groups(np);
5002         niu_init_drr_weight(np);
5003
5004         err = niu_init_hostinfo(np);
5005         if (err)
5006                 return err;
5007
5008         for (i = 0; i < np->num_rx_rings; i++) {
5009                 struct rx_ring_info *rp = &np->rx_rings[i];
5010
5011                 err = niu_init_one_rx_channel(np, rp);
5012                 if (err)
5013                         return err;
5014         }
5015
5016         return 0;
5017 }
5018
5019 static int niu_set_ip_frag_rule(struct niu *np)
5020 {
5021         struct niu_parent *parent = np->parent;
5022         struct niu_classifier *cp = &np->clas;
5023         struct niu_tcam_entry *tp;
5024         int index, err;
5025
5026         index = cp->tcam_top;
5027         tp = &parent->tcam[index];
5028
5029         /* Note that the noport bit is the same in both ipv4 and
5030          * ipv6 format TCAM entries.
5031          */
5032         memset(tp, 0, sizeof(*tp));
5033         tp->key[1] = TCAM_V4KEY1_NOPORT;
5034         tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5035         tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5036                           ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5037         err = tcam_write(np, index, tp->key, tp->key_mask);
5038         if (err)
5039                 return err;
5040         err = tcam_assoc_write(np, index, tp->assoc_data);
5041         if (err)
5042                 return err;
5043         tp->valid = 1;
5044         cp->tcam_valid_entries++;
5045
5046         return 0;
5047 }
5048
5049 static int niu_init_classifier_hw(struct niu *np)
5050 {
5051         struct niu_parent *parent = np->parent;
5052         struct niu_classifier *cp = &np->clas;
5053         int i, err;
5054
5055         nw64(H1POLY, cp->h1_init);
5056         nw64(H2POLY, cp->h2_init);
5057
5058         err = niu_init_hostinfo(np);
5059         if (err)
5060                 return err;
5061
5062         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5063                 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5064
5065                 vlan_tbl_write(np, i, np->port,
5066                                vp->vlan_pref, vp->rdc_num);
5067         }
5068
5069         for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5070                 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5071
5072                 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5073                                                 ap->rdc_num, ap->mac_pref);
5074                 if (err)
5075                         return err;
5076         }
5077
5078         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5079                 int index = i - CLASS_CODE_USER_PROG1;
5080
5081                 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5082                 if (err)
5083                         return err;
5084                 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5085                 if (err)
5086                         return err;
5087         }
5088
5089         err = niu_set_ip_frag_rule(np);
5090         if (err)
5091                 return err;
5092
5093         tcam_enable(np, 1);
5094
5095         return 0;
5096 }
5097
5098 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5099 {
5100         nw64(ZCP_RAM_DATA0, data[0]);
5101         nw64(ZCP_RAM_DATA1, data[1]);
5102         nw64(ZCP_RAM_DATA2, data[2]);
5103         nw64(ZCP_RAM_DATA3, data[3]);
5104         nw64(ZCP_RAM_DATA4, data[4]);
5105         nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5106         nw64(ZCP_RAM_ACC,
5107              (ZCP_RAM_ACC_WRITE |
5108               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5109               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5110
5111         return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5112                                    1000, 100);
5113 }
5114
5115 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5116 {
5117         int err;
5118
5119         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5120                                   1000, 100);
5121         if (err) {
5122                 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5123                            (unsigned long long)nr64(ZCP_RAM_ACC));
5124                 return err;
5125         }
5126
5127         nw64(ZCP_RAM_ACC,
5128              (ZCP_RAM_ACC_READ |
5129               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5130               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5131
5132         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5133                                   1000, 100);
5134         if (err) {
5135                 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5136                            (unsigned long long)nr64(ZCP_RAM_ACC));
5137                 return err;
5138         }
5139
5140         data[0] = nr64(ZCP_RAM_DATA0);
5141         data[1] = nr64(ZCP_RAM_DATA1);
5142         data[2] = nr64(ZCP_RAM_DATA2);
5143         data[3] = nr64(ZCP_RAM_DATA3);
5144         data[4] = nr64(ZCP_RAM_DATA4);
5145
5146         return 0;
5147 }
5148
5149 static void niu_zcp_cfifo_reset(struct niu *np)
5150 {
5151         u64 val = nr64(RESET_CFIFO);
5152
5153         val |= RESET_CFIFO_RST(np->port);
5154         nw64(RESET_CFIFO, val);
5155         udelay(10);
5156
5157         val &= ~RESET_CFIFO_RST(np->port);
5158         nw64(RESET_CFIFO, val);
5159 }
5160
5161 static int niu_init_zcp(struct niu *np)
5162 {
5163         u64 data[5], rbuf[5];
5164         int i, max, err;
5165
5166         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5167                 if (np->port == 0 || np->port == 1)
5168                         max = ATLAS_P0_P1_CFIFO_ENTRIES;
5169                 else
5170                         max = ATLAS_P2_P3_CFIFO_ENTRIES;
5171         } else
5172                 max = NIU_CFIFO_ENTRIES;
5173
5174         data[0] = 0;
5175         data[1] = 0;
5176         data[2] = 0;
5177         data[3] = 0;
5178         data[4] = 0;
5179
5180         for (i = 0; i < max; i++) {
5181                 err = niu_zcp_write(np, i, data);
5182                 if (err)
5183                         return err;
5184                 err = niu_zcp_read(np, i, rbuf);
5185                 if (err)
5186                         return err;
5187         }
5188
5189         niu_zcp_cfifo_reset(np);
5190         nw64(CFIFO_ECC(np->port), 0);
5191         nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5192         (void) nr64(ZCP_INT_STAT);
5193         nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5194
5195         return 0;
5196 }
5197
5198 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5199 {
5200         u64 val = nr64_ipp(IPP_CFIG);
5201
5202         nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5203         nw64_ipp(IPP_DFIFO_WR_PTR, index);
5204         nw64_ipp(IPP_DFIFO_WR0, data[0]);
5205         nw64_ipp(IPP_DFIFO_WR1, data[1]);
5206         nw64_ipp(IPP_DFIFO_WR2, data[2]);
5207         nw64_ipp(IPP_DFIFO_WR3, data[3]);
5208         nw64_ipp(IPP_DFIFO_WR4, data[4]);
5209         nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5210 }
5211
5212 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5213 {
5214         nw64_ipp(IPP_DFIFO_RD_PTR, index);
5215         data[0] = nr64_ipp(IPP_DFIFO_RD0);
5216         data[1] = nr64_ipp(IPP_DFIFO_RD1);
5217         data[2] = nr64_ipp(IPP_DFIFO_RD2);
5218         data[3] = nr64_ipp(IPP_DFIFO_RD3);
5219         data[4] = nr64_ipp(IPP_DFIFO_RD4);
5220 }
5221
5222 static int niu_ipp_reset(struct niu *np)
5223 {
5224         return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5225                                           1000, 100, "IPP_CFIG");
5226 }
5227
5228 static int niu_init_ipp(struct niu *np)
5229 {
5230         u64 data[5], rbuf[5], val;
5231         int i, max, err;
5232
5233         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5234                 if (np->port == 0 || np->port == 1)
5235                         max = ATLAS_P0_P1_DFIFO_ENTRIES;
5236                 else
5237                         max = ATLAS_P2_P3_DFIFO_ENTRIES;
5238         } else
5239                 max = NIU_DFIFO_ENTRIES;
5240
5241         data[0] = 0;
5242         data[1] = 0;
5243         data[2] = 0;
5244         data[3] = 0;
5245         data[4] = 0;
5246
5247         for (i = 0; i < max; i++) {
5248                 niu_ipp_write(np, i, data);
5249                 niu_ipp_read(np, i, rbuf);
5250         }
5251
5252         (void) nr64_ipp(IPP_INT_STAT);
5253         (void) nr64_ipp(IPP_INT_STAT);
5254
5255         err = niu_ipp_reset(np);
5256         if (err)
5257                 return err;
5258
5259         (void) nr64_ipp(IPP_PKT_DIS);
5260         (void) nr64_ipp(IPP_BAD_CS_CNT);
5261         (void) nr64_ipp(IPP_ECC);
5262
5263         (void) nr64_ipp(IPP_INT_STAT);
5264
5265         nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5266
5267         val = nr64_ipp(IPP_CFIG);
5268         val &= ~IPP_CFIG_IP_MAX_PKT;
5269         val |= (IPP_CFIG_IPP_ENABLE |
5270                 IPP_CFIG_DFIFO_ECC_EN |
5271                 IPP_CFIG_DROP_BAD_CRC |
5272                 IPP_CFIG_CKSUM_EN |
5273                 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5274         nw64_ipp(IPP_CFIG, val);
5275
5276         return 0;
5277 }
5278
5279 static void niu_handle_led(struct niu *np, int status)
5280 {
5281         u64 val;
5282         val = nr64_mac(XMAC_CONFIG);
5283
5284         if ((np->flags & NIU_FLAGS_10G) != 0 &&
5285             (np->flags & NIU_FLAGS_FIBER) != 0) {
5286                 if (status) {
5287                         val |= XMAC_CONFIG_LED_POLARITY;
5288                         val &= ~XMAC_CONFIG_FORCE_LED_ON;
5289                 } else {
5290                         val |= XMAC_CONFIG_FORCE_LED_ON;
5291                         val &= ~XMAC_CONFIG_LED_POLARITY;
5292                 }
5293         }
5294
5295         nw64_mac(XMAC_CONFIG, val);
5296 }
5297
5298 static void niu_init_xif_xmac(struct niu *np)
5299 {
5300         struct niu_link_config *lp = &np->link_config;
5301         u64 val;
5302
5303         if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5304                 val = nr64(MIF_CONFIG);
5305                 val |= MIF_CONFIG_ATCA_GE;
5306                 nw64(MIF_CONFIG, val);
5307         }
5308
5309         val = nr64_mac(XMAC_CONFIG);
5310         val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5311
5312         val |= XMAC_CONFIG_TX_OUTPUT_EN;
5313
5314         if (lp->loopback_mode == LOOPBACK_MAC) {
5315                 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5316                 val |= XMAC_CONFIG_LOOPBACK;
5317         } else {
5318                 val &= ~XMAC_CONFIG_LOOPBACK;
5319         }
5320
5321         if (np->flags & NIU_FLAGS_10G) {
5322                 val &= ~XMAC_CONFIG_LFS_DISABLE;
5323         } else {
5324                 val |= XMAC_CONFIG_LFS_DISABLE;
5325                 if (!(np->flags & NIU_FLAGS_FIBER) &&
5326                     !(np->flags & NIU_FLAGS_XCVR_SERDES))
5327                         val |= XMAC_CONFIG_1G_PCS_BYPASS;
5328                 else
5329                         val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5330         }
5331
5332         val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5333
5334         if (lp->active_speed == SPEED_100)
5335                 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5336         else
5337                 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5338
5339         nw64_mac(XMAC_CONFIG, val);
5340
5341         val = nr64_mac(XMAC_CONFIG);
5342         val &= ~XMAC_CONFIG_MODE_MASK;
5343         if (np->flags & NIU_FLAGS_10G) {
5344                 val |= XMAC_CONFIG_MODE_XGMII;
5345         } else {
5346                 if (lp->active_speed == SPEED_1000)
5347                         val |= XMAC_CONFIG_MODE_GMII;
5348                 else
5349                         val |= XMAC_CONFIG_MODE_MII;
5350         }
5351
5352         nw64_mac(XMAC_CONFIG, val);
5353 }
5354
5355 static void niu_init_xif_bmac(struct niu *np)
5356 {
5357         struct niu_link_config *lp = &np->link_config;
5358         u64 val;
5359
5360         val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5361
5362         if (lp->loopback_mode == LOOPBACK_MAC)
5363                 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5364         else
5365                 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5366
5367         if (lp->active_speed == SPEED_1000)
5368                 val |= BMAC_XIF_CONFIG_GMII_MODE;
5369         else
5370                 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5371
5372         val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5373                  BMAC_XIF_CONFIG_LED_POLARITY);
5374
5375         if (!(np->flags & NIU_FLAGS_10G) &&
5376             !(np->flags & NIU_FLAGS_FIBER) &&
5377             lp->active_speed == SPEED_100)
5378                 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5379         else
5380                 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5381
5382         nw64_mac(BMAC_XIF_CONFIG, val);
5383 }
5384
5385 static void niu_init_xif(struct niu *np)
5386 {
5387         if (np->flags & NIU_FLAGS_XMAC)
5388                 niu_init_xif_xmac(np);
5389         else
5390                 niu_init_xif_bmac(np);
5391 }
5392
5393 static void niu_pcs_mii_reset(struct niu *np)
5394 {
5395         int limit = 1000;
5396         u64 val = nr64_pcs(PCS_MII_CTL);
5397         val |= PCS_MII_CTL_RST;
5398         nw64_pcs(PCS_MII_CTL, val);
5399         while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5400                 udelay(100);
5401                 val = nr64_pcs(PCS_MII_CTL);
5402         }
5403 }
5404
5405 static void niu_xpcs_reset(struct niu *np)
5406 {
5407         int limit = 1000;
5408         u64 val = nr64_xpcs(XPCS_CONTROL1);
5409         val |= XPCS_CONTROL1_RESET;
5410         nw64_xpcs(XPCS_CONTROL1, val);
5411         while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5412                 udelay(100);
5413                 val = nr64_xpcs(XPCS_CONTROL1);
5414         }
5415 }
5416
5417 static int niu_init_pcs(struct niu *np)
5418 {
5419         struct niu_link_config *lp = &np->link_config;
5420         u64 val;
5421
5422         switch (np->flags & (NIU_FLAGS_10G |
5423                              NIU_FLAGS_FIBER |
5424                              NIU_FLAGS_XCVR_SERDES)) {
5425         case NIU_FLAGS_FIBER:
5426                 /* 1G fiber */
5427                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5428                 nw64_pcs(PCS_DPATH_MODE, 0);
5429                 niu_pcs_mii_reset(np);
5430                 break;
5431
5432         case NIU_FLAGS_10G:
5433         case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5434         case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5435                 /* 10G SERDES */
5436                 if (!(np->flags & NIU_FLAGS_XMAC))
5437                         return -EINVAL;
5438
5439                 /* 10G copper or fiber */
5440                 val = nr64_mac(XMAC_CONFIG);
5441                 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5442                 nw64_mac(XMAC_CONFIG, val);
5443
5444                 niu_xpcs_reset(np);
5445
5446                 val = nr64_xpcs(XPCS_CONTROL1);
5447                 if (lp->loopback_mode == LOOPBACK_PHY)
5448                         val |= XPCS_CONTROL1_LOOPBACK;
5449                 else
5450                         val &= ~XPCS_CONTROL1_LOOPBACK;
5451                 nw64_xpcs(XPCS_CONTROL1, val);
5452
5453                 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5454                 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5455                 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5456                 break;
5457
5458
5459         case NIU_FLAGS_XCVR_SERDES:
5460                 /* 1G SERDES */
5461                 niu_pcs_mii_reset(np);
5462                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5463                 nw64_pcs(PCS_DPATH_MODE, 0);
5464                 break;
5465
5466         case 0:
5467                 /* 1G copper */
5468         case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5469                 /* 1G RGMII FIBER */
5470                 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5471                 niu_pcs_mii_reset(np);
5472                 break;
5473
5474         default:
5475                 return -EINVAL;
5476         }
5477
5478         return 0;
5479 }
5480
5481 static int niu_reset_tx_xmac(struct niu *np)
5482 {
5483         return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5484                                           (XTXMAC_SW_RST_REG_RS |
5485                                            XTXMAC_SW_RST_SOFT_RST),
5486                                           1000, 100, "XTXMAC_SW_RST");
5487 }
5488
5489 static int niu_reset_tx_bmac(struct niu *np)
5490 {
5491         int limit;
5492
5493         nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5494         limit = 1000;
5495         while (--limit >= 0) {
5496                 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5497                         break;
5498                 udelay(100);
5499         }
5500         if (limit < 0) {
5501                 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
5502                         np->port,
5503                         (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5504                 return -ENODEV;
5505         }
5506
5507         return 0;
5508 }
5509
5510 static int niu_reset_tx_mac(struct niu *np)
5511 {
5512         if (np->flags & NIU_FLAGS_XMAC)
5513                 return niu_reset_tx_xmac(np);
5514         else
5515                 return niu_reset_tx_bmac(np);
5516 }
5517
5518 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5519 {
5520         u64 val;
5521
5522         val = nr64_mac(XMAC_MIN);
5523         val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5524                  XMAC_MIN_RX_MIN_PKT_SIZE);
5525         val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5526         val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5527         nw64_mac(XMAC_MIN, val);
5528
5529         nw64_mac(XMAC_MAX, max);
5530
5531         nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5532
5533         val = nr64_mac(XMAC_IPG);
5534         if (np->flags & NIU_FLAGS_10G) {
5535                 val &= ~XMAC_IPG_IPG_XGMII;
5536                 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5537         } else {
5538                 val &= ~XMAC_IPG_IPG_MII_GMII;
5539                 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5540         }
5541         nw64_mac(XMAC_IPG, val);
5542
5543         val = nr64_mac(XMAC_CONFIG);
5544         val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5545                  XMAC_CONFIG_STRETCH_MODE |
5546                  XMAC_CONFIG_VAR_MIN_IPG_EN |
5547                  XMAC_CONFIG_TX_ENABLE);
5548         nw64_mac(XMAC_CONFIG, val);
5549
5550         nw64_mac(TXMAC_FRM_CNT, 0);
5551         nw64_mac(TXMAC_BYTE_CNT, 0);
5552 }
5553
5554 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5555 {
5556         u64 val;
5557
5558         nw64_mac(BMAC_MIN_FRAME, min);
5559         nw64_mac(BMAC_MAX_FRAME, max);
5560
5561         nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5562         nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5563         nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5564
5565         val = nr64_mac(BTXMAC_CONFIG);
5566         val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5567                  BTXMAC_CONFIG_ENABLE);
5568         nw64_mac(BTXMAC_CONFIG, val);
5569 }
5570
5571 static void niu_init_tx_mac(struct niu *np)
5572 {
5573         u64 min, max;
5574
5575         min = 64;
5576         if (np->dev->mtu > ETH_DATA_LEN)
5577                 max = 9216;
5578         else
5579                 max = 1522;
5580
5581         /* The XMAC_MIN register only accepts values for TX min which
5582          * have the low 3 bits cleared.
5583          */
5584         BUG_ON(min & 0x7);
5585
5586         if (np->flags & NIU_FLAGS_XMAC)
5587                 niu_init_tx_xmac(np, min, max);
5588         else
5589                 niu_init_tx_bmac(np, min, max);
5590 }
5591
5592 static int niu_reset_rx_xmac(struct niu *np)
5593 {
5594         int limit;
5595
5596         nw64_mac(XRXMAC_SW_RST,
5597                  XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5598         limit = 1000;
5599         while (--limit >= 0) {
5600                 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5601                                                  XRXMAC_SW_RST_SOFT_RST)))
5602                         break;
5603                 udelay(100);
5604         }
5605         if (limit < 0) {
5606                 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
5607                         np->port,
5608                         (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5609                 return -ENODEV;
5610         }
5611
5612         return 0;
5613 }
5614
5615 static int niu_reset_rx_bmac(struct niu *np)
5616 {
5617         int limit;
5618
5619         nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5620         limit = 1000;
5621         while (--limit >= 0) {
5622                 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5623                         break;
5624                 udelay(100);
5625         }
5626         if (limit < 0) {
5627                 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
5628                         np->port,
5629                         (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5630                 return -ENODEV;
5631         }
5632
5633         return 0;
5634 }
5635
5636 static int niu_reset_rx_mac(struct niu *np)
5637 {
5638         if (np->flags & NIU_FLAGS_XMAC)
5639                 return niu_reset_rx_xmac(np);
5640         else
5641                 return niu_reset_rx_bmac(np);
5642 }
5643
5644 static void niu_init_rx_xmac(struct niu *np)
5645 {
5646         struct niu_parent *parent = np->parent;
5647         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5648         int first_rdc_table = tp->first_table_num;
5649         unsigned long i;
5650         u64 val;
5651
5652         nw64_mac(XMAC_ADD_FILT0, 0);
5653         nw64_mac(XMAC_ADD_FILT1, 0);
5654         nw64_mac(XMAC_ADD_FILT2, 0);
5655         nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5656         nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5657         for (i = 0; i < MAC_NUM_HASH; i++)
5658                 nw64_mac(XMAC_HASH_TBL(i), 0);
5659         nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5660         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5661         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5662
5663         val = nr64_mac(XMAC_CONFIG);
5664         val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5665                  XMAC_CONFIG_PROMISCUOUS |
5666                  XMAC_CONFIG_PROMISC_GROUP |
5667                  XMAC_CONFIG_ERR_CHK_DIS |
5668                  XMAC_CONFIG_RX_CRC_CHK_DIS |
5669                  XMAC_CONFIG_RESERVED_MULTICAST |
5670                  XMAC_CONFIG_RX_CODEV_CHK_DIS |
5671                  XMAC_CONFIG_ADDR_FILTER_EN |
5672                  XMAC_CONFIG_RCV_PAUSE_ENABLE |
5673                  XMAC_CONFIG_STRIP_CRC |
5674                  XMAC_CONFIG_PASS_FLOW_CTRL |
5675                  XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5676         val |= (XMAC_CONFIG_HASH_FILTER_EN);
5677         nw64_mac(XMAC_CONFIG, val);
5678
5679         nw64_mac(RXMAC_BT_CNT, 0);
5680         nw64_mac(RXMAC_BC_FRM_CNT, 0);
5681         nw64_mac(RXMAC_MC_FRM_CNT, 0);
5682         nw64_mac(RXMAC_FRAG_CNT, 0);
5683         nw64_mac(RXMAC_HIST_CNT1, 0);
5684         nw64_mac(RXMAC_HIST_CNT2, 0);
5685         nw64_mac(RXMAC_HIST_CNT3, 0);
5686         nw64_mac(RXMAC_HIST_CNT4, 0);
5687         nw64_mac(RXMAC_HIST_CNT5, 0);
5688         nw64_mac(RXMAC_HIST_CNT6, 0);
5689         nw64_mac(RXMAC_HIST_CNT7, 0);
5690         nw64_mac(RXMAC_MPSZER_CNT, 0);
5691         nw64_mac(RXMAC_CRC_ER_CNT, 0);
5692         nw64_mac(RXMAC_CD_VIO_CNT, 0);
5693         nw64_mac(LINK_FAULT_CNT, 0);
5694 }
5695
5696 static void niu_init_rx_bmac(struct niu *np)
5697 {
5698         struct niu_parent *parent = np->parent;
5699         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5700         int first_rdc_table = tp->first_table_num;
5701         unsigned long i;
5702         u64 val;
5703
5704         nw64_mac(BMAC_ADD_FILT0, 0);
5705         nw64_mac(BMAC_ADD_FILT1, 0);
5706         nw64_mac(BMAC_ADD_FILT2, 0);
5707         nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5708         nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5709         for (i = 0; i < MAC_NUM_HASH; i++)
5710                 nw64_mac(BMAC_HASH_TBL(i), 0);
5711         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5712         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5713         nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5714
5715         val = nr64_mac(BRXMAC_CONFIG);
5716         val &= ~(BRXMAC_CONFIG_ENABLE |
5717                  BRXMAC_CONFIG_STRIP_PAD |
5718                  BRXMAC_CONFIG_STRIP_FCS |
5719                  BRXMAC_CONFIG_PROMISC |
5720                  BRXMAC_CONFIG_PROMISC_GRP |
5721                  BRXMAC_CONFIG_ADDR_FILT_EN |
5722                  BRXMAC_CONFIG_DISCARD_DIS);
5723         val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5724         nw64_mac(BRXMAC_CONFIG, val);
5725
5726         val = nr64_mac(BMAC_ADDR_CMPEN);
5727         val |= BMAC_ADDR_CMPEN_EN0;
5728         nw64_mac(BMAC_ADDR_CMPEN, val);
5729 }
5730
5731 static void niu_init_rx_mac(struct niu *np)
5732 {
5733         niu_set_primary_mac(np, np->dev->dev_addr);
5734
5735         if (np->flags & NIU_FLAGS_XMAC)
5736                 niu_init_rx_xmac(np);
5737         else
5738                 niu_init_rx_bmac(np);
5739 }
5740
5741 static void niu_enable_tx_xmac(struct niu *np, int on)
5742 {
5743         u64 val = nr64_mac(XMAC_CONFIG);
5744
5745         if (on)
5746                 val |= XMAC_CONFIG_TX_ENABLE;
5747         else
5748                 val &= ~XMAC_CONFIG_TX_ENABLE;
5749         nw64_mac(XMAC_CONFIG, val);
5750 }
5751
5752 static void niu_enable_tx_bmac(struct niu *np, int on)
5753 {
5754         u64 val = nr64_mac(BTXMAC_CONFIG);
5755
5756         if (on)
5757                 val |= BTXMAC_CONFIG_ENABLE;
5758         else
5759                 val &= ~BTXMAC_CONFIG_ENABLE;
5760         nw64_mac(BTXMAC_CONFIG, val);
5761 }
5762
5763 static void niu_enable_tx_mac(struct niu *np, int on)
5764 {
5765         if (np->flags & NIU_FLAGS_XMAC)
5766                 niu_enable_tx_xmac(np, on);
5767         else
5768                 niu_enable_tx_bmac(np, on);
5769 }
5770
5771 static void niu_enable_rx_xmac(struct niu *np, int on)
5772 {
5773         u64 val = nr64_mac(XMAC_CONFIG);
5774
5775         val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5776                  XMAC_CONFIG_PROMISCUOUS);
5777
5778         if (np->flags & NIU_FLAGS_MCAST)
5779                 val |= XMAC_CONFIG_HASH_FILTER_EN;
5780         if (np->flags & NIU_FLAGS_PROMISC)
5781                 val |= XMAC_CONFIG_PROMISCUOUS;
5782
5783         if (on)
5784                 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5785         else
5786                 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5787         nw64_mac(XMAC_CONFIG, val);
5788 }
5789
5790 static void niu_enable_rx_bmac(struct niu *np, int on)
5791 {
5792         u64 val = nr64_mac(BRXMAC_CONFIG);
5793
5794         val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5795                  BRXMAC_CONFIG_PROMISC);
5796
5797         if (np->flags & NIU_FLAGS_MCAST)
5798                 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5799         if (np->flags & NIU_FLAGS_PROMISC)
5800                 val |= BRXMAC_CONFIG_PROMISC;
5801
5802         if (on)
5803                 val |= BRXMAC_CONFIG_ENABLE;
5804         else
5805                 val &= ~BRXMAC_CONFIG_ENABLE;
5806         nw64_mac(BRXMAC_CONFIG, val);
5807 }
5808
5809 static void niu_enable_rx_mac(struct niu *np, int on)
5810 {
5811         if (np->flags & NIU_FLAGS_XMAC)
5812                 niu_enable_rx_xmac(np, on);
5813         else
5814                 niu_enable_rx_bmac(np, on);
5815 }
5816
5817 static int niu_init_mac(struct niu *np)
5818 {
5819         int err;
5820
5821         niu_init_xif(np);
5822         err = niu_init_pcs(np);
5823         if (err)
5824                 return err;
5825
5826         err = niu_reset_tx_mac(np);
5827         if (err)
5828                 return err;
5829         niu_init_tx_mac(np);
5830         err = niu_reset_rx_mac(np);
5831         if (err)
5832                 return err;
5833         niu_init_rx_mac(np);
5834
5835         /* This looks hookey but the RX MAC reset we just did will
5836          * undo some of the state we setup in niu_init_tx_mac() so we
5837          * have to call it again.  In particular, the RX MAC reset will
5838          * set the XMAC_MAX register back to it's default value.
5839          */
5840         niu_init_tx_mac(np);
5841         niu_enable_tx_mac(np, 1);
5842
5843         niu_enable_rx_mac(np, 1);
5844
5845         return 0;
5846 }
5847
5848 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5849 {
5850         (void) niu_tx_channel_stop(np, rp->tx_channel);
5851 }
5852
5853 static void niu_stop_tx_channels(struct niu *np)
5854 {
5855         int i;
5856
5857         for (i = 0; i < np->num_tx_rings; i++) {
5858                 struct tx_ring_info *rp = &np->tx_rings[i];
5859
5860                 niu_stop_one_tx_channel(np, rp);
5861         }
5862 }
5863
5864 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5865 {
5866         (void) niu_tx_channel_reset(np, rp->tx_channel);
5867 }
5868
5869 static void niu_reset_tx_channels(struct niu *np)
5870 {
5871         int i;
5872
5873         for (i = 0; i < np->num_tx_rings; i++) {
5874                 struct tx_ring_info *rp = &np->tx_rings[i];
5875
5876                 niu_reset_one_tx_channel(np, rp);
5877         }
5878 }
5879
5880 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5881 {
5882         (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5883 }
5884
5885 static void niu_stop_rx_channels(struct niu *np)
5886 {
5887         int i;
5888
5889         for (i = 0; i < np->num_rx_rings; i++) {
5890                 struct rx_ring_info *rp = &np->rx_rings[i];
5891
5892                 niu_stop_one_rx_channel(np, rp);
5893         }
5894 }
5895
5896 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5897 {
5898         int channel = rp->rx_channel;
5899
5900         (void) niu_rx_channel_reset(np, channel);
5901         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5902         nw64(RX_DMA_CTL_STAT(channel), 0);
5903         (void) niu_enable_rx_channel(np, channel, 0);
5904 }
5905
5906 static void niu_reset_rx_channels(struct niu *np)
5907 {
5908         int i;
5909
5910         for (i = 0; i < np->num_rx_rings; i++) {
5911                 struct rx_ring_info *rp = &np->rx_rings[i];
5912
5913                 niu_reset_one_rx_channel(np, rp);
5914         }
5915 }
5916
5917 static void niu_disable_ipp(struct niu *np)
5918 {
5919         u64 rd, wr, val;
5920         int limit;
5921
5922         rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5923         wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5924         limit = 100;
5925         while (--limit >= 0 && (rd != wr)) {
5926                 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5927                 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5928         }
5929         if (limit < 0 &&
5930             (rd != 0 && wr != 1)) {
5931                 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5932                            (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5933                            (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
5934         }
5935
5936         val = nr64_ipp(IPP_CFIG);
5937         val &= ~(IPP_CFIG_IPP_ENABLE |
5938                  IPP_CFIG_DFIFO_ECC_EN |
5939                  IPP_CFIG_DROP_BAD_CRC |
5940                  IPP_CFIG_CKSUM_EN);
5941         nw64_ipp(IPP_CFIG, val);
5942
5943         (void) niu_ipp_reset(np);
5944 }
5945
5946 static int niu_init_hw(struct niu *np)
5947 {
5948         int i, err;
5949
5950         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
5951         niu_txc_enable_port(np, 1);
5952         niu_txc_port_dma_enable(np, 1);
5953         niu_txc_set_imask(np, 0);
5954
5955         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
5956         for (i = 0; i < np->num_tx_rings; i++) {
5957                 struct tx_ring_info *rp = &np->tx_rings[i];
5958
5959                 err = niu_init_one_tx_channel(np, rp);
5960                 if (err)
5961                         return err;
5962         }
5963
5964         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
5965         err = niu_init_rx_channels(np);
5966         if (err)
5967                 goto out_uninit_tx_channels;
5968
5969         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
5970         err = niu_init_classifier_hw(np);
5971         if (err)
5972                 goto out_uninit_rx_channels;
5973
5974         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
5975         err = niu_init_zcp(np);
5976         if (err)
5977                 goto out_uninit_rx_channels;
5978
5979         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
5980         err = niu_init_ipp(np);
5981         if (err)
5982                 goto out_uninit_rx_channels;
5983
5984         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
5985         err = niu_init_mac(np);
5986         if (err)
5987                 goto out_uninit_ipp;
5988
5989         return 0;
5990
5991 out_uninit_ipp:
5992         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
5993         niu_disable_ipp(np);
5994
5995 out_uninit_rx_channels:
5996         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
5997         niu_stop_rx_channels(np);
5998         niu_reset_rx_channels(np);
5999
6000 out_uninit_tx_channels:
6001         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
6002         niu_stop_tx_channels(np);
6003         niu_reset_tx_channels(np);
6004
6005         return err;
6006 }
6007
6008 static void niu_stop_hw(struct niu *np)
6009 {
6010         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
6011         niu_enable_interrupts(np, 0);
6012
6013         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
6014         niu_enable_rx_mac(np, 0);
6015
6016         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
6017         niu_disable_ipp(np);
6018
6019         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
6020         niu_stop_tx_channels(np);
6021
6022         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
6023         niu_stop_rx_channels(np);
6024
6025         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
6026         niu_reset_tx_channels(np);
6027
6028         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
6029         niu_reset_rx_channels(np);
6030 }
6031
6032 static void niu_set_irq_name(struct niu *np)
6033 {
6034         int port = np->port;
6035         int i, j = 1;
6036
6037         sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6038
6039         if (port == 0) {
6040                 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6041                 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6042                 j = 3;
6043         }
6044
6045         for (i = 0; i < np->num_ldg - j; i++) {
6046                 if (i < np->num_rx_rings)
6047                         sprintf(np->irq_name[i+j], "%s-rx-%d",
6048                                 np->dev->name, i);
6049                 else if (i < np->num_tx_rings + np->num_rx_rings)
6050                         sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6051                                 i - np->num_rx_rings);
6052         }
6053 }
6054
6055 static int niu_request_irq(struct niu *np)
6056 {
6057         int i, j, err;
6058
6059         niu_set_irq_name(np);
6060
6061         err = 0;
6062         for (i = 0; i < np->num_ldg; i++) {
6063                 struct niu_ldg *lp = &np->ldg[i];
6064
6065                 err = request_irq(lp->irq, niu_interrupt,
6066                                   IRQF_SHARED | IRQF_SAMPLE_RANDOM,
6067                                   np->irq_name[i], lp);
6068                 if (err)
6069                         goto out_free_irqs;
6070
6071         }
6072
6073         return 0;
6074
6075 out_free_irqs:
6076         for (j = 0; j < i; j++) {
6077                 struct niu_ldg *lp = &np->ldg[j];
6078
6079                 free_irq(lp->irq, lp);
6080         }
6081         return err;
6082 }
6083
6084 static void niu_free_irq(struct niu *np)
6085 {
6086         int i;
6087
6088         for (i = 0; i < np->num_ldg; i++) {
6089                 struct niu_ldg *lp = &np->ldg[i];
6090
6091                 free_irq(lp->irq, lp);
6092         }
6093 }
6094
6095 static void niu_enable_napi(struct niu *np)
6096 {
6097         int i;
6098
6099         for (i = 0; i < np->num_ldg; i++)
6100                 napi_enable(&np->ldg[i].napi);
6101 }
6102
6103 static void niu_disable_napi(struct niu *np)
6104 {
6105         int i;
6106
6107         for (i = 0; i < np->num_ldg; i++)
6108                 napi_disable(&np->ldg[i].napi);
6109 }
6110
6111 static int niu_open(struct net_device *dev)
6112 {
6113         struct niu *np = netdev_priv(dev);
6114         int err;
6115
6116         netif_carrier_off(dev);
6117
6118         err = niu_alloc_channels(np);
6119         if (err)
6120                 goto out_err;
6121
6122         err = niu_enable_interrupts(np, 0);
6123         if (err)
6124                 goto out_free_channels;
6125
6126         err = niu_request_irq(np);
6127         if (err)
6128                 goto out_free_channels;
6129
6130         niu_enable_napi(np);
6131
6132         spin_lock_irq(&np->lock);
6133
6134         err = niu_init_hw(np);
6135         if (!err) {
6136                 init_timer(&np->timer);
6137                 np->timer.expires = jiffies + HZ;
6138                 np->timer.data = (unsigned long) np;
6139                 np->timer.function = niu_timer;
6140
6141                 err = niu_enable_interrupts(np, 1);
6142                 if (err)
6143                         niu_stop_hw(np);
6144         }
6145
6146         spin_unlock_irq(&np->lock);
6147
6148         if (err) {
6149                 niu_disable_napi(np);
6150                 goto out_free_irq;
6151         }
6152
6153         netif_tx_start_all_queues(dev);
6154
6155         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6156                 netif_carrier_on(dev);
6157
6158         add_timer(&np->timer);
6159
6160         return 0;
6161
6162 out_free_irq:
6163         niu_free_irq(np);
6164
6165 out_free_channels:
6166         niu_free_channels(np);
6167
6168 out_err:
6169         return err;
6170 }
6171
6172 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6173 {
6174         cancel_work_sync(&np->reset_task);
6175
6176         niu_disable_napi(np);
6177         netif_tx_stop_all_queues(dev);
6178
6179         del_timer_sync(&np->timer);
6180
6181         spin_lock_irq(&np->lock);
6182
6183         niu_stop_hw(np);
6184
6185         spin_unlock_irq(&np->lock);
6186 }
6187
6188 static int niu_close(struct net_device *dev)
6189 {
6190         struct niu *np = netdev_priv(dev);
6191
6192         niu_full_shutdown(np, dev);
6193
6194         niu_free_irq(np);
6195
6196         niu_free_channels(np);
6197
6198         niu_handle_led(np, 0);
6199
6200         return 0;
6201 }
6202
6203 static void niu_sync_xmac_stats(struct niu *np)
6204 {
6205         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6206
6207         mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6208         mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6209
6210         mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6211         mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6212         mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6213         mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6214         mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6215         mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6216         mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6217         mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6218         mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6219         mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6220         mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6221         mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6222         mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6223         mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6224         mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6225         mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6226 }
6227
6228 static void niu_sync_bmac_stats(struct niu *np)
6229 {
6230         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6231
6232         mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6233         mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6234
6235         mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6236         mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6237         mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6238         mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6239 }
6240
6241 static void niu_sync_mac_stats(struct niu *np)
6242 {
6243         if (np->flags & NIU_FLAGS_XMAC)
6244                 niu_sync_xmac_stats(np);
6245         else
6246                 niu_sync_bmac_stats(np);
6247 }
6248
6249 static void niu_get_rx_stats(struct niu *np)
6250 {
6251         unsigned long pkts, dropped, errors, bytes;
6252         int i;
6253
6254         pkts = dropped = errors = bytes = 0;
6255         for (i = 0; i < np->num_rx_rings; i++) {
6256                 struct rx_ring_info *rp = &np->rx_rings[i];
6257
6258                 niu_sync_rx_discard_stats(np, rp, 0);
6259
6260                 pkts += rp->rx_packets;
6261                 bytes += rp->rx_bytes;
6262                 dropped += rp->rx_dropped;
6263                 errors += rp->rx_errors;
6264         }
6265         np->dev->stats.rx_packets = pkts;
6266         np->dev->stats.rx_bytes = bytes;
6267         np->dev->stats.rx_dropped = dropped;
6268         np->dev->stats.rx_errors = errors;
6269 }
6270
6271 static void niu_get_tx_stats(struct niu *np)
6272 {
6273         unsigned long pkts, errors, bytes;
6274         int i;
6275
6276         pkts = errors = bytes = 0;
6277         for (i = 0; i < np->num_tx_rings; i++) {
6278                 struct tx_ring_info *rp = &np->tx_rings[i];
6279
6280                 pkts += rp->tx_packets;
6281                 bytes += rp->tx_bytes;
6282                 errors += rp->tx_errors;
6283         }
6284         np->dev->stats.tx_packets = pkts;
6285         np->dev->stats.tx_bytes = bytes;
6286         np->dev->stats.tx_errors = errors;
6287 }
6288
6289 static struct net_device_stats *niu_get_stats(struct net_device *dev)
6290 {
6291         struct niu *np = netdev_priv(dev);
6292
6293         niu_get_rx_stats(np);
6294         niu_get_tx_stats(np);
6295
6296         return &dev->stats;
6297 }
6298
6299 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6300 {
6301         int i;
6302
6303         for (i = 0; i < 16; i++)
6304                 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6305 }
6306
6307 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6308 {
6309         int i;
6310
6311         for (i = 0; i < 16; i++)
6312                 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6313 }
6314
6315 static void niu_load_hash(struct niu *np, u16 *hash)
6316 {
6317         if (np->flags & NIU_FLAGS_XMAC)
6318                 niu_load_hash_xmac(np, hash);
6319         else
6320                 niu_load_hash_bmac(np, hash);
6321 }
6322
6323 static void niu_set_rx_mode(struct net_device *dev)
6324 {
6325         struct niu *np = netdev_priv(dev);
6326         int i, alt_cnt, err;
6327         struct netdev_hw_addr *ha;
6328         unsigned long flags;
6329         u16 hash[16] = { 0, };
6330
6331         spin_lock_irqsave(&np->lock, flags);
6332         niu_enable_rx_mac(np, 0);
6333
6334         np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6335         if (dev->flags & IFF_PROMISC)
6336                 np->flags |= NIU_FLAGS_PROMISC;
6337         if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
6338                 np->flags |= NIU_FLAGS_MCAST;
6339
6340         alt_cnt = netdev_uc_count(dev);
6341         if (alt_cnt > niu_num_alt_addr(np)) {
6342                 alt_cnt = 0;
6343                 np->flags |= NIU_FLAGS_PROMISC;
6344         }
6345
6346         if (alt_cnt) {
6347                 int index = 0;
6348
6349                 netdev_for_each_uc_addr(ha, dev) {
6350                         err = niu_set_alt_mac(np, index, ha->addr);
6351                         if (err)
6352                                 netdev_warn(dev, "Error %d adding alt mac %d\n",
6353                                             err, index);
6354                         err = niu_enable_alt_mac(np, index, 1);
6355                         if (err)
6356                                 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6357                                             err, index);
6358
6359                         index++;
6360                 }
6361         } else {
6362                 int alt_start;
6363                 if (np->flags & NIU_FLAGS_XMAC)
6364                         alt_start = 0;
6365                 else
6366                         alt_start = 1;
6367                 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6368                         err = niu_enable_alt_mac(np, i, 0);
6369                         if (err)
6370                                 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6371                                             err, i);
6372                 }
6373         }
6374         if (dev->flags & IFF_ALLMULTI) {
6375                 for (i = 0; i < 16; i++)
6376                         hash[i] = 0xffff;
6377         } else if (!netdev_mc_empty(dev)) {
6378                 netdev_for_each_mc_addr(ha, dev) {
6379                         u32 crc = ether_crc_le(ETH_ALEN, ha->addr);
6380
6381