niu: Add support for C10NEM
[linux-2.6.git] / drivers / net / niu.c
1 /* niu.c: Neptune ethernet driver.
2  *
3  * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
4  */
5
6 #include <linux/module.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/netdevice.h>
11 #include <linux/ethtool.h>
12 #include <linux/etherdevice.h>
13 #include <linux/platform_device.h>
14 #include <linux/delay.h>
15 #include <linux/bitops.h>
16 #include <linux/mii.h>
17 #include <linux/if_ether.h>
18 #include <linux/if_vlan.h>
19 #include <linux/ip.h>
20 #include <linux/in.h>
21 #include <linux/ipv6.h>
22 #include <linux/log2.h>
23 #include <linux/jiffies.h>
24 #include <linux/crc32.h>
25
26 #include <linux/io.h>
27
28 #ifdef CONFIG_SPARC64
29 #include <linux/of_device.h>
30 #endif
31
32 #include "niu.h"
33
34 #define DRV_MODULE_NAME         "niu"
35 #define PFX DRV_MODULE_NAME     ": "
36 #define DRV_MODULE_VERSION      "1.0"
37 #define DRV_MODULE_RELDATE      "Nov 14, 2008"
38
39 static char version[] __devinitdata =
40         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
41
42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43 MODULE_DESCRIPTION("NIU ethernet driver");
44 MODULE_LICENSE("GPL");
45 MODULE_VERSION(DRV_MODULE_VERSION);
46
47 #ifndef DMA_44BIT_MASK
48 #define DMA_44BIT_MASK  0x00000fffffffffffULL
49 #endif
50
51 #ifndef readq
52 static u64 readq(void __iomem *reg)
53 {
54         return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
55 }
56
57 static void writeq(u64 val, void __iomem *reg)
58 {
59         writel(val & 0xffffffff, reg);
60         writel(val >> 32, reg + 0x4UL);
61 }
62 #endif
63
64 static struct pci_device_id niu_pci_tbl[] = {
65         {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
66         {}
67 };
68
69 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
70
71 #define NIU_TX_TIMEOUT                  (5 * HZ)
72
73 #define nr64(reg)               readq(np->regs + (reg))
74 #define nw64(reg, val)          writeq((val), np->regs + (reg))
75
76 #define nr64_mac(reg)           readq(np->mac_regs + (reg))
77 #define nw64_mac(reg, val)      writeq((val), np->mac_regs + (reg))
78
79 #define nr64_ipp(reg)           readq(np->regs + np->ipp_off + (reg))
80 #define nw64_ipp(reg, val)      writeq((val), np->regs + np->ipp_off + (reg))
81
82 #define nr64_pcs(reg)           readq(np->regs + np->pcs_off + (reg))
83 #define nw64_pcs(reg, val)      writeq((val), np->regs + np->pcs_off + (reg))
84
85 #define nr64_xpcs(reg)          readq(np->regs + np->xpcs_off + (reg))
86 #define nw64_xpcs(reg, val)     writeq((val), np->regs + np->xpcs_off + (reg))
87
88 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
89
90 static int niu_debug;
91 static int debug = -1;
92 module_param(debug, int, 0);
93 MODULE_PARM_DESC(debug, "NIU debug level");
94
95 #define niudbg(TYPE, f, a...) \
96 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
97                 printk(KERN_DEBUG PFX f, ## a); \
98 } while (0)
99
100 #define niuinfo(TYPE, f, a...) \
101 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
102                 printk(KERN_INFO PFX f, ## a); \
103 } while (0)
104
105 #define niuwarn(TYPE, f, a...) \
106 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
107                 printk(KERN_WARNING PFX f, ## a); \
108 } while (0)
109
110 #define niu_lock_parent(np, flags) \
111         spin_lock_irqsave(&np->parent->lock, flags)
112 #define niu_unlock_parent(np, flags) \
113         spin_unlock_irqrestore(&np->parent->lock, flags)
114
115 static int serdes_init_10g_serdes(struct niu *np);
116
117 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
118                                      u64 bits, int limit, int delay)
119 {
120         while (--limit >= 0) {
121                 u64 val = nr64_mac(reg);
122
123                 if (!(val & bits))
124                         break;
125                 udelay(delay);
126         }
127         if (limit < 0)
128                 return -ENODEV;
129         return 0;
130 }
131
132 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
133                                         u64 bits, int limit, int delay,
134                                         const char *reg_name)
135 {
136         int err;
137
138         nw64_mac(reg, bits);
139         err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
140         if (err)
141                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
142                         "would not clear, val[%llx]\n",
143                         np->dev->name, (unsigned long long) bits, reg_name,
144                         (unsigned long long) nr64_mac(reg));
145         return err;
146 }
147
148 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
149 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
150         __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
151 })
152
153 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
154                                      u64 bits, int limit, int delay)
155 {
156         while (--limit >= 0) {
157                 u64 val = nr64_ipp(reg);
158
159                 if (!(val & bits))
160                         break;
161                 udelay(delay);
162         }
163         if (limit < 0)
164                 return -ENODEV;
165         return 0;
166 }
167
168 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
169                                         u64 bits, int limit, int delay,
170                                         const char *reg_name)
171 {
172         int err;
173         u64 val;
174
175         val = nr64_ipp(reg);
176         val |= bits;
177         nw64_ipp(reg, val);
178
179         err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
180         if (err)
181                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
182                         "would not clear, val[%llx]\n",
183                         np->dev->name, (unsigned long long) bits, reg_name,
184                         (unsigned long long) nr64_ipp(reg));
185         return err;
186 }
187
188 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
189 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
190         __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
191 })
192
193 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
194                                  u64 bits, int limit, int delay)
195 {
196         while (--limit >= 0) {
197                 u64 val = nr64(reg);
198
199                 if (!(val & bits))
200                         break;
201                 udelay(delay);
202         }
203         if (limit < 0)
204                 return -ENODEV;
205         return 0;
206 }
207
208 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
209 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
210         __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
211 })
212
213 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
214                                     u64 bits, int limit, int delay,
215                                     const char *reg_name)
216 {
217         int err;
218
219         nw64(reg, bits);
220         err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
221         if (err)
222                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
223                         "would not clear, val[%llx]\n",
224                         np->dev->name, (unsigned long long) bits, reg_name,
225                         (unsigned long long) nr64(reg));
226         return err;
227 }
228
229 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
230 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
231         __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
232 })
233
234 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
235 {
236         u64 val = (u64) lp->timer;
237
238         if (on)
239                 val |= LDG_IMGMT_ARM;
240
241         nw64(LDG_IMGMT(lp->ldg_num), val);
242 }
243
244 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
245 {
246         unsigned long mask_reg, bits;
247         u64 val;
248
249         if (ldn < 0 || ldn > LDN_MAX)
250                 return -EINVAL;
251
252         if (ldn < 64) {
253                 mask_reg = LD_IM0(ldn);
254                 bits = LD_IM0_MASK;
255         } else {
256                 mask_reg = LD_IM1(ldn - 64);
257                 bits = LD_IM1_MASK;
258         }
259
260         val = nr64(mask_reg);
261         if (on)
262                 val &= ~bits;
263         else
264                 val |= bits;
265         nw64(mask_reg, val);
266
267         return 0;
268 }
269
270 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
271 {
272         struct niu_parent *parent = np->parent;
273         int i;
274
275         for (i = 0; i <= LDN_MAX; i++) {
276                 int err;
277
278                 if (parent->ldg_map[i] != lp->ldg_num)
279                         continue;
280
281                 err = niu_ldn_irq_enable(np, i, on);
282                 if (err)
283                         return err;
284         }
285         return 0;
286 }
287
288 static int niu_enable_interrupts(struct niu *np, int on)
289 {
290         int i;
291
292         for (i = 0; i < np->num_ldg; i++) {
293                 struct niu_ldg *lp = &np->ldg[i];
294                 int err;
295
296                 err = niu_enable_ldn_in_ldg(np, lp, on);
297                 if (err)
298                         return err;
299         }
300         for (i = 0; i < np->num_ldg; i++)
301                 niu_ldg_rearm(np, &np->ldg[i], on);
302
303         return 0;
304 }
305
306 static u32 phy_encode(u32 type, int port)
307 {
308         return (type << (port * 2));
309 }
310
311 static u32 phy_decode(u32 val, int port)
312 {
313         return (val >> (port * 2)) & PORT_TYPE_MASK;
314 }
315
316 static int mdio_wait(struct niu *np)
317 {
318         int limit = 1000;
319         u64 val;
320
321         while (--limit > 0) {
322                 val = nr64(MIF_FRAME_OUTPUT);
323                 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
324                         return val & MIF_FRAME_OUTPUT_DATA;
325
326                 udelay(10);
327         }
328
329         return -ENODEV;
330 }
331
332 static int mdio_read(struct niu *np, int port, int dev, int reg)
333 {
334         int err;
335
336         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
337         err = mdio_wait(np);
338         if (err < 0)
339                 return err;
340
341         nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
342         return mdio_wait(np);
343 }
344
345 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
346 {
347         int err;
348
349         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
350         err = mdio_wait(np);
351         if (err < 0)
352                 return err;
353
354         nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
355         err = mdio_wait(np);
356         if (err < 0)
357                 return err;
358
359         return 0;
360 }
361
362 static int mii_read(struct niu *np, int port, int reg)
363 {
364         nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
365         return mdio_wait(np);
366 }
367
368 static int mii_write(struct niu *np, int port, int reg, int data)
369 {
370         int err;
371
372         nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
373         err = mdio_wait(np);
374         if (err < 0)
375                 return err;
376
377         return 0;
378 }
379
380 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
381 {
382         int err;
383
384         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
385                          ESR2_TI_PLL_TX_CFG_L(channel),
386                          val & 0xffff);
387         if (!err)
388                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
389                                  ESR2_TI_PLL_TX_CFG_H(channel),
390                                  val >> 16);
391         return err;
392 }
393
394 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
395 {
396         int err;
397
398         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
399                          ESR2_TI_PLL_RX_CFG_L(channel),
400                          val & 0xffff);
401         if (!err)
402                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
403                                  ESR2_TI_PLL_RX_CFG_H(channel),
404                                  val >> 16);
405         return err;
406 }
407
408 /* Mode is always 10G fiber.  */
409 static int serdes_init_niu_10g_fiber(struct niu *np)
410 {
411         struct niu_link_config *lp = &np->link_config;
412         u32 tx_cfg, rx_cfg;
413         unsigned long i;
414
415         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
416         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
417                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
418                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
419
420         if (lp->loopback_mode == LOOPBACK_PHY) {
421                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
422
423                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
424                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
425
426                 tx_cfg |= PLL_TX_CFG_ENTEST;
427                 rx_cfg |= PLL_RX_CFG_ENTEST;
428         }
429
430         /* Initialize all 4 lanes of the SERDES.  */
431         for (i = 0; i < 4; i++) {
432                 int err = esr2_set_tx_cfg(np, i, tx_cfg);
433                 if (err)
434                         return err;
435         }
436
437         for (i = 0; i < 4; i++) {
438                 int err = esr2_set_rx_cfg(np, i, rx_cfg);
439                 if (err)
440                         return err;
441         }
442
443         return 0;
444 }
445
446 static int serdes_init_niu_1g_serdes(struct niu *np)
447 {
448         struct niu_link_config *lp = &np->link_config;
449         u16 pll_cfg, pll_sts;
450         int max_retry = 100;
451         u64 uninitialized_var(sig), mask, val;
452         u32 tx_cfg, rx_cfg;
453         unsigned long i;
454         int err;
455
456         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
457                   PLL_TX_CFG_RATE_HALF);
458         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
459                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
460                   PLL_RX_CFG_RATE_HALF);
461
462         if (np->port == 0)
463                 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
464
465         if (lp->loopback_mode == LOOPBACK_PHY) {
466                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
467
468                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
469                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
470
471                 tx_cfg |= PLL_TX_CFG_ENTEST;
472                 rx_cfg |= PLL_RX_CFG_ENTEST;
473         }
474
475         /* Initialize PLL for 1G */
476         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
477
478         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
479                          ESR2_TI_PLL_CFG_L, pll_cfg);
480         if (err) {
481                 dev_err(np->device, PFX "NIU Port %d "
482                         "serdes_init_niu_1g_serdes: "
483                         "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
484                 return err;
485         }
486
487         pll_sts = PLL_CFG_ENPLL;
488
489         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
490                          ESR2_TI_PLL_STS_L, pll_sts);
491         if (err) {
492                 dev_err(np->device, PFX "NIU Port %d "
493                         "serdes_init_niu_1g_serdes: "
494                         "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
495                 return err;
496         }
497
498         udelay(200);
499
500         /* Initialize all 4 lanes of the SERDES.  */
501         for (i = 0; i < 4; i++) {
502                 err = esr2_set_tx_cfg(np, i, tx_cfg);
503                 if (err)
504                         return err;
505         }
506
507         for (i = 0; i < 4; i++) {
508                 err = esr2_set_rx_cfg(np, i, rx_cfg);
509                 if (err)
510                         return err;
511         }
512
513         switch (np->port) {
514         case 0:
515                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
516                 mask = val;
517                 break;
518
519         case 1:
520                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
521                 mask = val;
522                 break;
523
524         default:
525                 return -EINVAL;
526         }
527
528         while (max_retry--) {
529                 sig = nr64(ESR_INT_SIGNALS);
530                 if ((sig & mask) == val)
531                         break;
532
533                 mdelay(500);
534         }
535
536         if ((sig & mask) != val) {
537                 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
538                         "[%08x]\n", np->port, (int) (sig & mask), (int) val);
539                 return -ENODEV;
540         }
541
542         return 0;
543 }
544
545 static int serdes_init_niu_10g_serdes(struct niu *np)
546 {
547         struct niu_link_config *lp = &np->link_config;
548         u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
549         int max_retry = 100;
550         u64 uninitialized_var(sig), mask, val;
551         unsigned long i;
552         int err;
553
554         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
555         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
556                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
557                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
558
559         if (lp->loopback_mode == LOOPBACK_PHY) {
560                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
561
562                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
563                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
564
565                 tx_cfg |= PLL_TX_CFG_ENTEST;
566                 rx_cfg |= PLL_RX_CFG_ENTEST;
567         }
568
569         /* Initialize PLL for 10G */
570         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
571
572         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
573                          ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
574         if (err) {
575                 dev_err(np->device, PFX "NIU Port %d "
576                         "serdes_init_niu_10g_serdes: "
577                         "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
578                 return err;
579         }
580
581         pll_sts = PLL_CFG_ENPLL;
582
583         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
584                          ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
585         if (err) {
586                 dev_err(np->device, PFX "NIU Port %d "
587                         "serdes_init_niu_10g_serdes: "
588                         "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
589                 return err;
590         }
591
592         udelay(200);
593
594         /* Initialize all 4 lanes of the SERDES.  */
595         for (i = 0; i < 4; i++) {
596                 err = esr2_set_tx_cfg(np, i, tx_cfg);
597                 if (err)
598                         return err;
599         }
600
601         for (i = 0; i < 4; i++) {
602                 err = esr2_set_rx_cfg(np, i, rx_cfg);
603                 if (err)
604                         return err;
605         }
606
607         /* check if serdes is ready */
608
609         switch (np->port) {
610         case 0:
611                 mask = ESR_INT_SIGNALS_P0_BITS;
612                 val = (ESR_INT_SRDY0_P0 |
613                        ESR_INT_DET0_P0 |
614                        ESR_INT_XSRDY_P0 |
615                        ESR_INT_XDP_P0_CH3 |
616                        ESR_INT_XDP_P0_CH2 |
617                        ESR_INT_XDP_P0_CH1 |
618                        ESR_INT_XDP_P0_CH0);
619                 break;
620
621         case 1:
622                 mask = ESR_INT_SIGNALS_P1_BITS;
623                 val = (ESR_INT_SRDY0_P1 |
624                        ESR_INT_DET0_P1 |
625                        ESR_INT_XSRDY_P1 |
626                        ESR_INT_XDP_P1_CH3 |
627                        ESR_INT_XDP_P1_CH2 |
628                        ESR_INT_XDP_P1_CH1 |
629                        ESR_INT_XDP_P1_CH0);
630                 break;
631
632         default:
633                 return -EINVAL;
634         }
635
636         while (max_retry--) {
637                 sig = nr64(ESR_INT_SIGNALS);
638                 if ((sig & mask) == val)
639                         break;
640
641                 mdelay(500);
642         }
643
644         if ((sig & mask) != val) {
645                 pr_info(PFX "NIU Port %u signal bits [%08x] are not "
646                         "[%08x] for 10G...trying 1G\n",
647                         np->port, (int) (sig & mask), (int) val);
648
649                 /* 10G failed, try initializing at 1G */
650                 err = serdes_init_niu_1g_serdes(np);
651                 if (!err) {
652                         np->flags &= ~NIU_FLAGS_10G;
653                         np->mac_xcvr = MAC_XCVR_PCS;
654                 }  else {
655                         dev_err(np->device, PFX "Port %u 10G/1G SERDES "
656                                 "Link Failed \n", np->port);
657                         return -ENODEV;
658                 }
659         }
660         return 0;
661 }
662
663 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
664 {
665         int err;
666
667         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
668         if (err >= 0) {
669                 *val = (err & 0xffff);
670                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
671                                 ESR_RXTX_CTRL_H(chan));
672                 if (err >= 0)
673                         *val |= ((err & 0xffff) << 16);
674                 err = 0;
675         }
676         return err;
677 }
678
679 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
680 {
681         int err;
682
683         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
684                         ESR_GLUE_CTRL0_L(chan));
685         if (err >= 0) {
686                 *val = (err & 0xffff);
687                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
688                                 ESR_GLUE_CTRL0_H(chan));
689                 if (err >= 0) {
690                         *val |= ((err & 0xffff) << 16);
691                         err = 0;
692                 }
693         }
694         return err;
695 }
696
697 static int esr_read_reset(struct niu *np, u32 *val)
698 {
699         int err;
700
701         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
702                         ESR_RXTX_RESET_CTRL_L);
703         if (err >= 0) {
704                 *val = (err & 0xffff);
705                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
706                                 ESR_RXTX_RESET_CTRL_H);
707                 if (err >= 0) {
708                         *val |= ((err & 0xffff) << 16);
709                         err = 0;
710                 }
711         }
712         return err;
713 }
714
715 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
716 {
717         int err;
718
719         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
720                          ESR_RXTX_CTRL_L(chan), val & 0xffff);
721         if (!err)
722                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
723                                  ESR_RXTX_CTRL_H(chan), (val >> 16));
724         return err;
725 }
726
727 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
728 {
729         int err;
730
731         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
732                         ESR_GLUE_CTRL0_L(chan), val & 0xffff);
733         if (!err)
734                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
735                                  ESR_GLUE_CTRL0_H(chan), (val >> 16));
736         return err;
737 }
738
739 static int esr_reset(struct niu *np)
740 {
741         u32 uninitialized_var(reset);
742         int err;
743
744         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
745                          ESR_RXTX_RESET_CTRL_L, 0x0000);
746         if (err)
747                 return err;
748         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
749                          ESR_RXTX_RESET_CTRL_H, 0xffff);
750         if (err)
751                 return err;
752         udelay(200);
753
754         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
755                          ESR_RXTX_RESET_CTRL_L, 0xffff);
756         if (err)
757                 return err;
758         udelay(200);
759
760         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
761                          ESR_RXTX_RESET_CTRL_H, 0x0000);
762         if (err)
763                 return err;
764         udelay(200);
765
766         err = esr_read_reset(np, &reset);
767         if (err)
768                 return err;
769         if (reset != 0) {
770                 dev_err(np->device, PFX "Port %u ESR_RESET "
771                         "did not clear [%08x]\n",
772                         np->port, reset);
773                 return -ENODEV;
774         }
775
776         return 0;
777 }
778
779 static int serdes_init_10g(struct niu *np)
780 {
781         struct niu_link_config *lp = &np->link_config;
782         unsigned long ctrl_reg, test_cfg_reg, i;
783         u64 ctrl_val, test_cfg_val, sig, mask, val;
784         int err;
785
786         switch (np->port) {
787         case 0:
788                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
789                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
790                 break;
791         case 1:
792                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
793                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
794                 break;
795
796         default:
797                 return -EINVAL;
798         }
799         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
800                     ENET_SERDES_CTRL_SDET_1 |
801                     ENET_SERDES_CTRL_SDET_2 |
802                     ENET_SERDES_CTRL_SDET_3 |
803                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
804                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
805                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
806                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
807                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
808                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
809                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
810                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
811         test_cfg_val = 0;
812
813         if (lp->loopback_mode == LOOPBACK_PHY) {
814                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
815                                   ENET_SERDES_TEST_MD_0_SHIFT) |
816                                  (ENET_TEST_MD_PAD_LOOPBACK <<
817                                   ENET_SERDES_TEST_MD_1_SHIFT) |
818                                  (ENET_TEST_MD_PAD_LOOPBACK <<
819                                   ENET_SERDES_TEST_MD_2_SHIFT) |
820                                  (ENET_TEST_MD_PAD_LOOPBACK <<
821                                   ENET_SERDES_TEST_MD_3_SHIFT));
822         }
823
824         nw64(ctrl_reg, ctrl_val);
825         nw64(test_cfg_reg, test_cfg_val);
826
827         /* Initialize all 4 lanes of the SERDES.  */
828         for (i = 0; i < 4; i++) {
829                 u32 rxtx_ctrl, glue0;
830
831                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
832                 if (err)
833                         return err;
834                 err = esr_read_glue0(np, i, &glue0);
835                 if (err)
836                         return err;
837
838                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
839                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
840                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
841
842                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
843                            ESR_GLUE_CTRL0_THCNT |
844                            ESR_GLUE_CTRL0_BLTIME);
845                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
846                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
847                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
848                           (BLTIME_300_CYCLES <<
849                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
850
851                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
852                 if (err)
853                         return err;
854                 err = esr_write_glue0(np, i, glue0);
855                 if (err)
856                         return err;
857         }
858
859         err = esr_reset(np);
860         if (err)
861                 return err;
862
863         sig = nr64(ESR_INT_SIGNALS);
864         switch (np->port) {
865         case 0:
866                 mask = ESR_INT_SIGNALS_P0_BITS;
867                 val = (ESR_INT_SRDY0_P0 |
868                        ESR_INT_DET0_P0 |
869                        ESR_INT_XSRDY_P0 |
870                        ESR_INT_XDP_P0_CH3 |
871                        ESR_INT_XDP_P0_CH2 |
872                        ESR_INT_XDP_P0_CH1 |
873                        ESR_INT_XDP_P0_CH0);
874                 break;
875
876         case 1:
877                 mask = ESR_INT_SIGNALS_P1_BITS;
878                 val = (ESR_INT_SRDY0_P1 |
879                        ESR_INT_DET0_P1 |
880                        ESR_INT_XSRDY_P1 |
881                        ESR_INT_XDP_P1_CH3 |
882                        ESR_INT_XDP_P1_CH2 |
883                        ESR_INT_XDP_P1_CH1 |
884                        ESR_INT_XDP_P1_CH0);
885                 break;
886
887         default:
888                 return -EINVAL;
889         }
890
891         if ((sig & mask) != val) {
892                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
893                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
894                         return 0;
895                 }
896                 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
897                         "[%08x]\n", np->port, (int) (sig & mask), (int) val);
898                 return -ENODEV;
899         }
900         if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
901                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
902         return 0;
903 }
904
905 static int serdes_init_1g(struct niu *np)
906 {
907         u64 val;
908
909         val = nr64(ENET_SERDES_1_PLL_CFG);
910         val &= ~ENET_SERDES_PLL_FBDIV2;
911         switch (np->port) {
912         case 0:
913                 val |= ENET_SERDES_PLL_HRATE0;
914                 break;
915         case 1:
916                 val |= ENET_SERDES_PLL_HRATE1;
917                 break;
918         case 2:
919                 val |= ENET_SERDES_PLL_HRATE2;
920                 break;
921         case 3:
922                 val |= ENET_SERDES_PLL_HRATE3;
923                 break;
924         default:
925                 return -EINVAL;
926         }
927         nw64(ENET_SERDES_1_PLL_CFG, val);
928
929         return 0;
930 }
931
932 static int serdes_init_1g_serdes(struct niu *np)
933 {
934         struct niu_link_config *lp = &np->link_config;
935         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
936         u64 ctrl_val, test_cfg_val, sig, mask, val;
937         int err;
938         u64 reset_val, val_rd;
939
940         val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
941                 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
942                 ENET_SERDES_PLL_FBDIV0;
943         switch (np->port) {
944         case 0:
945                 reset_val =  ENET_SERDES_RESET_0;
946                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
947                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
948                 pll_cfg = ENET_SERDES_0_PLL_CFG;
949                 break;
950         case 1:
951                 reset_val =  ENET_SERDES_RESET_1;
952                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
953                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
954                 pll_cfg = ENET_SERDES_1_PLL_CFG;
955                 break;
956
957         default:
958                 return -EINVAL;
959         }
960         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
961                     ENET_SERDES_CTRL_SDET_1 |
962                     ENET_SERDES_CTRL_SDET_2 |
963                     ENET_SERDES_CTRL_SDET_3 |
964                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
965                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
966                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
967                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
968                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
969                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
970                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
971                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
972         test_cfg_val = 0;
973
974         if (lp->loopback_mode == LOOPBACK_PHY) {
975                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
976                                   ENET_SERDES_TEST_MD_0_SHIFT) |
977                                  (ENET_TEST_MD_PAD_LOOPBACK <<
978                                   ENET_SERDES_TEST_MD_1_SHIFT) |
979                                  (ENET_TEST_MD_PAD_LOOPBACK <<
980                                   ENET_SERDES_TEST_MD_2_SHIFT) |
981                                  (ENET_TEST_MD_PAD_LOOPBACK <<
982                                   ENET_SERDES_TEST_MD_3_SHIFT));
983         }
984
985         nw64(ENET_SERDES_RESET, reset_val);
986         mdelay(20);
987         val_rd = nr64(ENET_SERDES_RESET);
988         val_rd &= ~reset_val;
989         nw64(pll_cfg, val);
990         nw64(ctrl_reg, ctrl_val);
991         nw64(test_cfg_reg, test_cfg_val);
992         nw64(ENET_SERDES_RESET, val_rd);
993         mdelay(2000);
994
995         /* Initialize all 4 lanes of the SERDES.  */
996         for (i = 0; i < 4; i++) {
997                 u32 rxtx_ctrl, glue0;
998
999                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
1000                 if (err)
1001                         return err;
1002                 err = esr_read_glue0(np, i, &glue0);
1003                 if (err)
1004                         return err;
1005
1006                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
1007                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
1008                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
1009
1010                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
1011                            ESR_GLUE_CTRL0_THCNT |
1012                            ESR_GLUE_CTRL0_BLTIME);
1013                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
1014                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
1015                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
1016                           (BLTIME_300_CYCLES <<
1017                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
1018
1019                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
1020                 if (err)
1021                         return err;
1022                 err = esr_write_glue0(np, i, glue0);
1023                 if (err)
1024                         return err;
1025         }
1026
1027
1028         sig = nr64(ESR_INT_SIGNALS);
1029         switch (np->port) {
1030         case 0:
1031                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1032                 mask = val;
1033                 break;
1034
1035         case 1:
1036                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1037                 mask = val;
1038                 break;
1039
1040         default:
1041                 return -EINVAL;
1042         }
1043
1044         if ((sig & mask) != val) {
1045                 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
1046                         "[%08x]\n", np->port, (int) (sig & mask), (int) val);
1047                 return -ENODEV;
1048         }
1049
1050         return 0;
1051 }
1052
1053 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1054 {
1055         struct niu_link_config *lp = &np->link_config;
1056         int link_up;
1057         u64 val;
1058         u16 current_speed;
1059         unsigned long flags;
1060         u8 current_duplex;
1061
1062         link_up = 0;
1063         current_speed = SPEED_INVALID;
1064         current_duplex = DUPLEX_INVALID;
1065
1066         spin_lock_irqsave(&np->lock, flags);
1067
1068         val = nr64_pcs(PCS_MII_STAT);
1069
1070         if (val & PCS_MII_STAT_LINK_STATUS) {
1071                 link_up = 1;
1072                 current_speed = SPEED_1000;
1073                 current_duplex = DUPLEX_FULL;
1074         }
1075
1076         lp->active_speed = current_speed;
1077         lp->active_duplex = current_duplex;
1078         spin_unlock_irqrestore(&np->lock, flags);
1079
1080         *link_up_p = link_up;
1081         return 0;
1082 }
1083
1084 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1085 {
1086         unsigned long flags;
1087         struct niu_link_config *lp = &np->link_config;
1088         int link_up = 0;
1089         int link_ok = 1;
1090         u64 val, val2;
1091         u16 current_speed;
1092         u8 current_duplex;
1093
1094         if (!(np->flags & NIU_FLAGS_10G))
1095                 return link_status_1g_serdes(np, link_up_p);
1096
1097         current_speed = SPEED_INVALID;
1098         current_duplex = DUPLEX_INVALID;
1099         spin_lock_irqsave(&np->lock, flags);
1100
1101         val = nr64_xpcs(XPCS_STATUS(0));
1102         val2 = nr64_mac(XMAC_INTER2);
1103         if (val2 & 0x01000000)
1104                 link_ok = 0;
1105
1106         if ((val & 0x1000ULL) && link_ok) {
1107                 link_up = 1;
1108                 current_speed = SPEED_10000;
1109                 current_duplex = DUPLEX_FULL;
1110         }
1111         lp->active_speed = current_speed;
1112         lp->active_duplex = current_duplex;
1113         spin_unlock_irqrestore(&np->lock, flags);
1114         *link_up_p = link_up;
1115         return 0;
1116 }
1117
1118 static int link_status_mii(struct niu *np, int *link_up_p)
1119 {
1120         struct niu_link_config *lp = &np->link_config;
1121         int err;
1122         int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1123         int supported, advertising, active_speed, active_duplex;
1124
1125         err = mii_read(np, np->phy_addr, MII_BMCR);
1126         if (unlikely(err < 0))
1127                 return err;
1128         bmcr = err;
1129
1130         err = mii_read(np, np->phy_addr, MII_BMSR);
1131         if (unlikely(err < 0))
1132                 return err;
1133         bmsr = err;
1134
1135         err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1136         if (unlikely(err < 0))
1137                 return err;
1138         advert = err;
1139
1140         err = mii_read(np, np->phy_addr, MII_LPA);
1141         if (unlikely(err < 0))
1142                 return err;
1143         lpa = err;
1144
1145         if (likely(bmsr & BMSR_ESTATEN)) {
1146                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1147                 if (unlikely(err < 0))
1148                         return err;
1149                 estatus = err;
1150
1151                 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1152                 if (unlikely(err < 0))
1153                         return err;
1154                 ctrl1000 = err;
1155
1156                 err = mii_read(np, np->phy_addr, MII_STAT1000);
1157                 if (unlikely(err < 0))
1158                         return err;
1159                 stat1000 = err;
1160         } else
1161                 estatus = ctrl1000 = stat1000 = 0;
1162
1163         supported = 0;
1164         if (bmsr & BMSR_ANEGCAPABLE)
1165                 supported |= SUPPORTED_Autoneg;
1166         if (bmsr & BMSR_10HALF)
1167                 supported |= SUPPORTED_10baseT_Half;
1168         if (bmsr & BMSR_10FULL)
1169                 supported |= SUPPORTED_10baseT_Full;
1170         if (bmsr & BMSR_100HALF)
1171                 supported |= SUPPORTED_100baseT_Half;
1172         if (bmsr & BMSR_100FULL)
1173                 supported |= SUPPORTED_100baseT_Full;
1174         if (estatus & ESTATUS_1000_THALF)
1175                 supported |= SUPPORTED_1000baseT_Half;
1176         if (estatus & ESTATUS_1000_TFULL)
1177                 supported |= SUPPORTED_1000baseT_Full;
1178         lp->supported = supported;
1179
1180         advertising = 0;
1181         if (advert & ADVERTISE_10HALF)
1182                 advertising |= ADVERTISED_10baseT_Half;
1183         if (advert & ADVERTISE_10FULL)
1184                 advertising |= ADVERTISED_10baseT_Full;
1185         if (advert & ADVERTISE_100HALF)
1186                 advertising |= ADVERTISED_100baseT_Half;
1187         if (advert & ADVERTISE_100FULL)
1188                 advertising |= ADVERTISED_100baseT_Full;
1189         if (ctrl1000 & ADVERTISE_1000HALF)
1190                 advertising |= ADVERTISED_1000baseT_Half;
1191         if (ctrl1000 & ADVERTISE_1000FULL)
1192                 advertising |= ADVERTISED_1000baseT_Full;
1193
1194         if (bmcr & BMCR_ANENABLE) {
1195                 int neg, neg1000;
1196
1197                 lp->active_autoneg = 1;
1198                 advertising |= ADVERTISED_Autoneg;
1199
1200                 neg = advert & lpa;
1201                 neg1000 = (ctrl1000 << 2) & stat1000;
1202
1203                 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1204                         active_speed = SPEED_1000;
1205                 else if (neg & LPA_100)
1206                         active_speed = SPEED_100;
1207                 else if (neg & (LPA_10HALF | LPA_10FULL))
1208                         active_speed = SPEED_10;
1209                 else
1210                         active_speed = SPEED_INVALID;
1211
1212                 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1213                         active_duplex = DUPLEX_FULL;
1214                 else if (active_speed != SPEED_INVALID)
1215                         active_duplex = DUPLEX_HALF;
1216                 else
1217                         active_duplex = DUPLEX_INVALID;
1218         } else {
1219                 lp->active_autoneg = 0;
1220
1221                 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1222                         active_speed = SPEED_1000;
1223                 else if (bmcr & BMCR_SPEED100)
1224                         active_speed = SPEED_100;
1225                 else
1226                         active_speed = SPEED_10;
1227
1228                 if (bmcr & BMCR_FULLDPLX)
1229                         active_duplex = DUPLEX_FULL;
1230                 else
1231                         active_duplex = DUPLEX_HALF;
1232         }
1233
1234         lp->active_advertising = advertising;
1235         lp->active_speed = active_speed;
1236         lp->active_duplex = active_duplex;
1237         *link_up_p = !!(bmsr & BMSR_LSTATUS);
1238
1239         return 0;
1240 }
1241
1242 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1243 {
1244         struct niu_link_config *lp = &np->link_config;
1245         u16 current_speed, bmsr;
1246         unsigned long flags;
1247         u8 current_duplex;
1248         int err, link_up;
1249
1250         link_up = 0;
1251         current_speed = SPEED_INVALID;
1252         current_duplex = DUPLEX_INVALID;
1253
1254         spin_lock_irqsave(&np->lock, flags);
1255
1256         err = -EINVAL;
1257
1258         err = mii_read(np, np->phy_addr, MII_BMSR);
1259         if (err < 0)
1260                 goto out;
1261
1262         bmsr = err;
1263         if (bmsr & BMSR_LSTATUS) {
1264                 u16 adv, lpa, common, estat;
1265
1266                 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1267                 if (err < 0)
1268                         goto out;
1269                 adv = err;
1270
1271                 err = mii_read(np, np->phy_addr, MII_LPA);
1272                 if (err < 0)
1273                         goto out;
1274                 lpa = err;
1275
1276                 common = adv & lpa;
1277
1278                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1279                 if (err < 0)
1280                         goto out;
1281                 estat = err;
1282                 link_up = 1;
1283                 current_speed = SPEED_1000;
1284                 current_duplex = DUPLEX_FULL;
1285
1286         }
1287         lp->active_speed = current_speed;
1288         lp->active_duplex = current_duplex;
1289         err = 0;
1290
1291 out:
1292         spin_unlock_irqrestore(&np->lock, flags);
1293
1294         *link_up_p = link_up;
1295         return err;
1296 }
1297
1298 static int link_status_1g(struct niu *np, int *link_up_p)
1299 {
1300         struct niu_link_config *lp = &np->link_config;
1301         unsigned long flags;
1302         int err;
1303
1304         spin_lock_irqsave(&np->lock, flags);
1305
1306         err = link_status_mii(np, link_up_p);
1307         lp->supported |= SUPPORTED_TP;
1308         lp->active_advertising |= ADVERTISED_TP;
1309
1310         spin_unlock_irqrestore(&np->lock, flags);
1311         return err;
1312 }
1313
1314 static int bcm8704_reset(struct niu *np)
1315 {
1316         int err, limit;
1317
1318         err = mdio_read(np, np->phy_addr,
1319                         BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1320         if (err < 0 || err == 0xffff)
1321                 return err;
1322         err |= BMCR_RESET;
1323         err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1324                          MII_BMCR, err);
1325         if (err)
1326                 return err;
1327
1328         limit = 1000;
1329         while (--limit >= 0) {
1330                 err = mdio_read(np, np->phy_addr,
1331                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1332                 if (err < 0)
1333                         return err;
1334                 if (!(err & BMCR_RESET))
1335                         break;
1336         }
1337         if (limit < 0) {
1338                 dev_err(np->device, PFX "Port %u PHY will not reset "
1339                         "(bmcr=%04x)\n", np->port, (err & 0xffff));
1340                 return -ENODEV;
1341         }
1342         return 0;
1343 }
1344
1345 /* When written, certain PHY registers need to be read back twice
1346  * in order for the bits to settle properly.
1347  */
1348 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1349 {
1350         int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1351         if (err < 0)
1352                 return err;
1353         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1354         if (err < 0)
1355                 return err;
1356         return 0;
1357 }
1358
1359 static int bcm8706_init_user_dev3(struct niu *np)
1360 {
1361         int err;
1362
1363
1364         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1365                         BCM8704_USER_OPT_DIGITAL_CTRL);
1366         if (err < 0)
1367                 return err;
1368         err &= ~USER_ODIG_CTRL_GPIOS;
1369         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1370         err |=  USER_ODIG_CTRL_RESV2;
1371         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1372                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1373         if (err)
1374                 return err;
1375
1376         mdelay(1000);
1377
1378         return 0;
1379 }
1380
1381 static int bcm8704_init_user_dev3(struct niu *np)
1382 {
1383         int err;
1384
1385         err = mdio_write(np, np->phy_addr,
1386                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1387                          (USER_CONTROL_OPTXRST_LVL |
1388                           USER_CONTROL_OPBIASFLT_LVL |
1389                           USER_CONTROL_OBTMPFLT_LVL |
1390                           USER_CONTROL_OPPRFLT_LVL |
1391                           USER_CONTROL_OPTXFLT_LVL |
1392                           USER_CONTROL_OPRXLOS_LVL |
1393                           USER_CONTROL_OPRXFLT_LVL |
1394                           USER_CONTROL_OPTXON_LVL |
1395                           (0x3f << USER_CONTROL_RES1_SHIFT)));
1396         if (err)
1397                 return err;
1398
1399         err = mdio_write(np, np->phy_addr,
1400                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1401                          (USER_PMD_TX_CTL_XFP_CLKEN |
1402                           (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1403                           (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1404                           USER_PMD_TX_CTL_TSCK_LPWREN));
1405         if (err)
1406                 return err;
1407
1408         err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1409         if (err)
1410                 return err;
1411         err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1412         if (err)
1413                 return err;
1414
1415         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1416                         BCM8704_USER_OPT_DIGITAL_CTRL);
1417         if (err < 0)
1418                 return err;
1419         err &= ~USER_ODIG_CTRL_GPIOS;
1420         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1421         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1422                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1423         if (err)
1424                 return err;
1425
1426         mdelay(1000);
1427
1428         return 0;
1429 }
1430
1431 static int mrvl88x2011_act_led(struct niu *np, int val)
1432 {
1433         int     err;
1434
1435         err  = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1436                 MRVL88X2011_LED_8_TO_11_CTL);
1437         if (err < 0)
1438                 return err;
1439
1440         err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1441         err |=  MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1442
1443         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1444                           MRVL88X2011_LED_8_TO_11_CTL, err);
1445 }
1446
1447 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1448 {
1449         int     err;
1450
1451         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1452                         MRVL88X2011_LED_BLINK_CTL);
1453         if (err >= 0) {
1454                 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1455                 err |= (rate << 4);
1456
1457                 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1458                                  MRVL88X2011_LED_BLINK_CTL, err);
1459         }
1460
1461         return err;
1462 }
1463
1464 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1465 {
1466         int     err;
1467
1468         /* Set LED functions */
1469         err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1470         if (err)
1471                 return err;
1472
1473         /* led activity */
1474         err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1475         if (err)
1476                 return err;
1477
1478         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1479                         MRVL88X2011_GENERAL_CTL);
1480         if (err < 0)
1481                 return err;
1482
1483         err |= MRVL88X2011_ENA_XFPREFCLK;
1484
1485         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1486                          MRVL88X2011_GENERAL_CTL, err);
1487         if (err < 0)
1488                 return err;
1489
1490         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1491                         MRVL88X2011_PMA_PMD_CTL_1);
1492         if (err < 0)
1493                 return err;
1494
1495         if (np->link_config.loopback_mode == LOOPBACK_MAC)
1496                 err |= MRVL88X2011_LOOPBACK;
1497         else
1498                 err &= ~MRVL88X2011_LOOPBACK;
1499
1500         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1501                          MRVL88X2011_PMA_PMD_CTL_1, err);
1502         if (err < 0)
1503                 return err;
1504
1505         /* Enable PMD  */
1506         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1507                           MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1508 }
1509
1510
1511 static int xcvr_diag_bcm870x(struct niu *np)
1512 {
1513         u16 analog_stat0, tx_alarm_status;
1514         int err = 0;
1515
1516 #if 1
1517         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1518                         MII_STAT1000);
1519         if (err < 0)
1520                 return err;
1521         pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
1522                 np->port, err);
1523
1524         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1525         if (err < 0)
1526                 return err;
1527         pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n",
1528                 np->port, err);
1529
1530         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1531                         MII_NWAYTEST);
1532         if (err < 0)
1533                 return err;
1534         pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
1535                 np->port, err);
1536 #endif
1537
1538         /* XXX dig this out it might not be so useful XXX */
1539         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1540                         BCM8704_USER_ANALOG_STATUS0);
1541         if (err < 0)
1542                 return err;
1543         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1544                         BCM8704_USER_ANALOG_STATUS0);
1545         if (err < 0)
1546                 return err;
1547         analog_stat0 = err;
1548
1549         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1550                         BCM8704_USER_TX_ALARM_STATUS);
1551         if (err < 0)
1552                 return err;
1553         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1554                         BCM8704_USER_TX_ALARM_STATUS);
1555         if (err < 0)
1556                 return err;
1557         tx_alarm_status = err;
1558
1559         if (analog_stat0 != 0x03fc) {
1560                 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1561                         pr_info(PFX "Port %u cable not connected "
1562                                 "or bad cable.\n", np->port);
1563                 } else if (analog_stat0 == 0x639c) {
1564                         pr_info(PFX "Port %u optical module is bad "
1565                                 "or missing.\n", np->port);
1566                 }
1567         }
1568
1569         return 0;
1570 }
1571
1572 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1573 {
1574         struct niu_link_config *lp = &np->link_config;
1575         int err;
1576
1577         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1578                         MII_BMCR);
1579         if (err < 0)
1580                 return err;
1581
1582         err &= ~BMCR_LOOPBACK;
1583
1584         if (lp->loopback_mode == LOOPBACK_MAC)
1585                 err |= BMCR_LOOPBACK;
1586
1587         err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1588                          MII_BMCR, err);
1589         if (err)
1590                 return err;
1591
1592         return 0;
1593 }
1594
1595 static int xcvr_init_10g_bcm8706(struct niu *np)
1596 {
1597         int err = 0;
1598         u64 val;
1599
1600         if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1601             (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1602                         return err;
1603
1604         val = nr64_mac(XMAC_CONFIG);
1605         val &= ~XMAC_CONFIG_LED_POLARITY;
1606         val |= XMAC_CONFIG_FORCE_LED_ON;
1607         nw64_mac(XMAC_CONFIG, val);
1608
1609         val = nr64(MIF_CONFIG);
1610         val |= MIF_CONFIG_INDIRECT_MODE;
1611         nw64(MIF_CONFIG, val);
1612
1613         err = bcm8704_reset(np);
1614         if (err)
1615                 return err;
1616
1617         err = xcvr_10g_set_lb_bcm870x(np);
1618         if (err)
1619                 return err;
1620
1621         err = bcm8706_init_user_dev3(np);
1622         if (err)
1623                 return err;
1624
1625         err = xcvr_diag_bcm870x(np);
1626         if (err)
1627                 return err;
1628
1629         return 0;
1630 }
1631
1632 static int xcvr_init_10g_bcm8704(struct niu *np)
1633 {
1634         int err;
1635
1636         err = bcm8704_reset(np);
1637         if (err)
1638                 return err;
1639
1640         err = bcm8704_init_user_dev3(np);
1641         if (err)
1642                 return err;
1643
1644         err = xcvr_10g_set_lb_bcm870x(np);
1645         if (err)
1646                 return err;
1647
1648         err =  xcvr_diag_bcm870x(np);
1649         if (err)
1650                 return err;
1651
1652         return 0;
1653 }
1654
1655 static int xcvr_init_10g(struct niu *np)
1656 {
1657         int phy_id, err;
1658         u64 val;
1659
1660         val = nr64_mac(XMAC_CONFIG);
1661         val &= ~XMAC_CONFIG_LED_POLARITY;
1662         val |= XMAC_CONFIG_FORCE_LED_ON;
1663         nw64_mac(XMAC_CONFIG, val);
1664
1665         /* XXX shared resource, lock parent XXX */
1666         val = nr64(MIF_CONFIG);
1667         val |= MIF_CONFIG_INDIRECT_MODE;
1668         nw64(MIF_CONFIG, val);
1669
1670         phy_id = phy_decode(np->parent->port_phy, np->port);
1671         phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1672
1673         /* handle different phy types */
1674         switch (phy_id & NIU_PHY_ID_MASK) {
1675         case NIU_PHY_ID_MRVL88X2011:
1676                 err = xcvr_init_10g_mrvl88x2011(np);
1677                 break;
1678
1679         default: /* bcom 8704 */
1680                 err = xcvr_init_10g_bcm8704(np);
1681                 break;
1682         }
1683
1684         return 0;
1685 }
1686
1687 static int mii_reset(struct niu *np)
1688 {
1689         int limit, err;
1690
1691         err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1692         if (err)
1693                 return err;
1694
1695         limit = 1000;
1696         while (--limit >= 0) {
1697                 udelay(500);
1698                 err = mii_read(np, np->phy_addr, MII_BMCR);
1699                 if (err < 0)
1700                         return err;
1701                 if (!(err & BMCR_RESET))
1702                         break;
1703         }
1704         if (limit < 0) {
1705                 dev_err(np->device, PFX "Port %u MII would not reset, "
1706                         "bmcr[%04x]\n", np->port, err);
1707                 return -ENODEV;
1708         }
1709
1710         return 0;
1711 }
1712
1713 static int xcvr_init_1g_rgmii(struct niu *np)
1714 {
1715         int err;
1716         u64 val;
1717         u16 bmcr, bmsr, estat;
1718
1719         val = nr64(MIF_CONFIG);
1720         val &= ~MIF_CONFIG_INDIRECT_MODE;
1721         nw64(MIF_CONFIG, val);
1722
1723         err = mii_reset(np);
1724         if (err)
1725                 return err;
1726
1727         err = mii_read(np, np->phy_addr, MII_BMSR);
1728         if (err < 0)
1729                 return err;
1730         bmsr = err;
1731
1732         estat = 0;
1733         if (bmsr & BMSR_ESTATEN) {
1734                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1735                 if (err < 0)
1736                         return err;
1737                 estat = err;
1738         }
1739
1740         bmcr = 0;
1741         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1742         if (err)
1743                 return err;
1744
1745         if (bmsr & BMSR_ESTATEN) {
1746                 u16 ctrl1000 = 0;
1747
1748                 if (estat & ESTATUS_1000_TFULL)
1749                         ctrl1000 |= ADVERTISE_1000FULL;
1750                 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1751                 if (err)
1752                         return err;
1753         }
1754
1755         bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1756
1757         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1758         if (err)
1759                 return err;
1760
1761         err = mii_read(np, np->phy_addr, MII_BMCR);
1762         if (err < 0)
1763                 return err;
1764         bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1765
1766         err = mii_read(np, np->phy_addr, MII_BMSR);
1767         if (err < 0)
1768                 return err;
1769
1770         return 0;
1771 }
1772
1773 static int mii_init_common(struct niu *np)
1774 {
1775         struct niu_link_config *lp = &np->link_config;
1776         u16 bmcr, bmsr, adv, estat;
1777         int err;
1778
1779         err = mii_reset(np);
1780         if (err)
1781                 return err;
1782
1783         err = mii_read(np, np->phy_addr, MII_BMSR);
1784         if (err < 0)
1785                 return err;
1786         bmsr = err;
1787
1788         estat = 0;
1789         if (bmsr & BMSR_ESTATEN) {
1790                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1791                 if (err < 0)
1792                         return err;
1793                 estat = err;
1794         }
1795
1796         bmcr = 0;
1797         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1798         if (err)
1799                 return err;
1800
1801         if (lp->loopback_mode == LOOPBACK_MAC) {
1802                 bmcr |= BMCR_LOOPBACK;
1803                 if (lp->active_speed == SPEED_1000)
1804                         bmcr |= BMCR_SPEED1000;
1805                 if (lp->active_duplex == DUPLEX_FULL)
1806                         bmcr |= BMCR_FULLDPLX;
1807         }
1808
1809         if (lp->loopback_mode == LOOPBACK_PHY) {
1810                 u16 aux;
1811
1812                 aux = (BCM5464R_AUX_CTL_EXT_LB |
1813                        BCM5464R_AUX_CTL_WRITE_1);
1814                 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1815                 if (err)
1816                         return err;
1817         }
1818
1819         if (lp->autoneg) {
1820                 u16 ctrl1000;
1821
1822                 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1823                 if ((bmsr & BMSR_10HALF) &&
1824                         (lp->advertising & ADVERTISED_10baseT_Half))
1825                         adv |= ADVERTISE_10HALF;
1826                 if ((bmsr & BMSR_10FULL) &&
1827                         (lp->advertising & ADVERTISED_10baseT_Full))
1828                         adv |= ADVERTISE_10FULL;
1829                 if ((bmsr & BMSR_100HALF) &&
1830                         (lp->advertising & ADVERTISED_100baseT_Half))
1831                         adv |= ADVERTISE_100HALF;
1832                 if ((bmsr & BMSR_100FULL) &&
1833                         (lp->advertising & ADVERTISED_100baseT_Full))
1834                         adv |= ADVERTISE_100FULL;
1835                 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1836                 if (err)
1837                         return err;
1838
1839                 if (likely(bmsr & BMSR_ESTATEN)) {
1840                         ctrl1000 = 0;
1841                         if ((estat & ESTATUS_1000_THALF) &&
1842                                 (lp->advertising & ADVERTISED_1000baseT_Half))
1843                                 ctrl1000 |= ADVERTISE_1000HALF;
1844                         if ((estat & ESTATUS_1000_TFULL) &&
1845                                 (lp->advertising & ADVERTISED_1000baseT_Full))
1846                                 ctrl1000 |= ADVERTISE_1000FULL;
1847                         err = mii_write(np, np->phy_addr,
1848                                         MII_CTRL1000, ctrl1000);
1849                         if (err)
1850                                 return err;
1851                 }
1852
1853                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1854         } else {
1855                 /* !lp->autoneg */
1856                 int fulldpx;
1857
1858                 if (lp->duplex == DUPLEX_FULL) {
1859                         bmcr |= BMCR_FULLDPLX;
1860                         fulldpx = 1;
1861                 } else if (lp->duplex == DUPLEX_HALF)
1862                         fulldpx = 0;
1863                 else
1864                         return -EINVAL;
1865
1866                 if (lp->speed == SPEED_1000) {
1867                         /* if X-full requested while not supported, or
1868                            X-half requested while not supported... */
1869                         if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1870                                 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1871                                 return -EINVAL;
1872                         bmcr |= BMCR_SPEED1000;
1873                 } else if (lp->speed == SPEED_100) {
1874                         if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1875                                 (!fulldpx && !(bmsr & BMSR_100HALF)))
1876                                 return -EINVAL;
1877                         bmcr |= BMCR_SPEED100;
1878                 } else if (lp->speed == SPEED_10) {
1879                         if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1880                                 (!fulldpx && !(bmsr & BMSR_10HALF)))
1881                                 return -EINVAL;
1882                 } else
1883                         return -EINVAL;
1884         }
1885
1886         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1887         if (err)
1888                 return err;
1889
1890 #if 0
1891         err = mii_read(np, np->phy_addr, MII_BMCR);
1892         if (err < 0)
1893                 return err;
1894         bmcr = err;
1895
1896         err = mii_read(np, np->phy_addr, MII_BMSR);
1897         if (err < 0)
1898                 return err;
1899         bmsr = err;
1900
1901         pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1902                 np->port, bmcr, bmsr);
1903 #endif
1904
1905         return 0;
1906 }
1907
1908 static int xcvr_init_1g(struct niu *np)
1909 {
1910         u64 val;
1911
1912         /* XXX shared resource, lock parent XXX */
1913         val = nr64(MIF_CONFIG);
1914         val &= ~MIF_CONFIG_INDIRECT_MODE;
1915         nw64(MIF_CONFIG, val);
1916
1917         return mii_init_common(np);
1918 }
1919
1920 static int niu_xcvr_init(struct niu *np)
1921 {
1922         const struct niu_phy_ops *ops = np->phy_ops;
1923         int err;
1924
1925         err = 0;
1926         if (ops->xcvr_init)
1927                 err = ops->xcvr_init(np);
1928
1929         return err;
1930 }
1931
1932 static int niu_serdes_init(struct niu *np)
1933 {
1934         const struct niu_phy_ops *ops = np->phy_ops;
1935         int err;
1936
1937         err = 0;
1938         if (ops->serdes_init)
1939                 err = ops->serdes_init(np);
1940
1941         return err;
1942 }
1943
1944 static void niu_init_xif(struct niu *);
1945 static void niu_handle_led(struct niu *, int status);
1946
1947 static int niu_link_status_common(struct niu *np, int link_up)
1948 {
1949         struct niu_link_config *lp = &np->link_config;
1950         struct net_device *dev = np->dev;
1951         unsigned long flags;
1952
1953         if (!netif_carrier_ok(dev) && link_up) {
1954                 niuinfo(LINK, "%s: Link is up at %s, %s duplex\n",
1955                        dev->name,
1956                        (lp->active_speed == SPEED_10000 ?
1957                         "10Gb/sec" :
1958                         (lp->active_speed == SPEED_1000 ?
1959                          "1Gb/sec" :
1960                          (lp->active_speed == SPEED_100 ?
1961                           "100Mbit/sec" : "10Mbit/sec"))),
1962                        (lp->active_duplex == DUPLEX_FULL ?
1963                         "full" : "half"));
1964
1965                 spin_lock_irqsave(&np->lock, flags);
1966                 niu_init_xif(np);
1967                 niu_handle_led(np, 1);
1968                 spin_unlock_irqrestore(&np->lock, flags);
1969
1970                 netif_carrier_on(dev);
1971         } else if (netif_carrier_ok(dev) && !link_up) {
1972                 niuwarn(LINK, "%s: Link is down\n", dev->name);
1973                 spin_lock_irqsave(&np->lock, flags);
1974                 niu_handle_led(np, 0);
1975                 spin_unlock_irqrestore(&np->lock, flags);
1976                 netif_carrier_off(dev);
1977         }
1978
1979         return 0;
1980 }
1981
1982 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1983 {
1984         int err, link_up, pma_status, pcs_status;
1985
1986         link_up = 0;
1987
1988         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1989                         MRVL88X2011_10G_PMD_STATUS_2);
1990         if (err < 0)
1991                 goto out;
1992
1993         /* Check PMA/PMD Register: 1.0001.2 == 1 */
1994         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1995                         MRVL88X2011_PMA_PMD_STATUS_1);
1996         if (err < 0)
1997                 goto out;
1998
1999         pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
2000
2001         /* Check PMC Register : 3.0001.2 == 1: read twice */
2002         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
2003                         MRVL88X2011_PMA_PMD_STATUS_1);
2004         if (err < 0)
2005                 goto out;
2006
2007         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
2008                         MRVL88X2011_PMA_PMD_STATUS_1);
2009         if (err < 0)
2010                 goto out;
2011
2012         pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
2013
2014         /* Check XGXS Register : 4.0018.[0-3,12] */
2015         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
2016                         MRVL88X2011_10G_XGXS_LANE_STAT);
2017         if (err < 0)
2018                 goto out;
2019
2020         if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
2021                     PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
2022                     PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
2023                     0x800))
2024                 link_up = (pma_status && pcs_status) ? 1 : 0;
2025
2026         np->link_config.active_speed = SPEED_10000;
2027         np->link_config.active_duplex = DUPLEX_FULL;
2028         err = 0;
2029 out:
2030         mrvl88x2011_act_led(np, (link_up ?
2031                                  MRVL88X2011_LED_CTL_PCS_ACT :
2032                                  MRVL88X2011_LED_CTL_OFF));
2033
2034         *link_up_p = link_up;
2035         return err;
2036 }
2037
2038 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2039 {
2040         int err, link_up;
2041         link_up = 0;
2042
2043         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2044                         BCM8704_PMD_RCV_SIGDET);
2045         if (err < 0 || err == 0xffff)
2046                 goto out;
2047         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2048                 err = 0;
2049                 goto out;
2050         }
2051
2052         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2053                         BCM8704_PCS_10G_R_STATUS);
2054         if (err < 0)
2055                 goto out;
2056
2057         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2058                 err = 0;
2059                 goto out;
2060         }
2061
2062         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2063                         BCM8704_PHYXS_XGXS_LANE_STAT);
2064         if (err < 0)
2065                 goto out;
2066         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2067                     PHYXS_XGXS_LANE_STAT_MAGIC |
2068                     PHYXS_XGXS_LANE_STAT_PATTEST |
2069                     PHYXS_XGXS_LANE_STAT_LANE3 |
2070                     PHYXS_XGXS_LANE_STAT_LANE2 |
2071                     PHYXS_XGXS_LANE_STAT_LANE1 |
2072                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2073                 err = 0;
2074                 np->link_config.active_speed = SPEED_INVALID;
2075                 np->link_config.active_duplex = DUPLEX_INVALID;
2076                 goto out;
2077         }
2078
2079         link_up = 1;
2080         np->link_config.active_speed = SPEED_10000;
2081         np->link_config.active_duplex = DUPLEX_FULL;
2082         err = 0;
2083
2084 out:
2085         *link_up_p = link_up;
2086         return err;
2087 }
2088
2089 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2090 {
2091         int err, link_up;
2092
2093         link_up = 0;
2094
2095         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2096                         BCM8704_PMD_RCV_SIGDET);
2097         if (err < 0)
2098                 goto out;
2099         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2100                 err = 0;
2101                 goto out;
2102         }
2103
2104         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2105                         BCM8704_PCS_10G_R_STATUS);
2106         if (err < 0)
2107                 goto out;
2108         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2109                 err = 0;
2110                 goto out;
2111         }
2112
2113         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2114                         BCM8704_PHYXS_XGXS_LANE_STAT);
2115         if (err < 0)
2116                 goto out;
2117
2118         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2119                     PHYXS_XGXS_LANE_STAT_MAGIC |
2120                     PHYXS_XGXS_LANE_STAT_LANE3 |
2121                     PHYXS_XGXS_LANE_STAT_LANE2 |
2122                     PHYXS_XGXS_LANE_STAT_LANE1 |
2123                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2124                 err = 0;
2125                 goto out;
2126         }
2127
2128         link_up = 1;
2129         np->link_config.active_speed = SPEED_10000;
2130         np->link_config.active_duplex = DUPLEX_FULL;
2131         err = 0;
2132
2133 out:
2134         *link_up_p = link_up;
2135         return err;
2136 }
2137
2138 static int link_status_10g(struct niu *np, int *link_up_p)
2139 {
2140         unsigned long flags;
2141         int err = -EINVAL;
2142
2143         spin_lock_irqsave(&np->lock, flags);
2144
2145         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2146                 int phy_id;
2147
2148                 phy_id = phy_decode(np->parent->port_phy, np->port);
2149                 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2150
2151                 /* handle different phy types */
2152                 switch (phy_id & NIU_PHY_ID_MASK) {
2153                 case NIU_PHY_ID_MRVL88X2011:
2154                         err = link_status_10g_mrvl(np, link_up_p);
2155                         break;
2156
2157                 default: /* bcom 8704 */
2158                         err = link_status_10g_bcom(np, link_up_p);
2159                         break;
2160                 }
2161         }
2162
2163         spin_unlock_irqrestore(&np->lock, flags);
2164
2165         return err;
2166 }
2167
2168 static int niu_10g_phy_present(struct niu *np)
2169 {
2170         u64 sig, mask, val;
2171
2172         sig = nr64(ESR_INT_SIGNALS);
2173         switch (np->port) {
2174         case 0:
2175                 mask = ESR_INT_SIGNALS_P0_BITS;
2176                 val = (ESR_INT_SRDY0_P0 |
2177                        ESR_INT_DET0_P0 |
2178                        ESR_INT_XSRDY_P0 |
2179                        ESR_INT_XDP_P0_CH3 |
2180                        ESR_INT_XDP_P0_CH2 |
2181                        ESR_INT_XDP_P0_CH1 |
2182                        ESR_INT_XDP_P0_CH0);
2183                 break;
2184
2185         case 1:
2186                 mask = ESR_INT_SIGNALS_P1_BITS;
2187                 val = (ESR_INT_SRDY0_P1 |
2188                        ESR_INT_DET0_P1 |
2189                        ESR_INT_XSRDY_P1 |
2190                        ESR_INT_XDP_P1_CH3 |
2191                        ESR_INT_XDP_P1_CH2 |
2192                        ESR_INT_XDP_P1_CH1 |
2193                        ESR_INT_XDP_P1_CH0);
2194                 break;
2195
2196         default:
2197                 return 0;
2198         }
2199
2200         if ((sig & mask) != val)
2201                 return 0;
2202         return 1;
2203 }
2204
2205 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2206 {
2207         unsigned long flags;
2208         int err = 0;
2209         int phy_present;
2210         int phy_present_prev;
2211
2212         spin_lock_irqsave(&np->lock, flags);
2213
2214         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2215                 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2216                         1 : 0;
2217                 phy_present = niu_10g_phy_present(np);
2218                 if (phy_present != phy_present_prev) {
2219                         /* state change */
2220                         if (phy_present) {
2221                                 /* A NEM was just plugged in */
2222                                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2223                                 if (np->phy_ops->xcvr_init)
2224                                         err = np->phy_ops->xcvr_init(np);
2225                                 if (err) {
2226                                         err = mdio_read(np, np->phy_addr,
2227                                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2228                                         if (err == 0xffff) {
2229                                                 /* No mdio, back-to-back XAUI */
2230                                                 goto out;
2231                                         }
2232                                         /* debounce */
2233                                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2234                                 }
2235                         } else {
2236                                 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2237                                 *link_up_p = 0;
2238                                 niuwarn(LINK, "%s: Hotplug PHY Removed\n",
2239                                         np->dev->name);
2240                         }
2241                 }
2242 out:
2243                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
2244                         err = link_status_10g_bcm8706(np, link_up_p);
2245                         if (err == 0xffff) {
2246                                 /* No mdio, back-to-back XAUI: it is C10NEM */
2247                                 *link_up_p = 1;
2248                                 np->link_config.active_speed = SPEED_10000;
2249                                 np->link_config.active_duplex = DUPLEX_FULL;
2250                         }
2251                 }
2252         }
2253
2254         spin_unlock_irqrestore(&np->lock, flags);
2255
2256         return 0;
2257 }
2258
2259 static int niu_link_status(struct niu *np, int *link_up_p)
2260 {
2261         const struct niu_phy_ops *ops = np->phy_ops;
2262         int err;
2263
2264         err = 0;
2265         if (ops->link_status)
2266                 err = ops->link_status(np, link_up_p);
2267
2268         return err;
2269 }
2270
2271 static void niu_timer(unsigned long __opaque)
2272 {
2273         struct niu *np = (struct niu *) __opaque;
2274         unsigned long off;
2275         int err, link_up;
2276
2277         err = niu_link_status(np, &link_up);
2278         if (!err)
2279                 niu_link_status_common(np, link_up);
2280
2281         if (netif_carrier_ok(np->dev))
2282                 off = 5 * HZ;
2283         else
2284                 off = 1 * HZ;
2285         np->timer.expires = jiffies + off;
2286
2287         add_timer(&np->timer);
2288 }
2289
2290 static const struct niu_phy_ops phy_ops_10g_serdes = {
2291         .serdes_init            = serdes_init_10g_serdes,
2292         .link_status            = link_status_10g_serdes,
2293 };
2294
2295 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2296         .serdes_init            = serdes_init_niu_10g_serdes,
2297         .link_status            = link_status_10g_serdes,
2298 };
2299
2300 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2301         .serdes_init            = serdes_init_niu_1g_serdes,
2302         .link_status            = link_status_1g_serdes,
2303 };
2304
2305 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2306         .xcvr_init              = xcvr_init_1g_rgmii,
2307         .link_status            = link_status_1g_rgmii,
2308 };
2309
2310 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2311         .serdes_init            = serdes_init_niu_10g_fiber,
2312         .xcvr_init              = xcvr_init_10g,
2313         .link_status            = link_status_10g,
2314 };
2315
2316 static const struct niu_phy_ops phy_ops_10g_fiber = {
2317         .serdes_init            = serdes_init_10g,
2318         .xcvr_init              = xcvr_init_10g,
2319         .link_status            = link_status_10g,
2320 };
2321
2322 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2323         .serdes_init            = serdes_init_10g,
2324         .xcvr_init              = xcvr_init_10g_bcm8706,
2325         .link_status            = link_status_10g_hotplug,
2326 };
2327
2328 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2329         .serdes_init            = serdes_init_niu_10g_fiber,
2330         .xcvr_init              = xcvr_init_10g_bcm8706,
2331         .link_status            = link_status_10g_hotplug,
2332 };
2333
2334 static const struct niu_phy_ops phy_ops_10g_copper = {
2335         .serdes_init            = serdes_init_10g,
2336         .link_status            = link_status_10g, /* XXX */
2337 };
2338
2339 static const struct niu_phy_ops phy_ops_1g_fiber = {
2340         .serdes_init            = serdes_init_1g,
2341         .xcvr_init              = xcvr_init_1g,
2342         .link_status            = link_status_1g,
2343 };
2344
2345 static const struct niu_phy_ops phy_ops_1g_copper = {
2346         .xcvr_init              = xcvr_init_1g,
2347         .link_status            = link_status_1g,
2348 };
2349
2350 struct niu_phy_template {
2351         const struct niu_phy_ops        *ops;
2352         u32                             phy_addr_base;
2353 };
2354
2355 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2356         .ops            = &phy_ops_10g_fiber_niu,
2357         .phy_addr_base  = 16,
2358 };
2359
2360 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2361         .ops            = &phy_ops_10g_serdes_niu,
2362         .phy_addr_base  = 0,
2363 };
2364
2365 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2366         .ops            = &phy_ops_1g_serdes_niu,
2367         .phy_addr_base  = 0,
2368 };
2369
2370 static const struct niu_phy_template phy_template_10g_fiber = {
2371         .ops            = &phy_ops_10g_fiber,
2372         .phy_addr_base  = 8,
2373 };
2374
2375 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2376         .ops            = &phy_ops_10g_fiber_hotplug,
2377         .phy_addr_base  = 8,
2378 };
2379
2380 static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2381         .ops            = &phy_ops_niu_10g_hotplug,
2382         .phy_addr_base  = 8,
2383 };
2384
2385 static const struct niu_phy_template phy_template_10g_copper = {
2386         .ops            = &phy_ops_10g_copper,
2387         .phy_addr_base  = 10,
2388 };
2389
2390 static const struct niu_phy_template phy_template_1g_fiber = {
2391         .ops            = &phy_ops_1g_fiber,
2392         .phy_addr_base  = 0,
2393 };
2394
2395 static const struct niu_phy_template phy_template_1g_copper = {
2396         .ops            = &phy_ops_1g_copper,
2397         .phy_addr_base  = 0,
2398 };
2399
2400 static const struct niu_phy_template phy_template_1g_rgmii = {
2401         .ops            = &phy_ops_1g_rgmii,
2402         .phy_addr_base  = 0,
2403 };
2404
2405 static const struct niu_phy_template phy_template_10g_serdes = {
2406         .ops            = &phy_ops_10g_serdes,
2407         .phy_addr_base  = 0,
2408 };
2409
2410 static int niu_atca_port_num[4] = {
2411         0, 0,  11, 10
2412 };
2413
2414 static int serdes_init_10g_serdes(struct niu *np)
2415 {
2416         struct niu_link_config *lp = &np->link_config;
2417         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2418         u64 ctrl_val, test_cfg_val, sig, mask, val;
2419         u64 reset_val;
2420
2421         switch (np->port) {
2422         case 0:
2423                 reset_val =  ENET_SERDES_RESET_0;
2424                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2425                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2426                 pll_cfg = ENET_SERDES_0_PLL_CFG;
2427                 break;
2428         case 1:
2429                 reset_val =  ENET_SERDES_RESET_1;
2430                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2431                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2432                 pll_cfg = ENET_SERDES_1_PLL_CFG;
2433                 break;
2434
2435         default:
2436                 return -EINVAL;
2437         }
2438         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2439                     ENET_SERDES_CTRL_SDET_1 |
2440                     ENET_SERDES_CTRL_SDET_2 |
2441                     ENET_SERDES_CTRL_SDET_3 |
2442                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2443                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2444                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2445                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2446                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2447                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2448                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2449                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2450         test_cfg_val = 0;
2451
2452         if (lp->loopback_mode == LOOPBACK_PHY) {
2453                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2454                                   ENET_SERDES_TEST_MD_0_SHIFT) |
2455                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2456                                   ENET_SERDES_TEST_MD_1_SHIFT) |
2457                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2458                                   ENET_SERDES_TEST_MD_2_SHIFT) |
2459                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2460                                   ENET_SERDES_TEST_MD_3_SHIFT));
2461         }
2462
2463         esr_reset(np);
2464         nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2465         nw64(ctrl_reg, ctrl_val);
2466         nw64(test_cfg_reg, test_cfg_val);
2467
2468         /* Initialize all 4 lanes of the SERDES.  */
2469         for (i = 0; i < 4; i++) {
2470                 u32 rxtx_ctrl, glue0;
2471                 int err;
2472
2473                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2474                 if (err)
2475                         return err;
2476                 err = esr_read_glue0(np, i, &glue0);
2477                 if (err)
2478                         return err;
2479
2480                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2481                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2482                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2483
2484                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2485                            ESR_GLUE_CTRL0_THCNT |
2486                            ESR_GLUE_CTRL0_BLTIME);
2487                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2488                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2489                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2490                           (BLTIME_300_CYCLES <<
2491                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
2492
2493                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2494                 if (err)
2495                         return err;
2496                 err = esr_write_glue0(np, i, glue0);
2497                 if (err)
2498                         return err;
2499         }
2500
2501
2502         sig = nr64(ESR_INT_SIGNALS);
2503         switch (np->port) {
2504         case 0:
2505                 mask = ESR_INT_SIGNALS_P0_BITS;
2506                 val = (ESR_INT_SRDY0_P0 |
2507                        ESR_INT_DET0_P0 |
2508                        ESR_INT_XSRDY_P0 |
2509                        ESR_INT_XDP_P0_CH3 |
2510                        ESR_INT_XDP_P0_CH2 |
2511                        ESR_INT_XDP_P0_CH1 |
2512                        ESR_INT_XDP_P0_CH0);
2513                 break;
2514
2515         case 1:
2516                 mask = ESR_INT_SIGNALS_P1_BITS;
2517                 val = (ESR_INT_SRDY0_P1 |
2518                        ESR_INT_DET0_P1 |
2519                        ESR_INT_XSRDY_P1 |
2520                        ESR_INT_XDP_P1_CH3 |
2521                        ESR_INT_XDP_P1_CH2 |
2522                        ESR_INT_XDP_P1_CH1 |
2523                        ESR_INT_XDP_P1_CH0);
2524                 break;
2525
2526         default:
2527                 return -EINVAL;
2528         }
2529
2530         if ((sig & mask) != val) {
2531                 int err;
2532                 err = serdes_init_1g_serdes(np);
2533                 if (!err) {
2534                         np->flags &= ~NIU_FLAGS_10G;
2535                         np->mac_xcvr = MAC_XCVR_PCS;
2536                 }  else {
2537                         dev_err(np->device, PFX "Port %u 10G/1G SERDES Link Failed \n",
2538                          np->port);
2539                         return -ENODEV;
2540                 }
2541         }
2542
2543         return 0;
2544 }
2545
2546 static int niu_determine_phy_disposition(struct niu *np)
2547 {
2548         struct niu_parent *parent = np->parent;
2549         u8 plat_type = parent->plat_type;
2550         const struct niu_phy_template *tp;
2551         u32 phy_addr_off = 0;
2552
2553         if (plat_type == PLAT_TYPE_NIU) {
2554                 switch (np->flags &
2555                         (NIU_FLAGS_10G |
2556                          NIU_FLAGS_FIBER |
2557                          NIU_FLAGS_XCVR_SERDES)) {
2558                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2559                         /* 10G Serdes */
2560                         tp = &phy_template_niu_10g_serdes;
2561                         break;
2562                 case NIU_FLAGS_XCVR_SERDES:
2563                         /* 1G Serdes */
2564                         tp = &phy_template_niu_1g_serdes;
2565                         break;
2566                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2567                         /* 10G Fiber */
2568                 default:
2569                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2570                                 tp = &phy_template_niu_10g_hotplug;
2571                                 if (np->port == 0)
2572                                         phy_addr_off = 8;
2573                                 if (np->port == 1)
2574                                         phy_addr_off = 12;
2575                         } else {
2576                                 tp = &phy_template_niu_10g_fiber;
2577                                 phy_addr_off += np->port;
2578                         }
2579                         break;
2580                 }
2581         } else {
2582                 switch (np->flags &
2583                         (NIU_FLAGS_10G |
2584                          NIU_FLAGS_FIBER |
2585                          NIU_FLAGS_XCVR_SERDES)) {
2586                 case 0:
2587                         /* 1G copper */
2588                         tp = &phy_template_1g_copper;
2589                         if (plat_type == PLAT_TYPE_VF_P0)
2590                                 phy_addr_off = 10;
2591                         else if (plat_type == PLAT_TYPE_VF_P1)
2592                                 phy_addr_off = 26;
2593
2594                         phy_addr_off += (np->port ^ 0x3);
2595                         break;
2596
2597                 case NIU_FLAGS_10G:
2598                         /* 10G copper */
2599                         tp = &phy_template_10g_copper;
2600                         break;
2601
2602                 case NIU_FLAGS_FIBER:
2603                         /* 1G fiber */
2604                         tp = &phy_template_1g_fiber;
2605                         break;
2606
2607                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2608                         /* 10G fiber */
2609                         tp = &phy_template_10g_fiber;
2610                         if (plat_type == PLAT_TYPE_VF_P0 ||
2611                             plat_type == PLAT_TYPE_VF_P1)
2612                                 phy_addr_off = 8;
2613                         phy_addr_off += np->port;
2614                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2615                                 tp = &phy_template_10g_fiber_hotplug;
2616                                 if (np->port == 0)
2617                                         phy_addr_off = 8;
2618                                 if (np->port == 1)
2619                                         phy_addr_off = 12;
2620                         }
2621                         break;
2622
2623                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2624                 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2625                 case NIU_FLAGS_XCVR_SERDES:
2626                         switch(np->port) {
2627                         case 0:
2628                         case 1:
2629                                 tp = &phy_template_10g_serdes;
2630                                 break;
2631                         case 2:
2632                         case 3:
2633                                 tp = &phy_template_1g_rgmii;
2634                                 break;
2635                         default:
2636                                 return -EINVAL;
2637                                 break;
2638                         }
2639                         phy_addr_off = niu_atca_port_num[np->port];
2640                         break;
2641
2642                 default:
2643                         return -EINVAL;
2644                 }
2645         }
2646
2647         np->phy_ops = tp->ops;
2648         np->phy_addr = tp->phy_addr_base + phy_addr_off;
2649
2650         return 0;
2651 }
2652
2653 static int niu_init_link(struct niu *np)
2654 {
2655         struct niu_parent *parent = np->parent;
2656         int err, ignore;
2657
2658         if (parent->plat_type == PLAT_TYPE_NIU) {
2659                 err = niu_xcvr_init(np);
2660                 if (err)
2661                         return err;
2662                 msleep(200);
2663         }
2664         err = niu_serdes_init(np);
2665         if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
2666                 return err;
2667         msleep(200);
2668         err = niu_xcvr_init(np);
2669         if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
2670                 niu_link_status(np, &ignore);
2671         return 0;
2672 }
2673
2674 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2675 {
2676         u16 reg0 = addr[4] << 8 | addr[5];
2677         u16 reg1 = addr[2] << 8 | addr[3];
2678         u16 reg2 = addr[0] << 8 | addr[1];
2679
2680         if (np->flags & NIU_FLAGS_XMAC) {
2681                 nw64_mac(XMAC_ADDR0, reg0);
2682                 nw64_mac(XMAC_ADDR1, reg1);
2683                 nw64_mac(XMAC_ADDR2, reg2);
2684         } else {
2685                 nw64_mac(BMAC_ADDR0, reg0);
2686                 nw64_mac(BMAC_ADDR1, reg1);
2687                 nw64_mac(BMAC_ADDR2, reg2);
2688         }
2689 }
2690
2691 static int niu_num_alt_addr(struct niu *np)
2692 {
2693         if (np->flags & NIU_FLAGS_XMAC)
2694                 return XMAC_NUM_ALT_ADDR;
2695         else
2696                 return BMAC_NUM_ALT_ADDR;
2697 }
2698
2699 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2700 {
2701         u16 reg0 = addr[4] << 8 | addr[5];
2702         u16 reg1 = addr[2] << 8 | addr[3];
2703         u16 reg2 = addr[0] << 8 | addr[1];
2704
2705         if (index >= niu_num_alt_addr(np))
2706                 return -EINVAL;
2707
2708         if (np->flags & NIU_FLAGS_XMAC) {
2709                 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2710                 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2711                 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2712         } else {
2713                 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2714                 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2715                 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2716         }
2717
2718         return 0;
2719 }
2720
2721 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2722 {
2723         unsigned long reg;
2724         u64 val, mask;
2725
2726         if (index >= niu_num_alt_addr(np))
2727                 return -EINVAL;
2728
2729         if (np->flags & NIU_FLAGS_XMAC) {
2730                 reg = XMAC_ADDR_CMPEN;
2731                 mask = 1 << index;
2732         } else {
2733                 reg = BMAC_ADDR_CMPEN;
2734                 mask = 1 << (index + 1);
2735         }
2736
2737         val = nr64_mac(reg);
2738         if (on)
2739                 val |= mask;
2740         else
2741                 val &= ~mask;
2742         nw64_mac(reg, val);
2743
2744         return 0;
2745 }
2746
2747 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2748                                    int num, int mac_pref)
2749 {
2750         u64 val = nr64_mac(reg);
2751         val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2752         val |= num;
2753         if (mac_pref)
2754                 val |= HOST_INFO_MPR;
2755         nw64_mac(reg, val);
2756 }
2757
2758 static int __set_rdc_table_num(struct niu *np,
2759                                int xmac_index, int bmac_index,
2760                                int rdc_table_num, int mac_pref)
2761 {
2762         unsigned long reg;
2763
2764         if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2765                 return -EINVAL;
2766         if (np->flags & NIU_FLAGS_XMAC)
2767                 reg = XMAC_HOST_INFO(xmac_index);
2768         else
2769                 reg = BMAC_HOST_INFO(bmac_index);
2770         __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2771         return 0;
2772 }
2773
2774 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2775                                          int mac_pref)
2776 {
2777         return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2778 }
2779
2780 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2781                                            int mac_pref)
2782 {
2783         return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2784 }
2785
2786 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2787                                      int table_num, int mac_pref)
2788 {
2789         if (idx >= niu_num_alt_addr(np))
2790                 return -EINVAL;
2791         return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2792 }
2793
2794 static u64 vlan_entry_set_parity(u64 reg_val)
2795 {
2796         u64 port01_mask;
2797         u64 port23_mask;
2798
2799         port01_mask = 0x00ff;
2800         port23_mask = 0xff00;
2801
2802         if (hweight64(reg_val & port01_mask) & 1)
2803                 reg_val |= ENET_VLAN_TBL_PARITY0;
2804         else
2805                 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2806
2807         if (hweight64(reg_val & port23_mask) & 1)
2808                 reg_val |= ENET_VLAN_TBL_PARITY1;
2809         else
2810                 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2811
2812         return reg_val;
2813 }
2814
2815 static void vlan_tbl_write(struct niu *np, unsigned long index,
2816                            int port, int vpr, int rdc_table)
2817 {
2818         u64 reg_val = nr64(ENET_VLAN_TBL(index));
2819
2820         reg_val &= ~((ENET_VLAN_TBL_VPR |
2821                       ENET_VLAN_TBL_VLANRDCTBLN) <<
2822                      ENET_VLAN_TBL_SHIFT(port));
2823         if (vpr)
2824                 reg_val |= (ENET_VLAN_TBL_VPR <<
2825                             ENET_VLAN_TBL_SHIFT(port));
2826         reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2827
2828         reg_val = vlan_entry_set_parity(reg_val);
2829
2830         nw64(ENET_VLAN_TBL(index), reg_val);
2831 }
2832
2833 static void vlan_tbl_clear(struct niu *np)
2834 {
2835         int i;
2836
2837         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2838                 nw64(ENET_VLAN_TBL(i), 0);
2839 }
2840
2841 static int tcam_wait_bit(struct niu *np, u64 bit)
2842 {
2843         int limit = 1000;
2844
2845         while (--limit > 0) {
2846                 if (nr64(TCAM_CTL) & bit)
2847                         break;
2848                 udelay(1);
2849         }
2850         if (limit < 0)
2851                 return -ENODEV;
2852
2853         return 0;
2854 }
2855
2856 static int tcam_flush(struct niu *np, int index)
2857 {
2858         nw64(TCAM_KEY_0, 0x00);
2859         nw64(TCAM_KEY_MASK_0, 0xff);
2860         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2861
2862         return tcam_wait_bit(np, TCAM_CTL_STAT);
2863 }
2864
2865 #if 0
2866 static int tcam_read(struct niu *np, int index,
2867                      u64 *key, u64 *mask)
2868 {
2869         int err;
2870
2871         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2872         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2873         if (!err) {
2874                 key[0] = nr64(TCAM_KEY_0);
2875                 key[1] = nr64(TCAM_KEY_1);
2876                 key[2] = nr64(TCAM_KEY_2);
2877                 key[3] = nr64(TCAM_KEY_3);
2878                 mask[0] = nr64(TCAM_KEY_MASK_0);
2879                 mask[1] = nr64(TCAM_KEY_MASK_1);
2880                 mask[2] = nr64(TCAM_KEY_MASK_2);
2881                 mask[3] = nr64(TCAM_KEY_MASK_3);
2882         }
2883         return err;
2884 }
2885 #endif
2886
2887 static int tcam_write(struct niu *np, int index,
2888                       u64 *key, u64 *mask)
2889 {
2890         nw64(TCAM_KEY_0, key[0]);
2891         nw64(TCAM_KEY_1, key[1]);
2892         nw64(TCAM_KEY_2, key[2]);
2893         nw64(TCAM_KEY_3, key[3]);
2894         nw64(TCAM_KEY_MASK_0, mask[0]);
2895         nw64(TCAM_KEY_MASK_1, mask[1]);
2896         nw64(TCAM_KEY_MASK_2, mask[2]);
2897         nw64(TCAM_KEY_MASK_3, mask[3]);
2898         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2899
2900         return tcam_wait_bit(np, TCAM_CTL_STAT);
2901 }
2902
2903 #if 0
2904 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2905 {
2906         int err;
2907
2908         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2909         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2910         if (!err)
2911                 *data = nr64(TCAM_KEY_1);
2912
2913         return err;
2914 }
2915 #endif
2916
2917 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2918 {
2919         nw64(TCAM_KEY_1, assoc_data);
2920         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2921
2922         return tcam_wait_bit(np, TCAM_CTL_STAT);
2923 }
2924
2925 static void tcam_enable(struct niu *np, int on)
2926 {
2927         u64 val = nr64(FFLP_CFG_1);
2928
2929         if (on)
2930                 val &= ~FFLP_CFG_1_TCAM_DIS;
2931         else
2932                 val |= FFLP_CFG_1_TCAM_DIS;
2933         nw64(FFLP_CFG_1, val);
2934 }
2935
2936 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2937 {
2938         u64 val = nr64(FFLP_CFG_1);
2939
2940         val &= ~(FFLP_CFG_1_FFLPINITDONE |
2941                  FFLP_CFG_1_CAMLAT |
2942                  FFLP_CFG_1_CAMRATIO);
2943         val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2944         val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2945         nw64(FFLP_CFG_1, val);
2946
2947         val = nr64(FFLP_CFG_1);
2948         val |= FFLP_CFG_1_FFLPINITDONE;
2949         nw64(FFLP_CFG_1, val);
2950 }
2951
2952 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2953                                       int on)
2954 {
2955         unsigned long reg;
2956         u64 val;
2957
2958         if (class < CLASS_CODE_ETHERTYPE1 ||
2959             class > CLASS_CODE_ETHERTYPE2)
2960                 return -EINVAL;
2961
2962         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2963         val = nr64(reg);
2964         if (on)
2965                 val |= L2_CLS_VLD;
2966         else
2967                 val &= ~L2_CLS_VLD;
2968         nw64(reg, val);
2969
2970         return 0;
2971 }
2972
2973 #if 0
2974 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2975                                    u64 ether_type)
2976 {
2977         unsigned long reg;
2978         u64 val;
2979
2980         if (class < CLASS_CODE_ETHERTYPE1 ||
2981             class > CLASS_CODE_ETHERTYPE2 ||
2982             (ether_type & ~(u64)0xffff) != 0)
2983                 return -EINVAL;
2984
2985         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2986         val = nr64(reg);
2987         val &= ~L2_CLS_ETYPE;
2988         val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2989         nw64(reg, val);
2990
2991         return 0;
2992 }
2993 #endif
2994
2995 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2996                                      int on)
2997 {
2998         unsigned long reg;
2999         u64 val;
3000
3001         if (class < CLASS_CODE_USER_PROG1 ||
3002             class > CLASS_CODE_USER_PROG4)
3003                 return -EINVAL;
3004
3005         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
3006         val = nr64(reg);
3007         if (on)
3008                 val |= L3_CLS_VALID;
3009         else
3010                 val &= ~L3_CLS_VALID;
3011         nw64(reg, val);
3012
3013         return 0;
3014 }
3015
3016 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
3017                                   int ipv6, u64 protocol_id,
3018                                   u64 tos_mask, u64 tos_val)
3019 {
3020         unsigned long reg;
3021         u64 val;
3022
3023         if (class < CLASS_CODE_USER_PROG1 ||
3024             class > CLASS_CODE_USER_PROG4 ||
3025             (protocol_id & ~(u64)0xff) != 0 ||
3026             (tos_mask & ~(u64)0xff) != 0 ||
3027             (tos_val & ~(u64)0xff) != 0)
3028                 return -EINVAL;
3029
3030         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
3031         val = nr64(reg);
3032         val &= ~(L3_CLS_IPVER | L3_CLS_PID |
3033                  L3_CLS_TOSMASK | L3_CLS_TOS);
3034         if (ipv6)
3035                 val |= L3_CLS_IPVER;
3036         val |= (protocol_id << L3_CLS_PID_SHIFT);
3037         val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
3038         val |= (tos_val << L3_CLS_TOS_SHIFT);
3039         nw64(reg, val);
3040
3041         return 0;
3042 }
3043
3044 static int tcam_early_init(struct niu *np)
3045 {
3046         unsigned long i;
3047         int err;
3048
3049         tcam_enable(np, 0);
3050         tcam_set_lat_and_ratio(np,
3051                                DEFAULT_TCAM_LATENCY,
3052                                DEFAULT_TCAM_ACCESS_RATIO);
3053         for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3054                 err = tcam_user_eth_class_enable(np, i, 0);
3055                 if (err)
3056                         return err;
3057         }
3058         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3059                 err = tcam_user_ip_class_enable(np, i, 0);
3060                 if (err)
3061                         return err;
3062         }
3063
3064         return 0;
3065 }
3066
3067 static int tcam_flush_all(struct niu *np)
3068 {
3069         unsigned long i;
3070
3071         for (i = 0; i < np->parent->tcam_num_entries; i++) {
3072                 int err = tcam_flush(np, i);
3073                 if (err)
3074                         return err;
3075         }
3076         return 0;
3077 }
3078
3079 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3080 {
3081         return ((u64)index | (num_entries == 1 ?
3082                               HASH_TBL_ADDR_AUTOINC : 0));
3083 }
3084
3085 #if 0
3086 static int hash_read(struct niu *np, unsigned long partition,
3087                      unsigned long index, unsigned long num_entries,
3088                      u64 *data)
3089 {
3090         u64 val = hash_addr_regval(index, num_entries);
3091         unsigned long i;
3092
3093         if (partition >= FCRAM_NUM_PARTITIONS ||
3094             index + num_entries > FCRAM_SIZE)
3095                 return -EINVAL;
3096
3097         nw64(HASH_TBL_ADDR(partition), val);
3098         for (i = 0; i < num_entries; i++)
3099                 data[i] = nr64(HASH_TBL_DATA(partition));
3100
3101         return 0;
3102 }
3103 #endif
3104
3105 static int hash_write(struct niu *np, unsigned long partition,
3106                       unsigned long index, unsigned long num_entries,
3107                       u64 *data)
3108 {
3109         u64 val = hash_addr_regval(index, num_entries);
3110         unsigned long i;
3111
3112         if (partition >= FCRAM_NUM_PARTITIONS ||
3113             index + (num_entries * 8) > FCRAM_SIZE)
3114                 return -EINVAL;
3115
3116         nw64(HASH_TBL_ADDR(partition), val);
3117         for (i = 0; i < num_entries; i++)
3118                 nw64(HASH_TBL_DATA(partition), data[i]);
3119
3120         return 0;
3121 }
3122
3123 static void fflp_reset(struct niu *np)
3124 {
3125         u64 val;
3126
3127         nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3128         udelay(10);
3129         nw64(FFLP_CFG_1, 0);
3130
3131         val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3132         nw64(FFLP_CFG_1, val);
3133 }
3134
3135 static void fflp_set_timings(struct niu *np)
3136 {
3137         u64 val = nr64(FFLP_CFG_1);
3138
3139         val &= ~FFLP_CFG_1_FFLPINITDONE;
3140         val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3141         nw64(FFLP_CFG_1, val);
3142
3143         val = nr64(FFLP_CFG_1);
3144         val |= FFLP_CFG_1_FFLPINITDONE;
3145         nw64(FFLP_CFG_1, val);
3146
3147         val = nr64(FCRAM_REF_TMR);
3148         val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3149         val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3150         val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3151         nw64(FCRAM_REF_TMR, val);
3152 }
3153
3154 static int fflp_set_partition(struct niu *np, u64 partition,
3155                               u64 mask, u64 base, int enable)
3156 {
3157         unsigned long reg;
3158         u64 val;
3159
3160         if (partition >= FCRAM_NUM_PARTITIONS ||
3161             (mask & ~(u64)0x1f) != 0 ||
3162             (base & ~(u64)0x1f) != 0)
3163                 return -EINVAL;
3164
3165         reg = FLW_PRT_SEL(partition);
3166
3167         val = nr64(reg);
3168         val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3169         val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3170         val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3171         if (enable)
3172                 val |= FLW_PRT_SEL_EXT;
3173         nw64(reg, val);
3174
3175         return 0;
3176 }
3177
3178 static int fflp_disable_all_partitions(struct niu *np)
3179 {
3180         unsigned long i;
3181
3182         for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3183                 int err = fflp_set_partition(np, 0, 0, 0, 0);
3184                 if (err)
3185                         return err;
3186         }
3187         return 0;
3188 }
3189
3190 static void fflp_llcsnap_enable(struct niu *np, int on)
3191 {
3192         u64 val = nr64(FFLP_CFG_1);
3193
3194         if (on)
3195                 val |= FFLP_CFG_1_LLCSNAP;
3196         else
3197                 val &= ~FFLP_CFG_1_LLCSNAP;
3198         nw64(FFLP_CFG_1, val);
3199 }
3200
3201 static void fflp_errors_enable(struct niu *np, int on)
3202 {
3203         u64 val = nr64(FFLP_CFG_1);
3204
3205         if (on)
3206                 val &= ~FFLP_CFG_1_ERRORDIS;
3207         else
3208                 val |= FFLP_CFG_1_ERRORDIS;
3209         nw64(FFLP_CFG_1, val);
3210 }
3211
3212 static int fflp_hash_clear(struct niu *np)
3213 {
3214         struct fcram_hash_ipv4 ent;
3215         unsigned long i;
3216
3217         /* IPV4 hash entry with valid bit clear, rest is don't care.  */
3218         memset(&ent, 0, sizeof(ent));
3219         ent.header = HASH_HEADER_EXT;
3220
3221         for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3222                 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3223                 if (err)
3224                         return err;
3225         }
3226         return 0;
3227 }
3228
3229 static int fflp_early_init(struct niu *np)
3230 {
3231         struct niu_parent *parent;
3232         unsigned long flags;
3233         int err;
3234
3235         niu_lock_parent(np, flags);
3236
3237         parent = np->parent;
3238         err = 0;
3239         if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3240                 niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n",
3241                        np->port);
3242                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3243                         fflp_reset(np);
3244                         fflp_set_timings(np);
3245                         err = fflp_disable_all_partitions(np);
3246                         if (err) {
3247                                 niudbg(PROBE, "fflp_disable_all_partitions "
3248                                        "failed, err=%d\n", err);
3249                                 goto out;
3250                         }
3251                 }
3252
3253                 err = tcam_early_init(np);
3254                 if (err) {
3255                         niudbg(PROBE, "tcam_early_init failed, err=%d\n",
3256                                err);
3257                         goto out;
3258                 }
3259                 fflp_llcsnap_enable(np, 1);
3260                 fflp_errors_enable(np, 0);
3261                 nw64(H1POLY, 0);
3262                 nw64(H2POLY, 0);
3263
3264                 err = tcam_flush_all(np);
3265                 if (err) {
3266                         niudbg(PROBE, "tcam_flush_all failed, err=%d\n",
3267                                err);
3268                         goto out;
3269                 }
3270                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3271                         err = fflp_hash_clear(np);
3272                         if (err) {
3273                                 niudbg(PROBE, "fflp_hash_clear failed, "
3274                                        "err=%d\n", err);
3275                                 goto out;
3276                         }
3277                 }
3278
3279                 vlan_tbl_clear(np);
3280
3281                 niudbg(PROBE, "fflp_early_init: Success\n");
3282                 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3283         }
3284 out:
3285         niu_unlock_parent(np, flags);
3286         return err;
3287 }
3288
3289 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3290 {
3291         if (class_code < CLASS_CODE_USER_PROG1 ||
3292             class_code > CLASS_CODE_SCTP_IPV6)
3293                 return -EINVAL;
3294
3295         nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3296         return 0;
3297 }
3298
3299 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3300 {
3301         if (class_code < CLASS_CODE_USER_PROG1 ||
3302             class_code > CLASS_CODE_SCTP_IPV6)
3303                 return -EINVAL;
3304
3305         nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3306         return 0;
3307 }
3308
3309 /* Entries for the ports are interleaved in the TCAM */
3310 static u16 tcam_get_index(struct niu *np, u16 idx)
3311 {
3312         /* One entry reserved for IP fragment rule */
3313         if (idx >= (np->clas.tcam_sz - 1))
3314                 idx = 0;
3315         return (np->clas.tcam_top + ((idx+1) * np->parent->num_ports));
3316 }
3317
3318 static u16 tcam_get_size(struct niu *np)
3319 {
3320         /* One entry reserved for IP fragment rule */
3321         return np->clas.tcam_sz - 1;
3322 }
3323
3324 static u16 tcam_get_valid_entry_cnt(struct niu *np)
3325 {
3326         /* One entry reserved for IP fragment rule */
3327         return np->clas.tcam_valid_entries - 1;
3328 }
3329
3330 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3331                               u32 offset, u32 size)
3332 {
3333         int i = skb_shinfo(skb)->nr_frags;
3334         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3335
3336         frag->page = page;
3337         frag->page_offset = offset;
3338         frag->size = size;
3339
3340         skb->len += size;
3341         skb->data_len += size;
3342         skb->truesize += size;
3343
3344         skb_shinfo(skb)->nr_frags = i + 1;
3345 }
3346
3347 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3348 {
3349         a >>= PAGE_SHIFT;
3350         a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3351
3352         return (a & (MAX_RBR_RING_SIZE - 1));
3353 }
3354
3355 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3356                                     struct page ***link)
3357 {
3358         unsigned int h = niu_hash_rxaddr(rp, addr);
3359         struct page *p, **pp;
3360
3361         addr &= PAGE_MASK;
3362         pp = &rp->rxhash[h];
3363         for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3364                 if (p->index == addr) {
3365                         *link = pp;
3366                         break;
3367                 }
3368         }
3369
3370         return p;
3371 }
3372
3373 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3374 {
3375         unsigned int h = niu_hash_rxaddr(rp, base);
3376
3377         page->index = base;
3378         page->mapping = (struct address_space *) rp->rxhash[h];
3379         rp->rxhash[h] = page;
3380 }
3381
3382 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3383                             gfp_t mask, int start_index)
3384 {
3385         struct page *page;
3386         u64 addr;
3387         int i;
3388
3389         page = alloc_page(mask);
3390         if (!page)
3391                 return -ENOMEM;
3392
3393         addr = np->ops->map_page(np->device, page, 0,
3394                                  PAGE_SIZE, DMA_FROM_DEVICE);
3395
3396         niu_hash_page(rp, page, addr);
3397         if (rp->rbr_blocks_per_page > 1)
3398                 atomic_add(rp->rbr_blocks_per_page - 1,
3399                            &compound_head(page)->_count);
3400
3401         for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3402                 __le32 *rbr = &rp->rbr[start_index + i];
3403
3404                 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3405                 addr += rp->rbr_block_size;
3406         }
3407
3408         return 0;
3409 }
3410
3411 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3412 {
3413         int index = rp->rbr_index;
3414
3415         rp->rbr_pending++;
3416         if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3417                 int err = niu_rbr_add_page(np, rp, mask, index);
3418
3419                 if (unlikely(err)) {
3420                         rp->rbr_pending--;
3421                         return;
3422                 }
3423
3424                 rp->rbr_index += rp->rbr_blocks_per_page;
3425                 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3426                 if (rp->rbr_index == rp->rbr_table_size)
3427                         rp->rbr_index = 0;
3428
3429                 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3430                         nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3431                         rp->rbr_pending = 0;
3432                 }
3433         }
3434 }
3435
3436 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3437 {
3438         unsigned int index = rp->rcr_index;
3439         int num_rcr = 0;
3440
3441         rp->rx_dropped++;
3442         while (1) {
3443                 struct page *page, **link;
3444                 u64 addr, val;
3445                 u32 rcr_size;
3446
3447                 num_rcr++;
3448
3449                 val = le64_to_cpup(&rp->rcr[index]);
3450                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3451                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3452                 page = niu_find_rxpage(rp, addr, &link);
3453
3454                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3455                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3456                 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3457                         *link = (struct page *) page->mapping;
3458                         np->ops->unmap_page(np->device, page->index,
3459                                             PAGE_SIZE, DMA_FROM_DEVICE);
3460                         page->index = 0;
3461                         page->mapping = NULL;
3462                         __free_page(page);
3463                         rp->rbr_refill_pending++;
3464                 }
3465
3466                 index = NEXT_RCR(rp, index);
3467                 if (!(val & RCR_ENTRY_MULTI))
3468                         break;
3469
3470         }
3471         rp->rcr_index = index;
3472
3473         return num_rcr;
3474 }
3475
3476 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3477                               struct rx_ring_info *rp)
3478 {
3479         unsigned int index = rp->rcr_index;
3480         struct sk_buff *skb;
3481         int len, num_rcr;
3482
3483         skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3484         if (unlikely(!skb))
3485                 return niu_rx_pkt_ignore(np, rp);
3486
3487         num_rcr = 0;
3488         while (1) {
3489                 struct page *page, **link;
3490                 u32 rcr_size, append_size;
3491                 u64 addr, val, off;
3492
3493                 num_rcr++;
3494
3495                 val = le64_to_cpup(&rp->rcr[index]);
3496
3497                 len = (val & RCR_ENTRY_L2_LEN) >>
3498                         RCR_ENTRY_L2_LEN_SHIFT;
3499                 len -= ETH_FCS_LEN;
3500
3501                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3502                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3503                 page = niu_find_rxpage(rp, addr, &link);
3504
3505                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3506                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3507
3508                 off = addr & ~PAGE_MASK;
3509                 append_size = rcr_size;
3510                 if (num_rcr == 1) {
3511                         int ptype;
3512
3513                         off += 2;
3514                         append_size -= 2;
3515
3516                         ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3517                         if ((ptype == RCR_PKT_TYPE_TCP ||
3518                              ptype == RCR_PKT_TYPE_UDP) &&
3519                             !(val & (RCR_ENTRY_NOPORT |
3520                                      RCR_ENTRY_ERROR)))
3521                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3522                         else
3523                                 skb->ip_summed = CHECKSUM_NONE;
3524                 }
3525                 if (!(val & RCR_ENTRY_MULTI))
3526                         append_size = len - skb->len;
3527
3528                 niu_rx_skb_append(skb, page, off, append_size);
3529                 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3530                         *link = (struct page *) page->mapping;
3531                         np->ops->unmap_page(np->device, page->index,
3532                                             PAGE_SIZE, DMA_FROM_DEVICE);
3533                         page->index = 0;
3534                         page->mapping = NULL;
3535                         rp->rbr_refill_pending++;
3536                 } else
3537                         get_page(page);
3538
3539                 index = NEXT_RCR(rp, index);
3540                 if (!(val & RCR_ENTRY_MULTI))
3541                         break;
3542
3543         }
3544         rp->rcr_index = index;
3545
3546         skb_reserve(skb, NET_IP_ALIGN);
3547         __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX));
3548
3549         rp->rx_packets++;
3550         rp->rx_bytes += skb->len;
3551
3552         skb->protocol = eth_type_trans(skb, np->dev);
3553         skb_record_rx_queue(skb, rp->rx_channel);
3554         napi_gro_receive(napi, skb);
3555
3556         return num_rcr;
3557 }
3558
3559 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3560 {
3561         int blocks_per_page = rp->rbr_blocks_per_page;
3562         int err, index = rp->rbr_index;
3563
3564         err = 0;
3565         while (index < (rp->rbr_table_size - blocks_per_page)) {
3566                 err = niu_rbr_add_page(np, rp, mask, index);
3567                 if (err)
3568                         break;
3569
3570                 index += blocks_per_page;
3571         }
3572
3573         rp->rbr_index = index;
3574         return err;
3575 }
3576
3577 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3578 {
3579         int i;
3580
3581         for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3582                 struct page *page;
3583
3584                 page = rp->rxhash[i];
3585                 while (page) {
3586                         struct page *next = (struct page *) page->mapping;
3587                         u64 base = page->index;
3588
3589                         np->ops->unmap_page(np->device, base, PAGE_SIZE,
3590                                             DMA_FROM_DEVICE);
3591                         page->index = 0;
3592                         page->mapping = NULL;
3593
3594                         __free_page(page);
3595
3596                         page = next;
3597                 }
3598         }
3599
3600         for (i = 0; i < rp->rbr_table_size; i++)
3601                 rp->rbr[i] = cpu_to_le32(0);
3602         rp->rbr_index = 0;
3603 }
3604
3605 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3606 {
3607         struct tx_buff_info *tb = &rp->tx_buffs[idx];
3608         struct sk_buff *skb = tb->skb;
3609         struct tx_pkt_hdr *tp;
3610         u64 tx_flags;
3611         int i, len;
3612
3613         tp = (struct tx_pkt_hdr *) skb->data;
3614         tx_flags = le64_to_cpup(&tp->flags);
3615
3616         rp->tx_packets++;
3617         rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3618                          ((tx_flags & TXHDR_PAD) / 2));
3619
3620         len = skb_headlen(skb);
3621         np->ops->unmap_single(np->device, tb->mapping,
3622                               len, DMA_TO_DEVICE);
3623
3624         if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3625                 rp->mark_pending--;
3626
3627         tb->skb = NULL;
3628         do {
3629                 idx = NEXT_TX(rp, idx);
3630                 len -= MAX_TX_DESC_LEN;
3631         } while (len > 0);
3632
3633         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3634                 tb = &rp->tx_buffs[idx];
3635                 BUG_ON(tb->skb != NULL);
3636                 np->ops->unmap_page(np->device, tb->mapping,
3637                                     skb_shinfo(skb)->frags[i].size,
3638                                     DMA_TO_DEVICE);
3639                 idx = NEXT_TX(rp, idx);
3640         }
3641
3642         dev_kfree_skb(skb);
3643
3644         return idx;
3645 }
3646
3647 #define NIU_TX_WAKEUP_THRESH(rp)                ((rp)->pending / 4)
3648
3649 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3650 {
3651         struct netdev_queue *txq;
3652         u16 pkt_cnt, tmp;
3653         int cons, index;
3654         u64 cs;
3655
3656         index = (rp - np->tx_rings);
3657         txq = netdev_get_tx_queue(np->dev, index);
3658
3659         cs = rp->tx_cs;
3660         if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3661                 goto out;
3662
3663         tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3664         pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3665                 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3666
3667         rp->last_pkt_cnt = tmp;
3668
3669         cons = rp->cons;
3670
3671         niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
3672                np->dev->name, pkt_cnt, cons);
3673
3674         while (pkt_cnt--)
3675                 cons = release_tx_packet(np, rp, cons);
3676
3677         rp->cons = cons;
3678         smp_mb();
3679
3680 out:
3681         if (unlikely(netif_tx_queue_stopped(txq) &&
3682                      (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3683                 __netif_tx_lock(txq, smp_processor_id());
3684                 if (netif_tx_queue_stopped(txq) &&
3685                     (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3686                         netif_tx_wake_queue(txq);
3687                 __netif_tx_unlock(txq);
3688         }
3689 }
3690
3691 static inline void niu_sync_rx_discard_stats(struct niu *np,
3692                                              struct rx_ring_info *rp,
3693                                              const int limit)
3694 {
3695         /* This elaborate scheme is needed for reading the RX discard
3696          * counters, as they are only 16-bit and can overflow quickly,
3697          * and because the overflow indication bit is not usable as
3698          * the counter value does not wrap, but remains at max value
3699          * 0xFFFF.
3700          *
3701          * In theory and in practice counters can be lost in between
3702          * reading nr64() and clearing the counter nw64().  For this
3703          * reason, the number of counter clearings nw64() is
3704          * limited/reduced though the limit parameter.
3705          */
3706         int rx_channel = rp->rx_channel;
3707         u32 misc, wred;
3708
3709         /* RXMISC (Receive Miscellaneous Discard Count), covers the
3710          * following discard events: IPP (Input Port Process),
3711          * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3712          * Block Ring) prefetch buffer is empty.
3713          */
3714         misc = nr64(RXMISC(rx_channel));
3715         if (unlikely((misc & RXMISC_COUNT) > limit)) {
3716                 nw64(RXMISC(rx_channel), 0);
3717                 rp->rx_errors += misc & RXMISC_COUNT;
3718
3719                 if (unlikely(misc & RXMISC_OFLOW))
3720                         dev_err(np->device, "rx-%d: Counter overflow "
3721                                 "RXMISC discard\n", rx_channel);
3722
3723                 niudbg(RX_ERR, "%s-rx-%d: MISC drop=%u over=%u\n",
3724                        np->dev->name, rx_channel, misc, misc-limit);
3725         }
3726
3727         /* WRED (Weighted Random Early Discard) by hardware */
3728         wred = nr64(RED_DIS_CNT(rx_channel));
3729         if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3730                 nw64(RED_DIS_CNT(rx_channel), 0);
3731                 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3732
3733                 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3734                         dev_err(np->device, "rx-%d: Counter overflow "
3735                                 "WRED discard\n", rx_channel);
3736
3737                 niudbg(RX_ERR, "%s-rx-%d: WRED drop=%u over=%u\n",
3738                        np->dev->name, rx_channel, wred, wred-limit);
3739         }
3740 }
3741
3742 static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3743                        struct rx_ring_info *rp, int budget)
3744 {
3745         int qlen, rcr_done = 0, work_done = 0;
3746         struct rxdma_mailbox *mbox = rp->mbox;
3747         u64 stat;
3748
3749 #if 1
3750         stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3751         qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3752 #else
3753         stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3754         qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3755 #endif
3756         mbox->rx_dma_ctl_stat = 0;
3757         mbox->rcrstat_a = 0;
3758
3759         niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
3760                np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen);
3761
3762         rcr_done = work_done = 0;
3763         qlen = min(qlen, budget);
3764         while (work_done < qlen) {
3765                 rcr_done += niu_process_rx_pkt(napi, np, rp);
3766                 work_done++;
3767         }
3768
3769         if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3770                 unsigned int i;
3771
3772                 for (i = 0; i < rp->rbr_refill_pending; i++)
3773                         niu_rbr_refill(np, rp, GFP_ATOMIC);
3774                 rp->rbr_refill_pending = 0;
3775         }
3776
3777         stat = (RX_DMA_CTL_STAT_MEX |
3778                 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3779                 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3780
3781         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3782
3783         /* Only sync discards stats when qlen indicate potential for drops */
3784         if (qlen > 10)
3785                 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3786
3787         return work_done;
3788 }
3789
3790 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3791 {
3792         u64 v0 = lp->v0;
3793         u32 tx_vec = (v0 >> 32);
3794         u32 rx_vec = (v0 & 0xffffffff);
3795         int i, work_done = 0;
3796
3797         niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n",
3798                np->dev->name, (unsigned long long) v0);
3799
3800         for (i = 0; i < np->num_tx_rings; i++) {
3801                 struct tx_ring_info *rp = &np->tx_rings[i];
3802                 if (tx_vec & (1 << rp->tx_channel))
3803                         niu_tx_work(np, rp);
3804                 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3805         }
3806
3807         for (i = 0; i < np->num_rx_rings; i++) {
3808                 struct rx_ring_info *rp = &np->rx_rings[i];
3809
3810                 if (rx_vec & (1 << rp->rx_channel)) {
3811                         int this_work_done;
3812
3813                         this_work_done = niu_rx_work(&lp->napi, np, rp,
3814                                                      budget);
3815
3816                         budget -= this_work_done;
3817                         work_done += this_work_done;
3818                 }
3819                 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3820         }
3821
3822         return work_done;
3823 }
3824
3825 static int niu_poll(struct napi_struct *napi, int budget)
3826 {
3827         struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3828         struct niu *np = lp->np;
3829         int work_done;
3830
3831         work_done = niu_poll_core(np, lp, budget);
3832
3833         if (work_done < budget) {
3834                 napi_complete(napi);
3835                 niu_ldg_rearm(np, lp, 1);
3836         }
3837         return work_done;
3838 }
3839
3840 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3841                                   u64 stat)
3842 {
3843         dev_err(np->device, PFX "%s: RX channel %u errors ( ",
3844                 np->dev->name, rp->rx_channel);
3845
3846         if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3847                 printk("RBR_TMOUT ");
3848         if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3849                 printk("RSP_CNT ");
3850         if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3851                 printk("BYTE_EN_BUS ");
3852         if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3853                 printk("RSP_DAT ");
3854         if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3855                 printk("RCR_ACK ");
3856         if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3857                 printk("RCR_SHA_PAR ");
3858         if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3859                 printk("RBR_PRE_PAR ");
3860         if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3861                 printk("CONFIG ");
3862         if (stat & RX_DMA_CTL_STAT_RCRINCON)
3863                 printk("RCRINCON ");
3864         if (stat & RX_DMA_CTL_STAT_RCRFULL)
3865                 printk("RCRFULL ");
3866         if (stat & RX_DMA_CTL_STAT_RBRFULL)
3867                 printk("RBRFULL ");
3868         if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3869                 printk("RBRLOGPAGE ");
3870         if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3871                 printk("CFIGLOGPAGE ");
3872         if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3873                 printk("DC_FIDO ");
3874
3875         printk(")\n");
3876 }
3877
3878 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3879 {
3880         u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3881         int err = 0;
3882
3883
3884         if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3885                     RX_DMA_CTL_STAT_PORT_FATAL))
3886                 err = -EINVAL;
3887
3888         if (err) {
3889                 dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n",
3890                         np->dev->name, rp->rx_channel,
3891                         (unsigned long long) stat);
3892
3893                 niu_log_rxchan_errors(np, rp, stat);
3894         }
3895
3896         nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3897              stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3898
3899         return err;
3900 }
3901
3902 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3903                                   u64 cs)
3904 {
3905         dev_err(np->device, PFX "%s: TX channel %u errors ( ",
3906                 np->dev->name, rp->tx_channel);
3907
3908         if (cs & TX_CS_MBOX_ERR)
3909                 printk("MBOX ");
3910         if (cs & TX_CS_PKT_SIZE_ERR)
3911                 printk("PKT_SIZE ");
3912         if (cs & TX_CS_TX_RING_OFLOW)
3913                 printk("TX_RING_OFLOW ");
3914         if (cs & TX_CS_PREF_BUF_PAR_ERR)
3915                 printk("PREF_BUF_PAR ");
3916         if (cs & TX_CS_NACK_PREF)
3917                 printk("NACK_PREF ");
3918         if (cs & TX_CS_NACK_PKT_RD)
3919                 printk("NACK_PKT_RD ");
3920         if (cs & TX_CS_CONF_PART_ERR)
3921                 printk("CONF_PART ");
3922         if (cs & TX_CS_PKT_PRT_ERR)
3923                 printk("PKT_PTR ");
3924
3925         printk(")\n");
3926 }
3927
3928 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3929 {
3930         u64 cs, logh, logl;
3931
3932         cs = nr64(TX_CS(rp->tx_channel));
3933         logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3934         logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3935
3936         dev_err(np->device, PFX "%s: TX channel %u error, "
3937                 "cs[%llx] logh[%llx] logl[%llx]\n",
3938                 np->dev->name, rp->tx_channel,
3939                 (unsigned long long) cs,
3940                 (unsigned long long) logh,
3941                 (unsigned long long) logl);
3942
3943         niu_log_txchan_errors(np, rp, cs);
3944
3945         return -ENODEV;
3946 }
3947
3948 static int niu_mif_interrupt(struct niu *np)
3949 {
3950         u64 mif_status = nr64(MIF_STATUS);
3951         int phy_mdint = 0;
3952
3953         if (np->flags & NIU_FLAGS_XMAC) {
3954                 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3955
3956                 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3957                         phy_mdint = 1;
3958         }
3959
3960         dev_err(np->device, PFX "%s: MIF interrupt, "
3961                 "stat[%llx] phy_mdint(%d)\n",
3962                 np->dev->name, (unsigned long long) mif_status, phy_mdint);
3963
3964         return -ENODEV;
3965 }
3966
3967 static void niu_xmac_interrupt(struct niu *np)
3968 {
3969         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3970         u64 val;
3971
3972         val = nr64_mac(XTXMAC_STATUS);
3973         if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3974                 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3975         if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3976                 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3977         if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3978                 mp->tx_fifo_errors++;
3979         if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3980                 mp->tx_overflow_errors++;
3981         if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3982                 mp->tx_max_pkt_size_errors++;
3983         if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3984                 mp->tx_underflow_errors++;
3985
3986         val = nr64_mac(XRXMAC_STATUS);
3987         if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3988                 mp->rx_local_faults++;
3989         if (val & XRXMAC_STATUS_RFLT_DET)
3990                 mp->rx_remote_faults++;
3991         if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3992                 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3993         if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3994                 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3995         if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3996                 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3997         if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3998                 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3999         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
4000                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
4001         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
4002                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
4003         if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
4004                 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
4005         if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
4006                 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
4007         if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
4008                 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
4009         if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
4010                 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
4011         if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
4012                 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
4013         if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
4014                 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
4015         if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
4016                 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
4017         if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP)
4018                 mp->rx_octets += RXMAC_BT_CNT_COUNT;
4019         if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
4020                 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
4021         if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
4022                 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
4023         if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
4024                 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
4025         if (val & XRXMAC_STATUS_RXUFLOW)
4026                 mp->rx_underflows++;
4027         if (val & XRXMAC_STATUS_RXOFLOW)
4028                 mp->rx_overflows++;
4029
4030         val = nr64_mac(XMAC_FC_STAT);
4031         if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
4032                 mp->pause_off_state++;
4033         if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
4034                 mp->pause_on_state++;
4035         if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
4036                 mp->pause_received++;
4037 }
4038
4039 static void niu_bmac_interrupt(struct niu *np)
4040 {
4041         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4042         u64 val;
4043
4044         val = nr64_mac(BTXMAC_STATUS);
4045         if (val & BTXMAC_STATUS_UNDERRUN)
4046                 mp->tx_underflow_errors++;
4047         if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4048                 mp->tx_max_pkt_size_errors++;
4049         if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4050                 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4051         if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4052                 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4053
4054         val = nr64_mac(BRXMAC_STATUS);
4055         if (val & BRXMAC_STATUS_OVERFLOW)
4056                 mp->rx_overflows++;
4057         if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4058                 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4059         if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4060                 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4061         if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4062                 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4063         if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4064                 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4065
4066         val = nr64_mac(BMAC_CTRL_STATUS);
4067         if (val & BMAC_CTRL_STATUS_NOPAUSE)
4068                 mp->pause_off_state++;
4069         if (val & BMAC_CTRL_STATUS_PAUSE)
4070                 mp->pause_on_state++;
4071         if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4072                 mp->pause_received++;
4073 }
4074
4075 static int niu_mac_interrupt(struct niu *np)
4076 {
4077         if (np->flags & NIU_FLAGS_XMAC)
4078                 niu_xmac_interrupt(np);
4079         else
4080                 niu_bmac_interrupt(np);
4081
4082         return 0;
4083 }
4084
4085 static void niu_log_device_error(struct niu *np, u64 stat)
4086 {
4087         dev_err(np->device, PFX "%s: Core device errors ( ",
4088                 np->dev->name);
4089
4090         if (stat & SYS_ERR_MASK_META2)
4091                 printk("META2 ");
4092         if (stat & SYS_ERR_MASK_META1)
4093                 printk("META1 ");
4094         if (stat & SYS_ERR_MASK_PEU)
4095                 printk("PEU ");
4096         if (stat & SYS_ERR_MASK_TXC)
4097                 printk("TXC ");
4098         if (stat & SYS_ERR_MASK_RDMC)
4099                 printk("RDMC ");
4100         if (stat & SYS_ERR_MASK_TDMC)
4101                 printk("TDMC ");
4102         if (stat & SYS_ERR_MASK_ZCP)
4103                 printk("ZCP ");
4104         if (stat & SYS_ERR_MASK_FFLP)
4105                 printk("FFLP ");
4106         if (stat & SYS_ERR_MASK_IPP)
4107                 printk("IPP ");
4108         if (stat & SYS_ERR_MASK_MAC)
4109                 printk("MAC ");
4110         if (stat & SYS_ERR_MASK_SMX)
4111                 printk("SMX ");
4112
4113         printk(")\n");
4114 }
4115
4116 static int niu_device_error(struct niu *np)
4117 {
4118         u64 stat = nr64(SYS_ERR_STAT);
4119
4120         dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n",
4121                 np->dev->name, (unsigned long long) stat);
4122
4123         niu_log_device_error(np, stat);
4124
4125         return -ENODEV;
4126 }
4127
4128 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4129                               u64 v0, u64 v1, u64 v2)
4130 {
4131
4132         int i, err = 0;
4133
4134         lp->v0 = v0;
4135         lp->v1 = v1;
4136         lp->v2 = v2;
4137
4138         if (v1 & 0x00000000ffffffffULL) {
4139                 u32 rx_vec = (v1 & 0xffffffff);
4140
4141                 for (i = 0; i < np->num_rx_rings; i++) {
4142                         struct rx_ring_info *rp = &np->rx_rings[i];
4143
4144                         if (rx_vec & (1 << rp->rx_channel)) {
4145                                 int r = niu_rx_error(np, rp);
4146                                 if (r) {
4147                                         err = r;
4148                                 } else {
4149                                         if (!v0)
4150                                                 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4151                                                      RX_DMA_CTL_STAT_MEX);
4152                                 }
4153                         }
4154                 }
4155         }
4156         if (v1 & 0x7fffffff00000000ULL) {
4157                 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4158
4159                 for (i = 0; i < np->num_tx_rings; i++) {
4160                         struct tx_ring_info *rp = &np->tx_rings[i];
4161
4162                         if (tx_vec & (1 << rp->tx_channel)) {
4163                                 int r = niu_tx_error(np, rp);
4164                                 if (r)
4165                                         err = r;
4166                         }
4167                 }
4168         }
4169         if ((v0 | v1) & 0x8000000000000000ULL) {
4170                 int r = niu_mif_interrupt(np);
4171                 if (r)
4172                         err = r;
4173         }
4174         if (v2) {
4175                 if (v2 & 0x01ef) {
4176                         int r = niu_mac_interrupt(np);
4177                         if (r)
4178                                 err = r;
4179                 }
4180                 if (v2 & 0x0210) {
4181                         int r = niu_device_error(np);
4182                         if (r)
4183                                 err = r;
4184                 }
4185         }
4186
4187         if (err)
4188                 niu_enable_interrupts(np, 0);
4189
4190         return err;
4191 }
4192
4193 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4194                             int ldn)
4195 {
4196         struct rxdma_mailbox *mbox = rp->mbox;
4197         u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4198
4199         stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4200                       RX_DMA_CTL_STAT_RCRTO);
4201         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4202
4203         niudbg(INTR, "%s: rxchan_intr stat[%llx]\n",
4204                np->dev->name, (unsigned long long) stat);
4205 }
4206
4207 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4208                             int ldn)
4209 {
4210         rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4211
4212         niudbg(INTR, "%s: txchan_intr cs[%llx]\n",
4213                np->dev->name, (unsigned long long) rp->tx_cs);
4214 }
4215
4216 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4217 {
4218         struct niu_parent *parent = np->parent;
4219         u32 rx_vec, tx_vec;
4220         int i;
4221
4222         tx_vec = (v0 >> 32);
4223         rx_vec = (v0 & 0xffffffff);
4224
4225         for (i = 0; i < np->num_rx_rings; i++) {
4226                 struct rx_ring_info *rp = &np->rx_rings[i];
4227                 int ldn = LDN_RXDMA(rp->rx_channel);
4228
4229                 if (parent->ldg_map[ldn] != ldg)
4230                         continue;
4231
4232                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4233                 if (rx_vec & (1 << rp->rx_channel))
4234                         niu_rxchan_intr(np, rp, ldn);
4235         }
4236
4237         for (i = 0; i < np->num_tx_rings; i++) {
4238                 struct tx_ring_info *rp = &np->tx_rings[i];
4239                 int ldn = LDN_TXDMA(rp->tx_channel);
4240
4241                 if (parent->ldg_map[ldn] != ldg)
4242                         continue;
4243
4244                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4245                 if (tx_vec & (1 << rp->tx_channel))
4246                         niu_txchan_intr(np, rp, ldn);
4247         }
4248 }
4249
4250 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4251                               u64 v0, u64 v1, u64 v2)
4252 {
4253         if (likely(napi_schedule_prep(&lp->napi))) {
4254                 lp->v0 = v0;
4255                 lp->v1 = v1;
4256                 lp->v2 = v2;
4257                 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4258                 __napi_schedule(&lp->napi);
4259         }
4260 }
4261
4262 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4263 {
4264         struct niu_ldg *lp = dev_id;
4265         struct niu *np = lp->np;
4266         int ldg = lp->ldg_num;
4267         unsigned long flags;
4268         u64 v0, v1, v2;
4269
4270         if (netif_msg_intr(np))
4271                 printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ",
4272                        lp, ldg);
4273
4274         spin_lock_irqsave(&np->lock, flags);
4275
4276         v0 = nr64(LDSV0(ldg));
4277         v1 = nr64(LDSV1(ldg));
4278         v2 = nr64(LDSV2(ldg));
4279
4280         if (netif_msg_intr(np))
4281                 printk("v0[%llx] v1[%llx] v2[%llx]\n",
4282                        (unsigned long long) v0,
4283                        (unsigned long long) v1,
4284                        (unsigned long long) v2);
4285
4286         if (unlikely(!v0 && !v1 && !v2)) {
4287                 spin_unlock_irqrestore(&np->lock, flags);
4288                 return IRQ_NONE;
4289         }
4290
4291         if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4292                 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4293                 if (err)
4294                         goto out;
4295         }
4296         if (likely(v0 & ~((u64)1 << LDN_MIF)))
4297                 niu_schedule_napi(np, lp, v0, v1, v2);
4298         else
4299                 niu_ldg_rearm(np, lp, 1);
4300 out:
4301         spin_unlock_irqrestore(&np->lock, flags);
4302
4303         return IRQ_HANDLED;
4304 }
4305
4306 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4307 {
4308         if (rp->mbox) {
4309                 np->ops->free_coherent(np->device,
4310                                        sizeof(struct rxdma_mailbox),
4311                                        rp->mbox, rp->mbox_dma);
4312                 rp->mbox = NULL;
4313         }
4314         if (rp->rcr) {
4315                 np->ops->free_coherent(np->device,
4316                                        MAX_RCR_RING_SIZE * sizeof(__le64),
4317                                        rp->rcr, rp->rcr_dma);
4318                 rp->rcr = NULL;
4319                 rp->rcr_table_size = 0;
4320                 rp->rcr_index = 0;
4321         }
4322         if (rp->rbr) {
4323                 niu_rbr_free(np, rp);
4324
4325                 np->ops->free_coherent(np->device,
4326                                        MAX_RBR_RING_SIZE * sizeof(__le32),
4327                                        rp->rbr, rp->rbr_dma);
4328                 rp->rbr = NULL;
4329                 rp->rbr_table_size = 0;
4330                 rp->rbr_index = 0;
4331         }
4332         kfree(rp->rxhash);
4333         rp->rxhash = NULL;
4334 }
4335
4336 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4337 {
4338         if (rp->mbox) {
4339                 np->ops->free_coherent(np->device,
4340                                        sizeof(struct txdma_mailbox),
4341                                        rp->mbox, rp->mbox_dma);
4342                 rp->mbox = NULL;
4343         }
4344         if (rp->descr) {
4345                 int i;
4346
4347                 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4348                         if (rp->tx_buffs[i].skb)
4349                                 (void) release_tx_packet(np, rp, i);
4350                 }
4351
4352                 np->ops->free_coherent(np->device,
4353                                        MAX_TX_RING_SIZE * sizeof(__le64),
4354                                        rp->descr, rp->descr_dma);
4355                 rp->descr = NULL;
4356                 rp->pending = 0;
4357                 rp->prod = 0;
4358                 rp->cons = 0;
4359                 rp->wrap_bit = 0;
4360         }
4361 }
4362
4363 static void niu_free_channels(struct niu *np)
4364 {
4365         int i;
4366
4367         if (np->rx_rings) {
4368                 for (i = 0; i < np->num_rx_rings; i++) {
4369                         struct rx_ring_info *rp = &np->rx_rings[i];
4370
4371                         niu_free_rx_ring_info(np, rp);
4372                 }
4373                 kfree(np->rx_rings);
4374                 np->rx_rings = NULL;
4375                 np->num_rx_rings = 0;
4376         }
4377
4378         if (np->tx_rings) {
4379                 for (i = 0; i < np->num_tx_rings; i++) {
4380                         struct tx_ring_info *rp = &np->tx_rings[i];
4381
4382                         niu_free_tx_ring_info(np, rp);
4383                 }
4384                 kfree(np->tx_rings);
4385                 np->tx_rings = NULL;
4386                 np->num_tx_rings = 0;
4387         }
4388 }
4389
4390 static int niu_alloc_rx_ring_info(struct niu *np,
4391                                   struct rx_ring_info *rp)
4392 {
4393         BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4394
4395         rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4396                              GFP_KERNEL);
4397         if (!rp->rxhash)
4398                 return -ENOMEM;
4399
4400         rp->mbox = np->ops->alloc_coherent(np->device,
4401                                            sizeof(struct rxdma_mailbox),
4402                                            &rp->mbox_dma, GFP_KERNEL);
4403         if (!rp->mbox)
4404                 return -ENOMEM;
4405         if ((unsigned long)rp->mbox & (64UL - 1)) {
4406                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4407                         "RXDMA mailbox %p\n", np->dev->name, rp->mbox);
4408                 return -EINVAL;
4409         }
4410
4411         rp->rcr = np->ops->alloc_coherent(np->device,
4412                                           MAX_RCR_RING_SIZE * sizeof(__le64),
4413                                           &rp->rcr_dma, GFP_KERNEL);
4414         if (!rp->rcr)
4415                 return -ENOMEM;
4416         if ((unsigned long)rp->rcr & (64UL - 1)) {
4417                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4418                         "RXDMA RCR table %p\n", np->dev->name, rp->rcr);
4419                 return -EINVAL;
4420         }
4421         rp->rcr_table_size = MAX_RCR_RING_SIZE;
4422         rp->rcr_index = 0;
4423
4424         rp->rbr = np->ops->alloc_coherent(np->device,
4425                                           MAX_RBR_RING_SIZE * sizeof(__le32),
4426                                           &rp->rbr_dma, GFP_KERNEL);
4427         if (!rp->rbr)
4428                 return -ENOMEM;
4429         if ((unsigned long)rp->rbr & (64UL - 1)) {
4430                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4431                         "RXDMA RBR table %p\n", np->dev->name, rp->rbr);
4432                 return -EINVAL;
4433         }
4434         rp->rbr_table_size = MAX_RBR_RING_SIZE;
4435         rp->rbr_index = 0;
4436         rp->rbr_pending = 0;
4437
4438         return 0;
4439 }
4440
4441 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4442 {
4443         int mtu = np->dev->mtu;
4444
4445         /* These values are recommended by the HW designers for fair
4446          * utilization of DRR amongst the rings.
4447          */
4448         rp->max_burst = mtu + 32;
4449         if (rp->max_burst > 4096)
4450                 rp->max_burst = 4096;
4451 }
4452
4453 static int niu_alloc_tx_ring_info(struct niu *np,
4454                                   struct tx_ring_info *rp)
4455 {
4456         BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4457
4458         rp->mbox = np->ops->alloc_coherent(np->device,
4459                                            sizeof(struct txdma_mailbox),
4460                                            &rp->mbox_dma, GFP_KERNEL);
4461         if (!rp->mbox)
4462                 return -ENOMEM;
4463         if ((unsigned long)rp->mbox & (64UL - 1)) {
4464                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4465                         "TXDMA mailbox %p\n", np->dev->name, rp->mbox);
4466                 return -EINVAL;
4467         }
4468
4469         rp->descr = np->ops->alloc_coherent(np->device,
4470                                             MAX_TX_RING_SIZE * sizeof(__le64),
4471                                             &rp->descr_dma, GFP_KERNEL);
4472         if (!rp->descr)
4473                 return -ENOMEM;
4474         if ((unsigned long)rp->descr & (64UL - 1)) {
4475                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4476                         "TXDMA descr table %p\n", np->dev->name, rp->descr);
4477                 return -EINVAL;
4478         }
4479
4480         rp->pending = MAX_TX_RING_SIZE;
4481         rp->prod = 0;
4482         rp->cons = 0;
4483         rp->wrap_bit = 0;
4484
4485         /* XXX make these configurable... XXX */
4486         rp->mark_freq = rp->pending / 4;
4487
4488         niu_set_max_burst(np, rp);
4489
4490         return 0;
4491 }
4492
4493 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4494 {
4495         u16 bss;
4496
4497         bss = min(PAGE_SHIFT, 15);
4498
4499         rp->rbr_block_size = 1 << bss;
4500         rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4501
4502         rp->rbr_sizes[0] = 256;
4503         rp->rbr_sizes[1] = 1024;
4504         if (np->dev->mtu > ETH_DATA_LEN) {
4505                 switch (PAGE_SIZE) {
4506                 case 4 * 1024:
4507                         rp->rbr_sizes[2] = 4096;
4508                         break;
4509
4510                 default:
4511                         rp->rbr_sizes[2] = 8192;
4512                         break;
4513                 }
4514         } else {
4515                 rp->rbr_sizes[2] = 2048;
4516         }
4517         rp->rbr_sizes[3] = rp->rbr_block_size;
4518 }
4519
4520 static int niu_alloc_channels(struct niu *np)
4521 {
4522         struct niu_parent *parent = np->parent;
4523         int first_rx_channel, first_tx_channel;
4524         int i, port, err;
4525
4526         port = np->port;
4527         first_rx_channel = first_tx_channel = 0;
4528         for (i = 0; i < port; i++) {
4529                 first_rx_channel += parent->rxchan_per_port[i];
4530                 first_tx_channel += parent->txchan_per_port[i];
4531         }
4532
4533         np->num_rx_rings = parent->rxchan_per_port[port];
4534         np->num_tx_rings = parent->txchan_per_port[port];
4535
4536         np->dev->real_num_tx_queues = np->num_tx_rings;
4537
4538         np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4539                                GFP_KERNEL);
4540         err = -ENOMEM;
4541         if (!np->rx_rings)
4542                 goto out_err;
4543
4544         for (i = 0; i < np->num_rx_rings; i++) {
4545                 struct rx_ring_info *rp = &np->rx_rings[i];
4546
4547                 rp->np = np;
4548                 rp->rx_channel = first_rx_channel + i;
4549
4550                 err = niu_alloc_rx_ring_info(np, rp);
4551                 if (err)
4552                         goto out_err;
4553
4554                 niu_size_rbr(np, rp);
4555
4556                 /* XXX better defaults, configurable, etc... XXX */
4557                 rp->nonsyn_window = 64;
4558                 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4559                 rp->syn_window = 64;
4560                 rp->syn_threshold = rp->rcr_table_size - 64;
4561                 rp->rcr_pkt_threshold = 16;
4562                 rp->rcr_timeout = 8;
4563                 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4564                 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4565                         rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4566
4567                 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4568                 if (err)
4569                         return err;
4570         }
4571
4572         np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
4573                                GFP_KERNEL);
4574         err = -ENOMEM;
4575         if (!np->tx_rings)
4576                 goto out_err;
4577
4578         for (i = 0; i < np->num_tx_rings; i++) {
4579                 struct tx_ring_info *rp = &np->tx_rings[i];
4580
4581                 rp->np = np;
4582                 rp->tx_channel = first_tx_channel + i;
4583
4584                 err = niu_alloc_tx_ring_info(np, rp);
4585                 if (err)
4586                         goto out_err;
4587         }
4588
4589         return 0;
4590
4591 out_err:
4592         niu_free_channels(np);
4593         return err;
4594 }
4595
4596 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4597 {
4598         int limit = 1000;
4599
4600         while (--limit > 0) {
4601                 u64 val = nr64(TX_CS(channel));
4602                 if (val & TX_CS_SNG_STATE)
4603                         return 0;
4604         }
4605         return -ENODEV;
4606 }
4607
4608 static int niu_tx_channel_stop(struct niu *np, int channel)
4609 {
4610         u64 val = nr64(TX_CS(channel));
4611
4612         val |= TX_CS_STOP_N_GO;
4613         nw64(TX_CS(channel), val);
4614
4615         return niu_tx_cs_sng_poll(np, channel);
4616 }
4617
4618 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4619 {
4620         int limit = 1000;
4621
4622         while (--limit > 0) {
4623                 u64 val = nr64(TX_CS(channel));
4624                 if (!(val & TX_CS_RST))
4625                         return 0;
4626         }
4627         return -ENODEV;
4628 }
4629
4630 static int niu_tx_channel_reset(struct niu *np, int channel)
4631 {
4632         u64 val = nr64(TX_CS(channel));
4633         int err;
4634
4635         val |= TX_CS_RST;
4636         nw64(TX_CS(channel), val);
4637
4638         err = niu_tx_cs_reset_poll(np, channel);
4639         if (!err)
4640                 nw64(TX_RING_KICK(channel), 0);
4641
4642         return err;
4643 }
4644
4645 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4646 {
4647         u64 val;
4648
4649         nw64(TX_LOG_MASK1(channel), 0);
4650         nw64(TX_LOG_VAL1(channel), 0);
4651         nw64(TX_LOG_MASK2(channel), 0);
4652         nw64(TX_LOG_VAL2(channel), 0);
4653         nw64(TX_LOG_PAGE_RELO1(channel), 0);
4654         nw64(TX_LOG_PAGE_RELO2(channel), 0);
4655         nw64(TX_LOG_PAGE_HDL(channel), 0);
4656
4657         val  = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4658         val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4659         nw64(TX_LOG_PAGE_VLD(channel), val);
4660
4661         /* XXX TXDMA 32bit mode? XXX */
4662
4663         return 0;
4664 }
4665
4666 static void niu_txc_enable_port(struct niu *np, int on)
4667 {
4668         unsigned long flags;
4669         u64 val, mask;
4670
4671         niu_lock_parent(np, flags);
4672         val = nr64(TXC_CONTROL);
4673         mask = (u64)1 << np->port;
4674         if (on) {
4675                 val |= TXC_CONTROL_ENABLE | mask;
4676         } else {
4677                 val &= ~mask;
4678                 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4679                         val &= ~TXC_CONTROL_ENABLE;
4680         }
4681         nw64(TXC_CONTROL, val);
4682         niu_unlock_parent(np, flags);
4683 }
4684
4685 static void niu_txc_set_imask(struct niu *np, u64 imask)
4686 {
4687         unsigned long flags;
4688         u64 val;
4689
4690         niu_lock_parent(np, flags);
4691         val = nr64(TXC_INT_MASK);
4692         val &= ~TXC_INT_MASK_VAL(np->port);
4693         val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4694         niu_unlock_parent(np, flags);
4695 }
4696
4697 static void niu_txc_port_dma_enable(struct niu *np, int on)
4698 {
4699         u64 val = 0;
4700
4701         if (on) {
4702                 int i;
4703
4704                 for (i = 0; i < np->num_tx_rings; i++)
4705                         val |= (1 << np->tx_rings[i].tx_channel);
4706         }
4707         nw64(TXC_PORT_DMA(np->port), val);
4708 }
4709
4710 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4711 {
4712         int err, channel = rp->tx_channel;
4713         u64 val, ring_len;
4714
4715         err = niu_tx_channel_stop(np, channel);
4716         if (err)
4717                 return err;
4718
4719         err = niu_tx_channel_reset(np, channel);
4720         if (err)
4721                 return err;
4722
4723         err = niu_tx_channel_lpage_init(np, channel);
4724         if (err)
4725                 return err;
4726
4727         nw64(TXC_DMA_MAX(channel), rp->max_burst);
4728         nw64(TX_ENT_MSK(channel), 0);
4729
4730         if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4731                               TX_RNG_CFIG_STADDR)) {
4732                 dev_err(np->device, PFX "%s: TX ring channel %d "
4733                         "DMA addr (%llx) is not aligned.\n",
4734                         np->dev->name, channel,
4735                         (unsigned long long) rp->descr_dma);
4736                 return -EINVAL;
4737         }
4738
4739         /* The length field in TX_RNG_CFIG is measured in 64-byte
4740          * blocks.  rp->pending is the number of TX descriptors in
4741          * our ring, 8 bytes each, thus we divide by 8 bytes more
4742          * to get the proper value the chip wants.
4743          */
4744         ring_len = (rp->pending / 8);
4745
4746         val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4747                rp->descr_dma);
4748         nw64(TX_RNG_CFIG(channel), val);
4749
4750         if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4751             ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4752                 dev_err(np->device, PFX "%s: TX ring channel %d "
4753                         "MBOX addr (%llx) is has illegal bits.\n",
4754                         np->dev->name, channel,
4755                         (unsigned long long) rp->mbox_dma);
4756                 return -EINVAL;
4757         }
4758         nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4759         nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4760
4761         nw64(TX_CS(channel), 0);
4762
4763         rp->last_pkt_cnt = 0;
4764
4765         return 0;
4766 }
4767
4768 static void niu_init_rdc_groups(struct niu *np)
4769 {
4770         struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4771         int i, first_table_num = tp->first_table_num;
4772
4773         for (i = 0; i < tp->num_tables; i++) {
4774                 struct rdc_table *tbl = &tp->tables[i];
4775                 int this_table = first_table_num + i;
4776                 int slot;
4777
4778                 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4779                         nw64(RDC_TBL(this_table, slot),
4780                              tbl->rxdma_channel[slot]);
4781         }
4782
4783         nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4784 }
4785
4786 static void niu_init_drr_weight(struct niu *np)
4787 {
4788         int type = phy_decode(np->parent->port_phy, np->port);
4789         u64 val;
4790
4791         switch (type) {
4792         case PORT_TYPE_10G:
4793                 val = PT_DRR_WEIGHT_DEFAULT_10G;
4794                 break;
4795
4796         case PORT_TYPE_1G:
4797         default:
4798                 val = PT_DRR_WEIGHT_DEFAULT_1G;
4799                 break;
4800         }
4801         nw64(PT_DRR_WT(np->port), val);
4802 }
4803
4804 static int niu_init_hostinfo(struct niu *np)
4805 {
4806         struct niu_parent *parent = np->parent;
4807         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4808         int i, err, num_alt = niu_num_alt_addr(np);
4809         int first_rdc_table = tp->first_table_num;
4810
4811         err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4812         if (err)
4813                 return err;
4814
4815         err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4816         if (err)
4817                 return err;
4818
4819         for (i = 0; i < num_alt; i++) {
4820                 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4821                 if (err)
4822                         return err;
4823         }
4824
4825         return 0;
4826 }
4827
4828 static int niu_rx_channel_reset(struct niu *np, int channel)
4829 {
4830         return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4831                                       RXDMA_CFIG1_RST, 1000, 10,
4832                                       "RXDMA_CFIG1");
4833 }
4834
4835 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4836 {
4837         u64 val;
4838
4839         nw64(RX_LOG_MASK1(channel), 0);
4840         nw64(RX_LOG_VAL1(channel), 0);
4841         nw64(RX_LOG_MASK2(channel), 0);
4842         nw64(RX_LOG_VAL2(channel), 0);
4843         nw64(RX_LOG_PAGE_RELO1(channel), 0);
4844         nw64(RX_LOG_PAGE_RELO2(channel), 0);
4845         nw64(RX_LOG_PAGE_HDL(channel), 0);
4846
4847         val  = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4848         val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4849         nw64(RX_LOG_PAGE_VLD(channel), val);
4850
4851         return 0;
4852 }
4853
4854 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4855 {
4856         u64 val;
4857
4858         val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4859                ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4860                ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4861                ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4862         nw64(RDC_RED_PARA(rp->rx_channel), val);
4863 }
4864
4865 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4866 {
4867         u64 val = 0;
4868
4869         *ret = 0;
4870         switch (rp->rbr_block_size) {
4871         case 4 * 1024:
4872                 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4873                 break;
4874         case 8 * 1024:
4875                 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4876                 break;
4877         case 16 * 1024:
4878                 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4879                 break;
4880         case 32 * 1024:
4881                 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4882                 break;
4883         default:
4884                 return -EINVAL;
4885         }
4886         val |= RBR_CFIG_B_VLD2;
4887         switch (rp->rbr_sizes[2]) {
4888         case 2 * 1024:
4889                 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4890                 break;
4891         case 4 * 1024:
4892                 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4893                 break;
4894         case 8 * 1024:
4895                 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4896                 break;
4897         case 16 * 1024:
4898                 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4899                 break;
4900
4901         default:
4902                 return -EINVAL;
4903         }
4904         val |= RBR_CFIG_B_VLD1;
4905         switch (rp->rbr_sizes[1]) {
4906         case 1 * 1024:
4907                 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4908                 break;
4909         case 2 * 1024:
4910                 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4911                 break;
4912         case 4 * 1024:
4913                 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4914                 break;
4915         case 8 * 1024:
4916                 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4917                 break;
4918
4919         default:
4920                 return -EINVAL;
4921         }
4922         val |= RBR_CFIG_B_VLD0;
4923         switch (rp->rbr_sizes[0]) {
4924         case 256:
4925                 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4926                 break;
4927         case 512:
4928                 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4929                 break;
4930         case 1 * 1024:
4931                 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4932                 break;
4933         case 2 * 1024:
4934                 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4935                 break;
4936
4937         default:
4938                 return -EINVAL;
4939         }
4940
4941         *ret = val;
4942         return 0;
4943 }
4944
4945 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4946 {
4947         u64 val = nr64(RXDMA_CFIG1(channel));
4948         int limit;
4949
4950         if (on)
4951                 val |= RXDMA_CFIG1_EN;
4952         else
4953                 val &= ~RXDMA_CFIG1_EN;
4954         nw64(RXDMA_CFIG1(channel), val);
4955
4956         limit = 1000;
4957         while (--limit > 0) {
4958                 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4959                         break;
4960                 udelay(10);
4961         }
4962         if (limit <= 0)
4963                 return -ENODEV;
4964         return 0;
4965 }
4966
4967 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4968 {
4969         int err, channel = rp->rx_channel;
4970         u64 val;
4971
4972         err = niu_rx_channel_reset(np, channel);
4973         if (err)
4974                 return err;
4975
4976         err = niu_rx_channel_lpage_init(np, channel);
4977         if (err)
4978                 return err;
4979
4980         niu_rx_channel_wred_init(np, rp);
4981
4982         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4983         nw64(RX_DMA_CTL_STAT(channel),
4984              (RX_DMA_CTL_STAT_MEX |
4985               RX_DMA_CTL_STAT_RCRTHRES |
4986               RX_DMA_CTL_STAT_RCRTO |
4987               RX_DMA_CTL_STAT_RBR_EMPTY));
4988         nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4989         nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
4990         nw64(RBR_CFIG_A(channel),
4991              ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4992              (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4993         err = niu_compute_rbr_cfig_b(rp, &val);
4994         if (err)
4995                 return err;
4996         nw64(RBR_CFIG_B(channel), val);
4997         nw64(RCRCFIG_A(channel),
4998              ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4999              (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
5000         nw64(RCRCFIG_B(channel),
5001              ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
5002              RCRCFIG_B_ENTOUT |
5003              ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
5004
5005         err = niu_enable_rx_channel(np, channel, 1);
5006         if (err)
5007                 return err;
5008
5009         nw64(RBR_KICK(channel), rp->rbr_index);
5010
5011         val = nr64(RX_DMA_CTL_STAT(channel));
5012         val |= RX_DMA_CTL_STAT_RBR_EMPTY;
5013         nw64(RX_DMA_CTL_STAT(channel), val);
5014
5015         return 0;
5016 }
5017
5018 static int niu_init_rx_channels(struct niu *np)
5019 {
5020         unsigned long flags;
5021         u64 seed = jiffies_64;
5022         int err, i;
5023
5024         niu_lock_parent(np, flags);
5025         nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
5026         nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
5027         niu_unlock_parent(np, flags);
5028
5029         /* XXX RXDMA 32bit mode? XXX */
5030
5031         niu_init_rdc_groups(np);
5032         niu_init_drr_weight(np);
5033
5034         err = niu_init_hostinfo(np);
5035         if (err)
5036                 return err;
5037
5038         for (i = 0; i < np->num_rx_rings; i++) {
5039                 struct rx_ring_info *rp = &np->rx_rings[i];
5040
5041                 err = niu_init_one_rx_channel(np, rp);
5042                 if (err)
5043                         return err;
5044         }
5045
5046         return 0;
5047 }
5048
5049 static int niu_set_ip_frag_rule(struct niu *np)
5050 {
5051         struct niu_parent *parent = np->parent;
5052         struct niu_classifier *cp = &np->clas;
5053         struct niu_tcam_entry *tp;
5054         int index, err;
5055
5056         index = cp->tcam_top;
5057         tp = &parent->tcam[index];
5058
5059         /* Note that the noport bit is the same in both ipv4 and
5060          * ipv6 format TCAM entries.
5061          */
5062         memset(tp, 0, sizeof(*tp));
5063         tp->key[1] = TCAM_V4KEY1_NOPORT;
5064         tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5065         tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5066                           ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5067         err = tcam_write(np, index, tp->key, tp->key_mask);
5068         if (err)
5069                 return err;
5070         err = tcam_assoc_write(np, index, tp->assoc_data);
5071         if (err)
5072                 return err;
5073         tp->valid = 1;
5074         cp->tcam_valid_entries++;
5075
5076         return 0;
5077 }
5078
5079 static int niu_init_classifier_hw(struct niu *np)
5080 {
5081         struct niu_parent *parent = np->parent;
5082         struct niu_classifier *cp = &np->clas;
5083         int i, err;
5084
5085         nw64(H1POLY, cp->h1_init);
5086         nw64(H2POLY, cp->h2_init);
5087
5088         err = niu_init_hostinfo(np);
5089         if (err)
5090                 return err;
5091
5092         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5093                 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5094
5095                 vlan_tbl_write(np, i, np->port,
5096                                vp->vlan_pref, vp->rdc_num);
5097         }
5098
5099         for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5100                 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5101
5102                 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5103                                                 ap->rdc_num, ap->mac_pref);
5104                 if (err)
5105                         return err;
5106         }
5107
5108         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5109                 int index = i - CLASS_CODE_USER_PROG1;
5110
5111                 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5112                 if (err)
5113                         return err;
5114                 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5115                 if (err)
5116                         return err;
5117         }
5118
5119         err = niu_set_ip_frag_rule(np);
5120         if (err)
5121                 return err;
5122
5123         tcam_enable(np, 1);
5124
5125         return 0;
5126 }
5127
5128 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5129 {
5130         nw64(ZCP_RAM_DATA0, data[0]);
5131         nw64(ZCP_RAM_DATA1, data[1]);
5132         nw64(ZCP_RAM_DATA2, data[2]);
5133         nw64(ZCP_RAM_DATA3, data[3]);
5134         nw64(ZCP_RAM_DATA4, data[4]);
5135         nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5136         nw64(ZCP_RAM_ACC,
5137              (ZCP_RAM_ACC_WRITE |
5138               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5139               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5140
5141         return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5142                                    1000, 100);
5143 }
5144
5145 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5146 {
5147         int err;
5148
5149         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5150                                   1000, 100);
5151         if (err) {
5152                 dev_err(np->device, PFX "%s: ZCP read busy won't clear, "
5153                         "ZCP_RAM_ACC[%llx]\n", np->dev->name,
5154                         (unsigned long long) nr64(ZCP_RAM_ACC));
5155                 return err;
5156         }
5157
5158         nw64(ZCP_RAM_ACC,
5159              (ZCP_RAM_ACC_READ |
5160               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5161               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5162
5163         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5164                                   1000, 100);
5165         if (err) {
5166                 dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, "
5167                         "ZCP_RAM_ACC[%llx]\n", np->dev->name,
5168                         (unsigned long long) nr64(ZCP_RAM_ACC));
5169                 return err;
5170         }
5171
5172         data[0] = nr64(ZCP_RAM_DATA0);
5173         data[1] = nr64(ZCP_RAM_DATA1);
5174         data[2] = nr64(ZCP_RAM_DATA2);
5175         data[3] = nr64(ZCP_RAM_DATA3);
5176         data[4] = nr64(ZCP_RAM_DATA4);
5177
5178         return 0;
5179 }
5180
5181 static void niu_zcp_cfifo_reset(struct niu *np)
5182 {
5183         u64 val = nr64(RESET_CFIFO);
5184
5185         val |= RESET_CFIFO_RST(np->port);
5186         nw64(RESET_CFIFO, val);
5187         udelay(10);
5188
5189         val &= ~RESET_CFIFO_RST(np->port);
5190         nw64(RESET_CFIFO, val);
5191 }
5192
5193 static int niu_init_zcp(struct niu *np)
5194 {
5195         u64 data[5], rbuf[5];
5196         int i, max, err;
5197
5198         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5199                 if (np->port == 0 || np->port == 1)
5200                         max = ATLAS_P0_P1_CFIFO_ENTRIES;
5201                 else
5202                         max = ATLAS_P2_P3_CFIFO_ENTRIES;
5203         } else
5204                 max = NIU_CFIFO_ENTRIES;
5205
5206         data[0] = 0;
5207         data[1] = 0;
5208         data[2] = 0;
5209         data[3] = 0;
5210         data[4] = 0;
5211
5212         for (i = 0; i < max; i++) {
5213                 err = niu_zcp_write(np, i, data);
5214                 if (err)
5215                         return err;
5216                 err = niu_zcp_read(np, i, rbuf);
5217                 if (err)
5218                         return err;
5219         }
5220
5221         niu_zcp_cfifo_reset(np);
5222         nw64(CFIFO_ECC(np->port), 0);
5223         nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5224         (void) nr64(ZCP_INT_STAT);
5225         nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5226
5227         return 0;
5228 }
5229
5230 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5231 {
5232         u64 val = nr64_ipp(IPP_CFIG);
5233
5234         nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5235         nw64_ipp(IPP_DFIFO_WR_PTR, index);
5236         nw64_ipp(IPP_DFIFO_WR0, data[0]);
5237         nw64_ipp(IPP_DFIFO_WR1, data[1]);
5238         nw64_ipp(IPP_DFIFO_WR2, data[2]);
5239         nw64_ipp(IPP_DFIFO_WR3, data[3]);
5240         nw64_ipp(IPP_DFIFO_WR4, data[4]);
5241         nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5242 }
5243
5244 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5245 {
5246         nw64_ipp(IPP_DFIFO_RD_PTR, index);
5247         data[0] = nr64_ipp(IPP_DFIFO_RD0);
5248         data[1] = nr64_ipp(IPP_DFIFO_RD1);
5249         data[2] = nr64_ipp(IPP_DFIFO_RD2);
5250         data[3] = nr64_ipp(IPP_DFIFO_RD3);
5251         data[4] = nr64_ipp(IPP_DFIFO_RD4);
5252 }
5253
5254 static int niu_ipp_reset(struct niu *np)
5255 {
5256         return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5257                                           1000, 100, "IPP_CFIG");
5258 }
5259
5260 static int niu_init_ipp(struct niu *np)
5261 {
5262         u64 data[5], rbuf[5], val;
5263         int i, max, err;
5264
5265         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5266                 if (np->port == 0 || np->port == 1)
5267                         max = ATLAS_P0_P1_DFIFO_ENTRIES;
5268                 else
5269                         max = ATLAS_P2_P3_DFIFO_ENTRIES;
5270         } else
5271                 max = NIU_DFIFO_ENTRIES;
5272
5273         data[0] = 0;
5274         data[1] = 0;
5275         data[2] = 0;
5276         data[3] = 0;
5277         data[4] = 0;
5278
5279         for (i = 0; i < max; i++) {
5280                 niu_ipp_write(np, i, data);
5281                 niu_ipp_read(np, i, rbuf);
5282         }
5283
5284         (void) nr64_ipp(IPP_INT_STAT);
5285         (void) nr64_ipp(IPP_INT_STAT);
5286
5287         err = niu_ipp_reset(np);
5288         if (err)
5289                 return err;
5290
5291         (void) nr64_ipp(IPP_PKT_DIS);
5292         (void) nr64_ipp(IPP_BAD_CS_CNT);
5293         (void) nr64_ipp(IPP_ECC);
5294
5295         (void) nr64_ipp(IPP_INT_STAT);
5296
5297         nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5298
5299         val = nr64_ipp(IPP_CFIG);
5300         val &= ~IPP_CFIG_IP_MAX_PKT;
5301         val |= (IPP_CFIG_IPP_ENABLE |
5302                 IPP_CFIG_DFIFO_ECC_EN |
5303                 IPP_CFIG_DROP_BAD_CRC |
5304                 IPP_CFIG_CKSUM_EN |
5305                 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5306         nw64_ipp(IPP_CFIG, val);
5307
5308         return 0;
5309 }
5310
5311 static void niu_handle_led(struct niu *np, int status)
5312 {
5313         u64 val;
5314         val = nr64_mac(XMAC_CONFIG);
5315
5316         if ((np->flags & NIU_FLAGS_10G) != 0 &&
5317             (np->flags & NIU_FLAGS_FIBER) != 0) {
5318                 if (status) {
5319                         val |= XMAC_CONFIG_LED_POLARITY;
5320                         val &= ~XMAC_CONFIG_FORCE_LED_ON;
5321                 } else {
5322                         val |= XMAC_CONFIG_FORCE_LED_ON;
5323                         val &= ~XMAC_CONFIG_LED_POLARITY;
5324                 }
5325         }
5326
5327         nw64_mac(XMAC_CONFIG, val);
5328 }
5329
5330 static void niu_init_xif_xmac(struct niu *np)
5331 {
5332         struct niu_link_config *lp = &np->link_config;
5333         u64 val;
5334
5335         if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5336                 val = nr64(MIF_CONFIG);
5337                 val |= MIF_CONFIG_ATCA_GE;
5338                 nw64(MIF_CONFIG, val);
5339         }
5340
5341         val = nr64_mac(XMAC_CONFIG);
5342         val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5343
5344         val |= XMAC_CONFIG_TX_OUTPUT_EN;
5345
5346         if (lp->loopback_mode == LOOPBACK_MAC) {
5347                 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5348                 val |= XMAC_CONFIG_LOOPBACK;
5349         } else {
5350                 val &= ~XMAC_CONFIG_LOOPBACK;
5351         }
5352
5353         if (np->flags & NIU_FLAGS_10G) {
5354                 val &= ~XMAC_CONFIG_LFS_DISABLE;
5355         } else {
5356                 val |= XMAC_CONFIG_LFS_DISABLE;
5357                 if (!(np->flags & NIU_FLAGS_FIBER) &&
5358                     !(np->flags & NIU_FLAGS_XCVR_SERDES))
5359                         val |= XMAC_CONFIG_1G_PCS_BYPASS;
5360                 else
5361                         val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5362         }
5363
5364         val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5365
5366         if (lp->active_speed == SPEED_100)
5367                 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5368         else
5369                 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5370
5371         nw64_mac(XMAC_CONFIG, val);
5372
5373         val = nr64_mac(XMAC_CONFIG);
5374         val &= ~XMAC_CONFIG_MODE_MASK;
5375         if (np->flags & NIU_FLAGS_10G) {
5376                 val |= XMAC_CONFIG_MODE_XGMII;
5377         } else {
5378                 if (lp->active_speed == SPEED_1000)
5379                         val |= XMAC_CONFIG_MODE_GMII;
5380                 else
5381                         val |= XMAC_CONFIG_MODE_MII;
5382         }
5383
5384         nw64_mac(XMAC_CONFIG, val);
5385 }
5386
5387 static void niu_init_xif_bmac(struct niu *np)
5388 {
5389         struct niu_link_config *lp = &np->link_config;
5390         u64 val;
5391
5392         val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5393
5394         if (lp->loopback_mode == LOOPBACK_MAC)
5395                 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5396         else
5397                 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5398
5399         if (lp->active_speed == SPEED_1000)
5400                 val |= BMAC_XIF_CONFIG_GMII_MODE;
5401         else
5402                 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5403
5404         val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5405                  BMAC_XIF_CONFIG_LED_POLARITY);
5406
5407         if (!(np->flags & NIU_FLAGS_10G) &&
5408             !(np->flags & NIU_FLAGS_FIBER) &&
5409             lp->active_speed == SPEED_100)
5410                 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5411         else
5412                 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5413
5414         nw64_mac(BMAC_XIF_CONFIG, val);
5415 }
5416
5417 static void niu_init_xif(struct niu *np)
5418 {
5419         if (np->flags & NIU_FLAGS_XMAC)
5420                 niu_init_xif_xmac(np);
5421         else
5422                 niu_init_xif_bmac(np);
5423 }
5424
5425 static void niu_pcs_mii_reset(struct niu *np)
5426 {
5427         int limit = 1000;
5428         u64 val = nr64_pcs(PCS_MII_CTL);
5429         val |= PCS_MII_CTL_RST;
5430         nw64_pcs(PCS_MII_CTL, val);
5431         while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5432                 udelay(100);
5433                 val = nr64_pcs(PCS_MII_CTL);
5434         }
5435 }
5436
5437 static void niu_xpcs_reset(struct niu *np)
5438 {
5439         int limit = 1000;
5440         u64 val = nr64_xpcs(XPCS_CONTROL1);
5441         val |= XPCS_CONTROL1_RESET;
5442         nw64_xpcs(XPCS_CONTROL1, val);
5443         while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5444                 udelay(100);
5445                 val = nr64_xpcs(XPCS_CONTROL1);
5446         }
5447 }
5448
5449 static int niu_init_pcs(struct niu *np)
5450 {
5451         struct niu_link_config *lp = &np->link_config;
5452         u64 val;
5453
5454         switch (np->flags & (NIU_FLAGS_10G |
5455                              NIU_FLAGS_FIBER |
5456                              NIU_FLAGS_XCVR_SERDES)) {
5457         case NIU_FLAGS_FIBER:
5458                 /* 1G fiber */
5459                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5460                 nw64_pcs(PCS_DPATH_MODE, 0);
5461                 niu_pcs_mii_reset(np);
5462                 break;
5463
5464         case NIU_FLAGS_10G:
5465         case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5466         case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5467                 /* 10G SERDES */
5468                 if (!(np->flags & NIU_FLAGS_XMAC))
5469                         return -EINVAL;
5470
5471                 /* 10G copper or fiber */
5472                 val = nr64_mac(XMAC_CONFIG);
5473                 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5474                 nw64_mac(XMAC_CONFIG, val);
5475
5476                 niu_xpcs_reset(np);
5477
5478                 val = nr64_xpcs(XPCS_CONTROL1);
5479                 if (lp->loopback_mode == LOOPBACK_PHY)
5480                         val |= XPCS_CONTROL1_LOOPBACK;
5481                 else
5482                         val &= ~XPCS_CONTROL1_LOOPBACK;
5483                 nw64_xpcs(XPCS_CONTROL1, val);
5484
5485                 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5486                 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5487                 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5488                 break;
5489
5490
5491         case NIU_FLAGS_XCVR_SERDES:
5492                 /* 1G SERDES */
5493                 niu_pcs_mii_reset(np);
5494                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5495                 nw64_pcs(PCS_DPATH_MODE, 0);
5496                 break;
5497
5498         case 0:
5499                 /* 1G copper */
5500         case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5501                 /* 1G RGMII FIBER */
5502                 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5503                 niu_pcs_mii_reset(np);
5504                 break;
5505
5506         default:
5507                 return -EINVAL;
5508         }
5509
5510         return 0;
5511 }
5512
5513 static int niu_reset_tx_xmac(struct niu *np)
5514 {
5515         return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5516                                           (XTXMAC_SW_RST_REG_RS |
5517                                            XTXMAC_SW_RST_SOFT_RST),
5518                                           1000, 100, "XTXMAC_SW_RST");
5519 }
5520
5521 static int niu_reset_tx_bmac(struct niu *np)
5522 {
5523         int limit;
5524
5525         nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5526         limit = 1000;
5527         while (--limit >= 0) {
5528                 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5529                         break;
5530                 udelay(100);
5531         }
5532         if (limit < 0) {
5533                 dev_err(np->device, PFX "Port %u TX BMAC would not reset, "
5534                         "BTXMAC_SW_RST[%llx]\n",
5535                         np->port,
5536                         (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5537                 return -ENODEV;
5538         }
5539
5540         return 0;
5541 }
5542
5543 static int niu_reset_tx_mac(struct niu *np)
5544 {
5545         if (np->flags & NIU_FLAGS_XMAC)
5546                 return niu_reset_tx_xmac(np);
5547         else
5548                 return niu_reset_tx_bmac(np);
5549 }
5550
5551 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5552 {
5553         u64 val;
5554
5555         val = nr64_mac(XMAC_MIN);
5556         val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5557                  XMAC_MIN_RX_MIN_PKT_SIZE);
5558         val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5559         val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5560         nw64_mac(XMAC_MIN, val);
5561
5562         nw64_mac(XMAC_MAX, max);
5563
5564         nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5565
5566         val = nr64_mac(XMAC_IPG);
5567         if (np->flags & NIU_FLAGS_10G) {
5568                 val &= ~XMAC_IPG_IPG_XGMII;
5569                 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5570         } else {
5571                 val &= ~XMAC_IPG_IPG_MII_GMII;
5572                 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5573         }
5574         nw64_mac(XMAC_IPG, val);
5575
5576         val = nr64_mac(XMAC_CONFIG);
5577         val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5578                  XMAC_CONFIG_STRETCH_MODE |
5579                  XMAC_CONFIG_VAR_MIN_IPG_EN |
5580                  XMAC_CONFIG_TX_ENABLE);
5581         nw64_mac(XMAC_CONFIG, val);
5582
5583         nw64_mac(TXMAC_FRM_CNT, 0);
5584         nw64_mac(TXMAC_BYTE_CNT, 0);
5585 }
5586
5587 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5588 {
5589         u64 val;
5590
5591         nw64_mac(BMAC_MIN_FRAME, min);
5592         nw64_mac(BMAC_MAX_FRAME, max);
5593
5594         nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5595         nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5596         nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5597
5598         val = nr64_mac(BTXMAC_CONFIG);
5599         val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5600                  BTXMAC_CONFIG_ENABLE);
5601         nw64_mac(BTXMAC_CONFIG, val);
5602 }
5603
5604 static void niu_init_tx_mac(struct niu *np)
5605 {
5606         u64 min, max;
5607
5608         min = 64;
5609         if (np->dev->mtu > ETH_DATA_LEN)
5610                 max = 9216;
5611         else
5612                 max = 1522;
5613
5614         /* The XMAC_MIN register only accepts values for TX min which
5615          * have the low 3 bits cleared.
5616          */
5617         BUILD_BUG_ON(min & 0x7);
5618
5619         if (np->flags & NIU_FLAGS_XMAC)
5620                 niu_init_tx_xmac(np, min, max);
5621         else
5622                 niu_init_tx_bmac(np, min, max);
5623 }
5624
5625 static int niu_reset_rx_xmac(struct niu *np)
5626 {
5627         int limit;
5628
5629         nw64_mac(XRXMAC_SW_RST,
5630                  XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5631         limit = 1000;
5632         while (--limit >= 0) {
5633                 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5634                                                  XRXMAC_SW_RST_SOFT_RST)))
5635                     break;
5636                 udelay(100);
5637         }
5638         if (limit < 0) {
5639                 dev_err(np->device, PFX "Port %u RX XMAC would not reset, "
5640                         "XRXMAC_SW_RST[%llx]\n",
5641                         np->port,
5642                         (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5643                 return -ENODEV;
5644         }
5645
5646         return 0;
5647 }
5648
5649 static int niu_reset_rx_bmac(struct niu *np)
5650 {
5651         int limit;
5652
5653         nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5654         limit = 1000;
5655         while (--limit >= 0) {
5656                 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5657                         break;
5658                 udelay(100);
5659         }
5660         if (limit < 0) {
5661                 dev_err(np->device, PFX "Port %u RX BMAC would not reset, "
5662                         "BRXMAC_SW_RST[%llx]\n",
5663                         np->port,
5664                         (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5665                 return -ENODEV;
5666         }
5667
5668         return 0;
5669 }
5670
5671 static int niu_reset_rx_mac(struct niu *np)
5672 {
5673         if (np->flags & NIU_FLAGS_XMAC)
5674                 return niu_reset_rx_xmac(np);
5675         else
5676                 return niu_reset_rx_bmac(np);
5677 }
5678
5679 static void niu_init_rx_xmac(struct niu *np)
5680 {
5681         struct niu_parent *parent = np->parent;
5682         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5683         int first_rdc_table = tp->first_table_num;
5684         unsigned long i;
5685         u64 val;
5686
5687         nw64_mac(XMAC_ADD_FILT0, 0);
5688         nw64_mac(XMAC_ADD_FILT1, 0);
5689         nw64_mac(XMAC_ADD_FILT2, 0);
5690         nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5691         nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5692         for (i = 0; i < MAC_NUM_HASH; i++)
5693                 nw64_mac(XMAC_HASH_TBL(i), 0);
5694         nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5695         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5696         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5697
5698         val = nr64_mac(XMAC_CONFIG);
5699         val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5700                  XMAC_CONFIG_PROMISCUOUS |
5701                  XMAC_CONFIG_PROMISC_GROUP |
5702                  XMAC_CONFIG_ERR_CHK_DIS |
5703                  XMAC_CONFIG_RX_CRC_CHK_DIS |
5704                  XMAC_CONFIG_RESERVED_MULTICAST |
5705                  XMAC_CONFIG_RX_CODEV_CHK_DIS |
5706                  XMAC_CONFIG_ADDR_FILTER_EN |
5707                  XMAC_CONFIG_RCV_PAUSE_ENABLE |
5708                  XMAC_CONFIG_STRIP_CRC |
5709                  XMAC_CONFIG_PASS_FLOW_CTRL |
5710                  XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5711         val |= (XMAC_CONFIG_HASH_FILTER_EN);
5712         nw64_mac(XMAC_CONFIG, val);
5713
5714         nw64_mac(RXMAC_BT_CNT, 0);
5715         nw64_mac(RXMAC_BC_FRM_CNT, 0);
5716         nw64_mac(RXMAC_MC_FRM_CNT, 0);
5717         nw64_mac(RXMAC_FRAG_CNT, 0);
5718         nw64_mac(RXMAC_HIST_CNT1, 0);
5719         nw64_mac(RXMAC_HIST_CNT2, 0);
5720         nw64_mac(RXMAC_HIST_CNT3, 0);
5721         nw64_mac(RXMAC_HIST_CNT4, 0);
5722         nw64_mac(RXMAC_HIST_CNT5, 0);
5723         nw64_mac(RXMAC_HIST_CNT6, 0);
5724         nw64_mac(RXMAC_HIST_CNT7, 0);
5725         nw64_mac(RXMAC_MPSZER_CNT, 0);
5726         nw64_mac(RXMAC_CRC_ER_CNT, 0);
5727         nw64_mac(RXMAC_CD_VIO_CNT, 0);
5728         nw64_mac(LINK_FAULT_CNT, 0);
5729 }
5730
5731 static void niu_init_rx_bmac(struct niu *np)
5732 {
5733         struct niu_parent *parent = np->parent;
5734         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5735         int first_rdc_table = tp->first_table_num;
5736         unsigned long i;
5737         u64 val;
5738
5739         nw64_mac(BMAC_ADD_FILT0, 0);
5740         nw64_mac(BMAC_ADD_FILT1, 0);
5741         nw64_mac(BMAC_ADD_FILT2, 0);
5742         nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5743         nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5744         for (i = 0; i < MAC_NUM_HASH; i++)
5745                 nw64_mac(BMAC_HASH_TBL(i), 0);
5746         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5747         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5748         nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5749
5750         val = nr64_mac(BRXMAC_CONFIG);
5751         val &= ~(BRXMAC_CONFIG_ENABLE |
5752                  BRXMAC_CONFIG_STRIP_PAD |
5753                  BRXMAC_CONFIG_STRIP_FCS |
5754                  BRXMAC_CONFIG_PROMISC |
5755                  BRXMAC_CONFIG_PROMISC_GRP |
5756                  BRXMAC_CONFIG_ADDR_FILT_EN |
5757                  BRXMAC_CONFIG_DISCARD_DIS);
5758         val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5759         nw64_mac(BRXMAC_CONFIG, val);
5760
5761         val = nr64_mac(BMAC_ADDR_CMPEN);
5762         val |= BMAC_ADDR_CMPEN_EN0;
5763         nw64_mac(BMAC_ADDR_CMPEN, val);
5764 }
5765
5766 static void niu_init_rx_mac(struct niu *np)
5767 {
5768         niu_set_primary_mac(np, np->dev->dev_addr);
5769
5770         if (np->flags & NIU_FLAGS_XMAC)
5771                 niu_init_rx_xmac(np);
5772         else
5773                 niu_init_rx_bmac(np);
5774 }
5775
5776 static void niu_enable_tx_xmac(struct niu *np, int on)
5777 {
5778         u64 val = nr64_mac(XMAC_CONFIG);
5779
5780         if (on)
5781                 val |= XMAC_CONFIG_TX_ENABLE;
5782         else
5783                 val &= ~XMAC_CONFIG_TX_ENABLE;
5784         nw64_mac(XMAC_CONFIG, val);
5785 }
5786
5787 static void niu_enable_tx_bmac(struct niu *np, int on)
5788 {
5789         u64 val = nr64_mac(BTXMAC_CONFIG);
5790
5791         if (on)
5792                 val |= BTXMAC_CONFIG_ENABLE;
5793         else
5794                 val &= ~BTXMAC_CONFIG_ENABLE;
5795         nw64_mac(BTXMAC_CONFIG, val);
5796 }
5797
5798 static void niu_enable_tx_mac(struct niu *np, int on)
5799 {
5800         if (np->flags & NIU_FLAGS_XMAC)
5801                 niu_enable_tx_xmac(np, on);
5802         else
5803                 niu_enable_tx_bmac(np, on);
5804 }
5805
5806 static void niu_enable_rx_xmac(struct niu *np, int on)
5807 {
5808         u64 val = nr64_mac(XMAC_CONFIG);
5809
5810         val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5811                  XMAC_CONFIG_PROMISCUOUS);
5812
5813         if (np->flags & NIU_FLAGS_MCAST)
5814                 val |= XMAC_CONFIG_HASH_FILTER_EN;
5815         if (np->flags & NIU_FLAGS_PROMISC)
5816                 val |= XMAC_CONFIG_PROMISCUOUS;
5817
5818         if (on)
5819                 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5820         else
5821                 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5822         nw64_mac(XMAC_CONFIG, val);
5823 }
5824
5825 static void niu_enable_rx_bmac(struct niu *np, int on)
5826 {
5827         u64 val = nr64_mac(BRXMAC_CONFIG);
5828
5829         val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5830                  BRXMAC_CONFIG_PROMISC);
5831
5832         if (np->flags & NIU_FLAGS_MCAST)
5833                 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5834         if (np->flags & NIU_FLAGS_PROMISC)
5835                 val |= BRXMAC_CONFIG_PROMISC;
5836
5837         if (on)
5838                 val |= BRXMAC_CONFIG_ENABLE;
5839         else
5840                 val &= ~BRXMAC_CONFIG_ENABLE;
5841         nw64_mac(BRXMAC_CONFIG, val);
5842 }
5843
5844 static void niu_enable_rx_mac(struct niu *np, int on)
5845 {
5846         if (np->flags & NIU_FLAGS_XMAC)
5847                 niu_enable_rx_xmac(np, on);
5848         else
5849                 niu_enable_rx_bmac(np, on);
5850 }
5851
5852 static int niu_init_mac(struct niu *np)
5853 {
5854         int err;
5855
5856         niu_init_xif(np);
5857         err = niu_init_pcs(np);
5858         if (err)
5859                 return err;
5860
5861         err = niu_reset_tx_mac(np);
5862         if (err)
5863                 return err;
5864         niu_init_tx_mac(np);
5865         err = niu_reset_rx_mac(np);
5866         if (err)
5867                 return err;
5868         niu_init_rx_mac(np);
5869
5870         /* This looks hookey but the RX MAC reset we just did will
5871          * undo some of the state we setup in niu_init_tx_mac() so we
5872          * have to call it again.  In particular, the RX MAC reset will
5873          * set the XMAC_MAX register back to it's default value.
5874          */
5875         niu_init_tx_mac(np);
5876         niu_enable_tx_mac(np, 1);
5877
5878         niu_enable_rx_mac(np, 1);
5879
5880         return 0;
5881 }
5882
5883 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5884 {
5885         (void) niu_tx_channel_stop(np, rp->tx_channel);
5886 }
5887
5888 static void niu_stop_tx_channels(struct niu *np)
5889 {
5890         int i;
5891
5892         for (i = 0; i < np->num_tx_rings; i++) {
5893                 struct tx_ring_info *rp = &np->tx_rings[i];
5894
5895                 niu_stop_one_tx_channel(np, rp);
5896         }
5897 }
5898
5899 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5900 {
5901         (void) niu_tx_channel_reset(np, rp->tx_channel);
5902 }
5903
5904 static void niu_reset_tx_channels(struct niu *np)
5905 {
5906         int i;
5907
5908         for (i = 0; i < np->num_tx_rings; i++) {
5909                 struct tx_ring_info *rp = &np->tx_rings[i];
5910
5911                 niu_reset_one_tx_channel(np, rp);
5912         }
5913 }
5914
5915 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5916 {
5917         (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5918 }
5919
5920 static void niu_stop_rx_channels(struct niu *np)
5921 {
5922         int i;
5923
5924         for (i = 0; i < np->num_rx_rings; i++) {
5925                 struct rx_ring_info *rp = &np->rx_rings[i];
5926
5927                 niu_stop_one_rx_channel(np, rp);
5928         }
5929 }
5930
5931 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5932 {
5933         int channel = rp->rx_channel;
5934
5935         (void) niu_rx_channel_reset(np, channel);
5936         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5937         nw64(RX_DMA_CTL_STAT(channel), 0);
5938         (void) niu_enable_rx_channel(np, channel, 0);
5939 }
5940
5941 static void niu_reset_rx_channels(struct niu *np)
5942 {
5943         int i;
5944
5945         for (i = 0; i < np->num_rx_rings; i++) {
5946                 struct rx_ring_info *rp = &np->rx_rings[i];
5947
5948                 niu_reset_one_rx_channel(np, rp);
5949         }
5950 }
5951
5952 static void niu_disable_ipp(struct niu *np)
5953 {
5954         u64 rd, wr, val;
5955         int limit;
5956
5957         rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5958         wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5959         limit = 100;
5960         while (--limit >= 0 && (rd != wr)) {
5961                 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5962                 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5963         }
5964         if (limit < 0 &&
5965             (rd != 0 && wr != 1)) {
5966                 dev_err(np->device, PFX "%s: IPP would not quiesce, "
5967                         "rd_ptr[%llx] wr_ptr[%llx]\n",
5968                         np->dev->name,
5969                         (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR),
5970                         (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR));
5971         }
5972
5973         val = nr64_ipp(IPP_CFIG);
5974         val &= ~(IPP_CFIG_IPP_ENABLE |
5975                  IPP_CFIG_DFIFO_ECC_EN |
5976                  IPP_CFIG_DROP_BAD_CRC |
5977                  IPP_CFIG_CKSUM_EN);
5978         nw64_ipp(IPP_CFIG, val);
5979
5980         (void) niu_ipp_reset(np);
5981 }
5982
5983 static int niu_init_hw(struct niu *np)
5984 {
5985         int i, err;
5986
5987         niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name);
5988         niu_txc_enable_port(np, 1);
5989         niu_txc_port_dma_enable(np, 1);
5990         niu_txc_set_imask(np, 0);
5991
5992         niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name);
5993         for (i = 0; i < np->num_tx_rings; i++) {
5994                 struct tx_ring_info *rp = &np->tx_rings[i];
5995
5996                 err = niu_init_one_tx_channel(np, rp);
5997                 if (err)
5998                         return err;
5999         }
6000
6001         niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name);
6002         err = niu_init_rx_channels(np);
6003         if (err)
6004                 goto out_uninit_tx_channels;
6005
6006         niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name);
6007         err = niu_init_classifier_hw(np);
6008         if (err)
6009                 goto out_uninit_rx_channels;
6010
6011         niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name);
6012         err = niu_init_zcp(np);
6013         if (err)
6014                 goto out_uninit_rx_channels;
6015
6016         niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name);
6017         err = niu_init_ipp(np);
6018         if (err)
6019                 goto out_uninit_rx_channels;
6020
6021         niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name);
6022         err = niu_init_mac(np);
6023         if (err)
6024                 goto out_uninit_ipp;
6025
6026         return 0;
6027
6028 out_uninit_ipp:
6029         niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name);
6030         niu_disable_ipp(np);
6031
6032 out_uninit_rx_channels:
6033         niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name);
6034         niu_stop_rx_channels(np);
6035         niu_reset_rx_channels(np);
6036
6037 out_uninit_tx_channels:
6038         niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name);
6039         niu_stop_tx_channels(np);
6040         niu_reset_tx_channels(np);
6041
6042         return err;
6043 }
6044
6045 static void niu_stop_hw(struct niu *np)
6046 {
6047         niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name);
6048         niu_enable_interrupts(np, 0);
6049
6050         niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name);
6051         niu_enable_rx_mac(np, 0);
6052
6053         niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name);
6054         niu_disable_ipp(np);
6055
6056         niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name);
6057         niu_stop_tx_channels(np);
6058
6059         niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name);
6060         niu_stop_rx_channels(np);
6061
6062         niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name);
6063         niu_reset_tx_channels(np);
6064
6065         niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name);
6066         niu_reset_rx_channels(np);
6067 }
6068
6069 static void niu_set_irq_name(struct niu *np)
6070 {
6071         int port = np->port;
6072         int i, j = 1;
6073
6074         sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6075
6076         if (port == 0) {
6077                 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6078                 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6079                 j = 3;
6080         }
6081
6082         for (i = 0; i < np->num_ldg - j; i++) {
6083                 if (i < np->num_rx_rings)
6084                         sprintf(np->irq_name[i+j], "%s-rx-%d",
6085                                 np->dev->name, i);
6086                 else if (i < np->num_tx_rings + np->num_rx_rings)
6087                         sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6088                                 i - np->num_rx_rings);
6089         }
6090 }
6091
6092 static int niu_request_irq(struct niu *np)
6093 {
6094         int i, j, err;
6095
6096         niu_set_irq_name(np);
6097
6098         err = 0;
6099         for (i = 0; i < np->num_ldg; i++) {
6100                 struct niu_ldg *lp = &np->ldg[i];
6101
6102                 err = request_irq(lp->irq, niu_interrupt,
6103                                   IRQF_SHARED | IRQF_SAMPLE_RANDOM,
6104                                   np->irq_name[i], lp);
6105                 if (err)
6106                         goto out_free_irqs;
6107
6108         }
6109
6110         return 0;
6111
6112 out_free_irqs:
6113         for (j = 0; j < i; j++) {
6114                 struct niu_ldg *lp = &np->ldg[j];
6115
6116                 free_irq(lp->irq, lp);
6117         }
6118         return err;
6119 }
6120
6121 static void niu_free_irq(struct niu *np)
6122 {
6123         int i;
6124
6125         for (i = 0; i < np->num_ldg; i++) {
6126                 struct niu_ldg *lp = &np->ldg[i];
6127
6128                 free_irq(lp->irq, lp);
6129         }
6130 }
6131
6132 static void niu_enable_napi(struct niu *np)
6133 {
6134         int i;
6135
6136         for (i = 0; i < np->num_ldg; i++)
6137                 napi_enable(&np->ldg[i].napi);
6138 }
6139
6140 static void niu_disable_napi(struct niu *np)
6141 {
6142         int i;
6143
6144         for (i = 0; i < np->num_ldg; i++)
6145                 napi_disable(&np->ldg[i].napi);
6146 }
6147
6148 static int niu_open(struct net_device *dev)
6149 {
6150         struct niu *np = netdev_priv(dev);
6151         int err;
6152
6153         netif_carrier_off(dev);
6154
6155         err = niu_alloc_channels(np);
6156         if (err)
6157                 goto out_err;
6158
6159         err = niu_enable_interrupts(np, 0);
6160         if (err)
6161                 goto out_free_channels;
6162
6163         err = niu_request_irq(np);
6164         if (err)
6165                 goto out_free_channels;
6166
6167         niu_enable_napi(np);
6168
6169         spin_lock_irq(&np->lock);
6170
6171         err = niu_init_hw(np);
6172         if (!err) {
6173                 init_timer(&np->timer);
6174                 np->timer.expires = jiffies + HZ;
6175                 np->timer.data = (unsigned long) np;
6176                 np->timer.function = niu_timer;
6177
6178                 err = niu_enable_interrupts(np, 1);
6179                 if (err)
6180                         niu_stop_hw(np);
6181         }
6182
6183         spin_unlock_irq(&np->lock);
6184
6185         if (err) {
6186                 niu_disable_napi(np);
6187                 goto out_free_irq;
6188         }
6189
6190         netif_tx_start_all_queues(dev);
6191
6192         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6193                 netif_carrier_on(dev);
6194
6195         add_timer(&np->timer);
6196
6197         return 0;
6198
6199 out_free_irq:
6200         niu_free_irq(np);
6201
6202 out_free_channels:
6203         niu_free_channels(np);
6204
6205 out_err:
6206         return err;
6207 }
6208
6209 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6210 {
6211         cancel_work_sync(&np->reset_task);
6212
6213         niu_disable_napi(np);
6214         netif_tx_stop_all_queues(dev);
6215
6216         del_timer_sync(&np->timer);
6217
6218         spin_lock_irq(&np->lock);
6219
6220         niu_stop_hw(np);
6221
6222         spin_unlock_irq(&np->lock);
6223 }
6224
6225 static int niu_close(struct net_device *dev)
6226 {
6227         struct niu *np = netdev_priv(dev);
6228
6229         niu_full_shutdown(np, dev);
6230
6231         niu_free_irq(np);
6232
6233         niu_free_channels(np);
6234
6235         niu_handle_led(np, 0);
6236
6237         return 0;
6238 }
6239
6240 static void niu_sync_xmac_stats(struct niu *np)
6241 {
6242         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6243
6244         mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6245         mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6246
6247         mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6248         mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6249         mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6250         mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6251         mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6252         mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6253         mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6254         mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6255         mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6256         mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6257         mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6258         mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6259         mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6260         mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6261         mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6262         mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6263 }
6264
6265 static void niu_sync_bmac_stats(struct niu *np)
6266 {
6267         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6268
6269         mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6270         mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6271
6272         mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6273         mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6274         mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6275         mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6276 }
6277
6278 static void niu_sync_mac_stats(struct niu *np)
6279 {
6280         if (np->flags & NIU_FLAGS_XMAC)
6281                 niu_sync_xmac_stats(np);
6282         else
6283                 niu_sync_bmac_stats(np);
6284 }
6285
6286 static void niu_get_rx_stats(struct niu *np)
6287 {
6288         unsigned long pkts, dropped, errors, bytes;
6289         int i;
6290
6291         pkts = dropped = errors = bytes = 0;
6292         for (i = 0; i < np->num_rx_rings; i++) {
6293                 struct rx_ring_info *rp = &np->rx_rings[i];
6294
6295                 niu_sync_rx_discard_stats(np, rp, 0);
6296
6297                 pkts += rp->rx_packets;
6298                 bytes += rp->rx_bytes;
6299                 dropped += rp->rx_dropped;
6300                 errors += rp->rx_errors;
6301         }
6302         np->dev->stats.rx_packets = pkts;
6303         np->dev->stats.rx_bytes = bytes;
6304         np->dev->stats.rx_dropped = dropped;
6305         np->dev->stats.rx_errors = errors;
6306 }
6307
6308 static void niu_get_tx_stats(struct niu *np)
6309 {
6310         unsigned long pkts, errors, bytes;
6311         int i;
6312
6313         pkts = errors = bytes = 0;
6314         for (i = 0; i < np->num_tx_rings; i++) {
6315                 struct tx_ring_info *rp = &np->tx_rings[i];
6316
6317                 pkts += rp->tx_packets;
6318                 bytes += rp->tx_bytes;
6319                 errors += rp->tx_errors;
6320         }
6321         np->dev->stats.tx_packets = pkts;
6322         np->dev->stats.tx_bytes = bytes;
6323         np->dev->stats.tx_errors = errors;
6324 }
6325
6326 static struct net_device_stats *niu_get_stats(struct net_device *dev)
6327 {
6328         struct niu *np = netdev_priv(dev);
6329
6330         niu_get_rx_stats(np);
6331         niu_get_tx_stats(np);
6332
6333         return &dev->stats;
6334 }
6335
6336 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6337 {
6338         int i;
6339
6340         for (i = 0; i < 16; i++)
6341                 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6342 }
6343
6344 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6345 {
6346         int i;
6347
6348         for (i = 0; i < 16; i++)
6349                 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6350 }
6351
6352 static void niu_load_hash(struct niu *np, u16 *hash)
6353 {
6354         if (np->flags & NIU_FLAGS_XMAC)
6355                 niu_load_hash_xmac(np, hash);
6356         else
6357                 niu_load_hash_bmac(np, hash);
6358 }
6359
6360 static void niu_set_rx_mode(struct net_device *dev)
6361 {
6362         struct niu *np = netdev_priv(dev);
6363         int i, alt_cnt, err;
6364         struct dev_addr_list *addr;
6365         unsigned long flags;
6366         u16 hash[16] = { 0, };
6367
6368         spin_lock_irqsave(&np->lock, flags);
6369         niu_enable_rx_mac(np, 0);
6370
6371         np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6372         if (dev->flags & IFF_PROMISC)
6373                 np->flags |= NIU_FLAGS_PROMISC;
6374         if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
6375                 np->flags |= NIU_FLAGS_MCAST;
6376
6377         alt_cnt = dev->uc_count;
6378         if (alt_cnt > niu_num_alt_addr(np)) {
6379                 alt_cnt = 0;
6380                 np->flags |= NIU_FLAGS_PROMISC;
6381         }
6382
6383         if (alt_cnt) {
6384                 int index = 0;
6385
6386                 for (addr = dev->uc_list; addr; addr = addr->next) {
6387                         err = niu_set_alt_mac(np, index,
6388                                               addr->da_addr);
6389                         if (err)