of/platform: remove all of_bus_type and of_platform_bus_type references
[linux-2.6.git] / drivers / net / niu.c
1 /* niu.c: Neptune ethernet driver.
2  *
3  * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
4  */
5
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/netdevice.h>
13 #include <linux/ethtool.h>
14 #include <linux/etherdevice.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/bitops.h>
18 #include <linux/mii.h>
19 #include <linux/if_ether.h>
20 #include <linux/if_vlan.h>
21 #include <linux/ip.h>
22 #include <linux/in.h>
23 #include <linux/ipv6.h>
24 #include <linux/log2.h>
25 #include <linux/jiffies.h>
26 #include <linux/crc32.h>
27 #include <linux/list.h>
28 #include <linux/slab.h>
29
30 #include <linux/io.h>
31 #include <linux/of_device.h>
32
33 #include "niu.h"
34
35 #define DRV_MODULE_NAME         "niu"
36 #define DRV_MODULE_VERSION      "1.1"
37 #define DRV_MODULE_RELDATE      "Apr 22, 2010"
38
39 static char version[] __devinitdata =
40         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
41
42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43 MODULE_DESCRIPTION("NIU ethernet driver");
44 MODULE_LICENSE("GPL");
45 MODULE_VERSION(DRV_MODULE_VERSION);
46
47 #ifndef readq
48 static u64 readq(void __iomem *reg)
49 {
50         return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
51 }
52
53 static void writeq(u64 val, void __iomem *reg)
54 {
55         writel(val & 0xffffffff, reg);
56         writel(val >> 32, reg + 0x4UL);
57 }
58 #endif
59
60 static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl) = {
61         {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
62         {}
63 };
64
65 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
66
67 #define NIU_TX_TIMEOUT                  (5 * HZ)
68
69 #define nr64(reg)               readq(np->regs + (reg))
70 #define nw64(reg, val)          writeq((val), np->regs + (reg))
71
72 #define nr64_mac(reg)           readq(np->mac_regs + (reg))
73 #define nw64_mac(reg, val)      writeq((val), np->mac_regs + (reg))
74
75 #define nr64_ipp(reg)           readq(np->regs + np->ipp_off + (reg))
76 #define nw64_ipp(reg, val)      writeq((val), np->regs + np->ipp_off + (reg))
77
78 #define nr64_pcs(reg)           readq(np->regs + np->pcs_off + (reg))
79 #define nw64_pcs(reg, val)      writeq((val), np->regs + np->pcs_off + (reg))
80
81 #define nr64_xpcs(reg)          readq(np->regs + np->xpcs_off + (reg))
82 #define nw64_xpcs(reg, val)     writeq((val), np->regs + np->xpcs_off + (reg))
83
84 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
85
86 static int niu_debug;
87 static int debug = -1;
88 module_param(debug, int, 0);
89 MODULE_PARM_DESC(debug, "NIU debug level");
90
91 #define niu_lock_parent(np, flags) \
92         spin_lock_irqsave(&np->parent->lock, flags)
93 #define niu_unlock_parent(np, flags) \
94         spin_unlock_irqrestore(&np->parent->lock, flags)
95
96 static int serdes_init_10g_serdes(struct niu *np);
97
98 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
99                                      u64 bits, int limit, int delay)
100 {
101         while (--limit >= 0) {
102                 u64 val = nr64_mac(reg);
103
104                 if (!(val & bits))
105                         break;
106                 udelay(delay);
107         }
108         if (limit < 0)
109                 return -ENODEV;
110         return 0;
111 }
112
113 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
114                                         u64 bits, int limit, int delay,
115                                         const char *reg_name)
116 {
117         int err;
118
119         nw64_mac(reg, bits);
120         err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
121         if (err)
122                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
123                            (unsigned long long)bits, reg_name,
124                            (unsigned long long)nr64_mac(reg));
125         return err;
126 }
127
128 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
129 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
130         __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
131 })
132
133 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
134                                      u64 bits, int limit, int delay)
135 {
136         while (--limit >= 0) {
137                 u64 val = nr64_ipp(reg);
138
139                 if (!(val & bits))
140                         break;
141                 udelay(delay);
142         }
143         if (limit < 0)
144                 return -ENODEV;
145         return 0;
146 }
147
148 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
149                                         u64 bits, int limit, int delay,
150                                         const char *reg_name)
151 {
152         int err;
153         u64 val;
154
155         val = nr64_ipp(reg);
156         val |= bits;
157         nw64_ipp(reg, val);
158
159         err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
160         if (err)
161                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
162                            (unsigned long long)bits, reg_name,
163                            (unsigned long long)nr64_ipp(reg));
164         return err;
165 }
166
167 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
168 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
169         __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
170 })
171
172 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
173                                  u64 bits, int limit, int delay)
174 {
175         while (--limit >= 0) {
176                 u64 val = nr64(reg);
177
178                 if (!(val & bits))
179                         break;
180                 udelay(delay);
181         }
182         if (limit < 0)
183                 return -ENODEV;
184         return 0;
185 }
186
187 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
188 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
189         __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
190 })
191
192 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
193                                     u64 bits, int limit, int delay,
194                                     const char *reg_name)
195 {
196         int err;
197
198         nw64(reg, bits);
199         err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
200         if (err)
201                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
202                            (unsigned long long)bits, reg_name,
203                            (unsigned long long)nr64(reg));
204         return err;
205 }
206
207 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
208 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
209         __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
210 })
211
212 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
213 {
214         u64 val = (u64) lp->timer;
215
216         if (on)
217                 val |= LDG_IMGMT_ARM;
218
219         nw64(LDG_IMGMT(lp->ldg_num), val);
220 }
221
222 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
223 {
224         unsigned long mask_reg, bits;
225         u64 val;
226
227         if (ldn < 0 || ldn > LDN_MAX)
228                 return -EINVAL;
229
230         if (ldn < 64) {
231                 mask_reg = LD_IM0(ldn);
232                 bits = LD_IM0_MASK;
233         } else {
234                 mask_reg = LD_IM1(ldn - 64);
235                 bits = LD_IM1_MASK;
236         }
237
238         val = nr64(mask_reg);
239         if (on)
240                 val &= ~bits;
241         else
242                 val |= bits;
243         nw64(mask_reg, val);
244
245         return 0;
246 }
247
248 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
249 {
250         struct niu_parent *parent = np->parent;
251         int i;
252
253         for (i = 0; i <= LDN_MAX; i++) {
254                 int err;
255
256                 if (parent->ldg_map[i] != lp->ldg_num)
257                         continue;
258
259                 err = niu_ldn_irq_enable(np, i, on);
260                 if (err)
261                         return err;
262         }
263         return 0;
264 }
265
266 static int niu_enable_interrupts(struct niu *np, int on)
267 {
268         int i;
269
270         for (i = 0; i < np->num_ldg; i++) {
271                 struct niu_ldg *lp = &np->ldg[i];
272                 int err;
273
274                 err = niu_enable_ldn_in_ldg(np, lp, on);
275                 if (err)
276                         return err;
277         }
278         for (i = 0; i < np->num_ldg; i++)
279                 niu_ldg_rearm(np, &np->ldg[i], on);
280
281         return 0;
282 }
283
284 static u32 phy_encode(u32 type, int port)
285 {
286         return (type << (port * 2));
287 }
288
289 static u32 phy_decode(u32 val, int port)
290 {
291         return (val >> (port * 2)) & PORT_TYPE_MASK;
292 }
293
294 static int mdio_wait(struct niu *np)
295 {
296         int limit = 1000;
297         u64 val;
298
299         while (--limit > 0) {
300                 val = nr64(MIF_FRAME_OUTPUT);
301                 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
302                         return val & MIF_FRAME_OUTPUT_DATA;
303
304                 udelay(10);
305         }
306
307         return -ENODEV;
308 }
309
310 static int mdio_read(struct niu *np, int port, int dev, int reg)
311 {
312         int err;
313
314         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
315         err = mdio_wait(np);
316         if (err < 0)
317                 return err;
318
319         nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
320         return mdio_wait(np);
321 }
322
323 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
324 {
325         int err;
326
327         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
328         err = mdio_wait(np);
329         if (err < 0)
330                 return err;
331
332         nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
333         err = mdio_wait(np);
334         if (err < 0)
335                 return err;
336
337         return 0;
338 }
339
340 static int mii_read(struct niu *np, int port, int reg)
341 {
342         nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
343         return mdio_wait(np);
344 }
345
346 static int mii_write(struct niu *np, int port, int reg, int data)
347 {
348         int err;
349
350         nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
351         err = mdio_wait(np);
352         if (err < 0)
353                 return err;
354
355         return 0;
356 }
357
358 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
359 {
360         int err;
361
362         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
363                          ESR2_TI_PLL_TX_CFG_L(channel),
364                          val & 0xffff);
365         if (!err)
366                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
367                                  ESR2_TI_PLL_TX_CFG_H(channel),
368                                  val >> 16);
369         return err;
370 }
371
372 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
373 {
374         int err;
375
376         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
377                          ESR2_TI_PLL_RX_CFG_L(channel),
378                          val & 0xffff);
379         if (!err)
380                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
381                                  ESR2_TI_PLL_RX_CFG_H(channel),
382                                  val >> 16);
383         return err;
384 }
385
386 /* Mode is always 10G fiber.  */
387 static int serdes_init_niu_10g_fiber(struct niu *np)
388 {
389         struct niu_link_config *lp = &np->link_config;
390         u32 tx_cfg, rx_cfg;
391         unsigned long i;
392
393         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
394         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
395                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
396                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
397
398         if (lp->loopback_mode == LOOPBACK_PHY) {
399                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
400
401                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
402                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
403
404                 tx_cfg |= PLL_TX_CFG_ENTEST;
405                 rx_cfg |= PLL_RX_CFG_ENTEST;
406         }
407
408         /* Initialize all 4 lanes of the SERDES.  */
409         for (i = 0; i < 4; i++) {
410                 int err = esr2_set_tx_cfg(np, i, tx_cfg);
411                 if (err)
412                         return err;
413         }
414
415         for (i = 0; i < 4; i++) {
416                 int err = esr2_set_rx_cfg(np, i, rx_cfg);
417                 if (err)
418                         return err;
419         }
420
421         return 0;
422 }
423
424 static int serdes_init_niu_1g_serdes(struct niu *np)
425 {
426         struct niu_link_config *lp = &np->link_config;
427         u16 pll_cfg, pll_sts;
428         int max_retry = 100;
429         u64 uninitialized_var(sig), mask, val;
430         u32 tx_cfg, rx_cfg;
431         unsigned long i;
432         int err;
433
434         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
435                   PLL_TX_CFG_RATE_HALF);
436         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
437                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
438                   PLL_RX_CFG_RATE_HALF);
439
440         if (np->port == 0)
441                 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
442
443         if (lp->loopback_mode == LOOPBACK_PHY) {
444                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
445
446                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
447                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
448
449                 tx_cfg |= PLL_TX_CFG_ENTEST;
450                 rx_cfg |= PLL_RX_CFG_ENTEST;
451         }
452
453         /* Initialize PLL for 1G */
454         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
455
456         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
457                          ESR2_TI_PLL_CFG_L, pll_cfg);
458         if (err) {
459                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
460                            np->port, __func__);
461                 return err;
462         }
463
464         pll_sts = PLL_CFG_ENPLL;
465
466         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
467                          ESR2_TI_PLL_STS_L, pll_sts);
468         if (err) {
469                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
470                            np->port, __func__);
471                 return err;
472         }
473
474         udelay(200);
475
476         /* Initialize all 4 lanes of the SERDES.  */
477         for (i = 0; i < 4; i++) {
478                 err = esr2_set_tx_cfg(np, i, tx_cfg);
479                 if (err)
480                         return err;
481         }
482
483         for (i = 0; i < 4; i++) {
484                 err = esr2_set_rx_cfg(np, i, rx_cfg);
485                 if (err)
486                         return err;
487         }
488
489         switch (np->port) {
490         case 0:
491                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
492                 mask = val;
493                 break;
494
495         case 1:
496                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
497                 mask = val;
498                 break;
499
500         default:
501                 return -EINVAL;
502         }
503
504         while (max_retry--) {
505                 sig = nr64(ESR_INT_SIGNALS);
506                 if ((sig & mask) == val)
507                         break;
508
509                 mdelay(500);
510         }
511
512         if ((sig & mask) != val) {
513                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
514                            np->port, (int)(sig & mask), (int)val);
515                 return -ENODEV;
516         }
517
518         return 0;
519 }
520
521 static int serdes_init_niu_10g_serdes(struct niu *np)
522 {
523         struct niu_link_config *lp = &np->link_config;
524         u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
525         int max_retry = 100;
526         u64 uninitialized_var(sig), mask, val;
527         unsigned long i;
528         int err;
529
530         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
531         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
532                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
533                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
534
535         if (lp->loopback_mode == LOOPBACK_PHY) {
536                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
537
538                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
539                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
540
541                 tx_cfg |= PLL_TX_CFG_ENTEST;
542                 rx_cfg |= PLL_RX_CFG_ENTEST;
543         }
544
545         /* Initialize PLL for 10G */
546         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
547
548         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
549                          ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
550         if (err) {
551                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
552                            np->port, __func__);
553                 return err;
554         }
555
556         pll_sts = PLL_CFG_ENPLL;
557
558         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
559                          ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
560         if (err) {
561                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
562                            np->port, __func__);
563                 return err;
564         }
565
566         udelay(200);
567
568         /* Initialize all 4 lanes of the SERDES.  */
569         for (i = 0; i < 4; i++) {
570                 err = esr2_set_tx_cfg(np, i, tx_cfg);
571                 if (err)
572                         return err;
573         }
574
575         for (i = 0; i < 4; i++) {
576                 err = esr2_set_rx_cfg(np, i, rx_cfg);
577                 if (err)
578                         return err;
579         }
580
581         /* check if serdes is ready */
582
583         switch (np->port) {
584         case 0:
585                 mask = ESR_INT_SIGNALS_P0_BITS;
586                 val = (ESR_INT_SRDY0_P0 |
587                        ESR_INT_DET0_P0 |
588                        ESR_INT_XSRDY_P0 |
589                        ESR_INT_XDP_P0_CH3 |
590                        ESR_INT_XDP_P0_CH2 |
591                        ESR_INT_XDP_P0_CH1 |
592                        ESR_INT_XDP_P0_CH0);
593                 break;
594
595         case 1:
596                 mask = ESR_INT_SIGNALS_P1_BITS;
597                 val = (ESR_INT_SRDY0_P1 |
598                        ESR_INT_DET0_P1 |
599                        ESR_INT_XSRDY_P1 |
600                        ESR_INT_XDP_P1_CH3 |
601                        ESR_INT_XDP_P1_CH2 |
602                        ESR_INT_XDP_P1_CH1 |
603                        ESR_INT_XDP_P1_CH0);
604                 break;
605
606         default:
607                 return -EINVAL;
608         }
609
610         while (max_retry--) {
611                 sig = nr64(ESR_INT_SIGNALS);
612                 if ((sig & mask) == val)
613                         break;
614
615                 mdelay(500);
616         }
617
618         if ((sig & mask) != val) {
619                 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
620                         np->port, (int)(sig & mask), (int)val);
621
622                 /* 10G failed, try initializing at 1G */
623                 err = serdes_init_niu_1g_serdes(np);
624                 if (!err) {
625                         np->flags &= ~NIU_FLAGS_10G;
626                         np->mac_xcvr = MAC_XCVR_PCS;
627                 }  else {
628                         netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
629                                    np->port);
630                         return -ENODEV;
631                 }
632         }
633         return 0;
634 }
635
636 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
637 {
638         int err;
639
640         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
641         if (err >= 0) {
642                 *val = (err & 0xffff);
643                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
644                                 ESR_RXTX_CTRL_H(chan));
645                 if (err >= 0)
646                         *val |= ((err & 0xffff) << 16);
647                 err = 0;
648         }
649         return err;
650 }
651
652 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
653 {
654         int err;
655
656         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
657                         ESR_GLUE_CTRL0_L(chan));
658         if (err >= 0) {
659                 *val = (err & 0xffff);
660                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
661                                 ESR_GLUE_CTRL0_H(chan));
662                 if (err >= 0) {
663                         *val |= ((err & 0xffff) << 16);
664                         err = 0;
665                 }
666         }
667         return err;
668 }
669
670 static int esr_read_reset(struct niu *np, u32 *val)
671 {
672         int err;
673
674         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
675                         ESR_RXTX_RESET_CTRL_L);
676         if (err >= 0) {
677                 *val = (err & 0xffff);
678                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
679                                 ESR_RXTX_RESET_CTRL_H);
680                 if (err >= 0) {
681                         *val |= ((err & 0xffff) << 16);
682                         err = 0;
683                 }
684         }
685         return err;
686 }
687
688 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
689 {
690         int err;
691
692         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
693                          ESR_RXTX_CTRL_L(chan), val & 0xffff);
694         if (!err)
695                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
696                                  ESR_RXTX_CTRL_H(chan), (val >> 16));
697         return err;
698 }
699
700 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
701 {
702         int err;
703
704         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
705                         ESR_GLUE_CTRL0_L(chan), val & 0xffff);
706         if (!err)
707                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
708                                  ESR_GLUE_CTRL0_H(chan), (val >> 16));
709         return err;
710 }
711
712 static int esr_reset(struct niu *np)
713 {
714         u32 uninitialized_var(reset);
715         int err;
716
717         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
718                          ESR_RXTX_RESET_CTRL_L, 0x0000);
719         if (err)
720                 return err;
721         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
722                          ESR_RXTX_RESET_CTRL_H, 0xffff);
723         if (err)
724                 return err;
725         udelay(200);
726
727         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
728                          ESR_RXTX_RESET_CTRL_L, 0xffff);
729         if (err)
730                 return err;
731         udelay(200);
732
733         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
734                          ESR_RXTX_RESET_CTRL_H, 0x0000);
735         if (err)
736                 return err;
737         udelay(200);
738
739         err = esr_read_reset(np, &reset);
740         if (err)
741                 return err;
742         if (reset != 0) {
743                 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
744                            np->port, reset);
745                 return -ENODEV;
746         }
747
748         return 0;
749 }
750
751 static int serdes_init_10g(struct niu *np)
752 {
753         struct niu_link_config *lp = &np->link_config;
754         unsigned long ctrl_reg, test_cfg_reg, i;
755         u64 ctrl_val, test_cfg_val, sig, mask, val;
756         int err;
757
758         switch (np->port) {
759         case 0:
760                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
761                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
762                 break;
763         case 1:
764                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
765                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
766                 break;
767
768         default:
769                 return -EINVAL;
770         }
771         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
772                     ENET_SERDES_CTRL_SDET_1 |
773                     ENET_SERDES_CTRL_SDET_2 |
774                     ENET_SERDES_CTRL_SDET_3 |
775                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
776                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
777                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
778                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
779                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
780                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
781                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
782                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
783         test_cfg_val = 0;
784
785         if (lp->loopback_mode == LOOPBACK_PHY) {
786                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
787                                   ENET_SERDES_TEST_MD_0_SHIFT) |
788                                  (ENET_TEST_MD_PAD_LOOPBACK <<
789                                   ENET_SERDES_TEST_MD_1_SHIFT) |
790                                  (ENET_TEST_MD_PAD_LOOPBACK <<
791                                   ENET_SERDES_TEST_MD_2_SHIFT) |
792                                  (ENET_TEST_MD_PAD_LOOPBACK <<
793                                   ENET_SERDES_TEST_MD_3_SHIFT));
794         }
795
796         nw64(ctrl_reg, ctrl_val);
797         nw64(test_cfg_reg, test_cfg_val);
798
799         /* Initialize all 4 lanes of the SERDES.  */
800         for (i = 0; i < 4; i++) {
801                 u32 rxtx_ctrl, glue0;
802
803                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
804                 if (err)
805                         return err;
806                 err = esr_read_glue0(np, i, &glue0);
807                 if (err)
808                         return err;
809
810                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
811                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
812                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
813
814                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
815                            ESR_GLUE_CTRL0_THCNT |
816                            ESR_GLUE_CTRL0_BLTIME);
817                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
818                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
819                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
820                           (BLTIME_300_CYCLES <<
821                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
822
823                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
824                 if (err)
825                         return err;
826                 err = esr_write_glue0(np, i, glue0);
827                 if (err)
828                         return err;
829         }
830
831         err = esr_reset(np);
832         if (err)
833                 return err;
834
835         sig = nr64(ESR_INT_SIGNALS);
836         switch (np->port) {
837         case 0:
838                 mask = ESR_INT_SIGNALS_P0_BITS;
839                 val = (ESR_INT_SRDY0_P0 |
840                        ESR_INT_DET0_P0 |
841                        ESR_INT_XSRDY_P0 |
842                        ESR_INT_XDP_P0_CH3 |
843                        ESR_INT_XDP_P0_CH2 |
844                        ESR_INT_XDP_P0_CH1 |
845                        ESR_INT_XDP_P0_CH0);
846                 break;
847
848         case 1:
849                 mask = ESR_INT_SIGNALS_P1_BITS;
850                 val = (ESR_INT_SRDY0_P1 |
851                        ESR_INT_DET0_P1 |
852                        ESR_INT_XSRDY_P1 |
853                        ESR_INT_XDP_P1_CH3 |
854                        ESR_INT_XDP_P1_CH2 |
855                        ESR_INT_XDP_P1_CH1 |
856                        ESR_INT_XDP_P1_CH0);
857                 break;
858
859         default:
860                 return -EINVAL;
861         }
862
863         if ((sig & mask) != val) {
864                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
865                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
866                         return 0;
867                 }
868                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
869                            np->port, (int)(sig & mask), (int)val);
870                 return -ENODEV;
871         }
872         if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
873                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
874         return 0;
875 }
876
877 static int serdes_init_1g(struct niu *np)
878 {
879         u64 val;
880
881         val = nr64(ENET_SERDES_1_PLL_CFG);
882         val &= ~ENET_SERDES_PLL_FBDIV2;
883         switch (np->port) {
884         case 0:
885                 val |= ENET_SERDES_PLL_HRATE0;
886                 break;
887         case 1:
888                 val |= ENET_SERDES_PLL_HRATE1;
889                 break;
890         case 2:
891                 val |= ENET_SERDES_PLL_HRATE2;
892                 break;
893         case 3:
894                 val |= ENET_SERDES_PLL_HRATE3;
895                 break;
896         default:
897                 return -EINVAL;
898         }
899         nw64(ENET_SERDES_1_PLL_CFG, val);
900
901         return 0;
902 }
903
904 static int serdes_init_1g_serdes(struct niu *np)
905 {
906         struct niu_link_config *lp = &np->link_config;
907         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
908         u64 ctrl_val, test_cfg_val, sig, mask, val;
909         int err;
910         u64 reset_val, val_rd;
911
912         val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
913                 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
914                 ENET_SERDES_PLL_FBDIV0;
915         switch (np->port) {
916         case 0:
917                 reset_val =  ENET_SERDES_RESET_0;
918                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
919                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
920                 pll_cfg = ENET_SERDES_0_PLL_CFG;
921                 break;
922         case 1:
923                 reset_val =  ENET_SERDES_RESET_1;
924                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
925                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
926                 pll_cfg = ENET_SERDES_1_PLL_CFG;
927                 break;
928
929         default:
930                 return -EINVAL;
931         }
932         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
933                     ENET_SERDES_CTRL_SDET_1 |
934                     ENET_SERDES_CTRL_SDET_2 |
935                     ENET_SERDES_CTRL_SDET_3 |
936                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
937                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
938                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
939                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
940                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
941                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
942                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
943                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
944         test_cfg_val = 0;
945
946         if (lp->loopback_mode == LOOPBACK_PHY) {
947                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
948                                   ENET_SERDES_TEST_MD_0_SHIFT) |
949                                  (ENET_TEST_MD_PAD_LOOPBACK <<
950                                   ENET_SERDES_TEST_MD_1_SHIFT) |
951                                  (ENET_TEST_MD_PAD_LOOPBACK <<
952                                   ENET_SERDES_TEST_MD_2_SHIFT) |
953                                  (ENET_TEST_MD_PAD_LOOPBACK <<
954                                   ENET_SERDES_TEST_MD_3_SHIFT));
955         }
956
957         nw64(ENET_SERDES_RESET, reset_val);
958         mdelay(20);
959         val_rd = nr64(ENET_SERDES_RESET);
960         val_rd &= ~reset_val;
961         nw64(pll_cfg, val);
962         nw64(ctrl_reg, ctrl_val);
963         nw64(test_cfg_reg, test_cfg_val);
964         nw64(ENET_SERDES_RESET, val_rd);
965         mdelay(2000);
966
967         /* Initialize all 4 lanes of the SERDES.  */
968         for (i = 0; i < 4; i++) {
969                 u32 rxtx_ctrl, glue0;
970
971                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
972                 if (err)
973                         return err;
974                 err = esr_read_glue0(np, i, &glue0);
975                 if (err)
976                         return err;
977
978                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
979                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
980                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
981
982                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
983                            ESR_GLUE_CTRL0_THCNT |
984                            ESR_GLUE_CTRL0_BLTIME);
985                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
986                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
987                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
988                           (BLTIME_300_CYCLES <<
989                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
990
991                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
992                 if (err)
993                         return err;
994                 err = esr_write_glue0(np, i, glue0);
995                 if (err)
996                         return err;
997         }
998
999
1000         sig = nr64(ESR_INT_SIGNALS);
1001         switch (np->port) {
1002         case 0:
1003                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1004                 mask = val;
1005                 break;
1006
1007         case 1:
1008                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1009                 mask = val;
1010                 break;
1011
1012         default:
1013                 return -EINVAL;
1014         }
1015
1016         if ((sig & mask) != val) {
1017                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1018                            np->port, (int)(sig & mask), (int)val);
1019                 return -ENODEV;
1020         }
1021
1022         return 0;
1023 }
1024
1025 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1026 {
1027         struct niu_link_config *lp = &np->link_config;
1028         int link_up;
1029         u64 val;
1030         u16 current_speed;
1031         unsigned long flags;
1032         u8 current_duplex;
1033
1034         link_up = 0;
1035         current_speed = SPEED_INVALID;
1036         current_duplex = DUPLEX_INVALID;
1037
1038         spin_lock_irqsave(&np->lock, flags);
1039
1040         val = nr64_pcs(PCS_MII_STAT);
1041
1042         if (val & PCS_MII_STAT_LINK_STATUS) {
1043                 link_up = 1;
1044                 current_speed = SPEED_1000;
1045                 current_duplex = DUPLEX_FULL;
1046         }
1047
1048         lp->active_speed = current_speed;
1049         lp->active_duplex = current_duplex;
1050         spin_unlock_irqrestore(&np->lock, flags);
1051
1052         *link_up_p = link_up;
1053         return 0;
1054 }
1055
1056 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1057 {
1058         unsigned long flags;
1059         struct niu_link_config *lp = &np->link_config;
1060         int link_up = 0;
1061         int link_ok = 1;
1062         u64 val, val2;
1063         u16 current_speed;
1064         u8 current_duplex;
1065
1066         if (!(np->flags & NIU_FLAGS_10G))
1067                 return link_status_1g_serdes(np, link_up_p);
1068
1069         current_speed = SPEED_INVALID;
1070         current_duplex = DUPLEX_INVALID;
1071         spin_lock_irqsave(&np->lock, flags);
1072
1073         val = nr64_xpcs(XPCS_STATUS(0));
1074         val2 = nr64_mac(XMAC_INTER2);
1075         if (val2 & 0x01000000)
1076                 link_ok = 0;
1077
1078         if ((val & 0x1000ULL) && link_ok) {
1079                 link_up = 1;
1080                 current_speed = SPEED_10000;
1081                 current_duplex = DUPLEX_FULL;
1082         }
1083         lp->active_speed = current_speed;
1084         lp->active_duplex = current_duplex;
1085         spin_unlock_irqrestore(&np->lock, flags);
1086         *link_up_p = link_up;
1087         return 0;
1088 }
1089
1090 static int link_status_mii(struct niu *np, int *link_up_p)
1091 {
1092         struct niu_link_config *lp = &np->link_config;
1093         int err;
1094         int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1095         int supported, advertising, active_speed, active_duplex;
1096
1097         err = mii_read(np, np->phy_addr, MII_BMCR);
1098         if (unlikely(err < 0))
1099                 return err;
1100         bmcr = err;
1101
1102         err = mii_read(np, np->phy_addr, MII_BMSR);
1103         if (unlikely(err < 0))
1104                 return err;
1105         bmsr = err;
1106
1107         err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1108         if (unlikely(err < 0))
1109                 return err;
1110         advert = err;
1111
1112         err = mii_read(np, np->phy_addr, MII_LPA);
1113         if (unlikely(err < 0))
1114                 return err;
1115         lpa = err;
1116
1117         if (likely(bmsr & BMSR_ESTATEN)) {
1118                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1119                 if (unlikely(err < 0))
1120                         return err;
1121                 estatus = err;
1122
1123                 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1124                 if (unlikely(err < 0))
1125                         return err;
1126                 ctrl1000 = err;
1127
1128                 err = mii_read(np, np->phy_addr, MII_STAT1000);
1129                 if (unlikely(err < 0))
1130                         return err;
1131                 stat1000 = err;
1132         } else
1133                 estatus = ctrl1000 = stat1000 = 0;
1134
1135         supported = 0;
1136         if (bmsr & BMSR_ANEGCAPABLE)
1137                 supported |= SUPPORTED_Autoneg;
1138         if (bmsr & BMSR_10HALF)
1139                 supported |= SUPPORTED_10baseT_Half;
1140         if (bmsr & BMSR_10FULL)
1141                 supported |= SUPPORTED_10baseT_Full;
1142         if (bmsr & BMSR_100HALF)
1143                 supported |= SUPPORTED_100baseT_Half;
1144         if (bmsr & BMSR_100FULL)
1145                 supported |= SUPPORTED_100baseT_Full;
1146         if (estatus & ESTATUS_1000_THALF)
1147                 supported |= SUPPORTED_1000baseT_Half;
1148         if (estatus & ESTATUS_1000_TFULL)
1149                 supported |= SUPPORTED_1000baseT_Full;
1150         lp->supported = supported;
1151
1152         advertising = 0;
1153         if (advert & ADVERTISE_10HALF)
1154                 advertising |= ADVERTISED_10baseT_Half;
1155         if (advert & ADVERTISE_10FULL)
1156                 advertising |= ADVERTISED_10baseT_Full;
1157         if (advert & ADVERTISE_100HALF)
1158                 advertising |= ADVERTISED_100baseT_Half;
1159         if (advert & ADVERTISE_100FULL)
1160                 advertising |= ADVERTISED_100baseT_Full;
1161         if (ctrl1000 & ADVERTISE_1000HALF)
1162                 advertising |= ADVERTISED_1000baseT_Half;
1163         if (ctrl1000 & ADVERTISE_1000FULL)
1164                 advertising |= ADVERTISED_1000baseT_Full;
1165
1166         if (bmcr & BMCR_ANENABLE) {
1167                 int neg, neg1000;
1168
1169                 lp->active_autoneg = 1;
1170                 advertising |= ADVERTISED_Autoneg;
1171
1172                 neg = advert & lpa;
1173                 neg1000 = (ctrl1000 << 2) & stat1000;
1174
1175                 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1176                         active_speed = SPEED_1000;
1177                 else if (neg & LPA_100)
1178                         active_speed = SPEED_100;
1179                 else if (neg & (LPA_10HALF | LPA_10FULL))
1180                         active_speed = SPEED_10;
1181                 else
1182                         active_speed = SPEED_INVALID;
1183
1184                 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1185                         active_duplex = DUPLEX_FULL;
1186                 else if (active_speed != SPEED_INVALID)
1187                         active_duplex = DUPLEX_HALF;
1188                 else
1189                         active_duplex = DUPLEX_INVALID;
1190         } else {
1191                 lp->active_autoneg = 0;
1192
1193                 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1194                         active_speed = SPEED_1000;
1195                 else if (bmcr & BMCR_SPEED100)
1196                         active_speed = SPEED_100;
1197                 else
1198                         active_speed = SPEED_10;
1199
1200                 if (bmcr & BMCR_FULLDPLX)
1201                         active_duplex = DUPLEX_FULL;
1202                 else
1203                         active_duplex = DUPLEX_HALF;
1204         }
1205
1206         lp->active_advertising = advertising;
1207         lp->active_speed = active_speed;
1208         lp->active_duplex = active_duplex;
1209         *link_up_p = !!(bmsr & BMSR_LSTATUS);
1210
1211         return 0;
1212 }
1213
1214 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1215 {
1216         struct niu_link_config *lp = &np->link_config;
1217         u16 current_speed, bmsr;
1218         unsigned long flags;
1219         u8 current_duplex;
1220         int err, link_up;
1221
1222         link_up = 0;
1223         current_speed = SPEED_INVALID;
1224         current_duplex = DUPLEX_INVALID;
1225
1226         spin_lock_irqsave(&np->lock, flags);
1227
1228         err = -EINVAL;
1229
1230         err = mii_read(np, np->phy_addr, MII_BMSR);
1231         if (err < 0)
1232                 goto out;
1233
1234         bmsr = err;
1235         if (bmsr & BMSR_LSTATUS) {
1236                 u16 adv, lpa, common, estat;
1237
1238                 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1239                 if (err < 0)
1240                         goto out;
1241                 adv = err;
1242
1243                 err = mii_read(np, np->phy_addr, MII_LPA);
1244                 if (err < 0)
1245                         goto out;
1246                 lpa = err;
1247
1248                 common = adv & lpa;
1249
1250                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1251                 if (err < 0)
1252                         goto out;
1253                 estat = err;
1254                 link_up = 1;
1255                 current_speed = SPEED_1000;
1256                 current_duplex = DUPLEX_FULL;
1257
1258         }
1259         lp->active_speed = current_speed;
1260         lp->active_duplex = current_duplex;
1261         err = 0;
1262
1263 out:
1264         spin_unlock_irqrestore(&np->lock, flags);
1265
1266         *link_up_p = link_up;
1267         return err;
1268 }
1269
1270 static int link_status_1g(struct niu *np, int *link_up_p)
1271 {
1272         struct niu_link_config *lp = &np->link_config;
1273         unsigned long flags;
1274         int err;
1275
1276         spin_lock_irqsave(&np->lock, flags);
1277
1278         err = link_status_mii(np, link_up_p);
1279         lp->supported |= SUPPORTED_TP;
1280         lp->active_advertising |= ADVERTISED_TP;
1281
1282         spin_unlock_irqrestore(&np->lock, flags);
1283         return err;
1284 }
1285
1286 static int bcm8704_reset(struct niu *np)
1287 {
1288         int err, limit;
1289
1290         err = mdio_read(np, np->phy_addr,
1291                         BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1292         if (err < 0 || err == 0xffff)
1293                 return err;
1294         err |= BMCR_RESET;
1295         err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1296                          MII_BMCR, err);
1297         if (err)
1298                 return err;
1299
1300         limit = 1000;
1301         while (--limit >= 0) {
1302                 err = mdio_read(np, np->phy_addr,
1303                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1304                 if (err < 0)
1305                         return err;
1306                 if (!(err & BMCR_RESET))
1307                         break;
1308         }
1309         if (limit < 0) {
1310                 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1311                            np->port, (err & 0xffff));
1312                 return -ENODEV;
1313         }
1314         return 0;
1315 }
1316
1317 /* When written, certain PHY registers need to be read back twice
1318  * in order for the bits to settle properly.
1319  */
1320 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1321 {
1322         int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1323         if (err < 0)
1324                 return err;
1325         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1326         if (err < 0)
1327                 return err;
1328         return 0;
1329 }
1330
1331 static int bcm8706_init_user_dev3(struct niu *np)
1332 {
1333         int err;
1334
1335
1336         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1337                         BCM8704_USER_OPT_DIGITAL_CTRL);
1338         if (err < 0)
1339                 return err;
1340         err &= ~USER_ODIG_CTRL_GPIOS;
1341         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1342         err |=  USER_ODIG_CTRL_RESV2;
1343         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1344                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1345         if (err)
1346                 return err;
1347
1348         mdelay(1000);
1349
1350         return 0;
1351 }
1352
1353 static int bcm8704_init_user_dev3(struct niu *np)
1354 {
1355         int err;
1356
1357         err = mdio_write(np, np->phy_addr,
1358                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1359                          (USER_CONTROL_OPTXRST_LVL |
1360                           USER_CONTROL_OPBIASFLT_LVL |
1361                           USER_CONTROL_OBTMPFLT_LVL |
1362                           USER_CONTROL_OPPRFLT_LVL |
1363                           USER_CONTROL_OPTXFLT_LVL |
1364                           USER_CONTROL_OPRXLOS_LVL |
1365                           USER_CONTROL_OPRXFLT_LVL |
1366                           USER_CONTROL_OPTXON_LVL |
1367                           (0x3f << USER_CONTROL_RES1_SHIFT)));
1368         if (err)
1369                 return err;
1370
1371         err = mdio_write(np, np->phy_addr,
1372                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1373                          (USER_PMD_TX_CTL_XFP_CLKEN |
1374                           (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1375                           (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1376                           USER_PMD_TX_CTL_TSCK_LPWREN));
1377         if (err)
1378                 return err;
1379
1380         err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1381         if (err)
1382                 return err;
1383         err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1384         if (err)
1385                 return err;
1386
1387         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1388                         BCM8704_USER_OPT_DIGITAL_CTRL);
1389         if (err < 0)
1390                 return err;
1391         err &= ~USER_ODIG_CTRL_GPIOS;
1392         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1393         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1394                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1395         if (err)
1396                 return err;
1397
1398         mdelay(1000);
1399
1400         return 0;
1401 }
1402
1403 static int mrvl88x2011_act_led(struct niu *np, int val)
1404 {
1405         int     err;
1406
1407         err  = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1408                 MRVL88X2011_LED_8_TO_11_CTL);
1409         if (err < 0)
1410                 return err;
1411
1412         err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1413         err |=  MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1414
1415         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1416                           MRVL88X2011_LED_8_TO_11_CTL, err);
1417 }
1418
1419 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1420 {
1421         int     err;
1422
1423         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1424                         MRVL88X2011_LED_BLINK_CTL);
1425         if (err >= 0) {
1426                 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1427                 err |= (rate << 4);
1428
1429                 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1430                                  MRVL88X2011_LED_BLINK_CTL, err);
1431         }
1432
1433         return err;
1434 }
1435
1436 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1437 {
1438         int     err;
1439
1440         /* Set LED functions */
1441         err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1442         if (err)
1443                 return err;
1444
1445         /* led activity */
1446         err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1447         if (err)
1448                 return err;
1449
1450         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1451                         MRVL88X2011_GENERAL_CTL);
1452         if (err < 0)
1453                 return err;
1454
1455         err |= MRVL88X2011_ENA_XFPREFCLK;
1456
1457         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1458                          MRVL88X2011_GENERAL_CTL, err);
1459         if (err < 0)
1460                 return err;
1461
1462         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1463                         MRVL88X2011_PMA_PMD_CTL_1);
1464         if (err < 0)
1465                 return err;
1466
1467         if (np->link_config.loopback_mode == LOOPBACK_MAC)
1468                 err |= MRVL88X2011_LOOPBACK;
1469         else
1470                 err &= ~MRVL88X2011_LOOPBACK;
1471
1472         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1473                          MRVL88X2011_PMA_PMD_CTL_1, err);
1474         if (err < 0)
1475                 return err;
1476
1477         /* Enable PMD  */
1478         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1479                           MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1480 }
1481
1482
1483 static int xcvr_diag_bcm870x(struct niu *np)
1484 {
1485         u16 analog_stat0, tx_alarm_status;
1486         int err = 0;
1487
1488 #if 1
1489         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1490                         MII_STAT1000);
1491         if (err < 0)
1492                 return err;
1493         pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
1494
1495         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1496         if (err < 0)
1497                 return err;
1498         pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
1499
1500         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1501                         MII_NWAYTEST);
1502         if (err < 0)
1503                 return err;
1504         pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
1505 #endif
1506
1507         /* XXX dig this out it might not be so useful XXX */
1508         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1509                         BCM8704_USER_ANALOG_STATUS0);
1510         if (err < 0)
1511                 return err;
1512         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1513                         BCM8704_USER_ANALOG_STATUS0);
1514         if (err < 0)
1515                 return err;
1516         analog_stat0 = err;
1517
1518         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1519                         BCM8704_USER_TX_ALARM_STATUS);
1520         if (err < 0)
1521                 return err;
1522         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1523                         BCM8704_USER_TX_ALARM_STATUS);
1524         if (err < 0)
1525                 return err;
1526         tx_alarm_status = err;
1527
1528         if (analog_stat0 != 0x03fc) {
1529                 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1530                         pr_info("Port %u cable not connected or bad cable\n",
1531                                 np->port);
1532                 } else if (analog_stat0 == 0x639c) {
1533                         pr_info("Port %u optical module is bad or missing\n",
1534                                 np->port);
1535                 }
1536         }
1537
1538         return 0;
1539 }
1540
1541 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1542 {
1543         struct niu_link_config *lp = &np->link_config;
1544         int err;
1545
1546         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1547                         MII_BMCR);
1548         if (err < 0)
1549                 return err;
1550
1551         err &= ~BMCR_LOOPBACK;
1552
1553         if (lp->loopback_mode == LOOPBACK_MAC)
1554                 err |= BMCR_LOOPBACK;
1555
1556         err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1557                          MII_BMCR, err);
1558         if (err)
1559                 return err;
1560
1561         return 0;
1562 }
1563
1564 static int xcvr_init_10g_bcm8706(struct niu *np)
1565 {
1566         int err = 0;
1567         u64 val;
1568
1569         if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1570             (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1571                         return err;
1572
1573         val = nr64_mac(XMAC_CONFIG);
1574         val &= ~XMAC_CONFIG_LED_POLARITY;
1575         val |= XMAC_CONFIG_FORCE_LED_ON;
1576         nw64_mac(XMAC_CONFIG, val);
1577
1578         val = nr64(MIF_CONFIG);
1579         val |= MIF_CONFIG_INDIRECT_MODE;
1580         nw64(MIF_CONFIG, val);
1581
1582         err = bcm8704_reset(np);
1583         if (err)
1584                 return err;
1585
1586         err = xcvr_10g_set_lb_bcm870x(np);
1587         if (err)
1588                 return err;
1589
1590         err = bcm8706_init_user_dev3(np);
1591         if (err)
1592                 return err;
1593
1594         err = xcvr_diag_bcm870x(np);
1595         if (err)
1596                 return err;
1597
1598         return 0;
1599 }
1600
1601 static int xcvr_init_10g_bcm8704(struct niu *np)
1602 {
1603         int err;
1604
1605         err = bcm8704_reset(np);
1606         if (err)
1607                 return err;
1608
1609         err = bcm8704_init_user_dev3(np);
1610         if (err)
1611                 return err;
1612
1613         err = xcvr_10g_set_lb_bcm870x(np);
1614         if (err)
1615                 return err;
1616
1617         err =  xcvr_diag_bcm870x(np);
1618         if (err)
1619                 return err;
1620
1621         return 0;
1622 }
1623
1624 static int xcvr_init_10g(struct niu *np)
1625 {
1626         int phy_id, err;
1627         u64 val;
1628
1629         val = nr64_mac(XMAC_CONFIG);
1630         val &= ~XMAC_CONFIG_LED_POLARITY;
1631         val |= XMAC_CONFIG_FORCE_LED_ON;
1632         nw64_mac(XMAC_CONFIG, val);
1633
1634         /* XXX shared resource, lock parent XXX */
1635         val = nr64(MIF_CONFIG);
1636         val |= MIF_CONFIG_INDIRECT_MODE;
1637         nw64(MIF_CONFIG, val);
1638
1639         phy_id = phy_decode(np->parent->port_phy, np->port);
1640         phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1641
1642         /* handle different phy types */
1643         switch (phy_id & NIU_PHY_ID_MASK) {
1644         case NIU_PHY_ID_MRVL88X2011:
1645                 err = xcvr_init_10g_mrvl88x2011(np);
1646                 break;
1647
1648         default: /* bcom 8704 */
1649                 err = xcvr_init_10g_bcm8704(np);
1650                 break;
1651         }
1652
1653         return 0;
1654 }
1655
1656 static int mii_reset(struct niu *np)
1657 {
1658         int limit, err;
1659
1660         err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1661         if (err)
1662                 return err;
1663
1664         limit = 1000;
1665         while (--limit >= 0) {
1666                 udelay(500);
1667                 err = mii_read(np, np->phy_addr, MII_BMCR);
1668                 if (err < 0)
1669                         return err;
1670                 if (!(err & BMCR_RESET))
1671                         break;
1672         }
1673         if (limit < 0) {
1674                 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1675                            np->port, err);
1676                 return -ENODEV;
1677         }
1678
1679         return 0;
1680 }
1681
1682 static int xcvr_init_1g_rgmii(struct niu *np)
1683 {
1684         int err;
1685         u64 val;
1686         u16 bmcr, bmsr, estat;
1687
1688         val = nr64(MIF_CONFIG);
1689         val &= ~MIF_CONFIG_INDIRECT_MODE;
1690         nw64(MIF_CONFIG, val);
1691
1692         err = mii_reset(np);
1693         if (err)
1694                 return err;
1695
1696         err = mii_read(np, np->phy_addr, MII_BMSR);
1697         if (err < 0)
1698                 return err;
1699         bmsr = err;
1700
1701         estat = 0;
1702         if (bmsr & BMSR_ESTATEN) {
1703                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1704                 if (err < 0)
1705                         return err;
1706                 estat = err;
1707         }
1708
1709         bmcr = 0;
1710         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1711         if (err)
1712                 return err;
1713
1714         if (bmsr & BMSR_ESTATEN) {
1715                 u16 ctrl1000 = 0;
1716
1717                 if (estat & ESTATUS_1000_TFULL)
1718                         ctrl1000 |= ADVERTISE_1000FULL;
1719                 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1720                 if (err)
1721                         return err;
1722         }
1723
1724         bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1725
1726         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1727         if (err)
1728                 return err;
1729
1730         err = mii_read(np, np->phy_addr, MII_BMCR);
1731         if (err < 0)
1732                 return err;
1733         bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1734
1735         err = mii_read(np, np->phy_addr, MII_BMSR);
1736         if (err < 0)
1737                 return err;
1738
1739         return 0;
1740 }
1741
1742 static int mii_init_common(struct niu *np)
1743 {
1744         struct niu_link_config *lp = &np->link_config;
1745         u16 bmcr, bmsr, adv, estat;
1746         int err;
1747
1748         err = mii_reset(np);
1749         if (err)
1750                 return err;
1751
1752         err = mii_read(np, np->phy_addr, MII_BMSR);
1753         if (err < 0)
1754                 return err;
1755         bmsr = err;
1756
1757         estat = 0;
1758         if (bmsr & BMSR_ESTATEN) {
1759                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1760                 if (err < 0)
1761                         return err;
1762                 estat = err;
1763         }
1764
1765         bmcr = 0;
1766         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1767         if (err)
1768                 return err;
1769
1770         if (lp->loopback_mode == LOOPBACK_MAC) {
1771                 bmcr |= BMCR_LOOPBACK;
1772                 if (lp->active_speed == SPEED_1000)
1773                         bmcr |= BMCR_SPEED1000;
1774                 if (lp->active_duplex == DUPLEX_FULL)
1775                         bmcr |= BMCR_FULLDPLX;
1776         }
1777
1778         if (lp->loopback_mode == LOOPBACK_PHY) {
1779                 u16 aux;
1780
1781                 aux = (BCM5464R_AUX_CTL_EXT_LB |
1782                        BCM5464R_AUX_CTL_WRITE_1);
1783                 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1784                 if (err)
1785                         return err;
1786         }
1787
1788         if (lp->autoneg) {
1789                 u16 ctrl1000;
1790
1791                 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1792                 if ((bmsr & BMSR_10HALF) &&
1793                         (lp->advertising & ADVERTISED_10baseT_Half))
1794                         adv |= ADVERTISE_10HALF;
1795                 if ((bmsr & BMSR_10FULL) &&
1796                         (lp->advertising & ADVERTISED_10baseT_Full))
1797                         adv |= ADVERTISE_10FULL;
1798                 if ((bmsr & BMSR_100HALF) &&
1799                         (lp->advertising & ADVERTISED_100baseT_Half))
1800                         adv |= ADVERTISE_100HALF;
1801                 if ((bmsr & BMSR_100FULL) &&
1802                         (lp->advertising & ADVERTISED_100baseT_Full))
1803                         adv |= ADVERTISE_100FULL;
1804                 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1805                 if (err)
1806                         return err;
1807
1808                 if (likely(bmsr & BMSR_ESTATEN)) {
1809                         ctrl1000 = 0;
1810                         if ((estat & ESTATUS_1000_THALF) &&
1811                                 (lp->advertising & ADVERTISED_1000baseT_Half))
1812                                 ctrl1000 |= ADVERTISE_1000HALF;
1813                         if ((estat & ESTATUS_1000_TFULL) &&
1814                                 (lp->advertising & ADVERTISED_1000baseT_Full))
1815                                 ctrl1000 |= ADVERTISE_1000FULL;
1816                         err = mii_write(np, np->phy_addr,
1817                                         MII_CTRL1000, ctrl1000);
1818                         if (err)
1819                                 return err;
1820                 }
1821
1822                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1823         } else {
1824                 /* !lp->autoneg */
1825                 int fulldpx;
1826
1827                 if (lp->duplex == DUPLEX_FULL) {
1828                         bmcr |= BMCR_FULLDPLX;
1829                         fulldpx = 1;
1830                 } else if (lp->duplex == DUPLEX_HALF)
1831                         fulldpx = 0;
1832                 else
1833                         return -EINVAL;
1834
1835                 if (lp->speed == SPEED_1000) {
1836                         /* if X-full requested while not supported, or
1837                            X-half requested while not supported... */
1838                         if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1839                                 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1840                                 return -EINVAL;
1841                         bmcr |= BMCR_SPEED1000;
1842                 } else if (lp->speed == SPEED_100) {
1843                         if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1844                                 (!fulldpx && !(bmsr & BMSR_100HALF)))
1845                                 return -EINVAL;
1846                         bmcr |= BMCR_SPEED100;
1847                 } else if (lp->speed == SPEED_10) {
1848                         if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1849                                 (!fulldpx && !(bmsr & BMSR_10HALF)))
1850                                 return -EINVAL;
1851                 } else
1852                         return -EINVAL;
1853         }
1854
1855         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1856         if (err)
1857                 return err;
1858
1859 #if 0
1860         err = mii_read(np, np->phy_addr, MII_BMCR);
1861         if (err < 0)
1862                 return err;
1863         bmcr = err;
1864
1865         err = mii_read(np, np->phy_addr, MII_BMSR);
1866         if (err < 0)
1867                 return err;
1868         bmsr = err;
1869
1870         pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1871                 np->port, bmcr, bmsr);
1872 #endif
1873
1874         return 0;
1875 }
1876
1877 static int xcvr_init_1g(struct niu *np)
1878 {
1879         u64 val;
1880
1881         /* XXX shared resource, lock parent XXX */
1882         val = nr64(MIF_CONFIG);
1883         val &= ~MIF_CONFIG_INDIRECT_MODE;
1884         nw64(MIF_CONFIG, val);
1885
1886         return mii_init_common(np);
1887 }
1888
1889 static int niu_xcvr_init(struct niu *np)
1890 {
1891         const struct niu_phy_ops *ops = np->phy_ops;
1892         int err;
1893
1894         err = 0;
1895         if (ops->xcvr_init)
1896                 err = ops->xcvr_init(np);
1897
1898         return err;
1899 }
1900
1901 static int niu_serdes_init(struct niu *np)
1902 {
1903         const struct niu_phy_ops *ops = np->phy_ops;
1904         int err;
1905
1906         err = 0;
1907         if (ops->serdes_init)
1908                 err = ops->serdes_init(np);
1909
1910         return err;
1911 }
1912
1913 static void niu_init_xif(struct niu *);
1914 static void niu_handle_led(struct niu *, int status);
1915
1916 static int niu_link_status_common(struct niu *np, int link_up)
1917 {
1918         struct niu_link_config *lp = &np->link_config;
1919         struct net_device *dev = np->dev;
1920         unsigned long flags;
1921
1922         if (!netif_carrier_ok(dev) && link_up) {
1923                 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1924                            lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1925                            lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1926                            lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1927                            "10Mbit/sec",
1928                            lp->active_duplex == DUPLEX_FULL ? "full" : "half");
1929
1930                 spin_lock_irqsave(&np->lock, flags);
1931                 niu_init_xif(np);
1932                 niu_handle_led(np, 1);
1933                 spin_unlock_irqrestore(&np->lock, flags);
1934
1935                 netif_carrier_on(dev);
1936         } else if (netif_carrier_ok(dev) && !link_up) {
1937                 netif_warn(np, link, dev, "Link is down\n");
1938                 spin_lock_irqsave(&np->lock, flags);
1939                 niu_handle_led(np, 0);
1940                 spin_unlock_irqrestore(&np->lock, flags);
1941                 netif_carrier_off(dev);
1942         }
1943
1944         return 0;
1945 }
1946
1947 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1948 {
1949         int err, link_up, pma_status, pcs_status;
1950
1951         link_up = 0;
1952
1953         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1954                         MRVL88X2011_10G_PMD_STATUS_2);
1955         if (err < 0)
1956                 goto out;
1957
1958         /* Check PMA/PMD Register: 1.0001.2 == 1 */
1959         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1960                         MRVL88X2011_PMA_PMD_STATUS_1);
1961         if (err < 0)
1962                 goto out;
1963
1964         pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1965
1966         /* Check PMC Register : 3.0001.2 == 1: read twice */
1967         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1968                         MRVL88X2011_PMA_PMD_STATUS_1);
1969         if (err < 0)
1970                 goto out;
1971
1972         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1973                         MRVL88X2011_PMA_PMD_STATUS_1);
1974         if (err < 0)
1975                 goto out;
1976
1977         pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1978
1979         /* Check XGXS Register : 4.0018.[0-3,12] */
1980         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1981                         MRVL88X2011_10G_XGXS_LANE_STAT);
1982         if (err < 0)
1983                 goto out;
1984
1985         if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1986                     PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1987                     PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1988                     0x800))
1989                 link_up = (pma_status && pcs_status) ? 1 : 0;
1990
1991         np->link_config.active_speed = SPEED_10000;
1992         np->link_config.active_duplex = DUPLEX_FULL;
1993         err = 0;
1994 out:
1995         mrvl88x2011_act_led(np, (link_up ?
1996                                  MRVL88X2011_LED_CTL_PCS_ACT :
1997                                  MRVL88X2011_LED_CTL_OFF));
1998
1999         *link_up_p = link_up;
2000         return err;
2001 }
2002
2003 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2004 {
2005         int err, link_up;
2006         link_up = 0;
2007
2008         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2009                         BCM8704_PMD_RCV_SIGDET);
2010         if (err < 0 || err == 0xffff)
2011                 goto out;
2012         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2013                 err = 0;
2014                 goto out;
2015         }
2016
2017         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2018                         BCM8704_PCS_10G_R_STATUS);
2019         if (err < 0)
2020                 goto out;
2021
2022         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2023                 err = 0;
2024                 goto out;
2025         }
2026
2027         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2028                         BCM8704_PHYXS_XGXS_LANE_STAT);
2029         if (err < 0)
2030                 goto out;
2031         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2032                     PHYXS_XGXS_LANE_STAT_MAGIC |
2033                     PHYXS_XGXS_LANE_STAT_PATTEST |
2034                     PHYXS_XGXS_LANE_STAT_LANE3 |
2035                     PHYXS_XGXS_LANE_STAT_LANE2 |
2036                     PHYXS_XGXS_LANE_STAT_LANE1 |
2037                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2038                 err = 0;
2039                 np->link_config.active_speed = SPEED_INVALID;
2040                 np->link_config.active_duplex = DUPLEX_INVALID;
2041                 goto out;
2042         }
2043
2044         link_up = 1;
2045         np->link_config.active_speed = SPEED_10000;
2046         np->link_config.active_duplex = DUPLEX_FULL;
2047         err = 0;
2048
2049 out:
2050         *link_up_p = link_up;
2051         return err;
2052 }
2053
2054 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2055 {
2056         int err, link_up;
2057
2058         link_up = 0;
2059
2060         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2061                         BCM8704_PMD_RCV_SIGDET);
2062         if (err < 0)
2063                 goto out;
2064         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2065                 err = 0;
2066                 goto out;
2067         }
2068
2069         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2070                         BCM8704_PCS_10G_R_STATUS);
2071         if (err < 0)
2072                 goto out;
2073         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2074                 err = 0;
2075                 goto out;
2076         }
2077
2078         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2079                         BCM8704_PHYXS_XGXS_LANE_STAT);
2080         if (err < 0)
2081                 goto out;
2082
2083         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2084                     PHYXS_XGXS_LANE_STAT_MAGIC |
2085                     PHYXS_XGXS_LANE_STAT_LANE3 |
2086                     PHYXS_XGXS_LANE_STAT_LANE2 |
2087                     PHYXS_XGXS_LANE_STAT_LANE1 |
2088                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2089                 err = 0;
2090                 goto out;
2091         }
2092
2093         link_up = 1;
2094         np->link_config.active_speed = SPEED_10000;
2095         np->link_config.active_duplex = DUPLEX_FULL;
2096         err = 0;
2097
2098 out:
2099         *link_up_p = link_up;
2100         return err;
2101 }
2102
2103 static int link_status_10g(struct niu *np, int *link_up_p)
2104 {
2105         unsigned long flags;
2106         int err = -EINVAL;
2107
2108         spin_lock_irqsave(&np->lock, flags);
2109
2110         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2111                 int phy_id;
2112
2113                 phy_id = phy_decode(np->parent->port_phy, np->port);
2114                 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2115
2116                 /* handle different phy types */
2117                 switch (phy_id & NIU_PHY_ID_MASK) {
2118                 case NIU_PHY_ID_MRVL88X2011:
2119                         err = link_status_10g_mrvl(np, link_up_p);
2120                         break;
2121
2122                 default: /* bcom 8704 */
2123                         err = link_status_10g_bcom(np, link_up_p);
2124                         break;
2125                 }
2126         }
2127
2128         spin_unlock_irqrestore(&np->lock, flags);
2129
2130         return err;
2131 }
2132
2133 static int niu_10g_phy_present(struct niu *np)
2134 {
2135         u64 sig, mask, val;
2136
2137         sig = nr64(ESR_INT_SIGNALS);
2138         switch (np->port) {
2139         case 0:
2140                 mask = ESR_INT_SIGNALS_P0_BITS;
2141                 val = (ESR_INT_SRDY0_P0 |
2142                        ESR_INT_DET0_P0 |
2143                        ESR_INT_XSRDY_P0 |
2144                        ESR_INT_XDP_P0_CH3 |
2145                        ESR_INT_XDP_P0_CH2 |
2146                        ESR_INT_XDP_P0_CH1 |
2147                        ESR_INT_XDP_P0_CH0);
2148                 break;
2149
2150         case 1:
2151                 mask = ESR_INT_SIGNALS_P1_BITS;
2152                 val = (ESR_INT_SRDY0_P1 |
2153                        ESR_INT_DET0_P1 |
2154                        ESR_INT_XSRDY_P1 |
2155                        ESR_INT_XDP_P1_CH3 |
2156                        ESR_INT_XDP_P1_CH2 |
2157                        ESR_INT_XDP_P1_CH1 |
2158                        ESR_INT_XDP_P1_CH0);
2159                 break;
2160
2161         default:
2162                 return 0;
2163         }
2164
2165         if ((sig & mask) != val)
2166                 return 0;
2167         return 1;
2168 }
2169
2170 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2171 {
2172         unsigned long flags;
2173         int err = 0;
2174         int phy_present;
2175         int phy_present_prev;
2176
2177         spin_lock_irqsave(&np->lock, flags);
2178
2179         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2180                 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2181                         1 : 0;
2182                 phy_present = niu_10g_phy_present(np);
2183                 if (phy_present != phy_present_prev) {
2184                         /* state change */
2185                         if (phy_present) {
2186                                 /* A NEM was just plugged in */
2187                                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2188                                 if (np->phy_ops->xcvr_init)
2189                                         err = np->phy_ops->xcvr_init(np);
2190                                 if (err) {
2191                                         err = mdio_read(np, np->phy_addr,
2192                                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2193                                         if (err == 0xffff) {
2194                                                 /* No mdio, back-to-back XAUI */
2195                                                 goto out;
2196                                         }
2197                                         /* debounce */
2198                                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2199                                 }
2200                         } else {
2201                                 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2202                                 *link_up_p = 0;
2203                                 netif_warn(np, link, np->dev,
2204                                            "Hotplug PHY Removed\n");
2205                         }
2206                 }
2207 out:
2208                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
2209                         err = link_status_10g_bcm8706(np, link_up_p);
2210                         if (err == 0xffff) {
2211                                 /* No mdio, back-to-back XAUI: it is C10NEM */
2212                                 *link_up_p = 1;
2213                                 np->link_config.active_speed = SPEED_10000;
2214                                 np->link_config.active_duplex = DUPLEX_FULL;
2215                         }
2216                 }
2217         }
2218
2219         spin_unlock_irqrestore(&np->lock, flags);
2220
2221         return 0;
2222 }
2223
2224 static int niu_link_status(struct niu *np, int *link_up_p)
2225 {
2226         const struct niu_phy_ops *ops = np->phy_ops;
2227         int err;
2228
2229         err = 0;
2230         if (ops->link_status)
2231                 err = ops->link_status(np, link_up_p);
2232
2233         return err;
2234 }
2235
2236 static void niu_timer(unsigned long __opaque)
2237 {
2238         struct niu *np = (struct niu *) __opaque;
2239         unsigned long off;
2240         int err, link_up;
2241
2242         err = niu_link_status(np, &link_up);
2243         if (!err)
2244                 niu_link_status_common(np, link_up);
2245
2246         if (netif_carrier_ok(np->dev))
2247                 off = 5 * HZ;
2248         else
2249                 off = 1 * HZ;
2250         np->timer.expires = jiffies + off;
2251
2252         add_timer(&np->timer);
2253 }
2254
2255 static const struct niu_phy_ops phy_ops_10g_serdes = {
2256         .serdes_init            = serdes_init_10g_serdes,
2257         .link_status            = link_status_10g_serdes,
2258 };
2259
2260 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2261         .serdes_init            = serdes_init_niu_10g_serdes,
2262         .link_status            = link_status_10g_serdes,
2263 };
2264
2265 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2266         .serdes_init            = serdes_init_niu_1g_serdes,
2267         .link_status            = link_status_1g_serdes,
2268 };
2269
2270 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2271         .xcvr_init              = xcvr_init_1g_rgmii,
2272         .link_status            = link_status_1g_rgmii,
2273 };
2274
2275 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2276         .serdes_init            = serdes_init_niu_10g_fiber,
2277         .xcvr_init              = xcvr_init_10g,
2278         .link_status            = link_status_10g,
2279 };
2280
2281 static const struct niu_phy_ops phy_ops_10g_fiber = {
2282         .serdes_init            = serdes_init_10g,
2283         .xcvr_init              = xcvr_init_10g,
2284         .link_status            = link_status_10g,
2285 };
2286
2287 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2288         .serdes_init            = serdes_init_10g,
2289         .xcvr_init              = xcvr_init_10g_bcm8706,
2290         .link_status            = link_status_10g_hotplug,
2291 };
2292
2293 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2294         .serdes_init            = serdes_init_niu_10g_fiber,
2295         .xcvr_init              = xcvr_init_10g_bcm8706,
2296         .link_status            = link_status_10g_hotplug,
2297 };
2298
2299 static const struct niu_phy_ops phy_ops_10g_copper = {
2300         .serdes_init            = serdes_init_10g,
2301         .link_status            = link_status_10g, /* XXX */
2302 };
2303
2304 static const struct niu_phy_ops phy_ops_1g_fiber = {
2305         .serdes_init            = serdes_init_1g,
2306         .xcvr_init              = xcvr_init_1g,
2307         .link_status            = link_status_1g,
2308 };
2309
2310 static const struct niu_phy_ops phy_ops_1g_copper = {
2311         .xcvr_init              = xcvr_init_1g,
2312         .link_status            = link_status_1g,
2313 };
2314
2315 struct niu_phy_template {
2316         const struct niu_phy_ops        *ops;
2317         u32                             phy_addr_base;
2318 };
2319
2320 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2321         .ops            = &phy_ops_10g_fiber_niu,
2322         .phy_addr_base  = 16,
2323 };
2324
2325 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2326         .ops            = &phy_ops_10g_serdes_niu,
2327         .phy_addr_base  = 0,
2328 };
2329
2330 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2331         .ops            = &phy_ops_1g_serdes_niu,
2332         .phy_addr_base  = 0,
2333 };
2334
2335 static const struct niu_phy_template phy_template_10g_fiber = {
2336         .ops            = &phy_ops_10g_fiber,
2337         .phy_addr_base  = 8,
2338 };
2339
2340 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2341         .ops            = &phy_ops_10g_fiber_hotplug,
2342         .phy_addr_base  = 8,
2343 };
2344
2345 static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2346         .ops            = &phy_ops_niu_10g_hotplug,
2347         .phy_addr_base  = 8,
2348 };
2349
2350 static const struct niu_phy_template phy_template_10g_copper = {
2351         .ops            = &phy_ops_10g_copper,
2352         .phy_addr_base  = 10,
2353 };
2354
2355 static const struct niu_phy_template phy_template_1g_fiber = {
2356         .ops            = &phy_ops_1g_fiber,
2357         .phy_addr_base  = 0,
2358 };
2359
2360 static const struct niu_phy_template phy_template_1g_copper = {
2361         .ops            = &phy_ops_1g_copper,
2362         .phy_addr_base  = 0,
2363 };
2364
2365 static const struct niu_phy_template phy_template_1g_rgmii = {
2366         .ops            = &phy_ops_1g_rgmii,
2367         .phy_addr_base  = 0,
2368 };
2369
2370 static const struct niu_phy_template phy_template_10g_serdes = {
2371         .ops            = &phy_ops_10g_serdes,
2372         .phy_addr_base  = 0,
2373 };
2374
2375 static int niu_atca_port_num[4] = {
2376         0, 0,  11, 10
2377 };
2378
2379 static int serdes_init_10g_serdes(struct niu *np)
2380 {
2381         struct niu_link_config *lp = &np->link_config;
2382         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2383         u64 ctrl_val, test_cfg_val, sig, mask, val;
2384         u64 reset_val;
2385
2386         switch (np->port) {
2387         case 0:
2388                 reset_val =  ENET_SERDES_RESET_0;
2389                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2390                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2391                 pll_cfg = ENET_SERDES_0_PLL_CFG;
2392                 break;
2393         case 1:
2394                 reset_val =  ENET_SERDES_RESET_1;
2395                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2396                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2397                 pll_cfg = ENET_SERDES_1_PLL_CFG;
2398                 break;
2399
2400         default:
2401                 return -EINVAL;
2402         }
2403         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2404                     ENET_SERDES_CTRL_SDET_1 |
2405                     ENET_SERDES_CTRL_SDET_2 |
2406                     ENET_SERDES_CTRL_SDET_3 |
2407                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2408                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2409                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2410                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2411                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2412                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2413                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2414                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2415         test_cfg_val = 0;
2416
2417         if (lp->loopback_mode == LOOPBACK_PHY) {
2418                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2419                                   ENET_SERDES_TEST_MD_0_SHIFT) |
2420                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2421                                   ENET_SERDES_TEST_MD_1_SHIFT) |
2422                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2423                                   ENET_SERDES_TEST_MD_2_SHIFT) |
2424                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2425                                   ENET_SERDES_TEST_MD_3_SHIFT));
2426         }
2427
2428         esr_reset(np);
2429         nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2430         nw64(ctrl_reg, ctrl_val);
2431         nw64(test_cfg_reg, test_cfg_val);
2432
2433         /* Initialize all 4 lanes of the SERDES.  */
2434         for (i = 0; i < 4; i++) {
2435                 u32 rxtx_ctrl, glue0;
2436                 int err;
2437
2438                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2439                 if (err)
2440                         return err;
2441                 err = esr_read_glue0(np, i, &glue0);
2442                 if (err)
2443                         return err;
2444
2445                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2446                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2447                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2448
2449                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2450                            ESR_GLUE_CTRL0_THCNT |
2451                            ESR_GLUE_CTRL0_BLTIME);
2452                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2453                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2454                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2455                           (BLTIME_300_CYCLES <<
2456                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
2457
2458                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2459                 if (err)
2460                         return err;
2461                 err = esr_write_glue0(np, i, glue0);
2462                 if (err)
2463                         return err;
2464         }
2465
2466
2467         sig = nr64(ESR_INT_SIGNALS);
2468         switch (np->port) {
2469         case 0:
2470                 mask = ESR_INT_SIGNALS_P0_BITS;
2471                 val = (ESR_INT_SRDY0_P0 |
2472                        ESR_INT_DET0_P0 |
2473                        ESR_INT_XSRDY_P0 |
2474                        ESR_INT_XDP_P0_CH3 |
2475                        ESR_INT_XDP_P0_CH2 |
2476                        ESR_INT_XDP_P0_CH1 |
2477                        ESR_INT_XDP_P0_CH0);
2478                 break;
2479
2480         case 1:
2481                 mask = ESR_INT_SIGNALS_P1_BITS;
2482                 val = (ESR_INT_SRDY0_P1 |
2483                        ESR_INT_DET0_P1 |
2484                        ESR_INT_XSRDY_P1 |
2485                        ESR_INT_XDP_P1_CH3 |
2486                        ESR_INT_XDP_P1_CH2 |
2487                        ESR_INT_XDP_P1_CH1 |
2488                        ESR_INT_XDP_P1_CH0);
2489                 break;
2490
2491         default:
2492                 return -EINVAL;
2493         }
2494
2495         if ((sig & mask) != val) {
2496                 int err;
2497                 err = serdes_init_1g_serdes(np);
2498                 if (!err) {
2499                         np->flags &= ~NIU_FLAGS_10G;
2500                         np->mac_xcvr = MAC_XCVR_PCS;
2501                 }  else {
2502                         netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2503                                    np->port);
2504                         return -ENODEV;
2505                 }
2506         }
2507
2508         return 0;
2509 }
2510
2511 static int niu_determine_phy_disposition(struct niu *np)
2512 {
2513         struct niu_parent *parent = np->parent;
2514         u8 plat_type = parent->plat_type;
2515         const struct niu_phy_template *tp;
2516         u32 phy_addr_off = 0;
2517
2518         if (plat_type == PLAT_TYPE_NIU) {
2519                 switch (np->flags &
2520                         (NIU_FLAGS_10G |
2521                          NIU_FLAGS_FIBER |
2522                          NIU_FLAGS_XCVR_SERDES)) {
2523                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2524                         /* 10G Serdes */
2525                         tp = &phy_template_niu_10g_serdes;
2526                         break;
2527                 case NIU_FLAGS_XCVR_SERDES:
2528                         /* 1G Serdes */
2529                         tp = &phy_template_niu_1g_serdes;
2530                         break;
2531                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2532                         /* 10G Fiber */
2533                 default:
2534                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2535                                 tp = &phy_template_niu_10g_hotplug;
2536                                 if (np->port == 0)
2537                                         phy_addr_off = 8;
2538                                 if (np->port == 1)
2539                                         phy_addr_off = 12;
2540                         } else {
2541                                 tp = &phy_template_niu_10g_fiber;
2542                                 phy_addr_off += np->port;
2543                         }
2544                         break;
2545                 }
2546         } else {
2547                 switch (np->flags &
2548                         (NIU_FLAGS_10G |
2549                          NIU_FLAGS_FIBER |
2550                          NIU_FLAGS_XCVR_SERDES)) {
2551                 case 0:
2552                         /* 1G copper */
2553                         tp = &phy_template_1g_copper;
2554                         if (plat_type == PLAT_TYPE_VF_P0)
2555                                 phy_addr_off = 10;
2556                         else if (plat_type == PLAT_TYPE_VF_P1)
2557                                 phy_addr_off = 26;
2558
2559                         phy_addr_off += (np->port ^ 0x3);
2560                         break;
2561
2562                 case NIU_FLAGS_10G:
2563                         /* 10G copper */
2564                         tp = &phy_template_10g_copper;
2565                         break;
2566
2567                 case NIU_FLAGS_FIBER:
2568                         /* 1G fiber */
2569                         tp = &phy_template_1g_fiber;
2570                         break;
2571
2572                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2573                         /* 10G fiber */
2574                         tp = &phy_template_10g_fiber;
2575                         if (plat_type == PLAT_TYPE_VF_P0 ||
2576                             plat_type == PLAT_TYPE_VF_P1)
2577                                 phy_addr_off = 8;
2578                         phy_addr_off += np->port;
2579                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2580                                 tp = &phy_template_10g_fiber_hotplug;
2581                                 if (np->port == 0)
2582                                         phy_addr_off = 8;
2583                                 if (np->port == 1)
2584                                         phy_addr_off = 12;
2585                         }
2586                         break;
2587
2588                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2589                 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2590                 case NIU_FLAGS_XCVR_SERDES:
2591                         switch(np->port) {
2592                         case 0:
2593                         case 1:
2594                                 tp = &phy_template_10g_serdes;
2595                                 break;
2596                         case 2:
2597                         case 3:
2598                                 tp = &phy_template_1g_rgmii;
2599                                 break;
2600                         default:
2601                                 return -EINVAL;
2602                                 break;
2603                         }
2604                         phy_addr_off = niu_atca_port_num[np->port];
2605                         break;
2606
2607                 default:
2608                         return -EINVAL;
2609                 }
2610         }
2611
2612         np->phy_ops = tp->ops;
2613         np->phy_addr = tp->phy_addr_base + phy_addr_off;
2614
2615         return 0;
2616 }
2617
2618 static int niu_init_link(struct niu *np)
2619 {
2620         struct niu_parent *parent = np->parent;
2621         int err, ignore;
2622
2623         if (parent->plat_type == PLAT_TYPE_NIU) {
2624                 err = niu_xcvr_init(np);
2625                 if (err)
2626                         return err;
2627                 msleep(200);
2628         }
2629         err = niu_serdes_init(np);
2630         if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
2631                 return err;
2632         msleep(200);
2633         err = niu_xcvr_init(np);
2634         if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
2635                 niu_link_status(np, &ignore);
2636         return 0;
2637 }
2638
2639 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2640 {
2641         u16 reg0 = addr[4] << 8 | addr[5];
2642         u16 reg1 = addr[2] << 8 | addr[3];
2643         u16 reg2 = addr[0] << 8 | addr[1];
2644
2645         if (np->flags & NIU_FLAGS_XMAC) {
2646                 nw64_mac(XMAC_ADDR0, reg0);
2647                 nw64_mac(XMAC_ADDR1, reg1);
2648                 nw64_mac(XMAC_ADDR2, reg2);
2649         } else {
2650                 nw64_mac(BMAC_ADDR0, reg0);
2651                 nw64_mac(BMAC_ADDR1, reg1);
2652                 nw64_mac(BMAC_ADDR2, reg2);
2653         }
2654 }
2655
2656 static int niu_num_alt_addr(struct niu *np)
2657 {
2658         if (np->flags & NIU_FLAGS_XMAC)
2659                 return XMAC_NUM_ALT_ADDR;
2660         else
2661                 return BMAC_NUM_ALT_ADDR;
2662 }
2663
2664 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2665 {
2666         u16 reg0 = addr[4] << 8 | addr[5];
2667         u16 reg1 = addr[2] << 8 | addr[3];
2668         u16 reg2 = addr[0] << 8 | addr[1];
2669
2670         if (index >= niu_num_alt_addr(np))
2671                 return -EINVAL;
2672
2673         if (np->flags & NIU_FLAGS_XMAC) {
2674                 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2675                 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2676                 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2677         } else {
2678                 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2679                 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2680                 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2681         }
2682
2683         return 0;
2684 }
2685
2686 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2687 {
2688         unsigned long reg;
2689         u64 val, mask;
2690
2691         if (index >= niu_num_alt_addr(np))
2692                 return -EINVAL;
2693
2694         if (np->flags & NIU_FLAGS_XMAC) {
2695                 reg = XMAC_ADDR_CMPEN;
2696                 mask = 1 << index;
2697         } else {
2698                 reg = BMAC_ADDR_CMPEN;
2699                 mask = 1 << (index + 1);
2700         }
2701
2702         val = nr64_mac(reg);
2703         if (on)
2704                 val |= mask;
2705         else
2706                 val &= ~mask;
2707         nw64_mac(reg, val);
2708
2709         return 0;
2710 }
2711
2712 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2713                                    int num, int mac_pref)
2714 {
2715         u64 val = nr64_mac(reg);
2716         val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2717         val |= num;
2718         if (mac_pref)
2719                 val |= HOST_INFO_MPR;
2720         nw64_mac(reg, val);
2721 }
2722
2723 static int __set_rdc_table_num(struct niu *np,
2724                                int xmac_index, int bmac_index,
2725                                int rdc_table_num, int mac_pref)
2726 {
2727         unsigned long reg;
2728
2729         if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2730                 return -EINVAL;
2731         if (np->flags & NIU_FLAGS_XMAC)
2732                 reg = XMAC_HOST_INFO(xmac_index);
2733         else
2734                 reg = BMAC_HOST_INFO(bmac_index);
2735         __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2736         return 0;
2737 }
2738
2739 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2740                                          int mac_pref)
2741 {
2742         return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2743 }
2744
2745 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2746                                            int mac_pref)
2747 {
2748         return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2749 }
2750
2751 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2752                                      int table_num, int mac_pref)
2753 {
2754         if (idx >= niu_num_alt_addr(np))
2755                 return -EINVAL;
2756         return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2757 }
2758
2759 static u64 vlan_entry_set_parity(u64 reg_val)
2760 {
2761         u64 port01_mask;
2762         u64 port23_mask;
2763
2764         port01_mask = 0x00ff;
2765         port23_mask = 0xff00;
2766
2767         if (hweight64(reg_val & port01_mask) & 1)
2768                 reg_val |= ENET_VLAN_TBL_PARITY0;
2769         else
2770                 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2771
2772         if (hweight64(reg_val & port23_mask) & 1)
2773                 reg_val |= ENET_VLAN_TBL_PARITY1;
2774         else
2775                 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2776
2777         return reg_val;
2778 }
2779
2780 static void vlan_tbl_write(struct niu *np, unsigned long index,
2781                            int port, int vpr, int rdc_table)
2782 {
2783         u64 reg_val = nr64(ENET_VLAN_TBL(index));
2784
2785         reg_val &= ~((ENET_VLAN_TBL_VPR |
2786                       ENET_VLAN_TBL_VLANRDCTBLN) <<
2787                      ENET_VLAN_TBL_SHIFT(port));
2788         if (vpr)
2789                 reg_val |= (ENET_VLAN_TBL_VPR <<
2790                             ENET_VLAN_TBL_SHIFT(port));
2791         reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2792
2793         reg_val = vlan_entry_set_parity(reg_val);
2794
2795         nw64(ENET_VLAN_TBL(index), reg_val);
2796 }
2797
2798 static void vlan_tbl_clear(struct niu *np)
2799 {
2800         int i;
2801
2802         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2803                 nw64(ENET_VLAN_TBL(i), 0);
2804 }
2805
2806 static int tcam_wait_bit(struct niu *np, u64 bit)
2807 {
2808         int limit = 1000;
2809
2810         while (--limit > 0) {
2811                 if (nr64(TCAM_CTL) & bit)
2812                         break;
2813                 udelay(1);
2814         }
2815         if (limit <= 0)
2816                 return -ENODEV;
2817
2818         return 0;
2819 }
2820
2821 static int tcam_flush(struct niu *np, int index)
2822 {
2823         nw64(TCAM_KEY_0, 0x00);
2824         nw64(TCAM_KEY_MASK_0, 0xff);
2825         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2826
2827         return tcam_wait_bit(np, TCAM_CTL_STAT);
2828 }
2829
2830 #if 0
2831 static int tcam_read(struct niu *np, int index,
2832                      u64 *key, u64 *mask)
2833 {
2834         int err;
2835
2836         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2837         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2838         if (!err) {
2839                 key[0] = nr64(TCAM_KEY_0);
2840                 key[1] = nr64(TCAM_KEY_1);
2841                 key[2] = nr64(TCAM_KEY_2);
2842                 key[3] = nr64(TCAM_KEY_3);
2843                 mask[0] = nr64(TCAM_KEY_MASK_0);
2844                 mask[1] = nr64(TCAM_KEY_MASK_1);
2845                 mask[2] = nr64(TCAM_KEY_MASK_2);
2846                 mask[3] = nr64(TCAM_KEY_MASK_3);
2847         }
2848         return err;
2849 }
2850 #endif
2851
2852 static int tcam_write(struct niu *np, int index,
2853                       u64 *key, u64 *mask)
2854 {
2855         nw64(TCAM_KEY_0, key[0]);
2856         nw64(TCAM_KEY_1, key[1]);
2857         nw64(TCAM_KEY_2, key[2]);
2858         nw64(TCAM_KEY_3, key[3]);
2859         nw64(TCAM_KEY_MASK_0, mask[0]);
2860         nw64(TCAM_KEY_MASK_1, mask[1]);
2861         nw64(TCAM_KEY_MASK_2, mask[2]);
2862         nw64(TCAM_KEY_MASK_3, mask[3]);
2863         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2864
2865         return tcam_wait_bit(np, TCAM_CTL_STAT);
2866 }
2867
2868 #if 0
2869 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2870 {
2871         int err;
2872
2873         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2874         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2875         if (!err)
2876                 *data = nr64(TCAM_KEY_1);
2877
2878         return err;
2879 }
2880 #endif
2881
2882 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2883 {
2884         nw64(TCAM_KEY_1, assoc_data);
2885         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2886
2887         return tcam_wait_bit(np, TCAM_CTL_STAT);
2888 }
2889
2890 static void tcam_enable(struct niu *np, int on)
2891 {
2892         u64 val = nr64(FFLP_CFG_1);
2893
2894         if (on)
2895                 val &= ~FFLP_CFG_1_TCAM_DIS;
2896         else
2897                 val |= FFLP_CFG_1_TCAM_DIS;
2898         nw64(FFLP_CFG_1, val);
2899 }
2900
2901 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2902 {
2903         u64 val = nr64(FFLP_CFG_1);
2904
2905         val &= ~(FFLP_CFG_1_FFLPINITDONE |
2906                  FFLP_CFG_1_CAMLAT |
2907                  FFLP_CFG_1_CAMRATIO);
2908         val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2909         val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2910         nw64(FFLP_CFG_1, val);
2911
2912         val = nr64(FFLP_CFG_1);
2913         val |= FFLP_CFG_1_FFLPINITDONE;
2914         nw64(FFLP_CFG_1, val);
2915 }
2916
2917 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2918                                       int on)
2919 {
2920         unsigned long reg;
2921         u64 val;
2922
2923         if (class < CLASS_CODE_ETHERTYPE1 ||
2924             class > CLASS_CODE_ETHERTYPE2)
2925                 return -EINVAL;
2926
2927         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2928         val = nr64(reg);
2929         if (on)
2930                 val |= L2_CLS_VLD;
2931         else
2932                 val &= ~L2_CLS_VLD;
2933         nw64(reg, val);
2934
2935         return 0;
2936 }
2937
2938 #if 0
2939 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2940                                    u64 ether_type)
2941 {
2942         unsigned long reg;
2943         u64 val;
2944
2945         if (class < CLASS_CODE_ETHERTYPE1 ||
2946             class > CLASS_CODE_ETHERTYPE2 ||
2947             (ether_type & ~(u64)0xffff) != 0)
2948                 return -EINVAL;
2949
2950         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2951         val = nr64(reg);
2952         val &= ~L2_CLS_ETYPE;
2953         val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2954         nw64(reg, val);
2955
2956         return 0;
2957 }
2958 #endif
2959
2960 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2961                                      int on)
2962 {
2963         unsigned long reg;
2964         u64 val;
2965
2966         if (class < CLASS_CODE_USER_PROG1 ||
2967             class > CLASS_CODE_USER_PROG4)
2968                 return -EINVAL;
2969
2970         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2971         val = nr64(reg);
2972         if (on)
2973                 val |= L3_CLS_VALID;
2974         else
2975                 val &= ~L3_CLS_VALID;
2976         nw64(reg, val);
2977
2978         return 0;
2979 }
2980
2981 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2982                                   int ipv6, u64 protocol_id,
2983                                   u64 tos_mask, u64 tos_val)
2984 {
2985         unsigned long reg;
2986         u64 val;
2987
2988         if (class < CLASS_CODE_USER_PROG1 ||
2989             class > CLASS_CODE_USER_PROG4 ||
2990             (protocol_id & ~(u64)0xff) != 0 ||
2991             (tos_mask & ~(u64)0xff) != 0 ||
2992             (tos_val & ~(u64)0xff) != 0)
2993                 return -EINVAL;
2994
2995         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2996         val = nr64(reg);
2997         val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2998                  L3_CLS_TOSMASK | L3_CLS_TOS);
2999         if (ipv6)
3000                 val |= L3_CLS_IPVER;
3001         val |= (protocol_id << L3_CLS_PID_SHIFT);
3002         val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
3003         val |= (tos_val << L3_CLS_TOS_SHIFT);
3004         nw64(reg, val);
3005
3006         return 0;
3007 }
3008
3009 static int tcam_early_init(struct niu *np)
3010 {
3011         unsigned long i;
3012         int err;
3013
3014         tcam_enable(np, 0);
3015         tcam_set_lat_and_ratio(np,
3016                                DEFAULT_TCAM_LATENCY,
3017                                DEFAULT_TCAM_ACCESS_RATIO);
3018         for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3019                 err = tcam_user_eth_class_enable(np, i, 0);
3020                 if (err)
3021                         return err;
3022         }
3023         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3024                 err = tcam_user_ip_class_enable(np, i, 0);
3025                 if (err)
3026                         return err;
3027         }
3028
3029         return 0;
3030 }
3031
3032 static int tcam_flush_all(struct niu *np)
3033 {
3034         unsigned long i;
3035
3036         for (i = 0; i < np->parent->tcam_num_entries; i++) {
3037                 int err = tcam_flush(np, i);
3038                 if (err)
3039                         return err;
3040         }
3041         return 0;
3042 }
3043
3044 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3045 {
3046         return ((u64)index | (num_entries == 1 ?
3047                               HASH_TBL_ADDR_AUTOINC : 0));
3048 }
3049
3050 #if 0
3051 static int hash_read(struct niu *np, unsigned long partition,
3052                      unsigned long index, unsigned long num_entries,
3053                      u64 *data)
3054 {
3055         u64 val = hash_addr_regval(index, num_entries);
3056         unsigned long i;
3057
3058         if (partition >= FCRAM_NUM_PARTITIONS ||
3059             index + num_entries > FCRAM_SIZE)
3060                 return -EINVAL;
3061
3062         nw64(HASH_TBL_ADDR(partition), val);
3063         for (i = 0; i < num_entries; i++)
3064                 data[i] = nr64(HASH_TBL_DATA(partition));
3065
3066         return 0;
3067 }
3068 #endif
3069
3070 static int hash_write(struct niu *np, unsigned long partition,
3071                       unsigned long index, unsigned long num_entries,
3072                       u64 *data)
3073 {
3074         u64 val = hash_addr_regval(index, num_entries);
3075         unsigned long i;
3076
3077         if (partition >= FCRAM_NUM_PARTITIONS ||
3078             index + (num_entries * 8) > FCRAM_SIZE)
3079                 return -EINVAL;
3080
3081         nw64(HASH_TBL_ADDR(partition), val);
3082         for (i = 0; i < num_entries; i++)
3083                 nw64(HASH_TBL_DATA(partition), data[i]);
3084
3085         return 0;
3086 }
3087
3088 static void fflp_reset(struct niu *np)
3089 {
3090         u64 val;
3091
3092         nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3093         udelay(10);
3094         nw64(FFLP_CFG_1, 0);
3095
3096         val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3097         nw64(FFLP_CFG_1, val);
3098 }
3099
3100 static void fflp_set_timings(struct niu *np)
3101 {
3102         u64 val = nr64(FFLP_CFG_1);
3103
3104         val &= ~FFLP_CFG_1_FFLPINITDONE;
3105         val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3106         nw64(FFLP_CFG_1, val);
3107
3108         val = nr64(FFLP_CFG_1);
3109         val |= FFLP_CFG_1_FFLPINITDONE;
3110         nw64(FFLP_CFG_1, val);
3111
3112         val = nr64(FCRAM_REF_TMR);
3113         val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3114         val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3115         val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3116         nw64(FCRAM_REF_TMR, val);
3117 }
3118
3119 static int fflp_set_partition(struct niu *np, u64 partition,
3120                               u64 mask, u64 base, int enable)
3121 {
3122         unsigned long reg;
3123         u64 val;
3124
3125         if (partition >= FCRAM_NUM_PARTITIONS ||
3126             (mask & ~(u64)0x1f) != 0 ||
3127             (base & ~(u64)0x1f) != 0)
3128                 return -EINVAL;
3129
3130         reg = FLW_PRT_SEL(partition);
3131
3132         val = nr64(reg);
3133         val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3134         val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3135         val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3136         if (enable)
3137                 val |= FLW_PRT_SEL_EXT;
3138         nw64(reg, val);
3139
3140         return 0;
3141 }
3142
3143 static int fflp_disable_all_partitions(struct niu *np)
3144 {
3145         unsigned long i;
3146
3147         for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3148                 int err = fflp_set_partition(np, 0, 0, 0, 0);
3149                 if (err)
3150                         return err;
3151         }
3152         return 0;
3153 }
3154
3155 static void fflp_llcsnap_enable(struct niu *np, int on)
3156 {
3157         u64 val = nr64(FFLP_CFG_1);
3158
3159         if (on)
3160                 val |= FFLP_CFG_1_LLCSNAP;
3161         else
3162                 val &= ~FFLP_CFG_1_LLCSNAP;
3163         nw64(FFLP_CFG_1, val);
3164 }
3165
3166 static void fflp_errors_enable(struct niu *np, int on)
3167 {
3168         u64 val = nr64(FFLP_CFG_1);
3169
3170         if (on)
3171                 val &= ~FFLP_CFG_1_ERRORDIS;
3172         else
3173                 val |= FFLP_CFG_1_ERRORDIS;
3174         nw64(FFLP_CFG_1, val);
3175 }
3176
3177 static int fflp_hash_clear(struct niu *np)
3178 {
3179         struct fcram_hash_ipv4 ent;
3180         unsigned long i;
3181
3182         /* IPV4 hash entry with valid bit clear, rest is don't care.  */
3183         memset(&ent, 0, sizeof(ent));
3184         ent.header = HASH_HEADER_EXT;
3185
3186         for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3187                 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3188                 if (err)
3189                         return err;
3190         }
3191         return 0;
3192 }
3193
3194 static int fflp_early_init(struct niu *np)
3195 {
3196         struct niu_parent *parent;
3197         unsigned long flags;
3198         int err;
3199
3200         niu_lock_parent(np, flags);
3201
3202         parent = np->parent;
3203         err = 0;
3204         if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3205                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3206                         fflp_reset(np);
3207                         fflp_set_timings(np);
3208                         err = fflp_disable_all_partitions(np);
3209                         if (err) {
3210                                 netif_printk(np, probe, KERN_DEBUG, np->dev,
3211                                              "fflp_disable_all_partitions failed, err=%d\n",
3212                                              err);
3213                                 goto out;
3214                         }
3215                 }
3216
3217                 err = tcam_early_init(np);
3218                 if (err) {
3219                         netif_printk(np, probe, KERN_DEBUG, np->dev,
3220                                      "tcam_early_init failed, err=%d\n", err);
3221                         goto out;
3222                 }
3223                 fflp_llcsnap_enable(np, 1);
3224                 fflp_errors_enable(np, 0);
3225                 nw64(H1POLY, 0);
3226                 nw64(H2POLY, 0);
3227
3228                 err = tcam_flush_all(np);
3229                 if (err) {
3230                         netif_printk(np, probe, KERN_DEBUG, np->dev,
3231                                      "tcam_flush_all failed, err=%d\n", err);
3232                         goto out;
3233                 }
3234                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3235                         err = fflp_hash_clear(np);
3236                         if (err) {
3237                                 netif_printk(np, probe, KERN_DEBUG, np->dev,
3238                                              "fflp_hash_clear failed, err=%d\n",
3239                                              err);
3240                                 goto out;
3241                         }
3242                 }
3243
3244                 vlan_tbl_clear(np);
3245
3246                 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3247         }
3248 out:
3249         niu_unlock_parent(np, flags);
3250         return err;
3251 }
3252
3253 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3254 {
3255         if (class_code < CLASS_CODE_USER_PROG1 ||
3256             class_code > CLASS_CODE_SCTP_IPV6)
3257                 return -EINVAL;
3258
3259         nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3260         return 0;
3261 }
3262
3263 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3264 {
3265         if (class_code < CLASS_CODE_USER_PROG1 ||
3266             class_code > CLASS_CODE_SCTP_IPV6)
3267                 return -EINVAL;
3268
3269         nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3270         return 0;
3271 }
3272
3273 /* Entries for the ports are interleaved in the TCAM */
3274 static u16 tcam_get_index(struct niu *np, u16 idx)
3275 {
3276         /* One entry reserved for IP fragment rule */
3277         if (idx >= (np->clas.tcam_sz - 1))
3278                 idx = 0;
3279         return (np->clas.tcam_top + ((idx+1) * np->parent->num_ports));
3280 }
3281
3282 static u16 tcam_get_size(struct niu *np)
3283 {
3284         /* One entry reserved for IP fragment rule */
3285         return np->clas.tcam_sz - 1;
3286 }
3287
3288 static u16 tcam_get_valid_entry_cnt(struct niu *np)
3289 {
3290         /* One entry reserved for IP fragment rule */
3291         return np->clas.tcam_valid_entries - 1;
3292 }
3293
3294 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3295                               u32 offset, u32 size)
3296 {
3297         int i = skb_shinfo(skb)->nr_frags;
3298         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3299
3300         frag->page = page;
3301         frag->page_offset = offset;
3302         frag->size = size;
3303
3304         skb->len += size;
3305         skb->data_len += size;
3306         skb->truesize += size;
3307
3308         skb_shinfo(skb)->nr_frags = i + 1;
3309 }
3310
3311 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3312 {
3313         a >>= PAGE_SHIFT;
3314         a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3315
3316         return (a & (MAX_RBR_RING_SIZE - 1));
3317 }
3318
3319 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3320                                     struct page ***link)
3321 {
3322         unsigned int h = niu_hash_rxaddr(rp, addr);
3323         struct page *p, **pp;
3324
3325         addr &= PAGE_MASK;
3326         pp = &rp->rxhash[h];
3327         for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3328                 if (p->index == addr) {
3329                         *link = pp;
3330                         break;
3331                 }
3332         }
3333
3334         return p;
3335 }
3336
3337 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3338 {
3339         unsigned int h = niu_hash_rxaddr(rp, base);
3340
3341         page->index = base;
3342         page->mapping = (struct address_space *) rp->rxhash[h];
3343         rp->rxhash[h] = page;
3344 }
3345
3346 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3347                             gfp_t mask, int start_index)
3348 {
3349         struct page *page;
3350         u64 addr;
3351         int i;
3352
3353         page = alloc_page(mask);
3354         if (!page)
3355                 return -ENOMEM;
3356
3357         addr = np->ops->map_page(np->device, page, 0,
3358                                  PAGE_SIZE, DMA_FROM_DEVICE);
3359
3360         niu_hash_page(rp, page, addr);
3361         if (rp->rbr_blocks_per_page > 1)
3362                 atomic_add(rp->rbr_blocks_per_page - 1,
3363                            &compound_head(page)->_count);
3364
3365         for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3366                 __le32 *rbr = &rp->rbr[start_index + i];
3367
3368                 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3369                 addr += rp->rbr_block_size;
3370         }
3371
3372         return 0;
3373 }
3374
3375 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3376 {
3377         int index = rp->rbr_index;
3378
3379         rp->rbr_pending++;
3380         if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3381                 int err = niu_rbr_add_page(np, rp, mask, index);
3382
3383                 if (unlikely(err)) {
3384                         rp->rbr_pending--;
3385                         return;
3386                 }
3387
3388                 rp->rbr_index += rp->rbr_blocks_per_page;
3389                 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3390                 if (rp->rbr_index == rp->rbr_table_size)
3391                         rp->rbr_index = 0;
3392
3393                 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3394                         nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3395                         rp->rbr_pending = 0;
3396                 }
3397         }
3398 }
3399
3400 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3401 {
3402         unsigned int index = rp->rcr_index;
3403         int num_rcr = 0;
3404
3405         rp->rx_dropped++;
3406         while (1) {
3407                 struct page *page, **link;
3408                 u64 addr, val;
3409                 u32 rcr_size;
3410
3411                 num_rcr++;
3412
3413                 val = le64_to_cpup(&rp->rcr[index]);
3414                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3415                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3416                 page = niu_find_rxpage(rp, addr, &link);
3417
3418                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3419                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3420                 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3421                         *link = (struct page *) page->mapping;
3422                         np->ops->unmap_page(np->device, page->index,
3423                                             PAGE_SIZE, DMA_FROM_DEVICE);
3424                         page->index = 0;
3425                         page->mapping = NULL;
3426                         __free_page(page);
3427                         rp->rbr_refill_pending++;
3428                 }
3429
3430                 index = NEXT_RCR(rp, index);
3431                 if (!(val & RCR_ENTRY_MULTI))
3432                         break;
3433
3434         }
3435         rp->rcr_index = index;
3436
3437         return num_rcr;
3438 }
3439
3440 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3441                               struct rx_ring_info *rp)
3442 {
3443         unsigned int index = rp->rcr_index;
3444         struct rx_pkt_hdr1 *rh;
3445         struct sk_buff *skb;
3446         int len, num_rcr;
3447
3448         skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3449         if (unlikely(!skb))
3450                 return niu_rx_pkt_ignore(np, rp);
3451
3452         num_rcr = 0;
3453         while (1) {
3454                 struct page *page, **link;
3455                 u32 rcr_size, append_size;
3456                 u64 addr, val, off;
3457
3458                 num_rcr++;
3459
3460                 val = le64_to_cpup(&rp->rcr[index]);
3461
3462                 len = (val & RCR_ENTRY_L2_LEN) >>
3463                         RCR_ENTRY_L2_LEN_SHIFT;
3464                 len -= ETH_FCS_LEN;
3465
3466                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3467                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3468                 page = niu_find_rxpage(rp, addr, &link);
3469
3470                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3471                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3472
3473                 off = addr & ~PAGE_MASK;
3474                 append_size = rcr_size;
3475                 if (num_rcr == 1) {
3476                         int ptype;
3477
3478                         ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3479                         if ((ptype == RCR_PKT_TYPE_TCP ||
3480                              ptype == RCR_PKT_TYPE_UDP) &&
3481                             !(val & (RCR_ENTRY_NOPORT |
3482                                      RCR_ENTRY_ERROR)))
3483                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3484                         else
3485                                 skb->ip_summed = CHECKSUM_NONE;
3486                 } else if (!(val & RCR_ENTRY_MULTI))
3487                         append_size = len - skb->len;
3488
3489                 niu_rx_skb_append(skb, page, off, append_size);
3490                 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3491                         *link = (struct page *) page->mapping;
3492                         np->ops->unmap_page(np->device, page->index,
3493                                             PAGE_SIZE, DMA_FROM_DEVICE);
3494                         page->index = 0;
3495                         page->mapping = NULL;
3496                         rp->rbr_refill_pending++;
3497                 } else
3498                         get_page(page);
3499
3500                 index = NEXT_RCR(rp, index);
3501                 if (!(val & RCR_ENTRY_MULTI))
3502                         break;
3503
3504         }
3505         rp->rcr_index = index;
3506
3507         len += sizeof(*rh);
3508         len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN);
3509         __pskb_pull_tail(skb, len);
3510
3511         rh = (struct rx_pkt_hdr1 *) skb->data;
3512         if (np->dev->features & NETIF_F_RXHASH)
3513                 skb->rxhash = ((u32)rh->hashval2_0 << 24 |
3514                                (u32)rh->hashval2_1 << 16 |
3515                                (u32)rh->hashval1_1 << 8 |
3516                                (u32)rh->hashval1_2 << 0);
3517         skb_pull(skb, sizeof(*rh));
3518
3519         rp->rx_packets++;
3520         rp->rx_bytes += skb->len;
3521
3522         skb->protocol = eth_type_trans(skb, np->dev);
3523         skb_record_rx_queue(skb, rp->rx_channel);
3524         napi_gro_receive(napi, skb);
3525
3526         return num_rcr;
3527 }
3528
3529 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3530 {
3531         int blocks_per_page = rp->rbr_blocks_per_page;
3532         int err, index = rp->rbr_index;
3533
3534         err = 0;
3535         while (index < (rp->rbr_table_size - blocks_per_page)) {
3536                 err = niu_rbr_add_page(np, rp, mask, index);
3537                 if (err)
3538                         break;
3539
3540                 index += blocks_per_page;
3541         }
3542
3543         rp->rbr_index = index;
3544         return err;
3545 }
3546
3547 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3548 {
3549         int i;
3550
3551         for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3552                 struct page *page;
3553
3554                 page = rp->rxhash[i];
3555                 while (page) {
3556                         struct page *next = (struct page *) page->mapping;
3557                         u64 base = page->index;
3558
3559                         np->ops->unmap_page(np->device, base, PAGE_SIZE,
3560                                             DMA_FROM_DEVICE);
3561                         page->index = 0;
3562                         page->mapping = NULL;
3563
3564                         __free_page(page);
3565
3566                         page = next;
3567                 }
3568         }
3569
3570         for (i = 0; i < rp->rbr_table_size; i++)
3571                 rp->rbr[i] = cpu_to_le32(0);
3572         rp->rbr_index = 0;
3573 }
3574
3575 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3576 {
3577         struct tx_buff_info *tb = &rp->tx_buffs[idx];
3578         struct sk_buff *skb = tb->skb;
3579         struct tx_pkt_hdr *tp;
3580         u64 tx_flags;
3581         int i, len;
3582
3583         tp = (struct tx_pkt_hdr *) skb->data;
3584         tx_flags = le64_to_cpup(&tp->flags);
3585
3586         rp->tx_packets++;
3587         rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3588                          ((tx_flags & TXHDR_PAD) / 2));
3589
3590         len = skb_headlen(skb);
3591         np->ops->unmap_single(np->device, tb->mapping,
3592                               len, DMA_TO_DEVICE);
3593
3594         if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3595                 rp->mark_pending--;
3596
3597         tb->skb = NULL;
3598         do {
3599                 idx = NEXT_TX(rp, idx);
3600                 len -= MAX_TX_DESC_LEN;
3601         } while (len > 0);
3602
3603         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3604                 tb = &rp->tx_buffs[idx];
3605                 BUG_ON(tb->skb != NULL);
3606                 np->ops->unmap_page(np->device, tb->mapping,
3607                                     skb_shinfo(skb)->frags[i].size,
3608                                     DMA_TO_DEVICE);
3609                 idx = NEXT_TX(rp, idx);
3610         }
3611
3612         dev_kfree_skb(skb);
3613
3614         return idx;
3615 }
3616
3617 #define NIU_TX_WAKEUP_THRESH(rp)                ((rp)->pending / 4)
3618
3619 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3620 {
3621         struct netdev_queue *txq;
3622         u16 pkt_cnt, tmp;
3623         int cons, index;
3624         u64 cs;
3625
3626         index = (rp - np->tx_rings);
3627         txq = netdev_get_tx_queue(np->dev, index);
3628
3629         cs = rp->tx_cs;
3630         if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3631                 goto out;
3632
3633         tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3634         pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3635                 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3636
3637         rp->last_pkt_cnt = tmp;
3638
3639         cons = rp->cons;
3640
3641         netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3642                      "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
3643
3644         while (pkt_cnt--)
3645                 cons = release_tx_packet(np, rp, cons);
3646
3647         rp->cons = cons;
3648         smp_mb();
3649
3650 out:
3651         if (unlikely(netif_tx_queue_stopped(txq) &&
3652                      (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3653                 __netif_tx_lock(txq, smp_processor_id());
3654                 if (netif_tx_queue_stopped(txq) &&
3655                     (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3656                         netif_tx_wake_queue(txq);
3657                 __netif_tx_unlock(txq);
3658         }
3659 }
3660
3661 static inline void niu_sync_rx_discard_stats(struct niu *np,
3662                                              struct rx_ring_info *rp,
3663                                              const int limit)
3664 {
3665         /* This elaborate scheme is needed for reading the RX discard
3666          * counters, as they are only 16-bit and can overflow quickly,
3667          * and because the overflow indication bit is not usable as
3668          * the counter value does not wrap, but remains at max value
3669          * 0xFFFF.
3670          *
3671          * In theory and in practice counters can be lost in between
3672          * reading nr64() and clearing the counter nw64().  For this
3673          * reason, the number of counter clearings nw64() is
3674          * limited/reduced though the limit parameter.
3675          */
3676         int rx_channel = rp->rx_channel;
3677         u32 misc, wred;
3678
3679         /* RXMISC (Receive Miscellaneous Discard Count), covers the
3680          * following discard events: IPP (Input Port Process),
3681          * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3682          * Block Ring) prefetch buffer is empty.
3683          */
3684         misc = nr64(RXMISC(rx_channel));
3685         if (unlikely((misc & RXMISC_COUNT) > limit)) {
3686                 nw64(RXMISC(rx_channel), 0);
3687                 rp->rx_errors += misc & RXMISC_COUNT;
3688
3689                 if (unlikely(misc & RXMISC_OFLOW))
3690                         dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3691                                 rx_channel);
3692
3693                 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3694                              "rx-%d: MISC drop=%u over=%u\n",
3695                              rx_channel, misc, misc-limit);
3696         }
3697
3698         /* WRED (Weighted Random Early Discard) by hardware */
3699         wred = nr64(RED_DIS_CNT(rx_channel));
3700         if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3701                 nw64(RED_DIS_CNT(rx_channel), 0);
3702                 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3703
3704                 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3705                         dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
3706
3707                 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3708                              "rx-%d: WRED drop=%u over=%u\n",
3709                              rx_channel, wred, wred-limit);
3710         }
3711 }
3712
3713 static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3714                        struct rx_ring_info *rp, int budget)
3715 {
3716         int qlen, rcr_done = 0, work_done = 0;
3717         struct rxdma_mailbox *mbox = rp->mbox;
3718         u64 stat;
3719
3720 #if 1
3721         stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3722         qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3723 #else
3724         stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3725         qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3726 #endif
3727         mbox->rx_dma_ctl_stat = 0;
3728         mbox->rcrstat_a = 0;
3729
3730         netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3731                      "%s(chan[%d]), stat[%llx] qlen=%d\n",
3732                      __func__, rp->rx_channel, (unsigned long long)stat, qlen);
3733
3734         rcr_done = work_done = 0;
3735         qlen = min(qlen, budget);
3736         while (work_done < qlen) {
3737                 rcr_done += niu_process_rx_pkt(napi, np, rp);
3738                 work_done++;
3739         }
3740
3741         if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3742                 unsigned int i;
3743
3744                 for (i = 0; i < rp->rbr_refill_pending; i++)
3745                         niu_rbr_refill(np, rp, GFP_ATOMIC);
3746                 rp->rbr_refill_pending = 0;
3747         }
3748
3749         stat = (RX_DMA_CTL_STAT_MEX |
3750                 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3751                 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3752
3753         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3754
3755         /* Only sync discards stats when qlen indicate potential for drops */
3756         if (qlen > 10)
3757                 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3758
3759         return work_done;
3760 }
3761
3762 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3763 {
3764         u64 v0 = lp->v0;
3765         u32 tx_vec = (v0 >> 32);
3766         u32 rx_vec = (v0 & 0xffffffff);
3767         int i, work_done = 0;
3768
3769         netif_printk(np, intr, KERN_DEBUG, np->dev,
3770                      "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
3771
3772         for (i = 0; i < np->num_tx_rings; i++) {
3773                 struct tx_ring_info *rp = &np->tx_rings[i];
3774                 if (tx_vec & (1 << rp->tx_channel))
3775                         niu_tx_work(np, rp);
3776                 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3777         }
3778
3779         for (i = 0; i < np->num_rx_rings; i++) {
3780                 struct rx_ring_info *rp = &np->rx_rings[i];
3781
3782                 if (rx_vec & (1 << rp->rx_channel)) {
3783                         int this_work_done;
3784
3785                         this_work_done = niu_rx_work(&lp->napi, np, rp,
3786                                                      budget);
3787
3788                         budget -= this_work_done;
3789                         work_done += this_work_done;
3790                 }
3791                 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3792         }
3793
3794         return work_done;
3795 }
3796
3797 static int niu_poll(struct napi_struct *napi, int budget)
3798 {
3799         struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3800         struct niu *np = lp->np;
3801         int work_done;
3802
3803         work_done = niu_poll_core(np, lp, budget);
3804
3805         if (work_done < budget) {
3806                 napi_complete(napi);
3807                 niu_ldg_rearm(np, lp, 1);
3808         }
3809         return work_done;
3810 }
3811
3812 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3813                                   u64 stat)
3814 {
3815         netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
3816
3817         if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3818                 pr_cont("RBR_TMOUT ");
3819         if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3820                 pr_cont("RSP_CNT ");
3821         if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3822                 pr_cont("BYTE_EN_BUS ");
3823         if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3824                 pr_cont("RSP_DAT ");
3825         if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3826                 pr_cont("RCR_ACK ");
3827         if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3828                 pr_cont("RCR_SHA_PAR ");
3829         if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3830                 pr_cont("RBR_PRE_PAR ");
3831         if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3832                 pr_cont("CONFIG ");
3833         if (stat & RX_DMA_CTL_STAT_RCRINCON)
3834                 pr_cont("RCRINCON ");
3835         if (stat & RX_DMA_CTL_STAT_RCRFULL)
3836                 pr_cont("RCRFULL ");
3837         if (stat & RX_DMA_CTL_STAT_RBRFULL)
3838                 pr_cont("RBRFULL ");
3839         if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3840                 pr_cont("RBRLOGPAGE ");
3841         if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3842                 pr_cont("CFIGLOGPAGE ");
3843         if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3844                 pr_cont("DC_FIDO ");
3845
3846         pr_cont(")\n");
3847 }
3848
3849 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3850 {
3851         u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3852         int err = 0;
3853
3854
3855         if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3856                     RX_DMA_CTL_STAT_PORT_FATAL))
3857                 err = -EINVAL;
3858
3859         if (err) {
3860                 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3861                            rp->rx_channel,
3862                            (unsigned long long) stat);
3863
3864                 niu_log_rxchan_errors(np, rp, stat);
3865         }
3866
3867         nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3868              stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3869
3870         return err;
3871 }
3872
3873 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3874                                   u64 cs)
3875 {
3876         netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
3877
3878         if (cs & TX_CS_MBOX_ERR)
3879                 pr_cont("MBOX ");
3880         if (cs & TX_CS_PKT_SIZE_ERR)
3881                 pr_cont("PKT_SIZE ");
3882         if (cs & TX_CS_TX_RING_OFLOW)
3883                 pr_cont("TX_RING_OFLOW ");
3884         if (cs & TX_CS_PREF_BUF_PAR_ERR)
3885                 pr_cont("PREF_BUF_PAR ");
3886         if (cs & TX_CS_NACK_PREF)
3887                 pr_cont("NACK_PREF ");
3888         if (cs & TX_CS_NACK_PKT_RD)
3889                 pr_cont("NACK_PKT_RD ");
3890         if (cs & TX_CS_CONF_PART_ERR)
3891                 pr_cont("CONF_PART ");
3892         if (cs & TX_CS_PKT_PRT_ERR)
3893                 pr_cont("PKT_PTR ");
3894
3895         pr_cont(")\n");
3896 }
3897
3898 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3899 {
3900         u64 cs, logh, logl;
3901
3902         cs = nr64(TX_CS(rp->tx_channel));
3903         logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3904         logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3905
3906         netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3907                    rp->tx_channel,
3908                    (unsigned long long)cs,
3909                    (unsigned long long)logh,
3910                    (unsigned long long)logl);
3911
3912         niu_log_txchan_errors(np, rp, cs);
3913
3914         return -ENODEV;
3915 }
3916
3917 static int niu_mif_interrupt(struct niu *np)
3918 {
3919         u64 mif_status = nr64(MIF_STATUS);
3920         int phy_mdint = 0;
3921
3922         if (np->flags & NIU_FLAGS_XMAC) {
3923                 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3924
3925                 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3926                         phy_mdint = 1;
3927         }
3928
3929         netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3930                    (unsigned long long)mif_status, phy_mdint);
3931
3932         return -ENODEV;
3933 }
3934
3935 static void niu_xmac_interrupt(struct niu *np)
3936 {
3937         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3938         u64 val;
3939
3940         val = nr64_mac(XTXMAC_STATUS);
3941         if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3942                 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3943         if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3944                 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3945         if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3946                 mp->tx_fifo_errors++;
3947         if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3948                 mp->tx_overflow_errors++;
3949         if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3950                 mp->tx_max_pkt_size_errors++;
3951         if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3952                 mp->tx_underflow_errors++;
3953
3954         val = nr64_mac(XRXMAC_STATUS);
3955         if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3956                 mp->rx_local_faults++;
3957         if (val & XRXMAC_STATUS_RFLT_DET)
3958                 mp->rx_remote_faults++;
3959         if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3960                 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3961         if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3962                 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3963         if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3964                 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3965         if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3966                 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3967         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3968                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3969         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3970                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3971         if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3972                 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3973         if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3974                 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3975         if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3976                 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3977         if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3978                 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3979         if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3980                 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3981         if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3982                 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3983         if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3984                 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3985         if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
3986                 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3987         if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3988                 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3989         if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3990                 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3991         if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3992                 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3993         if (val & XRXMAC_STATUS_RXUFLOW)
3994                 mp->rx_underflows++;
3995         if (val & XRXMAC_STATUS_RXOFLOW)
3996                 mp->rx_overflows++;
3997
3998         val = nr64_mac(XMAC_FC_STAT);
3999         if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
4000                 mp->pause_off_state++;
4001         if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
4002                 mp->pause_on_state++;
4003         if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
4004                 mp->pause_received++;
4005 }
4006
4007 static void niu_bmac_interrupt(struct niu *np)
4008 {
4009         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4010         u64 val;
4011
4012         val = nr64_mac(BTXMAC_STATUS);
4013         if (val & BTXMAC_STATUS_UNDERRUN)
4014                 mp->tx_underflow_errors++;
4015         if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4016                 mp->tx_max_pkt_size_errors++;
4017         if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4018                 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4019         if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4020                 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4021
4022         val = nr64_mac(BRXMAC_STATUS);
4023         if (val & BRXMAC_STATUS_OVERFLOW)
4024                 mp->rx_overflows++;
4025         if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4026                 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4027         if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4028                 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4029         if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4030                 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4031         if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4032                 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4033
4034         val = nr64_mac(BMAC_CTRL_STATUS);
4035         if (val & BMAC_CTRL_STATUS_NOPAUSE)
4036                 mp->pause_off_state++;
4037         if (val & BMAC_CTRL_STATUS_PAUSE)
4038                 mp->pause_on_state++;
4039         if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4040                 mp->pause_received++;
4041 }
4042
4043 static int niu_mac_interrupt(struct niu *np)
4044 {
4045         if (np->flags & NIU_FLAGS_XMAC)
4046                 niu_xmac_interrupt(np);
4047         else
4048                 niu_bmac_interrupt(np);
4049
4050         return 0;
4051 }
4052
4053 static void niu_log_device_error(struct niu *np, u64 stat)
4054 {
4055         netdev_err(np->dev, "Core device errors ( ");
4056
4057         if (stat & SYS_ERR_MASK_META2)
4058                 pr_cont("META2 ");
4059         if (stat & SYS_ERR_MASK_META1)
4060                 pr_cont("META1 ");
4061         if (stat & SYS_ERR_MASK_PEU)
4062                 pr_cont("PEU ");
4063         if (stat & SYS_ERR_MASK_TXC)
4064                 pr_cont("TXC ");
4065         if (stat & SYS_ERR_MASK_RDMC)
4066                 pr_cont("RDMC ");
4067         if (stat & SYS_ERR_MASK_TDMC)
4068                 pr_cont("TDMC ");
4069         if (stat & SYS_ERR_MASK_ZCP)
4070                 pr_cont("ZCP ");
4071         if (stat & SYS_ERR_MASK_FFLP)
4072                 pr_cont("FFLP ");
4073         if (stat & SYS_ERR_MASK_IPP)
4074                 pr_cont("IPP ");
4075         if (stat & SYS_ERR_MASK_MAC)
4076                 pr_cont("MAC ");
4077         if (stat & SYS_ERR_MASK_SMX)
4078                 pr_cont("SMX ");
4079
4080         pr_cont(")\n");
4081 }
4082
4083 static int niu_device_error(struct niu *np)
4084 {
4085         u64 stat = nr64(SYS_ERR_STAT);
4086
4087         netdev_err(np->dev, "Core device error, stat[%llx]\n",
4088                    (unsigned long long)stat);
4089
4090         niu_log_device_error(np, stat);
4091
4092         return -ENODEV;
4093 }
4094
4095 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4096                               u64 v0, u64 v1, u64 v2)
4097 {
4098
4099         int i, err = 0;
4100
4101         lp->v0 = v0;
4102         lp->v1 = v1;
4103         lp->v2 = v2;
4104
4105         if (v1 & 0x00000000ffffffffULL) {
4106                 u32 rx_vec = (v1 & 0xffffffff);
4107
4108                 for (i = 0; i < np->num_rx_rings; i++) {
4109                         struct rx_ring_info *rp = &np->rx_rings[i];
4110
4111                         if (rx_vec & (1 << rp->rx_channel)) {
4112                                 int r = niu_rx_error(np, rp);
4113                                 if (r) {
4114                                         err = r;
4115                                 } else {
4116                                         if (!v0)
4117                                                 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4118                                                      RX_DMA_CTL_STAT_MEX);
4119                                 }
4120                         }
4121                 }
4122         }
4123         if (v1 & 0x7fffffff00000000ULL) {
4124                 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4125
4126                 for (i = 0; i < np->num_tx_rings; i++) {
4127                         struct tx_ring_info *rp = &np->tx_rings[i];
4128
4129                         if (tx_vec & (1 << rp->tx_channel)) {
4130                                 int r = niu_tx_error(np, rp);
4131                                 if (r)
4132                                         err = r;
4133                         }
4134                 }
4135         }
4136         if ((v0 | v1) & 0x8000000000000000ULL) {
4137                 int r = niu_mif_interrupt(np);
4138                 if (r)
4139                         err = r;
4140         }
4141         if (v2) {
4142                 if (v2 & 0x01ef) {
4143                         int r = niu_mac_interrupt(np);
4144                         if (r)
4145                                 err = r;
4146                 }
4147                 if (v2 & 0x0210) {
4148                         int r = niu_device_error(np);
4149                         if (r)
4150                                 err = r;
4151                 }
4152         }
4153
4154         if (err)
4155                 niu_enable_interrupts(np, 0);
4156
4157         return err;
4158 }
4159
4160 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4161                             int ldn)
4162 {
4163         struct rxdma_mailbox *mbox = rp->mbox;
4164         u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4165
4166         stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4167                       RX_DMA_CTL_STAT_RCRTO);
4168         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4169
4170         netif_printk(np, intr, KERN_DEBUG, np->dev,
4171                      "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
4172 }
4173
4174 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4175                             int ldn)
4176 {
4177         rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4178
4179         netif_printk(np, intr, KERN_DEBUG, np->dev,
4180                      "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
4181 }
4182
4183 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4184 {
4185         struct niu_parent *parent = np->parent;
4186         u32 rx_vec, tx_vec;
4187         int i;
4188
4189         tx_vec = (v0 >> 32);
4190         rx_vec = (v0 & 0xffffffff);
4191
4192         for (i = 0; i < np->num_rx_rings; i++) {
4193                 struct rx_ring_info *rp = &np->rx_rings[i];
4194                 int ldn = LDN_RXDMA(rp->rx_channel);
4195
4196                 if (parent->ldg_map[ldn] != ldg)
4197                         continue;
4198
4199                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4200                 if (rx_vec & (1 << rp->rx_channel))
4201                         niu_rxchan_intr(np, rp, ldn);
4202         }
4203
4204         for (i = 0; i < np->num_tx_rings; i++) {
4205                 struct tx_ring_info *rp = &np->tx_rings[i];
4206                 int ldn = LDN_TXDMA(rp->tx_channel);
4207
4208                 if (parent->ldg_map[ldn] != ldg)
4209                         continue;
4210
4211                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4212                 if (tx_vec & (1 << rp->tx_channel))
4213                         niu_txchan_intr(np, rp, ldn);
4214         }
4215 }
4216
4217 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4218                               u64 v0, u64 v1, u64 v2)
4219 {
4220         if (likely(napi_schedule_prep(&lp->napi))) {
4221                 lp->v0 = v0;
4222                 lp->v1 = v1;
4223                 lp->v2 = v2;
4224                 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4225                 __napi_schedule(&lp->napi);
4226         }
4227 }
4228
4229 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4230 {
4231         struct niu_ldg *lp = dev_id;
4232         struct niu *np = lp->np;
4233         int ldg = lp->ldg_num;
4234         unsigned long flags;
4235         u64 v0, v1, v2;
4236
4237         if (netif_msg_intr(np))
4238                 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4239                        __func__, lp, ldg);
4240
4241         spin_lock_irqsave(&np->lock, flags);
4242
4243         v0 = nr64(LDSV0(ldg));
4244         v1 = nr64(LDSV1(ldg));
4245         v2 = nr64(LDSV2(ldg));
4246
4247         if (netif_msg_intr(np))
4248                 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
4249                        (unsigned long long) v0,
4250                        (unsigned long long) v1,
4251                        (unsigned long long) v2);
4252
4253         if (unlikely(!v0 && !v1 && !v2)) {
4254                 spin_unlock_irqrestore(&np->lock, flags);
4255                 return IRQ_NONE;
4256         }
4257
4258         if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4259                 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4260                 if (err)
4261                         goto out;
4262         }
4263         if (likely(v0 & ~((u64)1 << LDN_MIF)))
4264                 niu_schedule_napi(np, lp, v0, v1, v2);
4265         else
4266                 niu_ldg_rearm(np, lp, 1);
4267 out:
4268         spin_unlock_irqrestore(&np->lock, flags);
4269
4270         return IRQ_HANDLED;
4271 }
4272
4273 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4274 {
4275         if (rp->mbox) {
4276                 np->ops->free_coherent(np->device,
4277                                        sizeof(struct rxdma_mailbox),
4278                                        rp->mbox, rp->mbox_dma);
4279                 rp->mbox = NULL;
4280         }
4281         if (rp->rcr) {
4282                 np->ops->free_coherent(np->device,
4283                                        MAX_RCR_RING_SIZE * sizeof(__le64),
4284                                        rp->rcr, rp->rcr_dma);
4285                 rp->rcr = NULL;
4286                 rp->rcr_table_size = 0;
4287                 rp->rcr_index = 0;
4288         }
4289         if (rp->rbr) {
4290                 niu_rbr_free(np, rp);
4291
4292                 np->ops->free_coherent(np->device,
4293                                        MAX_RBR_RING_SIZE * sizeof(__le32),
4294                                        rp->rbr, rp->rbr_dma);
4295                 rp->rbr = NULL;
4296                 rp->rbr_table_size = 0;
4297                 rp->rbr_index = 0;
4298         }
4299         kfree(rp->rxhash);
4300         rp->rxhash = NULL;
4301 }
4302
4303 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4304 {
4305         if (rp->mbox) {
4306                 np->ops->free_coherent(np->device,
4307                                        sizeof(struct txdma_mailbox),
4308                                        rp->mbox, rp->mbox_dma);
4309                 rp->mbox = NULL;
4310         }
4311         if (rp->descr) {
4312                 int i;
4313
4314                 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4315                         if (rp->tx_buffs[i].skb)
4316                                 (void) release_tx_packet(np, rp, i);
4317                 }
4318
4319                 np->ops->free_coherent(np->device,
4320                                        MAX_TX_RING_SIZE * sizeof(__le64),
4321                                        rp->descr, rp->descr_dma);
4322                 rp->descr = NULL;
4323                 rp->pending = 0;
4324                 rp->prod = 0;
4325                 rp->cons = 0;
4326                 rp->wrap_bit = 0;
4327         }
4328 }
4329
4330 static void niu_free_channels(struct niu *np)
4331 {
4332         int i;
4333
4334         if (np->rx_rings) {
4335                 for (i = 0; i < np->num_rx_rings; i++) {
4336                         struct rx_ring_info *rp = &np->rx_rings[i];
4337
4338                         niu_free_rx_ring_info(np, rp);
4339                 }
4340                 kfree(np->rx_rings);
4341                 np->rx_rings = NULL;
4342                 np->num_rx_rings = 0;
4343         }
4344
4345         if (np->tx_rings) {
4346                 for (i = 0; i < np->num_tx_rings; i++) {
4347                         struct tx_ring_info *rp = &np->tx_rings[i];
4348
4349                         niu_free_tx_ring_info(np, rp);
4350                 }
4351                 kfree(np->tx_rings);
4352                 np->tx_rings = NULL;
4353                 np->num_tx_rings = 0;
4354         }
4355 }
4356
4357 static int niu_alloc_rx_ring_info(struct niu *np,
4358                                   struct rx_ring_info *rp)
4359 {
4360         BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4361
4362         rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4363                              GFP_KERNEL);
4364         if (!rp->rxhash)
4365                 return -ENOMEM;
4366
4367         rp->mbox = np->ops->alloc_coherent(np->device,
4368                                            sizeof(struct rxdma_mailbox),
4369                                            &rp->mbox_dma, GFP_KERNEL);
4370         if (!rp->mbox)
4371                 return -ENOMEM;
4372         if ((unsigned long)rp->mbox & (64UL - 1)) {
4373                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4374                            rp->mbox);
4375                 return -EINVAL;
4376         }
4377
4378         rp->rcr = np->ops->alloc_coherent(np->device,
4379                                           MAX_RCR_RING_SIZE * sizeof(__le64),
4380                                           &rp->rcr_dma, GFP_KERNEL);
4381         if (!rp->rcr)
4382                 return -ENOMEM;
4383         if ((unsigned long)rp->rcr & (64UL - 1)) {
4384                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4385                            rp->rcr);
4386                 return -EINVAL;
4387         }
4388         rp->rcr_table_size = MAX_RCR_RING_SIZE;
4389         rp->rcr_index = 0;
4390
4391         rp->rbr = np->ops->alloc_coherent(np->device,
4392                                           MAX_RBR_RING_SIZE * sizeof(__le32),
4393                                           &rp->rbr_dma, GFP_KERNEL);
4394         if (!rp->rbr)
4395                 return -ENOMEM;
4396         if ((unsigned long)rp->rbr & (64UL - 1)) {
4397                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4398                            rp->rbr);
4399                 return -EINVAL;
4400         }
4401         rp->rbr_table_size = MAX_RBR_RING_SIZE;
4402         rp->rbr_index = 0;
4403         rp->rbr_pending = 0;
4404
4405         return 0;
4406 }
4407
4408 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4409 {
4410         int mtu = np->dev->mtu;
4411
4412         /* These values are recommended by the HW designers for fair
4413          * utilization of DRR amongst the rings.
4414          */
4415         rp->max_burst = mtu + 32;
4416         if (rp->max_burst > 4096)
4417                 rp->max_burst = 4096;
4418 }
4419
4420 static int niu_alloc_tx_ring_info(struct niu *np,
4421                                   struct tx_ring_info *rp)
4422 {
4423         BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4424
4425         rp->mbox = np->ops->alloc_coherent(np->device,
4426                                            sizeof(struct txdma_mailbox),
4427                                            &rp->mbox_dma, GFP_KERNEL);
4428         if (!rp->mbox)
4429                 return -ENOMEM;
4430         if ((unsigned long)rp->mbox & (64UL - 1)) {
4431                 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4432                            rp->mbox);
4433                 return -EINVAL;
4434         }
4435
4436         rp->descr = np->ops->alloc_coherent(np->device,
4437                                             MAX_TX_RING_SIZE * sizeof(__le64),
4438                                             &rp->descr_dma, GFP_KERNEL);
4439         if (!rp->descr)
4440                 return -ENOMEM;
4441         if ((unsigned long)rp->descr & (64UL - 1)) {
4442                 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4443                            rp->descr);
4444                 return -EINVAL;
4445         }
4446
4447         rp->pending = MAX_TX_RING_SIZE;
4448         rp->prod = 0;
4449         rp->cons = 0;
4450         rp->wrap_bit = 0;
4451
4452         /* XXX make these configurable... XXX */
4453         rp->mark_freq = rp->pending / 4;
4454
4455         niu_set_max_burst(np, rp);
4456
4457         return 0;
4458 }
4459
4460 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4461 {
4462         u16 bss;
4463
4464         bss = min(PAGE_SHIFT, 15);
4465
4466         rp->rbr_block_size = 1 << bss;
4467         rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4468
4469         rp->rbr_sizes[0] = 256;
4470         rp->rbr_sizes[1] = 1024;
4471         if (np->dev->mtu > ETH_DATA_LEN) {
4472                 switch (PAGE_SIZE) {
4473                 case 4 * 1024:
4474                         rp->rbr_sizes[2] = 4096;
4475                         break;
4476
4477                 default:
4478                         rp->rbr_sizes[2] = 8192;
4479                         break;
4480                 }
4481         } else {
4482                 rp->rbr_sizes[2] = 2048;
4483         }
4484         rp->rbr_sizes[3] = rp->rbr_block_size;
4485 }
4486
4487 static int niu_alloc_channels(struct niu *np)
4488 {
4489         struct niu_parent *parent = np->parent;
4490         int first_rx_channel, first_tx_channel;
4491         int i, port, err;
4492
4493         port = np->port;
4494         first_rx_channel = first_tx_channel = 0;
4495         for (i = 0; i < port; i++) {
4496                 first_rx_channel += parent->rxchan_per_port[i];
4497                 first_tx_channel += parent->txchan_per_port[i];
4498         }
4499
4500         np->num_rx_rings = parent->rxchan_per_port[port];
4501         np->num_tx_rings = parent->txchan_per_port[port];
4502
4503         np->dev->real_num_tx_queues = np->num_tx_rings;
4504
4505         np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4506                                GFP_KERNEL);
4507         err = -ENOMEM;
4508         if (!np->rx_rings)
4509                 goto out_err;
4510
4511         for (i = 0; i < np->num_rx_rings; i++) {
4512                 struct rx_ring_info *rp = &np->rx_rings[i];
4513
4514                 rp->np = np;
4515                 rp->rx_channel = first_rx_channel + i;
4516
4517                 err = niu_alloc_rx_ring_info(np, rp);
4518                 if (err)
4519                         goto out_err;
4520
4521                 niu_size_rbr(np, rp);
4522
4523                 /* XXX better defaults, configurable, etc... XXX */
4524                 rp->nonsyn_window = 64;
4525                 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4526                 rp->syn_window = 64;
4527                 rp->syn_threshold = rp->rcr_table_size - 64;
4528                 rp->rcr_pkt_threshold = 16;
4529                 rp->rcr_timeout = 8;
4530                 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4531                 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4532                         rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4533
4534                 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4535                 if (err)
4536                         return err;
4537         }
4538
4539         np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
4540                                GFP_KERNEL);
4541         err = -ENOMEM;
4542         if (!np->tx_rings)
4543                 goto out_err;
4544
4545         for (i = 0; i < np->num_tx_rings; i++) {
4546                 struct tx_ring_info *rp = &np->tx_rings[i];
4547
4548                 rp->np = np;
4549                 rp->tx_channel = first_tx_channel + i;
4550
4551                 err = niu_alloc_tx_ring_info(np, rp);
4552                 if (err)
4553                         goto out_err;
4554         }
4555
4556         return 0;
4557
4558 out_err:
4559         niu_free_channels(np);
4560         return err;
4561 }
4562
4563 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4564 {
4565         int limit = 1000;
4566
4567         while (--limit > 0) {
4568                 u64 val = nr64(TX_CS(channel));
4569                 if (val & TX_CS_SNG_STATE)
4570                         return 0;
4571         }
4572         return -ENODEV;
4573 }
4574
4575 static int niu_tx_channel_stop(struct niu *np, int channel)
4576 {
4577         u64 val = nr64(TX_CS(channel));
4578
4579         val |= TX_CS_STOP_N_GO;
4580         nw64(TX_CS(channel), val);
4581
4582         return niu_tx_cs_sng_poll(np, channel);
4583 }
4584
4585 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4586 {
4587         int limit = 1000;
4588
4589         while (--limit > 0) {
4590                 u64 val = nr64(TX_CS(channel));
4591                 if (!(val & TX_CS_RST))
4592                         return 0;
4593         }
4594         return -ENODEV;
4595 }
4596
4597 static int niu_tx_channel_reset(struct niu *np, int channel)
4598 {
4599         u64 val = nr64(TX_CS(channel));
4600         int err;
4601
4602         val |= TX_CS_RST;
4603         nw64(TX_CS(channel), val);
4604
4605         err = niu_tx_cs_reset_poll(np, channel);
4606         if (!err)
4607                 nw64(TX_RING_KICK(channel), 0);
4608
4609         return err;
4610 }
4611
4612 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4613 {
4614         u64 val;
4615
4616         nw64(TX_LOG_MASK1(channel), 0);
4617         nw64(TX_LOG_VAL1(channel), 0);
4618         nw64(TX_LOG_MASK2(channel), 0);
4619         nw64(TX_LOG_VAL2(channel), 0);
4620         nw64(TX_LOG_PAGE_RELO1(channel), 0);
4621         nw64(TX_LOG_PAGE_RELO2(channel), 0);
4622         nw64(TX_LOG_PAGE_HDL(channel), 0);
4623
4624         val  = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4625         val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4626         nw64(TX_LOG_PAGE_VLD(channel), val);
4627
4628         /* XXX TXDMA 32bit mode? XXX */
4629
4630         return 0;
4631 }
4632
4633 static void niu_txc_enable_port(struct niu *np, int on)
4634 {
4635         unsigned long flags;
4636         u64 val, mask;
4637
4638         niu_lock_parent(np, flags);
4639         val = nr64(TXC_CONTROL);
4640         mask = (u64)1 << np->port;
4641         if (on) {
4642                 val |= TXC_CONTROL_ENABLE | mask;
4643         } else {
4644                 val &= ~mask;
4645                 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4646                         val &= ~TXC_CONTROL_ENABLE;
4647         }
4648         nw64(TXC_CONTROL, val);
4649         niu_unlock_parent(np, flags);
4650 }
4651
4652 static void niu_txc_set_imask(struct niu *np, u64 imask)
4653 {
4654         unsigned long flags;
4655         u64 val;
4656
4657         niu_lock_parent(np, flags);
4658         val = nr64(TXC_INT_MASK);
4659         val &= ~TXC_INT_MASK_VAL(np->port);
4660         val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4661         niu_unlock_parent(np, flags);
4662 }
4663
4664 static void niu_txc_port_dma_enable(struct niu *np, int on)
4665 {
4666         u64 val = 0;
4667
4668         if (on) {
4669                 int i;
4670
4671                 for (i = 0; i < np->num_tx_rings; i++)
4672                         val |= (1 << np->tx_rings[i].tx_channel);
4673         }
4674         nw64(TXC_PORT_DMA(np->port), val);
4675 }
4676
4677 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4678 {
4679         int err, channel = rp->tx_channel;
4680         u64 val, ring_len;
4681
4682         err = niu_tx_channel_stop(np, channel);
4683         if (err)
4684                 return err;
4685
4686         err = niu_tx_channel_reset(np, channel);
4687         if (err)
4688                 return err;
4689
4690         err = niu_tx_channel_lpage_init(np, channel);
4691         if (err)
4692                 return err;
4693
4694         nw64(TXC_DMA_MAX(channel), rp->max_burst);
4695         nw64(TX_ENT_MSK(channel), 0);
4696
4697         if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4698                               TX_RNG_CFIG_STADDR)) {
4699                 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4700                            channel, (unsigned long long)rp->descr_dma);
4701                 return -EINVAL;
4702         }
4703
4704         /* The length field in TX_RNG_CFIG is measured in 64-byte
4705          * blocks.  rp->pending is the number of TX descriptors in
4706          * our ring, 8 bytes each, thus we divide by 8 bytes more
4707          * to get the proper value the chip wants.
4708          */
4709         ring_len = (rp->pending / 8);
4710
4711         val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4712                rp->descr_dma);
4713         nw64(TX_RNG_CFIG(channel), val);
4714
4715         if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4716             ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4717                 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4718                             channel, (unsigned long long)rp->mbox_dma);
4719                 return -EINVAL;
4720         }
4721         nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4722         nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4723
4724         nw64(TX_CS(channel), 0);
4725
4726         rp->last_pkt_cnt = 0;
4727
4728         return 0;
4729 }
4730
4731 static void niu_init_rdc_groups(struct niu *np)
4732 {
4733         struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4734         int i, first_table_num = tp->first_table_num;
4735
4736         for (i = 0; i < tp->num_tables; i++) {
4737                 struct rdc_table *tbl = &tp->tables[i];
4738                 int this_table = first_table_num + i;
4739                 int slot;
4740
4741                 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4742                         nw64(RDC_TBL(this_table, slot),
4743                              tbl->rxdma_channel[slot]);
4744         }
4745
4746         nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4747 }
4748
4749 static void niu_init_drr_weight(struct niu *np)
4750 {
4751         int type = phy_decode(np->parent->port_phy, np->port);
4752         u64 val;
4753
4754         switch (type) {
4755         case PORT_TYPE_10G:
4756                 val = PT_DRR_WEIGHT_DEFAULT_10G;
4757                 break;
4758
4759         case PORT_TYPE_1G:
4760         default:
4761                 val = PT_DRR_WEIGHT_DEFAULT_1G;
4762                 break;
4763         }
4764         nw64(PT_DRR_WT(np->port), val);
4765 }
4766
4767 static int niu_init_hostinfo(struct niu *np)
4768 {
4769         struct niu_parent *parent = np->parent;
4770         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4771         int i, err, num_alt = niu_num_alt_addr(np);
4772         int first_rdc_table = tp->first_table_num;
4773
4774         err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4775         if (err)
4776                 return err;
4777
4778         err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4779         if (err)
4780                 return err;
4781
4782         for (i = 0; i < num_alt; i++) {
4783                 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4784                 if (err)
4785                         return err;
4786         }
4787
4788         return 0;
4789 }
4790
4791 static int niu_rx_channel_reset(struct niu *np, int channel)
4792 {
4793         return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4794                                       RXDMA_CFIG1_RST, 1000, 10,
4795                                       "RXDMA_CFIG1");
4796 }
4797
4798 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4799 {
4800         u64 val;
4801
4802         nw64(RX_LOG_MASK1(channel), 0);
4803         nw64(RX_LOG_VAL1(channel), 0);
4804         nw64(RX_LOG_MASK2(channel), 0);
4805         nw64(RX_LOG_VAL2(channel), 0);
4806         nw64(RX_LOG_PAGE_RELO1(channel), 0);
4807         nw64(RX_LOG_PAGE_RELO2(channel), 0);
4808         nw64(RX_LOG_PAGE_HDL(channel), 0);
4809
4810         val  = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4811         val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4812         nw64(RX_LOG_PAGE_VLD(channel), val);
4813
4814         return 0;
4815 }
4816
4817 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4818 {
4819         u64 val;
4820
4821         val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4822                ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4823                ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4824                ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4825         nw64(RDC_RED_PARA(rp->rx_channel), val);
4826 }
4827
4828 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4829 {
4830         u64 val = 0;
4831
4832         *ret = 0;
4833         switch (rp->rbr_block_size) {
4834         case 4 * 1024:
4835                 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4836                 break;
4837         case 8 * 1024:
4838                 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4839                 break;
4840         case 16 * 1024:
4841                 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4842                 break;
4843         case 32 * 1024:
4844                 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4845                 break;
4846         default:
4847                 return -EINVAL;
4848         }
4849         val |= RBR_CFIG_B_VLD2;
4850         switch (rp->rbr_sizes[2]) {
4851         case 2 * 1024:
4852                 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4853                 break;
4854         case 4 * 1024:
4855                 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4856                 break;
4857         case 8 * 1024:
4858                 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4859                 break;
4860         case 16 * 1024:
4861                 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4862                 break;
4863
4864         default:
4865                 return -EINVAL;
4866         }
4867         val |= RBR_CFIG_B_VLD1;
4868         switch (rp->rbr_sizes[1]) {
4869         case 1 * 1024:
4870                 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4871                 break;
4872         case 2 * 1024:
4873                 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4874                 break;
4875         case 4 * 1024:
4876                 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4877                 break;
4878         case 8 * 1024:
4879                 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4880                 break;
4881
4882         default:
4883                 return -EINVAL;
4884         }
4885         val |= RBR_CFIG_B_VLD0;
4886         switch (rp->rbr_sizes[0]) {
4887         case 256:
4888                 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4889                 break;
4890         case 512:
4891                 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4892                 break;
4893         case 1 * 1024:
4894                 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4895                 break;
4896         case 2 * 1024:
4897                 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4898                 break;
4899
4900         default:
4901                 return -EINVAL;
4902         }
4903
4904         *ret = val;
4905         return 0;
4906 }
4907
4908 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4909 {
4910         u64 val = nr64(RXDMA_CFIG1(channel));
4911         int limit;
4912
4913         if (on)
4914                 val |= RXDMA_CFIG1_EN;
4915         else
4916                 val &= ~RXDMA_CFIG1_EN;
4917         nw64(RXDMA_CFIG1(channel), val);
4918
4919         limit = 1000;
4920         while (--limit > 0) {
4921                 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4922                         break;
4923                 udelay(10);
4924         }
4925         if (limit <= 0)
4926                 return -ENODEV;
4927         return 0;
4928 }
4929
4930 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4931 {
4932         int err, channel = rp->rx_channel;
4933         u64 val;
4934
4935         err = niu_rx_channel_reset(np, channel);
4936         if (err)
4937                 return err;
4938
4939         err = niu_rx_channel_lpage_init(np, channel);
4940         if (err)
4941                 return err;
4942
4943         niu_rx_channel_wred_init(np, rp);
4944
4945         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4946         nw64(RX_DMA_CTL_STAT(channel),
4947              (RX_DMA_CTL_STAT_MEX |
4948               RX_DMA_CTL_STAT_RCRTHRES |
4949               RX_DMA_CTL_STAT_RCRTO |
4950               RX_DMA_CTL_STAT_RBR_EMPTY));
4951         nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4952         nw64(RXDMA_CFIG2(channel),
4953              ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) |
4954               RXDMA_CFIG2_FULL_HDR));
4955         nw64(RBR_CFIG_A(channel),
4956              ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4957              (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4958         err = niu_compute_rbr_cfig_b(rp, &val);
4959         if (err)
4960                 return err;
4961         nw64(RBR_CFIG_B(channel), val);
4962         nw64(RCRCFIG_A(channel),
4963              ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4964              (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4965         nw64(RCRCFIG_B(channel),
4966              ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4967              RCRCFIG_B_ENTOUT |
4968              ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4969
4970         err = niu_enable_rx_channel(np, channel, 1);
4971         if (err)
4972                 return err;
4973
4974         nw64(RBR_KICK(channel), rp->rbr_index);
4975
4976         val = nr64(RX_DMA_CTL_STAT(channel));
4977         val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4978         nw64(RX_DMA_CTL_STAT(channel), val);
4979
4980         return 0;
4981 }
4982
4983 static int niu_init_rx_channels(struct niu *np)
4984 {
4985         unsigned long flags;
4986         u64 seed = jiffies_64;
4987         int err, i;
4988
4989         niu_lock_parent(np, flags);
4990         nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4991         nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4992         niu_unlock_parent(np, flags);
4993
4994         /* XXX RXDMA 32bit mode? XXX */
4995
4996         niu_init_rdc_groups(np);
4997         niu_init_drr_weight(np);
4998
4999         err = niu_init_hostinfo(np);
5000         if (err)
5001                 return err;
5002
5003         for (i = 0; i < np->num_rx_rings; i++) {
5004                 struct rx_ring_info *rp = &np->rx_rings[i];
5005
5006                 err = niu_init_one_rx_channel(np, rp);
5007                 if (err)
5008                         return err;
5009         }
5010
5011         return 0;
5012 }
5013
5014 static int niu_set_ip_frag_rule(struct niu *np)
5015 {
5016         struct niu_parent *parent = np->parent;
5017         struct niu_classifier *cp = &np->clas;
5018         struct niu_tcam_entry *tp;
5019         int index, err;
5020
5021         index = cp->tcam_top;
5022         tp = &parent->tcam[index];
5023
5024         /* Note that the noport bit is the same in both ipv4 and
5025          * ipv6 format TCAM entries.
5026          */
5027         memset(tp, 0, sizeof(*tp));
5028         tp->key[1] = TCAM_V4KEY1_NOPORT;
5029         tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5030         tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5031                           ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5032         err = tcam_write(np, index, tp->key, tp->key_mask);
5033         if (err)
5034                 return err;
5035         err = tcam_assoc_write(np, index, tp->assoc_data);
5036         if (err)
5037                 return err;
5038         tp->valid = 1;
5039         cp->tcam_valid_entries++;
5040
5041         return 0;
5042 }
5043
5044 static int niu_init_classifier_hw(struct niu *np)
5045 {
5046         struct niu_parent *parent = np->parent;
5047         struct niu_classifier *cp = &np->clas;
5048         int i, err;
5049
5050         nw64(H1POLY, cp->h1_init);
5051         nw64(H2POLY, cp->h2_init);
5052
5053         err = niu_init_hostinfo(np);
5054         if (err)
5055                 return err;
5056
5057         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5058                 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5059
5060                 vlan_tbl_write(np, i, np->port,
5061                                vp->vlan_pref, vp->rdc_num);
5062         }
5063
5064         for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5065                 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5066
5067                 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5068                                                 ap->rdc_num, ap->mac_pref);
5069                 if (err)
5070                         return err;
5071         }
5072
5073         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5074                 int index = i - CLASS_CODE_USER_PROG1;
5075
5076                 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5077                 if (err)
5078                         return err;
5079                 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5080                 if (err)
5081                         return err;
5082         }
5083
5084         err = niu_set_ip_frag_rule(np);
5085         if (err)
5086                 return err;
5087
5088         tcam_enable(np, 1);
5089
5090         return 0;
5091 }
5092
5093 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5094 {
5095         nw64(ZCP_RAM_DATA0, data[0]);
5096         nw64(ZCP_RAM_DATA1, data[1]);
5097         nw64(ZCP_RAM_DATA2, data[2]);
5098         nw64(ZCP_RAM_DATA3, data[3]);
5099         nw64(ZCP_RAM_DATA4, data[4]);
5100         nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5101         nw64(ZCP_RAM_ACC,
5102              (ZCP_RAM_ACC_WRITE |
5103               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5104               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5105
5106         return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5107                                    1000, 100);
5108 }
5109
5110 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5111 {
5112         int err;
5113
5114         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5115                                   1000, 100);
5116         if (err) {
5117                 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5118                            (unsigned long long)nr64(ZCP_RAM_ACC));
5119                 return err;
5120         }
5121
5122         nw64(ZCP_RAM_ACC,
5123              (ZCP_RAM_ACC_READ |
5124               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5125               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5126
5127         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5128                                   1000, 100);
5129         if (err) {
5130                 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5131                            (unsigned long long)nr64(ZCP_RAM_ACC));
5132                 return err;
5133         }
5134
5135         data[0] = nr64(ZCP_RAM_DATA0);
5136         data[1] = nr64(ZCP_RAM_DATA1);
5137         data[2] = nr64(ZCP_RAM_DATA2);
5138         data[3] = nr64(ZCP_RAM_DATA3);
5139         data[4] = nr64(ZCP_RAM_DATA4);
5140
5141         return 0;
5142 }
5143
5144 static void niu_zcp_cfifo_reset(struct niu *np)
5145 {
5146         u64 val = nr64(RESET_CFIFO);
5147
5148         val |= RESET_CFIFO_RST(np->port);
5149         nw64(RESET_CFIFO, val);
5150         udelay(10);
5151
5152         val &= ~RESET_CFIFO_RST(np->port);
5153         nw64(RESET_CFIFO, val);
5154 }
5155
5156 static int niu_init_zcp(struct niu *np)
5157 {
5158         u64 data[5], rbuf[5];
5159         int i, max, err;
5160
5161         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5162                 if (np->port == 0 || np->port == 1)
5163                         max = ATLAS_P0_P1_CFIFO_ENTRIES;
5164                 else
5165                         max = ATLAS_P2_P3_CFIFO_ENTRIES;
5166         } else
5167                 max = NIU_CFIFO_ENTRIES;
5168
5169         data[0] = 0;
5170         data[1] = 0;
5171         data[2] = 0;
5172         data[3] = 0;
5173         data[4] = 0;
5174
5175         for (i = 0; i < max; i++) {
5176                 err = niu_zcp_write(np, i, data);
5177                 if (err)
5178                         return err;
5179                 err = niu_zcp_read(np, i, rbuf);
5180                 if (err)
5181                         return err;
5182         }
5183
5184         niu_zcp_cfifo_reset(np);
5185         nw64(CFIFO_ECC(np->port), 0);
5186         nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5187         (void) nr64(ZCP_INT_STAT);
5188         nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5189
5190         return 0;
5191 }
5192
5193 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5194 {
5195         u64 val = nr64_ipp(IPP_CFIG);
5196
5197         nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5198         nw64_ipp(IPP_DFIFO_WR_PTR, index);
5199         nw64_ipp(IPP_DFIFO_WR0, data[0]);
5200         nw64_ipp(IPP_DFIFO_WR1, data[1]);
5201         nw64_ipp(IPP_DFIFO_WR2, data[2]);
5202         nw64_ipp(IPP_DFIFO_WR3, data[3]);
5203         nw64_ipp(IPP_DFIFO_WR4, data[4]);
5204         nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5205 }
5206
5207 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5208 {
5209         nw64_ipp(IPP_DFIFO_RD_PTR, index);
5210         data[0] = nr64_ipp(IPP_DFIFO_RD0);
5211         data[1] = nr64_ipp(IPP_DFIFO_RD1);
5212         data[2] = nr64_ipp(IPP_DFIFO_RD2);
5213         data[3] = nr64_ipp(IPP_DFIFO_RD3);
5214         data[4] = nr64_ipp(IPP_DFIFO_RD4);
5215 }
5216
5217 static int niu_ipp_reset(struct niu *np)
5218 {
5219         return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5220                                           1000, 100, "IPP_CFIG");
5221 }
5222
5223 static int niu_init_ipp(struct niu *np)
5224 {
5225         u64 data[5], rbuf[5], val;
5226         int i, max, err;
5227
5228         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5229                 if (np->port == 0 || np->port == 1)
5230                         max = ATLAS_P0_P1_DFIFO_ENTRIES;
5231                 else
5232                         max = ATLAS_P2_P3_DFIFO_ENTRIES;
5233         } else
5234                 max = NIU_DFIFO_ENTRIES;
5235
5236         data[0] = 0;
5237         data[1] = 0;
5238         data[2] = 0;
5239         data[3] = 0;
5240         data[4] = 0;
5241
5242         for (i = 0; i < max; i++) {
5243                 niu_ipp_write(np, i, data);
5244                 niu_ipp_read(np, i, rbuf);
5245         }
5246
5247         (void) nr64_ipp(IPP_INT_STAT);
5248         (void) nr64_ipp(IPP_INT_STAT);
5249
5250         err = niu_ipp_reset(np);
5251         if (err)
5252                 return err;
5253
5254         (void) nr64_ipp(IPP_PKT_DIS);
5255         (void) nr64_ipp(IPP_BAD_CS_CNT);
5256         (void) nr64_ipp(IPP_ECC);
5257
5258         (void) nr64_ipp(IPP_INT_STAT);
5259
5260         nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5261
5262         val = nr64_ipp(IPP_CFIG);
5263         val &= ~IPP_CFIG_IP_MAX_PKT;
5264         val |= (IPP_CFIG_IPP_ENABLE |
5265                 IPP_CFIG_DFIFO_ECC_EN |
5266                 IPP_CFIG_DROP_BAD_CRC |
5267                 IPP_CFIG_CKSUM_EN |
5268                 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5269         nw64_ipp(IPP_CFIG, val);
5270
5271         return 0;
5272 }
5273
5274 static void niu_handle_led(struct niu *np, int status)
5275 {
5276         u64 val;
5277         val = nr64_mac(XMAC_CONFIG);
5278
5279         if ((np->flags & NIU_FLAGS_10G) != 0 &&
5280             (np->flags & NIU_FLAGS_FIBER) != 0) {
5281                 if (status) {
5282                         val |= XMAC_CONFIG_LED_POLARITY;
5283                         val &= ~XMAC_CONFIG_FORCE_LED_ON;
5284                 } else {
5285                         val |= XMAC_CONFIG_FORCE_LED_ON;
5286                         val &= ~XMAC_CONFIG_LED_POLARITY;
5287                 }
5288         }
5289
5290         nw64_mac(XMAC_CONFIG, val);
5291 }
5292
5293 static void niu_init_xif_xmac(struct niu *np)
5294 {
5295         struct niu_link_config *lp = &np->link_config;
5296         u64 val;
5297
5298         if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5299                 val = nr64(MIF_CONFIG);
5300                 val |= MIF_CONFIG_ATCA_GE;
5301                 nw64(MIF_CONFIG, val);
5302         }
5303
5304         val = nr64_mac(XMAC_CONFIG);
5305         val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5306
5307         val |= XMAC_CONFIG_TX_OUTPUT_EN;
5308
5309         if (lp->loopback_mode == LOOPBACK_MAC) {
5310                 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5311                 val |= XMAC_CONFIG_LOOPBACK;
5312         } else {
5313                 val &= ~XMAC_CONFIG_LOOPBACK;
5314         }
5315
5316         if (np->flags & NIU_FLAGS_10G) {
5317                 val &= ~XMAC_CONFIG_LFS_DISABLE;
5318         } else {
5319                 val |= XMAC_CONFIG_LFS_DISABLE;
5320                 if (!(np->flags & NIU_FLAGS_FIBER) &&
5321                     !(np->flags & NIU_FLAGS_XCVR_SERDES))
5322                         val |= XMAC_CONFIG_1G_PCS_BYPASS;
5323                 else
5324                         val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5325         }
5326
5327         val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5328
5329         if (lp->active_speed == SPEED_100)
5330                 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5331         else
5332                 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5333
5334         nw64_mac(XMAC_CONFIG, val);
5335
5336         val = nr64_mac(XMAC_CONFIG);
5337         val &= ~XMAC_CONFIG_MODE_MASK;
5338         if (np->flags & NIU_FLAGS_10G) {
5339                 val |= XMAC_CONFIG_MODE_XGMII;
5340         } else {
5341                 if (lp->active_speed == SPEED_1000)
5342                         val |= XMAC_CONFIG_MODE_GMII;
5343                 else
5344                         val |= XMAC_CONFIG_MODE_MII;
5345         }
5346
5347         nw64_mac(XMAC_CONFIG, val);
5348 }
5349
5350 static void niu_init_xif_bmac(struct niu *np)
5351 {
5352         struct niu_link_config *lp = &np->link_config;
5353         u64 val;
5354
5355         val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5356
5357         if (lp->loopback_mode == LOOPBACK_MAC)
5358                 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5359         else
5360                 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5361
5362         if (lp->active_speed == SPEED_1000)
5363                 val |= BMAC_XIF_CONFIG_GMII_MODE;
5364         else
5365                 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5366
5367         val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5368                  BMAC_XIF_CONFIG_LED_POLARITY);
5369
5370         if (!(np->flags & NIU_FLAGS_10G) &&
5371             !(np->flags & NIU_FLAGS_FIBER) &&
5372             lp->active_speed == SPEED_100)
5373                 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5374         else
5375                 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5376
5377         nw64_mac(BMAC_XIF_CONFIG, val);
5378 }
5379
5380 static void niu_init_xif(struct niu *np)
5381 {
5382         if (np->flags & NIU_FLAGS_XMAC)
5383                 niu_init_xif_xmac(np);
5384         else
5385                 niu_init_xif_bmac(np);
5386 }
5387
5388 static void niu_pcs_mii_reset(struct niu *np)
5389 {
5390         int limit = 1000;
5391         u64 val = nr64_pcs(PCS_MII_CTL);
5392         val |= PCS_MII_CTL_RST;
5393         nw64_pcs(PCS_MII_CTL, val);
5394         while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5395                 udelay(100);
5396                 val = nr64_pcs(PCS_MII_CTL);
5397         }
5398 }
5399
5400 static void niu_xpcs_reset(struct niu *np)
5401 {
5402         int limit = 1000;
5403         u64 val = nr64_xpcs(XPCS_CONTROL1);
5404         val |= XPCS_CONTROL1_RESET;
5405         nw64_xpcs(XPCS_CONTROL1, val);
5406         while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5407                 udelay(100);
5408                 val = nr64_xpcs(XPCS_CONTROL1);
5409         }
5410 }
5411
5412 static int niu_init_pcs(struct niu *np)
5413 {
5414         struct niu_link_config *lp = &np->link_config;
5415         u64 val;
5416
5417         switch (np->flags & (NIU_FLAGS_10G |
5418                              NIU_FLAGS_FIBER |
5419                              NIU_FLAGS_XCVR_SERDES)) {
5420         case NIU_FLAGS_FIBER:
5421                 /* 1G fiber */
5422                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5423                 nw64_pcs(PCS_DPATH_MODE, 0);
5424                 niu_pcs_mii_reset(np);
5425                 break;
5426
5427         case NIU_FLAGS_10G:
5428         case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5429         case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5430                 /* 10G SERDES */
5431                 if (!(np->flags & NIU_FLAGS_XMAC))
5432                         return -EINVAL;
5433
5434                 /* 10G copper or fiber */
5435                 val = nr64_mac(XMAC_CONFIG);
5436                 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5437                 nw64_mac(XMAC_CONFIG, val);
5438
5439                 niu_xpcs_reset(np);
5440
5441                 val = nr64_xpcs(XPCS_CONTROL1);
5442                 if (lp->loopback_mode == LOOPBACK_PHY)
5443                         val |= XPCS_CONTROL1_LOOPBACK;
5444                 else
5445                         val &= ~XPCS_CONTROL1_LOOPBACK;
5446                 nw64_xpcs(XPCS_CONTROL1, val);
5447
5448                 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5449                 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5450                 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5451                 break;
5452
5453
5454         case NIU_FLAGS_XCVR_SERDES:
5455                 /* 1G SERDES */
5456                 niu_pcs_mii_reset(np);
5457                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5458                 nw64_pcs(PCS_DPATH_MODE, 0);
5459                 break;
5460
5461         case 0:
5462                 /* 1G copper */
5463         case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5464                 /* 1G RGMII FIBER */
5465                 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5466                 niu_pcs_mii_reset(np);
5467                 break;
5468
5469         default:
5470                 return -EINVAL;
5471         }
5472
5473         return 0;
5474 }
5475
5476 static int niu_reset_tx_xmac(struct niu *np)
5477 {
5478         return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5479                                           (XTXMAC_SW_RST_REG_RS |
5480                                            XTXMAC_SW_RST_SOFT_RST),
5481                                           1000, 100, "XTXMAC_SW_RST");
5482 }
5483
5484 static int niu_reset_tx_bmac(struct niu *np)
5485 {
5486         int limit;
5487
5488         nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5489         limit = 1000;
5490         while (--limit >= 0) {
5491                 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5492                         break;
5493                 udelay(100);
5494         }
5495         if (limit < 0) {
5496                 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
5497                         np->port,
5498                         (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5499                 return -ENODEV;
5500         }
5501
5502         return 0;
5503 }
5504
5505 static int niu_reset_tx_mac(struct niu *np)
5506 {
5507         if (np->flags & NIU_FLAGS_XMAC)
5508                 return niu_reset_tx_xmac(np);
5509         else
5510                 return niu_reset_tx_bmac(np);
5511 }
5512
5513 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5514 {
5515         u64 val;
5516
5517         val = nr64_mac(XMAC_MIN);
5518         val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5519                  XMAC_MIN_RX_MIN_PKT_SIZE);
5520         val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5521         val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5522         nw64_mac(XMAC_MIN, val);
5523
5524         nw64_mac(XMAC_MAX, max);
5525
5526         nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5527
5528         val = nr64_mac(XMAC_IPG);
5529         if (np->flags & NIU_FLAGS_10G) {
5530                 val &= ~XMAC_IPG_IPG_XGMII;
5531                 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5532         } else {
5533                 val &= ~XMAC_IPG_IPG_MII_GMII;
5534                 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5535         }
5536         nw64_mac(XMAC_IPG, val);
5537
5538         val = nr64_mac(XMAC_CONFIG);
5539         val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5540                  XMAC_CONFIG_STRETCH_MODE |
5541                  XMAC_CONFIG_VAR_MIN_IPG_EN |
5542                  XMAC_CONFIG_TX_ENABLE);
5543         nw64_mac(XMAC_CONFIG, val);
5544
5545         nw64_mac(TXMAC_FRM_CNT, 0);
5546         nw64_mac(TXMAC_BYTE_CNT, 0);
5547 }
5548
5549 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5550 {
5551         u64 val;
5552
5553         nw64_mac(BMAC_MIN_FRAME, min);
5554         nw64_mac(BMAC_MAX_FRAME, max);
5555
5556         nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5557         nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5558         nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5559
5560         val = nr64_mac(BTXMAC_CONFIG);
5561         val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5562                  BTXMAC_CONFIG_ENABLE);
5563         nw64_mac(BTXMAC_CONFIG, val);
5564 }
5565
5566 static void niu_init_tx_mac(struct niu *np)
5567 {
5568         u64 min, max;
5569
5570         min = 64;
5571         if (np->dev->mtu > ETH_DATA_LEN)
5572                 max = 9216;
5573         else
5574                 max = 1522;
5575
5576         /* The XMAC_MIN register only accepts values for TX min which
5577          * have the low 3 bits cleared.
5578          */
5579         BUG_ON(min & 0x7);
5580
5581         if (np->flags & NIU_FLAGS_XMAC)
5582                 niu_init_tx_xmac(np, min, max);
5583         else
5584                 niu_init_tx_bmac(np, min, max);
5585 }
5586
5587 static int niu_reset_rx_xmac(struct niu *np)
5588 {
5589         int limit;
5590
5591         nw64_mac(XRXMAC_SW_RST,
5592                  XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5593         limit = 1000;
5594         while (--limit >= 0) {
5595                 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5596                                                  XRXMAC_SW_RST_SOFT_RST)))
5597                         break;
5598                 udelay(100);
5599         }
5600         if (limit < 0) {
5601                 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
5602                         np->port,
5603                         (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5604                 return -ENODEV;
5605         }
5606
5607         return 0;
5608 }
5609
5610 static int niu_reset_rx_bmac(struct niu *np)
5611 {
5612         int limit;
5613
5614         nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5615         limit = 1000;
5616         while (--limit >= 0) {
5617                 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5618                         break;
5619                 udelay(100);
5620         }
5621         if (limit < 0) {
5622                 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
5623                         np->port,
5624                         (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5625                 return -ENODEV;
5626         }
5627
5628         return 0;
5629 }
5630
5631 static int niu_reset_rx_mac(struct niu *np)
5632 {
5633         if (np->flags & NIU_FLAGS_XMAC)
5634                 return niu_reset_rx_xmac(np);
5635         else
5636                 return niu_reset_rx_bmac(np);
5637 }
5638
5639 static void niu_init_rx_xmac(struct niu *np)
5640 {
5641         struct niu_parent *parent = np->parent;
5642         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5643         int first_rdc_table = tp->first_table_num;
5644         unsigned long i;
5645         u64 val;
5646
5647         nw64_mac(XMAC_ADD_FILT0, 0);
5648         nw64_mac(XMAC_ADD_FILT1, 0);
5649         nw64_mac(XMAC_ADD_FILT2, 0);
5650         nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5651         nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5652         for (i = 0; i < MAC_NUM_HASH; i++)
5653                 nw64_mac(XMAC_HASH_TBL(i), 0);
5654         nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5655         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5656         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5657
5658         val = nr64_mac(XMAC_CONFIG);
5659         val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5660                  XMAC_CONFIG_PROMISCUOUS |
5661                  XMAC_CONFIG_PROMISC_GROUP |
5662                  XMAC_CONFIG_ERR_CHK_DIS |
5663                  XMAC_CONFIG_RX_CRC_CHK_DIS |
5664                  XMAC_CONFIG_RESERVED_MULTICAST |
5665                  XMAC_CONFIG_RX_CODEV_CHK_DIS |
5666                  XMAC_CONFIG_ADDR_FILTER_EN |
5667                  XMAC_CONFIG_RCV_PAUSE_ENABLE |
5668                  XMAC_CONFIG_STRIP_CRC |
5669                  XMAC_CONFIG_PASS_FLOW_CTRL |
5670                  XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5671         val |= (XMAC_CONFIG_HASH_FILTER_EN);
5672         nw64_mac(XMAC_CONFIG, val);
5673
5674         nw64_mac(RXMAC_BT_CNT, 0);
5675         nw64_mac(RXMAC_BC_FRM_CNT, 0);
5676         nw64_mac(RXMAC_MC_FRM_CNT, 0);
5677         nw64_mac(RXMAC_FRAG_CNT, 0);
5678         nw64_mac(RXMAC_HIST_CNT1, 0);
5679         nw64_mac(RXMAC_HIST_CNT2, 0);
5680         nw64_mac(RXMAC_HIST_CNT3, 0);
5681         nw64_mac(RXMAC_HIST_CNT4, 0);
5682         nw64_mac(RXMAC_HIST_CNT5, 0);
5683         nw64_mac(RXMAC_HIST_CNT6, 0);
5684         nw64_mac(RXMAC_HIST_CNT7, 0);
5685         nw64_mac(RXMAC_MPSZER_CNT, 0);
5686         nw64_mac(RXMAC_CRC_ER_CNT, 0);
5687         nw64_mac(RXMAC_CD_VIO_CNT, 0);
5688         nw64_mac(LINK_FAULT_CNT, 0);
5689 }
5690
5691 static void niu_init_rx_bmac(struct niu *np)
5692 {
5693         struct niu_parent *parent = np->parent;
5694         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5695         int first_rdc_table = tp->first_table_num;
5696         unsigned long i;
5697         u64 val;
5698
5699         nw64_mac(BMAC_ADD_FILT0, 0);
5700         nw64_mac(BMAC_ADD_FILT1, 0);
5701         nw64_mac(BMAC_ADD_FILT2, 0);
5702         nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5703         nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5704         for (i = 0; i < MAC_NUM_HASH; i++)
5705                 nw64_mac(BMAC_HASH_TBL(i), 0);
5706         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5707         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5708         nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5709
5710         val = nr64_mac(BRXMAC_CONFIG);
5711         val &= ~(BRXMAC_CONFIG_ENABLE |
5712                  BRXMAC_CONFIG_STRIP_PAD |
5713                  BRXMAC_CONFIG_STRIP_FCS |
5714                  BRXMAC_CONFIG_PROMISC |
5715                  BRXMAC_CONFIG_PROMISC_GRP |
5716                  BRXMAC_CONFIG_ADDR_FILT_EN |
5717                  BRXMAC_CONFIG_DISCARD_DIS);
5718         val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5719         nw64_mac(BRXMAC_CONFIG, val);
5720
5721         val = nr64_mac(BMAC_ADDR_CMPEN);
5722         val |= BMAC_ADDR_CMPEN_EN0;
5723         nw64_mac(BMAC_ADDR_CMPEN, val);
5724 }
5725
5726 static void niu_init_rx_mac(struct niu *np)
5727 {
5728         niu_set_primary_mac(np, np->dev->dev_addr);
5729
5730         if (np->flags & NIU_FLAGS_XMAC)
5731                 niu_init_rx_xmac(np);
5732         else
5733                 niu_init_rx_bmac(np);
5734 }
5735
5736 static void niu_enable_tx_xmac(struct niu *np, int on)
5737 {
5738         u64 val = nr64_mac(XMAC_CONFIG);
5739
5740         if (on)
5741                 val |= XMAC_CONFIG_TX_ENABLE;
5742         else
5743                 val &= ~XMAC_CONFIG_TX_ENABLE;
5744         nw64_mac(XMAC_CONFIG, val);
5745 }
5746
5747 static void niu_enable_tx_bmac(struct niu *np, int on)
5748 {
5749         u64 val = nr64_mac(BTXMAC_CONFIG);
5750
5751         if (on)
5752                 val |= BTXMAC_CONFIG_ENABLE;
5753         else
5754                 val &= ~BTXMAC_CONFIG_ENABLE;
5755         nw64_mac(BTXMAC_CONFIG, val);
5756 }
5757
5758 static void niu_enable_tx_mac(struct niu *np, int on)
5759 {
5760         if (np->flags & NIU_FLAGS_XMAC)
5761                 niu_enable_tx_xmac(np, on);
5762         else
5763                 niu_enable_tx_bmac(np, on);
5764 }
5765
5766 static void niu_enable_rx_xmac(struct niu *np, int on)
5767 {
5768         u64 val = nr64_mac(XMAC_CONFIG);
5769
5770         val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5771                  XMAC_CONFIG_PROMISCUOUS);
5772
5773         if (np->flags & NIU_FLAGS_MCAST)
5774                 val |= XMAC_CONFIG_HASH_FILTER_EN;
5775         if (np->flags & NIU_FLAGS_PROMISC)
5776                 val |= XMAC_CONFIG_PROMISCUOUS;
5777
5778         if (on)
5779                 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5780         else
5781                 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5782         nw64_mac(XMAC_CONFIG, val);
5783 }
5784
5785 static void niu_enable_rx_bmac(struct niu *np, int on)
5786 {
5787         u64 val = nr64_mac(BRXMAC_CONFIG);
5788
5789         val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5790                  BRXMAC_CONFIG_PROMISC);
5791
5792         if (np->flags & NIU_FLAGS_MCAST)
5793                 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5794         if (np->flags & NIU_FLAGS_PROMISC)
5795                 val |= BRXMAC_CONFIG_PROMISC;
5796
5797         if (on)
5798                 val |= BRXMAC_CONFIG_ENABLE;
5799         else
5800                 val &= ~BRXMAC_CONFIG_ENABLE;
5801         nw64_mac(BRXMAC_CONFIG, val);
5802 }
5803
5804 static void niu_enable_rx_mac(struct niu *np, int on)
5805 {
5806         if (np->flags & NIU_FLAGS_XMAC)
5807                 niu_enable_rx_xmac(np, on);
5808         else
5809                 niu_enable_rx_bmac(np, on);
5810 }
5811
5812 static int niu_init_mac(struct niu *np)
5813 {
5814         int err;
5815
5816         niu_init_xif(np);
5817         err = niu_init_pcs(np);
5818         if (err)
5819                 return err;
5820
5821         err = niu_reset_tx_mac(np);
5822         if (err)
5823                 return err;
5824         niu_init_tx_mac(np);
5825         err = niu_reset_rx_mac(np);
5826         if (err)
5827                 return err;
5828         niu_init_rx_mac(np);
5829
5830         /* This looks hookey but the RX MAC reset we just did will
5831          * undo some of the state we setup in niu_init_tx_mac() so we
5832          * have to call it again.  In particular, the RX MAC reset will
5833          * set the XMAC_MAX register back to it's default value.
5834          */
5835         niu_init_tx_mac(np);
5836         niu_enable_tx_mac(np, 1);
5837
5838         niu_enable_rx_mac(np, 1);
5839
5840         return 0;
5841 }
5842
5843 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5844 {
5845         (void) niu_tx_channel_stop(np, rp->tx_channel);
5846 }
5847
5848 static void niu_stop_tx_channels(struct niu *np)
5849 {
5850         int i;
5851
5852         for (i = 0; i < np->num_tx_rings; i++) {
5853                 struct tx_ring_info *rp = &np->tx_rings[i];
5854
5855                 niu_stop_one_tx_channel(np, rp);
5856         }
5857 }
5858
5859 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5860 {
5861         (void) niu_tx_channel_reset(np, rp->tx_channel);
5862 }
5863
5864 static void niu_reset_tx_channels(struct niu *np)
5865 {
5866         int i;
5867
5868         for (i = 0; i < np->num_tx_rings; i++) {
5869                 struct tx_ring_info *rp = &np->tx_rings[i];
5870
5871                 niu_reset_one_tx_channel(np, rp);
5872         }
5873 }
5874
5875 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5876 {
5877         (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5878 }
5879
5880 static void niu_stop_rx_channels(struct niu *np)
5881 {
5882         int i;
5883
5884         for (i = 0; i < np->num_rx_rings; i++) {
5885                 struct rx_ring_info *rp = &np->rx_rings[i];
5886
5887                 niu_stop_one_rx_channel(np, rp);
5888         }
5889 }
5890
5891 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5892 {
5893         int channel = rp->rx_channel;
5894
5895         (void) niu_rx_channel_reset(np, channel);
5896         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5897         nw64(RX_DMA_CTL_STAT(channel), 0);
5898         (void) niu_enable_rx_channel(np, channel, 0);
5899 }
5900
5901 static void niu_reset_rx_channels(struct niu *np)
5902 {
5903         int i;
5904
5905         for (i = 0; i < np->num_rx_rings; i++) {
5906                 struct rx_ring_info *rp = &np->rx_rings[i];
5907
5908                 niu_reset_one_rx_channel(np, rp);
5909         }
5910 }
5911
5912 static void niu_disable_ipp(struct niu *np)
5913 {
5914         u64 rd, wr, val;
5915         int limit;
5916
5917         rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5918         wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5919         limit = 100;
5920         while (--limit >= 0 && (rd != wr)) {
5921                 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5922                 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5923         }
5924         if (limit < 0 &&
5925             (rd != 0 && wr != 1)) {
5926                 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5927                            (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5928                            (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
5929         }
5930
5931         val = nr64_ipp(IPP_CFIG);
5932         val &= ~(IPP_CFIG_IPP_ENABLE |
5933                  IPP_CFIG_DFIFO_ECC_EN |
5934                  IPP_CFIG_DROP_BAD_CRC |
5935                  IPP_CFIG_CKSUM_EN);
5936         nw64_ipp(IPP_CFIG, val);
5937
5938         (void) niu_ipp_reset(np);
5939 }
5940
5941 static int niu_init_hw(struct niu *np)
5942 {
5943         int i, err;
5944
5945         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
5946         niu_txc_enable_port(np, 1);
5947         niu_txc_port_dma_enable(np, 1);
5948         niu_txc_set_imask(np, 0);
5949
5950         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
5951         for (i = 0; i < np->num_tx_rings; i++) {
5952                 struct tx_ring_info *rp = &np->tx_rings[i];
5953
5954                 err = niu_init_one_tx_channel(np, rp);
5955                 if (err)
5956                         return err;
5957         }
5958
5959         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
5960         err = niu_init_rx_channels(np);
5961         if (err)
5962                 goto out_uninit_tx_channels;
5963
5964         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
5965         err = niu_init_classifier_hw(np);
5966         if (err)
5967                 goto out_uninit_rx_channels;
5968
5969         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
5970         err = niu_init_zcp(np);
5971         if (err)
5972                 goto out_uninit_rx_channels;
5973
5974         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
5975         err = niu_init_ipp(np);
5976         if (err)
5977                 goto out_uninit_rx_channels;
5978
5979         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
5980         err = niu_init_mac(np);
5981         if (err)
5982                 goto out_uninit_ipp;
5983
5984         return 0;
5985
5986 out_uninit_ipp:
5987         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
5988         niu_disable_ipp(np);
5989
5990 out_uninit_rx_channels:
5991         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
5992         niu_stop_rx_channels(np);
5993         niu_reset_rx_channels(np);
5994
5995 out_uninit_tx_channels:
5996         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
5997         niu_stop_tx_channels(np);
5998         niu_reset_tx_channels(np);
5999
6000         return err;
6001 }
6002
6003 static void niu_stop_hw(struct niu *np)
6004 {
6005         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
6006         niu_enable_interrupts(np, 0);
6007
6008         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
6009         niu_enable_rx_mac(np, 0);
6010
6011         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
6012         niu_disable_ipp(np);
6013
6014         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
6015         niu_stop_tx_channels(np);
6016
6017         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
6018         niu_stop_rx_channels(np);
6019
6020         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
6021         niu_reset_tx_channels(np);
6022
6023         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
6024         niu_reset_rx_channels(np);
6025 }
6026
6027 static void niu_set_irq_name(struct niu *np)
6028 {
6029         int port = np->port;
6030         int i, j = 1;
6031
6032         sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6033
6034         if (port == 0) {
6035                 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6036                 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6037                 j = 3;
6038         }
6039
6040         for (i = 0; i < np->num_ldg - j; i++) {
6041                 if (i < np->num_rx_rings)
6042                         sprintf(np->irq_name[i+j], "%s-rx-%d",
6043                                 np->dev->name, i);
6044                 else if (i < np->num_tx_rings + np->num_rx_rings)
6045                         sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6046                                 i - np->num_rx_rings);
6047         }
6048 }
6049
6050 static int niu_request_irq(struct niu *np)
6051 {
6052         int i, j, err;
6053
6054         niu_set_irq_name(np);
6055
6056         err = 0;
6057         for (i = 0; i < np->num_ldg; i++) {
6058                 struct niu_ldg *lp = &np->ldg[i];
6059
6060                 err = request_irq(lp->irq, niu_interrupt,
6061                                   IRQF_SHARED | IRQF_SAMPLE_RANDOM,
6062                                   np->irq_name[i], lp);
6063                 if (err)
6064                         goto out_free_irqs;
6065
6066         }
6067
6068         return 0;
6069
6070 out_free_irqs:
6071         for (j = 0; j < i; j++) {
6072                 struct niu_ldg *lp = &np->ldg[j];
6073
6074                 free_irq(lp->irq, lp);
6075         }
6076         return err;
6077 }
6078
6079 static void niu_free_irq(struct niu *np)
6080 {
6081         int i;
6082
6083         for (i = 0; i < np->num_ldg; i++) {
6084                 struct niu_ldg *lp = &np->ldg[i];
6085
6086                 free_irq(lp->irq, lp);
6087         }
6088 }
6089
6090 static void niu_enable_napi(struct niu *np)
6091 {
6092         int i;
6093
6094         for (i = 0; i < np->num_ldg; i++)
6095                 napi_enable(&np->ldg[i].napi);
6096 }
6097
6098 static void niu_disable_napi(struct niu *np)
6099 {
6100         int i;
6101
6102         for (i = 0; i < np->num_ldg; i++)
6103                 napi_disable(&np->ldg[i].napi);
6104 }
6105
6106 static int niu_open(struct net_device *dev)
6107 {
6108         struct niu *np = netdev_priv(dev);
6109         int err;
6110
6111         netif_carrier_off(dev);
6112
6113         err = niu_alloc_channels(np);
6114         if (err)
6115                 goto out_err;
6116
6117         err = niu_enable_interrupts(np, 0);
6118         if (err)
6119                 goto out_free_channels;
6120
6121         err = niu_request_irq(np);
6122         if (err)
6123                 goto out_free_channels;
6124
6125         niu_enable_napi(np);
6126
6127         spin_lock_irq(&np->lock);
6128
6129         err = niu_init_hw(np);
6130         if (!err) {
6131                 init_timer(&np->timer);
6132                 np->timer.expires = jiffies + HZ;
6133                 np->timer.data = (unsigned long) np;
6134                 np->timer.function = niu_timer;
6135
6136                 err = niu_enable_interrupts(np, 1);
6137                 if (err)
6138                         niu_stop_hw(np);
6139         }
6140
6141         spin_unlock_irq(&np->lock);
6142
6143         if (err) {
6144                 niu_disable_napi(np);
6145                 goto out_free_irq;
6146         }
6147
6148         netif_tx_start_all_queues(dev);
6149
6150         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6151                 netif_carrier_on(dev);
6152
6153         add_timer(&np->timer);
6154
6155         return 0;
6156
6157 out_free_irq:
6158         niu_free_irq(np);
6159
6160 out_free_channels:
6161         niu_free_channels(np);
6162
6163 out_err:
6164         return err;
6165 }
6166
6167 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6168 {
6169         cancel_work_sync(&np->reset_task);
6170
6171         niu_disable_napi(np);
6172         netif_tx_stop_all_queues(dev);
6173
6174         del_timer_sync(&np->timer);
6175
6176         spin_lock_irq(&np->lock);
6177
6178         niu_stop_hw(np);
6179
6180         spin_unlock_irq(&np->lock);
6181 }
6182
6183 static int niu_close(struct net_device *dev)
6184 {
6185         struct niu *np = netdev_priv(dev);
6186
6187         niu_full_shutdown(np, dev);
6188
6189         niu_free_irq(np);
6190
6191         niu_free_channels(np);
6192
6193         niu_handle_led(np, 0);
6194
6195         return 0;
6196 }
6197
6198 static void niu_sync_xmac_stats(struct niu *np)
6199 {
6200         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6201
6202         mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6203         mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6204
6205         mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6206         mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6207         mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6208         mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6209         mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6210         mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6211         mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6212         mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6213         mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6214         mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6215         mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6216         mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6217         mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6218         mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6219         mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6220         mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6221 }
6222
6223 static void niu_sync_bmac_stats(struct niu *np)
6224 {
6225         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6226
6227         mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6228         mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6229
6230         mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6231         mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6232         mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6233         mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6234 }
6235
6236 static void niu_sync_mac_stats(struct niu *np)
6237 {
6238         if (np->flags & NIU_FLAGS_XMAC)
6239                 niu_sync_xmac_stats(np);
6240         else
6241                 niu_sync_bmac_stats(np);
6242 }
6243
6244 static void niu_get_rx_stats(struct niu *np)
6245 {
6246         unsigned long pkts, dropped, errors, bytes;
6247         int i;
6248
6249         pkts = dropped = errors = bytes = 0;
6250         for (i = 0; i < np->num_rx_rings; i++) {
6251                 struct rx_ring_info *rp = &np->rx_rings[i];
6252
6253                 niu_sync_rx_discard_stats(np, rp, 0);
6254
6255                 pkts += rp->rx_packets;
6256                 bytes += rp->rx_bytes;
6257                 dropped += rp->rx_dropped;
6258                 errors += rp->rx_errors;
6259         }
6260         np->dev->stats.rx_packets = pkts;
6261         np->dev->stats.rx_bytes = bytes;
6262         np->dev->stats.rx_dropped = dropped;
6263         np->dev->stats.rx_errors = errors;
6264 }
6265
6266 static void niu_get_tx_stats(struct niu *np)
6267 {
6268         unsigned long pkts, errors, bytes;
6269         int i;
6270
6271         pkts = errors = bytes = 0;
6272         for (i = 0; i < np->num_tx_rings; i++) {
6273                 struct tx_ring_info *rp = &np->tx_rings[i];
6274
6275                 pkts += rp->tx_packets;
6276                 bytes += rp->tx_bytes;
6277                 errors += rp->tx_errors;
6278         }
6279         np->dev->stats.tx_packets = pkts;
6280         np->dev->stats.tx_bytes = bytes;
6281         np->dev->stats.tx_errors = errors;
6282 }
6283
6284 static struct net_device_stats *niu_get_stats(struct net_device *dev)
6285 {
6286         struct niu *np = netdev_priv(dev);
6287
6288         niu_get_rx_stats(np);
6289         niu_get_tx_stats(np);
6290
6291         return &dev->stats;
6292 }
6293
6294 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6295 {
6296         int i;
6297
6298         for (i = 0; i < 16; i++)
6299                 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6300 }
6301
6302 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6303 {
6304         int i;
6305
6306         for (i = 0; i < 16; i++)
6307                 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6308 }
6309
6310 static void niu_load_hash(struct niu *np, u16 *hash)
6311 {
6312         if (np->flags & NIU_FLAGS_XMAC)
6313                 niu_load_hash_xmac(np, hash);
6314         else
6315                 niu_load_hash_bmac(np, hash);
6316 }
6317
6318 static void niu_set_rx_mode(struct net_device *dev)
6319 {
6320         struct niu *np = netdev_priv(dev);
6321         int i, alt_cnt, err;
6322         struct netdev_hw_addr *ha;
6323         unsigned long flags;
6324         u16 hash[16] = { 0, };
6325
6326         spin_lock_irqsave(&np->lock, flags);
6327         niu_enable_rx_mac(np, 0);
6328
6329         np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6330         if (dev->flags & IFF_PROMISC)
6331                 np->flags |= NIU_FLAGS_PROMISC;
6332         if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
6333                 np->flags |= NIU_FLAGS_MCAST;
6334
6335         alt_cnt = netdev_uc_count(dev);
6336         if (alt_cnt > niu_num_alt_addr(np)) {
6337                 alt_cnt = 0;
6338                 np->flags |= NIU_FLAGS_PROMISC;
6339         }
6340
6341         if (alt_cnt) {
6342                 int index = 0;
6343
6344                 netdev_for_each_uc_addr(ha, dev) {
6345                         err = niu_set_alt_mac(np, index, ha->addr);
6346                         if (err)
6347                                 netdev_warn(dev, "Error %d adding alt mac %d\n",
6348                                             err, index);
6349                         err = niu_enable_alt_mac(np, index, 1);
6350                         if (err)
6351                                 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6352                                             err, index);
6353
6354                         index++;
6355                 }
6356         } else {
6357                 int alt_start;
6358                 if (np->flags & NIU_FLAGS_XMAC)
6359                         alt_start = 0;
6360                 else
6361                         alt_start = 1;
6362                 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6363                         err = niu_enable_alt_mac(np, i, 0);
6364                         if (err)
6365                                 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6366                                             err, i);
6367                 }
6368         }
6369         if (dev->flags & IFF_ALLMULTI) {
6370                 for (i = 0; i < 16; i++)
6371                         hash[i] = 0xffff;
6372         } else if (!netdev_mc_empty(dev)) {
6373                 netdev_for_each_mc_addr(ha, dev) {
6374                         u32 crc = ether_crc_le(ETH_ALEN, ha->addr);
6375
6376                         crc >>= 24;
6377                         hash[crc >> 4] |= (1 << (15 - (crc &