drivers/net/pcmcia: Use pr_<level> and netdev_<level>
[linux-2.6.git] / drivers / net / niu.c
1 /* niu.c: Neptune ethernet driver.
2  *
3  * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
4  */
5
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/netdevice.h>
13 #include <linux/ethtool.h>
14 #include <linux/etherdevice.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/bitops.h>
18 #include <linux/mii.h>
19 #include <linux/if_ether.h>
20 #include <linux/if_vlan.h>
21 #include <linux/ip.h>
22 #include <linux/in.h>
23 #include <linux/ipv6.h>
24 #include <linux/log2.h>
25 #include <linux/jiffies.h>
26 #include <linux/crc32.h>
27 #include <linux/list.h>
28 #include <linux/slab.h>
29
30 #include <linux/io.h>
31 #include <linux/of_device.h>
32
33 #include "niu.h"
34
35 #define DRV_MODULE_NAME         "niu"
36 #define DRV_MODULE_VERSION      "1.1"
37 #define DRV_MODULE_RELDATE      "Apr 22, 2010"
38
39 static char version[] __devinitdata =
40         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
41
42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43 MODULE_DESCRIPTION("NIU ethernet driver");
44 MODULE_LICENSE("GPL");
45 MODULE_VERSION(DRV_MODULE_VERSION);
46
47 #ifndef readq
48 static u64 readq(void __iomem *reg)
49 {
50         return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
51 }
52
53 static void writeq(u64 val, void __iomem *reg)
54 {
55         writel(val & 0xffffffff, reg);
56         writel(val >> 32, reg + 0x4UL);
57 }
58 #endif
59
60 static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl) = {
61         {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
62         {}
63 };
64
65 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
66
67 #define NIU_TX_TIMEOUT                  (5 * HZ)
68
69 #define nr64(reg)               readq(np->regs + (reg))
70 #define nw64(reg, val)          writeq((val), np->regs + (reg))
71
72 #define nr64_mac(reg)           readq(np->mac_regs + (reg))
73 #define nw64_mac(reg, val)      writeq((val), np->mac_regs + (reg))
74
75 #define nr64_ipp(reg)           readq(np->regs + np->ipp_off + (reg))
76 #define nw64_ipp(reg, val)      writeq((val), np->regs + np->ipp_off + (reg))
77
78 #define nr64_pcs(reg)           readq(np->regs + np->pcs_off + (reg))
79 #define nw64_pcs(reg, val)      writeq((val), np->regs + np->pcs_off + (reg))
80
81 #define nr64_xpcs(reg)          readq(np->regs + np->xpcs_off + (reg))
82 #define nw64_xpcs(reg, val)     writeq((val), np->regs + np->xpcs_off + (reg))
83
84 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
85
86 static int niu_debug;
87 static int debug = -1;
88 module_param(debug, int, 0);
89 MODULE_PARM_DESC(debug, "NIU debug level");
90
91 #define niu_lock_parent(np, flags) \
92         spin_lock_irqsave(&np->parent->lock, flags)
93 #define niu_unlock_parent(np, flags) \
94         spin_unlock_irqrestore(&np->parent->lock, flags)
95
96 static int serdes_init_10g_serdes(struct niu *np);
97
98 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
99                                      u64 bits, int limit, int delay)
100 {
101         while (--limit >= 0) {
102                 u64 val = nr64_mac(reg);
103
104                 if (!(val & bits))
105                         break;
106                 udelay(delay);
107         }
108         if (limit < 0)
109                 return -ENODEV;
110         return 0;
111 }
112
113 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
114                                         u64 bits, int limit, int delay,
115                                         const char *reg_name)
116 {
117         int err;
118
119         nw64_mac(reg, bits);
120         err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
121         if (err)
122                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
123                            (unsigned long long)bits, reg_name,
124                            (unsigned long long)nr64_mac(reg));
125         return err;
126 }
127
128 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
129 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
130         __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
131 })
132
133 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
134                                      u64 bits, int limit, int delay)
135 {
136         while (--limit >= 0) {
137                 u64 val = nr64_ipp(reg);
138
139                 if (!(val & bits))
140                         break;
141                 udelay(delay);
142         }
143         if (limit < 0)
144                 return -ENODEV;
145         return 0;
146 }
147
148 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
149                                         u64 bits, int limit, int delay,
150                                         const char *reg_name)
151 {
152         int err;
153         u64 val;
154
155         val = nr64_ipp(reg);
156         val |= bits;
157         nw64_ipp(reg, val);
158
159         err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
160         if (err)
161                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
162                            (unsigned long long)bits, reg_name,
163                            (unsigned long long)nr64_ipp(reg));
164         return err;
165 }
166
167 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
168 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
169         __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
170 })
171
172 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
173                                  u64 bits, int limit, int delay)
174 {
175         while (--limit >= 0) {
176                 u64 val = nr64(reg);
177
178                 if (!(val & bits))
179                         break;
180                 udelay(delay);
181         }
182         if (limit < 0)
183                 return -ENODEV;
184         return 0;
185 }
186
187 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
188 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
189         __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
190 })
191
192 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
193                                     u64 bits, int limit, int delay,
194                                     const char *reg_name)
195 {
196         int err;
197
198         nw64(reg, bits);
199         err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
200         if (err)
201                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
202                            (unsigned long long)bits, reg_name,
203                            (unsigned long long)nr64(reg));
204         return err;
205 }
206
207 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
208 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
209         __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
210 })
211
212 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
213 {
214         u64 val = (u64) lp->timer;
215
216         if (on)
217                 val |= LDG_IMGMT_ARM;
218
219         nw64(LDG_IMGMT(lp->ldg_num), val);
220 }
221
222 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
223 {
224         unsigned long mask_reg, bits;
225         u64 val;
226
227         if (ldn < 0 || ldn > LDN_MAX)
228                 return -EINVAL;
229
230         if (ldn < 64) {
231                 mask_reg = LD_IM0(ldn);
232                 bits = LD_IM0_MASK;
233         } else {
234                 mask_reg = LD_IM1(ldn - 64);
235                 bits = LD_IM1_MASK;
236         }
237
238         val = nr64(mask_reg);
239         if (on)
240                 val &= ~bits;
241         else
242                 val |= bits;
243         nw64(mask_reg, val);
244
245         return 0;
246 }
247
248 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
249 {
250         struct niu_parent *parent = np->parent;
251         int i;
252
253         for (i = 0; i <= LDN_MAX; i++) {
254                 int err;
255
256                 if (parent->ldg_map[i] != lp->ldg_num)
257                         continue;
258
259                 err = niu_ldn_irq_enable(np, i, on);
260                 if (err)
261                         return err;
262         }
263         return 0;
264 }
265
266 static int niu_enable_interrupts(struct niu *np, int on)
267 {
268         int i;
269
270         for (i = 0; i < np->num_ldg; i++) {
271                 struct niu_ldg *lp = &np->ldg[i];
272                 int err;
273
274                 err = niu_enable_ldn_in_ldg(np, lp, on);
275                 if (err)
276                         return err;
277         }
278         for (i = 0; i < np->num_ldg; i++)
279                 niu_ldg_rearm(np, &np->ldg[i], on);
280
281         return 0;
282 }
283
284 static u32 phy_encode(u32 type, int port)
285 {
286         return (type << (port * 2));
287 }
288
289 static u32 phy_decode(u32 val, int port)
290 {
291         return (val >> (port * 2)) & PORT_TYPE_MASK;
292 }
293
294 static int mdio_wait(struct niu *np)
295 {
296         int limit = 1000;
297         u64 val;
298
299         while (--limit > 0) {
300                 val = nr64(MIF_FRAME_OUTPUT);
301                 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
302                         return val & MIF_FRAME_OUTPUT_DATA;
303
304                 udelay(10);
305         }
306
307         return -ENODEV;
308 }
309
310 static int mdio_read(struct niu *np, int port, int dev, int reg)
311 {
312         int err;
313
314         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
315         err = mdio_wait(np);
316         if (err < 0)
317                 return err;
318
319         nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
320         return mdio_wait(np);
321 }
322
323 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
324 {
325         int err;
326
327         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
328         err = mdio_wait(np);
329         if (err < 0)
330                 return err;
331
332         nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
333         err = mdio_wait(np);
334         if (err < 0)
335                 return err;
336
337         return 0;
338 }
339
340 static int mii_read(struct niu *np, int port, int reg)
341 {
342         nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
343         return mdio_wait(np);
344 }
345
346 static int mii_write(struct niu *np, int port, int reg, int data)
347 {
348         int err;
349
350         nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
351         err = mdio_wait(np);
352         if (err < 0)
353                 return err;
354
355         return 0;
356 }
357
358 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
359 {
360         int err;
361
362         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
363                          ESR2_TI_PLL_TX_CFG_L(channel),
364                          val & 0xffff);
365         if (!err)
366                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
367                                  ESR2_TI_PLL_TX_CFG_H(channel),
368                                  val >> 16);
369         return err;
370 }
371
372 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
373 {
374         int err;
375
376         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
377                          ESR2_TI_PLL_RX_CFG_L(channel),
378                          val & 0xffff);
379         if (!err)
380                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
381                                  ESR2_TI_PLL_RX_CFG_H(channel),
382                                  val >> 16);
383         return err;
384 }
385
386 /* Mode is always 10G fiber.  */
387 static int serdes_init_niu_10g_fiber(struct niu *np)
388 {
389         struct niu_link_config *lp = &np->link_config;
390         u32 tx_cfg, rx_cfg;
391         unsigned long i;
392
393         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
394         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
395                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
396                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
397
398         if (lp->loopback_mode == LOOPBACK_PHY) {
399                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
400
401                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
402                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
403
404                 tx_cfg |= PLL_TX_CFG_ENTEST;
405                 rx_cfg |= PLL_RX_CFG_ENTEST;
406         }
407
408         /* Initialize all 4 lanes of the SERDES.  */
409         for (i = 0; i < 4; i++) {
410                 int err = esr2_set_tx_cfg(np, i, tx_cfg);
411                 if (err)
412                         return err;
413         }
414
415         for (i = 0; i < 4; i++) {
416                 int err = esr2_set_rx_cfg(np, i, rx_cfg);
417                 if (err)
418                         return err;
419         }
420
421         return 0;
422 }
423
424 static int serdes_init_niu_1g_serdes(struct niu *np)
425 {
426         struct niu_link_config *lp = &np->link_config;
427         u16 pll_cfg, pll_sts;
428         int max_retry = 100;
429         u64 uninitialized_var(sig), mask, val;
430         u32 tx_cfg, rx_cfg;
431         unsigned long i;
432         int err;
433
434         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
435                   PLL_TX_CFG_RATE_HALF);
436         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
437                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
438                   PLL_RX_CFG_RATE_HALF);
439
440         if (np->port == 0)
441                 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
442
443         if (lp->loopback_mode == LOOPBACK_PHY) {
444                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
445
446                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
447                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
448
449                 tx_cfg |= PLL_TX_CFG_ENTEST;
450                 rx_cfg |= PLL_RX_CFG_ENTEST;
451         }
452
453         /* Initialize PLL for 1G */
454         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
455
456         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
457                          ESR2_TI_PLL_CFG_L, pll_cfg);
458         if (err) {
459                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
460                            np->port, __func__);
461                 return err;
462         }
463
464         pll_sts = PLL_CFG_ENPLL;
465
466         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
467                          ESR2_TI_PLL_STS_L, pll_sts);
468         if (err) {
469                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
470                            np->port, __func__);
471                 return err;
472         }
473
474         udelay(200);
475
476         /* Initialize all 4 lanes of the SERDES.  */
477         for (i = 0; i < 4; i++) {
478                 err = esr2_set_tx_cfg(np, i, tx_cfg);
479                 if (err)
480                         return err;
481         }
482
483         for (i = 0; i < 4; i++) {
484                 err = esr2_set_rx_cfg(np, i, rx_cfg);
485                 if (err)
486                         return err;
487         }
488
489         switch (np->port) {
490         case 0:
491                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
492                 mask = val;
493                 break;
494
495         case 1:
496                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
497                 mask = val;
498                 break;
499
500         default:
501                 return -EINVAL;
502         }
503
504         while (max_retry--) {
505                 sig = nr64(ESR_INT_SIGNALS);
506                 if ((sig & mask) == val)
507                         break;
508
509                 mdelay(500);
510         }
511
512         if ((sig & mask) != val) {
513                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
514                            np->port, (int)(sig & mask), (int)val);
515                 return -ENODEV;
516         }
517
518         return 0;
519 }
520
521 static int serdes_init_niu_10g_serdes(struct niu *np)
522 {
523         struct niu_link_config *lp = &np->link_config;
524         u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
525         int max_retry = 100;
526         u64 uninitialized_var(sig), mask, val;
527         unsigned long i;
528         int err;
529
530         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
531         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
532                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
533                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
534
535         if (lp->loopback_mode == LOOPBACK_PHY) {
536                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
537
538                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
539                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
540
541                 tx_cfg |= PLL_TX_CFG_ENTEST;
542                 rx_cfg |= PLL_RX_CFG_ENTEST;
543         }
544
545         /* Initialize PLL for 10G */
546         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
547
548         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
549                          ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
550         if (err) {
551                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
552                            np->port, __func__);
553                 return err;
554         }
555
556         pll_sts = PLL_CFG_ENPLL;
557
558         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
559                          ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
560         if (err) {
561                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
562                            np->port, __func__);
563                 return err;
564         }
565
566         udelay(200);
567
568         /* Initialize all 4 lanes of the SERDES.  */
569         for (i = 0; i < 4; i++) {
570                 err = esr2_set_tx_cfg(np, i, tx_cfg);
571                 if (err)
572                         return err;
573         }
574
575         for (i = 0; i < 4; i++) {
576                 err = esr2_set_rx_cfg(np, i, rx_cfg);
577                 if (err)
578                         return err;
579         }
580
581         /* check if serdes is ready */
582
583         switch (np->port) {
584         case 0:
585                 mask = ESR_INT_SIGNALS_P0_BITS;
586                 val = (ESR_INT_SRDY0_P0 |
587                        ESR_INT_DET0_P0 |
588                        ESR_INT_XSRDY_P0 |
589                        ESR_INT_XDP_P0_CH3 |
590                        ESR_INT_XDP_P0_CH2 |
591                        ESR_INT_XDP_P0_CH1 |
592                        ESR_INT_XDP_P0_CH0);
593                 break;
594
595         case 1:
596                 mask = ESR_INT_SIGNALS_P1_BITS;
597                 val = (ESR_INT_SRDY0_P1 |
598                        ESR_INT_DET0_P1 |
599                        ESR_INT_XSRDY_P1 |
600                        ESR_INT_XDP_P1_CH3 |
601                        ESR_INT_XDP_P1_CH2 |
602                        ESR_INT_XDP_P1_CH1 |
603                        ESR_INT_XDP_P1_CH0);
604                 break;
605
606         default:
607                 return -EINVAL;
608         }
609
610         while (max_retry--) {
611                 sig = nr64(ESR_INT_SIGNALS);
612                 if ((sig & mask) == val)
613                         break;
614
615                 mdelay(500);
616         }
617
618         if ((sig & mask) != val) {
619                 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
620                         np->port, (int)(sig & mask), (int)val);
621
622                 /* 10G failed, try initializing at 1G */
623                 err = serdes_init_niu_1g_serdes(np);
624                 if (!err) {
625                         np->flags &= ~NIU_FLAGS_10G;
626                         np->mac_xcvr = MAC_XCVR_PCS;
627                 }  else {
628                         netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
629                                    np->port);
630                         return -ENODEV;
631                 }
632         }
633         return 0;
634 }
635
636 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
637 {
638         int err;
639
640         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
641         if (err >= 0) {
642                 *val = (err & 0xffff);
643                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
644                                 ESR_RXTX_CTRL_H(chan));
645                 if (err >= 0)
646                         *val |= ((err & 0xffff) << 16);
647                 err = 0;
648         }
649         return err;
650 }
651
652 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
653 {
654         int err;
655
656         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
657                         ESR_GLUE_CTRL0_L(chan));
658         if (err >= 0) {
659                 *val = (err & 0xffff);
660                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
661                                 ESR_GLUE_CTRL0_H(chan));
662                 if (err >= 0) {
663                         *val |= ((err & 0xffff) << 16);
664                         err = 0;
665                 }
666         }
667         return err;
668 }
669
670 static int esr_read_reset(struct niu *np, u32 *val)
671 {
672         int err;
673
674         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
675                         ESR_RXTX_RESET_CTRL_L);
676         if (err >= 0) {
677                 *val = (err & 0xffff);
678                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
679                                 ESR_RXTX_RESET_CTRL_H);
680                 if (err >= 0) {
681                         *val |= ((err & 0xffff) << 16);
682                         err = 0;
683                 }
684         }
685         return err;
686 }
687
688 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
689 {
690         int err;
691
692         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
693                          ESR_RXTX_CTRL_L(chan), val & 0xffff);
694         if (!err)
695                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
696                                  ESR_RXTX_CTRL_H(chan), (val >> 16));
697         return err;
698 }
699
700 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
701 {
702         int err;
703
704         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
705                         ESR_GLUE_CTRL0_L(chan), val & 0xffff);
706         if (!err)
707                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
708                                  ESR_GLUE_CTRL0_H(chan), (val >> 16));
709         return err;
710 }
711
712 static int esr_reset(struct niu *np)
713 {
714         u32 uninitialized_var(reset);
715         int err;
716
717         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
718                          ESR_RXTX_RESET_CTRL_L, 0x0000);
719         if (err)
720                 return err;
721         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
722                          ESR_RXTX_RESET_CTRL_H, 0xffff);
723         if (err)
724                 return err;
725         udelay(200);
726
727         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
728                          ESR_RXTX_RESET_CTRL_L, 0xffff);
729         if (err)
730                 return err;
731         udelay(200);
732
733         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
734                          ESR_RXTX_RESET_CTRL_H, 0x0000);
735         if (err)
736                 return err;
737         udelay(200);
738
739         err = esr_read_reset(np, &reset);
740         if (err)
741                 return err;
742         if (reset != 0) {
743                 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
744                            np->port, reset);
745                 return -ENODEV;
746         }
747
748         return 0;
749 }
750
751 static int serdes_init_10g(struct niu *np)
752 {
753         struct niu_link_config *lp = &np->link_config;
754         unsigned long ctrl_reg, test_cfg_reg, i;
755         u64 ctrl_val, test_cfg_val, sig, mask, val;
756         int err;
757
758         switch (np->port) {
759         case 0:
760                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
761                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
762                 break;
763         case 1:
764                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
765                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
766                 break;
767
768         default:
769                 return -EINVAL;
770         }
771         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
772                     ENET_SERDES_CTRL_SDET_1 |
773                     ENET_SERDES_CTRL_SDET_2 |
774                     ENET_SERDES_CTRL_SDET_3 |
775                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
776                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
777                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
778                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
779                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
780                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
781                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
782                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
783         test_cfg_val = 0;
784
785         if (lp->loopback_mode == LOOPBACK_PHY) {
786                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
787                                   ENET_SERDES_TEST_MD_0_SHIFT) |
788                                  (ENET_TEST_MD_PAD_LOOPBACK <<
789                                   ENET_SERDES_TEST_MD_1_SHIFT) |
790                                  (ENET_TEST_MD_PAD_LOOPBACK <<
791                                   ENET_SERDES_TEST_MD_2_SHIFT) |
792                                  (ENET_TEST_MD_PAD_LOOPBACK <<
793                                   ENET_SERDES_TEST_MD_3_SHIFT));
794         }
795
796         nw64(ctrl_reg, ctrl_val);
797         nw64(test_cfg_reg, test_cfg_val);
798
799         /* Initialize all 4 lanes of the SERDES.  */
800         for (i = 0; i < 4; i++) {
801                 u32 rxtx_ctrl, glue0;
802
803                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
804                 if (err)
805                         return err;
806                 err = esr_read_glue0(np, i, &glue0);
807                 if (err)
808                         return err;
809
810                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
811                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
812                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
813
814                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
815                            ESR_GLUE_CTRL0_THCNT |
816                            ESR_GLUE_CTRL0_BLTIME);
817                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
818                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
819                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
820                           (BLTIME_300_CYCLES <<
821                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
822
823                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
824                 if (err)
825                         return err;
826                 err = esr_write_glue0(np, i, glue0);
827                 if (err)
828                         return err;
829         }
830
831         err = esr_reset(np);
832         if (err)
833                 return err;
834
835         sig = nr64(ESR_INT_SIGNALS);
836         switch (np->port) {
837         case 0:
838                 mask = ESR_INT_SIGNALS_P0_BITS;
839                 val = (ESR_INT_SRDY0_P0 |
840                        ESR_INT_DET0_P0 |
841                        ESR_INT_XSRDY_P0 |
842                        ESR_INT_XDP_P0_CH3 |
843                        ESR_INT_XDP_P0_CH2 |
844                        ESR_INT_XDP_P0_CH1 |
845                        ESR_INT_XDP_P0_CH0);
846                 break;
847
848         case 1:
849                 mask = ESR_INT_SIGNALS_P1_BITS;
850                 val = (ESR_INT_SRDY0_P1 |
851                        ESR_INT_DET0_P1 |
852                        ESR_INT_XSRDY_P1 |
853                        ESR_INT_XDP_P1_CH3 |
854                        ESR_INT_XDP_P1_CH2 |
855                        ESR_INT_XDP_P1_CH1 |
856                        ESR_INT_XDP_P1_CH0);
857                 break;
858
859         default:
860                 return -EINVAL;
861         }
862
863         if ((sig & mask) != val) {
864                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
865                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
866                         return 0;
867                 }
868                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
869                            np->port, (int)(sig & mask), (int)val);
870                 return -ENODEV;
871         }
872         if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
873                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
874         return 0;
875 }
876
877 static int serdes_init_1g(struct niu *np)
878 {
879         u64 val;
880
881         val = nr64(ENET_SERDES_1_PLL_CFG);
882         val &= ~ENET_SERDES_PLL_FBDIV2;
883         switch (np->port) {
884         case 0:
885                 val |= ENET_SERDES_PLL_HRATE0;
886                 break;
887         case 1:
888                 val |= ENET_SERDES_PLL_HRATE1;
889                 break;
890         case 2:
891                 val |= ENET_SERDES_PLL_HRATE2;
892                 break;
893         case 3:
894                 val |= ENET_SERDES_PLL_HRATE3;
895                 break;
896         default:
897                 return -EINVAL;
898         }
899         nw64(ENET_SERDES_1_PLL_CFG, val);
900
901         return 0;
902 }
903
904 static int serdes_init_1g_serdes(struct niu *np)
905 {
906         struct niu_link_config *lp = &np->link_config;
907         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
908         u64 ctrl_val, test_cfg_val, sig, mask, val;
909         int err;
910         u64 reset_val, val_rd;
911
912         val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
913                 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
914                 ENET_SERDES_PLL_FBDIV0;
915         switch (np->port) {
916         case 0:
917                 reset_val =  ENET_SERDES_RESET_0;
918                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
919                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
920                 pll_cfg = ENET_SERDES_0_PLL_CFG;
921                 break;
922         case 1:
923                 reset_val =  ENET_SERDES_RESET_1;
924                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
925                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
926                 pll_cfg = ENET_SERDES_1_PLL_CFG;
927                 break;
928
929         default:
930                 return -EINVAL;
931         }
932         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
933                     ENET_SERDES_CTRL_SDET_1 |
934                     ENET_SERDES_CTRL_SDET_2 |
935                     ENET_SERDES_CTRL_SDET_3 |
936                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
937                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
938                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
939                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
940                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
941                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
942                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
943                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
944         test_cfg_val = 0;
945
946         if (lp->loopback_mode == LOOPBACK_PHY) {
947                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
948                                   ENET_SERDES_TEST_MD_0_SHIFT) |
949                                  (ENET_TEST_MD_PAD_LOOPBACK <<
950                                   ENET_SERDES_TEST_MD_1_SHIFT) |
951                                  (ENET_TEST_MD_PAD_LOOPBACK <<
952                                   ENET_SERDES_TEST_MD_2_SHIFT) |
953                                  (ENET_TEST_MD_PAD_LOOPBACK <<
954                                   ENET_SERDES_TEST_MD_3_SHIFT));
955         }
956
957         nw64(ENET_SERDES_RESET, reset_val);
958         mdelay(20);
959         val_rd = nr64(ENET_SERDES_RESET);
960         val_rd &= ~reset_val;
961         nw64(pll_cfg, val);
962         nw64(ctrl_reg, ctrl_val);
963         nw64(test_cfg_reg, test_cfg_val);
964         nw64(ENET_SERDES_RESET, val_rd);
965         mdelay(2000);
966
967         /* Initialize all 4 lanes of the SERDES.  */
968         for (i = 0; i < 4; i++) {
969                 u32 rxtx_ctrl, glue0;
970
971                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
972                 if (err)
973                         return err;
974                 err = esr_read_glue0(np, i, &glue0);
975                 if (err)
976                         return err;
977
978                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
979                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
980                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
981
982                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
983                            ESR_GLUE_CTRL0_THCNT |
984                            ESR_GLUE_CTRL0_BLTIME);
985                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
986                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
987                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
988                           (BLTIME_300_CYCLES <<
989                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
990
991                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
992                 if (err)
993                         return err;
994                 err = esr_write_glue0(np, i, glue0);
995                 if (err)
996                         return err;
997         }
998
999
1000         sig = nr64(ESR_INT_SIGNALS);
1001         switch (np->port) {
1002         case 0:
1003                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1004                 mask = val;
1005                 break;
1006
1007         case 1:
1008                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1009                 mask = val;
1010                 break;
1011
1012         default:
1013                 return -EINVAL;
1014         }
1015
1016         if ((sig & mask) != val) {
1017                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1018                            np->port, (int)(sig & mask), (int)val);
1019                 return -ENODEV;
1020         }
1021
1022         return 0;
1023 }
1024
1025 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1026 {
1027         struct niu_link_config *lp = &np->link_config;
1028         int link_up;
1029         u64 val;
1030         u16 current_speed;
1031         unsigned long flags;
1032         u8 current_duplex;
1033
1034         link_up = 0;
1035         current_speed = SPEED_INVALID;
1036         current_duplex = DUPLEX_INVALID;
1037
1038         spin_lock_irqsave(&np->lock, flags);
1039
1040         val = nr64_pcs(PCS_MII_STAT);
1041
1042         if (val & PCS_MII_STAT_LINK_STATUS) {
1043                 link_up = 1;
1044                 current_speed = SPEED_1000;
1045                 current_duplex = DUPLEX_FULL;
1046         }
1047
1048         lp->active_speed = current_speed;
1049         lp->active_duplex = current_duplex;
1050         spin_unlock_irqrestore(&np->lock, flags);
1051
1052         *link_up_p = link_up;
1053         return 0;
1054 }
1055
1056 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1057 {
1058         unsigned long flags;
1059         struct niu_link_config *lp = &np->link_config;
1060         int link_up = 0;
1061         int link_ok = 1;
1062         u64 val, val2;
1063         u16 current_speed;
1064         u8 current_duplex;
1065
1066         if (!(np->flags & NIU_FLAGS_10G))
1067                 return link_status_1g_serdes(np, link_up_p);
1068
1069         current_speed = SPEED_INVALID;
1070         current_duplex = DUPLEX_INVALID;
1071         spin_lock_irqsave(&np->lock, flags);
1072
1073         val = nr64_xpcs(XPCS_STATUS(0));
1074         val2 = nr64_mac(XMAC_INTER2);
1075         if (val2 & 0x01000000)
1076                 link_ok = 0;
1077
1078         if ((val & 0x1000ULL) && link_ok) {
1079                 link_up = 1;
1080                 current_speed = SPEED_10000;
1081                 current_duplex = DUPLEX_FULL;
1082         }
1083         lp->active_speed = current_speed;
1084         lp->active_duplex = current_duplex;
1085         spin_unlock_irqrestore(&np->lock, flags);
1086         *link_up_p = link_up;
1087         return 0;
1088 }
1089
1090 static int link_status_mii(struct niu *np, int *link_up_p)
1091 {
1092         struct niu_link_config *lp = &np->link_config;
1093         int err;
1094         int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1095         int supported, advertising, active_speed, active_duplex;
1096
1097         err = mii_read(np, np->phy_addr, MII_BMCR);
1098         if (unlikely(err < 0))
1099                 return err;
1100         bmcr = err;
1101
1102         err = mii_read(np, np->phy_addr, MII_BMSR);
1103         if (unlikely(err < 0))
1104                 return err;
1105         bmsr = err;
1106
1107         err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1108         if (unlikely(err < 0))
1109                 return err;
1110         advert = err;
1111
1112         err = mii_read(np, np->phy_addr, MII_LPA);
1113         if (unlikely(err < 0))
1114                 return err;
1115         lpa = err;
1116
1117         if (likely(bmsr & BMSR_ESTATEN)) {
1118                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1119                 if (unlikely(err < 0))
1120                         return err;
1121                 estatus = err;
1122
1123                 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1124                 if (unlikely(err < 0))
1125                         return err;
1126                 ctrl1000 = err;
1127
1128                 err = mii_read(np, np->phy_addr, MII_STAT1000);
1129                 if (unlikely(err < 0))
1130                         return err;
1131                 stat1000 = err;
1132         } else
1133                 estatus = ctrl1000 = stat1000 = 0;
1134
1135         supported = 0;
1136         if (bmsr & BMSR_ANEGCAPABLE)
1137                 supported |= SUPPORTED_Autoneg;
1138         if (bmsr & BMSR_10HALF)
1139                 supported |= SUPPORTED_10baseT_Half;
1140         if (bmsr & BMSR_10FULL)
1141                 supported |= SUPPORTED_10baseT_Full;
1142         if (bmsr & BMSR_100HALF)
1143                 supported |= SUPPORTED_100baseT_Half;
1144         if (bmsr & BMSR_100FULL)
1145                 supported |= SUPPORTED_100baseT_Full;
1146         if (estatus & ESTATUS_1000_THALF)
1147                 supported |= SUPPORTED_1000baseT_Half;
1148         if (estatus & ESTATUS_1000_TFULL)
1149                 supported |= SUPPORTED_1000baseT_Full;
1150         lp->supported = supported;
1151
1152         advertising = 0;
1153         if (advert & ADVERTISE_10HALF)
1154                 advertising |= ADVERTISED_10baseT_Half;
1155         if (advert & ADVERTISE_10FULL)
1156                 advertising |= ADVERTISED_10baseT_Full;
1157         if (advert & ADVERTISE_100HALF)
1158                 advertising |= ADVERTISED_100baseT_Half;
1159         if (advert & ADVERTISE_100FULL)
1160                 advertising |= ADVERTISED_100baseT_Full;
1161         if (ctrl1000 & ADVERTISE_1000HALF)
1162                 advertising |= ADVERTISED_1000baseT_Half;
1163         if (ctrl1000 & ADVERTISE_1000FULL)
1164                 advertising |= ADVERTISED_1000baseT_Full;
1165
1166         if (bmcr & BMCR_ANENABLE) {
1167                 int neg, neg1000;
1168
1169                 lp->active_autoneg = 1;
1170                 advertising |= ADVERTISED_Autoneg;
1171
1172                 neg = advert & lpa;
1173                 neg1000 = (ctrl1000 << 2) & stat1000;
1174
1175                 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1176                         active_speed = SPEED_1000;
1177                 else if (neg & LPA_100)
1178                         active_speed = SPEED_100;
1179                 else if (neg & (LPA_10HALF | LPA_10FULL))
1180                         active_speed = SPEED_10;
1181                 else
1182                         active_speed = SPEED_INVALID;
1183
1184                 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1185                         active_duplex = DUPLEX_FULL;
1186                 else if (active_speed != SPEED_INVALID)
1187                         active_duplex = DUPLEX_HALF;
1188                 else
1189                         active_duplex = DUPLEX_INVALID;
1190         } else {
1191                 lp->active_autoneg = 0;
1192
1193                 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1194                         active_speed = SPEED_1000;
1195                 else if (bmcr & BMCR_SPEED100)
1196                         active_speed = SPEED_100;
1197                 else
1198                         active_speed = SPEED_10;
1199
1200                 if (bmcr & BMCR_FULLDPLX)
1201                         active_duplex = DUPLEX_FULL;
1202                 else
1203                         active_duplex = DUPLEX_HALF;
1204         }
1205
1206         lp->active_advertising = advertising;
1207         lp->active_speed = active_speed;
1208         lp->active_duplex = active_duplex;
1209         *link_up_p = !!(bmsr & BMSR_LSTATUS);
1210
1211         return 0;
1212 }
1213
1214 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1215 {
1216         struct niu_link_config *lp = &np->link_config;
1217         u16 current_speed, bmsr;
1218         unsigned long flags;
1219         u8 current_duplex;
1220         int err, link_up;
1221
1222         link_up = 0;
1223         current_speed = SPEED_INVALID;
1224         current_duplex = DUPLEX_INVALID;
1225
1226         spin_lock_irqsave(&np->lock, flags);
1227
1228         err = -EINVAL;
1229
1230         err = mii_read(np, np->phy_addr, MII_BMSR);
1231         if (err < 0)
1232                 goto out;
1233
1234         bmsr = err;
1235         if (bmsr & BMSR_LSTATUS) {
1236                 u16 adv, lpa, common, estat;
1237
1238                 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1239                 if (err < 0)
1240                         goto out;
1241                 adv = err;
1242
1243                 err = mii_read(np, np->phy_addr, MII_LPA);
1244                 if (err < 0)
1245                         goto out;
1246                 lpa = err;
1247
1248                 common = adv & lpa;
1249
1250                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1251                 if (err < 0)
1252                         goto out;
1253                 estat = err;
1254                 link_up = 1;
1255                 current_speed = SPEED_1000;
1256                 current_duplex = DUPLEX_FULL;
1257
1258         }
1259         lp->active_speed = current_speed;
1260         lp->active_duplex = current_duplex;
1261         err = 0;
1262
1263 out:
1264         spin_unlock_irqrestore(&np->lock, flags);
1265
1266         *link_up_p = link_up;
1267         return err;
1268 }
1269
1270 static int link_status_1g(struct niu *np, int *link_up_p)
1271 {
1272         struct niu_link_config *lp = &np->link_config;
1273         unsigned long flags;
1274         int err;
1275
1276         spin_lock_irqsave(&np->lock, flags);
1277
1278         err = link_status_mii(np, link_up_p);
1279         lp->supported |= SUPPORTED_TP;
1280         lp->active_advertising |= ADVERTISED_TP;
1281
1282         spin_unlock_irqrestore(&np->lock, flags);
1283         return err;
1284 }
1285
1286 static int bcm8704_reset(struct niu *np)
1287 {
1288         int err, limit;
1289
1290         err = mdio_read(np, np->phy_addr,
1291                         BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1292         if (err < 0 || err == 0xffff)
1293                 return err;
1294         err |= BMCR_RESET;
1295         err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1296                          MII_BMCR, err);
1297         if (err)
1298                 return err;
1299
1300         limit = 1000;
1301         while (--limit >= 0) {
1302                 err = mdio_read(np, np->phy_addr,
1303                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1304                 if (err < 0)
1305                         return err;
1306                 if (!(err & BMCR_RESET))
1307                         break;
1308         }
1309         if (limit < 0) {
1310                 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1311                            np->port, (err & 0xffff));
1312                 return -ENODEV;
1313         }
1314         return 0;
1315 }
1316
1317 /* When written, certain PHY registers need to be read back twice
1318  * in order for the bits to settle properly.
1319  */
1320 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1321 {
1322         int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1323         if (err < 0)
1324                 return err;
1325         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1326         if (err < 0)
1327                 return err;
1328         return 0;
1329 }
1330
1331 static int bcm8706_init_user_dev3(struct niu *np)
1332 {
1333         int err;
1334
1335
1336         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1337                         BCM8704_USER_OPT_DIGITAL_CTRL);
1338         if (err < 0)
1339                 return err;
1340         err &= ~USER_ODIG_CTRL_GPIOS;
1341         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1342         err |=  USER_ODIG_CTRL_RESV2;
1343         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1344                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1345         if (err)
1346                 return err;
1347
1348         mdelay(1000);
1349
1350         return 0;
1351 }
1352
1353 static int bcm8704_init_user_dev3(struct niu *np)
1354 {
1355         int err;
1356
1357         err = mdio_write(np, np->phy_addr,
1358                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1359                          (USER_CONTROL_OPTXRST_LVL |
1360                           USER_CONTROL_OPBIASFLT_LVL |
1361                           USER_CONTROL_OBTMPFLT_LVL |
1362                           USER_CONTROL_OPPRFLT_LVL |
1363                           USER_CONTROL_OPTXFLT_LVL |
1364                           USER_CONTROL_OPRXLOS_LVL |
1365                           USER_CONTROL_OPRXFLT_LVL |
1366                           USER_CONTROL_OPTXON_LVL |
1367                           (0x3f << USER_CONTROL_RES1_SHIFT)));
1368         if (err)
1369                 return err;
1370
1371         err = mdio_write(np, np->phy_addr,
1372                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1373                          (USER_PMD_TX_CTL_XFP_CLKEN |
1374                           (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1375                           (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1376                           USER_PMD_TX_CTL_TSCK_LPWREN));
1377         if (err)
1378                 return err;
1379
1380         err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1381         if (err)
1382                 return err;
1383         err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1384         if (err)
1385                 return err;
1386
1387         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1388                         BCM8704_USER_OPT_DIGITAL_CTRL);
1389         if (err < 0)
1390                 return err;
1391         err &= ~USER_ODIG_CTRL_GPIOS;
1392         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1393         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1394                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1395         if (err)
1396                 return err;
1397
1398         mdelay(1000);
1399
1400         return 0;
1401 }
1402
1403 static int mrvl88x2011_act_led(struct niu *np, int val)
1404 {
1405         int     err;
1406
1407         err  = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1408                 MRVL88X2011_LED_8_TO_11_CTL);
1409         if (err < 0)
1410                 return err;
1411
1412         err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1413         err |=  MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1414
1415         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1416                           MRVL88X2011_LED_8_TO_11_CTL, err);
1417 }
1418
1419 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1420 {
1421         int     err;
1422
1423         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1424                         MRVL88X2011_LED_BLINK_CTL);
1425         if (err >= 0) {
1426                 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1427                 err |= (rate << 4);
1428
1429                 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1430                                  MRVL88X2011_LED_BLINK_CTL, err);
1431         }
1432
1433         return err;
1434 }
1435
1436 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1437 {
1438         int     err;
1439
1440         /* Set LED functions */
1441         err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1442         if (err)
1443                 return err;
1444
1445         /* led activity */
1446         err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1447         if (err)
1448                 return err;
1449
1450         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1451                         MRVL88X2011_GENERAL_CTL);
1452         if (err < 0)
1453                 return err;
1454
1455         err |= MRVL88X2011_ENA_XFPREFCLK;
1456
1457         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1458                          MRVL88X2011_GENERAL_CTL, err);
1459         if (err < 0)
1460                 return err;
1461
1462         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1463                         MRVL88X2011_PMA_PMD_CTL_1);
1464         if (err < 0)
1465                 return err;
1466
1467         if (np->link_config.loopback_mode == LOOPBACK_MAC)
1468                 err |= MRVL88X2011_LOOPBACK;
1469         else
1470                 err &= ~MRVL88X2011_LOOPBACK;
1471
1472         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1473                          MRVL88X2011_PMA_PMD_CTL_1, err);
1474         if (err < 0)
1475                 return err;
1476
1477         /* Enable PMD  */
1478         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1479                           MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1480 }
1481
1482
1483 static int xcvr_diag_bcm870x(struct niu *np)
1484 {
1485         u16 analog_stat0, tx_alarm_status;
1486         int err = 0;
1487
1488 #if 1
1489         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1490                         MII_STAT1000);
1491         if (err < 0)
1492                 return err;
1493         pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
1494
1495         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1496         if (err < 0)
1497                 return err;
1498         pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
1499
1500         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1501                         MII_NWAYTEST);
1502         if (err < 0)
1503                 return err;
1504         pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
1505 #endif
1506
1507         /* XXX dig this out it might not be so useful XXX */
1508         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1509                         BCM8704_USER_ANALOG_STATUS0);
1510         if (err < 0)
1511                 return err;
1512         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1513                         BCM8704_USER_ANALOG_STATUS0);
1514         if (err < 0)
1515                 return err;
1516         analog_stat0 = err;
1517
1518         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1519                         BCM8704_USER_TX_ALARM_STATUS);
1520         if (err < 0)
1521                 return err;
1522         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1523                         BCM8704_USER_TX_ALARM_STATUS);
1524         if (err < 0)
1525                 return err;
1526         tx_alarm_status = err;
1527
1528         if (analog_stat0 != 0x03fc) {
1529                 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1530                         pr_info("Port %u cable not connected or bad cable\n",
1531                                 np->port);
1532                 } else if (analog_stat0 == 0x639c) {
1533                         pr_info("Port %u optical module is bad or missing\n",
1534                                 np->port);
1535                 }
1536         }
1537
1538         return 0;
1539 }
1540
1541 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1542 {
1543         struct niu_link_config *lp = &np->link_config;
1544         int err;
1545
1546         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1547                         MII_BMCR);
1548         if (err < 0)
1549                 return err;
1550
1551         err &= ~BMCR_LOOPBACK;
1552
1553         if (lp->loopback_mode == LOOPBACK_MAC)
1554                 err |= BMCR_LOOPBACK;
1555
1556         err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1557                          MII_BMCR, err);
1558         if (err)
1559                 return err;
1560
1561         return 0;
1562 }
1563
1564 static int xcvr_init_10g_bcm8706(struct niu *np)
1565 {
1566         int err = 0;
1567         u64 val;
1568
1569         if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1570             (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1571                         return err;
1572
1573         val = nr64_mac(XMAC_CONFIG);
1574         val &= ~XMAC_CONFIG_LED_POLARITY;
1575         val |= XMAC_CONFIG_FORCE_LED_ON;
1576         nw64_mac(XMAC_CONFIG, val);
1577
1578         val = nr64(MIF_CONFIG);
1579         val |= MIF_CONFIG_INDIRECT_MODE;
1580         nw64(MIF_CONFIG, val);
1581
1582         err = bcm8704_reset(np);
1583         if (err)
1584                 return err;
1585
1586         err = xcvr_10g_set_lb_bcm870x(np);
1587         if (err)
1588                 return err;
1589
1590         err = bcm8706_init_user_dev3(np);
1591         if (err)
1592                 return err;
1593
1594         err = xcvr_diag_bcm870x(np);
1595         if (err)
1596                 return err;
1597
1598         return 0;
1599 }
1600
1601 static int xcvr_init_10g_bcm8704(struct niu *np)
1602 {
1603         int err;
1604
1605         err = bcm8704_reset(np);
1606         if (err)
1607                 return err;
1608
1609         err = bcm8704_init_user_dev3(np);
1610         if (err)
1611                 return err;
1612
1613         err = xcvr_10g_set_lb_bcm870x(np);
1614         if (err)
1615                 return err;
1616
1617         err =  xcvr_diag_bcm870x(np);
1618         if (err)
1619                 return err;
1620
1621         return 0;
1622 }
1623
1624 static int xcvr_init_10g(struct niu *np)
1625 {
1626         int phy_id, err;
1627         u64 val;
1628
1629         val = nr64_mac(XMAC_CONFIG);
1630         val &= ~XMAC_CONFIG_LED_POLARITY;
1631         val |= XMAC_CONFIG_FORCE_LED_ON;
1632         nw64_mac(XMAC_CONFIG, val);
1633
1634         /* XXX shared resource, lock parent XXX */
1635         val = nr64(MIF_CONFIG);
1636         val |= MIF_CONFIG_INDIRECT_MODE;
1637         nw64(MIF_CONFIG, val);
1638
1639         phy_id = phy_decode(np->parent->port_phy, np->port);
1640         phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1641
1642         /* handle different phy types */
1643         switch (phy_id & NIU_PHY_ID_MASK) {
1644         case NIU_PHY_ID_MRVL88X2011:
1645                 err = xcvr_init_10g_mrvl88x2011(np);
1646                 break;
1647
1648         default: /* bcom 8704 */
1649                 err = xcvr_init_10g_bcm8704(np);
1650                 break;
1651         }
1652
1653         return 0;
1654 }
1655
1656 static int mii_reset(struct niu *np)
1657 {
1658         int limit, err;
1659
1660         err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1661         if (err)
1662                 return err;
1663
1664         limit = 1000;
1665         while (--limit >= 0) {
1666                 udelay(500);
1667                 err = mii_read(np, np->phy_addr, MII_BMCR);
1668                 if (err < 0)
1669                         return err;
1670                 if (!(err & BMCR_RESET))
1671                         break;
1672         }
1673         if (limit < 0) {
1674                 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1675                            np->port, err);
1676                 return -ENODEV;
1677         }
1678
1679         return 0;
1680 }
1681
1682 static int xcvr_init_1g_rgmii(struct niu *np)
1683 {
1684         int err;
1685         u64 val;
1686         u16 bmcr, bmsr, estat;
1687
1688         val = nr64(MIF_CONFIG);
1689         val &= ~MIF_CONFIG_INDIRECT_MODE;
1690         nw64(MIF_CONFIG, val);
1691
1692         err = mii_reset(np);
1693         if (err)
1694                 return err;
1695
1696         err = mii_read(np, np->phy_addr, MII_BMSR);
1697         if (err < 0)
1698                 return err;
1699         bmsr = err;
1700
1701         estat = 0;
1702         if (bmsr & BMSR_ESTATEN) {
1703                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1704                 if (err < 0)
1705                         return err;
1706                 estat = err;
1707         }
1708
1709         bmcr = 0;
1710         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1711         if (err)
1712                 return err;
1713
1714         if (bmsr & BMSR_ESTATEN) {
1715                 u16 ctrl1000 = 0;
1716
1717                 if (estat & ESTATUS_1000_TFULL)
1718                         ctrl1000 |= ADVERTISE_1000FULL;
1719                 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1720                 if (err)
1721                         return err;
1722         }
1723
1724         bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1725
1726         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1727         if (err)
1728                 return err;
1729
1730         err = mii_read(np, np->phy_addr, MII_BMCR);
1731         if (err < 0)
1732                 return err;
1733         bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1734
1735         err = mii_read(np, np->phy_addr, MII_BMSR);
1736         if (err < 0)
1737                 return err;
1738
1739         return 0;
1740 }
1741
1742 static int mii_init_common(struct niu *np)
1743 {
1744         struct niu_link_config *lp = &np->link_config;
1745         u16 bmcr, bmsr, adv, estat;
1746         int err;
1747
1748         err = mii_reset(np);
1749         if (err)
1750                 return err;
1751
1752         err = mii_read(np, np->phy_addr, MII_BMSR);
1753         if (err < 0)
1754                 return err;
1755         bmsr = err;
1756
1757         estat = 0;
1758         if (bmsr & BMSR_ESTATEN) {
1759                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1760                 if (err < 0)
1761                         return err;
1762                 estat = err;
1763         }
1764
1765         bmcr = 0;
1766         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1767         if (err)
1768                 return err;
1769
1770         if (lp->loopback_mode == LOOPBACK_MAC) {
1771                 bmcr |= BMCR_LOOPBACK;
1772                 if (lp->active_speed == SPEED_1000)
1773                         bmcr |= BMCR_SPEED1000;
1774                 if (lp->active_duplex == DUPLEX_FULL)
1775                         bmcr |= BMCR_FULLDPLX;
1776         }
1777
1778         if (lp->loopback_mode == LOOPBACK_PHY) {
1779                 u16 aux;
1780
1781                 aux = (BCM5464R_AUX_CTL_EXT_LB |
1782                        BCM5464R_AUX_CTL_WRITE_1);
1783                 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1784                 if (err)
1785                         return err;
1786         }
1787
1788         if (lp->autoneg) {
1789                 u16 ctrl1000;
1790
1791                 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1792                 if ((bmsr & BMSR_10HALF) &&
1793                         (lp->advertising & ADVERTISED_10baseT_Half))
1794                         adv |= ADVERTISE_10HALF;
1795                 if ((bmsr & BMSR_10FULL) &&
1796                         (lp->advertising & ADVERTISED_10baseT_Full))
1797                         adv |= ADVERTISE_10FULL;
1798                 if ((bmsr & BMSR_100HALF) &&
1799                         (lp->advertising & ADVERTISED_100baseT_Half))
1800                         adv |= ADVERTISE_100HALF;
1801                 if ((bmsr & BMSR_100FULL) &&
1802                         (lp->advertising & ADVERTISED_100baseT_Full))
1803                         adv |= ADVERTISE_100FULL;
1804                 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1805                 if (err)
1806                         return err;
1807
1808                 if (likely(bmsr & BMSR_ESTATEN)) {
1809                         ctrl1000 = 0;
1810                         if ((estat & ESTATUS_1000_THALF) &&
1811                                 (lp->advertising & ADVERTISED_1000baseT_Half))
1812                                 ctrl1000 |= ADVERTISE_1000HALF;
1813                         if ((estat & ESTATUS_1000_TFULL) &&
1814                                 (lp->advertising & ADVERTISED_1000baseT_Full))
1815                                 ctrl1000 |= ADVERTISE_1000FULL;
1816                         err = mii_write(np, np->phy_addr,
1817                                         MII_CTRL1000, ctrl1000);
1818                         if (err)
1819                                 return err;
1820                 }
1821
1822                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1823         } else {
1824                 /* !lp->autoneg */
1825                 int fulldpx;
1826
1827                 if (lp->duplex == DUPLEX_FULL) {
1828                         bmcr |= BMCR_FULLDPLX;
1829                         fulldpx = 1;
1830                 } else if (lp->duplex == DUPLEX_HALF)
1831                         fulldpx = 0;
1832                 else
1833                         return -EINVAL;
1834
1835                 if (lp->speed == SPEED_1000) {
1836                         /* if X-full requested while not supported, or
1837                            X-half requested while not supported... */
1838                         if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1839                                 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1840                                 return -EINVAL;
1841                         bmcr |= BMCR_SPEED1000;
1842                 } else if (lp->speed == SPEED_100) {
1843                         if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1844                                 (!fulldpx && !(bmsr & BMSR_100HALF)))
1845                                 return -EINVAL;
1846                         bmcr |= BMCR_SPEED100;
1847                 } else if (lp->speed == SPEED_10) {
1848                         if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1849                                 (!fulldpx && !(bmsr & BMSR_10HALF)))
1850                                 return -EINVAL;
1851                 } else
1852                         return -EINVAL;
1853         }
1854
1855         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1856         if (err)
1857                 return err;
1858
1859 #if 0
1860         err = mii_read(np, np->phy_addr, MII_BMCR);
1861         if (err < 0)
1862                 return err;
1863         bmcr = err;
1864
1865         err = mii_read(np, np->phy_addr, MII_BMSR);
1866         if (err < 0)
1867                 return err;
1868         bmsr = err;
1869
1870         pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1871                 np->port, bmcr, bmsr);
1872 #endif
1873
1874         return 0;
1875 }
1876
1877 static int xcvr_init_1g(struct niu *np)
1878 {
1879         u64 val;
1880
1881         /* XXX shared resource, lock parent XXX */
1882         val = nr64(MIF_CONFIG);
1883         val &= ~MIF_CONFIG_INDIRECT_MODE;
1884         nw64(MIF_CONFIG, val);
1885
1886         return mii_init_common(np);
1887 }
1888
1889 static int niu_xcvr_init(struct niu *np)
1890 {
1891         const struct niu_phy_ops *ops = np->phy_ops;
1892         int err;
1893
1894         err = 0;
1895         if (ops->xcvr_init)
1896                 err = ops->xcvr_init(np);
1897
1898         return err;
1899 }
1900
1901 static int niu_serdes_init(struct niu *np)
1902 {
1903         const struct niu_phy_ops *ops = np->phy_ops;
1904         int err;
1905
1906         err = 0;
1907         if (ops->serdes_init)
1908                 err = ops->serdes_init(np);
1909
1910         return err;
1911 }
1912
1913 static void niu_init_xif(struct niu *);
1914 static void niu_handle_led(struct niu *, int status);
1915
1916 static int niu_link_status_common(struct niu *np, int link_up)
1917 {
1918         struct niu_link_config *lp = &np->link_config;
1919         struct net_device *dev = np->dev;
1920         unsigned long flags;
1921
1922         if (!netif_carrier_ok(dev) && link_up) {
1923                 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1924                            lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1925                            lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1926                            lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1927                            "10Mbit/sec",
1928                            lp->active_duplex == DUPLEX_FULL ? "full" : "half");
1929
1930                 spin_lock_irqsave(&np->lock, flags);
1931                 niu_init_xif(np);
1932                 niu_handle_led(np, 1);
1933                 spin_unlock_irqrestore(&np->lock, flags);
1934
1935                 netif_carrier_on(dev);
1936         } else if (netif_carrier_ok(dev) && !link_up) {
1937                 netif_warn(np, link, dev, "Link is down\n");
1938                 spin_lock_irqsave(&np->lock, flags);
1939                 niu_handle_led(np, 0);
1940                 spin_unlock_irqrestore(&np->lock, flags);
1941                 netif_carrier_off(dev);
1942         }
1943
1944         return 0;
1945 }
1946
1947 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1948 {
1949         int err, link_up, pma_status, pcs_status;
1950
1951         link_up = 0;
1952
1953         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1954                         MRVL88X2011_10G_PMD_STATUS_2);
1955         if (err < 0)
1956                 goto out;
1957
1958         /* Check PMA/PMD Register: 1.0001.2 == 1 */
1959         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1960                         MRVL88X2011_PMA_PMD_STATUS_1);
1961         if (err < 0)
1962                 goto out;
1963
1964         pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1965
1966         /* Check PMC Register : 3.0001.2 == 1: read twice */
1967         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1968                         MRVL88X2011_PMA_PMD_STATUS_1);
1969         if (err < 0)
1970                 goto out;
1971
1972         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1973                         MRVL88X2011_PMA_PMD_STATUS_1);
1974         if (err < 0)
1975                 goto out;
1976
1977         pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1978
1979         /* Check XGXS Register : 4.0018.[0-3,12] */
1980         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1981                         MRVL88X2011_10G_XGXS_LANE_STAT);
1982         if (err < 0)
1983                 goto out;
1984
1985         if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1986                     PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1987                     PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1988                     0x800))
1989                 link_up = (pma_status && pcs_status) ? 1 : 0;
1990
1991         np->link_config.active_speed = SPEED_10000;
1992         np->link_config.active_duplex = DUPLEX_FULL;
1993         err = 0;
1994 out:
1995         mrvl88x2011_act_led(np, (link_up ?
1996                                  MRVL88X2011_LED_CTL_PCS_ACT :
1997                                  MRVL88X2011_LED_CTL_OFF));
1998
1999         *link_up_p = link_up;
2000         return err;
2001 }
2002
2003 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2004 {
2005         int err, link_up;
2006         link_up = 0;
2007
2008         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2009                         BCM8704_PMD_RCV_SIGDET);
2010         if (err < 0 || err == 0xffff)
2011                 goto out;
2012         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2013                 err = 0;
2014                 goto out;
2015         }
2016
2017         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2018                         BCM8704_PCS_10G_R_STATUS);
2019         if (err < 0)
2020                 goto out;
2021
2022         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2023                 err = 0;
2024                 goto out;
2025         }
2026
2027         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2028                         BCM8704_PHYXS_XGXS_LANE_STAT);
2029         if (err < 0)
2030                 goto out;
2031         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2032                     PHYXS_XGXS_LANE_STAT_MAGIC |
2033                     PHYXS_XGXS_LANE_STAT_PATTEST |
2034                     PHYXS_XGXS_LANE_STAT_LANE3 |
2035                     PHYXS_XGXS_LANE_STAT_LANE2 |
2036                     PHYXS_XGXS_LANE_STAT_LANE1 |
2037                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2038                 err = 0;
2039                 np->link_config.active_speed = SPEED_INVALID;
2040                 np->link_config.active_duplex = DUPLEX_INVALID;
2041                 goto out;
2042         }
2043
2044         link_up = 1;
2045         np->link_config.active_speed = SPEED_10000;
2046         np->link_config.active_duplex = DUPLEX_FULL;
2047         err = 0;
2048
2049 out:
2050         *link_up_p = link_up;
2051         return err;
2052 }
2053
2054 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2055 {
2056         int err, link_up;
2057
2058         link_up = 0;
2059
2060         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2061                         BCM8704_PMD_RCV_SIGDET);
2062         if (err < 0)
2063                 goto out;
2064         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2065                 err = 0;
2066                 goto out;
2067         }
2068
2069         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2070                         BCM8704_PCS_10G_R_STATUS);
2071         if (err < 0)
2072                 goto out;
2073         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2074                 err = 0;
2075                 goto out;
2076         }
2077
2078         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2079                         BCM8704_PHYXS_XGXS_LANE_STAT);
2080         if (err < 0)
2081                 goto out;
2082
2083         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2084                     PHYXS_XGXS_LANE_STAT_MAGIC |
2085                     PHYXS_XGXS_LANE_STAT_LANE3 |
2086                     PHYXS_XGXS_LANE_STAT_LANE2 |
2087                     PHYXS_XGXS_LANE_STAT_LANE1 |
2088                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2089                 err = 0;
2090                 goto out;
2091         }
2092
2093         link_up = 1;
2094         np->link_config.active_speed = SPEED_10000;
2095         np->link_config.active_duplex = DUPLEX_FULL;
2096         err = 0;
2097
2098 out:
2099         *link_up_p = link_up;
2100         return err;
2101 }
2102
2103 static int link_status_10g(struct niu *np, int *link_up_p)
2104 {
2105         unsigned long flags;
2106         int err = -EINVAL;
2107
2108         spin_lock_irqsave(&np->lock, flags);
2109
2110         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2111                 int phy_id;
2112
2113                 phy_id = phy_decode(np->parent->port_phy, np->port);
2114                 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2115
2116                 /* handle different phy types */
2117                 switch (phy_id & NIU_PHY_ID_MASK) {
2118                 case NIU_PHY_ID_MRVL88X2011:
2119                         err = link_status_10g_mrvl(np, link_up_p);
2120                         break;
2121
2122                 default: /* bcom 8704 */
2123                         err = link_status_10g_bcom(np, link_up_p);
2124                         break;
2125                 }
2126         }
2127
2128         spin_unlock_irqrestore(&np->lock, flags);
2129
2130         return err;
2131 }
2132
2133 static int niu_10g_phy_present(struct niu *np)
2134 {
2135         u64 sig, mask, val;
2136
2137         sig = nr64(ESR_INT_SIGNALS);
2138         switch (np->port) {
2139         case 0:
2140                 mask = ESR_INT_SIGNALS_P0_BITS;
2141                 val = (ESR_INT_SRDY0_P0 |
2142                        ESR_INT_DET0_P0 |
2143                        ESR_INT_XSRDY_P0 |
2144                        ESR_INT_XDP_P0_CH3 |
2145                        ESR_INT_XDP_P0_CH2 |
2146                        ESR_INT_XDP_P0_CH1 |
2147                        ESR_INT_XDP_P0_CH0);
2148                 break;
2149
2150         case 1:
2151                 mask = ESR_INT_SIGNALS_P1_BITS;
2152                 val = (ESR_INT_SRDY0_P1 |
2153                        ESR_INT_DET0_P1 |
2154                        ESR_INT_XSRDY_P1 |
2155                        ESR_INT_XDP_P1_CH3 |
2156                        ESR_INT_XDP_P1_CH2 |
2157                        ESR_INT_XDP_P1_CH1 |
2158                        ESR_INT_XDP_P1_CH0);
2159                 break;
2160
2161         default:
2162                 return 0;
2163         }
2164
2165         if ((sig & mask) != val)
2166                 return 0;
2167         return 1;
2168 }
2169
2170 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2171 {
2172         unsigned long flags;
2173         int err = 0;
2174         int phy_present;
2175         int phy_present_prev;
2176
2177         spin_lock_irqsave(&np->lock, flags);
2178
2179         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2180                 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2181                         1 : 0;
2182                 phy_present = niu_10g_phy_present(np);
2183                 if (phy_present != phy_present_prev) {
2184                         /* state change */
2185                         if (phy_present) {
2186                                 /* A NEM was just plugged in */
2187                                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2188                                 if (np->phy_ops->xcvr_init)
2189                                         err = np->phy_ops->xcvr_init(np);
2190                                 if (err) {
2191                                         err = mdio_read(np, np->phy_addr,
2192                                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2193                                         if (err == 0xffff) {
2194                                                 /* No mdio, back-to-back XAUI */
2195                                                 goto out;
2196                                         }
2197                                         /* debounce */
2198                                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2199                                 }
2200                         } else {
2201                                 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2202                                 *link_up_p = 0;
2203                                 netif_warn(np, link, np->dev,
2204                                            "Hotplug PHY Removed\n");
2205                         }
2206                 }
2207 out:
2208                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
2209                         err = link_status_10g_bcm8706(np, link_up_p);
2210                         if (err == 0xffff) {
2211                                 /* No mdio, back-to-back XAUI: it is C10NEM */
2212                                 *link_up_p = 1;
2213                                 np->link_config.active_speed = SPEED_10000;
2214                                 np->link_config.active_duplex = DUPLEX_FULL;
2215                         }
2216                 }
2217         }
2218
2219         spin_unlock_irqrestore(&np->lock, flags);
2220
2221         return 0;
2222 }
2223
2224 static int niu_link_status(struct niu *np, int *link_up_p)
2225 {
2226         const struct niu_phy_ops *ops = np->phy_ops;
2227         int err;
2228
2229         err = 0;
2230         if (ops->link_status)
2231                 err = ops->link_status(np, link_up_p);
2232
2233         return err;
2234 }
2235
2236 static void niu_timer(unsigned long __opaque)
2237 {
2238         struct niu *np = (struct niu *) __opaque;
2239         unsigned long off;
2240         int err, link_up;
2241
2242         err = niu_link_status(np, &link_up);
2243         if (!err)
2244                 niu_link_status_common(np, link_up);
2245
2246         if (netif_carrier_ok(np->dev))
2247                 off = 5 * HZ;
2248         else
2249                 off = 1 * HZ;
2250         np->timer.expires = jiffies + off;
2251
2252         add_timer(&np->timer);
2253 }
2254
2255 static const struct niu_phy_ops phy_ops_10g_serdes = {
2256         .serdes_init            = serdes_init_10g_serdes,
2257         .link_status            = link_status_10g_serdes,
2258 };
2259
2260 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2261         .serdes_init            = serdes_init_niu_10g_serdes,
2262         .link_status            = link_status_10g_serdes,
2263 };
2264
2265 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2266         .serdes_init            = serdes_init_niu_1g_serdes,
2267         .link_status            = link_status_1g_serdes,
2268 };
2269
2270 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2271         .xcvr_init              = xcvr_init_1g_rgmii,
2272         .link_status            = link_status_1g_rgmii,
2273 };
2274
2275 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2276         .serdes_init            = serdes_init_niu_10g_fiber,
2277         .xcvr_init              = xcvr_init_10g,
2278         .link_status            = link_status_10g,
2279 };
2280
2281 static const struct niu_phy_ops phy_ops_10g_fiber = {
2282         .serdes_init            = serdes_init_10g,
2283         .xcvr_init              = xcvr_init_10g,
2284         .link_status            = link_status_10g,
2285 };
2286
2287 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2288         .serdes_init            = serdes_init_10g,
2289         .xcvr_init              = xcvr_init_10g_bcm8706,
2290         .link_status            = link_status_10g_hotplug,
2291 };
2292
2293 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2294         .serdes_init            = serdes_init_niu_10g_fiber,
2295         .xcvr_init              = xcvr_init_10g_bcm8706,
2296         .link_status            = link_status_10g_hotplug,
2297 };
2298
2299 static const struct niu_phy_ops phy_ops_10g_copper = {
2300         .serdes_init            = serdes_init_10g,
2301         .link_status            = link_status_10g, /* XXX */
2302 };
2303
2304 static const struct niu_phy_ops phy_ops_1g_fiber = {
2305         .serdes_init            = serdes_init_1g,
2306         .xcvr_init              = xcvr_init_1g,
2307         .link_status            = link_status_1g,
2308 };
2309
2310 static const struct niu_phy_ops phy_ops_1g_copper = {
2311         .xcvr_init              = xcvr_init_1g,
2312         .link_status            = link_status_1g,
2313 };
2314
2315 struct niu_phy_template {
2316         const struct niu_phy_ops        *ops;
2317         u32                             phy_addr_base;
2318 };
2319
2320 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2321         .ops            = &phy_ops_10g_fiber_niu,
2322         .phy_addr_base  = 16,
2323 };
2324
2325 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2326         .ops            = &phy_ops_10g_serdes_niu,
2327         .phy_addr_base  = 0,
2328 };
2329
2330 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2331         .ops            = &phy_ops_1g_serdes_niu,
2332         .phy_addr_base  = 0,
2333 };
2334
2335 static const struct niu_phy_template phy_template_10g_fiber = {
2336         .ops            = &phy_ops_10g_fiber,
2337         .phy_addr_base  = 8,
2338 };
2339
2340 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2341         .ops            = &phy_ops_10g_fiber_hotplug,
2342         .phy_addr_base  = 8,
2343 };
2344
2345 static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2346         .ops            = &phy_ops_niu_10g_hotplug,
2347         .phy_addr_base  = 8,
2348 };
2349
2350 static const struct niu_phy_template phy_template_10g_copper = {
2351         .ops            = &phy_ops_10g_copper,
2352         .phy_addr_base  = 10,
2353 };
2354
2355 static const struct niu_phy_template phy_template_1g_fiber = {
2356         .ops            = &phy_ops_1g_fiber,
2357         .phy_addr_base  = 0,
2358 };
2359
2360 static const struct niu_phy_template phy_template_1g_copper = {
2361         .ops            = &phy_ops_1g_copper,
2362         .phy_addr_base  = 0,
2363 };
2364
2365 static const struct niu_phy_template phy_template_1g_rgmii = {
2366         .ops            = &phy_ops_1g_rgmii,
2367         .phy_addr_base  = 0,
2368 };
2369
2370 static const struct niu_phy_template phy_template_10g_serdes = {
2371         .ops            = &phy_ops_10g_serdes,
2372         .phy_addr_base  = 0,
2373 };
2374
2375 static int niu_atca_port_num[4] = {
2376         0, 0,  11, 10
2377 };
2378
2379 static int serdes_init_10g_serdes(struct niu *np)
2380 {
2381         struct niu_link_config *lp = &np->link_config;
2382         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2383         u64 ctrl_val, test_cfg_val, sig, mask, val;
2384         u64 reset_val;
2385
2386         switch (np->port) {
2387         case 0:
2388                 reset_val =  ENET_SERDES_RESET_0;
2389                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2390                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2391                 pll_cfg = ENET_SERDES_0_PLL_CFG;
2392                 break;
2393         case 1:
2394                 reset_val =  ENET_SERDES_RESET_1;
2395                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2396                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2397                 pll_cfg = ENET_SERDES_1_PLL_CFG;
2398                 break;
2399
2400         default:
2401                 return -EINVAL;
2402         }
2403         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2404                     ENET_SERDES_CTRL_SDET_1 |
2405                     ENET_SERDES_CTRL_SDET_2 |
2406                     ENET_SERDES_CTRL_SDET_3 |
2407                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2408                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2409                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2410                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2411                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2412                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2413                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2414                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2415         test_cfg_val = 0;
2416
2417         if (lp->loopback_mode == LOOPBACK_PHY) {
2418                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2419                                   ENET_SERDES_TEST_MD_0_SHIFT) |
2420                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2421                                   ENET_SERDES_TEST_MD_1_SHIFT) |
2422                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2423                                   ENET_SERDES_TEST_MD_2_SHIFT) |
2424                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2425                                   ENET_SERDES_TEST_MD_3_SHIFT));
2426         }
2427
2428         esr_reset(np);
2429         nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2430         nw64(ctrl_reg, ctrl_val);
2431         nw64(test_cfg_reg, test_cfg_val);
2432
2433         /* Initialize all 4 lanes of the SERDES.  */
2434         for (i = 0; i < 4; i++) {
2435                 u32 rxtx_ctrl, glue0;
2436                 int err;
2437
2438                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2439                 if (err)
2440                         return err;
2441                 err = esr_read_glue0(np, i, &glue0);
2442                 if (err)
2443                         return err;
2444
2445                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2446                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2447                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2448
2449                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2450                            ESR_GLUE_CTRL0_THCNT |
2451                            ESR_GLUE_CTRL0_BLTIME);
2452                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2453                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2454                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2455                           (BLTIME_300_CYCLES <<
2456                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
2457
2458                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2459                 if (err)
2460                         return err;
2461                 err = esr_write_glue0(np, i, glue0);
2462                 if (err)
2463                         return err;
2464         }
2465
2466
2467         sig = nr64(ESR_INT_SIGNALS);
2468         switch (np->port) {
2469         case 0:
2470                 mask = ESR_INT_SIGNALS_P0_BITS;
2471                 val = (ESR_INT_SRDY0_P0 |
2472                        ESR_INT_DET0_P0 |
2473                        ESR_INT_XSRDY_P0 |
2474                        ESR_INT_XDP_P0_CH3 |
2475                        ESR_INT_XDP_P0_CH2 |
2476                        ESR_INT_XDP_P0_CH1 |
2477                        ESR_INT_XDP_P0_CH0);
2478                 break;
2479
2480         case 1:
2481                 mask = ESR_INT_SIGNALS_P1_BITS;
2482                 val = (ESR_INT_SRDY0_P1 |
2483                        ESR_INT_DET0_P1 |
2484                        ESR_INT_XSRDY_P1 |
2485                        ESR_INT_XDP_P1_CH3 |
2486                        ESR_INT_XDP_P1_CH2 |
2487                        ESR_INT_XDP_P1_CH1 |
2488                        ESR_INT_XDP_P1_CH0);
2489                 break;
2490
2491         default:
2492                 return -EINVAL;
2493         }
2494
2495         if ((sig & mask) != val) {
2496                 int err;
2497                 err = serdes_init_1g_serdes(np);
2498                 if (!err) {
2499                         np->flags &= ~NIU_FLAGS_10G;
2500                         np->mac_xcvr = MAC_XCVR_PCS;
2501                 }  else {
2502                         netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2503                                    np->port);
2504                         return -ENODEV;
2505                 }
2506         }
2507
2508         return 0;
2509 }
2510
2511 static int niu_determine_phy_disposition(struct niu *np)
2512 {
2513         struct niu_parent *parent = np->parent;
2514         u8 plat_type = parent->plat_type;
2515         const struct niu_phy_template *tp;
2516         u32 phy_addr_off = 0;
2517
2518         if (plat_type == PLAT_TYPE_NIU) {
2519                 switch (np->flags &
2520                         (NIU_FLAGS_10G |
2521                          NIU_FLAGS_FIBER |
2522                          NIU_FLAGS_XCVR_SERDES)) {
2523                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2524                         /* 10G Serdes */
2525                         tp = &phy_template_niu_10g_serdes;
2526                         break;
2527                 case NIU_FLAGS_XCVR_SERDES:
2528                         /* 1G Serdes */
2529                         tp = &phy_template_niu_1g_serdes;
2530                         break;
2531                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2532                         /* 10G Fiber */
2533                 default:
2534                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2535                                 tp = &phy_template_niu_10g_hotplug;
2536                                 if (np->port == 0)
2537                                         phy_addr_off = 8;
2538                                 if (np->port == 1)
2539                                         phy_addr_off = 12;
2540                         } else {
2541                                 tp = &phy_template_niu_10g_fiber;
2542                                 phy_addr_off += np->port;
2543                         }
2544                         break;
2545                 }
2546         } else {
2547                 switch (np->flags &
2548                         (NIU_FLAGS_10G |
2549                          NIU_FLAGS_FIBER |
2550                          NIU_FLAGS_XCVR_SERDES)) {
2551                 case 0:
2552                         /* 1G copper */
2553                         tp = &phy_template_1g_copper;
2554                         if (plat_type == PLAT_TYPE_VF_P0)
2555                                 phy_addr_off = 10;
2556                         else if (plat_type == PLAT_TYPE_VF_P1)
2557                                 phy_addr_off = 26;
2558
2559                         phy_addr_off += (np->port ^ 0x3);
2560                         break;
2561
2562                 case NIU_FLAGS_10G:
2563                         /* 10G copper */
2564                         tp = &phy_template_10g_copper;
2565                         break;
2566
2567                 case NIU_FLAGS_FIBER:
2568                         /* 1G fiber */
2569                         tp = &phy_template_1g_fiber;
2570                         break;
2571
2572                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2573                         /* 10G fiber */
2574                         tp = &phy_template_10g_fiber;
2575                         if (plat_type == PLAT_TYPE_VF_P0 ||
2576                             plat_type == PLAT_TYPE_VF_P1)
2577                                 phy_addr_off = 8;
2578                         phy_addr_off += np->port;
2579                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2580                                 tp = &phy_template_10g_fiber_hotplug;
2581                                 if (np->port == 0)
2582                                         phy_addr_off = 8;
2583                                 if (np->port == 1)
2584                                         phy_addr_off = 12;
2585                         }
2586                         break;
2587
2588                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2589                 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2590                 case NIU_FLAGS_XCVR_SERDES:
2591                         switch(np->port) {
2592                         case 0:
2593                         case 1:
2594                                 tp = &phy_template_10g_serdes;
2595                                 break;
2596                         case 2:
2597                         case 3:
2598                                 tp = &phy_template_1g_rgmii;
2599                                 break;
2600                         default:
2601                                 return -EINVAL;
2602                                 break;
2603                         }
2604                         phy_addr_off = niu_atca_port_num[np->port];
2605                         break;
2606
2607                 default:
2608                         return -EINVAL;
2609                 }
2610         }
2611
2612         np->phy_ops = tp->ops;
2613         np->phy_addr = tp->phy_addr_base + phy_addr_off;
2614
2615         return 0;
2616 }
2617
2618 static int niu_init_link(struct niu *np)
2619 {
2620         struct niu_parent *parent = np->parent;
2621         int err, ignore;
2622
2623         if (parent->plat_type == PLAT_TYPE_NIU) {
2624                 err = niu_xcvr_init(np);
2625                 if (err)
2626                         return err;
2627                 msleep(200);
2628         }
2629         err = niu_serdes_init(np);
2630         if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
2631                 return err;
2632         msleep(200);
2633         err = niu_xcvr_init(np);
2634         if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
2635                 niu_link_status(np, &ignore);
2636         return 0;
2637 }
2638
2639 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2640 {
2641         u16 reg0 = addr[4] << 8 | addr[5];
2642         u16 reg1 = addr[2] << 8 | addr[3];
2643         u16 reg2 = addr[0] << 8 | addr[1];
2644
2645         if (np->flags & NIU_FLAGS_XMAC) {
2646                 nw64_mac(XMAC_ADDR0, reg0);
2647                 nw64_mac(XMAC_ADDR1, reg1);
2648                 nw64_mac(XMAC_ADDR2, reg2);
2649         } else {
2650                 nw64_mac(BMAC_ADDR0, reg0);
2651                 nw64_mac(BMAC_ADDR1, reg1);
2652                 nw64_mac(BMAC_ADDR2, reg2);
2653         }
2654 }
2655
2656 static int niu_num_alt_addr(struct niu *np)
2657 {
2658         if (np->flags & NIU_FLAGS_XMAC)
2659                 return XMAC_NUM_ALT_ADDR;
2660         else
2661                 return BMAC_NUM_ALT_ADDR;
2662 }
2663
2664 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2665 {
2666         u16 reg0 = addr[4] << 8 | addr[5];
2667         u16 reg1 = addr[2] << 8 | addr[3];
2668         u16 reg2 = addr[0] << 8 | addr[1];
2669
2670         if (index >= niu_num_alt_addr(np))
2671                 return -EINVAL;
2672
2673         if (np->flags & NIU_FLAGS_XMAC) {
2674                 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2675                 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2676                 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2677         } else {
2678                 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2679                 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2680                 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2681         }
2682
2683         return 0;
2684 }
2685
2686 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2687 {
2688         unsigned long reg;
2689         u64 val, mask;
2690
2691         if (index >= niu_num_alt_addr(np))
2692                 return -EINVAL;
2693
2694         if (np->flags & NIU_FLAGS_XMAC) {
2695                 reg = XMAC_ADDR_CMPEN;
2696                 mask = 1 << index;
2697         } else {
2698                 reg = BMAC_ADDR_CMPEN;
2699                 mask = 1 << (index + 1);
2700         }
2701
2702         val = nr64_mac(reg);
2703         if (on)
2704                 val |= mask;
2705         else
2706                 val &= ~mask;
2707         nw64_mac(reg, val);
2708
2709         return 0;
2710 }
2711
2712 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2713                                    int num, int mac_pref)
2714 {
2715         u64 val = nr64_mac(reg);
2716         val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2717         val |= num;
2718         if (mac_pref)
2719                 val |= HOST_INFO_MPR;
2720         nw64_mac(reg, val);
2721 }
2722
2723 static int __set_rdc_table_num(struct niu *np,
2724                                int xmac_index, int bmac_index,
2725                                int rdc_table_num, int mac_pref)
2726 {
2727         unsigned long reg;
2728
2729         if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2730                 return -EINVAL;
2731         if (np->flags & NIU_FLAGS_XMAC)
2732                 reg = XMAC_HOST_INFO(xmac_index);
2733         else
2734                 reg = BMAC_HOST_INFO(bmac_index);
2735         __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2736         return 0;
2737 }
2738
2739 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2740                                          int mac_pref)
2741 {
2742         return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2743 }
2744
2745 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2746                                            int mac_pref)
2747 {
2748         return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2749 }
2750
2751 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2752                                      int table_num, int mac_pref)
2753 {
2754         if (idx >= niu_num_alt_addr(np))
2755                 return -EINVAL;
2756         return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2757 }
2758
2759 static u64 vlan_entry_set_parity(u64 reg_val)
2760 {
2761         u64 port01_mask;
2762         u64 port23_mask;
2763
2764         port01_mask = 0x00ff;
2765         port23_mask = 0xff00;
2766
2767         if (hweight64(reg_val & port01_mask) & 1)
2768                 reg_val |= ENET_VLAN_TBL_PARITY0;
2769         else
2770                 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2771
2772         if (hweight64(reg_val & port23_mask) & 1)
2773                 reg_val |= ENET_VLAN_TBL_PARITY1;
2774         else
2775                 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2776
2777         return reg_val;
2778 }
2779
2780 static void vlan_tbl_write(struct niu *np, unsigned long index,
2781                            int port, int vpr, int rdc_table)
2782 {
2783         u64 reg_val = nr64(ENET_VLAN_TBL(index));
2784
2785         reg_val &= ~((ENET_VLAN_TBL_VPR |
2786                       ENET_VLAN_TBL_VLANRDCTBLN) <<
2787                      ENET_VLAN_TBL_SHIFT(port));
2788         if (vpr)
2789                 reg_val |= (ENET_VLAN_TBL_VPR <<
2790                             ENET_VLAN_TBL_SHIFT(port));
2791         reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2792
2793         reg_val = vlan_entry_set_parity(reg_val);
2794
2795         nw64(ENET_VLAN_TBL(index), reg_val);
2796 }
2797
2798 static void vlan_tbl_clear(struct niu *np)
2799 {
2800         int i;
2801
2802         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2803                 nw64(ENET_VLAN_TBL(i), 0);
2804 }
2805
2806 static int tcam_wait_bit(struct niu *np, u64 bit)
2807 {
2808         int limit = 1000;
2809
2810         while (--limit > 0) {
2811                 if (nr64(TCAM_CTL) & bit)
2812                         break;
2813                 udelay(1);
2814         }
2815         if (limit <= 0)
2816                 return -ENODEV;
2817
2818         return 0;
2819 }
2820
2821 static int tcam_flush(struct niu *np, int index)
2822 {
2823         nw64(TCAM_KEY_0, 0x00);
2824         nw64(TCAM_KEY_MASK_0, 0xff);
2825         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2826
2827         return tcam_wait_bit(np, TCAM_CTL_STAT);
2828 }
2829
2830 #if 0
2831 static int tcam_read(struct niu *np, int index,
2832                      u64 *key, u64 *mask)
2833 {
2834         int err;
2835
2836         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2837         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2838         if (!err) {
2839                 key[0] = nr64(TCAM_KEY_0);
2840                 key[1] = nr64(TCAM_KEY_1);
2841                 key[2] = nr64(TCAM_KEY_2);
2842                 key[3] = nr64(TCAM_KEY_3);
2843                 mask[0] = nr64(TCAM_KEY_MASK_0);
2844                 mask[1] = nr64(TCAM_KEY_MASK_1);
2845                 mask[2] = nr64(TCAM_KEY_MASK_2);
2846                 mask[3] = nr64(TCAM_KEY_MASK_3);
2847         }
2848         return err;
2849 }
2850 #endif
2851
2852 static int tcam_write(struct niu *np, int index,
2853                       u64 *key, u64 *mask)
2854 {
2855         nw64(TCAM_KEY_0, key[0]);
2856         nw64(TCAM_KEY_1, key[1]);
2857         nw64(TCAM_KEY_2, key[2]);
2858         nw64(TCAM_KEY_3, key[3]);
2859         nw64(TCAM_KEY_MASK_0, mask[0]);
2860         nw64(TCAM_KEY_MASK_1, mask[1]);
2861         nw64(TCAM_KEY_MASK_2, mask[2]);
2862         nw64(TCAM_KEY_MASK_3, mask[3]);
2863         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2864
2865         return tcam_wait_bit(np, TCAM_CTL_STAT);
2866 }
2867
2868 #if 0
2869 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2870 {
2871         int err;
2872
2873         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2874         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2875         if (!err)
2876                 *data = nr64(TCAM_KEY_1);
2877
2878         return err;
2879 }
2880 #endif
2881
2882 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2883 {
2884         nw64(TCAM_KEY_1, assoc_data);
2885         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2886
2887         return tcam_wait_bit(np, TCAM_CTL_STAT);
2888 }
2889
2890 static void tcam_enable(struct niu *np, int on)
2891 {
2892         u64 val = nr64(FFLP_CFG_1);
2893
2894         if (on)
2895                 val &= ~FFLP_CFG_1_TCAM_DIS;
2896         else
2897                 val |= FFLP_CFG_1_TCAM_DIS;
2898         nw64(FFLP_CFG_1, val);
2899 }
2900
2901 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2902 {
2903         u64 val = nr64(FFLP_CFG_1);
2904
2905         val &= ~(FFLP_CFG_1_FFLPINITDONE |
2906                  FFLP_CFG_1_CAMLAT |
2907                  FFLP_CFG_1_CAMRATIO);
2908         val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2909         val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2910         nw64(FFLP_CFG_1, val);
2911
2912         val = nr64(FFLP_CFG_1);
2913         val |= FFLP_CFG_1_FFLPINITDONE;
2914         nw64(FFLP_CFG_1, val);
2915 }
2916
2917 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2918                                       int on)
2919 {
2920         unsigned long reg;
2921         u64 val;
2922
2923         if (class < CLASS_CODE_ETHERTYPE1 ||
2924             class > CLASS_CODE_ETHERTYPE2)
2925                 return -EINVAL;
2926
2927         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2928         val = nr64(reg);
2929         if (on)
2930                 val |= L2_CLS_VLD;
2931         else
2932                 val &= ~L2_CLS_VLD;
2933         nw64(reg, val);
2934
2935         return 0;
2936 }
2937
2938 #if 0
2939 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2940                                    u64 ether_type)
2941 {
2942         unsigned long reg;
2943         u64 val;
2944
2945         if (class < CLASS_CODE_ETHERTYPE1 ||
2946             class > CLASS_CODE_ETHERTYPE2 ||
2947             (ether_type & ~(u64)0xffff) != 0)
2948                 return -EINVAL;
2949
2950         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2951         val = nr64(reg);
2952         val &= ~L2_CLS_ETYPE;
2953         val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2954         nw64(reg, val);
2955
2956         return 0;
2957 }
2958 #endif
2959
2960 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2961                                      int on)
2962 {
2963         unsigned long reg;
2964         u64 val;
2965
2966         if (class < CLASS_CODE_USER_PROG1 ||
2967             class > CLASS_CODE_USER_PROG4)
2968                 return -EINVAL;
2969
2970         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2971         val = nr64(reg);
2972         if (on)
2973                 val |= L3_CLS_VALID;
2974         else
2975                 val &= ~L3_CLS_VALID;
2976         nw64(reg, val);
2977
2978         return 0;
2979 }
2980
2981 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2982                                   int ipv6, u64 protocol_id,
2983                                   u64 tos_mask, u64 tos_val)
2984 {
2985         unsigned long reg;
2986         u64 val;
2987
2988         if (class < CLASS_CODE_USER_PROG1 ||
2989             class > CLASS_CODE_USER_PROG4 ||
2990             (protocol_id & ~(u64)0xff) != 0 ||
2991             (tos_mask & ~(u64)0xff) != 0 ||
2992             (tos_val & ~(u64)0xff) != 0)
2993                 return -EINVAL;
2994
2995         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2996         val = nr64(reg);
2997         val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2998                  L3_CLS_TOSMASK | L3_CLS_TOS);
2999         if (ipv6)
3000                 val |= L3_CLS_IPVER;
3001         val |= (protocol_id << L3_CLS_PID_SHIFT);
3002         val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
3003         val |= (tos_val << L3_CLS_TOS_SHIFT);
3004         nw64(reg, val);
3005
3006         return 0;
3007 }
3008
3009 static int tcam_early_init(struct niu *np)
3010 {
3011         unsigned long i;
3012         int err;
3013
3014         tcam_enable(np, 0);
3015         tcam_set_lat_and_ratio(np,
3016                                DEFAULT_TCAM_LATENCY,
3017                                DEFAULT_TCAM_ACCESS_RATIO);
3018         for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3019                 err = tcam_user_eth_class_enable(np, i, 0);
3020                 if (err)
3021                         return err;
3022         }
3023         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3024                 err = tcam_user_ip_class_enable(np, i, 0);
3025                 if (err)
3026                         return err;
3027         }
3028
3029         return 0;
3030 }
3031
3032 static int tcam_flush_all(struct niu *np)
3033 {
3034         unsigned long i;
3035
3036         for (i = 0; i < np->parent->tcam_num_entries; i++) {
3037                 int err = tcam_flush(np, i);
3038                 if (err)
3039                         return err;
3040         }
3041         return 0;
3042 }
3043
3044 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3045 {
3046         return ((u64)index | (num_entries == 1 ?
3047                               HASH_TBL_ADDR_AUTOINC : 0));
3048 }
3049
3050 #if 0
3051 static int hash_read(struct niu *np, unsigned long partition,
3052                      unsigned long index, unsigned long num_entries,
3053                      u64 *data)
3054 {
3055         u64 val = hash_addr_regval(index, num_entries);
3056         unsigned long i;
3057
3058         if (partition >= FCRAM_NUM_PARTITIONS ||
3059             index + num_entries > FCRAM_SIZE)
3060                 return -EINVAL;
3061
3062         nw64(HASH_TBL_ADDR(partition), val);
3063         for (i = 0; i < num_entries; i++)
3064                 data[i] = nr64(HASH_TBL_DATA(partition));
3065
3066         return 0;
3067 }
3068 #endif
3069
3070 static int hash_write(struct niu *np, unsigned long partition,
3071                       unsigned long index, unsigned long num_entries,
3072                       u64 *data)
3073 {
3074         u64 val = hash_addr_regval(index, num_entries);
3075         unsigned long i;
3076
3077         if (partition >= FCRAM_NUM_PARTITIONS ||
3078             index + (num_entries * 8) > FCRAM_SIZE)
3079                 return -EINVAL;
3080
3081         nw64(HASH_TBL_ADDR(partition), val);
3082         for (i = 0; i < num_entries; i++)
3083                 nw64(HASH_TBL_DATA(partition), data[i]);
3084
3085         return 0;
3086 }
3087
3088 static void fflp_reset(struct niu *np)
3089 {
3090         u64 val;
3091
3092         nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3093         udelay(10);
3094         nw64(FFLP_CFG_1, 0);
3095
3096         val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3097         nw64(FFLP_CFG_1, val);
3098 }
3099
3100 static void fflp_set_timings(struct niu *np)
3101 {
3102         u64 val = nr64(FFLP_CFG_1);
3103
3104         val &= ~FFLP_CFG_1_FFLPINITDONE;
3105         val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3106         nw64(FFLP_CFG_1, val);
3107
3108         val = nr64(FFLP_CFG_1);
3109         val |= FFLP_CFG_1_FFLPINITDONE;
3110         nw64(FFLP_CFG_1, val);
3111
3112         val = nr64(FCRAM_REF_TMR);
3113         val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3114         val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3115         val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3116         nw64(FCRAM_REF_TMR, val);
3117 }
3118
3119 static int fflp_set_partition(struct niu *np, u64 partition,
3120                               u64 mask, u64 base, int enable)
3121 {
3122         unsigned long reg;
3123         u64 val;
3124
3125         if (partition >= FCRAM_NUM_PARTITIONS ||
3126             (mask & ~(u64)0x1f) != 0 ||
3127             (base & ~(u64)0x1f) != 0)
3128                 return -EINVAL;
3129
3130         reg = FLW_PRT_SEL(partition);
3131
3132         val = nr64(reg);
3133         val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3134         val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3135         val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3136         if (enable)
3137                 val |= FLW_PRT_SEL_EXT;
3138         nw64(reg, val);
3139
3140         return 0;
3141 }
3142
3143 static int fflp_disable_all_partitions(struct niu *np)
3144 {
3145         unsigned long i;
3146
3147         for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3148                 int err = fflp_set_partition(np, 0, 0, 0, 0);
3149                 if (err)
3150                         return err;
3151         }
3152         return 0;
3153 }
3154
3155 static void fflp_llcsnap_enable(struct niu *np, int on)
3156 {
3157         u64 val = nr64(FFLP_CFG_1);
3158
3159         if (on)
3160                 val |= FFLP_CFG_1_LLCSNAP;
3161         else
3162                 val &= ~FFLP_CFG_1_LLCSNAP;
3163         nw64(FFLP_CFG_1, val);
3164 }
3165
3166 static void fflp_errors_enable(struct niu *np, int on)
3167 {
3168         u64 val = nr64(FFLP_CFG_1);
3169
3170         if (on)
3171                 val &= ~FFLP_CFG_1_ERRORDIS;
3172         else
3173                 val |= FFLP_CFG_1_ERRORDIS;
3174         nw64(FFLP_CFG_1, val);
3175 }
3176
3177 static int fflp_hash_clear(struct niu *np)
3178 {
3179         struct fcram_hash_ipv4 ent;
3180         unsigned long i;
3181
3182         /* IPV4 hash entry with valid bit clear, rest is don't care.  */
3183         memset(&ent, 0, sizeof(ent));
3184         ent.header = HASH_HEADER_EXT;
3185
3186         for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3187                 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3188                 if (err)
3189                         return err;
3190         }
3191         return 0;
3192 }
3193
3194 static int fflp_early_init(struct niu *np)
3195 {
3196         struct niu_parent *parent;
3197         unsigned long flags;
3198         int err;
3199
3200         niu_lock_parent(np, flags);
3201
3202         parent = np->parent;
3203         err = 0;
3204         if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3205                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3206                         fflp_reset(np);
3207                         fflp_set_timings(np);
3208                         err = fflp_disable_all_partitions(np);
3209                         if (err) {
3210                                 netif_printk(np, probe, KERN_DEBUG, np->dev,
3211                                              "fflp_disable_all_partitions failed, err=%d\n",
3212                                              err);
3213                                 goto out;
3214                         }
3215                 }
3216
3217                 err = tcam_early_init(np);
3218                 if (err) {
3219                         netif_printk(np, probe, KERN_DEBUG, np->dev,
3220                                      "tcam_early_init failed, err=%d\n", err);
3221                         goto out;
3222                 }
3223                 fflp_llcsnap_enable(np, 1);
3224                 fflp_errors_enable(np, 0);
3225                 nw64(H1POLY, 0);
3226                 nw64(H2POLY, 0);
3227
3228                 err = tcam_flush_all(np);
3229                 if (err) {
3230                         netif_printk(np, probe, KERN_DEBUG, np->dev,
3231                                      "tcam_flush_all failed, err=%d\n", err);
3232                         goto out;
3233                 }
3234                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3235                         err = fflp_hash_clear(np);
3236                         if (err) {
3237                                 netif_printk(np, probe, KERN_DEBUG, np->dev,
3238                                              "fflp_hash_clear failed, err=%d\n",
3239                                              err);
3240                                 goto out;
3241                         }
3242                 }
3243
3244                 vlan_tbl_clear(np);
3245
3246                 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3247         }
3248 out:
3249         niu_unlock_parent(np, flags);
3250         return err;
3251 }
3252
3253 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3254 {
3255         if (class_code < CLASS_CODE_USER_PROG1 ||
3256             class_code > CLASS_CODE_SCTP_IPV6)
3257                 return -EINVAL;
3258
3259         nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3260         return 0;
3261 }
3262
3263 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3264 {
3265         if (class_code < CLASS_CODE_USER_PROG1 ||
3266             class_code > CLASS_CODE_SCTP_IPV6)
3267                 return -EINVAL;
3268
3269         nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3270         return 0;
3271 }
3272
3273 /* Entries for the ports are interleaved in the TCAM */
3274 static u16 tcam_get_index(struct niu *np, u16 idx)
3275 {
3276         /* One entry reserved for IP fragment rule */
3277         if (idx >= (np->clas.tcam_sz - 1))
3278                 idx = 0;
3279         return (np->clas.tcam_top + ((idx+1) * np->parent->num_ports));
3280 }
3281
3282 static u16 tcam_get_size(struct niu *np)
3283 {
3284         /* One entry reserved for IP fragment rule */
3285         return np->clas.tcam_sz - 1;
3286 }
3287
3288 static u16 tcam_get_valid_entry_cnt(struct niu *np)
3289 {
3290         /* One entry reserved for IP fragment rule */
3291         return np->clas.tcam_valid_entries - 1;
3292 }
3293
3294 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3295                               u32 offset, u32 size)
3296 {
3297         int i = skb_shinfo(skb)->nr_frags;
3298         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3299
3300         frag->page = page;
3301         frag->page_offset = offset;
3302         frag->size = size;
3303
3304         skb->len += size;
3305         skb->data_len += size;
3306         skb->truesize += size;
3307
3308         skb_shinfo(skb)->nr_frags = i + 1;
3309 }
3310
3311 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3312 {
3313         a >>= PAGE_SHIFT;
3314         a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3315
3316         return (a & (MAX_RBR_RING_SIZE - 1));
3317 }
3318
3319 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3320                                     struct page ***link)
3321 {
3322         unsigned int h = niu_hash_rxaddr(rp, addr);
3323         struct page *p, **pp;
3324
3325         addr &= PAGE_MASK;
3326         pp = &rp->rxhash[h];
3327         for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3328                 if (p->index == addr) {
3329                         *link = pp;
3330                         goto found;
3331                 }
3332         }
3333         BUG();
3334
3335 found:
3336         return p;
3337 }
3338
3339 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3340 {
3341         unsigned int h = niu_hash_rxaddr(rp, base);
3342
3343         page->index = base;
3344         page->mapping = (struct address_space *) rp->rxhash[h];
3345         rp->rxhash[h] = page;
3346 }
3347
3348 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3349                             gfp_t mask, int start_index)
3350 {
3351         struct page *page;
3352         u64 addr;
3353         int i;
3354
3355         page = alloc_page(mask);
3356         if (!page)
3357                 return -ENOMEM;
3358
3359         addr = np->ops->map_page(np->device, page, 0,
3360                                  PAGE_SIZE, DMA_FROM_DEVICE);
3361
3362         niu_hash_page(rp, page, addr);
3363         if (rp->rbr_blocks_per_page > 1)
3364                 atomic_add(rp->rbr_blocks_per_page - 1,
3365                            &compound_head(page)->_count);
3366
3367         for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3368                 __le32 *rbr = &rp->rbr[start_index + i];
3369
3370                 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3371                 addr += rp->rbr_block_size;
3372         }
3373
3374         return 0;
3375 }
3376
3377 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3378 {
3379         int index = rp->rbr_index;
3380
3381         rp->rbr_pending++;
3382         if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3383                 int err = niu_rbr_add_page(np, rp, mask, index);
3384
3385                 if (unlikely(err)) {
3386                         rp->rbr_pending--;
3387                         return;
3388                 }
3389
3390                 rp->rbr_index += rp->rbr_blocks_per_page;
3391                 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3392                 if (rp->rbr_index == rp->rbr_table_size)
3393                         rp->rbr_index = 0;
3394
3395                 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3396                         nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3397                         rp->rbr_pending = 0;
3398                 }
3399         }
3400 }
3401
3402 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3403 {
3404         unsigned int index = rp->rcr_index;
3405         int num_rcr = 0;
3406
3407         rp->rx_dropped++;
3408         while (1) {
3409                 struct page *page, **link;
3410                 u64 addr, val;
3411                 u32 rcr_size;
3412
3413                 num_rcr++;
3414
3415                 val = le64_to_cpup(&rp->rcr[index]);
3416                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3417                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3418                 page = niu_find_rxpage(rp, addr, &link);
3419
3420                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3421                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3422                 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3423                         *link = (struct page *) page->mapping;
3424                         np->ops->unmap_page(np->device, page->index,
3425                                             PAGE_SIZE, DMA_FROM_DEVICE);
3426                         page->index = 0;
3427                         page->mapping = NULL;
3428                         __free_page(page);
3429                         rp->rbr_refill_pending++;
3430                 }
3431
3432                 index = NEXT_RCR(rp, index);
3433                 if (!(val & RCR_ENTRY_MULTI))
3434                         break;
3435
3436         }
3437         rp->rcr_index = index;
3438
3439         return num_rcr;
3440 }
3441
3442 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3443                               struct rx_ring_info *rp)
3444 {
3445         unsigned int index = rp->rcr_index;
3446         struct rx_pkt_hdr1 *rh;
3447         struct sk_buff *skb;
3448         int len, num_rcr;
3449
3450         skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3451         if (unlikely(!skb))
3452                 return niu_rx_pkt_ignore(np, rp);
3453
3454         num_rcr = 0;
3455         while (1) {
3456                 struct page *page, **link;
3457                 u32 rcr_size, append_size;
3458                 u64 addr, val, off;
3459
3460                 num_rcr++;
3461
3462                 val = le64_to_cpup(&rp->rcr[index]);
3463
3464                 len = (val & RCR_ENTRY_L2_LEN) >>
3465                         RCR_ENTRY_L2_LEN_SHIFT;
3466                 len -= ETH_FCS_LEN;
3467
3468                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3469                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3470                 page = niu_find_rxpage(rp, addr, &link);
3471
3472                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3473                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3474
3475                 off = addr & ~PAGE_MASK;
3476                 append_size = rcr_size;
3477                 if (num_rcr == 1) {
3478                         int ptype;
3479
3480                         ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3481                         if ((ptype == RCR_PKT_TYPE_TCP ||
3482                              ptype == RCR_PKT_TYPE_UDP) &&
3483                             !(val & (RCR_ENTRY_NOPORT |
3484                                      RCR_ENTRY_ERROR)))
3485                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3486                         else
3487                                 skb->ip_summed = CHECKSUM_NONE;
3488                 } else if (!(val & RCR_ENTRY_MULTI))
3489                         append_size = len - skb->len;
3490
3491                 niu_rx_skb_append(skb, page, off, append_size);
3492                 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3493                         *link = (struct page *) page->mapping;
3494                         np->ops->unmap_page(np->device, page->index,
3495                                             PAGE_SIZE, DMA_FROM_DEVICE);
3496                         page->index = 0;
3497                         page->mapping = NULL;
3498                         rp->rbr_refill_pending++;
3499                 } else
3500                         get_page(page);
3501
3502                 index = NEXT_RCR(rp, index);
3503                 if (!(val & RCR_ENTRY_MULTI))
3504                         break;
3505
3506         }
3507         rp->rcr_index = index;
3508
3509         len += sizeof(*rh);
3510         len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN);
3511         __pskb_pull_tail(skb, len);
3512
3513         rh = (struct rx_pkt_hdr1 *) skb->data;
3514         if (np->dev->features & NETIF_F_RXHASH)
3515                 skb->rxhash = ((u32)rh->hashval2_0 << 24 |
3516                                (u32)rh->hashval2_1 << 16 |
3517                                (u32)rh->hashval1_1 << 8 |
3518                                (u32)rh->hashval1_2 << 0);
3519         skb_pull(skb, sizeof(*rh));
3520
3521         rp->rx_packets++;
3522         rp->rx_bytes += skb->len;
3523
3524         skb->protocol = eth_type_trans(skb, np->dev);
3525         skb_record_rx_queue(skb, rp->rx_channel);
3526         napi_gro_receive(napi, skb);
3527
3528         return num_rcr;
3529 }
3530
3531 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3532 {
3533         int blocks_per_page = rp->rbr_blocks_per_page;
3534         int err, index = rp->rbr_index;
3535
3536         err = 0;
3537         while (index < (rp->rbr_table_size - blocks_per_page)) {
3538                 err = niu_rbr_add_page(np, rp, mask, index);
3539                 if (err)
3540                         break;
3541
3542                 index += blocks_per_page;
3543         }
3544
3545         rp->rbr_index = index;
3546         return err;
3547 }
3548
3549 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3550 {
3551         int i;
3552
3553         for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3554                 struct page *page;
3555
3556                 page = rp->rxhash[i];
3557                 while (page) {
3558                         struct page *next = (struct page *) page->mapping;
3559                         u64 base = page->index;
3560
3561                         np->ops->unmap_page(np->device, base, PAGE_SIZE,
3562                                             DMA_FROM_DEVICE);
3563                         page->index = 0;
3564                         page->mapping = NULL;
3565
3566                         __free_page(page);
3567
3568                         page = next;
3569                 }
3570         }
3571
3572         for (i = 0; i < rp->rbr_table_size; i++)
3573                 rp->rbr[i] = cpu_to_le32(0);
3574         rp->rbr_index = 0;
3575 }
3576
3577 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3578 {
3579         struct tx_buff_info *tb = &rp->tx_buffs[idx];
3580         struct sk_buff *skb = tb->skb;
3581         struct tx_pkt_hdr *tp;
3582         u64 tx_flags;
3583         int i, len;
3584
3585         tp = (struct tx_pkt_hdr *) skb->data;
3586         tx_flags = le64_to_cpup(&tp->flags);
3587
3588         rp->tx_packets++;
3589         rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3590                          ((tx_flags & TXHDR_PAD) / 2));
3591
3592         len = skb_headlen(skb);
3593         np->ops->unmap_single(np->device, tb->mapping,
3594                               len, DMA_TO_DEVICE);
3595
3596         if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3597                 rp->mark_pending--;
3598
3599         tb->skb = NULL;
3600         do {
3601                 idx = NEXT_TX(rp, idx);
3602                 len -= MAX_TX_DESC_LEN;
3603         } while (len > 0);
3604
3605         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3606                 tb = &rp->tx_buffs[idx];
3607                 BUG_ON(tb->skb != NULL);
3608                 np->ops->unmap_page(np->device, tb->mapping,
3609                                     skb_shinfo(skb)->frags[i].size,
3610                                     DMA_TO_DEVICE);
3611                 idx = NEXT_TX(rp, idx);
3612         }
3613
3614         dev_kfree_skb(skb);
3615
3616         return idx;
3617 }
3618
3619 #define NIU_TX_WAKEUP_THRESH(rp)                ((rp)->pending / 4)
3620
3621 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3622 {
3623         struct netdev_queue *txq;
3624         u16 pkt_cnt, tmp;
3625         int cons, index;
3626         u64 cs;
3627
3628         index = (rp - np->tx_rings);
3629         txq = netdev_get_tx_queue(np->dev, index);
3630
3631         cs = rp->tx_cs;
3632         if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3633                 goto out;
3634
3635         tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3636         pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3637                 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3638
3639         rp->last_pkt_cnt = tmp;
3640
3641         cons = rp->cons;
3642
3643         netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3644                      "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
3645
3646         while (pkt_cnt--)
3647                 cons = release_tx_packet(np, rp, cons);
3648
3649         rp->cons = cons;
3650         smp_mb();
3651
3652 out:
3653         if (unlikely(netif_tx_queue_stopped(txq) &&
3654                      (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3655                 __netif_tx_lock(txq, smp_processor_id());
3656                 if (netif_tx_queue_stopped(txq) &&
3657                     (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3658                         netif_tx_wake_queue(txq);
3659                 __netif_tx_unlock(txq);
3660         }
3661 }
3662
3663 static inline void niu_sync_rx_discard_stats(struct niu *np,
3664                                              struct rx_ring_info *rp,
3665                                              const int limit)
3666 {
3667         /* This elaborate scheme is needed for reading the RX discard
3668          * counters, as they are only 16-bit and can overflow quickly,
3669          * and because the overflow indication bit is not usable as
3670          * the counter value does not wrap, but remains at max value
3671          * 0xFFFF.
3672          *
3673          * In theory and in practice counters can be lost in between
3674          * reading nr64() and clearing the counter nw64().  For this
3675          * reason, the number of counter clearings nw64() is
3676          * limited/reduced though the limit parameter.
3677          */
3678         int rx_channel = rp->rx_channel;
3679         u32 misc, wred;
3680
3681         /* RXMISC (Receive Miscellaneous Discard Count), covers the
3682          * following discard events: IPP (Input Port Process),
3683          * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3684          * Block Ring) prefetch buffer is empty.
3685          */
3686         misc = nr64(RXMISC(rx_channel));
3687         if (unlikely((misc & RXMISC_COUNT) > limit)) {
3688                 nw64(RXMISC(rx_channel), 0);
3689                 rp->rx_errors += misc & RXMISC_COUNT;
3690
3691                 if (unlikely(misc & RXMISC_OFLOW))
3692                         dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3693                                 rx_channel);
3694
3695                 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3696                              "rx-%d: MISC drop=%u over=%u\n",
3697                              rx_channel, misc, misc-limit);
3698         }
3699
3700         /* WRED (Weighted Random Early Discard) by hardware */
3701         wred = nr64(RED_DIS_CNT(rx_channel));
3702         if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3703                 nw64(RED_DIS_CNT(rx_channel), 0);
3704                 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3705
3706                 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3707                         dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
3708
3709                 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3710                              "rx-%d: WRED drop=%u over=%u\n",
3711                              rx_channel, wred, wred-limit);
3712         }
3713 }
3714
3715 static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3716                        struct rx_ring_info *rp, int budget)
3717 {
3718         int qlen, rcr_done = 0, work_done = 0;
3719         struct rxdma_mailbox *mbox = rp->mbox;
3720         u64 stat;
3721
3722 #if 1
3723         stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3724         qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3725 #else
3726         stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3727         qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3728 #endif
3729         mbox->rx_dma_ctl_stat = 0;
3730         mbox->rcrstat_a = 0;
3731
3732         netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3733                      "%s(chan[%d]), stat[%llx] qlen=%d\n",
3734                      __func__, rp->rx_channel, (unsigned long long)stat, qlen);
3735
3736         rcr_done = work_done = 0;
3737         qlen = min(qlen, budget);
3738         while (work_done < qlen) {
3739                 rcr_done += niu_process_rx_pkt(napi, np, rp);
3740                 work_done++;
3741         }
3742
3743         if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3744                 unsigned int i;
3745
3746                 for (i = 0; i < rp->rbr_refill_pending; i++)
3747                         niu_rbr_refill(np, rp, GFP_ATOMIC);
3748                 rp->rbr_refill_pending = 0;
3749         }
3750
3751         stat = (RX_DMA_CTL_STAT_MEX |
3752                 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3753                 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3754
3755         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3756
3757         /* Only sync discards stats when qlen indicate potential for drops */
3758         if (qlen > 10)
3759                 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3760
3761         return work_done;
3762 }
3763
3764 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3765 {
3766         u64 v0 = lp->v0;
3767         u32 tx_vec = (v0 >> 32);
3768         u32 rx_vec = (v0 & 0xffffffff);
3769         int i, work_done = 0;
3770
3771         netif_printk(np, intr, KERN_DEBUG, np->dev,
3772                      "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
3773
3774         for (i = 0; i < np->num_tx_rings; i++) {
3775                 struct tx_ring_info *rp = &np->tx_rings[i];
3776                 if (tx_vec & (1 << rp->tx_channel))
3777                         niu_tx_work(np, rp);
3778                 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3779         }
3780
3781         for (i = 0; i < np->num_rx_rings; i++) {
3782                 struct rx_ring_info *rp = &np->rx_rings[i];
3783
3784                 if (rx_vec & (1 << rp->rx_channel)) {
3785                         int this_work_done;
3786
3787                         this_work_done = niu_rx_work(&lp->napi, np, rp,
3788                                                      budget);
3789
3790                         budget -= this_work_done;
3791                         work_done += this_work_done;
3792                 }
3793                 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3794         }
3795
3796         return work_done;
3797 }
3798
3799 static int niu_poll(struct napi_struct *napi, int budget)
3800 {
3801         struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3802         struct niu *np = lp->np;
3803         int work_done;
3804
3805         work_done = niu_poll_core(np, lp, budget);
3806
3807         if (work_done < budget) {
3808                 napi_complete(napi);
3809                 niu_ldg_rearm(np, lp, 1);
3810         }
3811         return work_done;
3812 }
3813
3814 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3815                                   u64 stat)
3816 {
3817         netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
3818
3819         if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3820                 pr_cont("RBR_TMOUT ");
3821         if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3822                 pr_cont("RSP_CNT ");
3823         if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3824                 pr_cont("BYTE_EN_BUS ");
3825         if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3826                 pr_cont("RSP_DAT ");
3827         if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3828                 pr_cont("RCR_ACK ");
3829         if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3830                 pr_cont("RCR_SHA_PAR ");
3831         if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3832                 pr_cont("RBR_PRE_PAR ");
3833         if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3834                 pr_cont("CONFIG ");
3835         if (stat & RX_DMA_CTL_STAT_RCRINCON)
3836                 pr_cont("RCRINCON ");
3837         if (stat & RX_DMA_CTL_STAT_RCRFULL)
3838                 pr_cont("RCRFULL ");
3839         if (stat & RX_DMA_CTL_STAT_RBRFULL)
3840                 pr_cont("RBRFULL ");
3841         if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3842                 pr_cont("RBRLOGPAGE ");
3843         if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3844                 pr_cont("CFIGLOGPAGE ");
3845         if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3846                 pr_cont("DC_FIDO ");
3847
3848         pr_cont(")\n");
3849 }
3850
3851 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3852 {
3853         u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3854         int err = 0;
3855
3856
3857         if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3858                     RX_DMA_CTL_STAT_PORT_FATAL))
3859                 err = -EINVAL;
3860
3861         if (err) {
3862                 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3863                            rp->rx_channel,
3864                            (unsigned long long) stat);
3865
3866                 niu_log_rxchan_errors(np, rp, stat);
3867         }
3868
3869         nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3870              stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3871
3872         return err;
3873 }
3874
3875 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3876                                   u64 cs)
3877 {
3878         netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
3879
3880         if (cs & TX_CS_MBOX_ERR)
3881                 pr_cont("MBOX ");
3882         if (cs & TX_CS_PKT_SIZE_ERR)
3883                 pr_cont("PKT_SIZE ");
3884         if (cs & TX_CS_TX_RING_OFLOW)
3885                 pr_cont("TX_RING_OFLOW ");
3886         if (cs & TX_CS_PREF_BUF_PAR_ERR)
3887                 pr_cont("PREF_BUF_PAR ");
3888         if (cs & TX_CS_NACK_PREF)
3889                 pr_cont("NACK_PREF ");
3890         if (cs & TX_CS_NACK_PKT_RD)
3891                 pr_cont("NACK_PKT_RD ");
3892         if (cs & TX_CS_CONF_PART_ERR)
3893                 pr_cont("CONF_PART ");
3894         if (cs & TX_CS_PKT_PRT_ERR)
3895                 pr_cont("PKT_PTR ");
3896
3897         pr_cont(")\n");
3898 }
3899
3900 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3901 {
3902         u64 cs, logh, logl;
3903
3904         cs = nr64(TX_CS(rp->tx_channel));
3905         logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3906         logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3907
3908         netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3909                    rp->tx_channel,
3910                    (unsigned long long)cs,
3911                    (unsigned long long)logh,
3912                    (unsigned long long)logl);
3913
3914         niu_log_txchan_errors(np, rp, cs);
3915
3916         return -ENODEV;
3917 }
3918
3919 static int niu_mif_interrupt(struct niu *np)
3920 {
3921         u64 mif_status = nr64(MIF_STATUS);
3922         int phy_mdint = 0;
3923
3924         if (np->flags & NIU_FLAGS_XMAC) {
3925                 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3926
3927                 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3928                         phy_mdint = 1;
3929         }
3930
3931         netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3932                    (unsigned long long)mif_status, phy_mdint);
3933
3934         return -ENODEV;
3935 }
3936
3937 static void niu_xmac_interrupt(struct niu *np)
3938 {
3939         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3940         u64 val;
3941
3942         val = nr64_mac(XTXMAC_STATUS);
3943         if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3944                 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3945         if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3946                 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3947         if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3948                 mp->tx_fifo_errors++;
3949         if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3950                 mp->tx_overflow_errors++;
3951         if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3952                 mp->tx_max_pkt_size_errors++;
3953         if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3954                 mp->tx_underflow_errors++;
3955
3956         val = nr64_mac(XRXMAC_STATUS);
3957         if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3958                 mp->rx_local_faults++;
3959         if (val & XRXMAC_STATUS_RFLT_DET)
3960                 mp->rx_remote_faults++;
3961         if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3962                 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3963         if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3964                 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3965         if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3966                 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3967         if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3968                 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3969         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3970                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3971         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3972                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3973         if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3974                 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3975         if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3976                 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3977         if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3978                 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3979         if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3980                 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3981         if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3982                 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3983         if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3984                 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3985         if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3986                 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3987         if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
3988                 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3989         if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3990                 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3991         if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3992                 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3993         if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3994                 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3995         if (val & XRXMAC_STATUS_RXUFLOW)
3996                 mp->rx_underflows++;
3997         if (val & XRXMAC_STATUS_RXOFLOW)
3998                 mp->rx_overflows++;
3999
4000         val = nr64_mac(XMAC_FC_STAT);
4001         if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
4002                 mp->pause_off_state++;
4003         if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
4004                 mp->pause_on_state++;
4005         if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
4006                 mp->pause_received++;
4007 }
4008
4009 static void niu_bmac_interrupt(struct niu *np)
4010 {
4011         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4012         u64 val;
4013
4014         val = nr64_mac(BTXMAC_STATUS);
4015         if (val & BTXMAC_STATUS_UNDERRUN)
4016                 mp->tx_underflow_errors++;
4017         if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4018                 mp->tx_max_pkt_size_errors++;
4019         if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4020                 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4021         if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4022                 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4023
4024         val = nr64_mac(BRXMAC_STATUS);
4025         if (val & BRXMAC_STATUS_OVERFLOW)
4026                 mp->rx_overflows++;
4027         if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4028                 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4029         if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4030                 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4031         if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4032                 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4033         if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4034                 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4035
4036         val = nr64_mac(BMAC_CTRL_STATUS);
4037         if (val & BMAC_CTRL_STATUS_NOPAUSE)
4038                 mp->pause_off_state++;
4039         if (val & BMAC_CTRL_STATUS_PAUSE)
4040                 mp->pause_on_state++;
4041         if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4042                 mp->pause_received++;
4043 }
4044
4045 static int niu_mac_interrupt(struct niu *np)
4046 {
4047         if (np->flags & NIU_FLAGS_XMAC)
4048                 niu_xmac_interrupt(np);
4049         else
4050                 niu_bmac_interrupt(np);
4051
4052         return 0;
4053 }
4054
4055 static void niu_log_device_error(struct niu *np, u64 stat)
4056 {
4057         netdev_err(np->dev, "Core device errors ( ");
4058
4059         if (stat & SYS_ERR_MASK_META2)
4060                 pr_cont("META2 ");
4061         if (stat & SYS_ERR_MASK_META1)
4062                 pr_cont("META1 ");
4063         if (stat & SYS_ERR_MASK_PEU)
4064                 pr_cont("PEU ");
4065         if (stat & SYS_ERR_MASK_TXC)
4066                 pr_cont("TXC ");
4067         if (stat & SYS_ERR_MASK_RDMC)
4068                 pr_cont("RDMC ");
4069         if (stat & SYS_ERR_MASK_TDMC)
4070                 pr_cont("TDMC ");
4071         if (stat & SYS_ERR_MASK_ZCP)
4072                 pr_cont("ZCP ");
4073         if (stat & SYS_ERR_MASK_FFLP)
4074                 pr_cont("FFLP ");
4075         if (stat & SYS_ERR_MASK_IPP)
4076                 pr_cont("IPP ");
4077         if (stat & SYS_ERR_MASK_MAC)
4078                 pr_cont("MAC ");
4079         if (stat & SYS_ERR_MASK_SMX)
4080                 pr_cont("SMX ");
4081
4082         pr_cont(")\n");
4083 }
4084
4085 static int niu_device_error(struct niu *np)
4086 {
4087         u64 stat = nr64(SYS_ERR_STAT);
4088
4089         netdev_err(np->dev, "Core device error, stat[%llx]\n",
4090                    (unsigned long long)stat);
4091
4092         niu_log_device_error(np, stat);
4093
4094         return -ENODEV;
4095 }
4096
4097 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4098                               u64 v0, u64 v1, u64 v2)
4099 {
4100
4101         int i, err = 0;
4102
4103         lp->v0 = v0;
4104         lp->v1 = v1;
4105         lp->v2 = v2;
4106
4107         if (v1 & 0x00000000ffffffffULL) {
4108                 u32 rx_vec = (v1 & 0xffffffff);
4109
4110                 for (i = 0; i < np->num_rx_rings; i++) {
4111                         struct rx_ring_info *rp = &np->rx_rings[i];
4112
4113                         if (rx_vec & (1 << rp->rx_channel)) {
4114                                 int r = niu_rx_error(np, rp);
4115                                 if (r) {
4116                                         err = r;
4117                                 } else {
4118                                         if (!v0)
4119                                                 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4120                                                      RX_DMA_CTL_STAT_MEX);
4121                                 }
4122                         }
4123                 }
4124         }
4125         if (v1 & 0x7fffffff00000000ULL) {
4126                 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4127
4128                 for (i = 0; i < np->num_tx_rings; i++) {
4129                         struct tx_ring_info *rp = &np->tx_rings[i];
4130
4131                         if (tx_vec & (1 << rp->tx_channel)) {
4132                                 int r = niu_tx_error(np, rp);
4133                                 if (r)
4134                                         err = r;
4135                         }
4136                 }
4137         }
4138         if ((v0 | v1) & 0x8000000000000000ULL) {
4139                 int r = niu_mif_interrupt(np);
4140                 if (r)
4141                         err = r;
4142         }
4143         if (v2) {
4144                 if (v2 & 0x01ef) {
4145                         int r = niu_mac_interrupt(np);
4146                         if (r)
4147                                 err = r;
4148                 }
4149                 if (v2 & 0x0210) {
4150                         int r = niu_device_error(np);
4151                         if (r)
4152                                 err = r;
4153                 }
4154         }
4155
4156         if (err)
4157                 niu_enable_interrupts(np, 0);
4158
4159         return err;
4160 }
4161
4162 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4163                             int ldn)
4164 {
4165         struct rxdma_mailbox *mbox = rp->mbox;
4166         u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4167
4168         stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4169                       RX_DMA_CTL_STAT_RCRTO);
4170         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4171
4172         netif_printk(np, intr, KERN_DEBUG, np->dev,
4173                      "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
4174 }
4175
4176 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4177                             int ldn)
4178 {
4179         rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4180
4181         netif_printk(np, intr, KERN_DEBUG, np->dev,
4182                      "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
4183 }
4184
4185 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4186 {
4187         struct niu_parent *parent = np->parent;
4188         u32 rx_vec, tx_vec;
4189         int i;
4190
4191         tx_vec = (v0 >> 32);
4192         rx_vec = (v0 & 0xffffffff);
4193
4194         for (i = 0; i < np->num_rx_rings; i++) {
4195                 struct rx_ring_info *rp = &np->rx_rings[i];
4196                 int ldn = LDN_RXDMA(rp->rx_channel);
4197
4198                 if (parent->ldg_map[ldn] != ldg)
4199                         continue;
4200
4201                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4202                 if (rx_vec & (1 << rp->rx_channel))
4203                         niu_rxchan_intr(np, rp, ldn);
4204         }
4205
4206         for (i = 0; i < np->num_tx_rings; i++) {
4207                 struct tx_ring_info *rp = &np->tx_rings[i];
4208                 int ldn = LDN_TXDMA(rp->tx_channel);
4209
4210                 if (parent->ldg_map[ldn] != ldg)
4211                         continue;
4212
4213                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4214                 if (tx_vec & (1 << rp->tx_channel))
4215                         niu_txchan_intr(np, rp, ldn);
4216         }
4217 }
4218
4219 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4220                               u64 v0, u64 v1, u64 v2)
4221 {
4222         if (likely(napi_schedule_prep(&lp->napi))) {
4223                 lp->v0 = v0;
4224                 lp->v1 = v1;
4225                 lp->v2 = v2;
4226                 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4227                 __napi_schedule(&lp->napi);
4228         }
4229 }
4230
4231 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4232 {
4233         struct niu_ldg *lp = dev_id;
4234         struct niu *np = lp->np;
4235         int ldg = lp->ldg_num;
4236         unsigned long flags;
4237         u64 v0, v1, v2;
4238
4239         if (netif_msg_intr(np))
4240                 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4241                        __func__, lp, ldg);
4242
4243         spin_lock_irqsave(&np->lock, flags);
4244
4245         v0 = nr64(LDSV0(ldg));
4246         v1 = nr64(LDSV1(ldg));
4247         v2 = nr64(LDSV2(ldg));
4248
4249         if (netif_msg_intr(np))
4250                 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
4251                        (unsigned long long) v0,
4252                        (unsigned long long) v1,
4253                        (unsigned long long) v2);
4254
4255         if (unlikely(!v0 && !v1 && !v2)) {
4256                 spin_unlock_irqrestore(&np->lock, flags);
4257                 return IRQ_NONE;
4258         }
4259
4260         if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4261                 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4262                 if (err)
4263                         goto out;
4264         }
4265         if (likely(v0 & ~((u64)1 << LDN_MIF)))
4266                 niu_schedule_napi(np, lp, v0, v1, v2);
4267         else
4268                 niu_ldg_rearm(np, lp, 1);
4269 out:
4270         spin_unlock_irqrestore(&np->lock, flags);
4271
4272         return IRQ_HANDLED;
4273 }
4274
4275 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4276 {
4277         if (rp->mbox) {
4278                 np->ops->free_coherent(np->device,
4279                                        sizeof(struct rxdma_mailbox),
4280                                        rp->mbox, rp->mbox_dma);
4281                 rp->mbox = NULL;
4282         }
4283         if (rp->rcr) {
4284                 np->ops->free_coherent(np->device,
4285                                        MAX_RCR_RING_SIZE * sizeof(__le64),
4286                                        rp->rcr, rp->rcr_dma);
4287                 rp->rcr = NULL;
4288                 rp->rcr_table_size = 0;
4289                 rp->rcr_index = 0;
4290         }
4291         if (rp->rbr) {
4292                 niu_rbr_free(np, rp);
4293
4294                 np->ops->free_coherent(np->device,
4295                                        MAX_RBR_RING_SIZE * sizeof(__le32),
4296                                        rp->rbr, rp->rbr_dma);
4297                 rp->rbr = NULL;
4298                 rp->rbr_table_size = 0;
4299                 rp->rbr_index = 0;
4300         }
4301         kfree(rp->rxhash);
4302         rp->rxhash = NULL;
4303 }
4304
4305 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4306 {
4307         if (rp->mbox) {
4308                 np->ops->free_coherent(np->device,
4309                                        sizeof(struct txdma_mailbox),
4310                                        rp->mbox, rp->mbox_dma);
4311                 rp->mbox = NULL;
4312         }
4313         if (rp->descr) {
4314                 int i;
4315
4316                 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4317                         if (rp->tx_buffs[i].skb)
4318                                 (void) release_tx_packet(np, rp, i);
4319                 }
4320
4321                 np->ops->free_coherent(np->device,
4322                                        MAX_TX_RING_SIZE * sizeof(__le64),
4323                                        rp->descr, rp->descr_dma);
4324                 rp->descr = NULL;
4325                 rp->pending = 0;
4326                 rp->prod = 0;
4327                 rp->cons = 0;
4328                 rp->wrap_bit = 0;
4329         }
4330 }
4331
4332 static void niu_free_channels(struct niu *np)
4333 {
4334         int i;
4335
4336         if (np->rx_rings) {
4337                 for (i = 0; i < np->num_rx_rings; i++) {
4338                         struct rx_ring_info *rp = &np->rx_rings[i];
4339
4340                         niu_free_rx_ring_info(np, rp);
4341                 }
4342                 kfree(np->rx_rings);
4343                 np->rx_rings = NULL;
4344                 np->num_rx_rings = 0;
4345         }
4346
4347         if (np->tx_rings) {
4348                 for (i = 0; i < np->num_tx_rings; i++) {
4349                         struct tx_ring_info *rp = &np->tx_rings[i];
4350
4351                         niu_free_tx_ring_info(np, rp);
4352                 }
4353                 kfree(np->tx_rings);
4354                 np->tx_rings = NULL;
4355                 np->num_tx_rings = 0;
4356         }
4357 }
4358
4359 static int niu_alloc_rx_ring_info(struct niu *np,
4360                                   struct rx_ring_info *rp)
4361 {
4362         BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4363
4364         rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4365                              GFP_KERNEL);
4366         if (!rp->rxhash)
4367                 return -ENOMEM;
4368
4369         rp->mbox = np->ops->alloc_coherent(np->device,
4370                                            sizeof(struct rxdma_mailbox),
4371                                            &rp->mbox_dma, GFP_KERNEL);
4372         if (!rp->mbox)
4373                 return -ENOMEM;
4374         if ((unsigned long)rp->mbox & (64UL - 1)) {
4375                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4376                            rp->mbox);
4377                 return -EINVAL;
4378         }
4379
4380         rp->rcr = np->ops->alloc_coherent(np->device,
4381                                           MAX_RCR_RING_SIZE * sizeof(__le64),
4382                                           &rp->rcr_dma, GFP_KERNEL);
4383         if (!rp->rcr)
4384                 return -ENOMEM;
4385         if ((unsigned long)rp->rcr & (64UL - 1)) {
4386                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4387                            rp->rcr);
4388                 return -EINVAL;
4389         }
4390         rp->rcr_table_size = MAX_RCR_RING_SIZE;
4391         rp->rcr_index = 0;
4392
4393         rp->rbr = np->ops->alloc_coherent(np->device,
4394                                           MAX_RBR_RING_SIZE * sizeof(__le32),
4395                                           &rp->rbr_dma, GFP_KERNEL);
4396         if (!rp->rbr)
4397                 return -ENOMEM;
4398         if ((unsigned long)rp->rbr & (64UL - 1)) {
4399                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4400                            rp->rbr);
4401                 return -EINVAL;
4402         }
4403         rp->rbr_table_size = MAX_RBR_RING_SIZE;
4404         rp->rbr_index = 0;
4405         rp->rbr_pending = 0;
4406
4407         return 0;
4408 }
4409
4410 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4411 {
4412         int mtu = np->dev->mtu;
4413
4414         /* These values are recommended by the HW designers for fair
4415          * utilization of DRR amongst the rings.
4416          */
4417         rp->max_burst = mtu + 32;
4418         if (rp->max_burst > 4096)
4419                 rp->max_burst = 4096;
4420 }
4421
4422 static int niu_alloc_tx_ring_info(struct niu *np,
4423                                   struct tx_ring_info *rp)
4424 {
4425         BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4426
4427         rp->mbox = np->ops->alloc_coherent(np->device,
4428                                            sizeof(struct txdma_mailbox),
4429                                            &rp->mbox_dma, GFP_KERNEL);
4430         if (!rp->mbox)
4431                 return -ENOMEM;
4432         if ((unsigned long)rp->mbox & (64UL - 1)) {
4433                 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4434                            rp->mbox);
4435                 return -EINVAL;
4436         }
4437
4438         rp->descr = np->ops->alloc_coherent(np->device,
4439                                             MAX_TX_RING_SIZE * sizeof(__le64),
4440                                             &rp->descr_dma, GFP_KERNEL);
4441         if (!rp->descr)
4442                 return -ENOMEM;
4443         if ((unsigned long)rp->descr & (64UL - 1)) {
4444                 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4445                            rp->descr);
4446                 return -EINVAL;
4447         }
4448
4449         rp->pending = MAX_TX_RING_SIZE;
4450         rp->prod = 0;
4451         rp->cons = 0;
4452         rp->wrap_bit = 0;
4453
4454         /* XXX make these configurable... XXX */
4455         rp->mark_freq = rp->pending / 4;
4456
4457         niu_set_max_burst(np, rp);
4458
4459         return 0;
4460 }
4461
4462 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4463 {
4464         u16 bss;
4465
4466         bss = min(PAGE_SHIFT, 15);
4467
4468         rp->rbr_block_size = 1 << bss;
4469         rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4470
4471         rp->rbr_sizes[0] = 256;
4472         rp->rbr_sizes[1] = 1024;
4473         if (np->dev->mtu > ETH_DATA_LEN) {
4474                 switch (PAGE_SIZE) {
4475                 case 4 * 1024:
4476                         rp->rbr_sizes[2] = 4096;
4477                         break;
4478
4479                 default:
4480                         rp->rbr_sizes[2] = 8192;
4481                         break;
4482                 }
4483         } else {
4484                 rp->rbr_sizes[2] = 2048;
4485         }
4486         rp->rbr_sizes[3] = rp->rbr_block_size;
4487 }
4488
4489 static int niu_alloc_channels(struct niu *np)
4490 {
4491         struct niu_parent *parent = np->parent;
4492         int first_rx_channel, first_tx_channel;
4493         int i, port, err;
4494
4495         port = np->port;
4496         first_rx_channel = first_tx_channel = 0;
4497         for (i = 0; i < port; i++) {
4498                 first_rx_channel += parent->rxchan_per_port[i];
4499                 first_tx_channel += parent->txchan_per_port[i];
4500         }
4501
4502         np->num_rx_rings = parent->rxchan_per_port[port];
4503         np->num_tx_rings = parent->txchan_per_port[port];
4504
4505         np->dev->real_num_tx_queues = np->num_tx_rings;
4506
4507         np->rx_rings = kcalloc(np->num_rx_rings, sizeof(struct rx_ring_info),
4508                                GFP_KERNEL);
4509         err = -ENOMEM;
4510         if (!np->rx_rings)
4511                 goto out_err;
4512
4513         for (i = 0; i < np->num_rx_rings; i++) {
4514                 struct rx_ring_info *rp = &np->rx_rings[i];
4515
4516                 rp->np = np;
4517                 rp->rx_channel = first_rx_channel + i;
4518
4519                 err = niu_alloc_rx_ring_info(np, rp);
4520                 if (err)
4521                         goto out_err;
4522
4523                 niu_size_rbr(np, rp);
4524
4525                 /* XXX better defaults, configurable, etc... XXX */
4526                 rp->nonsyn_window = 64;
4527                 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4528                 rp->syn_window = 64;
4529                 rp->syn_threshold = rp->rcr_table_size - 64;
4530                 rp->rcr_pkt_threshold = 16;
4531                 rp->rcr_timeout = 8;
4532                 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4533                 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4534                         rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4535
4536                 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4537                 if (err)
4538                         return err;
4539         }
4540
4541         np->tx_rings = kcalloc(np->num_tx_rings, sizeof(struct tx_ring_info),
4542                                GFP_KERNEL);
4543         err = -ENOMEM;
4544         if (!np->tx_rings)
4545                 goto out_err;
4546
4547         for (i = 0; i < np->num_tx_rings; i++) {
4548                 struct tx_ring_info *rp = &np->tx_rings[i];
4549
4550                 rp->np = np;
4551                 rp->tx_channel = first_tx_channel + i;
4552
4553                 err = niu_alloc_tx_ring_info(np, rp);
4554                 if (err)
4555                         goto out_err;
4556         }
4557
4558         return 0;
4559
4560 out_err:
4561         niu_free_channels(np);
4562         return err;
4563 }
4564
4565 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4566 {
4567         int limit = 1000;
4568
4569         while (--limit > 0) {
4570                 u64 val = nr64(TX_CS(channel));
4571                 if (val & TX_CS_SNG_STATE)
4572                         return 0;
4573         }
4574         return -ENODEV;
4575 }
4576
4577 static int niu_tx_channel_stop(struct niu *np, int channel)
4578 {
4579         u64 val = nr64(TX_CS(channel));
4580
4581         val |= TX_CS_STOP_N_GO;
4582         nw64(TX_CS(channel), val);
4583
4584         return niu_tx_cs_sng_poll(np, channel);
4585 }
4586
4587 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4588 {
4589         int limit = 1000;
4590
4591         while (--limit > 0) {
4592                 u64 val = nr64(TX_CS(channel));
4593                 if (!(val & TX_CS_RST))
4594                         return 0;
4595         }
4596         return -ENODEV;
4597 }
4598
4599 static int niu_tx_channel_reset(struct niu *np, int channel)
4600 {
4601         u64 val = nr64(TX_CS(channel));
4602         int err;
4603
4604         val |= TX_CS_RST;
4605         nw64(TX_CS(channel), val);
4606
4607         err = niu_tx_cs_reset_poll(np, channel);
4608         if (!err)
4609                 nw64(TX_RING_KICK(channel), 0);
4610
4611         return err;
4612 }
4613
4614 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4615 {
4616         u64 val;
4617
4618         nw64(TX_LOG_MASK1(channel), 0);
4619         nw64(TX_LOG_VAL1(channel), 0);
4620         nw64(TX_LOG_MASK2(channel), 0);
4621         nw64(TX_LOG_VAL2(channel), 0);
4622         nw64(TX_LOG_PAGE_RELO1(channel), 0);
4623         nw64(TX_LOG_PAGE_RELO2(channel), 0);
4624         nw64(TX_LOG_PAGE_HDL(channel), 0);
4625
4626         val  = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4627         val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4628         nw64(TX_LOG_PAGE_VLD(channel), val);
4629
4630         /* XXX TXDMA 32bit mode? XXX */
4631
4632         return 0;
4633 }
4634
4635 static void niu_txc_enable_port(struct niu *np, int on)
4636 {
4637         unsigned long flags;
4638         u64 val, mask;
4639
4640         niu_lock_parent(np, flags);
4641         val = nr64(TXC_CONTROL);
4642         mask = (u64)1 << np->port;
4643         if (on) {
4644                 val |= TXC_CONTROL_ENABLE | mask;
4645         } else {
4646                 val &= ~mask;
4647                 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4648                         val &= ~TXC_CONTROL_ENABLE;
4649         }
4650         nw64(TXC_CONTROL, val);
4651         niu_unlock_parent(np, flags);
4652 }
4653
4654 static void niu_txc_set_imask(struct niu *np, u64 imask)
4655 {
4656         unsigned long flags;
4657         u64 val;
4658
4659         niu_lock_parent(np, flags);
4660         val = nr64(TXC_INT_MASK);
4661         val &= ~TXC_INT_MASK_VAL(np->port);
4662         val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4663         niu_unlock_parent(np, flags);
4664 }
4665
4666 static void niu_txc_port_dma_enable(struct niu *np, int on)
4667 {
4668         u64 val = 0;
4669
4670         if (on) {
4671                 int i;
4672
4673                 for (i = 0; i < np->num_tx_rings; i++)
4674                         val |= (1 << np->tx_rings[i].tx_channel);
4675         }
4676         nw64(TXC_PORT_DMA(np->port), val);
4677 }
4678
4679 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4680 {
4681         int err, channel = rp->tx_channel;
4682         u64 val, ring_len;
4683
4684         err = niu_tx_channel_stop(np, channel);
4685         if (err)
4686                 return err;
4687
4688         err = niu_tx_channel_reset(np, channel);
4689         if (err)
4690                 return err;
4691
4692         err = niu_tx_channel_lpage_init(np, channel);
4693         if (err)
4694                 return err;
4695
4696         nw64(TXC_DMA_MAX(channel), rp->max_burst);
4697         nw64(TX_ENT_MSK(channel), 0);
4698
4699         if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4700                               TX_RNG_CFIG_STADDR)) {
4701                 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4702                            channel, (unsigned long long)rp->descr_dma);
4703                 return -EINVAL;
4704         }
4705
4706         /* The length field in TX_RNG_CFIG is measured in 64-byte
4707          * blocks.  rp->pending is the number of TX descriptors in
4708          * our ring, 8 bytes each, thus we divide by 8 bytes more
4709          * to get the proper value the chip wants.
4710          */
4711         ring_len = (rp->pending / 8);
4712
4713         val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4714                rp->descr_dma);
4715         nw64(TX_RNG_CFIG(channel), val);
4716
4717         if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4718             ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4719                 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4720                             channel, (unsigned long long)rp->mbox_dma);
4721                 return -EINVAL;
4722         }
4723         nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4724         nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4725
4726         nw64(TX_CS(channel), 0);
4727
4728         rp->last_pkt_cnt = 0;
4729
4730         return 0;
4731 }
4732
4733 static void niu_init_rdc_groups(struct niu *np)
4734 {
4735         struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4736         int i, first_table_num = tp->first_table_num;
4737
4738         for (i = 0; i < tp->num_tables; i++) {
4739                 struct rdc_table *tbl = &tp->tables[i];
4740                 int this_table = first_table_num + i;
4741                 int slot;
4742
4743                 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4744                         nw64(RDC_TBL(this_table, slot),
4745                              tbl->rxdma_channel[slot]);
4746         }
4747
4748         nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4749 }
4750
4751 static void niu_init_drr_weight(struct niu *np)
4752 {
4753         int type = phy_decode(np->parent->port_phy, np->port);
4754         u64 val;
4755
4756         switch (type) {
4757         case PORT_TYPE_10G:
4758                 val = PT_DRR_WEIGHT_DEFAULT_10G;
4759                 break;
4760
4761         case PORT_TYPE_1G:
4762         default:
4763                 val = PT_DRR_WEIGHT_DEFAULT_1G;
4764                 break;
4765         }
4766         nw64(PT_DRR_WT(np->port), val);
4767 }
4768
4769 static int niu_init_hostinfo(struct niu *np)
4770 {
4771         struct niu_parent *parent = np->parent;
4772         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4773         int i, err, num_alt = niu_num_alt_addr(np);
4774         int first_rdc_table = tp->first_table_num;
4775
4776         err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4777         if (err)
4778                 return err;
4779
4780         err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4781         if (err)
4782                 return err;
4783
4784         for (i = 0; i < num_alt; i++) {
4785                 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4786                 if (err)
4787                         return err;
4788         }
4789
4790         return 0;
4791 }
4792
4793 static int niu_rx_channel_reset(struct niu *np, int channel)
4794 {
4795         return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4796                                       RXDMA_CFIG1_RST, 1000, 10,
4797                                       "RXDMA_CFIG1");
4798 }
4799
4800 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4801 {
4802         u64 val;
4803
4804         nw64(RX_LOG_MASK1(channel), 0);
4805         nw64(RX_LOG_VAL1(channel), 0);
4806         nw64(RX_LOG_MASK2(channel), 0);
4807         nw64(RX_LOG_VAL2(channel), 0);
4808         nw64(RX_LOG_PAGE_RELO1(channel), 0);
4809         nw64(RX_LOG_PAGE_RELO2(channel), 0);
4810         nw64(RX_LOG_PAGE_HDL(channel), 0);
4811
4812         val  = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4813         val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4814         nw64(RX_LOG_PAGE_VLD(channel), val);
4815
4816         return 0;
4817 }
4818
4819 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4820 {
4821         u64 val;
4822
4823         val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4824                ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4825                ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4826                ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4827         nw64(RDC_RED_PARA(rp->rx_channel), val);
4828 }
4829
4830 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4831 {
4832         u64 val = 0;
4833
4834         *ret = 0;
4835         switch (rp->rbr_block_size) {
4836         case 4 * 1024:
4837                 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4838                 break;
4839         case 8 * 1024:
4840                 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4841                 break;
4842         case 16 * 1024:
4843                 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4844                 break;
4845         case 32 * 1024:
4846                 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4847                 break;
4848         default:
4849                 return -EINVAL;
4850         }
4851         val |= RBR_CFIG_B_VLD2;
4852         switch (rp->rbr_sizes[2]) {
4853         case 2 * 1024:
4854                 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4855                 break;
4856         case 4 * 1024:
4857                 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4858                 break;
4859         case 8 * 1024:
4860                 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4861                 break;
4862         case 16 * 1024:
4863                 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4864                 break;
4865
4866         default:
4867                 return -EINVAL;
4868         }
4869         val |= RBR_CFIG_B_VLD1;
4870         switch (rp->rbr_sizes[1]) {
4871         case 1 * 1024:
4872                 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4873                 break;
4874         case 2 * 1024:
4875                 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4876                 break;
4877         case 4 * 1024:
4878                 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4879                 break;
4880         case 8 * 1024:
4881                 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4882                 break;
4883
4884         default:
4885                 return -EINVAL;
4886         }
4887         val |= RBR_CFIG_B_VLD0;
4888         switch (rp->rbr_sizes[0]) {
4889         case 256:
4890                 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4891                 break;
4892         case 512:
4893                 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4894                 break;
4895         case 1 * 1024:
4896                 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4897                 break;
4898         case 2 * 1024:
4899                 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4900                 break;
4901
4902         default:
4903                 return -EINVAL;
4904         }
4905
4906         *ret = val;
4907         return 0;
4908 }
4909
4910 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4911 {
4912         u64 val = nr64(RXDMA_CFIG1(channel));
4913         int limit;
4914
4915         if (on)
4916                 val |= RXDMA_CFIG1_EN;
4917         else
4918                 val &= ~RXDMA_CFIG1_EN;
4919         nw64(RXDMA_CFIG1(channel), val);
4920
4921         limit = 1000;
4922         while (--limit > 0) {
4923                 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4924                         break;
4925                 udelay(10);
4926         }
4927         if (limit <= 0)
4928                 return -ENODEV;
4929         return 0;
4930 }
4931
4932 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4933 {
4934         int err, channel = rp->rx_channel;
4935         u64 val;
4936
4937         err = niu_rx_channel_reset(np, channel);
4938         if (err)
4939                 return err;
4940
4941         err = niu_rx_channel_lpage_init(np, channel);
4942         if (err)
4943                 return err;
4944
4945         niu_rx_channel_wred_init(np, rp);
4946
4947         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4948         nw64(RX_DMA_CTL_STAT(channel),
4949              (RX_DMA_CTL_STAT_MEX |
4950               RX_DMA_CTL_STAT_RCRTHRES |
4951               RX_DMA_CTL_STAT_RCRTO |
4952               RX_DMA_CTL_STAT_RBR_EMPTY));
4953         nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4954         nw64(RXDMA_CFIG2(channel),
4955              ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) |
4956               RXDMA_CFIG2_FULL_HDR));
4957         nw64(RBR_CFIG_A(channel),
4958              ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4959              (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4960         err = niu_compute_rbr_cfig_b(rp, &val);
4961         if (err)
4962                 return err;
4963         nw64(RBR_CFIG_B(channel), val);
4964         nw64(RCRCFIG_A(channel),
4965              ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4966              (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4967         nw64(RCRCFIG_B(channel),
4968              ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4969              RCRCFIG_B_ENTOUT |
4970              ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4971
4972         err = niu_enable_rx_channel(np, channel, 1);
4973         if (err)
4974                 return err;
4975
4976         nw64(RBR_KICK(channel), rp->rbr_index);
4977
4978         val = nr64(RX_DMA_CTL_STAT(channel));
4979         val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4980         nw64(RX_DMA_CTL_STAT(channel), val);
4981
4982         return 0;
4983 }
4984
4985 static int niu_init_rx_channels(struct niu *np)
4986 {
4987         unsigned long flags;
4988         u64 seed = jiffies_64;
4989         int err, i;
4990
4991         niu_lock_parent(np, flags);
4992         nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4993         nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4994         niu_unlock_parent(np, flags);
4995
4996         /* XXX RXDMA 32bit mode? XXX */
4997
4998         niu_init_rdc_groups(np);
4999         niu_init_drr_weight(np);
5000
5001         err = niu_init_hostinfo(np);
5002         if (err)
5003                 return err;
5004
5005         for (i = 0; i < np->num_rx_rings; i++) {
5006                 struct rx_ring_info *rp = &np->rx_rings[i];
5007
5008                 err = niu_init_one_rx_channel(np, rp);
5009                 if (err)
5010                         return err;
5011         }
5012
5013         return 0;
5014 }
5015
5016 static int niu_set_ip_frag_rule(struct niu *np)
5017 {
5018         struct niu_parent *parent = np->parent;
5019         struct niu_classifier *cp = &np->clas;
5020         struct niu_tcam_entry *tp;
5021         int index, err;
5022
5023         index = cp->tcam_top;
5024         tp = &parent->tcam[index];
5025
5026         /* Note that the noport bit is the same in both ipv4 and
5027          * ipv6 format TCAM entries.
5028          */
5029         memset(tp, 0, sizeof(*tp));
5030         tp->key[1] = TCAM_V4KEY1_NOPORT;
5031         tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5032         tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5033                           ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5034         err = tcam_write(np, index, tp->key, tp->key_mask);
5035         if (err)
5036                 return err;
5037         err = tcam_assoc_write(np, index, tp->assoc_data);
5038         if (err)
5039                 return err;
5040         tp->valid = 1;
5041         cp->tcam_valid_entries++;
5042
5043         return 0;
5044 }
5045
5046 static int niu_init_classifier_hw(struct niu *np)
5047 {
5048         struct niu_parent *parent = np->parent;
5049         struct niu_classifier *cp = &np->clas;
5050         int i, err;
5051
5052         nw64(H1POLY, cp->h1_init);
5053         nw64(H2POLY, cp->h2_init);
5054
5055         err = niu_init_hostinfo(np);
5056         if (err)
5057                 return err;
5058
5059         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5060                 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5061
5062                 vlan_tbl_write(np, i, np->port,
5063                                vp->vlan_pref, vp->rdc_num);
5064         }
5065
5066         for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5067                 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5068
5069                 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5070                                                 ap->rdc_num, ap->mac_pref);
5071                 if (err)
5072                         return err;
5073         }
5074
5075         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5076                 int index = i - CLASS_CODE_USER_PROG1;
5077
5078                 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5079                 if (err)
5080                         return err;
5081                 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5082                 if (err)
5083                         return err;
5084         }
5085
5086         err = niu_set_ip_frag_rule(np);
5087         if (err)
5088                 return err;
5089
5090         tcam_enable(np, 1);
5091
5092         return 0;
5093 }
5094
5095 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5096 {
5097         nw64(ZCP_RAM_DATA0, data[0]);
5098         nw64(ZCP_RAM_DATA1, data[1]);
5099         nw64(ZCP_RAM_DATA2, data[2]);
5100         nw64(ZCP_RAM_DATA3, data[3]);
5101         nw64(ZCP_RAM_DATA4, data[4]);
5102         nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5103         nw64(ZCP_RAM_ACC,
5104              (ZCP_RAM_ACC_WRITE |
5105               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5106               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5107
5108         return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5109                                    1000, 100);
5110 }
5111
5112 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5113 {
5114         int err;
5115
5116         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5117                                   1000, 100);
5118         if (err) {
5119                 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5120                            (unsigned long long)nr64(ZCP_RAM_ACC));
5121                 return err;
5122         }
5123
5124         nw64(ZCP_RAM_ACC,
5125              (ZCP_RAM_ACC_READ |
5126               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5127               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5128
5129         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5130                                   1000, 100);
5131         if (err) {
5132                 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5133                            (unsigned long long)nr64(ZCP_RAM_ACC));
5134                 return err;
5135         }
5136
5137         data[0] = nr64(ZCP_RAM_DATA0);
5138         data[1] = nr64(ZCP_RAM_DATA1);
5139         data[2] = nr64(ZCP_RAM_DATA2);
5140         data[3] = nr64(ZCP_RAM_DATA3);
5141         data[4] = nr64(ZCP_RAM_DATA4);
5142
5143         return 0;
5144 }
5145
5146 static void niu_zcp_cfifo_reset(struct niu *np)
5147 {
5148         u64 val = nr64(RESET_CFIFO);
5149
5150         val |= RESET_CFIFO_RST(np->port);
5151         nw64(RESET_CFIFO, val);
5152         udelay(10);
5153
5154         val &= ~RESET_CFIFO_RST(np->port);
5155         nw64(RESET_CFIFO, val);
5156 }
5157
5158 static int niu_init_zcp(struct niu *np)
5159 {
5160         u64 data[5], rbuf[5];
5161         int i, max, err;
5162
5163         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5164                 if (np->port == 0 || np->port == 1)
5165                         max = ATLAS_P0_P1_CFIFO_ENTRIES;
5166                 else
5167                         max = ATLAS_P2_P3_CFIFO_ENTRIES;
5168         } else
5169                 max = NIU_CFIFO_ENTRIES;
5170
5171         data[0] = 0;
5172         data[1] = 0;
5173         data[2] = 0;
5174         data[3] = 0;
5175         data[4] = 0;
5176
5177         for (i = 0; i < max; i++) {
5178                 err = niu_zcp_write(np, i, data);
5179                 if (err)
5180                         return err;
5181                 err = niu_zcp_read(np, i, rbuf);
5182                 if (err)
5183                         return err;
5184         }
5185
5186         niu_zcp_cfifo_reset(np);
5187         nw64(CFIFO_ECC(np->port), 0);
5188         nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5189         (void) nr64(ZCP_INT_STAT);
5190         nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5191
5192         return 0;
5193 }
5194
5195 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5196 {
5197         u64 val = nr64_ipp(IPP_CFIG);
5198
5199         nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5200         nw64_ipp(IPP_DFIFO_WR_PTR, index);
5201         nw64_ipp(IPP_DFIFO_WR0, data[0]);
5202         nw64_ipp(IPP_DFIFO_WR1, data[1]);
5203         nw64_ipp(IPP_DFIFO_WR2, data[2]);
5204         nw64_ipp(IPP_DFIFO_WR3, data[3]);
5205         nw64_ipp(IPP_DFIFO_WR4, data[4]);
5206         nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5207 }
5208
5209 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5210 {
5211         nw64_ipp(IPP_DFIFO_RD_PTR, index);
5212         data[0] = nr64_ipp(IPP_DFIFO_RD0);
5213         data[1] = nr64_ipp(IPP_DFIFO_RD1);
5214         data[2] = nr64_ipp(IPP_DFIFO_RD2);
5215         data[3] = nr64_ipp(IPP_DFIFO_RD3);
5216         data[4] = nr64_ipp(IPP_DFIFO_RD4);
5217 }
5218
5219 static int niu_ipp_reset(struct niu *np)
5220 {
5221         return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5222                                           1000, 100, "IPP_CFIG");
5223 }
5224
5225 static int niu_init_ipp(struct niu *np)
5226 {
5227         u64 data[5], rbuf[5], val;
5228         int i, max, err;
5229
5230         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5231                 if (np->port == 0 || np->port == 1)
5232                         max = ATLAS_P0_P1_DFIFO_ENTRIES;
5233                 else
5234                         max = ATLAS_P2_P3_DFIFO_ENTRIES;
5235         } else
5236                 max = NIU_DFIFO_ENTRIES;
5237
5238         data[0] = 0;
5239         data[1] = 0;
5240         data[2] = 0;
5241         data[3] = 0;
5242         data[4] = 0;
5243
5244         for (i = 0; i < max; i++) {
5245                 niu_ipp_write(np, i, data);
5246                 niu_ipp_read(np, i, rbuf);
5247         }
5248
5249         (void) nr64_ipp(IPP_INT_STAT);
5250         (void) nr64_ipp(IPP_INT_STAT);
5251
5252         err = niu_ipp_reset(np);
5253         if (err)
5254                 return err;
5255
5256         (void) nr64_ipp(IPP_PKT_DIS);
5257         (void) nr64_ipp(IPP_BAD_CS_CNT);
5258         (void) nr64_ipp(IPP_ECC);
5259
5260         (void) nr64_ipp(IPP_INT_STAT);
5261
5262         nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5263
5264         val = nr64_ipp(IPP_CFIG);
5265         val &= ~IPP_CFIG_IP_MAX_PKT;
5266         val |= (IPP_CFIG_IPP_ENABLE |
5267                 IPP_CFIG_DFIFO_ECC_EN |
5268                 IPP_CFIG_DROP_BAD_CRC |
5269                 IPP_CFIG_CKSUM_EN |
5270                 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5271         nw64_ipp(IPP_CFIG, val);
5272
5273         return 0;
5274 }
5275
5276 static void niu_handle_led(struct niu *np, int status)
5277 {
5278         u64 val;
5279         val = nr64_mac(XMAC_CONFIG);
5280
5281         if ((np->flags & NIU_FLAGS_10G) != 0 &&
5282             (np->flags & NIU_FLAGS_FIBER) != 0) {
5283                 if (status) {
5284                         val |= XMAC_CONFIG_LED_POLARITY;
5285                         val &= ~XMAC_CONFIG_FORCE_LED_ON;
5286                 } else {
5287                         val |= XMAC_CONFIG_FORCE_LED_ON;
5288                         val &= ~XMAC_CONFIG_LED_POLARITY;
5289                 }
5290         }
5291
5292         nw64_mac(XMAC_CONFIG, val);
5293 }
5294
5295 static void niu_init_xif_xmac(struct niu *np)
5296 {
5297         struct niu_link_config *lp = &np->link_config;
5298         u64 val;
5299
5300         if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5301                 val = nr64(MIF_CONFIG);
5302                 val |= MIF_CONFIG_ATCA_GE;
5303                 nw64(MIF_CONFIG, val);
5304         }
5305
5306         val = nr64_mac(XMAC_CONFIG);
5307         val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5308
5309         val |= XMAC_CONFIG_TX_OUTPUT_EN;
5310
5311         if (lp->loopback_mode == LOOPBACK_MAC) {
5312                 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5313                 val |= XMAC_CONFIG_LOOPBACK;
5314         } else {
5315                 val &= ~XMAC_CONFIG_LOOPBACK;
5316         }
5317
5318         if (np->flags & NIU_FLAGS_10G) {
5319                 val &= ~XMAC_CONFIG_LFS_DISABLE;
5320         } else {
5321                 val |= XMAC_CONFIG_LFS_DISABLE;
5322                 if (!(np->flags & NIU_FLAGS_FIBER) &&
5323                     !(np->flags & NIU_FLAGS_XCVR_SERDES))
5324                         val |= XMAC_CONFIG_1G_PCS_BYPASS;
5325                 else
5326                         val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5327         }
5328
5329         val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5330
5331         if (lp->active_speed == SPEED_100)
5332                 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5333         else
5334                 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5335
5336         nw64_mac(XMAC_CONFIG, val);
5337
5338         val = nr64_mac(XMAC_CONFIG);
5339         val &= ~XMAC_CONFIG_MODE_MASK;
5340         if (np->flags & NIU_FLAGS_10G) {
5341                 val |= XMAC_CONFIG_MODE_XGMII;
5342         } else {
5343                 if (lp->active_speed == SPEED_1000)
5344                         val |= XMAC_CONFIG_MODE_GMII;
5345                 else
5346                         val |= XMAC_CONFIG_MODE_MII;
5347         }
5348
5349         nw64_mac(XMAC_CONFIG, val);
5350 }
5351
5352 static void niu_init_xif_bmac(struct niu *np)
5353 {
5354         struct niu_link_config *lp = &np->link_config;
5355         u64 val;
5356
5357         val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5358
5359         if (lp->loopback_mode == LOOPBACK_MAC)
5360                 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5361         else
5362                 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5363
5364         if (lp->active_speed == SPEED_1000)
5365                 val |= BMAC_XIF_CONFIG_GMII_MODE;
5366         else
5367                 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5368
5369         val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5370                  BMAC_XIF_CONFIG_LED_POLARITY);
5371
5372         if (!(np->flags & NIU_FLAGS_10G) &&
5373             !(np->flags & NIU_FLAGS_FIBER) &&
5374             lp->active_speed == SPEED_100)
5375                 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5376         else
5377                 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5378
5379         nw64_mac(BMAC_XIF_CONFIG, val);
5380 }
5381
5382 static void niu_init_xif(struct niu *np)
5383 {
5384         if (np->flags & NIU_FLAGS_XMAC)
5385                 niu_init_xif_xmac(np);
5386         else
5387                 niu_init_xif_bmac(np);
5388 }
5389
5390 static void niu_pcs_mii_reset(struct niu *np)
5391 {
5392         int limit = 1000;
5393         u64 val = nr64_pcs(PCS_MII_CTL);
5394         val |= PCS_MII_CTL_RST;
5395         nw64_pcs(PCS_MII_CTL, val);
5396         while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5397                 udelay(100);
5398                 val = nr64_pcs(PCS_MII_CTL);
5399         }
5400 }
5401
5402 static void niu_xpcs_reset(struct niu *np)
5403 {
5404         int limit = 1000;
5405         u64 val = nr64_xpcs(XPCS_CONTROL1);
5406         val |= XPCS_CONTROL1_RESET;
5407         nw64_xpcs(XPCS_CONTROL1, val);
5408         while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5409                 udelay(100);
5410                 val = nr64_xpcs(XPCS_CONTROL1);
5411         }
5412 }
5413
5414 static int niu_init_pcs(struct niu *np)
5415 {
5416         struct niu_link_config *lp = &np->link_config;
5417         u64 val;
5418
5419         switch (np->flags & (NIU_FLAGS_10G |
5420                              NIU_FLAGS_FIBER |
5421                              NIU_FLAGS_XCVR_SERDES)) {
5422         case NIU_FLAGS_FIBER:
5423                 /* 1G fiber */
5424                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5425                 nw64_pcs(PCS_DPATH_MODE, 0);
5426                 niu_pcs_mii_reset(np);
5427                 break;
5428
5429         case NIU_FLAGS_10G:
5430         case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5431         case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5432                 /* 10G SERDES */
5433                 if (!(np->flags & NIU_FLAGS_XMAC))
5434                         return -EINVAL;
5435
5436                 /* 10G copper or fiber */
5437                 val = nr64_mac(XMAC_CONFIG);
5438                 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5439                 nw64_mac(XMAC_CONFIG, val);
5440
5441                 niu_xpcs_reset(np);
5442
5443                 val = nr64_xpcs(XPCS_CONTROL1);
5444                 if (lp->loopback_mode == LOOPBACK_PHY)
5445                         val |= XPCS_CONTROL1_LOOPBACK;
5446                 else
5447                         val &= ~XPCS_CONTROL1_LOOPBACK;
5448                 nw64_xpcs(XPCS_CONTROL1, val);
5449
5450                 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5451                 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5452                 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5453                 break;
5454
5455
5456         case NIU_FLAGS_XCVR_SERDES:
5457                 /* 1G SERDES */
5458                 niu_pcs_mii_reset(np);
5459                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5460                 nw64_pcs(PCS_DPATH_MODE, 0);
5461                 break;
5462
5463         case 0:
5464                 /* 1G copper */
5465         case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5466                 /* 1G RGMII FIBER */
5467                 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5468                 niu_pcs_mii_reset(np);
5469                 break;
5470
5471         default:
5472                 return -EINVAL;
5473         }
5474
5475         return 0;
5476 }
5477
5478 static int niu_reset_tx_xmac(struct niu *np)
5479 {
5480         return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5481                                           (XTXMAC_SW_RST_REG_RS |
5482                                            XTXMAC_SW_RST_SOFT_RST),
5483                                           1000, 100, "XTXMAC_SW_RST");
5484 }
5485
5486 static int niu_reset_tx_bmac(struct niu *np)
5487 {
5488         int limit;
5489
5490         nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5491         limit = 1000;
5492         while (--limit >= 0) {
5493                 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5494                         break;
5495                 udelay(100);
5496         }
5497         if (limit < 0) {
5498                 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
5499                         np->port,
5500                         (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5501                 return -ENODEV;
5502         }
5503
5504         return 0;
5505 }
5506
5507 static int niu_reset_tx_mac(struct niu *np)
5508 {
5509         if (np->flags & NIU_FLAGS_XMAC)
5510                 return niu_reset_tx_xmac(np);
5511         else
5512                 return niu_reset_tx_bmac(np);
5513 }
5514
5515 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5516 {
5517         u64 val;
5518
5519         val = nr64_mac(XMAC_MIN);
5520         val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5521                  XMAC_MIN_RX_MIN_PKT_SIZE);
5522         val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5523         val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5524         nw64_mac(XMAC_MIN, val);
5525
5526         nw64_mac(XMAC_MAX, max);
5527
5528         nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5529
5530         val = nr64_mac(XMAC_IPG);
5531         if (np->flags & NIU_FLAGS_10G) {
5532                 val &= ~XMAC_IPG_IPG_XGMII;
5533                 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5534         } else {
5535                 val &= ~XMAC_IPG_IPG_MII_GMII;
5536                 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5537         }
5538         nw64_mac(XMAC_IPG, val);
5539
5540         val = nr64_mac(XMAC_CONFIG);
5541         val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5542                  XMAC_CONFIG_STRETCH_MODE |
5543                  XMAC_CONFIG_VAR_MIN_IPG_EN |
5544                  XMAC_CONFIG_TX_ENABLE);
5545         nw64_mac(XMAC_CONFIG, val);
5546
5547         nw64_mac(TXMAC_FRM_CNT, 0);
5548         nw64_mac(TXMAC_BYTE_CNT, 0);
5549 }
5550
5551 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5552 {
5553         u64 val;
5554
5555         nw64_mac(BMAC_MIN_FRAME, min);
5556         nw64_mac(BMAC_MAX_FRAME, max);
5557
5558         nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5559         nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5560         nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5561
5562         val = nr64_mac(BTXMAC_CONFIG);
5563         val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5564                  BTXMAC_CONFIG_ENABLE);
5565         nw64_mac(BTXMAC_CONFIG, val);
5566 }
5567
5568 static void niu_init_tx_mac(struct niu *np)
5569 {
5570         u64 min, max;
5571
5572         min = 64;
5573         if (np->dev->mtu > ETH_DATA_LEN)
5574                 max = 9216;
5575         else
5576                 max = 1522;
5577
5578         /* The XMAC_MIN register only accepts values for TX min which
5579          * have the low 3 bits cleared.
5580          */
5581         BUG_ON(min & 0x7);
5582
5583         if (np->flags & NIU_FLAGS_XMAC)
5584                 niu_init_tx_xmac(np, min, max);
5585         else
5586                 niu_init_tx_bmac(np, min, max);
5587 }
5588
5589 static int niu_reset_rx_xmac(struct niu *np)
5590 {
5591         int limit;
5592
5593         nw64_mac(XRXMAC_SW_RST,
5594                  XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5595         limit = 1000;
5596         while (--limit >= 0) {
5597                 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5598                                                  XRXMAC_SW_RST_SOFT_RST)))
5599                         break;
5600                 udelay(100);
5601         }
5602         if (limit < 0) {
5603                 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
5604                         np->port,
5605                         (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5606                 return -ENODEV;
5607         }
5608
5609         return 0;
5610 }
5611
5612 static int niu_reset_rx_bmac(struct niu *np)
5613 {
5614         int limit;
5615
5616         nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5617         limit = 1000;
5618         while (--limit >= 0) {
5619                 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5620                         break;
5621                 udelay(100);
5622         }
5623         if (limit < 0) {
5624                 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
5625                         np->port,
5626                         (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5627                 return -ENODEV;
5628         }
5629
5630         return 0;
5631 }
5632
5633 static int niu_reset_rx_mac(struct niu *np)
5634 {
5635         if (np->flags & NIU_FLAGS_XMAC)
5636                 return niu_reset_rx_xmac(np);
5637         else
5638                 return niu_reset_rx_bmac(np);
5639 }
5640
5641 static void niu_init_rx_xmac(struct niu *np)
5642 {
5643         struct niu_parent *parent = np->parent;
5644         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5645         int first_rdc_table = tp->first_table_num;
5646         unsigned long i;
5647         u64 val;
5648
5649         nw64_mac(XMAC_ADD_FILT0, 0);
5650         nw64_mac(XMAC_ADD_FILT1, 0);
5651         nw64_mac(XMAC_ADD_FILT2, 0);
5652         nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5653         nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5654         for (i = 0; i < MAC_NUM_HASH; i++)
5655                 nw64_mac(XMAC_HASH_TBL(i), 0);
5656         nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5657         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5658         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5659
5660         val = nr64_mac(XMAC_CONFIG);
5661         val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5662                  XMAC_CONFIG_PROMISCUOUS |
5663                  XMAC_CONFIG_PROMISC_GROUP |
5664                  XMAC_CONFIG_ERR_CHK_DIS |
5665                  XMAC_CONFIG_RX_CRC_CHK_DIS |
5666                  XMAC_CONFIG_RESERVED_MULTICAST |
5667                  XMAC_CONFIG_RX_CODEV_CHK_DIS |
5668                  XMAC_CONFIG_ADDR_FILTER_EN |
5669                  XMAC_CONFIG_RCV_PAUSE_ENABLE |
5670                  XMAC_CONFIG_STRIP_CRC |
5671                  XMAC_CONFIG_PASS_FLOW_CTRL |
5672                  XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5673         val |= (XMAC_CONFIG_HASH_FILTER_EN);
5674         nw64_mac(XMAC_CONFIG, val);
5675
5676         nw64_mac(RXMAC_BT_CNT, 0);
5677         nw64_mac(RXMAC_BC_FRM_CNT, 0);
5678         nw64_mac(RXMAC_MC_FRM_CNT, 0);
5679         nw64_mac(RXMAC_FRAG_CNT, 0);
5680         nw64_mac(RXMAC_HIST_CNT1, 0);
5681         nw64_mac(RXMAC_HIST_CNT2, 0);
5682         nw64_mac(RXMAC_HIST_CNT3, 0);
5683         nw64_mac(RXMAC_HIST_CNT4, 0);
5684         nw64_mac(RXMAC_HIST_CNT5, 0);
5685         nw64_mac(RXMAC_HIST_CNT6, 0);
5686         nw64_mac(RXMAC_HIST_CNT7, 0);
5687         nw64_mac(RXMAC_MPSZER_CNT, 0);
5688         nw64_mac(RXMAC_CRC_ER_CNT, 0);
5689         nw64_mac(RXMAC_CD_VIO_CNT, 0);
5690         nw64_mac(LINK_FAULT_CNT, 0);
5691 }
5692
5693 static void niu_init_rx_bmac(struct niu *np)
5694 {
5695         struct niu_parent *parent = np->parent;
5696         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5697         int first_rdc_table = tp->first_table_num;
5698         unsigned long i;
5699         u64 val;
5700
5701         nw64_mac(BMAC_ADD_FILT0, 0);
5702         nw64_mac(BMAC_ADD_FILT1, 0);
5703         nw64_mac(BMAC_ADD_FILT2, 0);
5704         nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5705         nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5706         for (i = 0; i < MAC_NUM_HASH; i++)
5707                 nw64_mac(BMAC_HASH_TBL(i), 0);
5708         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5709         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5710         nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5711
5712         val = nr64_mac(BRXMAC_CONFIG);
5713         val &= ~(BRXMAC_CONFIG_ENABLE |
5714                  BRXMAC_CONFIG_STRIP_PAD |
5715                  BRXMAC_CONFIG_STRIP_FCS |
5716                  BRXMAC_CONFIG_PROMISC |
5717                  BRXMAC_CONFIG_PROMISC_GRP |
5718                  BRXMAC_CONFIG_ADDR_FILT_EN |
5719                  BRXMAC_CONFIG_DISCARD_DIS);
5720         val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5721         nw64_mac(BRXMAC_CONFIG, val);
5722
5723         val = nr64_mac(BMAC_ADDR_CMPEN);
5724         val |= BMAC_ADDR_CMPEN_EN0;
5725         nw64_mac(BMAC_ADDR_CMPEN, val);
5726 }
5727
5728 static void niu_init_rx_mac(struct niu *np)
5729 {
5730         niu_set_primary_mac(np, np->dev->dev_addr);
5731
5732         if (np->flags & NIU_FLAGS_XMAC)
5733                 niu_init_rx_xmac(np);
5734         else
5735                 niu_init_rx_bmac(np);
5736 }
5737
5738 static void niu_enable_tx_xmac(struct niu *np, int on)
5739 {
5740         u64 val = nr64_mac(XMAC_CONFIG);
5741
5742         if (on)
5743                 val |= XMAC_CONFIG_TX_ENABLE;
5744         else
5745                 val &= ~XMAC_CONFIG_TX_ENABLE;
5746         nw64_mac(XMAC_CONFIG, val);
5747 }
5748
5749 static void niu_enable_tx_bmac(struct niu *np, int on)
5750 {
5751         u64 val = nr64_mac(BTXMAC_CONFIG);
5752
5753         if (on)
5754                 val |= BTXMAC_CONFIG_ENABLE;
5755         else
5756                 val &= ~BTXMAC_CONFIG_ENABLE;
5757         nw64_mac(BTXMAC_CONFIG, val);
5758 }
5759
5760 static void niu_enable_tx_mac(struct niu *np, int on)
5761 {
5762         if (np->flags & NIU_FLAGS_XMAC)
5763                 niu_enable_tx_xmac(np, on);
5764         else
5765                 niu_enable_tx_bmac(np, on);
5766 }
5767
5768 static void niu_enable_rx_xmac(struct niu *np, int on)
5769 {
5770         u64 val = nr64_mac(XMAC_CONFIG);
5771
5772         val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5773                  XMAC_CONFIG_PROMISCUOUS);
5774
5775         if (np->flags & NIU_FLAGS_MCAST)
5776                 val |= XMAC_CONFIG_HASH_FILTER_EN;
5777         if (np->flags & NIU_FLAGS_PROMISC)
5778                 val |= XMAC_CONFIG_PROMISCUOUS;
5779
5780         if (on)
5781                 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5782         else
5783                 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5784         nw64_mac(XMAC_CONFIG, val);
5785 }
5786
5787 static void niu_enable_rx_bmac(struct niu *np, int on)
5788 {
5789         u64 val = nr64_mac(BRXMAC_CONFIG);
5790
5791         val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5792                  BRXMAC_CONFIG_PROMISC);
5793
5794         if (np->flags & NIU_FLAGS_MCAST)
5795                 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5796         if (np->flags & NIU_FLAGS_PROMISC)
5797                 val |= BRXMAC_CONFIG_PROMISC;
5798
5799         if (on)
5800                 val |= BRXMAC_CONFIG_ENABLE;
5801         else
5802                 val &= ~BRXMAC_CONFIG_ENABLE;
5803         nw64_mac(BRXMAC_CONFIG, val);
5804 }
5805
5806 static void niu_enable_rx_mac(struct niu *np, int on)
5807 {
5808         if (np->flags & NIU_FLAGS_XMAC)
5809                 niu_enable_rx_xmac(np, on);
5810         else
5811                 niu_enable_rx_bmac(np, on);
5812 }
5813
5814 static int niu_init_mac(struct niu *np)
5815 {
5816         int err;
5817
5818         niu_init_xif(np);
5819         err = niu_init_pcs(np);
5820         if (err)
5821                 return err;
5822
5823         err = niu_reset_tx_mac(np);
5824         if (err)
5825                 return err;
5826         niu_init_tx_mac(np);
5827         err = niu_reset_rx_mac(np);
5828         if (err)
5829                 return err;
5830         niu_init_rx_mac(np);
5831
5832         /* This looks hookey but the RX MAC reset we just did will
5833          * undo some of the state we setup in niu_init_tx_mac() so we
5834          * have to call it again.  In particular, the RX MAC reset will
5835          * set the XMAC_MAX register back to it's default value.
5836          */
5837         niu_init_tx_mac(np);
5838         niu_enable_tx_mac(np, 1);
5839
5840         niu_enable_rx_mac(np, 1);
5841
5842         return 0;
5843 }
5844
5845 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5846 {
5847         (void) niu_tx_channel_stop(np, rp->tx_channel);
5848 }
5849
5850 static void niu_stop_tx_channels(struct niu *np)
5851 {
5852         int i;
5853
5854         for (i = 0; i < np->num_tx_rings; i++) {
5855                 struct tx_ring_info *rp = &np->tx_rings[i];
5856
5857                 niu_stop_one_tx_channel(np, rp);
5858         }
5859 }
5860
5861 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5862 {
5863         (void) niu_tx_channel_reset(np, rp->tx_channel);
5864 }
5865
5866 static void niu_reset_tx_channels(struct niu *np)
5867 {
5868         int i;
5869
5870         for (i = 0; i < np->num_tx_rings; i++) {
5871                 struct tx_ring_info *rp = &np->tx_rings[i];
5872
5873                 niu_reset_one_tx_channel(np, rp);
5874         }
5875 }
5876
5877 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5878 {
5879         (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5880 }
5881
5882 static void niu_stop_rx_channels(struct niu *np)
5883 {
5884         int i;
5885
5886         for (i = 0; i < np->num_rx_rings; i++) {
5887                 struct rx_ring_info *rp = &np->rx_rings[i];
5888
5889                 niu_stop_one_rx_channel(np, rp);
5890         }
5891 }
5892
5893 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5894 {
5895         int channel = rp->rx_channel;
5896
5897         (void) niu_rx_channel_reset(np, channel);
5898         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5899         nw64(RX_DMA_CTL_STAT(channel), 0);
5900         (void) niu_enable_rx_channel(np, channel, 0);
5901 }
5902
5903 static void niu_reset_rx_channels(struct niu *np)
5904 {
5905         int i;
5906
5907         for (i = 0; i < np->num_rx_rings; i++) {
5908                 struct rx_ring_info *rp = &np->rx_rings[i];
5909
5910                 niu_reset_one_rx_channel(np, rp);
5911         }
5912 }
5913
5914 static void niu_disable_ipp(struct niu *np)
5915 {
5916         u64 rd, wr, val;
5917         int limit;
5918
5919         rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5920         wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5921         limit = 100;
5922         while (--limit >= 0 && (rd != wr)) {
5923                 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5924                 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5925         }
5926         if (limit < 0 &&
5927             (rd != 0 && wr != 1)) {
5928                 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5929                            (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5930                            (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
5931         }
5932
5933         val = nr64_ipp(IPP_CFIG);
5934         val &= ~(IPP_CFIG_IPP_ENABLE |
5935                  IPP_CFIG_DFIFO_ECC_EN |
5936                  IPP_CFIG_DROP_BAD_CRC |
5937                  IPP_CFIG_CKSUM_EN);
5938         nw64_ipp(IPP_CFIG, val);
5939
5940         (void) niu_ipp_reset(np);
5941 }
5942
5943 static int niu_init_hw(struct niu *np)
5944 {
5945         int i, err;
5946
5947         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
5948         niu_txc_enable_port(np, 1);
5949         niu_txc_port_dma_enable(np, 1);
5950         niu_txc_set_imask(np, 0);
5951
5952         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
5953         for (i = 0; i < np->num_tx_rings; i++) {
5954                 struct tx_ring_info *rp = &np->tx_rings[i];
5955
5956                 err = niu_init_one_tx_channel(np, rp);
5957                 if (err)
5958                         return err;
5959         }
5960
5961         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
5962         err = niu_init_rx_channels(np);
5963         if (err)
5964                 goto out_uninit_tx_channels;
5965
5966         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
5967         err = niu_init_classifier_hw(np);
5968         if (err)
5969                 goto out_uninit_rx_channels;
5970
5971         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
5972         err = niu_init_zcp(np);
5973         if (err)
5974                 goto out_uninit_rx_channels;
5975
5976         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
5977         err = niu_init_ipp(np);
5978         if (err)
5979                 goto out_uninit_rx_channels;
5980
5981         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
5982         err = niu_init_mac(np);
5983         if (err)
5984                 goto out_uninit_ipp;
5985
5986         return 0;
5987
5988 out_uninit_ipp:
5989         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
5990         niu_disable_ipp(np);
5991
5992 out_uninit_rx_channels:
5993         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
5994         niu_stop_rx_channels(np);
5995         niu_reset_rx_channels(np);
5996
5997 out_uninit_tx_channels:
5998         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
5999         niu_stop_tx_channels(np);
6000         niu_reset_tx_channels(np);
6001
6002         return err;
6003 }
6004
6005 static void niu_stop_hw(struct niu *np)
6006 {
6007         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
6008         niu_enable_interrupts(np, 0);
6009
6010         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
6011         niu_enable_rx_mac(np, 0);
6012
6013         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
6014         niu_disable_ipp(np);
6015
6016         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
6017         niu_stop_tx_channels(np);
6018
6019         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
6020         niu_stop_rx_channels(np);
6021
6022         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
6023         niu_reset_tx_channels(np);
6024
6025         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
6026         niu_reset_rx_channels(np);
6027 }
6028
6029 static void niu_set_irq_name(struct niu *np)
6030 {
6031         int port = np->port;
6032         int i, j = 1;
6033
6034         sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6035
6036         if (port == 0) {
6037                 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6038                 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6039                 j = 3;
6040         }
6041
6042         for (i = 0; i < np->num_ldg - j; i++) {
6043                 if (i < np->num_rx_rings)
6044                         sprintf(np->irq_name[i+j], "%s-rx-%d",
6045                                 np->dev->name, i);
6046                 else if (i < np->num_tx_rings + np->num_rx_rings)
6047                         sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6048                                 i - np->num_rx_rings);
6049         }
6050 }
6051
6052 static int niu_request_irq(struct niu *np)
6053 {
6054         int i, j, err;
6055
6056         niu_set_irq_name(np);
6057
6058         err = 0;
6059         for (i = 0; i < np->num_ldg; i++) {
6060                 struct niu_ldg *lp = &np->ldg[i];
6061
6062                 err = request_irq(lp->irq, niu_interrupt,
6063                                   IRQF_SHARED | IRQF_SAMPLE_RANDOM,
6064                                   np->irq_name[i], lp);
6065                 if (err)
6066                         goto out_free_irqs;
6067
6068         }
6069
6070         return 0;
6071
6072 out_free_irqs:
6073         for (j = 0; j < i; j++) {
6074                 struct niu_ldg *lp = &np->ldg[j];
6075
6076                 free_irq(lp->irq, lp);
6077         }
6078         return err;
6079 }
6080
6081 static void niu_free_irq(struct niu *np)
6082 {
6083         int i;
6084
6085         for (i = 0; i < np->num_ldg; i++) {
6086                 struct niu_ldg *lp = &np->ldg[i];
6087
6088                 free_irq(lp->irq, lp);
6089         }
6090 }
6091
6092 static void niu_enable_napi(struct niu *np)
6093 {
6094         int i;
6095
6096         for (i = 0; i < np->num_ldg; i++)
6097                 napi_enable(&np->ldg[i].napi);
6098 }
6099
6100 static void niu_disable_napi(struct niu *np)
6101 {
6102         int i;
6103
6104         for (i = 0; i < np->num_ldg; i++)
6105                 napi_disable(&np->ldg[i].napi);
6106 }
6107
6108 static int niu_open(struct net_device *dev)
6109 {
6110         struct niu *np = netdev_priv(dev);
6111         int err;
6112
6113         netif_carrier_off(dev);
6114
6115         err = niu_alloc_channels(np);
6116         if (err)
6117                 goto out_err;
6118
6119         err = niu_enable_interrupts(np, 0);
6120         if (err)
6121                 goto out_free_channels;
6122
6123         err = niu_request_irq(np);
6124         if (err)
6125                 goto out_free_channels;
6126
6127         niu_enable_napi(np);
6128
6129         spin_lock_irq(&np->lock);
6130
6131         err = niu_init_hw(np);
6132         if (!err) {
6133                 init_timer(&np->timer);
6134                 np->timer.expires = jiffies + HZ;
6135                 np->timer.data = (unsigned long) np;
6136                 np->timer.function = niu_timer;
6137
6138                 err = niu_enable_interrupts(np, 1);
6139                 if (err)
6140                         niu_stop_hw(np);
6141         }
6142
6143         spin_unlock_irq(&np->lock);
6144
6145         if (err) {
6146                 niu_disable_napi(np);
6147                 goto out_free_irq;
6148         }
6149
6150         netif_tx_start_all_queues(dev);
6151
6152         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6153                 netif_carrier_on(dev);
6154
6155         add_timer(&np->timer);
6156
6157         return 0;
6158
6159 out_free_irq:
6160         niu_free_irq(np);
6161
6162 out_free_channels:
6163         niu_free_channels(np);
6164
6165 out_err:
6166         return err;
6167 }
6168
6169 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6170 {
6171         cancel_work_sync(&np->reset_task);
6172
6173         niu_disable_napi(np);
6174         netif_tx_stop_all_queues(dev);
6175
6176         del_timer_sync(&np->timer);
6177
6178         spin_lock_irq(&np->lock);
6179
6180         niu_stop_hw(np);
6181
6182         spin_unlock_irq(&np->lock);
6183 }
6184
6185 static int niu_close(struct net_device *dev)
6186 {
6187         struct niu *np = netdev_priv(dev);
6188
6189         niu_full_shutdown(np, dev);
6190
6191         niu_free_irq(np);
6192
6193         niu_free_channels(np);
6194
6195         niu_handle_led(np, 0);
6196
6197         return 0;
6198 }
6199
6200 static void niu_sync_xmac_stats(struct niu *np)
6201 {
6202         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6203
6204         mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6205         mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6206
6207         mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6208         mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6209         mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6210         mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6211         mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6212         mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6213         mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6214         mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6215         mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6216         mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6217         mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6218         mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6219         mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6220         mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6221         mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6222         mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6223 }
6224
6225 static void niu_sync_bmac_stats(struct niu *np)
6226 {
6227         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6228
6229         mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6230         mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6231
6232         mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6233         mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6234         mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6235         mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6236 }
6237
6238 static void niu_sync_mac_stats(struct niu *np)
6239 {
6240         if (np->flags & NIU_FLAGS_XMAC)
6241                 niu_sync_xmac_stats(np);
6242         else
6243                 niu_sync_bmac_stats(np);
6244 }
6245
6246 static void niu_get_rx_stats(struct niu *np)
6247 {
6248         unsigned long pkts, dropped, errors, bytes;
6249         int i;
6250
6251         pkts = dropped = errors = bytes = 0;
6252         for (i = 0; i < np->num_rx_rings; i++) {
6253                 struct rx_ring_info *rp = &np->rx_rings[i];
6254
6255                 niu_sync_rx_discard_stats(np, rp, 0);
6256
6257                 pkts += rp->rx_packets;
6258                 bytes += rp->rx_bytes;
6259                 dropped += rp->rx_dropped;
6260                 errors += rp->rx_errors;
6261         }
6262         np->dev->stats.rx_packets = pkts;
6263         np->dev->stats.rx_bytes = bytes;
6264         np->dev->stats.rx_dropped = dropped;
6265         np->dev->stats.rx_errors = errors;
6266 }
6267
6268 static void niu_get_tx_stats(struct niu *np)
6269 {
6270         unsigned long pkts, errors, bytes;
6271         int i;
6272
6273         pkts = errors = bytes = 0;
6274         for (i = 0; i < np->num_tx_rings; i++) {
6275                 struct tx_ring_info *rp = &np->tx_rings[i];
6276
6277                 pkts += rp->tx_packets;
6278                 bytes += rp->tx_bytes;
6279                 errors += rp->tx_errors;
6280         }
6281         np->dev->stats.tx_packets = pkts;
6282         np->dev->stats.tx_bytes = bytes;
6283         np->dev->stats.tx_errors = errors;
6284 }
6285
6286 static struct net_device_stats *niu_get_stats(struct net_device *dev)
6287 {
6288         struct niu *np = netdev_priv(dev);
6289
6290         niu_get_rx_stats(np);
6291         niu_get_tx_stats(np);
6292
6293         return &dev->stats;
6294 }
6295
6296 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6297 {
6298         int i;
6299
6300         for (i = 0; i < 16; i++)
6301                 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6302 }
6303
6304 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6305 {
6306         int i;
6307
6308         for (i = 0; i < 16; i++)
6309                 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6310 }
6311
6312 static void niu_load_hash(struct niu *np, u16 *hash)
6313 {
6314         if (np->flags & NIU_FLAGS_XMAC)
6315                 niu_load_hash_xmac(np, hash);
6316         else
6317                 niu_load_hash_bmac(np, hash);
6318 }
6319
6320 static void niu_set_rx_mode(struct net_device *dev)
6321 {
6322         struct niu *np = netdev_priv(dev);
6323         int i, alt_cnt, err;
6324         struct netdev_hw_addr *ha;
6325         unsigned long flags;
6326         u16 hash[16] = { 0, };
6327
6328         spin_lock_irqsave(&np->lock, flags);
6329         niu_enable_rx_mac(np, 0);
6330
6331         np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6332         if (dev->flags & IFF_PROMISC)
6333                 np->flags |= NIU_FLAGS_PROMISC;
6334         if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
6335                 np->flags |= NIU_FLAGS_MCAST;
6336
6337         alt_cnt = netdev_uc_count(dev);
6338         if (alt_cnt > niu_num_alt_addr(np)) {
6339                 alt_cnt = 0;
6340                 np->flags |= NIU_FLAGS_PROMISC;
6341         }
6342
6343         if (alt_cnt) {
6344                 int index = 0;
6345
6346                 netdev_for_each_uc_addr(ha, dev) {
6347                         err = niu_set_alt_mac(np, index, ha->addr);
6348                         if (err)
6349                                 netdev_warn(dev, "Error %d adding alt mac %d\n",
6350                                             err, index);
6351                         err = niu_enable_alt_mac(np, index, 1);
6352                         if (err)
6353                                 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6354                                             err, index);
6355
6356                         index++;
6357                 }
6358         } else {
6359                 int alt_start;
6360                 if (np->flags & NIU_FLAGS_XMAC)
6361                         alt_start = 0;
6362                 else
6363                         alt_start = 1;
6364                 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6365                         err = niu_enable_alt_mac(np, i, 0);
6366                         if (err)
6367                                 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6368                                             err, i);
6369                 }
6370         }
6371         if (dev->flags & IFF_ALLMULTI) {
6372                 for (i = 0; i < 16; i++)
6373                         hash[i] = 0xffff;
6374         } else if (!netdev_mc_empty(dev)) {
6375                 netdev_for_each_mc_addr(ha, dev) {
6376                         u32 crc = ether_crc_le(ETH_ALEN, ha->addr);
6377
6378                         crc >>= 24;
6379        &