myri10ge: add MODULE_DEVICE_TABLE
[linux-2.6.git] / drivers / net / myri10ge / myri10ge.c
1 /*************************************************************************
2  * myri10ge.c: Myricom Myri-10G Ethernet driver.
3  *
4  * Copyright (C) 2005 - 2009 Myricom, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16  *    may be used to endorse or promote products derived from this software
17  *    without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  *
31  *
32  * If the eeprom on your board is not recent enough, you will need to get a
33  * newer firmware image at:
34  *   http://www.myri.com/scs/download-Myri10GE.html
35  *
36  * Contact Information:
37  *   <help@myri.com>
38  *   Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39  *************************************************************************/
40
41 #include <linux/tcp.h>
42 #include <linux/netdevice.h>
43 #include <linux/skbuff.h>
44 #include <linux/string.h>
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/etherdevice.h>
49 #include <linux/if_ether.h>
50 #include <linux/if_vlan.h>
51 #include <linux/inet_lro.h>
52 #include <linux/dca.h>
53 #include <linux/ip.h>
54 #include <linux/inet.h>
55 #include <linux/in.h>
56 #include <linux/ethtool.h>
57 #include <linux/firmware.h>
58 #include <linux/delay.h>
59 #include <linux/timer.h>
60 #include <linux/vmalloc.h>
61 #include <linux/crc32.h>
62 #include <linux/moduleparam.h>
63 #include <linux/io.h>
64 #include <linux/log2.h>
65 #include <net/checksum.h>
66 #include <net/ip.h>
67 #include <net/tcp.h>
68 #include <asm/byteorder.h>
69 #include <asm/io.h>
70 #include <asm/processor.h>
71 #ifdef CONFIG_MTRR
72 #include <asm/mtrr.h>
73 #endif
74
75 #include "myri10ge_mcp.h"
76 #include "myri10ge_mcp_gen_header.h"
77
78 #define MYRI10GE_VERSION_STR "1.4.4-1.412"
79
80 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81 MODULE_AUTHOR("Maintainer: help@myri.com");
82 MODULE_VERSION(MYRI10GE_VERSION_STR);
83 MODULE_LICENSE("Dual BSD/GPL");
84
85 #define MYRI10GE_MAX_ETHER_MTU 9014
86
87 #define MYRI10GE_ETH_STOPPED 0
88 #define MYRI10GE_ETH_STOPPING 1
89 #define MYRI10GE_ETH_STARTING 2
90 #define MYRI10GE_ETH_RUNNING 3
91 #define MYRI10GE_ETH_OPEN_FAILED 4
92
93 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
94 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
95 #define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96 #define MYRI10GE_LRO_MAX_PKTS 64
97
98 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
99 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
100
101 #define MYRI10GE_ALLOC_ORDER 0
102 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
104
105 #define MYRI10GE_MAX_SLICES 32
106
107 struct myri10ge_rx_buffer_state {
108         struct page *page;
109         int page_offset;
110          DECLARE_PCI_UNMAP_ADDR(bus)
111          DECLARE_PCI_UNMAP_LEN(len)
112 };
113
114 struct myri10ge_tx_buffer_state {
115         struct sk_buff *skb;
116         int last;
117          DECLARE_PCI_UNMAP_ADDR(bus)
118          DECLARE_PCI_UNMAP_LEN(len)
119 };
120
121 struct myri10ge_cmd {
122         u32 data0;
123         u32 data1;
124         u32 data2;
125 };
126
127 struct myri10ge_rx_buf {
128         struct mcp_kreq_ether_recv __iomem *lanai;      /* lanai ptr for recv ring */
129         struct mcp_kreq_ether_recv *shadow;     /* host shadow of recv ring */
130         struct myri10ge_rx_buffer_state *info;
131         struct page *page;
132         dma_addr_t bus;
133         int page_offset;
134         int cnt;
135         int fill_cnt;
136         int alloc_fail;
137         int mask;               /* number of rx slots -1 */
138         int watchdog_needed;
139 };
140
141 struct myri10ge_tx_buf {
142         struct mcp_kreq_ether_send __iomem *lanai;      /* lanai ptr for sendq */
143         __be32 __iomem *send_go;        /* "go" doorbell ptr */
144         __be32 __iomem *send_stop;      /* "stop" doorbell ptr */
145         struct mcp_kreq_ether_send *req_list;   /* host shadow of sendq */
146         char *req_bytes;
147         struct myri10ge_tx_buffer_state *info;
148         int mask;               /* number of transmit slots -1  */
149         int req ____cacheline_aligned;  /* transmit slots submitted     */
150         int pkt_start;          /* packets started */
151         int stop_queue;
152         int linearized;
153         int done ____cacheline_aligned; /* transmit slots completed     */
154         int pkt_done;           /* packets completed */
155         int wake_queue;
156         int queue_active;
157 };
158
159 struct myri10ge_rx_done {
160         struct mcp_slot *entry;
161         dma_addr_t bus;
162         int cnt;
163         int idx;
164         struct net_lro_mgr lro_mgr;
165         struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
166 };
167
168 struct myri10ge_slice_netstats {
169         unsigned long rx_packets;
170         unsigned long tx_packets;
171         unsigned long rx_bytes;
172         unsigned long tx_bytes;
173         unsigned long rx_dropped;
174         unsigned long tx_dropped;
175 };
176
177 struct myri10ge_slice_state {
178         struct myri10ge_tx_buf tx;      /* transmit ring        */
179         struct myri10ge_rx_buf rx_small;
180         struct myri10ge_rx_buf rx_big;
181         struct myri10ge_rx_done rx_done;
182         struct net_device *dev;
183         struct napi_struct napi;
184         struct myri10ge_priv *mgp;
185         struct myri10ge_slice_netstats stats;
186         __be32 __iomem *irq_claim;
187         struct mcp_irq_data *fw_stats;
188         dma_addr_t fw_stats_bus;
189         int watchdog_tx_done;
190         int watchdog_tx_req;
191 #ifdef CONFIG_MYRI10GE_DCA
192         int cached_dca_tag;
193         int cpu;
194         __be32 __iomem *dca_tag;
195 #endif
196         char irq_desc[32];
197 };
198
199 struct myri10ge_priv {
200         struct myri10ge_slice_state *ss;
201         int tx_boundary;        /* boundary transmits cannot cross */
202         int num_slices;
203         int running;            /* running?             */
204         int csum_flag;          /* rx_csums?            */
205         int small_bytes;
206         int big_bytes;
207         int max_intr_slots;
208         struct net_device *dev;
209         struct net_device_stats stats;
210         spinlock_t stats_lock;
211         u8 __iomem *sram;
212         int sram_size;
213         unsigned long board_span;
214         unsigned long iomem_base;
215         __be32 __iomem *irq_deassert;
216         char *mac_addr_string;
217         struct mcp_cmd_response *cmd;
218         dma_addr_t cmd_bus;
219         struct pci_dev *pdev;
220         int msi_enabled;
221         int msix_enabled;
222         struct msix_entry *msix_vectors;
223 #ifdef CONFIG_MYRI10GE_DCA
224         int dca_enabled;
225 #endif
226         u32 link_state;
227         unsigned int rdma_tags_available;
228         int intr_coal_delay;
229         __be32 __iomem *intr_coal_delay_ptr;
230         int mtrr;
231         int wc_enabled;
232         int down_cnt;
233         wait_queue_head_t down_wq;
234         struct work_struct watchdog_work;
235         struct timer_list watchdog_timer;
236         int watchdog_resets;
237         int watchdog_pause;
238         int pause;
239         char *fw_name;
240         char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
241         char *product_code_string;
242         char fw_version[128];
243         int fw_ver_major;
244         int fw_ver_minor;
245         int fw_ver_tiny;
246         int adopted_rx_filter_bug;
247         u8 mac_addr[6];         /* eeprom mac address */
248         unsigned long serial_number;
249         int vendor_specific_offset;
250         int fw_multicast_support;
251         unsigned long features;
252         u32 max_tso6;
253         u32 read_dma;
254         u32 write_dma;
255         u32 read_write_dma;
256         u32 link_changes;
257         u32 msg_enable;
258         unsigned int board_number;
259 };
260
261 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
262 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
263 static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
264 static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
265
266 static char *myri10ge_fw_name = NULL;
267 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
268 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
269
270 #define MYRI10GE_MAX_BOARDS 8
271 static char *myri10ge_fw_names[MYRI10GE_MAX_BOARDS] =
272     {[0...(MYRI10GE_MAX_BOARDS - 1)] = NULL };
273 module_param_array_named(myri10ge_fw_names, myri10ge_fw_names, charp, NULL,
274                          0444);
275 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image names per board");
276
277 static int myri10ge_ecrc_enable = 1;
278 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
279 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
280
281 static int myri10ge_small_bytes = -1;   /* -1 == auto */
282 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
283 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
284
285 static int myri10ge_msi = 1;    /* enable msi by default */
286 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
287 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
288
289 static int myri10ge_intr_coal_delay = 75;
290 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
291 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
292
293 static int myri10ge_flow_control = 1;
294 module_param(myri10ge_flow_control, int, S_IRUGO);
295 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
296
297 static int myri10ge_deassert_wait = 1;
298 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
299 MODULE_PARM_DESC(myri10ge_deassert_wait,
300                  "Wait when deasserting legacy interrupts");
301
302 static int myri10ge_force_firmware = 0;
303 module_param(myri10ge_force_firmware, int, S_IRUGO);
304 MODULE_PARM_DESC(myri10ge_force_firmware,
305                  "Force firmware to assume aligned completions");
306
307 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
308 module_param(myri10ge_initial_mtu, int, S_IRUGO);
309 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
310
311 static int myri10ge_napi_weight = 64;
312 module_param(myri10ge_napi_weight, int, S_IRUGO);
313 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
314
315 static int myri10ge_watchdog_timeout = 1;
316 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
317 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
318
319 static int myri10ge_max_irq_loops = 1048576;
320 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
321 MODULE_PARM_DESC(myri10ge_max_irq_loops,
322                  "Set stuck legacy IRQ detection threshold");
323
324 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
325
326 static int myri10ge_debug = -1; /* defaults above */
327 module_param(myri10ge_debug, int, 0);
328 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
329
330 static int myri10ge_lro = 1;
331 module_param(myri10ge_lro, int, S_IRUGO);
332 MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload");
333
334 static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
335 module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
336 MODULE_PARM_DESC(myri10ge_lro_max_pkts,
337                  "Number of LRO packets to be aggregated");
338
339 static int myri10ge_fill_thresh = 256;
340 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
341 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
342
343 static int myri10ge_reset_recover = 1;
344
345 static int myri10ge_max_slices = 1;
346 module_param(myri10ge_max_slices, int, S_IRUGO);
347 MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
348
349 static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
350 module_param(myri10ge_rss_hash, int, S_IRUGO);
351 MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
352
353 static int myri10ge_dca = 1;
354 module_param(myri10ge_dca, int, S_IRUGO);
355 MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
356
357 #define MYRI10GE_FW_OFFSET 1024*1024
358 #define MYRI10GE_HIGHPART_TO_U32(X) \
359 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
360 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
361
362 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
363
364 static void myri10ge_set_multicast_list(struct net_device *dev);
365 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
366
367 static inline void put_be32(__be32 val, __be32 __iomem * p)
368 {
369         __raw_writel((__force __u32) val, (__force void __iomem *)p);
370 }
371
372 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev);
373
374 static int
375 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
376                   struct myri10ge_cmd *data, int atomic)
377 {
378         struct mcp_cmd *buf;
379         char buf_bytes[sizeof(*buf) + 8];
380         struct mcp_cmd_response *response = mgp->cmd;
381         char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
382         u32 dma_low, dma_high, result, value;
383         int sleep_total = 0;
384
385         /* ensure buf is aligned to 8 bytes */
386         buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
387
388         buf->data0 = htonl(data->data0);
389         buf->data1 = htonl(data->data1);
390         buf->data2 = htonl(data->data2);
391         buf->cmd = htonl(cmd);
392         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
393         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
394
395         buf->response_addr.low = htonl(dma_low);
396         buf->response_addr.high = htonl(dma_high);
397         response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
398         mb();
399         myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
400
401         /* wait up to 15ms. Longest command is the DMA benchmark,
402          * which is capped at 5ms, but runs from a timeout handler
403          * that runs every 7.8ms. So a 15ms timeout leaves us with
404          * a 2.2ms margin
405          */
406         if (atomic) {
407                 /* if atomic is set, do not sleep,
408                  * and try to get the completion quickly
409                  * (1ms will be enough for those commands) */
410                 for (sleep_total = 0;
411                      sleep_total < 1000
412                      && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
413                      sleep_total += 10) {
414                         udelay(10);
415                         mb();
416                 }
417         } else {
418                 /* use msleep for most command */
419                 for (sleep_total = 0;
420                      sleep_total < 15
421                      && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
422                      sleep_total++)
423                         msleep(1);
424         }
425
426         result = ntohl(response->result);
427         value = ntohl(response->data);
428         if (result != MYRI10GE_NO_RESPONSE_RESULT) {
429                 if (result == 0) {
430                         data->data0 = value;
431                         return 0;
432                 } else if (result == MXGEFW_CMD_UNKNOWN) {
433                         return -ENOSYS;
434                 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
435                         return -E2BIG;
436                 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
437                            cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
438                            (data->
439                             data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
440                            0) {
441                         return -ERANGE;
442                 } else {
443                         dev_err(&mgp->pdev->dev,
444                                 "command %d failed, result = %d\n",
445                                 cmd, result);
446                         return -ENXIO;
447                 }
448         }
449
450         dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
451                 cmd, result);
452         return -EAGAIN;
453 }
454
455 /*
456  * The eeprom strings on the lanaiX have the format
457  * SN=x\0
458  * MAC=x:x:x:x:x:x\0
459  * PT:ddd mmm xx xx:xx:xx xx\0
460  * PV:ddd mmm xx xx:xx:xx xx\0
461  */
462 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
463 {
464         char *ptr, *limit;
465         int i;
466
467         ptr = mgp->eeprom_strings;
468         limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
469
470         while (*ptr != '\0' && ptr < limit) {
471                 if (memcmp(ptr, "MAC=", 4) == 0) {
472                         ptr += 4;
473                         mgp->mac_addr_string = ptr;
474                         for (i = 0; i < 6; i++) {
475                                 if ((ptr + 2) > limit)
476                                         goto abort;
477                                 mgp->mac_addr[i] =
478                                     simple_strtoul(ptr, &ptr, 16);
479                                 ptr += 1;
480                         }
481                 }
482                 if (memcmp(ptr, "PC=", 3) == 0) {
483                         ptr += 3;
484                         mgp->product_code_string = ptr;
485                 }
486                 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
487                         ptr += 3;
488                         mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
489                 }
490                 while (ptr < limit && *ptr++) ;
491         }
492
493         return 0;
494
495 abort:
496         dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
497         return -ENXIO;
498 }
499
500 /*
501  * Enable or disable periodic RDMAs from the host to make certain
502  * chipsets resend dropped PCIe messages
503  */
504
505 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
506 {
507         char __iomem *submit;
508         __be32 buf[16] __attribute__ ((__aligned__(8)));
509         u32 dma_low, dma_high;
510         int i;
511
512         /* clear confirmation addr */
513         mgp->cmd->data = 0;
514         mb();
515
516         /* send a rdma command to the PCIe engine, and wait for the
517          * response in the confirmation address.  The firmware should
518          * write a -1 there to indicate it is alive and well
519          */
520         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
521         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
522
523         buf[0] = htonl(dma_high);       /* confirm addr MSW */
524         buf[1] = htonl(dma_low);        /* confirm addr LSW */
525         buf[2] = MYRI10GE_NO_CONFIRM_DATA;      /* confirm data */
526         buf[3] = htonl(dma_high);       /* dummy addr MSW */
527         buf[4] = htonl(dma_low);        /* dummy addr LSW */
528         buf[5] = htonl(enable); /* enable? */
529
530         submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
531
532         myri10ge_pio_copy(submit, &buf, sizeof(buf));
533         for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
534                 msleep(1);
535         if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
536                 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
537                         (enable ? "enable" : "disable"));
538 }
539
540 static int
541 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
542                            struct mcp_gen_header *hdr)
543 {
544         struct device *dev = &mgp->pdev->dev;
545
546         /* check firmware type */
547         if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
548                 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
549                 return -EINVAL;
550         }
551
552         /* save firmware version for ethtool */
553         strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
554
555         sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
556                &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
557
558         if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
559               && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
560                 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
561                 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
562                         MXGEFW_VERSION_MINOR);
563                 return -EINVAL;
564         }
565         return 0;
566 }
567
568 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
569 {
570         unsigned crc, reread_crc;
571         const struct firmware *fw;
572         struct device *dev = &mgp->pdev->dev;
573         unsigned char *fw_readback;
574         struct mcp_gen_header *hdr;
575         size_t hdr_offset;
576         int status;
577         unsigned i;
578
579         if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
580                 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
581                         mgp->fw_name);
582                 status = -EINVAL;
583                 goto abort_with_nothing;
584         }
585
586         /* check size */
587
588         if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
589             fw->size < MCP_HEADER_PTR_OFFSET + 4) {
590                 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
591                 status = -EINVAL;
592                 goto abort_with_fw;
593         }
594
595         /* check id */
596         hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
597         if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
598                 dev_err(dev, "Bad firmware file\n");
599                 status = -EINVAL;
600                 goto abort_with_fw;
601         }
602         hdr = (void *)(fw->data + hdr_offset);
603
604         status = myri10ge_validate_firmware(mgp, hdr);
605         if (status != 0)
606                 goto abort_with_fw;
607
608         crc = crc32(~0, fw->data, fw->size);
609         for (i = 0; i < fw->size; i += 256) {
610                 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
611                                   fw->data + i,
612                                   min(256U, (unsigned)(fw->size - i)));
613                 mb();
614                 readb(mgp->sram);
615         }
616         fw_readback = vmalloc(fw->size);
617         if (!fw_readback) {
618                 status = -ENOMEM;
619                 goto abort_with_fw;
620         }
621         /* corruption checking is good for parity recovery and buggy chipset */
622         memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
623         reread_crc = crc32(~0, fw_readback, fw->size);
624         vfree(fw_readback);
625         if (crc != reread_crc) {
626                 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
627                         (unsigned)fw->size, reread_crc, crc);
628                 status = -EIO;
629                 goto abort_with_fw;
630         }
631         *size = (u32) fw->size;
632
633 abort_with_fw:
634         release_firmware(fw);
635
636 abort_with_nothing:
637         return status;
638 }
639
640 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
641 {
642         struct mcp_gen_header *hdr;
643         struct device *dev = &mgp->pdev->dev;
644         const size_t bytes = sizeof(struct mcp_gen_header);
645         size_t hdr_offset;
646         int status;
647
648         /* find running firmware header */
649         hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
650
651         if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
652                 dev_err(dev, "Running firmware has bad header offset (%d)\n",
653                         (int)hdr_offset);
654                 return -EIO;
655         }
656
657         /* copy header of running firmware from SRAM to host memory to
658          * validate firmware */
659         hdr = kmalloc(bytes, GFP_KERNEL);
660         if (hdr == NULL) {
661                 dev_err(dev, "could not malloc firmware hdr\n");
662                 return -ENOMEM;
663         }
664         memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
665         status = myri10ge_validate_firmware(mgp, hdr);
666         kfree(hdr);
667
668         /* check to see if adopted firmware has bug where adopting
669          * it will cause broadcasts to be filtered unless the NIC
670          * is kept in ALLMULTI mode */
671         if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
672             mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
673                 mgp->adopted_rx_filter_bug = 1;
674                 dev_warn(dev, "Adopting fw %d.%d.%d: "
675                          "working around rx filter bug\n",
676                          mgp->fw_ver_major, mgp->fw_ver_minor,
677                          mgp->fw_ver_tiny);
678         }
679         return status;
680 }
681
682 static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
683 {
684         struct myri10ge_cmd cmd;
685         int status;
686
687         /* probe for IPv6 TSO support */
688         mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
689         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
690                                    &cmd, 0);
691         if (status == 0) {
692                 mgp->max_tso6 = cmd.data0;
693                 mgp->features |= NETIF_F_TSO6;
694         }
695
696         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
697         if (status != 0) {
698                 dev_err(&mgp->pdev->dev,
699                         "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
700                 return -ENXIO;
701         }
702
703         mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
704
705         return 0;
706 }
707
708 static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
709 {
710         char __iomem *submit;
711         __be32 buf[16] __attribute__ ((__aligned__(8)));
712         u32 dma_low, dma_high, size;
713         int status, i;
714
715         size = 0;
716         status = myri10ge_load_hotplug_firmware(mgp, &size);
717         if (status) {
718                 if (!adopt)
719                         return status;
720                 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
721
722                 /* Do not attempt to adopt firmware if there
723                  * was a bad crc */
724                 if (status == -EIO)
725                         return status;
726
727                 status = myri10ge_adopt_running_firmware(mgp);
728                 if (status != 0) {
729                         dev_err(&mgp->pdev->dev,
730                                 "failed to adopt running firmware\n");
731                         return status;
732                 }
733                 dev_info(&mgp->pdev->dev,
734                          "Successfully adopted running firmware\n");
735                 if (mgp->tx_boundary == 4096) {
736                         dev_warn(&mgp->pdev->dev,
737                                  "Using firmware currently running on NIC"
738                                  ".  For optimal\n");
739                         dev_warn(&mgp->pdev->dev,
740                                  "performance consider loading optimized "
741                                  "firmware\n");
742                         dev_warn(&mgp->pdev->dev, "via hotplug\n");
743                 }
744
745                 mgp->fw_name = "adopted";
746                 mgp->tx_boundary = 2048;
747                 myri10ge_dummy_rdma(mgp, 1);
748                 status = myri10ge_get_firmware_capabilities(mgp);
749                 return status;
750         }
751
752         /* clear confirmation addr */
753         mgp->cmd->data = 0;
754         mb();
755
756         /* send a reload command to the bootstrap MCP, and wait for the
757          *  response in the confirmation address.  The firmware should
758          * write a -1 there to indicate it is alive and well
759          */
760         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
761         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
762
763         buf[0] = htonl(dma_high);       /* confirm addr MSW */
764         buf[1] = htonl(dma_low);        /* confirm addr LSW */
765         buf[2] = MYRI10GE_NO_CONFIRM_DATA;      /* confirm data */
766
767         /* FIX: All newest firmware should un-protect the bottom of
768          * the sram before handoff. However, the very first interfaces
769          * do not. Therefore the handoff copy must skip the first 8 bytes
770          */
771         buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
772         buf[4] = htonl(size - 8);       /* length of code */
773         buf[5] = htonl(8);      /* where to copy to */
774         buf[6] = htonl(0);      /* where to jump to */
775
776         submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
777
778         myri10ge_pio_copy(submit, &buf, sizeof(buf));
779         mb();
780         msleep(1);
781         mb();
782         i = 0;
783         while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
784                 msleep(1 << i);
785                 i++;
786         }
787         if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
788                 dev_err(&mgp->pdev->dev, "handoff failed\n");
789                 return -ENXIO;
790         }
791         myri10ge_dummy_rdma(mgp, 1);
792         status = myri10ge_get_firmware_capabilities(mgp);
793
794         return status;
795 }
796
797 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
798 {
799         struct myri10ge_cmd cmd;
800         int status;
801
802         cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
803                      | (addr[2] << 8) | addr[3]);
804
805         cmd.data1 = ((addr[4] << 8) | (addr[5]));
806
807         status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
808         return status;
809 }
810
811 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
812 {
813         struct myri10ge_cmd cmd;
814         int status, ctl;
815
816         ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
817         status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
818
819         if (status) {
820                 printk(KERN_ERR
821                        "myri10ge: %s: Failed to set flow control mode\n",
822                        mgp->dev->name);
823                 return status;
824         }
825         mgp->pause = pause;
826         return 0;
827 }
828
829 static void
830 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
831 {
832         struct myri10ge_cmd cmd;
833         int status, ctl;
834
835         ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
836         status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
837         if (status)
838                 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
839                        mgp->dev->name);
840 }
841
842 static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
843 {
844         struct myri10ge_cmd cmd;
845         int status;
846         u32 len;
847         struct page *dmatest_page;
848         dma_addr_t dmatest_bus;
849         char *test = " ";
850
851         dmatest_page = alloc_page(GFP_KERNEL);
852         if (!dmatest_page)
853                 return -ENOMEM;
854         dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
855                                    DMA_BIDIRECTIONAL);
856
857         /* Run a small DMA test.
858          * The magic multipliers to the length tell the firmware
859          * to do DMA read, write, or read+write tests.  The
860          * results are returned in cmd.data0.  The upper 16
861          * bits or the return is the number of transfers completed.
862          * The lower 16 bits is the time in 0.5us ticks that the
863          * transfers took to complete.
864          */
865
866         len = mgp->tx_boundary;
867
868         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
869         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
870         cmd.data2 = len * 0x10000;
871         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
872         if (status != 0) {
873                 test = "read";
874                 goto abort;
875         }
876         mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
877         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
878         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
879         cmd.data2 = len * 0x1;
880         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
881         if (status != 0) {
882                 test = "write";
883                 goto abort;
884         }
885         mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
886
887         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
888         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
889         cmd.data2 = len * 0x10001;
890         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
891         if (status != 0) {
892                 test = "read/write";
893                 goto abort;
894         }
895         mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
896             (cmd.data0 & 0xffff);
897
898 abort:
899         pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
900         put_page(dmatest_page);
901
902         if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
903                 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
904                          test, status);
905
906         return status;
907 }
908
909 static int myri10ge_reset(struct myri10ge_priv *mgp)
910 {
911         struct myri10ge_cmd cmd;
912         struct myri10ge_slice_state *ss;
913         int i, status;
914         size_t bytes;
915 #ifdef CONFIG_MYRI10GE_DCA
916         unsigned long dca_tag_off;
917 #endif
918
919         /* try to send a reset command to the card to see if it
920          * is alive */
921         memset(&cmd, 0, sizeof(cmd));
922         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
923         if (status != 0) {
924                 dev_err(&mgp->pdev->dev, "failed reset\n");
925                 return -ENXIO;
926         }
927
928         (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
929         /*
930          * Use non-ndis mcp_slot (eg, 4 bytes total,
931          * no toeplitz hash value returned.  Older firmware will
932          * not understand this command, but will use the correct
933          * sized mcp_slot, so we ignore error returns
934          */
935         cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
936         (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
937
938         /* Now exchange information about interrupts  */
939
940         bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
941         cmd.data0 = (u32) bytes;
942         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
943
944         /*
945          * Even though we already know how many slices are supported
946          * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
947          * has magic side effects, and must be called after a reset.
948          * It must be called prior to calling any RSS related cmds,
949          * including assigning an interrupt queue for anything but
950          * slice 0.  It must also be called *after*
951          * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
952          * the firmware to compute offsets.
953          */
954
955         if (mgp->num_slices > 1) {
956
957                 /* ask the maximum number of slices it supports */
958                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
959                                            &cmd, 0);
960                 if (status != 0) {
961                         dev_err(&mgp->pdev->dev,
962                                 "failed to get number of slices\n");
963                 }
964
965                 /*
966                  * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
967                  * to setting up the interrupt queue DMA
968                  */
969
970                 cmd.data0 = mgp->num_slices;
971                 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
972                 if (mgp->dev->real_num_tx_queues > 1)
973                         cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
974                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
975                                            &cmd, 0);
976
977                 /* Firmware older than 1.4.32 only supports multiple
978                  * RX queues, so if we get an error, first retry using a
979                  * single TX queue before giving up */
980                 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
981                         mgp->dev->real_num_tx_queues = 1;
982                         cmd.data0 = mgp->num_slices;
983                         cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
984                         status = myri10ge_send_cmd(mgp,
985                                                    MXGEFW_CMD_ENABLE_RSS_QUEUES,
986                                                    &cmd, 0);
987                 }
988
989                 if (status != 0) {
990                         dev_err(&mgp->pdev->dev,
991                                 "failed to set number of slices\n");
992
993                         return status;
994                 }
995         }
996         for (i = 0; i < mgp->num_slices; i++) {
997                 ss = &mgp->ss[i];
998                 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
999                 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
1000                 cmd.data2 = i;
1001                 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
1002                                             &cmd, 0);
1003         };
1004
1005         status |=
1006             myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
1007         for (i = 0; i < mgp->num_slices; i++) {
1008                 ss = &mgp->ss[i];
1009                 ss->irq_claim =
1010                     (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1011         }
1012         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1013                                     &cmd, 0);
1014         mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
1015
1016         status |= myri10ge_send_cmd
1017             (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
1018         mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
1019         if (status != 0) {
1020                 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1021                 return status;
1022         }
1023         put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1024
1025 #ifdef CONFIG_MYRI10GE_DCA
1026         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1027         dca_tag_off = cmd.data0;
1028         for (i = 0; i < mgp->num_slices; i++) {
1029                 ss = &mgp->ss[i];
1030                 if (status == 0) {
1031                         ss->dca_tag = (__iomem __be32 *)
1032                             (mgp->sram + dca_tag_off + 4 * i);
1033                 } else {
1034                         ss->dca_tag = NULL;
1035                 }
1036         }
1037 #endif                          /* CONFIG_MYRI10GE_DCA */
1038
1039         /* reset mcp/driver shared state back to 0 */
1040
1041         mgp->link_changes = 0;
1042         for (i = 0; i < mgp->num_slices; i++) {
1043                 ss = &mgp->ss[i];
1044
1045                 memset(ss->rx_done.entry, 0, bytes);
1046                 ss->tx.req = 0;
1047                 ss->tx.done = 0;
1048                 ss->tx.pkt_start = 0;
1049                 ss->tx.pkt_done = 0;
1050                 ss->rx_big.cnt = 0;
1051                 ss->rx_small.cnt = 0;
1052                 ss->rx_done.idx = 0;
1053                 ss->rx_done.cnt = 0;
1054                 ss->tx.wake_queue = 0;
1055                 ss->tx.stop_queue = 0;
1056         }
1057
1058         status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
1059         myri10ge_change_pause(mgp, mgp->pause);
1060         myri10ge_set_multicast_list(mgp->dev);
1061         return status;
1062 }
1063
1064 #ifdef CONFIG_MYRI10GE_DCA
1065 static void
1066 myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1067 {
1068         ss->cpu = cpu;
1069         ss->cached_dca_tag = tag;
1070         put_be32(htonl(tag), ss->dca_tag);
1071 }
1072
1073 static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1074 {
1075         int cpu = get_cpu();
1076         int tag;
1077
1078         if (cpu != ss->cpu) {
1079                 tag = dca_get_tag(cpu);
1080                 if (ss->cached_dca_tag != tag)
1081                         myri10ge_write_dca(ss, cpu, tag);
1082         }
1083         put_cpu();
1084 }
1085
1086 static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1087 {
1088         int err, i;
1089         struct pci_dev *pdev = mgp->pdev;
1090
1091         if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1092                 return;
1093         if (!myri10ge_dca) {
1094                 dev_err(&pdev->dev, "dca disabled by administrator\n");
1095                 return;
1096         }
1097         err = dca_add_requester(&pdev->dev);
1098         if (err) {
1099                 if (err != -ENODEV)
1100                         dev_err(&pdev->dev,
1101                                 "dca_add_requester() failed, err=%d\n", err);
1102                 return;
1103         }
1104         mgp->dca_enabled = 1;
1105         for (i = 0; i < mgp->num_slices; i++)
1106                 myri10ge_write_dca(&mgp->ss[i], -1, 0);
1107 }
1108
1109 static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1110 {
1111         struct pci_dev *pdev = mgp->pdev;
1112         int err;
1113
1114         if (!mgp->dca_enabled)
1115                 return;
1116         mgp->dca_enabled = 0;
1117         err = dca_remove_requester(&pdev->dev);
1118 }
1119
1120 static int myri10ge_notify_dca_device(struct device *dev, void *data)
1121 {
1122         struct myri10ge_priv *mgp;
1123         unsigned long event;
1124
1125         mgp = dev_get_drvdata(dev);
1126         event = *(unsigned long *)data;
1127
1128         if (event == DCA_PROVIDER_ADD)
1129                 myri10ge_setup_dca(mgp);
1130         else if (event == DCA_PROVIDER_REMOVE)
1131                 myri10ge_teardown_dca(mgp);
1132         return 0;
1133 }
1134 #endif                          /* CONFIG_MYRI10GE_DCA */
1135
1136 static inline void
1137 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1138                     struct mcp_kreq_ether_recv *src)
1139 {
1140         __be32 low;
1141
1142         low = src->addr_low;
1143         src->addr_low = htonl(DMA_BIT_MASK(32));
1144         myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1145         mb();
1146         myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
1147         mb();
1148         src->addr_low = low;
1149         put_be32(low, &dst->addr_low);
1150         mb();
1151 }
1152
1153 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
1154 {
1155         struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1156
1157         if ((skb->protocol == htons(ETH_P_8021Q)) &&
1158             (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1159              vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1160                 skb->csum = hw_csum;
1161                 skb->ip_summed = CHECKSUM_COMPLETE;
1162         }
1163 }
1164
1165 static inline void
1166 myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1167                       struct skb_frag_struct *rx_frags, int len, int hlen)
1168 {
1169         struct skb_frag_struct *skb_frags;
1170
1171         skb->len = skb->data_len = len;
1172         skb->truesize = len + sizeof(struct sk_buff);
1173         /* attach the page(s) */
1174
1175         skb_frags = skb_shinfo(skb)->frags;
1176         while (len > 0) {
1177                 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1178                 len -= rx_frags->size;
1179                 skb_frags++;
1180                 rx_frags++;
1181                 skb_shinfo(skb)->nr_frags++;
1182         }
1183
1184         /* pskb_may_pull is not available in irq context, but
1185          * skb_pull() (for ether_pad and eth_type_trans()) requires
1186          * the beginning of the packet in skb_headlen(), move it
1187          * manually */
1188         skb_copy_to_linear_data(skb, va, hlen);
1189         skb_shinfo(skb)->frags[0].page_offset += hlen;
1190         skb_shinfo(skb)->frags[0].size -= hlen;
1191         skb->data_len -= hlen;
1192         skb->tail += hlen;
1193         skb_pull(skb, MXGEFW_PAD);
1194 }
1195
1196 static void
1197 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1198                         int bytes, int watchdog)
1199 {
1200         struct page *page;
1201         int idx;
1202
1203         if (unlikely(rx->watchdog_needed && !watchdog))
1204                 return;
1205
1206         /* try to refill entire ring */
1207         while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1208                 idx = rx->fill_cnt & rx->mask;
1209                 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
1210                         /* we can use part of previous page */
1211                         get_page(rx->page);
1212                 } else {
1213                         /* we need a new page */
1214                         page =
1215                             alloc_pages(GFP_ATOMIC | __GFP_COMP,
1216                                         MYRI10GE_ALLOC_ORDER);
1217                         if (unlikely(page == NULL)) {
1218                                 if (rx->fill_cnt - rx->cnt < 16)
1219                                         rx->watchdog_needed = 1;
1220                                 return;
1221                         }
1222                         rx->page = page;
1223                         rx->page_offset = 0;
1224                         rx->bus = pci_map_page(mgp->pdev, page, 0,
1225                                                MYRI10GE_ALLOC_SIZE,
1226                                                PCI_DMA_FROMDEVICE);
1227                 }
1228                 rx->info[idx].page = rx->page;
1229                 rx->info[idx].page_offset = rx->page_offset;
1230                 /* note that this is the address of the start of the
1231                  * page */
1232                 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1233                 rx->shadow[idx].addr_low =
1234                     htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1235                 rx->shadow[idx].addr_high =
1236                     htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1237
1238                 /* start next packet on a cacheline boundary */
1239                 rx->page_offset += SKB_DATA_ALIGN(bytes);
1240
1241 #if MYRI10GE_ALLOC_SIZE > 4096
1242                 /* don't cross a 4KB boundary */
1243                 if ((rx->page_offset >> 12) !=
1244                     ((rx->page_offset + bytes - 1) >> 12))
1245                         rx->page_offset = (rx->page_offset + 4096) & ~4095;
1246 #endif
1247                 rx->fill_cnt++;
1248
1249                 /* copy 8 descriptors to the firmware at a time */
1250                 if ((idx & 7) == 7) {
1251                         myri10ge_submit_8rx(&rx->lanai[idx - 7],
1252                                             &rx->shadow[idx - 7]);
1253                 }
1254         }
1255 }
1256
1257 static inline void
1258 myri10ge_unmap_rx_page(struct pci_dev *pdev,
1259                        struct myri10ge_rx_buffer_state *info, int bytes)
1260 {
1261         /* unmap the recvd page if we're the only or last user of it */
1262         if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1263             (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1264                 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1265                                       & ~(MYRI10GE_ALLOC_SIZE - 1)),
1266                                MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1267         }
1268 }
1269
1270 #define MYRI10GE_HLEN 64        /* The number of bytes to copy from a
1271                                  * page into an skb */
1272
1273 static inline int
1274 myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
1275                  int bytes, int len, __wsum csum)
1276 {
1277         struct myri10ge_priv *mgp = ss->mgp;
1278         struct sk_buff *skb;
1279         struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1280         int i, idx, hlen, remainder;
1281         struct pci_dev *pdev = mgp->pdev;
1282         struct net_device *dev = mgp->dev;
1283         u8 *va;
1284
1285         len += MXGEFW_PAD;
1286         idx = rx->cnt & rx->mask;
1287         va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1288         prefetch(va);
1289         /* Fill skb_frag_struct(s) with data from our receive */
1290         for (i = 0, remainder = len; remainder > 0; i++) {
1291                 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1292                 rx_frags[i].page = rx->info[idx].page;
1293                 rx_frags[i].page_offset = rx->info[idx].page_offset;
1294                 if (remainder < MYRI10GE_ALLOC_SIZE)
1295                         rx_frags[i].size = remainder;
1296                 else
1297                         rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1298                 rx->cnt++;
1299                 idx = rx->cnt & rx->mask;
1300                 remainder -= MYRI10GE_ALLOC_SIZE;
1301         }
1302
1303         if (mgp->csum_flag && myri10ge_lro) {
1304                 rx_frags[0].page_offset += MXGEFW_PAD;
1305                 rx_frags[0].size -= MXGEFW_PAD;
1306                 len -= MXGEFW_PAD;
1307                 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
1308                                   /* opaque, will come back in get_frag_header */
1309                                   len, len,
1310                                   (void *)(__force unsigned long)csum, csum);
1311
1312                 return 1;
1313         }
1314
1315         hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1316
1317         /* allocate an skb to attach the page(s) to. This is done
1318          * after trying LRO, so as to avoid skb allocation overheads */
1319
1320         skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1321         if (unlikely(skb == NULL)) {
1322                 ss->stats.rx_dropped++;
1323                 do {
1324                         i--;
1325                         put_page(rx_frags[i].page);
1326                 } while (i != 0);
1327                 return 0;
1328         }
1329
1330         /* Attach the pages to the skb, and trim off any padding */
1331         myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1332         if (skb_shinfo(skb)->frags[0].size <= 0) {
1333                 put_page(skb_shinfo(skb)->frags[0].page);
1334                 skb_shinfo(skb)->nr_frags = 0;
1335         }
1336         skb->protocol = eth_type_trans(skb, dev);
1337         skb_record_rx_queue(skb, ss - &mgp->ss[0]);
1338
1339         if (mgp->csum_flag) {
1340                 if ((skb->protocol == htons(ETH_P_IP)) ||
1341                     (skb->protocol == htons(ETH_P_IPV6))) {
1342                         skb->csum = csum;
1343                         skb->ip_summed = CHECKSUM_COMPLETE;
1344                 } else
1345                         myri10ge_vlan_ip_csum(skb, csum);
1346         }
1347         netif_receive_skb(skb);
1348         return 1;
1349 }
1350
1351 static inline void
1352 myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
1353 {
1354         struct pci_dev *pdev = ss->mgp->pdev;
1355         struct myri10ge_tx_buf *tx = &ss->tx;
1356         struct netdev_queue *dev_queue;
1357         struct sk_buff *skb;
1358         int idx, len;
1359
1360         while (tx->pkt_done != mcp_index) {
1361                 idx = tx->done & tx->mask;
1362                 skb = tx->info[idx].skb;
1363
1364                 /* Mark as free */
1365                 tx->info[idx].skb = NULL;
1366                 if (tx->info[idx].last) {
1367                         tx->pkt_done++;
1368                         tx->info[idx].last = 0;
1369                 }
1370                 tx->done++;
1371                 len = pci_unmap_len(&tx->info[idx], len);
1372                 pci_unmap_len_set(&tx->info[idx], len, 0);
1373                 if (skb) {
1374                         ss->stats.tx_bytes += skb->len;
1375                         ss->stats.tx_packets++;
1376                         dev_kfree_skb_irq(skb);
1377                         if (len)
1378                                 pci_unmap_single(pdev,
1379                                                  pci_unmap_addr(&tx->info[idx],
1380                                                                 bus), len,
1381                                                  PCI_DMA_TODEVICE);
1382                 } else {
1383                         if (len)
1384                                 pci_unmap_page(pdev,
1385                                                pci_unmap_addr(&tx->info[idx],
1386                                                               bus), len,
1387                                                PCI_DMA_TODEVICE);
1388                 }
1389         }
1390
1391         dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1392         /*
1393          * Make a minimal effort to prevent the NIC from polling an
1394          * idle tx queue.  If we can't get the lock we leave the queue
1395          * active. In this case, either a thread was about to start
1396          * using the queue anyway, or we lost a race and the NIC will
1397          * waste some of its resources polling an inactive queue for a
1398          * while.
1399          */
1400
1401         if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1402             __netif_tx_trylock(dev_queue)) {
1403                 if (tx->req == tx->done) {
1404                         tx->queue_active = 0;
1405                         put_be32(htonl(1), tx->send_stop);
1406                         mb();
1407                         mmiowb();
1408                 }
1409                 __netif_tx_unlock(dev_queue);
1410         }
1411
1412         /* start the queue if we've stopped it */
1413         if (netif_tx_queue_stopped(dev_queue)
1414             && tx->req - tx->done < (tx->mask >> 1)) {
1415                 tx->wake_queue++;
1416                 netif_tx_wake_queue(dev_queue);
1417         }
1418 }
1419
1420 static inline int
1421 myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
1422 {
1423         struct myri10ge_rx_done *rx_done = &ss->rx_done;
1424         struct myri10ge_priv *mgp = ss->mgp;
1425         unsigned long rx_bytes = 0;
1426         unsigned long rx_packets = 0;
1427         unsigned long rx_ok;
1428
1429         int idx = rx_done->idx;
1430         int cnt = rx_done->cnt;
1431         int work_done = 0;
1432         u16 length;
1433         __wsum checksum;
1434
1435         while (rx_done->entry[idx].length != 0 && work_done < budget) {
1436                 length = ntohs(rx_done->entry[idx].length);
1437                 rx_done->entry[idx].length = 0;
1438                 checksum = csum_unfold(rx_done->entry[idx].checksum);
1439                 if (length <= mgp->small_bytes)
1440                         rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
1441                                                  mgp->small_bytes,
1442                                                  length, checksum);
1443                 else
1444                         rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
1445                                                  mgp->big_bytes,
1446                                                  length, checksum);
1447                 rx_packets += rx_ok;
1448                 rx_bytes += rx_ok * (unsigned long)length;
1449                 cnt++;
1450                 idx = cnt & (mgp->max_intr_slots - 1);
1451                 work_done++;
1452         }
1453         rx_done->idx = idx;
1454         rx_done->cnt = cnt;
1455         ss->stats.rx_packets += rx_packets;
1456         ss->stats.rx_bytes += rx_bytes;
1457
1458         if (myri10ge_lro)
1459                 lro_flush_all(&rx_done->lro_mgr);
1460
1461         /* restock receive rings if needed */
1462         if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1463                 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1464                                         mgp->small_bytes + MXGEFW_PAD, 0);
1465         if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1466                 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1467
1468         return work_done;
1469 }
1470
1471 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1472 {
1473         struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
1474
1475         if (unlikely(stats->stats_updated)) {
1476                 unsigned link_up = ntohl(stats->link_up);
1477                 if (mgp->link_state != link_up) {
1478                         mgp->link_state = link_up;
1479
1480                         if (mgp->link_state == MXGEFW_LINK_UP) {
1481                                 if (netif_msg_link(mgp))
1482                                         printk(KERN_INFO
1483                                                "myri10ge: %s: link up\n",
1484                                                mgp->dev->name);
1485                                 netif_carrier_on(mgp->dev);
1486                                 mgp->link_changes++;
1487                         } else {
1488                                 if (netif_msg_link(mgp))
1489                                         printk(KERN_INFO
1490                                                "myri10ge: %s: link %s\n",
1491                                                mgp->dev->name,
1492                                                (link_up == MXGEFW_LINK_MYRINET ?
1493                                                 "mismatch (Myrinet detected)" :
1494                                                 "down"));
1495                                 netif_carrier_off(mgp->dev);
1496                                 mgp->link_changes++;
1497                         }
1498                 }
1499                 if (mgp->rdma_tags_available !=
1500                     ntohl(stats->rdma_tags_available)) {
1501                         mgp->rdma_tags_available =
1502                             ntohl(stats->rdma_tags_available);
1503                         printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1504                                "%d tags left\n", mgp->dev->name,
1505                                mgp->rdma_tags_available);
1506                 }
1507                 mgp->down_cnt += stats->link_down;
1508                 if (stats->link_down)
1509                         wake_up(&mgp->down_wq);
1510         }
1511 }
1512
1513 static int myri10ge_poll(struct napi_struct *napi, int budget)
1514 {
1515         struct myri10ge_slice_state *ss =
1516             container_of(napi, struct myri10ge_slice_state, napi);
1517         int work_done;
1518
1519 #ifdef CONFIG_MYRI10GE_DCA
1520         if (ss->mgp->dca_enabled)
1521                 myri10ge_update_dca(ss);
1522 #endif
1523
1524         /* process as many rx events as NAPI will allow */
1525         work_done = myri10ge_clean_rx_done(ss, budget);
1526
1527         if (work_done < budget) {
1528                 napi_complete(napi);
1529                 put_be32(htonl(3), ss->irq_claim);
1530         }
1531         return work_done;
1532 }
1533
1534 static irqreturn_t myri10ge_intr(int irq, void *arg)
1535 {
1536         struct myri10ge_slice_state *ss = arg;
1537         struct myri10ge_priv *mgp = ss->mgp;
1538         struct mcp_irq_data *stats = ss->fw_stats;
1539         struct myri10ge_tx_buf *tx = &ss->tx;
1540         u32 send_done_count;
1541         int i;
1542
1543         /* an interrupt on a non-zero receive-only slice is implicitly
1544          * valid  since MSI-X irqs are not shared */
1545         if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
1546                 napi_schedule(&ss->napi);
1547                 return (IRQ_HANDLED);
1548         }
1549
1550         /* make sure it is our IRQ, and that the DMA has finished */
1551         if (unlikely(!stats->valid))
1552                 return (IRQ_NONE);
1553
1554         /* low bit indicates receives are present, so schedule
1555          * napi poll handler */
1556         if (stats->valid & 1)
1557                 napi_schedule(&ss->napi);
1558
1559         if (!mgp->msi_enabled && !mgp->msix_enabled) {
1560                 put_be32(0, mgp->irq_deassert);
1561                 if (!myri10ge_deassert_wait)
1562                         stats->valid = 0;
1563                 mb();
1564         } else
1565                 stats->valid = 0;
1566
1567         /* Wait for IRQ line to go low, if using INTx */
1568         i = 0;
1569         while (1) {
1570                 i++;
1571                 /* check for transmit completes and receives */
1572                 send_done_count = ntohl(stats->send_done_count);
1573                 if (send_done_count != tx->pkt_done)
1574                         myri10ge_tx_done(ss, (int)send_done_count);
1575                 if (unlikely(i > myri10ge_max_irq_loops)) {
1576                         printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1577                                mgp->dev->name);
1578                         stats->valid = 0;
1579                         schedule_work(&mgp->watchdog_work);
1580                 }
1581                 if (likely(stats->valid == 0))
1582                         break;
1583                 cpu_relax();
1584                 barrier();
1585         }
1586
1587         /* Only slice 0 updates stats */
1588         if (ss == mgp->ss)
1589                 myri10ge_check_statblock(mgp);
1590
1591         put_be32(htonl(3), ss->irq_claim + 1);
1592         return (IRQ_HANDLED);
1593 }
1594
1595 static int
1596 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1597 {
1598         struct myri10ge_priv *mgp = netdev_priv(netdev);
1599         char *ptr;
1600         int i;
1601
1602         cmd->autoneg = AUTONEG_DISABLE;
1603         cmd->speed = SPEED_10000;
1604         cmd->duplex = DUPLEX_FULL;
1605
1606         /*
1607          * parse the product code to deterimine the interface type
1608          * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1609          * after the 3rd dash in the driver's cached copy of the
1610          * EEPROM's product code string.
1611          */
1612         ptr = mgp->product_code_string;
1613         if (ptr == NULL) {
1614                 printk(KERN_ERR "myri10ge: %s: Missing product code\n",
1615                        netdev->name);
1616                 return 0;
1617         }
1618         for (i = 0; i < 3; i++, ptr++) {
1619                 ptr = strchr(ptr, '-');
1620                 if (ptr == NULL) {
1621                         printk(KERN_ERR "myri10ge: %s: Invalid product "
1622                                "code %s\n", netdev->name,
1623                                mgp->product_code_string);
1624                         return 0;
1625                 }
1626         }
1627         if (*ptr == 'R' || *ptr == 'Q') {
1628                 /* We've found either an XFP or quad ribbon fiber */
1629                 cmd->port = PORT_FIBRE;
1630         }
1631         return 0;
1632 }
1633
1634 static void
1635 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1636 {
1637         struct myri10ge_priv *mgp = netdev_priv(netdev);
1638
1639         strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1640         strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1641         strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1642         strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1643 }
1644
1645 static int
1646 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1647 {
1648         struct myri10ge_priv *mgp = netdev_priv(netdev);
1649
1650         coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1651         return 0;
1652 }
1653
1654 static int
1655 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1656 {
1657         struct myri10ge_priv *mgp = netdev_priv(netdev);
1658
1659         mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1660         put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1661         return 0;
1662 }
1663
1664 static void
1665 myri10ge_get_pauseparam(struct net_device *netdev,
1666                         struct ethtool_pauseparam *pause)
1667 {
1668         struct myri10ge_priv *mgp = netdev_priv(netdev);
1669
1670         pause->autoneg = 0;
1671         pause->rx_pause = mgp->pause;
1672         pause->tx_pause = mgp->pause;
1673 }
1674
1675 static int
1676 myri10ge_set_pauseparam(struct net_device *netdev,
1677                         struct ethtool_pauseparam *pause)
1678 {
1679         struct myri10ge_priv *mgp = netdev_priv(netdev);
1680
1681         if (pause->tx_pause != mgp->pause)
1682                 return myri10ge_change_pause(mgp, pause->tx_pause);
1683         if (pause->rx_pause != mgp->pause)
1684                 return myri10ge_change_pause(mgp, pause->tx_pause);
1685         if (pause->autoneg != 0)
1686                 return -EINVAL;
1687         return 0;
1688 }
1689
1690 static void
1691 myri10ge_get_ringparam(struct net_device *netdev,
1692                        struct ethtool_ringparam *ring)
1693 {
1694         struct myri10ge_priv *mgp = netdev_priv(netdev);
1695
1696         ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1697         ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
1698         ring->rx_jumbo_max_pending = 0;
1699         ring->tx_max_pending = mgp->ss[0].rx_small.mask + 1;
1700         ring->rx_mini_pending = ring->rx_mini_max_pending;
1701         ring->rx_pending = ring->rx_max_pending;
1702         ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1703         ring->tx_pending = ring->tx_max_pending;
1704 }
1705
1706 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1707 {
1708         struct myri10ge_priv *mgp = netdev_priv(netdev);
1709
1710         if (mgp->csum_flag)
1711                 return 1;
1712         else
1713                 return 0;
1714 }
1715
1716 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1717 {
1718         struct myri10ge_priv *mgp = netdev_priv(netdev);
1719
1720         if (csum_enabled)
1721                 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1722         else
1723                 mgp->csum_flag = 0;
1724         return 0;
1725 }
1726
1727 static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1728 {
1729         struct myri10ge_priv *mgp = netdev_priv(netdev);
1730         unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1731
1732         if (tso_enabled)
1733                 netdev->features |= flags;
1734         else
1735                 netdev->features &= ~flags;
1736         return 0;
1737 }
1738
1739 static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
1740         "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1741         "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1742         "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1743         "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1744         "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1745         "tx_heartbeat_errors", "tx_window_errors",
1746         /* device-specific stats */
1747         "tx_boundary", "WC", "irq", "MSI", "MSIX",
1748         "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1749         "serial_number", "watchdog_resets",
1750 #ifdef CONFIG_MYRI10GE_DCA
1751         "dca_capable_firmware", "dca_device_present",
1752 #endif
1753         "link_changes", "link_up", "dropped_link_overflow",
1754         "dropped_link_error_or_filtered",
1755         "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1756         "dropped_unicast_filtered", "dropped_multicast_filtered",
1757         "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1758         "dropped_no_big_buffer"
1759 };
1760
1761 static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1762         "----------- slice ---------",
1763         "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1764         "rx_small_cnt", "rx_big_cnt",
1765         "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1766             "LRO flushed",
1767         "LRO avg aggr", "LRO no_desc"
1768 };
1769
1770 #define MYRI10GE_NET_STATS_LEN      21
1771 #define MYRI10GE_MAIN_STATS_LEN  ARRAY_SIZE(myri10ge_gstrings_main_stats)
1772 #define MYRI10GE_SLICE_STATS_LEN  ARRAY_SIZE(myri10ge_gstrings_slice_stats)
1773
1774 static void
1775 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1776 {
1777         struct myri10ge_priv *mgp = netdev_priv(netdev);
1778         int i;
1779
1780         switch (stringset) {
1781         case ETH_SS_STATS:
1782                 memcpy(data, *myri10ge_gstrings_main_stats,
1783                        sizeof(myri10ge_gstrings_main_stats));
1784                 data += sizeof(myri10ge_gstrings_main_stats);
1785                 for (i = 0; i < mgp->num_slices; i++) {
1786                         memcpy(data, *myri10ge_gstrings_slice_stats,
1787                                sizeof(myri10ge_gstrings_slice_stats));
1788                         data += sizeof(myri10ge_gstrings_slice_stats);
1789                 }
1790                 break;
1791         }
1792 }
1793
1794 static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
1795 {
1796         struct myri10ge_priv *mgp = netdev_priv(netdev);
1797
1798         switch (sset) {
1799         case ETH_SS_STATS:
1800                 return MYRI10GE_MAIN_STATS_LEN +
1801                     mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
1802         default:
1803                 return -EOPNOTSUPP;
1804         }
1805 }
1806
1807 static void
1808 myri10ge_get_ethtool_stats(struct net_device *netdev,
1809                            struct ethtool_stats *stats, u64 * data)
1810 {
1811         struct myri10ge_priv *mgp = netdev_priv(netdev);
1812         struct myri10ge_slice_state *ss;
1813         int slice;
1814         int i;
1815
1816         /* force stats update */
1817         (void)myri10ge_get_stats(netdev);
1818         for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1819                 data[i] = ((unsigned long *)&mgp->stats)[i];
1820
1821         data[i++] = (unsigned int)mgp->tx_boundary;
1822         data[i++] = (unsigned int)mgp->wc_enabled;
1823         data[i++] = (unsigned int)mgp->pdev->irq;
1824         data[i++] = (unsigned int)mgp->msi_enabled;
1825         data[i++] = (unsigned int)mgp->msix_enabled;
1826         data[i++] = (unsigned int)mgp->read_dma;
1827         data[i++] = (unsigned int)mgp->write_dma;
1828         data[i++] = (unsigned int)mgp->read_write_dma;
1829         data[i++] = (unsigned int)mgp->serial_number;
1830         data[i++] = (unsigned int)mgp->watchdog_resets;
1831 #ifdef CONFIG_MYRI10GE_DCA
1832         data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1833         data[i++] = (unsigned int)(mgp->dca_enabled);
1834 #endif
1835         data[i++] = (unsigned int)mgp->link_changes;
1836
1837         /* firmware stats are useful only in the first slice */
1838         ss = &mgp->ss[0];
1839         data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1840         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
1841         data[i++] =
1842             (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1843         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1844         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1845         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1846         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
1847         data[i++] =
1848             (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1849         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1850         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1851         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1852         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1853
1854         for (slice = 0; slice < mgp->num_slices; slice++) {
1855                 ss = &mgp->ss[slice];
1856                 data[i++] = slice;
1857                 data[i++] = (unsigned int)ss->tx.pkt_start;
1858                 data[i++] = (unsigned int)ss->tx.pkt_done;
1859                 data[i++] = (unsigned int)ss->tx.req;
1860                 data[i++] = (unsigned int)ss->tx.done;
1861                 data[i++] = (unsigned int)ss->rx_small.cnt;
1862                 data[i++] = (unsigned int)ss->rx_big.cnt;
1863                 data[i++] = (unsigned int)ss->tx.wake_queue;
1864                 data[i++] = (unsigned int)ss->tx.stop_queue;
1865                 data[i++] = (unsigned int)ss->tx.linearized;
1866                 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1867                 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1868                 if (ss->rx_done.lro_mgr.stats.flushed)
1869                         data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1870                             ss->rx_done.lro_mgr.stats.flushed;
1871                 else
1872                         data[i++] = 0;
1873                 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1874         }
1875 }
1876
1877 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1878 {
1879         struct myri10ge_priv *mgp = netdev_priv(netdev);
1880         mgp->msg_enable = value;
1881 }
1882
1883 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1884 {
1885         struct myri10ge_priv *mgp = netdev_priv(netdev);
1886         return mgp->msg_enable;
1887 }
1888
1889 static const struct ethtool_ops myri10ge_ethtool_ops = {
1890         .get_settings = myri10ge_get_settings,
1891         .get_drvinfo = myri10ge_get_drvinfo,
1892         .get_coalesce = myri10ge_get_coalesce,
1893         .set_coalesce = myri10ge_set_coalesce,
1894         .get_pauseparam = myri10ge_get_pauseparam,
1895         .set_pauseparam = myri10ge_set_pauseparam,
1896         .get_ringparam = myri10ge_get_ringparam,
1897         .get_rx_csum = myri10ge_get_rx_csum,
1898         .set_rx_csum = myri10ge_set_rx_csum,
1899         .set_tx_csum = ethtool_op_set_tx_hw_csum,
1900         .set_sg = ethtool_op_set_sg,
1901         .set_tso = myri10ge_set_tso,
1902         .get_link = ethtool_op_get_link,
1903         .get_strings = myri10ge_get_strings,
1904         .get_sset_count = myri10ge_get_sset_count,
1905         .get_ethtool_stats = myri10ge_get_ethtool_stats,
1906         .set_msglevel = myri10ge_set_msglevel,
1907         .get_msglevel = myri10ge_get_msglevel
1908 };
1909
1910 static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
1911 {
1912         struct myri10ge_priv *mgp = ss->mgp;
1913         struct myri10ge_cmd cmd;
1914         struct net_device *dev = mgp->dev;
1915         int tx_ring_size, rx_ring_size;
1916         int tx_ring_entries, rx_ring_entries;
1917         int i, slice, status;
1918         size_t bytes;
1919
1920         /* get ring sizes */
1921         slice = ss - mgp->ss;
1922         cmd.data0 = slice;
1923         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1924         tx_ring_size = cmd.data0;
1925         cmd.data0 = slice;
1926         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1927         if (status != 0)
1928                 return status;
1929         rx_ring_size = cmd.data0;
1930
1931         tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1932         rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1933         ss->tx.mask = tx_ring_entries - 1;
1934         ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
1935
1936         status = -ENOMEM;
1937
1938         /* allocate the host shadow rings */
1939
1940         bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1941             * sizeof(*ss->tx.req_list);
1942         ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1943         if (ss->tx.req_bytes == NULL)
1944                 goto abort_with_nothing;
1945
1946         /* ensure req_list entries are aligned to 8 bytes */
1947         ss->tx.req_list = (struct mcp_kreq_ether_send *)
1948             ALIGN((unsigned long)ss->tx.req_bytes, 8);
1949         ss->tx.queue_active = 0;
1950
1951         bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1952         ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1953         if (ss->rx_small.shadow == NULL)
1954                 goto abort_with_tx_req_bytes;
1955
1956         bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1957         ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1958         if (ss->rx_big.shadow == NULL)
1959                 goto abort_with_rx_small_shadow;
1960
1961         /* allocate the host info rings */
1962
1963         bytes = tx_ring_entries * sizeof(*ss->tx.info);
1964         ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1965         if (ss->tx.info == NULL)
1966                 goto abort_with_rx_big_shadow;
1967
1968         bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1969         ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1970         if (ss->rx_small.info == NULL)
1971                 goto abort_with_tx_info;
1972
1973         bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1974         ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1975         if (ss->rx_big.info == NULL)
1976                 goto abort_with_rx_small_info;
1977
1978         /* Fill the receive rings */
1979         ss->rx_big.cnt = 0;
1980         ss->rx_small.cnt = 0;
1981         ss->rx_big.fill_cnt = 0;
1982         ss->rx_small.fill_cnt = 0;
1983         ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1984         ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1985         ss->rx_small.watchdog_needed = 0;
1986         ss->rx_big.watchdog_needed = 0;
1987         myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1988                                 mgp->small_bytes + MXGEFW_PAD, 0);
1989
1990         if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
1991                 printk(KERN_ERR
1992                        "myri10ge: %s:slice-%d: alloced only %d small bufs\n",
1993                        dev->name, slice, ss->rx_small.fill_cnt);
1994                 goto abort_with_rx_small_ring;
1995         }
1996
1997         myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1998         if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
1999                 printk(KERN_ERR
2000                        "myri10ge: %s:slice-%d: alloced only %d big bufs\n",
2001                        dev->name, slice, ss->rx_big.fill_cnt);
2002                 goto abort_with_rx_big_ring;
2003         }
2004
2005         return 0;
2006
2007 abort_with_rx_big_ring:
2008         for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2009                 int idx = i & ss->rx_big.mask;
2010                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2011                                        mgp->big_bytes);
2012                 put_page(ss->rx_big.info[idx].page);
2013         }
2014
2015 abort_with_rx_small_ring:
2016         for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2017                 int idx = i & ss->rx_small.mask;
2018                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2019                                        mgp->small_bytes + MXGEFW_PAD);
2020                 put_page(ss->rx_small.info[idx].page);
2021         }
2022
2023         kfree(ss->rx_big.info);
2024
2025 abort_with_rx_small_info:
2026         kfree(ss->rx_small.info);
2027
2028 abort_with_tx_info:
2029         kfree(ss->tx.info);
2030
2031 abort_with_rx_big_shadow:
2032         kfree(ss->rx_big.shadow);
2033
2034 abort_with_rx_small_shadow:
2035         kfree(ss->rx_small.shadow);
2036
2037 abort_with_tx_req_bytes:
2038         kfree(ss->tx.req_bytes);
2039         ss->tx.req_bytes = NULL;
2040         ss->tx.req_list = NULL;
2041
2042 abort_with_nothing:
2043         return status;
2044 }
2045
2046 static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
2047 {
2048         struct myri10ge_priv *mgp = ss->mgp;
2049         struct sk_buff *skb;
2050         struct myri10ge_tx_buf *tx;
2051         int i, len, idx;
2052
2053         /* If not allocated, skip it */
2054         if (ss->tx.req_list == NULL)
2055                 return;
2056
2057         for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2058                 idx = i & ss->rx_big.mask;
2059                 if (i == ss->rx_big.fill_cnt - 1)
2060                         ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2061                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2062                                        mgp->big_bytes);
2063                 put_page(ss->rx_big.info[idx].page);
2064         }
2065
2066         for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2067                 idx = i & ss->rx_small.mask;
2068                 if (i == ss->rx_small.fill_cnt - 1)
2069                         ss->rx_small.info[idx].page_offset =
2070                             MYRI10GE_ALLOC_SIZE;
2071                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2072                                        mgp->small_bytes + MXGEFW_PAD);
2073                 put_page(ss->rx_small.info[idx].page);
2074         }
2075         tx = &ss->tx;
2076         while (tx->done != tx->req) {
2077                 idx = tx->done & tx->mask;
2078                 skb = tx->info[idx].skb;
2079
2080                 /* Mark as free */
2081                 tx->info[idx].skb = NULL;
2082                 tx->done++;
2083                 len = pci_unmap_len(&tx->info[idx], len);
2084                 pci_unmap_len_set(&tx->info[idx], len, 0);
2085                 if (skb) {
2086                         ss->stats.tx_dropped++;
2087                         dev_kfree_skb_any(skb);
2088                         if (len)
2089                                 pci_unmap_single(mgp->pdev,
2090                                                  pci_unmap_addr(&tx->info[idx],
2091                                                                 bus), len,
2092                                                  PCI_DMA_TODEVICE);
2093                 } else {
2094                         if (len)
2095                                 pci_unmap_page(mgp->pdev,
2096                                                pci_unmap_addr(&tx->info[idx],
2097                                                               bus), len,
2098                                                PCI_DMA_TODEVICE);
2099                 }
2100         }
2101         kfree(ss->rx_big.info);
2102
2103         kfree(ss->rx_small.info);
2104
2105         kfree(ss->tx.info);
2106
2107         kfree(ss->rx_big.shadow);
2108
2109         kfree(ss->rx_small.shadow);
2110
2111         kfree(ss->tx.req_bytes);
2112         ss->tx.req_bytes = NULL;
2113         ss->tx.req_list = NULL;
2114 }
2115
2116 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2117 {
2118         struct pci_dev *pdev = mgp->pdev;
2119         struct myri10ge_slice_state *ss;
2120         struct net_device *netdev = mgp->dev;
2121         int i;
2122         int status;
2123
2124         mgp->msi_enabled = 0;
2125         mgp->msix_enabled = 0;
2126         status = 0;
2127         if (myri10ge_msi) {
2128                 if (mgp->num_slices > 1) {
2129                         status =
2130                             pci_enable_msix(pdev, mgp->msix_vectors,
2131                                             mgp->num_slices);
2132                         if (status == 0) {
2133                                 mgp->msix_enabled = 1;
2134                         } else {
2135                                 dev_err(&pdev->dev,
2136                                         "Error %d setting up MSI-X\n", status);
2137                                 return status;
2138                         }
2139                 }
2140                 if (mgp->msix_enabled == 0) {
2141                         status = pci_enable_msi(pdev);
2142                         if (status != 0) {
2143                                 dev_err(&pdev->dev,
2144                                         "Error %d setting up MSI; falling back to xPIC\n",
2145                                         status);
2146                         } else {
2147                                 mgp->msi_enabled = 1;
2148                         }
2149                 }
2150         }
2151         if (mgp->msix_enabled) {
2152                 for (i = 0; i < mgp->num_slices; i++) {
2153                         ss = &mgp->ss[i];
2154                         snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2155                                  "%s:slice-%d", netdev->name, i);
2156                         status = request_irq(mgp->msix_vectors[i].vector,
2157                                              myri10ge_intr, 0, ss->irq_desc,
2158                                              ss);
2159                         if (status != 0) {
2160                                 dev_err(&pdev->dev,
2161                                         "slice %d failed to allocate IRQ\n", i);
2162                                 i--;
2163                                 while (i >= 0) {
2164                                         free_irq(mgp->msix_vectors[i].vector,
2165                                                  &mgp->ss[i]);
2166                                         i--;
2167                                 }
2168                                 pci_disable_msix(pdev);
2169                                 return status;
2170                         }
2171                 }
2172         } else {
2173                 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2174                                      mgp->dev->name, &mgp->ss[0]);
2175                 if (status != 0) {
2176                         dev_err(&pdev->dev, "failed to allocate IRQ\n");
2177                         if (mgp->msi_enabled)
2178                                 pci_disable_msi(pdev);
2179                 }
2180         }
2181         return status;
2182 }
2183
2184 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2185 {
2186         struct pci_dev *pdev = mgp->pdev;
2187         int i;
2188
2189         if (mgp->msix_enabled) {
2190                 for (i = 0; i < mgp->num_slices; i++)
2191                         free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2192         } else {
2193                 free_irq(pdev->irq, &mgp->ss[0]);
2194         }
2195         if (mgp->msi_enabled)
2196                 pci_disable_msi(pdev);
2197         if (mgp->msix_enabled)
2198                 pci_disable_msix(pdev);
2199 }
2200
2201 static int
2202 myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2203                          void **ip_hdr, void **tcpudp_hdr,
2204                          u64 * hdr_flags, void *priv)
2205 {
2206         struct ethhdr *eh;
2207         struct vlan_ethhdr *veh;
2208         struct iphdr *iph;
2209         u8 *va = page_address(frag->page) + frag->page_offset;
2210         unsigned long ll_hlen;
2211         /* passed opaque through lro_receive_frags() */
2212         __wsum csum = (__force __wsum) (unsigned long)priv;
2213
2214         /* find the mac header, aborting if not IPv4 */
2215
2216         eh = (struct ethhdr *)va;
2217         *mac_hdr = eh;
2218         ll_hlen = ETH_HLEN;
2219         if (eh->h_proto != htons(ETH_P_IP)) {
2220                 if (eh->h_proto == htons(ETH_P_8021Q)) {
2221                         veh = (struct vlan_ethhdr *)va;
2222                         if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2223                                 return -1;
2224
2225                         ll_hlen += VLAN_HLEN;
2226
2227                         /*
2228                          *  HW checksum starts ETH_HLEN bytes into
2229                          *  frame, so we must subtract off the VLAN
2230                          *  header's checksum before csum can be used
2231                          */
2232                         csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2233                                                            VLAN_HLEN, 0));
2234                 } else {
2235                         return -1;
2236                 }
2237         }
2238         *hdr_flags = LRO_IPV4;
2239
2240         iph = (struct iphdr *)(va + ll_hlen);
2241         *ip_hdr = iph;
2242         if (iph->protocol != IPPROTO_TCP)
2243                 return -1;
2244         if (iph->frag_off & htons(IP_MF | IP_OFFSET))
2245                 return -1;
2246         *hdr_flags |= LRO_TCP;
2247         *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2248
2249         /* verify the IP checksum */
2250         if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2251                 return -1;
2252
2253         /* verify the  checksum */
2254         if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2255                                        ntohs(iph->tot_len) - (iph->ihl << 2),
2256                                        IPPROTO_TCP, csum)))
2257                 return -1;
2258
2259         return 0;
2260 }
2261
2262 static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2263 {
2264         struct myri10ge_cmd cmd;
2265         struct myri10ge_slice_state *ss;
2266         int status;
2267
2268         ss = &mgp->ss[slice];
2269         status = 0;
2270         if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2271                 cmd.data0 = slice;
2272                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2273                                            &cmd, 0);
2274                 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2275                     (mgp->sram + cmd.data0);
2276         }
2277         cmd.data0 = slice;
2278         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2279                                     &cmd, 0);
2280         ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2281             (mgp->sram + cmd.data0);
2282
2283         cmd.data0 = slice;
2284         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2285         ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2286             (mgp->sram + cmd.data0);
2287
2288         ss->tx.send_go = (__iomem __be32 *)
2289             (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2290         ss->tx.send_stop = (__iomem __be32 *)
2291             (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
2292         return status;
2293
2294 }
2295
2296 static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2297 {
2298         struct myri10ge_cmd cmd;
2299         struct myri10ge_slice_state *ss;
2300         int status;
2301
2302         ss = &mgp->ss[slice];
2303         cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2304         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
2305         cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
2306         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2307         if (status == -ENOSYS) {
2308                 dma_addr_t bus = ss->fw_stats_bus;
2309                 if (slice != 0)
2310                         return -EINVAL;
2311                 bus += offsetof(struct mcp_irq_data, send_done_count);
2312                 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2313                 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2314                 status = myri10ge_send_cmd(mgp,
2315                                            MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2316                                            &cmd, 0);
2317                 /* Firmware cannot support multicast without STATS_DMA_V2 */
2318                 mgp->fw_multicast_support = 0;
2319         } else {
2320                 mgp->fw_multicast_support = 1;
2321         }
2322         return 0;
2323 }
2324
2325 static int myri10ge_open(struct net_device *dev)
2326 {
2327         struct myri10ge_slice_state *ss;
2328         struct myri10ge_priv *mgp = netdev_priv(dev);
2329         struct myri10ge_cmd cmd;
2330         int i, status, big_pow2, slice;
2331         u8 *itable;
2332         struct net_lro_mgr *lro_mgr;
2333
2334         if (mgp->running != MYRI10GE_ETH_STOPPED)
2335                 return -EBUSY;
2336
2337         mgp->running = MYRI10GE_ETH_STARTING;
2338         status = myri10ge_reset(mgp);
2339         if (status != 0) {
2340                 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
2341                 goto abort_with_nothing;
2342         }
2343
2344         if (mgp->num_slices > 1) {
2345                 cmd.data0 = mgp->num_slices;
2346                 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2347                 if (mgp->dev->real_num_tx_queues > 1)
2348                         cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
2349                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2350                                            &cmd, 0);
2351                 if (status != 0) {
2352                         printk(KERN_ERR
2353                                "myri10ge: %s: failed to set number of slices\n",
2354                                dev->name);
2355                         goto abort_with_nothing;
2356                 }
2357                 /* setup the indirection table */
2358                 cmd.data0 = mgp->num_slices;
2359                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2360                                            &cmd, 0);
2361
2362                 status |= myri10ge_send_cmd(mgp,
2363                                             MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2364                                             &cmd, 0);
2365                 if (status != 0) {
2366                         printk(KERN_ERR
2367                                "myri10ge: %s: failed to setup rss tables\n",
2368                                dev->name);
2369                         goto abort_with_nothing;
2370                 }
2371
2372                 /* just enable an identity mapping */
2373                 itable = mgp->sram + cmd.data0;
2374                 for (i = 0; i < mgp->num_slices; i++)
2375                         __raw_writeb(i, &itable[i]);
2376
2377                 cmd.data0 = 1;
2378                 cmd.data1 = myri10ge_rss_hash;
2379                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2380                                            &cmd, 0);
2381                 if (status != 0) {
2382                         printk(KERN_ERR
2383                                "myri10ge: %s: failed to enable slices\n",
2384                                dev->name);
2385                         goto abort_with_nothing;
2386                 }
2387         }
2388
2389         status = myri10ge_request_irq(mgp);
2390         if (status != 0)
2391                 goto abort_with_nothing;
2392
2393         /* decide what small buffer size to use.  For good TCP rx
2394          * performance, it is important to not receive 1514 byte
2395          * frames into jumbo buffers, as it confuses the socket buffer
2396          * accounting code, leading to drops and erratic performance.
2397          */
2398
2399         if (dev->mtu <= ETH_DATA_LEN)
2400                 /* enough for a TCP header */
2401                 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2402                     ? (128 - MXGEFW_PAD)
2403                     : (SMP_CACHE_BYTES - MXGEFW_PAD);
2404         else
2405                 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2406                 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
2407
2408         /* Override the small buffer size? */
2409         if (myri10ge_small_bytes > 0)
2410                 mgp->small_bytes = myri10ge_small_bytes;
2411
2412         /* Firmware needs the big buff size as a power of 2.  Lie and
2413          * tell him the buffer is larger, because we only use 1
2414          * buffer/pkt, and the mtu will prevent overruns.
2415          */
2416         big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2417         if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
2418                 while (!is_power_of_2(big_pow2))
2419                         big_pow2++;
2420                 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2421         } else {
2422                 big_pow2 = MYRI10GE_ALLOC_SIZE;
2423                 mgp->big_bytes = big_pow2;
2424         }
2425
2426         /* setup the per-slice data structures */
2427         for (slice = 0; slice < mgp->num_slices; slice++) {
2428                 ss = &mgp->ss[slice];
2429
2430                 status = myri10ge_get_txrx(mgp, slice);
2431                 if (status != 0) {
2432                         printk(KERN_ERR
2433                                "myri10ge: %s: failed to get ring sizes or locations\n",
2434                                dev->name);
2435                         goto abort_with_rings;
2436                 }
2437                 status = myri10ge_allocate_rings(ss);
2438                 if (status != 0)
2439                         goto abort_with_rings;
2440
2441                 /* only firmware which supports multiple TX queues
2442                  * supports setting up the tx stats on non-zero
2443                  * slices */
2444                 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
2445                         status = myri10ge_set_stats(mgp, slice);
2446                 if (status) {
2447                         printk(KERN_ERR
2448                                "myri10ge: %s: Couldn't set stats DMA\n",
2449                                dev->name);
2450                         goto abort_with_rings;
2451                 }
2452
2453                 lro_mgr = &ss->rx_done.lro_mgr;
2454                 lro_mgr->dev = dev;
2455                 lro_mgr->features = LRO_F_NAPI;
2456                 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2457                 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2458                 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2459                 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2460                 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2461                 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
2462                 lro_mgr->frag_align_pad = 2;
2463                 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2464                         lro_mgr->max_aggr = MAX_SKB_FRAGS;
2465
2466                 /* must happen prior to any irq */
2467                 napi_enable(&(ss)->napi);
2468         }
2469
2470         /* now give firmware buffers sizes, and MTU */
2471         cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2472         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2473         cmd.data0 = mgp->small_bytes;
2474         status |=
2475             myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2476         cmd.data0 = big_pow2;
2477         status |=
2478             myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2479         if (status) {
2480                 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
2481                        dev->name);
2482                 goto abort_with_rings;
2483         }
2484
2485         /*
2486          * Set Linux style TSO mode; this is needed only on newer
2487          *  firmware versions.  Older versions default to Linux
2488          *  style TSO
2489          */
2490         cmd.data0 = 0;
2491         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2492         if (status && status != -ENOSYS) {
2493                 printk(KERN_ERR "myri10ge: %s: Couldn't set TSO mode\n",
2494                        dev->name);
2495                 goto abort_with_rings;
2496         }
2497
2498         mgp->link_state = ~0U;
2499         mgp->rdma_tags_available = 15;
2500
2501         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2502         if (status) {
2503                 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
2504                        dev->name);
2505                 goto abort_with_rings;
2506         }
2507
2508         mgp->running = MYRI10GE_ETH_RUNNING;
2509         mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2510         add_timer(&mgp->watchdog_timer);
2511         netif_tx_wake_all_queues(dev);
2512
2513         return 0;
2514
2515 abort_with_rings:
2516         while (slice) {
2517                 slice--;
2518                 napi_disable(&mgp->ss[slice].napi);
2519         }
2520         for (i = 0; i < mgp->num_slices; i++)
2521                 myri10ge_free_rings(&mgp->ss[i]);
2522
2523         myri10ge_free_irq(mgp);
2524
2525 abort_with_nothing:
2526         mgp->running = MYRI10GE_ETH_STOPPED;
2527         return -ENOMEM;
2528 }
2529
2530 static int myri10ge_close(struct net_device *dev)
2531 {
2532         struct myri10ge_priv *mgp = netdev_priv(dev);
2533         struct myri10ge_cmd cmd;
2534         int status, old_down_cnt;
2535         int i;
2536
2537         if (mgp->running != MYRI10GE_ETH_RUNNING)
2538                 return 0;
2539
2540         if (mgp->ss[0].tx.req_bytes == NULL)
2541                 return 0;
2542
2543         del_timer_sync(&mgp->watchdog_timer);
2544         mgp->running = MYRI10GE_ETH_STOPPING;
2545         for (i = 0; i < mgp->num_slices; i++) {
2546                 napi_disable(&mgp->ss[i].napi);
2547         }
2548         netif_carrier_off(dev);
2549
2550         netif_tx_stop_all_queues(dev);
2551         old_down_cnt = mgp->down_cnt;
2552         mb();
2553         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2554         if (status)
2555                 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2556                        dev->name);
2557
2558         wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2559         if (old_down_cnt == mgp->down_cnt)
2560                 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2561
2562         netif_tx_disable(dev);
2563         myri10ge_free_irq(mgp);
2564         for (i = 0; i < mgp->num_slices; i++)
2565                 myri10ge_free_rings(&mgp->ss[i]);
2566
2567         mgp->running = MYRI10GE_ETH_STOPPED;
2568         return 0;
2569 }
2570
2571 /* copy an array of struct mcp_kreq_ether_send's to the mcp.  Copy
2572  * backwards one at a time and handle ring wraps */
2573
2574 static inline void
2575 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2576                               struct mcp_kreq_ether_send *src, int cnt)
2577 {
2578         int idx, starting_slot;
2579         starting_slot = tx->req;
2580         while (cnt > 1) {
2581                 cnt--;
2582                 idx = (starting_slot + cnt) & tx->mask;
2583                 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2584                 mb();
2585         }
2586 }
2587
2588 /*
2589  * copy an array of struct mcp_kreq_ether_send's to the mcp.  Copy
2590  * at most 32 bytes at a time, so as to avoid involving the software
2591  * pio handler in the nic.   We re-write the first segment's flags
2592  * to mark them valid only after writing the entire chain.
2593  */
2594
2595 static inline void
2596 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2597                     int cnt)
2598 {
2599         int idx, i;
2600         struct mcp_kreq_ether_send __iomem *dstp, *dst;
2601         struct mcp_kreq_ether_send *srcp;
2602         u8 last_flags;
2603
2604         idx = tx->req & tx->mask;
2605
2606         last_flags = src->flags;
2607         src->flags = 0;
2608         mb();
2609         dst = dstp = &tx->lanai[idx];
2610         srcp = src;
2611
2612         if ((idx + cnt) < tx->mask) {
2613                 for (i = 0; i < (cnt - 1); i += 2) {
2614                         myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2615                         mb();   /* force write every 32 bytes */
2616                         srcp += 2;
2617                         dstp += 2;
2618                 }
2619         } else {
2620                 /* submit all but the first request, and ensure
2621                  * that it is submitted below */
2622                 myri10ge_submit_req_backwards(tx, src, cnt);
2623                 i = 0;
2624         }
2625         if (i < cnt) {
2626                 /* submit the first request */
2627                 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2628                 mb();           /* barrier before setting valid flag */
2629         }
2630
2631         /* re-write the last 32-bits with the valid flags */
2632         src->flags = last_flags;
2633         put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
2634         tx->req += cnt;
2635         mb();
2636 }
2637
2638 /*
2639  * Transmit a packet.  We need to split the packet so that a single
2640  * segment does not cross myri10ge->tx_boundary, so this makes segment
2641  * counting tricky.  So rather than try to count segments up front, we
2642  * just give up if there are too few segments to hold a reasonably
2643  * fragmented packet currently available.  If we run
2644  * out of segments while preparing a packet for DMA, we just linearize
2645  * it and try again.
2646  */
2647
2648 static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2649 {
2650         struct myri10ge_priv *mgp = netdev_priv(dev);
2651         struct myri10ge_slice_state *ss;
2652         struct mcp_kreq_ether_send *req;
2653         struct myri10ge_tx_buf *tx;
2654         struct skb_frag_struct *frag;
2655         struct netdev_queue *netdev_queue;
2656         dma_addr_t bus;
2657         u32 low;
2658         __be32 high_swapped;
2659         unsigned int len;
2660         int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2661         u16 pseudo_hdr_offset, cksum_offset, queue;
2662         int cum_len, seglen, boundary, rdma_count;
2663         u8 flags, odd_flag;
2664
2665         queue = skb_get_queue_mapping(skb);
2666         ss = &mgp->ss[queue];
2667         netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
2668         tx = &ss->tx;
2669
2670 again:
2671         req = tx->req_list;
2672         avail = tx->mask - 1 - (tx->req - tx->done);
2673
2674         mss = 0;
2675         max_segments = MXGEFW_MAX_SEND_DESC;
2676
2677         if (skb_is_gso(skb)) {
2678                 mss = skb_shinfo(skb)->gso_size;
2679                 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
2680         }
2681
2682         if ((unlikely(avail < max_segments))) {
2683                 /* we are out of transmit resources */
2684                 tx->stop_queue++;
2685                 netif_tx_stop_queue(netdev_queue);
2686                 return 1;
2687         }
2688
2689         /* Setup checksum offloading, if needed */
2690         cksum_offset = 0;
2691         pseudo_hdr_offset = 0;
2692         odd_flag = 0;
2693         flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
2694         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2695                 cksum_offset = skb_transport_offset(skb);
2696                 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
2697                 /* If the headers are excessively large, then we must
2698                  * fall back to a software checksum */
2699                 if (unlikely(!mss && (cksum_offset > 255 ||
2700                                       pseudo_hdr_offset > 127))) {
2701                         if (skb_checksum_help(skb))
2702                                 goto drop;
2703                         cksum_offset = 0;
2704                         pseudo_hdr_offset = 0;
2705                 } else {
2706                         odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2707                         flags |= MXGEFW_FLAGS_CKSUM;
2708                 }
2709         }
2710
2711         cum_len = 0;
2712
2713         if (mss) {              /* TSO */
2714                 /* this removes any CKSUM flag from before */
2715                 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2716
2717                 /* negative cum_len signifies to the
2718                  * send loop that we are still in the
2719                  * header portion of the TSO packet.
2720                  * TSO header can be at most 1KB long */
2721                 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
2722
2723                 /* for IPv6 TSO, the checksum offset stores the
2724                  * TCP header length, to save the firmware from
2725                  * the need to parse the headers */
2726                 if (skb_is_gso_v6(skb)) {
2727                         cksum_offset = tcp_hdrlen(skb);
2728                         /* Can only handle headers <= max_tso6 long */
2729                         if (unlikely(-cum_len > mgp->max_tso6))
2730                                 return myri10ge_sw_tso(skb, dev);
2731                 }
2732                 /* for TSO, pseudo_hdr_offset holds mss.
2733                  * The firmware figures out where to put
2734                  * the checksum by parsing the header. */
2735                 pseudo_hdr_offset = mss;
2736         } else
2737                 /* Mark small packets, and pad out tiny packets */
2738         if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2739                 flags |= MXGEFW_FLAGS_SMALL;
2740
2741                 /* pad frames to at least ETH_ZLEN bytes */
2742                 if (unlikely(skb->len < ETH_ZLEN)) {
2743                         if (skb_padto(skb, ETH_ZLEN)) {
2744                                 /* The packet is gone, so we must
2745                                  * return 0 */
2746                                 ss->stats.tx_dropped += 1;
2747                                 return 0;
2748                         }
2749                         /* adjust the len to account for the zero pad
2750                          * so that the nic can know how long it is */
2751                         skb->len = ETH_ZLEN;
2752                 }
2753         }
2754
2755         /* map the skb for DMA */
2756         len = skb->len - skb->data_len;
2757         idx = tx->req & tx->mask;
2758         tx->info[idx].skb = skb;
2759         bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2760         pci_unmap_addr_set(&tx->info[idx], bus, bus);
2761         pci_unmap_len_set(&tx->info[idx], len, len);
2762
2763         frag_cnt = skb_shinfo(skb)->nr_frags;
2764         frag_idx = 0;
2765         count = 0;
2766         rdma_count = 0;
2767
2768         /* "rdma_count" is the number of RDMAs belonging to the
2769          * current packet BEFORE the current send request. For
2770          * non-TSO packets, this is equal to "count".
2771          * For TSO packets, rdma_count needs to be reset
2772          * to 0 after a segment cut.
2773          *
2774          * The rdma_count field of the send request is
2775          * the number of RDMAs of the packet starting at
2776          * that request. For TSO send requests with one ore more cuts
2777          * in the middle, this is the number of RDMAs starting
2778          * after the last cut in the request. All previous
2779          * segments before the last cut implicitly have 1 RDMA.
2780          *
2781          * Since the number of RDMAs is not known beforehand,
2782          * it must be filled-in retroactively - after each
2783          * segmentation cut or at the end of the entire packet.
2784          */
2785
2786         while (1) {
2787                 /* Break the SKB or Fragment up into pieces which
2788                  * do not cross mgp->tx_boundary */
2789                 low = MYRI10GE_LOWPART_TO_U32(bus);
2790                 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2791                 while (len) {
2792                         u8 flags_next;
2793                         int cum_len_next;
2794
2795                         if (unlikely(count == max_segments))
2796                                 goto abort_linearize;
2797
2798                         boundary =
2799                             (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
2800                         seglen = boundary - low;
2801                         if (seglen > len)
2802                                 seglen = len;
2803                         flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2804                         cum_len_next = cum_len + seglen;
2805                         if (mss) {      /* TSO */
2806                                 (req - rdma_count)->rdma_count = rdma_count + 1;
2807
2808                                 if (likely(cum_len >= 0)) {     /* payload */
2809                                         int next_is_first, chop;
2810
2811                                         chop = (cum_len_next > mss);
2812                                         cum_len_next = cum_len_next % mss;
2813                                         next_is_first = (cum_len_next == 0);
2814                                         flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2815                                         flags_next |= next_is_first *
2816                                             MXGEFW_FLAGS_FIRST;
2817                                         rdma_count |= -(chop | next_is_first);
2818                                         rdma_count += chop & !next_is_first;
2819                                 } else if (likely(cum_len_next >= 0)) { /* header ends */
2820                                         int small;
2821
2822                                         rdma_count = -1;
2823                                         cum_len_next = 0;
2824                                         seglen = -cum_len;
2825                                         small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2826                                         flags_next = MXGEFW_FLAGS_TSO_PLD |
2827                                             MXGEFW_FLAGS_FIRST |
2828                                             (small * MXGEFW_FLAGS_SMALL);
2829                                 }
2830                         }
2831                         req->addr_high = high_swapped;
2832                         req->addr_low = htonl(low);
2833                         req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2834                         req->pad = 0;   /* complete solid 16-byte block; does this matter? */
2835                         req->rdma_count = 1;
2836                         req->length = htons(seglen);
2837                         req->cksum_offset = cksum_offset;
2838                         req->flags = flags | ((cum_len & 1) * odd_flag);
2839
2840                         low += seglen;
2841                         len -= seglen;
2842                         cum_len = cum_len_next;
2843                         flags = flags_next;
2844                         req++;
2845                         count++;
2846                         rdma_count++;
2847                         if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2848                                 if (unlikely(cksum_offset > seglen))
2849                                         cksum_offset -= seglen;
2850                                 else
2851                                         cksum_offset = 0;
2852                         }
2853                 }
2854                 if (frag_idx == frag_cnt)
2855                         break;
2856
2857                 /* map next fragment for DMA */
2858                 idx = (count + tx->req) & tx->mask;
2859                 frag = &skb_shinfo(skb)->frags[frag_idx];
2860                 frag_idx++;
2861                 len = frag->size;
2862                 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2863                                    len, PCI_DMA_TODEVICE);
2864                 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2865                 pci_unmap_len_set(&tx->info[idx], len, len);
2866         }
2867
2868         (req - rdma_count)->rdma_count = rdma_count;
2869         if (mss)
2870                 do {
2871                         req--;
2872                         req->flags |= MXGEFW_FLAGS_TSO_LAST;
2873                 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2874                                          MXGEFW_FLAGS_FIRST)));
2875         idx = ((count - 1) + tx->req) & tx->mask;
2876         tx->info[idx].last = 1;
2877         myri10ge_submit_req(tx, tx->req_list, count);
2878         /* if using multiple tx queues, make sure NIC polls the
2879          * current slice */
2880         if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
2881                 tx->queue_active = 1;
2882                 put_be32(htonl(1), tx->send_go);
2883                 mb();
2884                 mmiowb();
2885         }
2886         tx->pkt_start++;
2887         if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2888                 tx->stop_queue++;
2889                 netif_tx_stop_queue(netdev_queue);
2890         }
2891         dev->trans_start = jiffies;
2892         return 0;
2893
2894 abort_linearize:
2895         /* Free any DMA resources we've alloced and clear out the skb
2896          * slot so as to not trip up assertions, and to avoid a
2897          * double-free if linearizing fails */
2898
2899         last_idx = (idx + 1) & tx->mask;
2900         idx = tx->req & tx->mask;
2901         tx->info[idx].skb = NULL;
2902         do {
2903                 len = pci_unmap_len(&tx->info[idx], len);
2904                 if (len) {
2905                         if (tx->info[idx].skb != NULL)
2906                                 pci_unmap_single(mgp->pdev,
2907                                                  pci_unmap_addr(&tx->info[idx],
2908                                                                 bus), len,
2909                                                  PCI_DMA_TODEVICE);
2910                         else
2911                                 pci_unmap_page(mgp->pdev,
2912                                                pci_unmap_addr(&tx->info[idx],
2913                                                               bus), len,
2914                                                PCI_DMA_TODEVICE);
2915                         pci_unmap_len_set(&tx->info[idx], len, 0);
2916                         tx->info[idx].skb = NULL;
2917                 }
2918                 idx = (idx + 1) & tx->mask;
2919         } while (idx != last_idx);
2920         if (skb_is_gso(skb)) {
2921                 printk(KERN_ERR
2922                        "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2923                        mgp->dev->name);
2924                 goto drop;
2925         }
2926
2927         if (skb_linearize(skb))
2928                 goto drop;
2929
2930         tx->linearized++;
2931         goto again;
2932
2933 drop:
2934         dev_kfree_skb_any(skb);
2935         ss->stats.tx_dropped += 1;
2936         return 0;
2937
2938 }
2939
2940 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2941 {
2942         struct sk_buff *segs, *curr;
2943         struct myri10ge_priv *mgp = netdev_priv(dev);
2944         struct myri10ge_slice_state *ss;
2945         int status;
2946
2947         segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
2948         if (IS_ERR(segs))
2949                 goto drop;
2950
2951         while (segs) {
2952                 curr = segs;
2953                 segs = segs->next;
2954                 curr->next = NULL;
2955                 status = myri10ge_xmit(curr, dev);
2956                 if (status != 0) {
2957                         dev_kfree_skb_any(curr);
2958                         if (segs != NULL) {
2959                                 curr = segs;
2960                                 segs = segs->next;
2961                                 curr->next = NULL;
2962                                 dev_kfree_skb_any(segs);
2963                         }
2964                         goto drop;
2965                 }
2966         }
2967         dev_kfree_skb_any(skb);
2968         return 0;
2969
2970 drop:
2971         ss = &mgp->ss[skb_get_queue_mapping(skb)];
2972         dev_kfree_skb_any(skb);
2973         ss->stats.tx_dropped += 1;
2974         return 0;
2975 }
2976
2977 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2978 {
2979         struct myri10ge_priv *mgp = netdev_priv(dev);
2980         struct myri10ge_slice_netstats *slice_stats;
2981         struct net_device_stats *stats = &mgp->stats;
2982         int i;
2983
2984         spin_lock(&mgp->stats_lock);
2985         memset(stats, 0, sizeof(*stats));
2986         for (i = 0; i < mgp->num_slices; i++) {
2987                 slice_stats = &mgp->ss[i].stats;
2988                 stats->rx_packets += slice_stats->rx_packets;
2989                 stats->tx_packets += slice_stats->tx_packets;
2990                 stats->rx_bytes += slice_stats->rx_bytes;
2991                 stats->tx_bytes += slice_stats->tx_bytes;
2992                 stats->rx_dropped += slice_stats->rx_dropped;
2993                 stats->tx_dropped += slice_stats->tx_dropped;
2994         }
2995         spin_unlock(&mgp->stats_lock);
2996         return stats;
2997 }
2998
2999 static void myri10ge_set_multicast_list(struct net_device *dev)
3000 {
3001         struct myri10ge_priv *mgp = netdev_priv(dev);
3002         struct myri10ge_cmd cmd;
3003         struct dev_mc_list *mc_list;
3004         __be32 data[2] = { 0, 0 };
3005         int err;
3006
3007         /* can be called from atomic contexts,
3008          * pass 1 to force atomicity in myri10ge_send_cmd() */
3009         myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
3010
3011         /* This firmware is known to not support multicast */
3012         if (!mgp->fw_multicast_support)
3013                 return;
3014
3015         /* Disable multicast filtering */
3016
3017         err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
3018         if (err != 0) {
3019                 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
3020                        " error status: %d\n", dev->name, err);
3021                 goto abort;
3022         }
3023
3024         if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
3025                 /* request to disable multicast filtering, so quit here */
3026                 return;
3027         }
3028
3029         /* Flush the filters */
3030
3031         err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
3032                                 &cmd, 1);
3033         if (err != 0) {
3034                 printk(KERN_ERR
3035                        "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
3036                        ", error status: %d\n", dev->name, err);
3037                 goto abort;
3038         }
3039
3040         /* Walk the multicast list, and add each address */
3041         for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
3042                 memcpy(data, &mc_list->dmi_addr, 6);
3043                 cmd.data0 = ntohl(data[0]);
3044                 cmd.data1 = ntohl(data[1]);
3045                 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
3046                                         &cmd, 1);
3047
3048                 if (err != 0) {
3049                         printk(KERN_ERR "myri10ge: %s: Failed "
3050                                "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
3051                                "%d\t", dev->name, err);
3052                         printk(KERN_ERR "MAC %pM\n", mc_list->dmi_addr);
3053                         goto abort;
3054                 }
3055         }
3056         /* Enable multicast filtering */
3057         err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3058         if (err != 0) {
3059                 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
3060                        "error status: %d\n", dev->name, err);
3061                 goto abort;
3062         }
3063
3064         return;
3065
3066 abort:
3067         return;
3068 }
3069
3070 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3071 {
3072         struct sockaddr *sa = addr;
3073         struct myri10ge_priv *mgp = netdev_priv(dev);
3074         int status;
3075
3076         if (!is_valid_ether_addr(sa->sa_data))
3077                 return -EADDRNOTAVAIL;
3078
3079         status = myri10ge_update_mac_address(mgp, sa->sa_data);
3080         if (status != 0) {
3081                 printk(KERN_ERR
3082                        "myri10ge: %s: changing mac address failed with %d\n",
3083                        dev->name, status);
3084                 return status;
3085         }
3086
3087         /* change the dev structure */
3088         memcpy(dev->dev_addr, sa->sa_data, 6);
3089         return 0;
3090 }
3091
3092 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3093 {
3094         struct myri10ge_priv *mgp = netdev_priv(dev);
3095         int error = 0;
3096
3097         if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
3098                 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
3099                        dev->name, new_mtu);
3100                 return -EINVAL;
3101         }
3102         printk(KERN_INFO "%s: changing mtu from %d to %d\n",
3103                dev->name, dev->mtu, new_mtu);
3104         if (mgp->running) {
3105                 /* if we change the mtu on an active device, we must
3106                  * reset the device so the firmware sees the change */
3107                 myri10ge_close(dev);
3108                 dev->mtu = new_mtu;
3109                 myri10ge_open(dev);
3110         } else
3111                 dev->mtu = new_mtu;
3112
3113         return error;
3114 }
3115
3116 /*
3117  * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3118  * Only do it if the bridge is a root port since we don't want to disturb
3119  * any other device, except if forced with myri10ge_ecrc_enable > 1.
3120  */
3121
3122 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3123 {
3124         struct pci_dev *bridge = mgp->pdev->bus->self;
3125         struct device *dev = &mgp->pdev->dev;
3126         unsigned cap;
3127         unsigned err_cap;
3128         u16 val;
3129         u8 ext_type;
3130         int ret;
3131
3132         if (!myri10ge_ecrc_enable || !bridge)
3133                 return;
3134
3135         /* check that the bridge is a root port */
3136         cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3137         pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3138         ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3139         if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3140                 if (myri10ge_ecrc_enable > 1) {
3141                         struct pci_dev *prev_bridge, *old_bridge = bridge;
3142
3143                         /* Walk the hierarchy up to the root port
3144                          * where ECRC has to be enabled */
3145                         do {
3146                                 prev_bridge = bridge;
3147                                 bridge = bridge->bus->self;
3148                                 if (!bridge || prev_bridge == bridge) {
3149                                         dev_err(dev,
3150                                                 "Failed to find root port"
3151                                                 " to force ECRC\n");
3152                                         return;
3153                                 }
3154                                 cap =
3155                                     pci_find_capability(bridge, PCI_CAP_ID_EXP);
3156                                 pci_read_config_word(bridge,
3157                                                      cap + PCI_CAP_FLAGS, &val);
3158                                 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3159                         } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3160
3161                         dev_info(dev,
3162                                  "Forcing ECRC on non-root port %s"
3163                                  " (enabling on root port %s)\n",
3164                                  pci_name(old_bridge), pci_name(bridge));
3165                 } else {
3166                         dev_err(dev,
3167                                 "Not enabling ECRC on non-root port %s\n",
3168                                 pci_name(bridge));
3169                         return;
3170                 }
3171         }
3172
3173         cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
3174         if (!cap)
3175                 return;
3176
3177         ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3178         if (ret) {
3179                 dev_err(dev, "failed reading ext-conf-space of %s\n",
3180                         pci_name(bridge));
3181                 dev_err(dev, "\t pci=nommconf in use? "
3182                         "or buggy/incomplete/absent ACPI MCFG attr?\n");
3183                 return;
3184         }
3185         if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3186                 return;
3187
3188         err_cap |= PCI_ERR_CAP_ECRC_GENE;
3189         pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3190         dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
3191 }
3192
3193 /*
3194  * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3195  * when the PCI-E Completion packets are aligned on an 8-byte
3196  * boundary.  Some PCI-E chip sets always align Completion packets; on
3197  * the ones that do not, the alignment can be enforced by enabling
3198  * ECRC generation (if supported).
3199  *
3200  * When PCI-E Completion packets are not aligned, it is actually more
3201  * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3202  *
3203  * If the driver can neither enable ECRC nor verify that it has
3204  * already been enabled, then it must use a firmware image which works
3205  * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
3206  * should also ensure that it never gives the device a Read-DMA which is
3207  * larger than 2KB by setting the tx_boundary to 2KB.  If ECRC is
3208  * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
3209  * firmware image, and set tx_boundary to 4KB.
3210  */
3211
3212 static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
3213 {
3214         struct pci_dev *pdev = mgp->pdev;
3215         struct device *dev = &pdev->dev;
3216         int status;
3217
3218         mgp->tx_boundary = 4096;
3219         /*
3220          * Verify the max read request size was set to 4KB
3221          * before trying the test with 4KB.
3222          */
3223         status = pcie_get_readrq(pdev);
3224         if (status < 0) {
3225                 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3226                 goto abort;
3227         }
3228         if (status != 4096) {
3229                 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
3230                 mgp->tx_boundary = 2048;
3231         }
3232         /*
3233          * load the optimized firmware (which assumes aligned PCIe
3234          * completions) in order to see if it works on this host.
3235          */
3236         mgp->fw_name = myri10ge_fw_aligned;
3237         status = myri10ge_load_firmware(mgp, 1);
3238         if (status != 0) {
3239                 goto abort;
3240         }
3241
3242         /*
3243          * Enable ECRC if possible
3244          */
3245         myri10ge_enable_ecrc(mgp);
3246
3247         /*
3248          * Run a DMA test which watches for unaligned completions and
3249          * aborts on the first one seen.
3250          */
3251
3252         status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3253         if (status == 0)
3254                 return;         /* keep the aligned firmware */
3255
3256         if (status != -E2BIG)
3257                 dev_warn(dev, "DMA test failed: %d\n", status);
3258         if (status == -ENOSYS)
3259                 dev_warn(dev, "Falling back to ethp! "
3260                          "Please install up to date fw\n");
3261 abort:
3262         /* fall back to using the unaligned firmware */
3263         mgp->tx_boundary = 2048;
3264         mgp->fw_name = myri10ge_fw_unaligned;
3265
3266 }
3267
3268 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3269 {
3270         int overridden = 0;
3271
3272         if (myri10ge_force_firmware == 0) {
3273                 int link_width, exp_cap;
3274                 u16 lnk;
3275
3276                 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3277                 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3278                 link_width = (lnk >> 4) & 0x3f;
3279
3280                 /* Check to see if Link is less than 8 or if the
3281                  * upstream bridge is known to provide aligned
3282                  * completions */
3283                 if (link_width < 8) {
3284                         dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3285                                  link_width);
3286                         mgp->tx_boundary = 4096;
3287                         mgp->fw_name = myri10ge_fw_aligned;
3288                 } else {
3289                         myri10ge_firmware_probe(mgp);
3290                 }
3291         } else {
3292                 if (myri10ge_force_firmware == 1) {
3293                         dev_info(&mgp->pdev->dev,
3294                                  "Assuming aligned completions (forced)\n");
3295                         mgp->tx_boundary = 4096;
3296                         mgp->fw_name = myri10ge_fw_aligned;
3297                 } else {
3298                         dev_info(&mgp->pdev->dev,
3299                                  "Assuming unaligned completions (forced)\n");
3300                         mgp->tx_boundary = 2048;
3301                         mgp->fw_name = myri10ge_fw_unaligned;
3302                 }
3303         }
3304         if (myri10ge_fw_name != NULL) {
3305                 overridden = 1;
3306                 mgp->fw_name = myri10ge_fw_name;
3307         }
3308         if (mgp->board_number < MYRI10GE_MAX_BOARDS &&
3309             myri10ge_fw_names[mgp->board_number] != NULL &&
3310             strlen(myri10ge_fw_names[mgp->board_number])) {
3311                 mgp->fw_name = myri10ge_fw_names[mgp->board_number];
3312                 overridden = 1;
3313         }
3314         if (overridden)
3315                 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3316                          mgp->fw_name);
3317 }
3318
3319 #ifdef CONFIG_PM
3320 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3321 {
3322         struct myri10ge_priv *mgp;
3323         struct net_device *netdev;
3324
3325         mgp = pci_get_drvdata(pdev);
3326         if (mgp == NULL)
3327                 return -EINVAL;
3328         netdev = mgp->dev;
3329
3330         netif_device_detach(netdev);
3331         if (netif_running(netdev)) {
3332                 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
3333                 rtnl_lock();
3334                 myri10ge_close(netdev);
3335                 rtnl_unlock();
3336         }
3337         myri10ge_dummy_rdma(mgp, 0);
3338         pci_save_state(pdev);
3339         pci_disable_device(pdev);
3340
3341         return pci_set_power_state(pdev, pci_choose_state(pdev, state));
3342 }
3343
3344 static int myri10ge_resume(struct pci_dev *pdev)
3345 {
3346         struct myri10ge_priv *mgp;
3347         struct net_device *netdev;
3348         int status;
3349         u16 vendor;
3350
3351         mgp = pci_get_drvdata(pdev);
3352         if (mgp == NULL)
3353                 return -EINVAL;
3354         netdev = mgp->dev;
3355         pci_set_power_state(pdev, 0);   /* zeros conf space as a side effect */
3356         msleep(5);              /* give card time to respond */
3357         pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3358         if (vendor == 0xffff) {
3359                 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
3360                        mgp->dev->name);
3361                 return -EIO;
3362         }
3363
3364         status = pci_restore_state(pdev);
3365         if (status)
3366                 return status;
3367
3368         status = pci_enable_device(pdev);
3369         if (status) {
3370                 dev_err(&pdev->dev, "failed to enable device\n");
3371                 return status;
3372         }
3373
3374         pci_set_master(pdev);
3375
3376         myri10ge_reset(mgp);
3377         myri10ge_dummy_rdma(mgp, 1);
3378
3379         /* Save configuration space to be restored if the
3380          * nic resets due to a parity error */
3381         pci_save_state(pdev);
3382
3383         if (netif_running(netdev)) {
3384                 rtnl_lock();
3385                 status = myri10ge_open(netdev);
3386                 rtnl_unlock();
3387                 if (status != 0)
3388                         goto abort_with_enabled;
3389
3390         }
3391         netif_device_attach(netdev);
3392
3393         return 0;
3394
3395 abort_with_enabled:
3396         pci_disable_device(pdev);
3397         return -EIO;
3398
3399 }
3400 #endif                          /* CONFIG_PM */
3401
3402 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3403 {
3404         struct pci_dev *pdev = mgp->pdev;
3405         int vs = mgp->vendor_specific_offset;
3406         u32 reboot;
3407
3408         /*enter read32 mode */
3409         pci_write_config_byte(pdev, vs + 0x10, 0x3);
3410
3411         /*read REBOOT_STATUS (0xfffffff0) */
3412         pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3413         pci_read_config_dword(pdev, vs + 0x14, &reboot);
3414         return reboot;
3415 }
3416
3417 /*
3418  * This watchdog is used to check whether the board has suffered
3419  * from a parity error and needs to be recovered.
3420  */
3421 static void myri10ge_watchdog(struct work_struct *work)
3422 {
3423         struct myri10ge_priv *mgp =
3424             container_of(work, struct myri10ge_priv, watchdog_work);
3425         struct myri10ge_tx_buf *tx;
3426         u32 reboot;
3427         int status;
3428         int i;
3429         u16 cmd, vendor;
3430
3431         mgp->watchdog_resets++;
3432         pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3433         if ((cmd & PCI_COMMAND_MASTER) == 0) {
3434                 /* Bus master DMA disabled?  Check to see
3435                  * if the card rebooted due to a parity error
3436                  * For now, just report it */
3437                 reboot = myri10ge_read_reboot(mgp);
3438                 printk(KERN_ERR
3439                        "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
3440                        mgp->dev->name, reboot,
3441                        myri10ge_reset_recover ? " " : " not");
3442                 if (myri10ge_reset_recover == 0)
3443                         return;
3444
3445                 myri10ge_reset_recover--;
3446
3447                 /*
3448                  * A rebooted nic will come back with config space as
3449                  * it was after power was applied to PCIe bus.
3450                  * Attempt to restore config space which was saved
3451                  * when the driver was loaded, or the last time the
3452                  * nic was resumed from power saving mode.
3453                  */
3454                 pci_restore_state(mgp->pdev);
3455
3456                 /* save state again for accounting reasons */
3457                 pci_save_state(mgp->pdev);
3458
3459         } else {
3460                 /* if we get back -1's from our slot, perhaps somebody
3461                  * powered off our card.  Don't try to reset it in
3462                  * this case */
3463                 if (cmd == 0xffff) {
3464                         pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3465                         if (vendor == 0xffff) {
3466                                 printk(KERN_ERR
3467                                        "myri10ge: %s: device disappeared!\n",
3468                                        mgp->dev->name);
3469                                 return;
3470                         }
3471                 }
3472                 /* Perhaps it is a software error.  Try to reset */
3473
3474                 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
3475                        mgp->dev->name);
3476                 for (i = 0; i < mgp->num_slices; i++) {
3477                         tx = &mgp->ss[i].tx;
3478                         printk(KERN_INFO
3479                                "myri10ge: %s: (%d): %d %d %d %d %d %d\n",
3480                                mgp->dev->name, i, tx->queue_active, tx->req,
3481                                tx->done, tx->pkt_start, tx->pkt_done,
3482                                (int)ntohl(mgp->ss[i].fw_stats->
3483                                           send_done_count));
3484                         msleep(2000);
3485                         printk(KERN_INFO
3486                                "myri10ge: %s: (%d): %d %d %d %d %d %d\n",
3487                                mgp->dev->name, i, tx->queue_active, tx->req,
3488                                tx->done, tx->pkt_start, tx->pkt_done,
3489                                (int)ntohl(mgp->ss[i].fw_stats->
3490                                           send_done_count));
3491                 }
3492         }
3493
3494         rtnl_lock();
3495         myri10ge_close(mgp->dev);
3496         status = myri10ge_load_firmware(mgp, 1);
3497         if (status != 0)
3498                 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
3499                        mgp->dev->name);
3500         else
3501                 myri10ge_open(mgp->dev);
3502         rtnl_unlock();
3503 }
3504
3505 /*
3506  * We use our own timer routine rather than relying upon
3507  * netdev->tx_timeout because we have a very large hardware transmit
3508  * queue.  Due to the large queue, the netdev->tx_timeout function
3509  * cannot detect a NIC with a parity error in a timely fashion if the
3510  * NIC is lightly loaded.
3511  */
3512 static void myri10ge_watchdog_timer(unsigned long arg)
3513 {
3514         struct myri10ge_priv *mgp;
3515         struct myri10ge_slice_state *ss;
3516         int i, reset_needed;
3517         u32 rx_pause_cnt;
3518
3519         mgp = (struct myri10ge_priv *)arg;
3520
3521         rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3522         for (i = 0, reset_needed = 0;
3523              i < mgp->num_slices && reset_needed == 0; ++i) {
3524
3525                 ss = &mgp->ss[i];
3526                 if (ss->rx_small.watchdog_needed) {
3527                         myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3528                                                 mgp->small_bytes + MXGEFW_PAD,
3529                                                 1);
3530                         if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3531                             myri10ge_fill_thresh)
3532                                 ss->rx_small.watchdog_needed = 0;
3533                 }
3534                 if (ss->rx_big.watchdog_needed) {
3535                         myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3536                                                 mgp->big_bytes, 1);
3537                         if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3538                             myri10ge_fill_thresh)
3539                                 ss->rx_big.watchdog_needed = 0;
3540                 }
3541
3542                 if (ss->tx.req != ss->tx.done &&
3543                     ss->tx.done == ss->watchdog_tx_done &&
3544                     ss->watchdog_tx_req != ss->watchdog_tx_done) {
3545                         /* nic seems like it might be stuck.. */
3546                         if (rx_pause_cnt != mgp->watchdog_pause) {
3547                                 if (net_ratelimit())
3548                                         printk(KERN_WARNING
3549                                                "myri10ge %s slice %d:"
3550                                                "TX paused, check link partner\n",
3551                                                mgp->dev->name, i);
3552                         } else {
3553                                 printk(KERN_WARNING
3554                                        "myri10ge %s slice %d stuck:",
3555                                        mgp->dev->name, i);
3556                                 reset_needed = 1;
3557                         }
3558                 }
3559                 ss->watchdog_tx_done = ss->tx.done;
3560                 ss->watchdog_tx_req = ss->tx.req;
3561         }
3562         mgp->watchdog_pause = rx_pause_cnt;
3563
3564         if (reset_needed) {
3565                 schedule_work(&mgp->watchdog_work);
3566         } else {
3567                 /* rearm timer */
3568                 mod_timer(&mgp->watchdog_timer,
3569                           jiffies + myri10ge_watchdog_timeout * HZ);
3570         }
3571 }
3572
3573 static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3574 {
3575         struct myri10ge_slice_state *ss;
3576         struct pci_dev *pdev = mgp->pdev;
3577         size_t bytes;
3578         int i;
3579
3580         if (mgp->ss == NULL)
3581                 return;
3582
3583         for (i = 0; i < mgp->num_slices; i++) {
3584                 ss = &mgp->ss[i];
3585                 if (ss->rx_done.entry != NULL) {
3586                         bytes = mgp->max_intr_slots *
3587                             sizeof(*ss->rx_done.entry);
3588                         dma_free_coherent(&pdev->dev, bytes,
3589                                           ss->rx_done.entry, ss->rx_done.bus);
3590                         ss->rx_done.entry = NULL;
3591                 }
3592                 if (ss->fw_stats != NULL) {
3593                         bytes = sizeof(*ss->fw_stats);
3594                         dma_free_coherent(&pdev->dev, bytes,
3595                                           ss->fw_stats, ss->fw_stats_bus);
3596                         ss->fw_stats = NULL;
3597                 }
3598         }
3599         kfree(mgp->ss);
3600         mgp->ss = NULL;
3601 }
3602
3603 static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3604 {
3605         struct myri10ge_slice_state *ss;
3606         struct pci_dev *pdev = mgp->pdev;
3607         size_t bytes;
3608         int i;
3609
3610         bytes = sizeof(*mgp->ss) * mgp->num_slices;
3611         mgp->ss = kzalloc(bytes, GFP_KERNEL);
3612         if (mgp->ss == NULL) {
3613                 return -ENOMEM;
3614         }
3615
3616         for (i = 0; i < mgp->num_slices; i++) {
3617                 ss = &mgp->ss[i];
3618                 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3619                 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3620                                                        &ss->rx_done.bus,
3621                                                        GFP_KERNEL);
3622                 if (ss->rx_done.entry == NULL)
3623                         goto abort;
3624                 memset(ss->rx_done.entry, 0, bytes);
3625                 bytes = sizeof(*ss->fw_stats);
3626                 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3627                                                   &ss->fw_stats_bus,
3628                                                   GFP_KERNEL);
3629                 if (ss->fw_stats == NULL)
3630                         goto abort;
3631                 ss->mgp = mgp;
3632                 ss->dev = mgp->dev;
3633                 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3634                                myri10ge_napi_weight);
3635         }
3636         return 0;
3637 abort:
3638         myri10ge_free_slices(mgp);
3639         return -ENOMEM;
3640 }
3641
3642 /*
3643  * This function determines the number of slices supported.
3644  * The number slices is the minumum of the number of CPUS,
3645  * the number of MSI-X irqs supported, the number of slices
3646  * supported by the firmware
3647  */
3648 static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3649 {
3650         struct myri10ge_cmd cmd;
3651         struct pci_dev *pdev = mgp->pdev;
3652         char *old_fw;
3653         int i, status, ncpus, msix_cap;
3654
3655         mgp->num_slices = 1;
3656         msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3657         ncpus = num_online_cpus();
3658
3659         if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3660             (myri10ge_max_slices == -1 && ncpus < 2))
3661                 return;
3662
3663         /* try to load the slice aware rss firmware */
3664         old_fw = mgp->fw_name;
3665         if (myri10ge_fw_name != NULL) {
3666                 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3667                          myri10ge_fw_name);
3668                 mgp->fw_name = myri10ge_fw_name;
3669         } else if (old_fw == myri10ge_fw_aligned)
3670                 mgp->fw_name = myri10ge_fw_rss_aligned;
3671         else
3672                 mgp->fw_name = myri10ge_fw_rss_unaligned;
3673         status = myri10ge_load_firmware(mgp, 0);
3674         if (status != 0) {
3675                 dev_info(&pdev->dev, "Rss firmware not found\n");
3676                 return;
3677         }
3678
3679         /* hit the board with a reset to ensure it is alive */
3680         memset(&cmd, 0, sizeof(cmd));
3681         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3682         if (status != 0) {
3683                 dev_err(&mgp->pdev->dev, "failed reset\n");
3684                 goto abort_with_fw;
3685                 return;
3686         }
3687
3688         mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3689
3690         /* tell it the size of the interrupt queues */
3691         cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3692         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3693         if (status != 0) {
3694                 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3695                 goto abort_with_fw;
3696         }
3697
3698         /* ask the maximum number of slices it supports */
3699         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3700         if (status != 0)
3701                 goto abort_with_fw;
3702         else
3703                 mgp->num_slices = cmd.data0;
3704
3705         /* Only allow multiple slices if MSI-X is usable */
3706         if (!myri10ge_msi) {
3707                 goto abort_with_fw;
3708         }
3709
3710         /* if the admin did not specify a limit to how many
3711          * slices we should use, cap it automatically to the
3712          * number of CPUs currently online */
3713         if (myri10ge_max_slices == -1)
3714                 myri10ge_max_slices = ncpus;
3715
3716         if (mgp->num_slices > myri10ge_max_slices)
3717                 mgp->num_slices = myri10ge_max_slices;
3718
3719         /* Now try to allocate as many MSI-X vectors as we have
3720          * slices. We give up on MSI-X if we can only get a single
3721          * vector. */
3722
3723         mgp->msix_vectors = kzalloc(mgp->num_slices *
3724                                     sizeof(*mgp->msix_vectors), GFP_KERNEL);
3725         if (mgp->msix_vectors == NULL)
3726                 goto disable_msix;
3727         for (i = 0; i < mgp->num_slices; i++) {
3728                 mgp->msix_vectors[i].entry = i;
3729         }
3730
3731         while (mgp->num_slices > 1) {
3732                 /* make sure it is a power of two */
3733                 while (!is_power_of_2(mgp->num_slices))
3734                         mgp->num_slices--;
3735                 if (mgp->num_slices == 1)
3736                         goto disable_msix;
3737                 status = pci_enable_msix(pdev, mgp->msix_vectors,
3738                                          mgp->num_slices);
3739                 if (status == 0) {
3740                         pci_disable_msix(pdev);
3741                         return;
3742                 }
3743                 if (status > 0)
3744                         mgp->num_slices = status;
3745                 else
3746                         goto disable_msix;
3747         }
3748
3749 disable_msix:
3750         if (mgp->msix_vectors != NULL) {
3751                 kfree(mgp->msix_vectors);
3752                 mgp->msix_vectors = NULL;
3753         }
3754
3755 abort_with_fw:
3756         mgp->num_slices = 1;
3757         mgp->fw_name = old_fw;
3758         myri10ge_load_firmware(mgp, 0);
3759 }
3760
3761 static const struct net_device_ops myri10ge_netdev_ops = {
3762         .ndo_open               = myri10ge_open,
3763         .ndo_stop               = myri10ge_close,
3764         .ndo_start_xmit         = myri10ge_xmit,
3765         .ndo_get_stats          = myri10ge_get_stats,
3766         .ndo_validate_addr      = eth_validate_addr,
3767         .ndo_change_mtu         = myri10ge_change_mtu,
3768         .ndo_set_multicast_list = myri10ge_set_multicast_list,
3769         .ndo_set_mac_address    = myri10ge_set_mac_address,
3770 };
3771
3772 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3773 {
3774         struct net_device *netdev;
3775         struct myri10ge_priv *mgp;
3776         struct device *dev = &pdev->dev;
3777         int i;
3778         int status = -ENXIO;
3779         int dac_enabled;
3780         unsigned hdr_offset, ss_offset;
3781         static int board_number;
3782
3783         netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
3784         if (netdev == NULL) {
3785                 dev_err(dev, "Could not allocate ethernet device\n");
3786                 return -ENOMEM;
3787         }
3788
3789         SET_NETDEV_DEV(netdev, &pdev->dev);
3790
3791         mgp = netdev_priv(netdev);
3792         mgp->dev = netdev;
3793         mgp->pdev = pdev;
3794         mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3795         mgp->pause = myri10ge_flow_control;
3796         mgp->intr_coal_delay = myri10ge_intr_coal_delay;
3797         mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
3798         mgp->board_number = board_number;
3799         init_waitqueue_head(&mgp->down_wq);
3800
3801         if (pci_enable_device(pdev)) {
3802                 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3803                 status = -ENODEV;
3804                 goto abort_with_netdev;
3805         }
3806
3807         /* Find the vendor-specific cap so we can check
3808          * the reboot register later on */
3809         mgp->vendor_specific_offset
3810             = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3811
3812         /* Set our max read request to 4KB */
3813         status = pcie_set_readrq(pdev, 4096);
3814         if (status != 0) {
3815                 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3816                         status);
3817                 goto abort_with_enabled;
3818         }
3819
3820         pci_set_master(pdev);
3821         dac_enabled = 1;
3822         status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3823         if (status != 0) {
3824                 dac_enabled = 0;
3825                 dev_err(&pdev->dev,
3826                         "64-bit pci address mask was refused, "
3827                         "trying 32-bit\n");
3828                 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3829         }
3830         if (status != 0) {
3831                 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3832                 goto abort_with_enabled;
3833         }
3834         (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3835         mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3836                                       &mgp->cmd_bus, GFP_KERNEL);
3837         if (mgp->cmd == NULL)
3838                 goto abort_with_enabled;
3839
3840         mgp->board_span = pci_resource_len(pdev, 0);
3841         mgp->iomem_base = pci_resource_start(pdev, 0);
3842         mgp->mtrr = -1;
3843         mgp->wc_enabled = 0;
3844 #ifdef CONFIG_MTRR
3845         mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3846                              MTRR_TYPE_WRCOMB, 1);
3847         if (mgp->mtrr >= 0)
3848                 mgp->wc_enabled = 1;
3849 #endif
3850         mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
3851         if (mgp->sram == NULL) {
3852                 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3853                         mgp->board_span, mgp->iomem_base);
3854                 status = -ENXIO;
3855                 goto abort_with_mtrr;
3856         }
3857         hdr_offset =
3858             ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
3859         ss_offset = hdr_offset + offsetof(struct mcp_gen_header, string_specs);
3860         mgp->sram_size = ntohl(__raw_readl(mgp->sram + ss_offset));
3861         if (mgp->sram_size > mgp->board_span ||
3862             mgp->sram_size <= MYRI10GE_FW_OFFSET) {
3863                 dev_err(&pdev->dev,
3864                         "invalid sram_size %dB or board span %ldB\n",
3865                         mgp->sram_size, mgp->board_span);
3866                 goto abort_with_ioremap;
3867         }
3868         memcpy_fromio(mgp->eeprom_strings,
3869                       mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
3870         memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3871         status = myri10ge_read_mac_addr(mgp);
3872         if (status)
3873                 goto abort_with_ioremap;
3874
3875         for (i = 0; i < ETH_ALEN; i++)
3876                 netdev->dev_addr[i] = mgp->mac_addr[i];
3877
3878         myri10ge_select_firmware(mgp);
3879
3880         status = myri10ge_load_firmware(mgp, 1);
3881         if (status != 0) {
3882                 dev_err(&pdev->dev, "failed to load firmware\n");
3883                 goto abort_with_ioremap;
3884         }
3885         myri10ge_probe_slices(mgp);
3886         status = myri10ge_alloc_slices(mgp);
3887         if (status != 0) {
3888                 dev_err(&pdev->dev, "failed to alloc slice state\n");
3889                 goto abort_with_firmware;
3890         }
3891         netdev->real_num_tx_queues = mgp->num_slices;
3892         status = myri10ge_reset(mgp);
3893         if (status != 0) {
3894                 dev_err(&pdev->dev, "failed reset\n");
3895                 goto abort_with_slices;
3896         }
3897 #ifdef CONFIG_MYRI10GE_DCA
3898         myri10ge_setup_dca(mgp);
3899 #endif
3900         pci_set_drvdata(pdev, mgp);
3901         if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3902                 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3903         if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3904                 myri10ge_initial_mtu = 68;
3905
3906         netdev->netdev_ops = &myri10ge_netdev_ops;
3907         netdev->mtu = myri10ge_initial_mtu;
3908         netdev->base_addr = mgp->iomem_base;
3909         netdev->features = mgp->features;
3910
3911         if (dac_enabled)
3912                 netdev->features |= NETIF_F_HIGHDMA;
3913
3914         /* make sure we can get an irq, and that MSI can be
3915          * setup (if available).  Also ensure netdev->irq
3916          * is set to correct value if MSI is enabled */
3917         status = myri10ge_request_irq(mgp);
3918         if (status != 0)
3919                 goto abort_with_firmware;
3920         netdev->irq = pdev->irq;
3921         myri10ge_free_irq(mgp);
3922
3923         /* Save configuration space to be restored if the
3924          * nic resets due to a parity error */
3925         pci_save_state(pdev);
3926
3927         /* Setup the watchdog timer */
3928         setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3929                     (unsigned long)mgp);
3930
3931         spin_lock_init(&mgp->stats_lock);
3932         SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
3933         INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
3934         status = register_netdev(netdev);
3935         if (status != 0) {
3936                 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
3937                 goto abort_with_state;
3938         }
3939         if (mgp->msix_enabled)
3940                 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3941                          mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3942                          (mgp->wc_enabled ? "Enabled" : "Disabled"));
3943         else
3944                 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3945                          mgp->msi_enabled ? "MSI" : "xPIC",
3946                          netdev->irq, mgp->tx_boundary, mgp->fw_name,
3947                          (mgp->wc_enabled ? "Enabled" : "Disabled"));
3948
3949         board_number++;
3950         return 0;
3951
3952 abort_with_state:
3953         pci_restore_state(pdev);
3954
3955 abort_with_slices:
3956         myri10ge_free_slices(mgp);
3957
3958 abort_with_firmware:
3959         myri10ge_dummy_rdma(mgp, 0);
3960
3961 abort_with_ioremap:
3962         if (mgp->mac_addr_string != NULL)
3963                 dev_err(&pdev->dev,
3964                         "myri10ge_probe() failed: MAC=%s, SN=%ld\n",
3965                         mgp->mac_addr_string, mgp->serial_number);
3966         iounmap(mgp->sram);
3967
3968 abort_with_mtrr:
3969 #ifdef CONFIG_MTRR
3970         if (mgp->mtrr >= 0)
3971                 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3972 #endif
3973         dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3974                           mgp->cmd, mgp->cmd_bus);
3975
3976 abort_with_enabled:
3977         pci_disable_device(pdev);
3978
3979 abort_with_netdev:
3980         free_netdev(netdev);
3981         return status;
3982 }
3983
3984 /*
3985  * myri10ge_remove
3986  *
3987  * Does what is necessary to shutdown one Myrinet device. Called
3988  *   once for each Myrinet card by the kernel when a module is
3989  *   unloaded.
3990  */
3991 static void myri10ge_remove(struct pci_dev *pdev)
3992 {
3993         struct myri10ge_priv *mgp;
3994         struct net_device *netdev;
3995
3996         mgp = pci_get_drvdata(pdev);
3997         if (mgp == NULL)
3998                 return;
3999
4000         flush_scheduled_work();
4001         netdev = mgp->dev;
4002         unregister_netdev(netdev);
4003
4004 #ifdef CONFIG_MYRI10GE_DCA
4005         myri10ge_teardown_dca(mgp);
4006 #endif
4007         myri10ge_dummy_rdma(mgp, 0);
4008
4009         /* avoid a memory leak */
4010         pci_restore_state(pdev);
4011
4012         iounmap(mgp->sram);
4013
4014 #ifdef CONFIG_MTRR
4015         if (mgp->mtrr >= 0)
4016                 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4017 #endif
4018         myri10ge_free_slices(mgp);
4019         if (mgp->msix_vectors != NULL)
4020                 kfree(mgp->msix_vectors);
4021         dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4022                           mgp->cmd, mgp->cmd_bus);
4023
4024         free_netdev(netdev);
4025         pci_disable_device(pdev);
4026         pci_set_drvdata(pdev, NULL);
4027 }
4028
4029 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E      0x0008
4030 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9    0x0009
4031
4032 static struct pci_device_id myri10ge_pci_tbl[] = {
4033         {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
4034         {PCI_DEVICE
4035          (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
4036         {0},
4037 };
4038
4039 MODULE_DEVICE_TABLE(pci, myri10ge_pci_tbl);
4040
4041 static struct pci_driver myri10ge_driver = {
4042         .name = "myri10ge",
4043         .probe = myri10ge_probe,
4044         .remove = myri10ge_remove,
4045         .id_table = myri10ge_pci_tbl,
4046 #ifdef CONFIG_PM
4047         .suspend = myri10ge_suspend,
4048         .resume = myri10ge_resume,
4049 #endif
4050 };
4051
4052 #ifdef CONFIG_MYRI10GE_DCA
4053 static int
4054 myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4055 {
4056         int err = driver_for_each_device(&myri10ge_driver.driver,
4057                                          NULL, &event,
4058                                          myri10ge_notify_dca_device);
4059
4060         if (err)
4061                 return NOTIFY_BAD;
4062         return NOTIFY_DONE;
4063 }
4064
4065 static struct notifier_block myri10ge_dca_notifier = {
4066         .notifier_call = myri10ge_notify_dca,
4067         .next = NULL,
4068         .priority = 0,
4069 };
4070 #endif                          /* CONFIG_MYRI10GE_DCA */
4071
4072 static __init int myri10ge_init_module(void)
4073 {
4074         printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
4075                MYRI10GE_VERSION_STR);
4076
4077         if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
4078                 printk(KERN_ERR
4079                        "%s: Illegal rssh hash type %d, defaulting to source port\n",
4080                        myri10ge_driver.name, myri10ge_rss_hash);
4081                 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4082         }
4083 #ifdef CONFIG_MYRI10GE_DCA
4084         dca_register_notify(&myri10ge_dca_notifier);
4085 #endif
4086         if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4087                 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
4088
4089         return pci_register_driver(&myri10ge_driver);
4090 }
4091
4092 module_init(myri10ge_init_module);
4093
4094 static __exit void myri10ge_cleanup_module(void)
4095 {
4096 #ifdef CONFIG_MYRI10GE_DCA
4097         dca_unregister_notify(&myri10ge_dca_notifier);
4098 #endif
4099         pci_unregister_driver(&myri10ge_driver);
4100 }
4101
4102 module_exit(myri10ge_cleanup_module);