2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_driver_name[] = "mv643xx_eth";
58 static char mv643xx_driver_version[] = "1.0";
60 #define MV643XX_CHECKSUM_OFFLOAD_TX
62 #define MV643XX_TX_FAST_REFILL
65 #define MV643XX_TX_COAL 100
67 #define MV643XX_RX_COAL 100
70 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
71 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
73 #define MAX_DESCS_PER_SKB 1
76 #define ETH_VLAN_HLEN 4
78 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
79 #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
80 ETH_VLAN_HLEN + ETH_FCS_LEN)
81 #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \
82 dma_get_cache_alignment())
85 * Registers shared between all ports.
87 #define PHY_ADDR 0x0000
88 #define SMI_REG 0x0004
89 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
90 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
91 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
92 #define WINDOW_BAR_ENABLE 0x0290
93 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
98 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
99 #define UNICAST_PROMISCUOUS_MODE 0x00000001
100 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
101 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
102 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
103 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
104 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
105 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
106 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
107 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
108 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
109 #define INT_RX 0x00000804
110 #define INT_EXT 0x00000002
111 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
112 #define INT_EXT_LINK 0x00100000
113 #define INT_EXT_PHY 0x00010000
114 #define INT_EXT_TX_ERROR_0 0x00000100
115 #define INT_EXT_TX_0 0x00000001
116 #define INT_EXT_TX 0x00000101
117 #define INT_MASK(p) (0x0468 + ((p) << 10))
118 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
119 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
120 #define RXQ_CURRENT_DESC_PTR(p) (0x060c + ((p) << 10))
121 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
122 #define TXQ_CURRENT_DESC_PTR(p) (0x06c0 + ((p) << 10))
123 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
124 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
125 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
126 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
130 * SDMA configuration register.
132 #define RX_BURST_SIZE_4_64BIT (2 << 1)
133 #define BLM_RX_NO_SWAP (1 << 4)
134 #define BLM_TX_NO_SWAP (1 << 5)
135 #define TX_BURST_SIZE_4_64BIT (2 << 22)
137 #if defined(__BIG_ENDIAN)
138 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
139 RX_BURST_SIZE_4_64BIT | \
140 TX_BURST_SIZE_4_64BIT
141 #elif defined(__LITTLE_ENDIAN)
142 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
143 RX_BURST_SIZE_4_64BIT | \
146 TX_BURST_SIZE_4_64BIT
148 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
153 * Port serial control register.
155 #define SET_MII_SPEED_TO_100 (1 << 24)
156 #define SET_GMII_SPEED_TO_1000 (1 << 23)
157 #define SET_FULL_DUPLEX_MODE (1 << 21)
158 #define MAX_RX_PACKET_1522BYTE (1 << 17)
159 #define MAX_RX_PACKET_9700BYTE (5 << 17)
160 #define MAX_RX_PACKET_MASK (7 << 17)
161 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
162 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
163 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
164 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
165 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
166 #define FORCE_LINK_PASS (1 << 1)
167 #define SERIAL_PORT_ENABLE (1 << 0)
169 #define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
170 #define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
172 #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
173 #define PHY_WAIT_MICRO_SECONDS 10
175 /* Buffer offset from buffer pointer */
176 #define RX_BUF_OFFSET 0x2
178 /* Gigabit Ethernet Unit Global Registers */
180 /* MIB Counters register definitions */
181 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
182 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
183 #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
184 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
185 #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
186 #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
187 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
188 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
189 #define ETH_MIB_FRAMES_64_OCTETS 0x20
190 #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
191 #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
192 #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
193 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
194 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
195 #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
196 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
197 #define ETH_MIB_GOOD_FRAMES_SENT 0x40
198 #define ETH_MIB_EXCESSIVE_COLLISION 0x44
199 #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
200 #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
201 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
202 #define ETH_MIB_FC_SENT 0x54
203 #define ETH_MIB_GOOD_FC_RECEIVED 0x58
204 #define ETH_MIB_BAD_FC_RECEIVED 0x5c
205 #define ETH_MIB_UNDERSIZE_RECEIVED 0x60
206 #define ETH_MIB_FRAGMENTS_RECEIVED 0x64
207 #define ETH_MIB_OVERSIZE_RECEIVED 0x68
208 #define ETH_MIB_JABBER_RECEIVED 0x6c
209 #define ETH_MIB_MAC_RECEIVE_ERROR 0x70
210 #define ETH_MIB_BAD_CRC_EVENT 0x74
211 #define ETH_MIB_COLLISION 0x78
212 #define ETH_MIB_LATE_COLLISION 0x7c
214 /* Port serial status reg (PSR) */
215 #define ETH_INTERFACE_PCM 0x00000001
216 #define ETH_LINK_IS_UP 0x00000002
217 #define ETH_PORT_AT_FULL_DUPLEX 0x00000004
218 #define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
219 #define ETH_GMII_SPEED_1000 0x00000010
220 #define ETH_MII_SPEED_100 0x00000020
221 #define ETH_TX_IN_PROGRESS 0x00000080
222 #define ETH_BYPASS_ACTIVE 0x00000100
223 #define ETH_PORT_AT_PARTITION_STATE 0x00000200
224 #define ETH_PORT_TX_FIFO_EMPTY 0x00000400
227 #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
228 #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
229 #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
230 #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
232 /* Interrupt Cause Register Bit Definitions */
234 /* SDMA command status fields macros */
236 /* Tx & Rx descriptors status */
237 #define ETH_ERROR_SUMMARY 0x00000001
239 /* Tx & Rx descriptors command */
240 #define ETH_BUFFER_OWNED_BY_DMA 0x80000000
242 /* Tx descriptors status */
243 #define ETH_LC_ERROR 0
244 #define ETH_UR_ERROR 0x00000002
245 #define ETH_RL_ERROR 0x00000004
246 #define ETH_LLC_SNAP_FORMAT 0x00000200
248 /* Rx descriptors status */
249 #define ETH_OVERRUN_ERROR 0x00000002
250 #define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
251 #define ETH_RESOURCE_ERROR 0x00000006
252 #define ETH_VLAN_TAGGED 0x00080000
253 #define ETH_BPDU_FRAME 0x00100000
254 #define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
255 #define ETH_OTHER_FRAME_TYPE 0x00400000
256 #define ETH_LAYER_2_IS_ETH_V_2 0x00800000
257 #define ETH_FRAME_TYPE_IP_V_4 0x01000000
258 #define ETH_FRAME_HEADER_OK 0x02000000
259 #define ETH_RX_LAST_DESC 0x04000000
260 #define ETH_RX_FIRST_DESC 0x08000000
261 #define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
262 #define ETH_RX_ENABLE_INTERRUPT 0x20000000
263 #define ETH_LAYER_4_CHECKSUM_OK 0x40000000
265 /* Rx descriptors byte count */
266 #define ETH_FRAME_FRAGMENTED 0x00000004
268 /* Tx descriptors command */
269 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
270 #define ETH_FRAME_SET_TO_VLAN 0x00008000
271 #define ETH_UDP_FRAME 0x00010000
272 #define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
273 #define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
274 #define ETH_ZERO_PADDING 0x00080000
275 #define ETH_TX_LAST_DESC 0x00100000
276 #define ETH_TX_FIRST_DESC 0x00200000
277 #define ETH_GEN_CRC 0x00400000
278 #define ETH_TX_ENABLE_INTERRUPT 0x00800000
279 #define ETH_AUTO_MODE 0x40000000
281 #define ETH_TX_IHL_SHIFT 11
285 typedef enum _eth_func_ret_status {
286 ETH_OK, /* Returned as expected. */
287 ETH_ERROR, /* Fundamental error. */
288 ETH_RETRY, /* Could not process request. Try later.*/
289 ETH_END_OF_JOB, /* Ring has nothing to process. */
290 ETH_QUEUE_FULL, /* Ring resource error. */
291 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
292 } ETH_FUNC_RET_STATUS;
294 /* These are for big-endian machines. Little endian needs different
297 #if defined(__BIG_ENDIAN)
299 u16 byte_cnt; /* Descriptor buffer byte count */
300 u16 buf_size; /* Buffer size */
301 u32 cmd_sts; /* Descriptor command status */
302 u32 next_desc_ptr; /* Next descriptor pointer */
303 u32 buf_ptr; /* Descriptor buffer pointer */
307 u16 byte_cnt; /* buffer byte count */
308 u16 l4i_chk; /* CPU provided TCP checksum */
309 u32 cmd_sts; /* Command/status field */
310 u32 next_desc_ptr; /* Pointer to next descriptor */
311 u32 buf_ptr; /* pointer to buffer for this descriptor*/
313 #elif defined(__LITTLE_ENDIAN)
315 u32 cmd_sts; /* Descriptor command status */
316 u16 buf_size; /* Buffer size */
317 u16 byte_cnt; /* Descriptor buffer byte count */
318 u32 buf_ptr; /* Descriptor buffer pointer */
319 u32 next_desc_ptr; /* Next descriptor pointer */
323 u32 cmd_sts; /* Command/status field */
324 u16 l4i_chk; /* CPU provided TCP checksum */
325 u16 byte_cnt; /* buffer byte count */
326 u32 buf_ptr; /* pointer to buffer for this descriptor*/
327 u32 next_desc_ptr; /* Pointer to next descriptor */
330 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
333 /* Unified struct for Rx and Tx operations. The user is not required to */
334 /* be familier with neither Tx nor Rx descriptors. */
336 unsigned short byte_cnt; /* Descriptor buffer byte count */
337 unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
338 unsigned int cmd_sts; /* Descriptor command status */
339 dma_addr_t buf_ptr; /* Descriptor buffer pointer */
340 struct sk_buff *return_info; /* User resource return information */
344 /* global *******************************************************************/
345 struct mv643xx_shared_private {
346 void __iomem *eth_base;
348 /* used to protect SMI_REG, which is shared across ports */
357 /* per-port *****************************************************************/
358 struct mv643xx_mib_counters {
359 u64 good_octets_received;
360 u32 bad_octets_received;
361 u32 internal_mac_transmit_err;
362 u32 good_frames_received;
363 u32 bad_frames_received;
364 u32 broadcast_frames_received;
365 u32 multicast_frames_received;
366 u32 frames_64_octets;
367 u32 frames_65_to_127_octets;
368 u32 frames_128_to_255_octets;
369 u32 frames_256_to_511_octets;
370 u32 frames_512_to_1023_octets;
371 u32 frames_1024_to_max_octets;
372 u64 good_octets_sent;
373 u32 good_frames_sent;
374 u32 excessive_collision;
375 u32 multicast_frames_sent;
376 u32 broadcast_frames_sent;
377 u32 unrec_mac_control_received;
379 u32 good_fc_received;
381 u32 undersize_received;
382 u32 fragments_received;
383 u32 oversize_received;
385 u32 mac_receive_error;
391 struct mv643xx_private {
392 struct mv643xx_shared_private *shared;
393 int port_num; /* User Ethernet port number */
395 struct mv643xx_shared_private *shared_smi;
397 u32 rx_sram_addr; /* Base address of rx sram area */
398 u32 rx_sram_size; /* Size of rx sram area */
399 u32 tx_sram_addr; /* Base address of tx sram area */
400 u32 tx_sram_size; /* Size of tx sram area */
402 int rx_resource_err; /* Rx ring resource error flag */
404 /* Tx/Rx rings managment indexes fields. For driver use */
406 /* Next available and first returning Rx resource */
407 int rx_curr_desc_q, rx_used_desc_q;
409 /* Next available and first returning Tx resource */
410 int tx_curr_desc_q, tx_used_desc_q;
412 #ifdef MV643XX_TX_FAST_REFILL
413 u32 tx_clean_threshold;
416 struct eth_rx_desc *p_rx_desc_area;
417 dma_addr_t rx_desc_dma;
418 int rx_desc_area_size;
419 struct sk_buff **rx_skb;
421 struct eth_tx_desc *p_tx_desc_area;
422 dma_addr_t tx_desc_dma;
423 int tx_desc_area_size;
424 struct sk_buff **tx_skb;
426 struct work_struct tx_timeout_task;
428 struct net_device *dev;
429 struct napi_struct napi;
430 struct net_device_stats stats;
431 struct mv643xx_mib_counters mib_counters;
433 /* Size of Tx Ring per queue */
435 /* Number of tx descriptors in use */
437 /* Size of Rx Ring per queue */
439 /* Number of rx descriptors in use */
443 * Used in case RX Ring is empty, which can be caused when
444 * system does not have resources (skb's)
446 struct timer_list timeout;
450 struct mii_if_info mii;
454 /* port register accessors **************************************************/
455 static inline u32 rdl(struct mv643xx_private *mp, int offset)
457 return readl(mp->shared->eth_base + offset);
460 static inline void wrl(struct mv643xx_private *mp, int offset, u32 data)
462 writel(data, mp->shared->eth_base + offset);
466 /* rxq/txq helper functions *************************************************/
467 static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp,
470 wrl(mp, RXQ_COMMAND(mp->port_num), queues);
473 static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp)
475 unsigned int port_num = mp->port_num;
478 /* Stop Rx port activity. Check port Rx activity. */
479 queues = rdl(mp, RXQ_COMMAND(port_num)) & 0xFF;
481 /* Issue stop command for active queues only */
482 wrl(mp, RXQ_COMMAND(port_num), (queues << 8));
484 /* Wait for all Rx activity to terminate. */
485 /* Check port cause register that all Rx queues are stopped */
486 while (rdl(mp, RXQ_COMMAND(port_num)) & 0xFF)
487 udelay(PHY_WAIT_MICRO_SECONDS);
493 static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp,
496 wrl(mp, TXQ_COMMAND(mp->port_num), queues);
499 static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp)
501 unsigned int port_num = mp->port_num;
504 /* Stop Tx port activity. Check port Tx activity. */
505 queues = rdl(mp, TXQ_COMMAND(port_num)) & 0xFF;
507 /* Issue stop command for active queues only */
508 wrl(mp, TXQ_COMMAND(port_num), (queues << 8));
510 /* Wait for all Tx activity to terminate. */
511 /* Check port cause register that all Tx queues are stopped */
512 while (rdl(mp, TXQ_COMMAND(port_num)) & 0xFF)
513 udelay(PHY_WAIT_MICRO_SECONDS);
515 /* Wait for Tx FIFO to empty */
516 while (rdl(mp, PORT_STATUS(port_num)) & ETH_PORT_TX_FIFO_EMPTY)
517 udelay(PHY_WAIT_MICRO_SECONDS);
524 /* rx ***********************************************************************/
525 static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev);
528 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
531 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
532 * next 'used' descriptor and attached the returned buffer to it.
533 * In case the Rx ring was in "resource error" condition, where there are
534 * no available Rx resources, the function resets the resource error flag.
537 * struct mv643xx_private *mp Ethernet Port Control srtuct.
538 * struct pkt_info *p_pkt_info Information on returned buffer.
541 * New available Rx resource in Rx descriptor ring.
544 * ETH_ERROR in case the routine can not access Rx desc ring.
547 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
548 struct pkt_info *p_pkt_info)
550 int used_rx_desc; /* Where to return Rx resource */
551 volatile struct eth_rx_desc *p_used_rx_desc;
554 spin_lock_irqsave(&mp->lock, flags);
556 /* Get 'used' Rx descriptor */
557 used_rx_desc = mp->rx_used_desc_q;
558 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
560 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
561 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
562 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
564 /* Flush the write pipe */
566 /* Return the descriptor to DMA ownership */
568 p_used_rx_desc->cmd_sts =
569 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
572 /* Move the used descriptor pointer to the next descriptor */
573 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
575 /* Any Rx return cancels the Rx resource error status */
576 mp->rx_resource_err = 0;
578 spin_unlock_irqrestore(&mp->lock, flags);
584 * mv643xx_eth_rx_refill_descs
586 * Fills / refills RX queue on a certain gigabit ethernet port
588 * Input : pointer to ethernet interface network device structure
591 static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
593 struct mv643xx_private *mp = netdev_priv(dev);
594 struct pkt_info pkt_info;
598 while (mp->rx_desc_count < mp->rx_ring_size) {
599 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
603 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
605 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
606 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
607 pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
608 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
609 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
610 pkt_info.return_info = skb;
611 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
613 "%s: Error allocating RX Ring\n", dev->name);
616 skb_reserve(skb, ETH_HW_IP_ALIGN);
619 * If RX ring is empty of SKB, set a timer to try allocating
620 * again at a later time.
622 if (mp->rx_desc_count == 0) {
623 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
624 mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */
625 add_timer(&mp->timeout);
630 * mv643xx_eth_rx_refill_descs_timer_wrapper
632 * Timer routine to wake up RX queue filling task. This function is
633 * used only in case the RX queue is empty, and all alloc_skb has
634 * failed (due to out of memory event).
636 * Input : pointer to ethernet interface network device structure
639 static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
641 mv643xx_eth_rx_refill_descs((struct net_device *)data);
645 * eth_port_receive - Get received information from Rx ring.
648 * This routine returns the received data to the caller. There is no
649 * data copying during routine operation. All information is returned
650 * using pointer to packet information struct passed from the caller.
651 * If the routine exhausts Rx ring resources then the resource error flag
655 * struct mv643xx_private *mp Ethernet Port Control srtuct.
656 * struct pkt_info *p_pkt_info User packet buffer.
659 * Rx ring current and used indexes are updated.
662 * ETH_ERROR in case the routine can not access Rx desc ring.
663 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
664 * ETH_END_OF_JOB if there is no received data.
667 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
668 struct pkt_info *p_pkt_info)
670 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
671 volatile struct eth_rx_desc *p_rx_desc;
672 unsigned int command_status;
675 /* Do not process Rx ring in case of Rx ring resource error */
676 if (mp->rx_resource_err)
677 return ETH_QUEUE_FULL;
679 spin_lock_irqsave(&mp->lock, flags);
681 /* Get the Rx Desc ring 'curr and 'used' indexes */
682 rx_curr_desc = mp->rx_curr_desc_q;
683 rx_used_desc = mp->rx_used_desc_q;
685 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
687 /* The following parameters are used to save readings from memory */
688 command_status = p_rx_desc->cmd_sts;
691 /* Nothing to receive... */
692 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
693 spin_unlock_irqrestore(&mp->lock, flags);
694 return ETH_END_OF_JOB;
697 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
698 p_pkt_info->cmd_sts = command_status;
699 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
700 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
701 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
704 * Clean the return info field to indicate that the
705 * packet has been moved to the upper layers
707 mp->rx_skb[rx_curr_desc] = NULL;
709 /* Update current index in data structure */
710 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
711 mp->rx_curr_desc_q = rx_next_curr_desc;
713 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
714 if (rx_next_curr_desc == rx_used_desc)
715 mp->rx_resource_err = 1;
717 spin_unlock_irqrestore(&mp->lock, flags);
723 * mv643xx_eth_receive
725 * This function is forward packets that are received from the port's
726 * queues toward kernel core or FastRoute them to another interface.
728 * Input : dev - a pointer to the required interface
729 * max - maximum number to receive (0 means unlimted)
731 * Output : number of served packets
733 static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
735 struct mv643xx_private *mp = netdev_priv(dev);
736 struct net_device_stats *stats = &dev->stats;
737 unsigned int received_packets = 0;
739 struct pkt_info pkt_info;
741 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
742 dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE,
749 * Note byte count includes 4 byte CRC count
752 stats->rx_bytes += pkt_info.byte_cnt;
753 skb = pkt_info.return_info;
755 * In case received a packet without first / last bits on OR
756 * the error summary bit is on, the packets needs to be dropeed.
758 if (((pkt_info.cmd_sts
759 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
760 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
761 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
763 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
764 ETH_RX_LAST_DESC)) !=
765 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
768 "%s: Received packet spread "
769 "on multiple descriptors\n",
772 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
775 dev_kfree_skb_irq(skb);
778 * The -4 is for the CRC in the trailer of the
781 skb_put(skb, pkt_info.byte_cnt - 4);
783 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
784 skb->ip_summed = CHECKSUM_UNNECESSARY;
786 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
788 skb->protocol = eth_type_trans(skb, dev);
790 netif_receive_skb(skb);
795 dev->last_rx = jiffies;
797 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
799 return received_packets;
806 * This function is used in case of NAPI
808 static int mv643xx_poll(struct napi_struct *napi, int budget)
810 struct mv643xx_private *mp = container_of(napi, struct mv643xx_private, napi);
811 struct net_device *dev = mp->dev;
812 unsigned int port_num = mp->port_num;
815 #ifdef MV643XX_TX_FAST_REFILL
816 if (++mp->tx_clean_threshold > 5) {
817 mv643xx_eth_free_completed_tx_descs(dev);
818 mp->tx_clean_threshold = 0;
823 if ((rdl(mp, RXQ_CURRENT_DESC_PTR(port_num)))
824 != (u32) mp->rx_used_desc_q)
825 work_done = mv643xx_eth_receive_queue(dev, budget);
827 if (work_done < budget) {
828 netif_rx_complete(dev, napi);
829 wrl(mp, INT_CAUSE(port_num), 0);
830 wrl(mp, INT_CAUSE_EXT(port_num), 0);
831 wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT);
839 /* tx ***********************************************************************/
841 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments
843 * Hardware can't handle unaligned fragments smaller than 9 bytes.
844 * This helper function detects that case.
847 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
852 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
853 fragp = &skb_shinfo(skb)->frags[frag];
854 if (fragp->size <= 8 && fragp->page_offset & 0x7)
861 * eth_alloc_tx_desc_index - return the index of the next available tx desc
863 static int eth_alloc_tx_desc_index(struct mv643xx_private *mp)
867 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
869 tx_desc_curr = mp->tx_curr_desc_q;
870 mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size;
872 BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q);
878 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments.
880 * Ensure the data for each fragment to be transmitted is mapped properly,
881 * then fill in descriptors in the tx hw queue.
883 static void eth_tx_fill_frag_descs(struct mv643xx_private *mp,
888 struct eth_tx_desc *desc;
890 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
891 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
893 tx_index = eth_alloc_tx_desc_index(mp);
894 desc = &mp->p_tx_desc_area[tx_index];
896 desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA;
897 /* Last Frag enables interrupt and frees the skb */
898 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
899 desc->cmd_sts |= ETH_ZERO_PADDING |
901 ETH_TX_ENABLE_INTERRUPT;
902 mp->tx_skb[tx_index] = skb;
904 mp->tx_skb[tx_index] = NULL;
906 desc = &mp->p_tx_desc_area[tx_index];
908 desc->byte_cnt = this_frag->size;
909 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
910 this_frag->page_offset,
916 static inline __be16 sum16_as_be(__sum16 sum)
918 return (__force __be16)sum;
922 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
924 * Ensure the data for an skb to be transmitted is mapped properly,
925 * then fill in descriptors in the tx hw queue and start the hardware.
927 static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
931 struct eth_tx_desc *desc;
934 int nr_frags = skb_shinfo(skb)->nr_frags;
936 cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA;
938 tx_index = eth_alloc_tx_desc_index(mp);
939 desc = &mp->p_tx_desc_area[tx_index];
942 eth_tx_fill_frag_descs(mp, skb);
944 length = skb_headlen(skb);
945 mp->tx_skb[tx_index] = NULL;
947 cmd_sts |= ETH_ZERO_PADDING |
949 ETH_TX_ENABLE_INTERRUPT;
951 mp->tx_skb[tx_index] = skb;
954 desc->byte_cnt = length;
955 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
957 if (skb->ip_summed == CHECKSUM_PARTIAL) {
958 BUG_ON(skb->protocol != htons(ETH_P_IP));
960 cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM |
961 ETH_GEN_IP_V_4_CHECKSUM |
962 ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT;
964 switch (ip_hdr(skb)->protocol) {
966 cmd_sts |= ETH_UDP_FRAME;
967 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
970 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
976 /* Errata BTS #50, IHL must be 5 if no HW checksum */
977 cmd_sts |= 5 << ETH_TX_IHL_SHIFT;
981 /* ensure all other descriptors are written before first cmd_sts */
983 desc->cmd_sts = cmd_sts;
985 /* ensure all descriptors are written before poking hardware */
987 mv643xx_eth_port_enable_tx(mp, 1);
989 mp->tx_desc_count += nr_frags + 1;
993 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
996 static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
998 struct mv643xx_private *mp = netdev_priv(dev);
999 struct net_device_stats *stats = &dev->stats;
1000 unsigned long flags;
1002 BUG_ON(netif_queue_stopped(dev));
1004 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
1005 stats->tx_dropped++;
1006 printk(KERN_DEBUG "%s: failed to linearize tiny "
1007 "unaligned fragment\n", dev->name);
1008 return NETDEV_TX_BUSY;
1011 spin_lock_irqsave(&mp->lock, flags);
1013 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
1014 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
1015 netif_stop_queue(dev);
1016 spin_unlock_irqrestore(&mp->lock, flags);
1017 return NETDEV_TX_BUSY;
1020 eth_tx_submit_descs_for_skb(mp, skb);
1021 stats->tx_bytes += skb->len;
1022 stats->tx_packets++;
1023 dev->trans_start = jiffies;
1025 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
1026 netif_stop_queue(dev);
1028 spin_unlock_irqrestore(&mp->lock, flags);
1030 return NETDEV_TX_OK;
1034 /* mii management interface *************************************************/
1035 static int ethernet_phy_get(struct mv643xx_private *mp);
1038 * eth_port_read_smi_reg - Read PHY registers
1041 * This routine utilize the SMI interface to interact with the PHY in
1042 * order to perform PHY register read.
1045 * struct mv643xx_private *mp Ethernet Port.
1046 * unsigned int phy_reg PHY register address offset.
1047 * unsigned int *value Register value buffer.
1050 * Write the value of a specified PHY register into given buffer.
1053 * false if the PHY is busy or read data is not in valid state.
1057 static void eth_port_read_smi_reg(struct mv643xx_private *mp,
1058 unsigned int phy_reg, unsigned int *value)
1060 void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG;
1061 int phy_addr = ethernet_phy_get(mp);
1062 unsigned long flags;
1065 /* the SMI register is a shared resource */
1066 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
1068 /* wait for the SMI register to become available */
1069 for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) {
1070 if (i == PHY_WAIT_ITERATIONS) {
1071 printk("%s: PHY busy timeout\n", mp->dev->name);
1074 udelay(PHY_WAIT_MICRO_SECONDS);
1077 writel((phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ,
1080 /* now wait for the data to be valid */
1081 for (i = 0; !(readl(smi_reg) & ETH_SMI_READ_VALID); i++) {
1082 if (i == PHY_WAIT_ITERATIONS) {
1083 printk("%s: PHY read timeout\n", mp->dev->name);
1086 udelay(PHY_WAIT_MICRO_SECONDS);
1089 *value = readl(smi_reg) & 0xffff;
1091 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1095 * eth_port_write_smi_reg - Write to PHY registers
1098 * This routine utilize the SMI interface to interact with the PHY in
1099 * order to perform writes to PHY registers.
1102 * struct mv643xx_private *mp Ethernet Port.
1103 * unsigned int phy_reg PHY register address offset.
1104 * unsigned int value Register value.
1107 * Write the given value to the specified PHY register.
1110 * false if the PHY is busy.
1114 static void eth_port_write_smi_reg(struct mv643xx_private *mp,
1115 unsigned int phy_reg, unsigned int value)
1117 void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG;
1118 int phy_addr = ethernet_phy_get(mp);
1119 unsigned long flags;
1122 /* the SMI register is a shared resource */
1123 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
1125 /* wait for the SMI register to become available */
1126 for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) {
1127 if (i == PHY_WAIT_ITERATIONS) {
1128 printk("%s: PHY busy timeout\n", mp->dev->name);
1131 udelay(PHY_WAIT_MICRO_SECONDS);
1134 writel((phy_addr << 16) | (phy_reg << 21) |
1135 ETH_SMI_OPCODE_WRITE | (value & 0xffff), smi_reg);
1137 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1141 /* mib counters *************************************************************/
1143 * eth_clear_mib_counters - Clear all MIB counters
1146 * This function clears all MIB counters of a specific ethernet port.
1147 * A read from the MIB counter will reset the counter.
1150 * struct mv643xx_private *mp Ethernet Port.
1153 * After reading all MIB counters, the counters resets.
1156 * MIB counter value.
1159 static void eth_clear_mib_counters(struct mv643xx_private *mp)
1161 unsigned int port_num = mp->port_num;
1164 /* Perform dummy reads from MIB counters */
1165 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
1167 rdl(mp, MIB_COUNTERS(port_num) + i);
1170 static inline u32 read_mib(struct mv643xx_private *mp, int offset)
1172 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1175 static void eth_update_mib_counters(struct mv643xx_private *mp)
1177 struct mv643xx_mib_counters *p = &mp->mib_counters;
1180 p->good_octets_received +=
1181 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
1182 p->good_octets_received +=
1183 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
1185 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
1186 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
1188 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
1190 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
1191 p->good_octets_sent +=
1192 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
1194 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
1195 offset <= ETH_MIB_LATE_COLLISION;
1197 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
1201 /* ethtool ******************************************************************/
1202 struct mv643xx_stats {
1203 char stat_string[ETH_GSTRING_LEN];
1208 #define MV643XX_STAT(m) FIELD_SIZEOF(struct mv643xx_private, m), \
1209 offsetof(struct mv643xx_private, m)
1211 static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
1212 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
1213 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
1214 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
1215 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
1216 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
1217 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
1218 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
1219 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
1220 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
1221 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
1222 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
1223 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
1224 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
1225 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
1226 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
1227 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
1228 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
1229 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
1230 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
1231 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
1232 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
1233 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
1234 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
1235 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
1236 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
1237 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
1238 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
1239 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
1240 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
1241 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
1242 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
1243 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
1244 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
1245 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
1246 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
1247 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
1248 { "collision", MV643XX_STAT(mib_counters.collision) },
1249 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
1252 #define MV643XX_STATS_LEN ARRAY_SIZE(mv643xx_gstrings_stats)
1254 static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1256 struct mv643xx_private *mp = netdev_priv(dev);
1259 spin_lock_irq(&mp->lock);
1260 err = mii_ethtool_gset(&mp->mii, cmd);
1261 spin_unlock_irq(&mp->lock);
1263 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
1264 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1265 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1270 static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1272 struct mv643xx_private *mp = netdev_priv(dev);
1275 spin_lock_irq(&mp->lock);
1276 err = mii_ethtool_sset(&mp->mii, cmd);
1277 spin_unlock_irq(&mp->lock);
1282 static void mv643xx_get_drvinfo(struct net_device *netdev,
1283 struct ethtool_drvinfo *drvinfo)
1285 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
1286 strncpy(drvinfo->version, mv643xx_driver_version, 32);
1287 strncpy(drvinfo->fw_version, "N/A", 32);
1288 strncpy(drvinfo->bus_info, "mv643xx", 32);
1289 drvinfo->n_stats = MV643XX_STATS_LEN;
1292 static int mv643xx_eth_nway_restart(struct net_device *dev)
1294 struct mv643xx_private *mp = netdev_priv(dev);
1296 return mii_nway_restart(&mp->mii);
1299 static u32 mv643xx_eth_get_link(struct net_device *dev)
1301 struct mv643xx_private *mp = netdev_priv(dev);
1303 return mii_link_ok(&mp->mii);
1306 static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
1313 for (i=0; i < MV643XX_STATS_LEN; i++) {
1314 memcpy(data + i * ETH_GSTRING_LEN,
1315 mv643xx_gstrings_stats[i].stat_string,
1322 static void mv643xx_get_ethtool_stats(struct net_device *netdev,
1323 struct ethtool_stats *stats, uint64_t *data)
1325 struct mv643xx_private *mp = netdev->priv;
1328 eth_update_mib_counters(mp);
1330 for (i = 0; i < MV643XX_STATS_LEN; i++) {
1331 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
1332 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
1333 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
1337 static int mv643xx_get_sset_count(struct net_device *netdev, int sset)
1341 return MV643XX_STATS_LEN;
1347 static const struct ethtool_ops mv643xx_ethtool_ops = {
1348 .get_settings = mv643xx_get_settings,
1349 .set_settings = mv643xx_set_settings,
1350 .get_drvinfo = mv643xx_get_drvinfo,
1351 .get_link = mv643xx_eth_get_link,
1352 .set_sg = ethtool_op_set_sg,
1353 .get_sset_count = mv643xx_get_sset_count,
1354 .get_ethtool_stats = mv643xx_get_ethtool_stats,
1355 .get_strings = mv643xx_get_strings,
1356 .nway_reset = mv643xx_eth_nway_restart,
1360 /* address handling *********************************************************/
1362 * eth_port_uc_addr_get - Read the MAC address from the port's hw registers
1364 static void eth_port_uc_addr_get(struct mv643xx_private *mp,
1365 unsigned char *p_addr)
1367 unsigned int port_num = mp->port_num;
1371 mac_h = rdl(mp, MAC_ADDR_HIGH(port_num));
1372 mac_l = rdl(mp, MAC_ADDR_LOW(port_num));
1374 p_addr[0] = (mac_h >> 24) & 0xff;
1375 p_addr[1] = (mac_h >> 16) & 0xff;
1376 p_addr[2] = (mac_h >> 8) & 0xff;
1377 p_addr[3] = mac_h & 0xff;
1378 p_addr[4] = (mac_l >> 8) & 0xff;
1379 p_addr[5] = mac_l & 0xff;
1383 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
1386 * Go through all the DA filter tables (Unicast, Special Multicast &
1387 * Other Multicast) and set each entry to 0.
1390 * struct mv643xx_private *mp Ethernet Port.
1393 * Multicast and Unicast packets are rejected.
1398 static void eth_port_init_mac_tables(struct mv643xx_private *mp)
1400 unsigned int port_num = mp->port_num;
1403 /* Clear DA filter unicast table (Ex_dFUT) */
1404 for (table_index = 0; table_index <= 0xC; table_index += 4)
1405 wrl(mp, UNICAST_TABLE(port_num) + table_index, 0);
1407 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1408 /* Clear DA filter special multicast table (Ex_dFSMT) */
1409 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0);
1410 /* Clear DA filter other multicast table (Ex_dFOMT) */
1411 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0);
1416 * The entries in each table are indexed by a hash of a packet's MAC
1417 * address. One bit in each entry determines whether the packet is
1418 * accepted. There are 4 entries (each 8 bits wide) in each register
1419 * of the table. The bits in each entry are defined as follows:
1420 * 0 Accept=1, Drop=0
1421 * 3-1 Queue (ETH_Q0=0)
1424 static void eth_port_set_filter_table_entry(struct mv643xx_private *mp,
1425 int table, unsigned char entry)
1427 unsigned int table_reg;
1428 unsigned int tbl_offset;
1429 unsigned int reg_offset;
1431 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
1432 reg_offset = entry % 4; /* Entry offset within the register */
1434 /* Set "accepts frame bit" at specified table entry */
1435 table_reg = rdl(mp, table + tbl_offset);
1436 table_reg |= 0x01 << (8 * reg_offset);
1437 wrl(mp, table + tbl_offset, table_reg);
1441 * eth_port_uc_addr_set - Write a MAC address into the port's hw registers
1443 static void eth_port_uc_addr_set(struct mv643xx_private *mp,
1444 unsigned char *p_addr)
1446 unsigned int port_num = mp->port_num;
1451 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1452 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1455 wrl(mp, MAC_ADDR_LOW(port_num), mac_l);
1456 wrl(mp, MAC_ADDR_HIGH(port_num), mac_h);
1458 /* Accept frames with this address */
1459 table = UNICAST_TABLE(port_num);
1460 eth_port_set_filter_table_entry(mp, table, p_addr[5] & 0x0f);
1464 * mv643xx_eth_update_mac_address
1466 * Update the MAC address of the port in the address table
1468 * Input : pointer to ethernet interface network device structure
1471 static void mv643xx_eth_update_mac_address(struct net_device *dev)
1473 struct mv643xx_private *mp = netdev_priv(dev);
1475 eth_port_init_mac_tables(mp);
1476 eth_port_uc_addr_set(mp, dev->dev_addr);
1480 * mv643xx_eth_set_mac_address
1482 * Change the interface's mac address.
1483 * No special hardware thing should be done because interface is always
1484 * put in promiscuous mode.
1486 * Input : pointer to ethernet interface network device structure and
1487 * a pointer to the designated entry to be added to the cache.
1488 * Output : zero upon success, negative upon failure
1490 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1494 for (i = 0; i < 6; i++)
1495 /* +2 is for the offset of the HW addr type */
1496 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
1497 mv643xx_eth_update_mac_address(dev);
1502 * eth_port_mc_addr - Multicast address settings.
1504 * The MV device supports multicast using two tables:
1505 * 1) Special Multicast Table for MAC addresses of the form
1506 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
1507 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1508 * Table entries in the DA-Filter table.
1509 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
1510 * is used as an index to the Other Multicast Table entries in the
1511 * DA-Filter table. This function calculates the CRC-8bit value.
1512 * In either case, eth_port_set_filter_table_entry() is then called
1513 * to set to set the actual table entry.
1515 static void eth_port_mc_addr(struct mv643xx_private *mp, unsigned char *p_addr)
1517 unsigned int port_num = mp->port_num;
1520 unsigned char crc_result = 0;
1526 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
1527 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
1528 table = SPECIAL_MCAST_TABLE(port_num);
1529 eth_port_set_filter_table_entry(mp, table, p_addr[5]);
1533 /* Calculate CRC-8 out of the given address */
1534 mac_h = (p_addr[0] << 8) | (p_addr[1]);
1535 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
1536 (p_addr[4] << 8) | (p_addr[5] << 0);
1538 for (i = 0; i < 32; i++)
1539 mac_array[i] = (mac_l >> i) & 0x1;
1540 for (i = 32; i < 48; i++)
1541 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1543 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
1544 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
1545 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1546 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
1547 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
1549 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1550 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
1551 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1552 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
1553 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
1554 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1555 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
1557 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
1558 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
1559 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1560 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
1561 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
1562 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
1564 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1565 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
1566 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
1567 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
1568 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
1569 mac_array[3] ^ mac_array[2] ^ mac_array[1];
1571 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
1572 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
1573 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
1574 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
1575 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
1576 mac_array[3] ^ mac_array[2];
1578 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
1579 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
1580 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
1581 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
1582 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
1583 mac_array[4] ^ mac_array[3];
1585 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
1586 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
1587 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
1588 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
1589 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
1592 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
1593 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
1594 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
1595 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
1596 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
1598 for (i = 0; i < 8; i++)
1599 crc_result = crc_result | (crc[i] << i);
1601 table = OTHER_MCAST_TABLE(port_num);
1602 eth_port_set_filter_table_entry(mp, table, crc_result);
1606 * Set the entire multicast list based on dev->mc_list.
1608 static void eth_port_set_multicast_list(struct net_device *dev)
1611 struct dev_mc_list *mc_list;
1614 struct mv643xx_private *mp = netdev_priv(dev);
1615 unsigned int eth_port_num = mp->port_num;
1617 /* If the device is in promiscuous mode or in all multicast mode,
1618 * we will fully populate both multicast tables with accept.
1619 * This is guaranteed to yield a match on all multicast addresses...
1621 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
1622 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1623 /* Set all entries in DA filter special multicast
1625 * Set for ETH_Q0 for now
1627 * 0 Accept=1, Drop=0
1628 * 3-1 Queue ETH_Q0=0
1631 wrl(mp, SPECIAL_MCAST_TABLE(eth_port_num) + table_index, 0x01010101);
1633 /* Set all entries in DA filter other multicast
1635 * Set for ETH_Q0 for now
1637 * 0 Accept=1, Drop=0
1638 * 3-1 Queue ETH_Q0=0
1641 wrl(mp, OTHER_MCAST_TABLE(eth_port_num) + table_index, 0x01010101);
1646 /* We will clear out multicast tables every time we get the list.
1647 * Then add the entire new list...
1649 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1650 /* Clear DA filter special multicast table (Ex_dFSMT) */
1651 wrl(mp, SPECIAL_MCAST_TABLE(eth_port_num) + table_index, 0);
1653 /* Clear DA filter other multicast table (Ex_dFOMT) */
1654 wrl(mp, OTHER_MCAST_TABLE(eth_port_num) + table_index, 0);
1657 /* Get pointer to net_device multicast list and add each one... */
1658 for (i = 0, mc_list = dev->mc_list;
1659 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
1660 i++, mc_list = mc_list->next)
1661 if (mc_list->dmi_addrlen == 6)
1662 eth_port_mc_addr(mp, mc_list->dmi_addr);
1666 * mv643xx_eth_set_rx_mode
1668 * Change from promiscuos to regular rx mode
1670 * Input : pointer to ethernet interface network device structure
1673 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1675 struct mv643xx_private *mp = netdev_priv(dev);
1678 config_reg = rdl(mp, PORT_CONFIG(mp->port_num));
1679 if (dev->flags & IFF_PROMISC)
1680 config_reg |= UNICAST_PROMISCUOUS_MODE;
1682 config_reg &= ~UNICAST_PROMISCUOUS_MODE;
1683 wrl(mp, PORT_CONFIG(mp->port_num), config_reg);
1685 eth_port_set_multicast_list(dev);
1689 /* rx/tx queue initialisation ***********************************************/
1691 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
1694 * This function prepares a Rx chained list of descriptors and packet
1695 * buffers in a form of a ring. The routine must be called after port
1696 * initialization routine and before port start routine.
1697 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1698 * devices in the system (i.e. DRAM). This function uses the ethernet
1699 * struct 'virtual to physical' routine (set by the user) to set the ring
1700 * with physical addresses.
1703 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1706 * The routine updates the Ethernet port control struct with information
1707 * regarding the Rx descriptors and buffers.
1712 static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
1714 volatile struct eth_rx_desc *p_rx_desc;
1715 int rx_desc_num = mp->rx_ring_size;
1718 /* initialize the next_desc_ptr links in the Rx descriptors ring */
1719 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
1720 for (i = 0; i < rx_desc_num; i++) {
1721 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
1722 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
1725 /* Save Rx desc pointer to driver struct. */
1726 mp->rx_curr_desc_q = 0;
1727 mp->rx_used_desc_q = 0;
1729 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
1732 static void mv643xx_eth_free_rx_rings(struct net_device *dev)
1734 struct mv643xx_private *mp = netdev_priv(dev);
1737 /* Stop RX Queues */
1738 mv643xx_eth_port_disable_rx(mp);
1740 /* Free preallocated skb's on RX rings */
1741 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
1742 if (mp->rx_skb[curr]) {
1743 dev_kfree_skb(mp->rx_skb[curr]);
1744 mp->rx_desc_count--;
1748 if (mp->rx_desc_count)
1750 "%s: Error in freeing Rx Ring. %d skb's still"
1751 " stuck in RX Ring - ignoring them\n", dev->name,
1754 if (mp->rx_sram_size)
1755 iounmap(mp->p_rx_desc_area);
1757 dma_free_coherent(NULL, mp->rx_desc_area_size,
1758 mp->p_rx_desc_area, mp->rx_desc_dma);
1762 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
1765 * This function prepares a Tx chained list of descriptors and packet
1766 * buffers in a form of a ring. The routine must be called after port
1767 * initialization routine and before port start routine.
1768 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1769 * devices in the system (i.e. DRAM). This function uses the ethernet
1770 * struct 'virtual to physical' routine (set by the user) to set the ring
1771 * with physical addresses.
1774 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1777 * The routine updates the Ethernet port control struct with information
1778 * regarding the Tx descriptors and buffers.
1783 static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
1785 int tx_desc_num = mp->tx_ring_size;
1786 struct eth_tx_desc *p_tx_desc;
1789 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
1790 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
1791 for (i = 0; i < tx_desc_num; i++) {
1792 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
1793 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
1796 mp->tx_curr_desc_q = 0;
1797 mp->tx_used_desc_q = 0;
1799 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
1803 * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors
1805 * If force is non-zero, frees uncompleted descriptors as well
1807 static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
1809 struct mv643xx_private *mp = netdev_priv(dev);
1810 struct eth_tx_desc *desc;
1812 struct sk_buff *skb;
1813 unsigned long flags;
1819 while (mp->tx_desc_count > 0) {
1820 spin_lock_irqsave(&mp->lock, flags);
1822 /* tx_desc_count might have changed before acquiring the lock */
1823 if (mp->tx_desc_count <= 0) {
1824 spin_unlock_irqrestore(&mp->lock, flags);
1828 tx_index = mp->tx_used_desc_q;
1829 desc = &mp->p_tx_desc_area[tx_index];
1830 cmd_sts = desc->cmd_sts;
1832 if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) {
1833 spin_unlock_irqrestore(&mp->lock, flags);
1837 mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size;
1838 mp->tx_desc_count--;
1840 addr = desc->buf_ptr;
1841 count = desc->byte_cnt;
1842 skb = mp->tx_skb[tx_index];
1844 mp->tx_skb[tx_index] = NULL;
1846 if (cmd_sts & ETH_ERROR_SUMMARY) {
1847 printk("%s: Error in TX\n", dev->name);
1848 dev->stats.tx_errors++;
1851 spin_unlock_irqrestore(&mp->lock, flags);
1853 if (cmd_sts & ETH_TX_FIRST_DESC)
1854 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1856 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1859 dev_kfree_skb_irq(skb);
1867 static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
1869 struct mv643xx_private *mp = netdev_priv(dev);
1871 if (mv643xx_eth_free_tx_descs(dev, 0) &&
1872 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
1873 netif_wake_queue(dev);
1876 static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
1878 mv643xx_eth_free_tx_descs(dev, 1);
1881 static void mv643xx_eth_free_tx_rings(struct net_device *dev)
1883 struct mv643xx_private *mp = netdev_priv(dev);
1885 /* Stop Tx Queues */
1886 mv643xx_eth_port_disable_tx(mp);
1888 /* Free outstanding skb's on TX ring */
1889 mv643xx_eth_free_all_tx_descs(dev);
1891 BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q);
1894 if (mp->tx_sram_size)
1895 iounmap(mp->p_tx_desc_area);
1897 dma_free_coherent(NULL, mp->tx_desc_area_size,
1898 mp->p_tx_desc_area, mp->tx_desc_dma);
1902 /* netdev ops and related ***************************************************/
1903 static void eth_port_reset(struct mv643xx_private *mp);
1905 /* Set the mv643xx port configuration register for the speed/duplex mode. */
1906 static void mv643xx_eth_update_pscr(struct net_device *dev,
1907 struct ethtool_cmd *ecmd)
1909 struct mv643xx_private *mp = netdev_priv(dev);
1910 int port_num = mp->port_num;
1912 unsigned int queues;
1914 o_pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num));
1917 /* clear speed, duplex and rx buffer size fields */
1918 n_pscr &= ~(SET_MII_SPEED_TO_100 |
1919 SET_GMII_SPEED_TO_1000 |
1920 SET_FULL_DUPLEX_MODE |
1921 MAX_RX_PACKET_MASK);
1923 if (ecmd->duplex == DUPLEX_FULL)
1924 n_pscr |= SET_FULL_DUPLEX_MODE;
1926 if (ecmd->speed == SPEED_1000)
1927 n_pscr |= SET_GMII_SPEED_TO_1000 |
1928 MAX_RX_PACKET_9700BYTE;
1930 if (ecmd->speed == SPEED_100)
1931 n_pscr |= SET_MII_SPEED_TO_100;
1932 n_pscr |= MAX_RX_PACKET_1522BYTE;
1935 if (n_pscr != o_pscr) {
1936 if ((o_pscr & SERIAL_PORT_ENABLE) == 0)
1937 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1939 queues = mv643xx_eth_port_disable_tx(mp);
1941 o_pscr &= ~SERIAL_PORT_ENABLE;
1942 wrl(mp, PORT_SERIAL_CONTROL(port_num), o_pscr);
1943 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1944 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1946 mv643xx_eth_port_enable_tx(mp, queues);
1952 * mv643xx_eth_int_handler
1954 * Main interrupt handler for the gigbit ethernet ports
1956 * Input : irq - irq number (not used)
1957 * dev_id - a pointer to the required interface's data structure
1962 static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
1964 struct net_device *dev = (struct net_device *)dev_id;
1965 struct mv643xx_private *mp = netdev_priv(dev);
1966 u32 eth_int_cause, eth_int_cause_ext = 0;
1967 unsigned int port_num = mp->port_num;
1969 /* Read interrupt cause registers */
1970 eth_int_cause = rdl(mp, INT_CAUSE(port_num)) & (INT_RX | INT_EXT);
1971 if (eth_int_cause & INT_EXT) {
1972 eth_int_cause_ext = rdl(mp, INT_CAUSE_EXT(port_num))
1973 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1974 wrl(mp, INT_CAUSE_EXT(port_num), ~eth_int_cause_ext);
1977 /* PHY status changed */
1978 if (eth_int_cause_ext & (INT_EXT_LINK | INT_EXT_PHY)) {
1979 struct ethtool_cmd cmd;
1981 if (mii_link_ok(&mp->mii)) {
1982 mii_ethtool_gset(&mp->mii, &cmd);
1983 mv643xx_eth_update_pscr(dev, &cmd);
1984 mv643xx_eth_port_enable_tx(mp, 1);
1985 if (!netif_carrier_ok(dev)) {
1986 netif_carrier_on(dev);
1987 if (mp->tx_ring_size - mp->tx_desc_count >=
1989 netif_wake_queue(dev);
1991 } else if (netif_carrier_ok(dev)) {
1992 netif_stop_queue(dev);
1993 netif_carrier_off(dev);
1998 if (eth_int_cause & INT_RX) {
1999 /* schedule the NAPI poll routine to maintain port */
2000 wrl(mp, INT_MASK(port_num), 0x00000000);
2002 /* wait for previous write to complete */
2003 rdl(mp, INT_MASK(port_num));
2005 netif_rx_schedule(dev, &mp->napi);
2008 if (eth_int_cause & INT_RX)
2009 mv643xx_eth_receive_queue(dev, INT_MAX);
2011 if (eth_int_cause_ext & INT_EXT_TX)
2012 mv643xx_eth_free_completed_tx_descs(dev);
2015 * If no real interrupt occured, exit.
2016 * This can happen when using gigE interrupt coalescing mechanism.
2018 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
2025 * ethernet_phy_reset - Reset Ethernet port PHY.
2028 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2031 * struct mv643xx_private *mp Ethernet Port.
2040 static void ethernet_phy_reset(struct mv643xx_private *mp)
2042 unsigned int phy_reg_data;
2045 eth_port_read_smi_reg(mp, 0, &phy_reg_data);
2046 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2047 eth_port_write_smi_reg(mp, 0, phy_reg_data);
2049 /* wait for PHY to come out of reset */
2052 eth_port_read_smi_reg(mp, 0, &phy_reg_data);
2053 } while (phy_reg_data & 0x8000);
2057 * eth_port_start - Start the Ethernet port activity.
2060 * This routine prepares the Ethernet port for Rx and Tx activity:
2061 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
2062 * has been initialized a descriptor's ring (using
2063 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
2064 * 2. Initialize and enable the Ethernet configuration port by writing to
2065 * the port's configuration and command registers.
2066 * 3. Initialize and enable the SDMA by writing to the SDMA's
2067 * configuration and command registers. After completing these steps,
2068 * the ethernet port SDMA can starts to perform Rx and Tx activities.
2070 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
2071 * to calling this function (use ether_init_tx_desc_ring for Tx queues
2072 * and ether_init_rx_desc_ring for Rx queues).
2075 * dev - a pointer to the required interface
2078 * Ethernet port is ready to receive and transmit.
2083 static void eth_port_start(struct net_device *dev)
2085 struct mv643xx_private *mp = netdev_priv(dev);
2086 unsigned int port_num = mp->port_num;
2087 int tx_curr_desc, rx_curr_desc;
2089 struct ethtool_cmd ethtool_cmd;
2091 /* Assignment of Tx CTRP of given queue */
2092 tx_curr_desc = mp->tx_curr_desc_q;
2093 wrl(mp, TXQ_CURRENT_DESC_PTR(port_num),
2094 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
2096 /* Assignment of Rx CRDP of given queue */
2097 rx_curr_desc = mp->rx_curr_desc_q;
2098 wrl(mp, RXQ_CURRENT_DESC_PTR(port_num),
2099 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
2101 /* Add the assigned Ethernet address to the port's address table */
2102 eth_port_uc_addr_set(mp, dev->dev_addr);
2105 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2106 * frames to RX queue #0.
2108 wrl(mp, PORT_CONFIG(port_num), 0x00000000);
2111 * Treat BPDUs as normal multicasts, and disable partition mode.
2113 wrl(mp, PORT_CONFIG_EXT(port_num), 0x00000000);
2115 pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num));
2117 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
2118 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
2120 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
2121 DISABLE_AUTO_NEG_SPEED_GMII |
2122 DISABLE_AUTO_NEG_FOR_DUPLEX |
2123 DO_NOT_FORCE_LINK_FAIL |
2124 SERIAL_PORT_CONTROL_RESERVED;
2126 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
2128 pscr |= SERIAL_PORT_ENABLE;
2129 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
2131 /* Assign port SDMA configuration */
2132 wrl(mp, SDMA_CONFIG(port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
2134 /* Enable port Rx. */
2135 mv643xx_eth_port_enable_rx(mp, 1);
2137 /* Disable port bandwidth limits by clearing MTU register */
2138 wrl(mp, TX_BW_MTU(port_num), 0);
2140 /* save phy settings across reset */
2141 mv643xx_get_settings(dev, ðtool_cmd);
2142 ethernet_phy_reset(mp);
2143 mv643xx_set_settings(dev, ðtool_cmd);
2149 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
2152 * This routine sets the RX coalescing interrupt mechanism parameter.
2153 * This parameter is a timeout counter, that counts in 64 t_clk
2154 * chunks ; that when timeout event occurs a maskable interrupt
2156 * The parameter is calculated using the tClk of the MV-643xx chip
2157 * , and the required delay of the interrupt in usec.
2160 * struct mv643xx_private *mp Ethernet port
2161 * unsigned int delay Delay in usec
2164 * Interrupt coalescing mechanism value is set in MV-643xx chip.
2167 * The interrupt coalescing value set in the gigE port.
2170 static unsigned int eth_port_set_rx_coal(struct mv643xx_private *mp,
2173 unsigned int port_num = mp->port_num;
2174 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2176 /* Set RX Coalescing mechanism */
2177 wrl(mp, SDMA_CONFIG(port_num),
2178 ((coal & 0x3fff) << 8) |
2179 (rdl(mp, SDMA_CONFIG(port_num))
2187 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
2190 * This routine sets the TX coalescing interrupt mechanism parameter.
2191 * This parameter is a timeout counter, that counts in 64 t_clk
2192 * chunks ; that when timeout event occurs a maskable interrupt
2194 * The parameter is calculated using the t_cLK frequency of the
2195 * MV-643xx chip and the required delay in the interrupt in uSec
2198 * struct mv643xx_private *mp Ethernet port
2199 * unsigned int delay Delay in uSeconds
2202 * Interrupt coalescing mechanism value is set in MV-643xx chip.
2205 * The interrupt coalescing value set in the gigE port.
2208 static unsigned int eth_port_set_tx_coal(struct mv643xx_private *mp,
2211 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2213 /* Set TX Coalescing mechanism */
2214 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), coal << 4);
2220 * eth_port_init - Initialize the Ethernet port driver
2223 * This function prepares the ethernet port to start its activity:
2224 * 1) Completes the ethernet port driver struct initialization toward port
2226 * 2) Resets the device to a quiescent state in case of warm reboot.
2227 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
2228 * 4) Clean MAC tables. The reset status of those tables is unknown.
2229 * 5) Set PHY address.
2230 * Note: Call this routine prior to eth_port_start routine and after
2231 * setting user values in the user fields of Ethernet port control
2235 * struct mv643xx_private *mp Ethernet port control struct
2243 static void eth_port_init(struct mv643xx_private *mp)
2245 mp->rx_resource_err = 0;
2249 eth_port_init_mac_tables(mp);
2255 * This function is called when openning the network device. The function
2256 * should initialize all the hardware, initialize cyclic Rx/Tx
2257 * descriptors chain and buffers and allocate an IRQ to the network
2260 * Input : a pointer to the network device structure
2262 * Output : zero of success , nonzero if fails.
2265 static int mv643xx_eth_open(struct net_device *dev)
2267 struct mv643xx_private *mp = netdev_priv(dev);
2268 unsigned int port_num = mp->port_num;
2272 /* Clear any pending ethernet port interrupts */
2273 wrl(mp, INT_CAUSE(port_num), 0);
2274 wrl(mp, INT_CAUSE_EXT(port_num), 0);
2275 /* wait for previous write to complete */
2276 rdl(mp, INT_CAUSE_EXT(port_num));
2278 err = request_irq(dev->irq, mv643xx_eth_int_handler,
2279 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
2281 printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name);
2287 memset(&mp->timeout, 0, sizeof(struct timer_list));
2288 mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper;
2289 mp->timeout.data = (unsigned long)dev;
2291 /* Allocate RX and TX skb rings */
2292 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
2295 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
2299 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
2302 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
2304 goto out_free_rx_skb;
2307 /* Allocate TX ring */
2308 mp->tx_desc_count = 0;
2309 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
2310 mp->tx_desc_area_size = size;
2312 if (mp->tx_sram_size) {
2313 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
2315 mp->tx_desc_dma = mp->tx_sram_addr;
2317 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
2321 if (!mp->p_tx_desc_area) {
2322 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
2325 goto out_free_tx_skb;
2327 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
2328 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
2330 ether_init_tx_desc_ring(mp);
2332 /* Allocate RX ring */
2333 mp->rx_desc_count = 0;
2334 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
2335 mp->rx_desc_area_size = size;
2337 if (mp->rx_sram_size) {
2338 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
2340 mp->rx_desc_dma = mp->rx_sram_addr;
2342 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
2346 if (!mp->p_rx_desc_area) {
2347 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
2349 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
2351 if (mp->rx_sram_size)
2352 iounmap(mp->p_tx_desc_area);
2354 dma_free_coherent(NULL, mp->tx_desc_area_size,
2355 mp->p_tx_desc_area, mp->tx_desc_dma);
2357 goto out_free_tx_skb;
2359 memset((void *)mp->p_rx_desc_area, 0, size);
2361 ether_init_rx_desc_ring(mp);
2363 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
2366 napi_enable(&mp->napi);
2369 eth_port_start(dev);
2371 /* Interrupt Coalescing */
2375 eth_port_set_rx_coal(mp, MV643XX_RX_COAL);
2379 eth_port_set_tx_coal(mp, MV643XX_TX_COAL);
2381 /* Unmask phy and link status changes interrupts */
2382 wrl(mp, INT_MASK_EXT(port_num), INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
2384 /* Unmask RX buffer and TX end interrupt */
2385 wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT);
2394 free_irq(dev->irq, dev);
2400 * eth_port_reset - Reset Ethernet port
2403 * This routine resets the chip by aborting any SDMA engine activity and
2404 * clearing the MIB counters. The Receiver and the Transmit unit are in
2405 * idle state after this command is performed and the port is disabled.
2408 * struct mv643xx_private *mp Ethernet Port.
2411 * Channel activity is halted.
2417 static void eth_port_reset(struct mv643xx_private *mp)
2419 unsigned int port_num = mp->port_num;
2420 unsigned int reg_data;
2422 mv643xx_eth_port_disable_tx(mp);
2423 mv643xx_eth_port_disable_rx(mp);
2425 /* Clear all MIB counters */
2426 eth_clear_mib_counters(mp);
2428 /* Reset the Enable bit in the Configuration Register */
2429 reg_data = rdl(mp, PORT_SERIAL_CONTROL(port_num));
2430 reg_data &= ~(SERIAL_PORT_ENABLE |
2431 DO_NOT_FORCE_LINK_FAIL |
2433 wrl(mp, PORT_SERIAL_CONTROL(port_num), reg_data);
2439 * This function is used when closing the network device.
2440 * It updates the hardware,
2441 * release all memory that holds buffers and descriptors and release the IRQ.
2442 * Input : a pointer to the device structure
2443 * Output : zero if success , nonzero if fails
2446 static int mv643xx_eth_stop(struct net_device *dev)
2448 struct mv643xx_private *mp = netdev_priv(dev);
2449 unsigned int port_num = mp->port_num;
2451 /* Mask all interrupts on ethernet port */
2452 wrl(mp, INT_MASK(port_num), 0x00000000);
2453 /* wait for previous write to complete */
2454 rdl(mp, INT_MASK(port_num));
2457 napi_disable(&mp->napi);
2459 netif_carrier_off(dev);
2460 netif_stop_queue(dev);
2464 mv643xx_eth_free_tx_rings(dev);
2465 mv643xx_eth_free_rx_rings(dev);
2467 free_irq(dev->irq, dev);
2472 static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2474 struct mv643xx_private *mp = netdev_priv(dev);
2476 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2480 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
2482 * Input : pointer to ethernet interface network device structure
2484 * Output : 0 upon success, -EINVAL upon failure
2486 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2488 if ((new_mtu > 9500) || (new_mtu < 64))
2492 if (!netif_running(dev))
2496 * Stop and then re-open the interface. This will allocate RX
2497 * skbs of the new MTU.
2498 * There is a possible danger that the open will not succeed,
2499 * due to memory being full, which might fail the open function.
2501 mv643xx_eth_stop(dev);
2502 if (mv643xx_eth_open(dev)) {
2503 printk(KERN_ERR "%s: Fatal error on opening device\n",
2511 * mv643xx_eth_tx_timeout_task
2513 * Actual routine to reset the adapter when a timeout on Tx has occurred
2515 static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
2517 struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private,
2519 struct net_device *dev = mp->dev;
2521 if (!netif_running(dev))
2524 netif_stop_queue(dev);
2527 eth_port_start(dev);
2529 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
2530 netif_wake_queue(dev);
2534 * mv643xx_eth_tx_timeout
2536 * Called upon a timeout on transmitting a packet
2538 * Input : pointer to ethernet interface network device structure.
2541 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2543 struct mv643xx_private *mp = netdev_priv(dev);
2545 printk(KERN_INFO "%s: TX timeout ", dev->name);
2547 /* Do the reset outside of interrupt context */
2548 schedule_work(&mp->tx_timeout_task);
2551 #ifdef CONFIG_NET_POLL_CONTROLLER
2552 static void mv643xx_netpoll(struct net_device *netdev)
2554 struct mv643xx_private *mp = netdev_priv(netdev);
2555 int port_num = mp->port_num;
2557 wrl(mp, INT_MASK(port_num), 0x00000000);
2558 /* wait for previous write to complete */
2559 rdl(mp, INT_MASK(port_num));
2561 mv643xx_eth_int_handler(netdev->irq, netdev);
2563 wrl(mp, INT_MASK(port_num), INT_RX | INT_CAUSE_EXT);
2568 * Wrappers for MII support library.
2570 static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location)
2572 struct mv643xx_private *mp = netdev_priv(dev);
2575 eth_port_read_smi_reg(mp, location, &val);
2579 static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val)
2581 struct mv643xx_private *mp = netdev_priv(dev);
2582 eth_port_write_smi_reg(mp, location, val);
2586 /* platform glue ************************************************************/
2587 static void mv643xx_eth_conf_mbus_windows(struct mv643xx_shared_private *msp,
2588 struct mbus_dram_target_info *dram)
2590 void __iomem *base = msp->eth_base;
2595 for (i = 0; i < 6; i++) {
2596 writel(0, base + WINDOW_BASE(i));
2597 writel(0, base + WINDOW_SIZE(i));
2599 writel(0, base + WINDOW_REMAP_HIGH(i));
2605 for (i = 0; i < dram->num_cs; i++) {
2606 struct mbus_dram_window *cs = dram->cs + i;
2608 writel((cs->base & 0xffff0000) |
2609 (cs->mbus_attr << 8) |
2610 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2611 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2613 win_enable &= ~(1 << i);
2614 win_protect |= 3 << (2 * i);
2617 writel(win_enable, base + WINDOW_BAR_ENABLE);
2618 msp->win_protect = win_protect;
2621 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2623 static int mv643xx_version_printed = 0;
2624 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2625 struct mv643xx_shared_private *msp;
2626 struct resource *res;
2629 if (!mv643xx_version_printed++)
2630 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
2633 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2638 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2641 memset(msp, 0, sizeof(*msp));
2643 msp->eth_base = ioremap(res->start, res->end - res->start + 1);
2644 if (msp->eth_base == NULL)
2647 spin_lock_init(&msp->phy_lock);
2648 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2650 platform_set_drvdata(pdev, msp);
2653 * (Re-)program MBUS remapping windows if we are asked to.
2655 if (pd != NULL && pd->dram != NULL)
2656 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2666 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2668 struct mv643xx_shared_private *msp = platform_get_drvdata(pdev);
2670 iounmap(msp->eth_base);
2676 static struct platform_driver mv643xx_eth_shared_driver = {
2677 .probe = mv643xx_eth_shared_probe,
2678 .remove = mv643xx_eth_shared_remove,
2680 .name = MV643XX_ETH_SHARED_NAME,
2681 .owner = THIS_MODULE,
2686 * ethernet_phy_set - Set the ethernet port PHY address.
2689 * This routine sets the given ethernet port PHY address.
2692 * struct mv643xx_private *mp Ethernet Port.
2693 * int phy_addr PHY address.
2702 static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr)
2705 int addr_shift = 5 * mp->port_num;
2707 reg_data = rdl(mp, PHY_ADDR);
2708 reg_data &= ~(0x1f << addr_shift);
2709 reg_data |= (phy_addr & 0x1f) << addr_shift;
2710 wrl(mp, PHY_ADDR, reg_data);
2714 * ethernet_phy_get - Get the ethernet port PHY address.
2717 * This routine returns the given ethernet port PHY address.
2720 * struct mv643xx_private *mp Ethernet Port.
2729 static int ethernet_phy_get(struct mv643xx_private *mp)
2731 unsigned int reg_data;
2733 reg_data = rdl(mp, PHY_ADDR);
2735 return ((reg_data >> (5 * mp->port_num)) & 0x1f);
2739 * ethernet_phy_detect - Detect whether a phy is present
2742 * This function tests whether there is a PHY present on
2743 * the specified port.
2746 * struct mv643xx_private *mp Ethernet Port.
2753 * -ENODEV on failure
2756 static int ethernet_phy_detect(struct mv643xx_private *mp)
2758 unsigned int phy_reg_data0;
2761 eth_port_read_smi_reg(mp, 0, &phy_reg_data0);
2762 auto_neg = phy_reg_data0 & 0x1000;
2763 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2764 eth_port_write_smi_reg(mp, 0, phy_reg_data0);
2766 eth_port_read_smi_reg(mp, 0, &phy_reg_data0);
2767 if ((phy_reg_data0 & 0x1000) == auto_neg)
2768 return -ENODEV; /* change didn't take */
2770 phy_reg_data0 ^= 0x1000;
2771 eth_port_write_smi_reg(mp, 0, phy_reg_data0);
2775 static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
2776 int speed, int duplex,
2777 struct ethtool_cmd *cmd)
2779 struct mv643xx_private *mp = netdev_priv(dev);
2781 memset(cmd, 0, sizeof(*cmd));
2783 cmd->port = PORT_MII;
2784 cmd->transceiver = XCVR_INTERNAL;
2785 cmd->phy_address = phy_address;
2788 cmd->autoneg = AUTONEG_ENABLE;
2789 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
2790 cmd->speed = SPEED_100;
2791 cmd->advertising = ADVERTISED_10baseT_Half |
2792 ADVERTISED_10baseT_Full |
2793 ADVERTISED_100baseT_Half |
2794 ADVERTISED_100baseT_Full;
2795 if (mp->mii.supports_gmii)
2796 cmd->advertising |= ADVERTISED_1000baseT_Full;
2798 cmd->autoneg = AUTONEG_DISABLE;
2800 cmd->duplex = duplex;
2807 * First function called after registering the network device.
2808 * It's purpose is to initialize the device as an ethernet device,
2809 * fill the ethernet device structure with pointers * to functions,
2810 * and set the MAC address of the interface
2812 * Input : struct device *
2813 * Output : -ENOMEM if failed , 0 if success
2815 static int mv643xx_eth_probe(struct platform_device *pdev)
2817 struct mv643xx_eth_platform_data *pd;
2819 struct mv643xx_private *mp;
2820 struct net_device *dev;
2822 struct resource *res;
2824 struct ethtool_cmd cmd;
2825 int duplex = DUPLEX_HALF;
2826 int speed = 0; /* default to auto-negotiation */
2827 DECLARE_MAC_BUF(mac);
2829 pd = pdev->dev.platform_data;
2831 printk(KERN_ERR "No mv643xx_eth_platform_data\n");
2835 if (pd->shared == NULL) {
2836 printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n");
2840 dev = alloc_etherdev(sizeof(struct mv643xx_private));
2844 platform_set_drvdata(pdev, dev);
2846 mp = netdev_priv(dev);
2849 netif_napi_add(dev, &mp->napi, mv643xx_poll, 64);
2852 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2854 dev->irq = res->start;
2856 dev->open = mv643xx_eth_open;
2857 dev->stop = mv643xx_eth_stop;
2858 dev->hard_start_xmit = mv643xx_eth_start_xmit;
2859 dev->set_mac_address = mv643xx_eth_set_mac_address;
2860 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2862 /* No need to Tx Timeout */
2863 dev->tx_timeout = mv643xx_eth_tx_timeout;
2865 #ifdef CONFIG_NET_POLL_CONTROLLER
2866 dev->poll_controller = mv643xx_netpoll;
2869 dev->watchdog_timeo = 2 * HZ;
2871 dev->change_mtu = mv643xx_eth_change_mtu;
2872 dev->do_ioctl = mv643xx_eth_do_ioctl;
2873 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
2875 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2876 #ifdef MAX_SKB_FRAGS
2878 * Zero copy can only work if we use Discovery II memory. Else, we will
2879 * have to map the buffers to ISA memory which is only 16 MB
2881 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2885 /* Configure the timeout task */
2886 INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
2888 spin_lock_init(&mp->lock);
2890 mp->shared = platform_get_drvdata(pd->shared);
2891 port_num = mp->port_num = pd->port_number;
2893 if (mp->shared->win_protect)
2894 wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect);
2896 mp->shared_smi = mp->shared;
2897 if (pd->shared_smi != NULL)
2898 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2900 /* set default config values */
2901 eth_port_uc_addr_get(mp, dev->dev_addr);
2902 mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
2903 mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
2905 if (is_valid_ether_addr(pd->mac_addr))
2906 memcpy(dev->dev_addr, pd->mac_addr, 6);
2908 if (pd->phy_addr || pd->force_phy_addr)
2909 ethernet_phy_set(mp, pd->phy_addr);
2911 if (pd->rx_queue_size)
2912 mp->rx_ring_size = pd->rx_queue_size;
2914 if (pd->tx_queue_size)
2915 mp->tx_ring_size = pd->tx_queue_size;
2917 if (pd->tx_sram_size) {
2918 mp->tx_sram_size = pd->tx_sram_size;
2919 mp->tx_sram_addr = pd->tx_sram_addr;
2922 if (pd->rx_sram_size) {
2923 mp->rx_sram_size = pd->rx_sram_size;
2924 mp->rx_sram_addr = pd->rx_sram_addr;
2927 duplex = pd->duplex;
2930 /* Hook up MII support for ethtool */
2932 mp->mii.mdio_read = mv643xx_mdio_read;
2933 mp->mii.mdio_write = mv643xx_mdio_write;
2934 mp->mii.phy_id = ethernet_phy_get(mp);
2935 mp->mii.phy_id_mask = 0x3f;
2936 mp->mii.reg_num_mask = 0x1f;
2938 err = ethernet_phy_detect(mp);
2940 pr_debug("%s: No PHY detected at addr %d\n",
2941 dev->name, ethernet_phy_get(mp));
2945 ethernet_phy_reset(mp);
2946 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2947 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
2948 mv643xx_eth_update_pscr(dev, &cmd);
2949 mv643xx_set_settings(dev, &cmd);
2951 SET_NETDEV_DEV(dev, &pdev->dev);
2952 err = register_netdev(dev);
2958 "%s: port %d with MAC address %s\n",
2959 dev->name, port_num, print_mac(mac, p));
2961 if (dev->features & NETIF_F_SG)
2962 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
2964 if (dev->features & NETIF_F_IP_CSUM)
2965 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
2968 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2969 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
2973 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
2978 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
2981 if (mp->tx_sram_size > 0)
2982 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
2992 static int mv643xx_eth_remove(struct platform_device *pdev)
2994 struct net_device *dev = platform_get_drvdata(pdev);
2996 unregister_netdev(dev);
2997 flush_scheduled_work();
3000 platform_set_drvdata(pdev, NULL);
3004 static void mv643xx_eth_shutdown(struct platform_device *pdev)
3006 struct net_device *dev = platform_get_drvdata(pdev);
3007 struct mv643xx_private *mp = netdev_priv(dev);
3008 unsigned int port_num = mp->port_num;
3010 /* Mask all interrupts on ethernet port */
3011 wrl(mp, INT_MASK(port_num), 0);
3012 rdl(mp, INT_MASK(port_num));
3017 static struct platform_driver mv643xx_eth_driver = {
3018 .probe = mv643xx_eth_probe,
3019 .remove = mv643xx_eth_remove,
3020 .shutdown = mv643xx_eth_shutdown,
3022 .name = MV643XX_ETH_NAME,
3023 .owner = THIS_MODULE,
3028 * mv643xx_init_module
3030 * Registers the network drivers into the Linux kernel
3036 static int __init mv643xx_init_module(void)
3040 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3042 rc = platform_driver_register(&mv643xx_eth_driver);
3044 platform_driver_unregister(&mv643xx_eth_shared_driver);
3050 * mv643xx_cleanup_module
3052 * Registers the network drivers into the Linux kernel
3058 static void __exit mv643xx_cleanup_module(void)
3060 platform_driver_unregister(&mv643xx_eth_driver);
3061 platform_driver_unregister(&mv643xx_eth_shared_driver);
3064 module_init(mv643xx_init_module);
3065 module_exit(mv643xx_cleanup_module);
3067 MODULE_LICENSE("GPL");
3068 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
3069 " and Dale Farnsworth");
3070 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3071 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
3072 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);