drivers/net: fixed drivers that support netpoll use ndo_start_xmit()
[linux-2.6.git] / drivers / net / mlx4 / en_tx.c
1 /*
2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  *
32  */
33
34 #include <asm/page.h>
35 #include <linux/mlx4/cq.h>
36 #include <linux/mlx4/qp.h>
37 #include <linux/skbuff.h>
38 #include <linux/if_vlan.h>
39 #include <linux/vmalloc.h>
40
41 #include "mlx4_en.h"
42
43 enum {
44         MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
45 };
46
47 static int inline_thold __read_mostly = MAX_INLINE;
48
49 module_param_named(inline_thold, inline_thold, int, 0444);
50 MODULE_PARM_DESC(inline_thold, "treshold for using inline data");
51
52 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
53                            struct mlx4_en_tx_ring *ring, u32 size,
54                            u16 stride)
55 {
56         struct mlx4_en_dev *mdev = priv->mdev;
57         int tmp;
58         int err;
59
60         ring->size = size;
61         ring->size_mask = size - 1;
62         ring->stride = stride;
63
64         inline_thold = min(inline_thold, MAX_INLINE);
65
66         spin_lock_init(&ring->comp_lock);
67
68         tmp = size * sizeof(struct mlx4_en_tx_info);
69         ring->tx_info = vmalloc(tmp);
70         if (!ring->tx_info) {
71                 en_err(priv, "Failed allocating tx_info ring\n");
72                 return -ENOMEM;
73         }
74         en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
75                  ring->tx_info, tmp);
76
77         ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL);
78         if (!ring->bounce_buf) {
79                 en_err(priv, "Failed allocating bounce buffer\n");
80                 err = -ENOMEM;
81                 goto err_tx;
82         }
83         ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE);
84
85         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size,
86                                  2 * PAGE_SIZE);
87         if (err) {
88                 en_err(priv, "Failed allocating hwq resources\n");
89                 goto err_bounce;
90         }
91
92         err = mlx4_en_map_buffer(&ring->wqres.buf);
93         if (err) {
94                 en_err(priv, "Failed to map TX buffer\n");
95                 goto err_hwq_res;
96         }
97
98         ring->buf = ring->wqres.buf.direct.buf;
99
100         en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d "
101                "buf_size:%d dma:%llx\n", ring, ring->buf, ring->size,
102                ring->buf_size, (unsigned long long) ring->wqres.buf.direct.map);
103
104         err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn);
105         if (err) {
106                 en_err(priv, "Failed reserving qp for tx ring.\n");
107                 goto err_map;
108         }
109
110         err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp);
111         if (err) {
112                 en_err(priv, "Failed allocating qp %d\n", ring->qpn);
113                 goto err_reserve;
114         }
115         ring->qp.event = mlx4_en_sqp_event;
116
117         return 0;
118
119 err_reserve:
120         mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
121 err_map:
122         mlx4_en_unmap_buffer(&ring->wqres.buf);
123 err_hwq_res:
124         mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
125 err_bounce:
126         kfree(ring->bounce_buf);
127         ring->bounce_buf = NULL;
128 err_tx:
129         vfree(ring->tx_info);
130         ring->tx_info = NULL;
131         return err;
132 }
133
134 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
135                              struct mlx4_en_tx_ring *ring)
136 {
137         struct mlx4_en_dev *mdev = priv->mdev;
138         en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
139
140         mlx4_qp_remove(mdev->dev, &ring->qp);
141         mlx4_qp_free(mdev->dev, &ring->qp);
142         mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
143         mlx4_en_unmap_buffer(&ring->wqres.buf);
144         mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
145         kfree(ring->bounce_buf);
146         ring->bounce_buf = NULL;
147         vfree(ring->tx_info);
148         ring->tx_info = NULL;
149 }
150
151 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
152                              struct mlx4_en_tx_ring *ring,
153                              int cq, int srqn)
154 {
155         struct mlx4_en_dev *mdev = priv->mdev;
156         int err;
157
158         ring->cqn = cq;
159         ring->prod = 0;
160         ring->cons = 0xffffffff;
161         ring->last_nr_txbb = 1;
162         ring->poll_cnt = 0;
163         ring->blocked = 0;
164         memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info));
165         memset(ring->buf, 0, ring->buf_size);
166
167         ring->qp_state = MLX4_QP_STATE_RST;
168         ring->doorbell_qpn = swab32(ring->qp.qpn << 8);
169
170         mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn,
171                                 ring->cqn, srqn, &ring->context);
172
173         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context,
174                                &ring->qp, &ring->qp_state);
175
176         return err;
177 }
178
179 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
180                                 struct mlx4_en_tx_ring *ring)
181 {
182         struct mlx4_en_dev *mdev = priv->mdev;
183
184         mlx4_qp_modify(mdev->dev, NULL, ring->qp_state,
185                        MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp);
186 }
187
188
189 static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
190                                 struct mlx4_en_tx_ring *ring,
191                                 int index, u8 owner)
192 {
193         struct mlx4_en_dev *mdev = priv->mdev;
194         struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
195         struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
196         struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
197         struct sk_buff *skb = tx_info->skb;
198         struct skb_frag_struct *frag;
199         void *end = ring->buf + ring->buf_size;
200         int frags = skb_shinfo(skb)->nr_frags;
201         int i;
202         __be32 *ptr = (__be32 *)tx_desc;
203         __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT));
204
205         /* Optimize the common case when there are no wraparounds */
206         if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
207                 if (!tx_info->inl) {
208                         if (tx_info->linear) {
209                                 pci_unmap_single(mdev->pdev,
210                                         (dma_addr_t) be64_to_cpu(data->addr),
211                                          be32_to_cpu(data->byte_count),
212                                          PCI_DMA_TODEVICE);
213                                 ++data;
214                         }
215
216                         for (i = 0; i < frags; i++) {
217                                 frag = &skb_shinfo(skb)->frags[i];
218                                 pci_unmap_page(mdev->pdev,
219                                         (dma_addr_t) be64_to_cpu(data[i].addr),
220                                         frag->size, PCI_DMA_TODEVICE);
221                         }
222                 }
223                 /* Stamp the freed descriptor */
224                 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) {
225                         *ptr = stamp;
226                         ptr += STAMP_DWORDS;
227                 }
228
229         } else {
230                 if (!tx_info->inl) {
231                         if ((void *) data >= end) {
232                                 data = (struct mlx4_wqe_data_seg *)
233                                                 (ring->buf + ((void *) data - end));
234                         }
235
236                         if (tx_info->linear) {
237                                 pci_unmap_single(mdev->pdev,
238                                         (dma_addr_t) be64_to_cpu(data->addr),
239                                          be32_to_cpu(data->byte_count),
240                                          PCI_DMA_TODEVICE);
241                                 ++data;
242                         }
243
244                         for (i = 0; i < frags; i++) {
245                                 /* Check for wraparound before unmapping */
246                                 if ((void *) data >= end)
247                                         data = (struct mlx4_wqe_data_seg *) ring->buf;
248                                 frag = &skb_shinfo(skb)->frags[i];
249                                 pci_unmap_page(mdev->pdev,
250                                         (dma_addr_t) be64_to_cpu(data->addr),
251                                          frag->size, PCI_DMA_TODEVICE);
252                                 ++data;
253                         }
254                 }
255                 /* Stamp the freed descriptor */
256                 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) {
257                         *ptr = stamp;
258                         ptr += STAMP_DWORDS;
259                         if ((void *) ptr >= end) {
260                                 ptr = ring->buf;
261                                 stamp ^= cpu_to_be32(0x80000000);
262                         }
263                 }
264
265         }
266         dev_kfree_skb_any(skb);
267         return tx_info->nr_txbb;
268 }
269
270
271 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
272 {
273         struct mlx4_en_priv *priv = netdev_priv(dev);
274         int cnt = 0;
275
276         /* Skip last polled descriptor */
277         ring->cons += ring->last_nr_txbb;
278         en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
279                  ring->cons, ring->prod);
280
281         if ((u32) (ring->prod - ring->cons) > ring->size) {
282                 if (netif_msg_tx_err(priv))
283                         en_warn(priv, "Tx consumer passed producer!\n");
284                 return 0;
285         }
286
287         while (ring->cons != ring->prod) {
288                 ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring,
289                                                 ring->cons & ring->size_mask,
290                                                 !!(ring->cons & ring->size));
291                 ring->cons += ring->last_nr_txbb;
292                 cnt++;
293         }
294
295         if (cnt)
296                 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
297
298         return cnt;
299 }
300
301
302 static void mlx4_en_process_tx_cq(struct net_device *dev, struct mlx4_en_cq *cq)
303 {
304         struct mlx4_en_priv *priv = netdev_priv(dev);
305         struct mlx4_cq *mcq = &cq->mcq;
306         struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring];
307         struct mlx4_cqe *cqe = cq->buf;
308         u16 index;
309         u16 new_index;
310         u32 txbbs_skipped = 0;
311         u32 cq_last_sav;
312
313         /* index always points to the first TXBB of the last polled descriptor */
314         index = ring->cons & ring->size_mask;
315         new_index = be16_to_cpu(cqe->wqe_index) & ring->size_mask;
316         if (index == new_index)
317                 return;
318
319         if (!priv->port_up)
320                 return;
321
322         /*
323          * We use a two-stage loop:
324          * - the first samples the HW-updated CQE
325          * - the second frees TXBBs until the last sample
326          * This lets us amortize CQE cache misses, while still polling the CQ
327          * until is quiescent.
328          */
329         cq_last_sav = mcq->cons_index;
330         do {
331                 do {
332                         /* Skip over last polled CQE */
333                         index = (index + ring->last_nr_txbb) & ring->size_mask;
334                         txbbs_skipped += ring->last_nr_txbb;
335
336                         /* Poll next CQE */
337                         ring->last_nr_txbb = mlx4_en_free_tx_desc(
338                                                 priv, ring, index,
339                                                 !!((ring->cons + txbbs_skipped) &
340                                                    ring->size));
341                         ++mcq->cons_index;
342
343                 } while (index != new_index);
344
345                 new_index = be16_to_cpu(cqe->wqe_index) & ring->size_mask;
346         } while (index != new_index);
347         AVG_PERF_COUNTER(priv->pstats.tx_coal_avg,
348                          (u32) (mcq->cons_index - cq_last_sav));
349
350         /*
351          * To prevent CQ overflow we first update CQ consumer and only then
352          * the ring consumer.
353          */
354         mlx4_cq_set_ci(mcq);
355         wmb();
356         ring->cons += txbbs_skipped;
357
358         /* Wakeup Tx queue if this ring stopped it */
359         if (unlikely(ring->blocked)) {
360                 if ((u32) (ring->prod - ring->cons) <=
361                      ring->size - HEADROOM - MAX_DESC_TXBBS) {
362                         ring->blocked = 0;
363                         netif_tx_wake_queue(netdev_get_tx_queue(dev, cq->ring));
364                         priv->port_stats.wake_queue++;
365                 }
366         }
367 }
368
369 void mlx4_en_tx_irq(struct mlx4_cq *mcq)
370 {
371         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
372         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
373         struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring];
374
375         if (!spin_trylock(&ring->comp_lock))
376                 return;
377         mlx4_en_process_tx_cq(cq->dev, cq);
378         mod_timer(&cq->timer, jiffies + 1);
379         spin_unlock(&ring->comp_lock);
380 }
381
382
383 void mlx4_en_poll_tx_cq(unsigned long data)
384 {
385         struct mlx4_en_cq *cq = (struct mlx4_en_cq *) data;
386         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
387         struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring];
388         u32 inflight;
389
390         INC_PERF_COUNTER(priv->pstats.tx_poll);
391
392         if (!spin_trylock_irq(&ring->comp_lock)) {
393                 mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
394                 return;
395         }
396         mlx4_en_process_tx_cq(cq->dev, cq);
397         inflight = (u32) (ring->prod - ring->cons - ring->last_nr_txbb);
398
399         /* If there are still packets in flight and the timer has not already
400          * been scheduled by the Tx routine then schedule it here to guarantee
401          * completion processing of these packets */
402         if (inflight && priv->port_up)
403                 mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
404
405         spin_unlock_irq(&ring->comp_lock);
406 }
407
408 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv,
409                                                       struct mlx4_en_tx_ring *ring,
410                                                       u32 index,
411                                                       unsigned int desc_size)
412 {
413         u32 copy = (ring->size - index) * TXBB_SIZE;
414         int i;
415
416         for (i = desc_size - copy - 4; i >= 0; i -= 4) {
417                 if ((i & (TXBB_SIZE - 1)) == 0)
418                         wmb();
419
420                 *((u32 *) (ring->buf + i)) =
421                         *((u32 *) (ring->bounce_buf + copy + i));
422         }
423
424         for (i = copy - 4; i >= 4 ; i -= 4) {
425                 if ((i & (TXBB_SIZE - 1)) == 0)
426                         wmb();
427
428                 *((u32 *) (ring->buf + index * TXBB_SIZE + i)) =
429                         *((u32 *) (ring->bounce_buf + i));
430         }
431
432         /* Return real descriptor location */
433         return ring->buf + index * TXBB_SIZE;
434 }
435
436 static inline void mlx4_en_xmit_poll(struct mlx4_en_priv *priv, int tx_ind)
437 {
438         struct mlx4_en_cq *cq = &priv->tx_cq[tx_ind];
439         struct mlx4_en_tx_ring *ring = &priv->tx_ring[tx_ind];
440         unsigned long flags;
441
442         /* If we don't have a pending timer, set one up to catch our recent
443            post in case the interface becomes idle */
444         if (!timer_pending(&cq->timer))
445                 mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
446
447         /* Poll the CQ every mlx4_en_TX_MODER_POLL packets */
448         if ((++ring->poll_cnt & (MLX4_EN_TX_POLL_MODER - 1)) == 0)
449                 if (spin_trylock_irqsave(&ring->comp_lock, flags)) {
450                         mlx4_en_process_tx_cq(priv->dev, cq);
451                         spin_unlock_irqrestore(&ring->comp_lock, flags);
452                 }
453 }
454
455 static void *get_frag_ptr(struct sk_buff *skb)
456 {
457         struct skb_frag_struct *frag =  &skb_shinfo(skb)->frags[0];
458         struct page *page = frag->page;
459         void *ptr;
460
461         ptr = page_address(page);
462         if (unlikely(!ptr))
463                 return NULL;
464
465         return ptr + frag->page_offset;
466 }
467
468 static int is_inline(struct sk_buff *skb, void **pfrag)
469 {
470         void *ptr;
471
472         if (inline_thold && !skb_is_gso(skb) && skb->len <= inline_thold) {
473                 if (skb_shinfo(skb)->nr_frags == 1) {
474                         ptr = get_frag_ptr(skb);
475                         if (unlikely(!ptr))
476                                 return 0;
477
478                         if (pfrag)
479                                 *pfrag = ptr;
480
481                         return 1;
482                 } else if (unlikely(skb_shinfo(skb)->nr_frags))
483                         return 0;
484                 else
485                         return 1;
486         }
487
488         return 0;
489 }
490
491 static int inline_size(struct sk_buff *skb)
492 {
493         if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg)
494             <= MLX4_INLINE_ALIGN)
495                 return ALIGN(skb->len + CTRL_SIZE +
496                              sizeof(struct mlx4_wqe_inline_seg), 16);
497         else
498                 return ALIGN(skb->len + CTRL_SIZE + 2 *
499                              sizeof(struct mlx4_wqe_inline_seg), 16);
500 }
501
502 static int get_real_size(struct sk_buff *skb, struct net_device *dev,
503                          int *lso_header_size)
504 {
505         struct mlx4_en_priv *priv = netdev_priv(dev);
506         int real_size;
507
508         if (skb_is_gso(skb)) {
509                 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb);
510                 real_size = CTRL_SIZE + skb_shinfo(skb)->nr_frags * DS_SIZE +
511                         ALIGN(*lso_header_size + 4, DS_SIZE);
512                 if (unlikely(*lso_header_size != skb_headlen(skb))) {
513                         /* We add a segment for the skb linear buffer only if
514                          * it contains data */
515                         if (*lso_header_size < skb_headlen(skb))
516                                 real_size += DS_SIZE;
517                         else {
518                                 if (netif_msg_tx_err(priv))
519                                         en_warn(priv, "Non-linear headers\n");
520                                 return 0;
521                         }
522                 }
523         } else {
524                 *lso_header_size = 0;
525                 if (!is_inline(skb, NULL))
526                         real_size = CTRL_SIZE + (skb_shinfo(skb)->nr_frags + 1) * DS_SIZE;
527                 else
528                         real_size = inline_size(skb);
529         }
530
531         return real_size;
532 }
533
534 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, struct sk_buff *skb,
535                              int real_size, u16 *vlan_tag, int tx_ind, void *fragptr)
536 {
537         struct mlx4_wqe_inline_seg *inl = &tx_desc->inl;
538         int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl;
539
540         if (skb->len <= spc) {
541                 inl->byte_count = cpu_to_be32(1 << 31 | skb->len);
542                 skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb));
543                 if (skb_shinfo(skb)->nr_frags)
544                         memcpy(((void *)(inl + 1)) + skb_headlen(skb), fragptr,
545                                skb_shinfo(skb)->frags[0].size);
546
547         } else {
548                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
549                 if (skb_headlen(skb) <= spc) {
550                         skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb));
551                         if (skb_headlen(skb) < spc) {
552                                 memcpy(((void *)(inl + 1)) + skb_headlen(skb),
553                                         fragptr, spc - skb_headlen(skb));
554                                 fragptr +=  spc - skb_headlen(skb);
555                         }
556                         inl = (void *) (inl + 1) + spc;
557                         memcpy(((void *)(inl + 1)), fragptr, skb->len - spc);
558                 } else {
559                         skb_copy_from_linear_data(skb, inl + 1, spc);
560                         inl = (void *) (inl + 1) + spc;
561                         skb_copy_from_linear_data_offset(skb, spc, inl + 1,
562                                         skb_headlen(skb) - spc);
563                         if (skb_shinfo(skb)->nr_frags)
564                                 memcpy(((void *)(inl + 1)) + skb_headlen(skb) - spc,
565                                         fragptr, skb_shinfo(skb)->frags[0].size);
566                 }
567
568                 wmb();
569                 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc));
570         }
571         tx_desc->ctrl.vlan_tag = cpu_to_be16(*vlan_tag);
572         tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * !!(*vlan_tag);
573         tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f;
574 }
575
576 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb)
577 {
578         struct mlx4_en_priv *priv = netdev_priv(dev);
579         u16 vlan_tag = 0;
580
581         /* If we support per priority flow control and the packet contains
582          * a vlan tag, send the packet to the TX ring assigned to that priority
583          */
584         if (priv->prof->rx_ppp && priv->vlgrp && vlan_tx_tag_present(skb)) {
585                 vlan_tag = vlan_tx_tag_get(skb);
586                 return MLX4_EN_NUM_TX_RINGS + (vlan_tag >> 13);
587         }
588
589         return skb_tx_hash(dev, skb);
590 }
591
592 int mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
593 {
594         struct mlx4_en_priv *priv = netdev_priv(dev);
595         struct mlx4_en_dev *mdev = priv->mdev;
596         struct mlx4_en_tx_ring *ring;
597         struct mlx4_en_cq *cq;
598         struct mlx4_en_tx_desc *tx_desc;
599         struct mlx4_wqe_data_seg *data;
600         struct skb_frag_struct *frag;
601         struct mlx4_en_tx_info *tx_info;
602         int tx_ind = 0;
603         int nr_txbb;
604         int desc_size;
605         int real_size;
606         dma_addr_t dma;
607         u32 index;
608         __be32 op_own;
609         u16 vlan_tag = 0;
610         int i;
611         int lso_header_size;
612         void *fragptr;
613
614         real_size = get_real_size(skb, dev, &lso_header_size);
615         if (unlikely(!real_size))
616                 goto tx_drop;
617
618         /* Allign descriptor to TXBB size */
619         desc_size = ALIGN(real_size, TXBB_SIZE);
620         nr_txbb = desc_size / TXBB_SIZE;
621         if (unlikely(nr_txbb > MAX_DESC_TXBBS)) {
622                 if (netif_msg_tx_err(priv))
623                         en_warn(priv, "Oversized header or SG list\n");
624                 goto tx_drop;
625         }
626
627         tx_ind = skb->queue_mapping;
628         ring = &priv->tx_ring[tx_ind];
629         if (priv->vlgrp && vlan_tx_tag_present(skb))
630                 vlan_tag = vlan_tx_tag_get(skb);
631
632         /* Check available TXBBs And 2K spare for prefetch */
633         if (unlikely(((int)(ring->prod - ring->cons)) >
634                      ring->size - HEADROOM - MAX_DESC_TXBBS)) {
635                 /* every full Tx ring stops queue */
636                 netif_tx_stop_queue(netdev_get_tx_queue(dev, tx_ind));
637                 ring->blocked = 1;
638                 priv->port_stats.queue_stopped++;
639
640                 /* Use interrupts to find out when queue opened */
641                 cq = &priv->tx_cq[tx_ind];
642                 mlx4_en_arm_cq(priv, cq);
643                 return NETDEV_TX_BUSY;
644         }
645
646         /* Track current inflight packets for performance analysis */
647         AVG_PERF_COUNTER(priv->pstats.inflight_avg,
648                          (u32) (ring->prod - ring->cons - 1));
649
650         /* Packet is good - grab an index and transmit it */
651         index = ring->prod & ring->size_mask;
652
653         /* See if we have enough space for whole descriptor TXBB for setting
654          * SW ownership on next descriptor; if not, use a bounce buffer. */
655         if (likely(index + nr_txbb <= ring->size))
656                 tx_desc = ring->buf + index * TXBB_SIZE;
657         else
658                 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
659
660         /* Save skb in tx_info ring */
661         tx_info = &ring->tx_info[index];
662         tx_info->skb = skb;
663         tx_info->nr_txbb = nr_txbb;
664
665         /* Prepare ctrl segement apart opcode+ownership, which depends on
666          * whether LSO is used */
667         tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag);
668         tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * !!vlan_tag;
669         tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f;
670         tx_desc->ctrl.srcrb_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
671                                                 MLX4_WQE_CTRL_SOLICITED);
672         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
673                 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
674                                                          MLX4_WQE_CTRL_TCP_UDP_CSUM);
675                 priv->port_stats.tx_chksum_offload++;
676         }
677
678         /* Handle LSO (TSO) packets */
679         if (lso_header_size) {
680                 /* Mark opcode as LSO */
681                 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) |
682                         ((ring->prod & ring->size) ?
683                                 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
684
685                 /* Fill in the LSO prefix */
686                 tx_desc->lso.mss_hdr_size = cpu_to_be32(
687                         skb_shinfo(skb)->gso_size << 16 | lso_header_size);
688
689                 /* Copy headers;
690                  * note that we already verified that it is linear */
691                 memcpy(tx_desc->lso.header, skb->data, lso_header_size);
692                 data = ((void *) &tx_desc->lso +
693                         ALIGN(lso_header_size + 4, DS_SIZE));
694
695                 priv->port_stats.tso_packets++;
696                 i = ((skb->len - lso_header_size) / skb_shinfo(skb)->gso_size) +
697                         !!((skb->len - lso_header_size) % skb_shinfo(skb)->gso_size);
698                 ring->bytes += skb->len + (i - 1) * lso_header_size;
699                 ring->packets += i;
700         } else {
701                 /* Normal (Non LSO) packet */
702                 op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
703                         ((ring->prod & ring->size) ?
704                          cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
705                 data = &tx_desc->data;
706                 ring->bytes += max(skb->len, (unsigned int) ETH_ZLEN);
707                 ring->packets++;
708
709         }
710         AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len);
711
712
713         /* valid only for none inline segments */
714         tx_info->data_offset = (void *) data - (void *) tx_desc;
715
716         tx_info->linear = (lso_header_size < skb_headlen(skb) && !is_inline(skb, NULL)) ? 1 : 0;
717         data += skb_shinfo(skb)->nr_frags + tx_info->linear - 1;
718
719         if (!is_inline(skb, &fragptr)) {
720                 /* Map fragments */
721                 for (i = skb_shinfo(skb)->nr_frags - 1; i >= 0; i--) {
722                         frag = &skb_shinfo(skb)->frags[i];
723                         dma = pci_map_page(mdev->dev->pdev, frag->page, frag->page_offset,
724                                            frag->size, PCI_DMA_TODEVICE);
725                         data->addr = cpu_to_be64(dma);
726                         data->lkey = cpu_to_be32(mdev->mr.key);
727                         wmb();
728                         data->byte_count = cpu_to_be32(frag->size);
729                         --data;
730                 }
731
732                 /* Map linear part */
733                 if (tx_info->linear) {
734                         dma = pci_map_single(mdev->dev->pdev, skb->data + lso_header_size,
735                                              skb_headlen(skb) - lso_header_size, PCI_DMA_TODEVICE);
736                         data->addr = cpu_to_be64(dma);
737                         data->lkey = cpu_to_be32(mdev->mr.key);
738                         wmb();
739                         data->byte_count = cpu_to_be32(skb_headlen(skb) - lso_header_size);
740                 }
741                 tx_info->inl = 0;
742         } else {
743                 build_inline_wqe(tx_desc, skb, real_size, &vlan_tag, tx_ind, fragptr);
744                 tx_info->inl = 1;
745         }
746
747         ring->prod += nr_txbb;
748
749         /* If we used a bounce buffer then copy descriptor back into place */
750         if (tx_desc == (struct mlx4_en_tx_desc *) ring->bounce_buf)
751                 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
752
753         /* Run destructor before passing skb to HW */
754         if (likely(!skb_shared(skb)))
755                 skb_orphan(skb);
756
757         /* Ensure new descirptor hits memory
758          * before setting ownership of this descriptor to HW */
759         wmb();
760         tx_desc->ctrl.owner_opcode = op_own;
761
762         /* Ring doorbell! */
763         wmb();
764         writel(ring->doorbell_qpn, mdev->uar_map + MLX4_SEND_DOORBELL);
765
766         /* Poll CQ here */
767         mlx4_en_xmit_poll(priv, tx_ind);
768
769         return 0;
770
771 tx_drop:
772         dev_kfree_skb_any(skb);
773         priv->stats.tx_dropped++;
774         return NETDEV_TX_OK;
775 }
776