korina: disable napi on close and restart
[linux-2.6.git] / drivers / net / korina.c
1 /*
2  *  Driver for the IDT RC32434 (Korina) on-chip ethernet controller.
3  *
4  *  Copyright 2004 IDT Inc. (rischelp@idt.com)
5  *  Copyright 2006 Felix Fietkau <nbd@openwrt.org>
6  *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
7  *
8  *  This program is free software; you can redistribute  it and/or modify it
9  *  under  the terms of  the GNU General  Public License as published by the
10  *  Free Software Foundation;  either version 2 of the  License, or (at your
11  *  option) any later version.
12  *
13  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
14  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
15  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
16  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
17  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
19  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
21  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23  *
24  *  You should have received a copy of the  GNU General Public License along
25  *  with this program; if not, write  to the Free Software Foundation, Inc.,
26  *  675 Mass Ave, Cambridge, MA 02139, USA.
27  *
28  *  Writing to a DMA status register:
29  *
30  *  When writing to the status register, you should mask the bit you have
31  *  been testing the status register with. Both Tx and Rx DMA registers
32  *  should stick to this procedure.
33  */
34
35 #include <linux/module.h>
36 #include <linux/kernel.h>
37 #include <linux/moduleparam.h>
38 #include <linux/sched.h>
39 #include <linux/ctype.h>
40 #include <linux/types.h>
41 #include <linux/interrupt.h>
42 #include <linux/init.h>
43 #include <linux/ioport.h>
44 #include <linux/in.h>
45 #include <linux/slab.h>
46 #include <linux/string.h>
47 #include <linux/delay.h>
48 #include <linux/netdevice.h>
49 #include <linux/etherdevice.h>
50 #include <linux/skbuff.h>
51 #include <linux/errno.h>
52 #include <linux/platform_device.h>
53 #include <linux/mii.h>
54 #include <linux/ethtool.h>
55 #include <linux/crc32.h>
56
57 #include <asm/bootinfo.h>
58 #include <asm/system.h>
59 #include <asm/bitops.h>
60 #include <asm/pgtable.h>
61 #include <asm/segment.h>
62 #include <asm/io.h>
63 #include <asm/dma.h>
64
65 #include <asm/mach-rc32434/rb.h>
66 #include <asm/mach-rc32434/rc32434.h>
67 #include <asm/mach-rc32434/eth.h>
68 #include <asm/mach-rc32434/dma_v.h>
69
70 #define DRV_NAME        "korina"
71 #define DRV_VERSION     "0.10"
72 #define DRV_RELDATE     "04Mar2008"
73
74 #define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
75                                    ((dev)->dev_addr[1]))
76 #define STATION_ADDRESS_LOW(dev)  (((dev)->dev_addr[2] << 24) | \
77                                    ((dev)->dev_addr[3] << 16) | \
78                                    ((dev)->dev_addr[4] << 8)  | \
79                                    ((dev)->dev_addr[5]))
80
81 #define MII_CLOCK 1250000       /* no more than 2.5MHz */
82
83 /* the following must be powers of two */
84 #define KORINA_NUM_RDS  64  /* number of receive descriptors */
85 #define KORINA_NUM_TDS  64  /* number of transmit descriptors */
86
87 /* KORINA_RBSIZE is the hardware's default maximum receive
88  * frame size in bytes. Having this hardcoded means that there
89  * is no support for MTU sizes greater than 1500. */
90 #define KORINA_RBSIZE   1536 /* size of one resource buffer = Ether MTU */
91 #define KORINA_RDS_MASK (KORINA_NUM_RDS - 1)
92 #define KORINA_TDS_MASK (KORINA_NUM_TDS - 1)
93 #define RD_RING_SIZE    (KORINA_NUM_RDS * sizeof(struct dma_desc))
94 #define TD_RING_SIZE    (KORINA_NUM_TDS * sizeof(struct dma_desc))
95
96 #define TX_TIMEOUT      (6000 * HZ / 1000)
97
98 enum chain_status { desc_filled, desc_empty };
99 #define IS_DMA_FINISHED(X)   (((X) & (DMA_DESC_FINI)) != 0)
100 #define IS_DMA_DONE(X)   (((X) & (DMA_DESC_DONE)) != 0)
101 #define RCVPKT_LENGTH(X)     (((X) & ETH_RX_LEN) >> ETH_RX_LEN_BIT)
102
103 /* Information that need to be kept for each board. */
104 struct korina_private {
105         struct eth_regs *eth_regs;
106         struct dma_reg *rx_dma_regs;
107         struct dma_reg *tx_dma_regs;
108         struct dma_desc *td_ring; /* transmit descriptor ring */
109         struct dma_desc *rd_ring; /* receive descriptor ring  */
110
111         struct sk_buff *tx_skb[KORINA_NUM_TDS];
112         struct sk_buff *rx_skb[KORINA_NUM_RDS];
113
114         int rx_next_done;
115         int rx_chain_head;
116         int rx_chain_tail;
117         enum chain_status rx_chain_status;
118
119         int tx_next_done;
120         int tx_chain_head;
121         int tx_chain_tail;
122         enum chain_status tx_chain_status;
123         int tx_count;
124         int tx_full;
125
126         int rx_irq;
127         int tx_irq;
128         int ovr_irq;
129         int und_irq;
130
131         spinlock_t lock;        /* NIC xmit lock */
132
133         int dma_halt_cnt;
134         int dma_run_cnt;
135         struct napi_struct napi;
136         struct mii_if_info mii_if;
137         struct net_device *dev;
138         int phy_addr;
139 };
140
141 extern unsigned int idt_cpu_freq;
142
143 static inline void korina_start_dma(struct dma_reg *ch, u32 dma_addr)
144 {
145         writel(0, &ch->dmandptr);
146         writel(dma_addr, &ch->dmadptr);
147 }
148
149 static inline void korina_abort_dma(struct net_device *dev,
150                                         struct dma_reg *ch)
151 {
152        if (readl(&ch->dmac) & DMA_CHAN_RUN_BIT) {
153                writel(0x10, &ch->dmac);
154
155                while (!(readl(&ch->dmas) & DMA_STAT_HALT))
156                        dev->trans_start = jiffies;
157
158                writel(0, &ch->dmas);
159        }
160
161        writel(0, &ch->dmadptr);
162        writel(0, &ch->dmandptr);
163 }
164
165 static inline void korina_chain_dma(struct dma_reg *ch, u32 dma_addr)
166 {
167         writel(dma_addr, &ch->dmandptr);
168 }
169
170 static void korina_abort_tx(struct net_device *dev)
171 {
172         struct korina_private *lp = netdev_priv(dev);
173
174         korina_abort_dma(dev, lp->tx_dma_regs);
175 }
176
177 static void korina_abort_rx(struct net_device *dev)
178 {
179         struct korina_private *lp = netdev_priv(dev);
180
181         korina_abort_dma(dev, lp->rx_dma_regs);
182 }
183
184 static void korina_start_rx(struct korina_private *lp,
185                                         struct dma_desc *rd)
186 {
187         korina_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
188 }
189
190 static void korina_chain_rx(struct korina_private *lp,
191                                         struct dma_desc *rd)
192 {
193         korina_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
194 }
195
196 /* transmit packet */
197 static int korina_send_packet(struct sk_buff *skb, struct net_device *dev)
198 {
199         struct korina_private *lp = netdev_priv(dev);
200         unsigned long flags;
201         u32 length;
202         u32 chain_index;
203         struct dma_desc *td;
204
205         spin_lock_irqsave(&lp->lock, flags);
206
207         td = &lp->td_ring[lp->tx_chain_tail];
208
209         /* stop queue when full, drop pkts if queue already full */
210         if (lp->tx_count >= (KORINA_NUM_TDS - 2)) {
211                 lp->tx_full = 1;
212
213                 if (lp->tx_count == (KORINA_NUM_TDS - 2))
214                         netif_stop_queue(dev);
215                 else {
216                         dev->stats.tx_dropped++;
217                         dev_kfree_skb_any(skb);
218                         spin_unlock_irqrestore(&lp->lock, flags);
219
220                         return NETDEV_TX_BUSY;
221                 }
222         }
223
224         lp->tx_count++;
225
226         lp->tx_skb[lp->tx_chain_tail] = skb;
227
228         length = skb->len;
229         dma_cache_wback((u32)skb->data, skb->len);
230
231         /* Setup the transmit descriptor. */
232         dma_cache_inv((u32) td, sizeof(*td));
233         td->ca = CPHYSADDR(skb->data);
234         chain_index = (lp->tx_chain_tail - 1) &
235                         KORINA_TDS_MASK;
236
237         if (readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
238                 if (lp->tx_chain_status == desc_empty) {
239                         /* Update tail */
240                         td->control = DMA_COUNT(length) |
241                                         DMA_DESC_COF | DMA_DESC_IOF;
242                         /* Move tail */
243                         lp->tx_chain_tail = chain_index;
244                         /* Write to NDPTR */
245                         writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),
246                                         &lp->tx_dma_regs->dmandptr);
247                         /* Move head to tail */
248                         lp->tx_chain_head = lp->tx_chain_tail;
249                 } else {
250                         /* Update tail */
251                         td->control = DMA_COUNT(length) |
252                                         DMA_DESC_COF | DMA_DESC_IOF;
253                         /* Link to prev */
254                         lp->td_ring[chain_index].control &=
255                                         ~DMA_DESC_COF;
256                         /* Link to prev */
257                         lp->td_ring[chain_index].link =  CPHYSADDR(td);
258                         /* Move tail */
259                         lp->tx_chain_tail = chain_index;
260                         /* Write to NDPTR */
261                         writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),
262                                         &(lp->tx_dma_regs->dmandptr));
263                         /* Move head to tail */
264                         lp->tx_chain_head = lp->tx_chain_tail;
265                         lp->tx_chain_status = desc_empty;
266                 }
267         } else {
268                 if (lp->tx_chain_status == desc_empty) {
269                         /* Update tail */
270                         td->control = DMA_COUNT(length) |
271                                         DMA_DESC_COF | DMA_DESC_IOF;
272                         /* Move tail */
273                         lp->tx_chain_tail = chain_index;
274                         lp->tx_chain_status = desc_filled;
275                         netif_stop_queue(dev);
276                 } else {
277                         /* Update tail */
278                         td->control = DMA_COUNT(length) |
279                                         DMA_DESC_COF | DMA_DESC_IOF;
280                         lp->td_ring[chain_index].control &=
281                                         ~DMA_DESC_COF;
282                         lp->td_ring[chain_index].link =  CPHYSADDR(td);
283                         lp->tx_chain_tail = chain_index;
284                 }
285         }
286         dma_cache_wback((u32) td, sizeof(*td));
287
288         dev->trans_start = jiffies;
289         spin_unlock_irqrestore(&lp->lock, flags);
290
291         return NETDEV_TX_OK;
292 }
293
294 static int mdio_read(struct net_device *dev, int mii_id, int reg)
295 {
296         struct korina_private *lp = netdev_priv(dev);
297         int ret;
298
299         mii_id = ((lp->rx_irq == 0x2c ? 1 : 0) << 8);
300
301         writel(0, &lp->eth_regs->miimcfg);
302         writel(0, &lp->eth_regs->miimcmd);
303         writel(mii_id | reg, &lp->eth_regs->miimaddr);
304         writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd);
305
306         ret = (int)(readl(&lp->eth_regs->miimrdd));
307         return ret;
308 }
309
310 static void mdio_write(struct net_device *dev, int mii_id, int reg, int val)
311 {
312         struct korina_private *lp = netdev_priv(dev);
313
314         mii_id = ((lp->rx_irq == 0x2c ? 1 : 0) << 8);
315
316         writel(0, &lp->eth_regs->miimcfg);
317         writel(1, &lp->eth_regs->miimcmd);
318         writel(mii_id | reg, &lp->eth_regs->miimaddr);
319         writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd);
320         writel(val, &lp->eth_regs->miimwtd);
321 }
322
323 /* Ethernet Rx DMA interrupt */
324 static irqreturn_t korina_rx_dma_interrupt(int irq, void *dev_id)
325 {
326         struct net_device *dev = dev_id;
327         struct korina_private *lp = netdev_priv(dev);
328         u32 dmas, dmasm;
329         irqreturn_t retval;
330
331         dmas = readl(&lp->rx_dma_regs->dmas);
332         if (dmas & (DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR)) {
333                 netif_rx_schedule_prep(&lp->napi);
334
335                 dmasm = readl(&lp->rx_dma_regs->dmasm);
336                 writel(dmasm | (DMA_STAT_DONE |
337                                 DMA_STAT_HALT | DMA_STAT_ERR),
338                                 &lp->rx_dma_regs->dmasm);
339
340                 if (dmas & DMA_STAT_ERR)
341                         printk(KERN_ERR DRV_NAME "%s: DMA error\n", dev->name);
342
343                 retval = IRQ_HANDLED;
344         } else
345                 retval = IRQ_NONE;
346
347         return retval;
348 }
349
350 static int korina_rx(struct net_device *dev, int limit)
351 {
352         struct korina_private *lp = netdev_priv(dev);
353         struct dma_desc *rd = &lp->rd_ring[lp->rx_next_done];
354         struct sk_buff *skb, *skb_new;
355         u8 *pkt_buf;
356         u32 devcs, pkt_len, dmas, rx_free_desc;
357         int count;
358
359         dma_cache_inv((u32)rd, sizeof(*rd));
360
361         for (count = 0; count < limit; count++) {
362
363                 devcs = rd->devcs;
364
365                 /* Update statistics counters */
366                 if (devcs & ETH_RX_CRC)
367                         dev->stats.rx_crc_errors++;
368                 if (devcs & ETH_RX_LOR)
369                         dev->stats.rx_length_errors++;
370                 if (devcs & ETH_RX_LE)
371                         dev->stats.rx_length_errors++;
372                 if (devcs & ETH_RX_OVR)
373                         dev->stats.rx_over_errors++;
374                 if (devcs & ETH_RX_CV)
375                         dev->stats.rx_frame_errors++;
376                 if (devcs & ETH_RX_CES)
377                         dev->stats.rx_length_errors++;
378                 if (devcs & ETH_RX_MP)
379                         dev->stats.multicast++;
380
381                 if ((devcs & ETH_RX_LD) != ETH_RX_LD) {
382                         /* check that this is a whole packet
383                          * WARNING: DMA_FD bit incorrectly set
384                          * in Rc32434 (errata ref #077) */
385                         dev->stats.rx_errors++;
386                         dev->stats.rx_dropped++;
387                 }
388
389                 while ((rx_free_desc = KORINA_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
390                         /* init the var. used for the later
391                          * operations within the while loop */
392                         skb_new = NULL;
393                         pkt_len = RCVPKT_LENGTH(devcs);
394                         skb = lp->rx_skb[lp->rx_next_done];
395
396                         if ((devcs & ETH_RX_ROK)) {
397                                 /* must be the (first and) last
398                                  * descriptor then */
399                                 pkt_buf = (u8 *)lp->rx_skb[lp->rx_next_done]->data;
400
401                                 /* invalidate the cache */
402                                 dma_cache_inv((unsigned long)pkt_buf, pkt_len - 4);
403
404                                 /* Malloc up new buffer. */
405                                 skb_new = netdev_alloc_skb(dev, KORINA_RBSIZE + 2);
406
407                                 if (!skb_new)
408                                         break;
409                                 /* Do not count the CRC */
410                                 skb_put(skb, pkt_len - 4);
411                                 skb->protocol = eth_type_trans(skb, dev);
412
413                                 /* Pass the packet to upper layers */
414                                 netif_receive_skb(skb);
415                                 dev->stats.rx_packets++;
416                                 dev->stats.rx_bytes += pkt_len;
417
418                                 /* Update the mcast stats */
419                                 if (devcs & ETH_RX_MP)
420                                         dev->stats.multicast++;
421
422                                 lp->rx_skb[lp->rx_next_done] = skb_new;
423                         }
424
425                         rd->devcs = 0;
426
427                         /* Restore descriptor's curr_addr */
428                         if (skb_new)
429                                 rd->ca = CPHYSADDR(skb_new->data);
430                         else
431                                 rd->ca = CPHYSADDR(skb->data);
432
433                         rd->control = DMA_COUNT(KORINA_RBSIZE) |
434                                 DMA_DESC_COD | DMA_DESC_IOD;
435                         lp->rd_ring[(lp->rx_next_done - 1) &
436                                 KORINA_RDS_MASK].control &=
437                                 ~DMA_DESC_COD;
438
439                         lp->rx_next_done = (lp->rx_next_done + 1) & KORINA_RDS_MASK;
440                         dma_cache_wback((u32)rd, sizeof(*rd));
441                         rd = &lp->rd_ring[lp->rx_next_done];
442                         writel(~DMA_STAT_DONE, &lp->rx_dma_regs->dmas);
443                 }
444         }
445
446         dmas = readl(&lp->rx_dma_regs->dmas);
447
448         if (dmas & DMA_STAT_HALT) {
449                 writel(~(DMA_STAT_HALT | DMA_STAT_ERR),
450                                 &lp->rx_dma_regs->dmas);
451
452                 lp->dma_halt_cnt++;
453                 rd->devcs = 0;
454                 skb = lp->rx_skb[lp->rx_next_done];
455                 rd->ca = CPHYSADDR(skb->data);
456                 dma_cache_wback((u32)rd, sizeof(*rd));
457                 korina_chain_rx(lp, rd);
458         }
459
460         return count;
461 }
462
463 static int korina_poll(struct napi_struct *napi, int budget)
464 {
465         struct korina_private *lp =
466                 container_of(napi, struct korina_private, napi);
467         struct net_device *dev = lp->dev;
468         int work_done;
469
470         work_done = korina_rx(dev, budget);
471         if (work_done < budget) {
472                 netif_rx_complete(napi);
473
474                 writel(readl(&lp->rx_dma_regs->dmasm) &
475                         ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR),
476                         &lp->rx_dma_regs->dmasm);
477         }
478         return work_done;
479 }
480
481 /*
482  * Set or clear the multicast filter for this adaptor.
483  */
484 static void korina_multicast_list(struct net_device *dev)
485 {
486         struct korina_private *lp = netdev_priv(dev);
487         unsigned long flags;
488         struct dev_mc_list *dmi = dev->mc_list;
489         u32 recognise = ETH_ARC_AB;     /* always accept broadcasts */
490         int i;
491
492         /* Set promiscuous mode */
493         if (dev->flags & IFF_PROMISC)
494                 recognise |= ETH_ARC_PRO;
495
496         else if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 4))
497                 /* All multicast and broadcast */
498                 recognise |= ETH_ARC_AM;
499
500         /* Build the hash table */
501         if (dev->mc_count > 4) {
502                 u16 hash_table[4];
503                 u32 crc;
504
505                 for (i = 0; i < 4; i++)
506                         hash_table[i] = 0;
507
508                 for (i = 0; i < dev->mc_count; i++) {
509                         char *addrs = dmi->dmi_addr;
510
511                         dmi = dmi->next;
512
513                         if (!(*addrs & 1))
514                                 continue;
515
516                         crc = ether_crc_le(6, addrs);
517                         crc >>= 26;
518                         hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
519                 }
520                 /* Accept filtered multicast */
521                 recognise |= ETH_ARC_AFM;
522
523                 /* Fill the MAC hash tables with their values */
524                 writel((u32)(hash_table[1] << 16 | hash_table[0]),
525                                         &lp->eth_regs->ethhash0);
526                 writel((u32)(hash_table[3] << 16 | hash_table[2]),
527                                         &lp->eth_regs->ethhash1);
528         }
529
530         spin_lock_irqsave(&lp->lock, flags);
531         writel(recognise, &lp->eth_regs->etharc);
532         spin_unlock_irqrestore(&lp->lock, flags);
533 }
534
535 static void korina_tx(struct net_device *dev)
536 {
537         struct korina_private *lp = netdev_priv(dev);
538         struct dma_desc *td = &lp->td_ring[lp->tx_next_done];
539         u32 devcs;
540         u32 dmas;
541
542         spin_lock(&lp->lock);
543
544         /* Process all desc that are done */
545         while (IS_DMA_FINISHED(td->control)) {
546                 if (lp->tx_full == 1) {
547                         netif_wake_queue(dev);
548                         lp->tx_full = 0;
549                 }
550
551                 devcs = lp->td_ring[lp->tx_next_done].devcs;
552                 if ((devcs & (ETH_TX_FD | ETH_TX_LD)) !=
553                                 (ETH_TX_FD | ETH_TX_LD)) {
554                         dev->stats.tx_errors++;
555                         dev->stats.tx_dropped++;
556
557                         /* Should never happen */
558                         printk(KERN_ERR DRV_NAME "%s: split tx ignored\n",
559                                                         dev->name);
560                 } else if (devcs & ETH_TX_TOK) {
561                         dev->stats.tx_packets++;
562                         dev->stats.tx_bytes +=
563                                         lp->tx_skb[lp->tx_next_done]->len;
564                 } else {
565                         dev->stats.tx_errors++;
566                         dev->stats.tx_dropped++;
567
568                         /* Underflow */
569                         if (devcs & ETH_TX_UND)
570                                 dev->stats.tx_fifo_errors++;
571
572                         /* Oversized frame */
573                         if (devcs & ETH_TX_OF)
574                                 dev->stats.tx_aborted_errors++;
575
576                         /* Excessive deferrals */
577                         if (devcs & ETH_TX_ED)
578                                 dev->stats.tx_carrier_errors++;
579
580                         /* Collisions: medium busy */
581                         if (devcs & ETH_TX_EC)
582                                 dev->stats.collisions++;
583
584                         /* Late collision */
585                         if (devcs & ETH_TX_LC)
586                                 dev->stats.tx_window_errors++;
587                 }
588
589                 /* We must always free the original skb */
590                 if (lp->tx_skb[lp->tx_next_done]) {
591                         dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
592                         lp->tx_skb[lp->tx_next_done] = NULL;
593                 }
594
595                 lp->td_ring[lp->tx_next_done].control = DMA_DESC_IOF;
596                 lp->td_ring[lp->tx_next_done].devcs = ETH_TX_FD | ETH_TX_LD;
597                 lp->td_ring[lp->tx_next_done].link = 0;
598                 lp->td_ring[lp->tx_next_done].ca = 0;
599                 lp->tx_count--;
600
601                 /* Go on to next transmission */
602                 lp->tx_next_done = (lp->tx_next_done + 1) & KORINA_TDS_MASK;
603                 td = &lp->td_ring[lp->tx_next_done];
604
605         }
606
607         /* Clear the DMA status register */
608         dmas = readl(&lp->tx_dma_regs->dmas);
609         writel(~dmas, &lp->tx_dma_regs->dmas);
610
611         writel(readl(&lp->tx_dma_regs->dmasm) &
612                         ~(DMA_STAT_FINI | DMA_STAT_ERR),
613                         &lp->tx_dma_regs->dmasm);
614
615         spin_unlock(&lp->lock);
616 }
617
618 static irqreturn_t
619 korina_tx_dma_interrupt(int irq, void *dev_id)
620 {
621         struct net_device *dev = dev_id;
622         struct korina_private *lp = netdev_priv(dev);
623         u32 dmas, dmasm;
624         irqreturn_t retval;
625
626         dmas = readl(&lp->tx_dma_regs->dmas);
627
628         if (dmas & (DMA_STAT_FINI | DMA_STAT_ERR)) {
629                 korina_tx(dev);
630
631                 dmasm = readl(&lp->tx_dma_regs->dmasm);
632                 writel(dmasm | (DMA_STAT_FINI | DMA_STAT_ERR),
633                                 &lp->tx_dma_regs->dmasm);
634
635                 if (lp->tx_chain_status == desc_filled &&
636                         (readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
637                         writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),
638                                 &(lp->tx_dma_regs->dmandptr));
639                         lp->tx_chain_status = desc_empty;
640                         lp->tx_chain_head = lp->tx_chain_tail;
641                         dev->trans_start = jiffies;
642                 }
643                 if (dmas & DMA_STAT_ERR)
644                         printk(KERN_ERR DRV_NAME "%s: DMA error\n", dev->name);
645
646                 retval = IRQ_HANDLED;
647         } else
648                 retval = IRQ_NONE;
649
650         return retval;
651 }
652
653
654 static void korina_check_media(struct net_device *dev, unsigned int init_media)
655 {
656         struct korina_private *lp = netdev_priv(dev);
657
658         mii_check_media(&lp->mii_if, 0, init_media);
659
660         if (lp->mii_if.full_duplex)
661                 writel(readl(&lp->eth_regs->ethmac2) | ETH_MAC2_FD,
662                                                 &lp->eth_regs->ethmac2);
663         else
664                 writel(readl(&lp->eth_regs->ethmac2) & ~ETH_MAC2_FD,
665                                                 &lp->eth_regs->ethmac2);
666 }
667
668 static void korina_set_carrier(struct mii_if_info *mii)
669 {
670         if (mii->force_media) {
671                 /* autoneg is off: Link is always assumed to be up */
672                 if (!netif_carrier_ok(mii->dev))
673                         netif_carrier_on(mii->dev);
674         } else  /* Let MMI library update carrier status */
675                 korina_check_media(mii->dev, 0);
676 }
677
678 static int korina_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
679 {
680         struct korina_private *lp = netdev_priv(dev);
681         struct mii_ioctl_data *data = if_mii(rq);
682         int rc;
683
684         if (!netif_running(dev))
685                 return -EINVAL;
686         spin_lock_irq(&lp->lock);
687         rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
688         spin_unlock_irq(&lp->lock);
689         korina_set_carrier(&lp->mii_if);
690
691         return rc;
692 }
693
694 /* ethtool helpers */
695 static void netdev_get_drvinfo(struct net_device *dev,
696                         struct ethtool_drvinfo *info)
697 {
698         struct korina_private *lp = netdev_priv(dev);
699
700         strcpy(info->driver, DRV_NAME);
701         strcpy(info->version, DRV_VERSION);
702         strcpy(info->bus_info, lp->dev->name);
703 }
704
705 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
706 {
707         struct korina_private *lp = netdev_priv(dev);
708         int rc;
709
710         spin_lock_irq(&lp->lock);
711         rc = mii_ethtool_gset(&lp->mii_if, cmd);
712         spin_unlock_irq(&lp->lock);
713
714         return rc;
715 }
716
717 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
718 {
719         struct korina_private *lp = netdev_priv(dev);
720         int rc;
721
722         spin_lock_irq(&lp->lock);
723         rc = mii_ethtool_sset(&lp->mii_if, cmd);
724         spin_unlock_irq(&lp->lock);
725         korina_set_carrier(&lp->mii_if);
726
727         return rc;
728 }
729
730 static u32 netdev_get_link(struct net_device *dev)
731 {
732         struct korina_private *lp = netdev_priv(dev);
733
734         return mii_link_ok(&lp->mii_if);
735 }
736
737 static struct ethtool_ops netdev_ethtool_ops = {
738         .get_drvinfo            = netdev_get_drvinfo,
739         .get_settings           = netdev_get_settings,
740         .set_settings           = netdev_set_settings,
741         .get_link               = netdev_get_link,
742 };
743
744 static void korina_alloc_ring(struct net_device *dev)
745 {
746         struct korina_private *lp = netdev_priv(dev);
747         int i;
748
749         /* Initialize the transmit descriptors */
750         for (i = 0; i < KORINA_NUM_TDS; i++) {
751                 lp->td_ring[i].control = DMA_DESC_IOF;
752                 lp->td_ring[i].devcs = ETH_TX_FD | ETH_TX_LD;
753                 lp->td_ring[i].ca = 0;
754                 lp->td_ring[i].link = 0;
755         }
756         lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail =
757                         lp->tx_full = lp->tx_count = 0;
758         lp->tx_chain_status = desc_empty;
759
760         /* Initialize the receive descriptors */
761         for (i = 0; i < KORINA_NUM_RDS; i++) {
762                 struct sk_buff *skb = lp->rx_skb[i];
763
764                 skb = dev_alloc_skb(KORINA_RBSIZE + 2);
765                 if (!skb)
766                         break;
767                 skb_reserve(skb, 2);
768                 lp->rx_skb[i] = skb;
769                 lp->rd_ring[i].control = DMA_DESC_IOD |
770                                 DMA_COUNT(KORINA_RBSIZE);
771                 lp->rd_ring[i].devcs = 0;
772                 lp->rd_ring[i].ca = CPHYSADDR(skb->data);
773                 lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
774         }
775
776         /* loop back */
777         lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[0]);
778         lp->rx_next_done  = 0;
779
780         lp->rd_ring[i].control |= DMA_DESC_COD;
781         lp->rx_chain_head = 0;
782         lp->rx_chain_tail = 0;
783         lp->rx_chain_status = desc_empty;
784 }
785
786 static void korina_free_ring(struct net_device *dev)
787 {
788         struct korina_private *lp = netdev_priv(dev);
789         int i;
790
791         for (i = 0; i < KORINA_NUM_RDS; i++) {
792                 lp->rd_ring[i].control = 0;
793                 if (lp->rx_skb[i])
794                         dev_kfree_skb_any(lp->rx_skb[i]);
795                 lp->rx_skb[i] = NULL;
796         }
797
798         for (i = 0; i < KORINA_NUM_TDS; i++) {
799                 lp->td_ring[i].control = 0;
800                 if (lp->tx_skb[i])
801                         dev_kfree_skb_any(lp->tx_skb[i]);
802                 lp->tx_skb[i] = NULL;
803         }
804 }
805
806 /*
807  * Initialize the RC32434 ethernet controller.
808  */
809 static int korina_init(struct net_device *dev)
810 {
811         struct korina_private *lp = netdev_priv(dev);
812
813         /* Disable DMA */
814         korina_abort_tx(dev);
815         korina_abort_rx(dev);
816
817         /* reset ethernet logic */
818         writel(0, &lp->eth_regs->ethintfc);
819         while ((readl(&lp->eth_regs->ethintfc) & ETH_INT_FC_RIP))
820                 dev->trans_start = jiffies;
821
822         /* Enable Ethernet Interface */
823         writel(ETH_INT_FC_EN, &lp->eth_regs->ethintfc);
824
825         /* Allocate rings */
826         korina_alloc_ring(dev);
827
828         writel(0, &lp->rx_dma_regs->dmas);
829         /* Start Rx DMA */
830         korina_start_rx(lp, &lp->rd_ring[0]);
831
832         writel(readl(&lp->tx_dma_regs->dmasm) &
833                         ~(DMA_STAT_FINI | DMA_STAT_ERR),
834                         &lp->tx_dma_regs->dmasm);
835         writel(readl(&lp->rx_dma_regs->dmasm) &
836                         ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR),
837                         &lp->rx_dma_regs->dmasm);
838
839         /* Accept only packets destined for this Ethernet device address */
840         writel(ETH_ARC_AB, &lp->eth_regs->etharc);
841
842         /* Set all Ether station address registers to their initial values */
843         writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
844         writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
845
846         writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
847         writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
848
849         writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
850         writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
851
852         writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
853         writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
854
855
856         /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
857         writel(ETH_MAC2_PE | ETH_MAC2_CEN | ETH_MAC2_FD,
858                         &lp->eth_regs->ethmac2);
859
860         /* Back to back inter-packet-gap */
861         writel(0x15, &lp->eth_regs->ethipgt);
862         /* Non - Back to back inter-packet-gap */
863         writel(0x12, &lp->eth_regs->ethipgr);
864
865         /* Management Clock Prescaler Divisor
866          * Clock independent setting */
867         writel(((idt_cpu_freq) / MII_CLOCK + 1) & ~1,
868                        &lp->eth_regs->ethmcp);
869
870         /* don't transmit until fifo contains 48b */
871         writel(48, &lp->eth_regs->ethfifott);
872
873         writel(ETH_MAC1_RE, &lp->eth_regs->ethmac1);
874
875         napi_enable(&lp->napi);
876         netif_start_queue(dev);
877
878         return 0;
879 }
880
881 /*
882  * Restart the RC32434 ethernet controller.
883  * FIXME: check the return status where we call it
884  */
885 static int korina_restart(struct net_device *dev)
886 {
887         struct korina_private *lp = netdev_priv(dev);
888         int ret;
889
890         /*
891          * Disable interrupts
892          */
893         disable_irq(lp->rx_irq);
894         disable_irq(lp->tx_irq);
895         disable_irq(lp->ovr_irq);
896         disable_irq(lp->und_irq);
897
898         writel(readl(&lp->tx_dma_regs->dmasm) |
899                                 DMA_STAT_FINI | DMA_STAT_ERR,
900                                 &lp->tx_dma_regs->dmasm);
901         writel(readl(&lp->rx_dma_regs->dmasm) |
902                                 DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR,
903                                 &lp->rx_dma_regs->dmasm);
904
905         korina_free_ring(dev);
906
907         napi_disable(&lp->napi);
908
909         ret = korina_init(dev);
910         if (ret < 0) {
911                 printk(KERN_ERR DRV_NAME "%s: cannot restart device\n",
912                                                                 dev->name);
913                 return ret;
914         }
915         korina_multicast_list(dev);
916
917         enable_irq(lp->und_irq);
918         enable_irq(lp->ovr_irq);
919         enable_irq(lp->tx_irq);
920         enable_irq(lp->rx_irq);
921
922         return ret;
923 }
924
925 static void korina_clear_and_restart(struct net_device *dev, u32 value)
926 {
927         struct korina_private *lp = netdev_priv(dev);
928
929         netif_stop_queue(dev);
930         writel(value, &lp->eth_regs->ethintfc);
931         korina_restart(dev);
932 }
933
934 /* Ethernet Tx Underflow interrupt */
935 static irqreturn_t korina_und_interrupt(int irq, void *dev_id)
936 {
937         struct net_device *dev = dev_id;
938         struct korina_private *lp = netdev_priv(dev);
939         unsigned int und;
940
941         spin_lock(&lp->lock);
942
943         und = readl(&lp->eth_regs->ethintfc);
944
945         if (und & ETH_INT_FC_UND)
946                 korina_clear_and_restart(dev, und & ~ETH_INT_FC_UND);
947
948         spin_unlock(&lp->lock);
949
950         return IRQ_HANDLED;
951 }
952
953 static void korina_tx_timeout(struct net_device *dev)
954 {
955         struct korina_private *lp = netdev_priv(dev);
956         unsigned long flags;
957
958         spin_lock_irqsave(&lp->lock, flags);
959         korina_restart(dev);
960         spin_unlock_irqrestore(&lp->lock, flags);
961 }
962
963 /* Ethernet Rx Overflow interrupt */
964 static irqreturn_t
965 korina_ovr_interrupt(int irq, void *dev_id)
966 {
967         struct net_device *dev = dev_id;
968         struct korina_private *lp = netdev_priv(dev);
969         unsigned int ovr;
970
971         spin_lock(&lp->lock);
972         ovr = readl(&lp->eth_regs->ethintfc);
973
974         if (ovr & ETH_INT_FC_OVR)
975                 korina_clear_and_restart(dev, ovr & ~ETH_INT_FC_OVR);
976
977         spin_unlock(&lp->lock);
978
979         return IRQ_HANDLED;
980 }
981
982 #ifdef CONFIG_NET_POLL_CONTROLLER
983 static void korina_poll_controller(struct net_device *dev)
984 {
985         disable_irq(dev->irq);
986         korina_tx_dma_interrupt(dev->irq, dev);
987         enable_irq(dev->irq);
988 }
989 #endif
990
991 static int korina_open(struct net_device *dev)
992 {
993         struct korina_private *lp = netdev_priv(dev);
994         int ret;
995
996         /* Initialize */
997         ret = korina_init(dev);
998         if (ret < 0) {
999                 printk(KERN_ERR DRV_NAME "%s: cannot open device\n", dev->name);
1000                 goto out;
1001         }
1002
1003         /* Install the interrupt handler
1004          * that handles the Done Finished
1005          * Ovr and Und Events */
1006         ret = request_irq(lp->rx_irq, &korina_rx_dma_interrupt,
1007                 IRQF_SHARED | IRQF_DISABLED, "Korina ethernet Rx", dev);
1008         if (ret < 0) {
1009                 printk(KERN_ERR DRV_NAME "%s: unable to get Rx DMA IRQ %d\n",
1010                     dev->name, lp->rx_irq);
1011                 goto err_release;
1012         }
1013         ret = request_irq(lp->tx_irq, &korina_tx_dma_interrupt,
1014                 IRQF_SHARED | IRQF_DISABLED, "Korina ethernet Tx", dev);
1015         if (ret < 0) {
1016                 printk(KERN_ERR DRV_NAME "%s: unable to get Tx DMA IRQ %d\n",
1017                     dev->name, lp->tx_irq);
1018                 goto err_free_rx_irq;
1019         }
1020
1021         /* Install handler for overrun error. */
1022         ret = request_irq(lp->ovr_irq, &korina_ovr_interrupt,
1023                         IRQF_SHARED | IRQF_DISABLED, "Ethernet Overflow", dev);
1024         if (ret < 0) {
1025                 printk(KERN_ERR DRV_NAME"%s: unable to get OVR IRQ %d\n",
1026                     dev->name, lp->ovr_irq);
1027                 goto err_free_tx_irq;
1028         }
1029
1030         /* Install handler for underflow error. */
1031         ret = request_irq(lp->und_irq, &korina_und_interrupt,
1032                         IRQF_SHARED | IRQF_DISABLED, "Ethernet Underflow", dev);
1033         if (ret < 0) {
1034                 printk(KERN_ERR DRV_NAME "%s: unable to get UND IRQ %d\n",
1035                     dev->name, lp->und_irq);
1036                 goto err_free_ovr_irq;
1037         }
1038 out:
1039         return ret;
1040
1041 err_free_ovr_irq:
1042         free_irq(lp->ovr_irq, dev);
1043 err_free_tx_irq:
1044         free_irq(lp->tx_irq, dev);
1045 err_free_rx_irq:
1046         free_irq(lp->rx_irq, dev);
1047 err_release:
1048         korina_free_ring(dev);
1049         goto out;
1050 }
1051
1052 static int korina_close(struct net_device *dev)
1053 {
1054         struct korina_private *lp = netdev_priv(dev);
1055         u32 tmp;
1056
1057         /* Disable interrupts */
1058         disable_irq(lp->rx_irq);
1059         disable_irq(lp->tx_irq);
1060         disable_irq(lp->ovr_irq);
1061         disable_irq(lp->und_irq);
1062
1063         korina_abort_tx(dev);
1064         tmp = readl(&lp->tx_dma_regs->dmasm);
1065         tmp = tmp | DMA_STAT_FINI | DMA_STAT_ERR;
1066         writel(tmp, &lp->tx_dma_regs->dmasm);
1067
1068         korina_abort_rx(dev);
1069         tmp = readl(&lp->rx_dma_regs->dmasm);
1070         tmp = tmp | DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR;
1071         writel(tmp, &lp->rx_dma_regs->dmasm);
1072
1073         korina_free_ring(dev);
1074
1075         napi_disable(&lp->napi);
1076
1077         free_irq(lp->rx_irq, dev);
1078         free_irq(lp->tx_irq, dev);
1079         free_irq(lp->ovr_irq, dev);
1080         free_irq(lp->und_irq, dev);
1081
1082         return 0;
1083 }
1084
1085 static int korina_probe(struct platform_device *pdev)
1086 {
1087         struct korina_device *bif = platform_get_drvdata(pdev);
1088         struct korina_private *lp;
1089         struct net_device *dev;
1090         struct resource *r;
1091         int rc;
1092
1093         dev = alloc_etherdev(sizeof(struct korina_private));
1094         if (!dev) {
1095                 printk(KERN_ERR DRV_NAME ": alloc_etherdev failed\n");
1096                 return -ENOMEM;
1097         }
1098         SET_NETDEV_DEV(dev, &pdev->dev);
1099         lp = netdev_priv(dev);
1100
1101         bif->dev = dev;
1102         memcpy(dev->dev_addr, bif->mac, 6);
1103
1104         lp->rx_irq = platform_get_irq_byname(pdev, "korina_rx");
1105         lp->tx_irq = platform_get_irq_byname(pdev, "korina_tx");
1106         lp->ovr_irq = platform_get_irq_byname(pdev, "korina_ovr");
1107         lp->und_irq = platform_get_irq_byname(pdev, "korina_und");
1108
1109         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_regs");
1110         dev->base_addr = r->start;
1111         lp->eth_regs = ioremap_nocache(r->start, r->end - r->start);
1112         if (!lp->eth_regs) {
1113                 printk(KERN_ERR DRV_NAME "cannot remap registers\n");
1114                 rc = -ENXIO;
1115                 goto probe_err_out;
1116         }
1117
1118         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_rx");
1119         lp->rx_dma_regs = ioremap_nocache(r->start, r->end - r->start);
1120         if (!lp->rx_dma_regs) {
1121                 printk(KERN_ERR DRV_NAME "cannot remap Rx DMA registers\n");
1122                 rc = -ENXIO;
1123                 goto probe_err_dma_rx;
1124         }
1125
1126         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_tx");
1127         lp->tx_dma_regs = ioremap_nocache(r->start, r->end - r->start);
1128         if (!lp->tx_dma_regs) {
1129                 printk(KERN_ERR DRV_NAME "cannot remap Tx DMA registers\n");
1130                 rc = -ENXIO;
1131                 goto probe_err_dma_tx;
1132         }
1133
1134         lp->td_ring = kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1135         if (!lp->td_ring) {
1136                 printk(KERN_ERR DRV_NAME "cannot allocate descriptors\n");
1137                 rc = -ENXIO;
1138                 goto probe_err_td_ring;
1139         }
1140
1141         dma_cache_inv((unsigned long)(lp->td_ring),
1142                         TD_RING_SIZE + RD_RING_SIZE);
1143
1144         /* now convert TD_RING pointer to KSEG1 */
1145         lp->td_ring = (struct dma_desc *)KSEG1ADDR(lp->td_ring);
1146         lp->rd_ring = &lp->td_ring[KORINA_NUM_TDS];
1147
1148         spin_lock_init(&lp->lock);
1149         /* just use the rx dma irq */
1150         dev->irq = lp->rx_irq;
1151         lp->dev = dev;
1152
1153         dev->open = korina_open;
1154         dev->stop = korina_close;
1155         dev->hard_start_xmit = korina_send_packet;
1156         dev->set_multicast_list = &korina_multicast_list;
1157         dev->ethtool_ops = &netdev_ethtool_ops;
1158         dev->tx_timeout = korina_tx_timeout;
1159         dev->watchdog_timeo = TX_TIMEOUT;
1160         dev->do_ioctl = &korina_ioctl;
1161 #ifdef CONFIG_NET_POLL_CONTROLLER
1162         dev->poll_controller = korina_poll_controller;
1163 #endif
1164         netif_napi_add(dev, &lp->napi, korina_poll, 64);
1165
1166         lp->phy_addr = (((lp->rx_irq == 0x2c? 1:0) << 8) | 0x05);
1167         lp->mii_if.dev = dev;
1168         lp->mii_if.mdio_read = mdio_read;
1169         lp->mii_if.mdio_write = mdio_write;
1170         lp->mii_if.phy_id = lp->phy_addr;
1171         lp->mii_if.phy_id_mask = 0x1f;
1172         lp->mii_if.reg_num_mask = 0x1f;
1173
1174         rc = register_netdev(dev);
1175         if (rc < 0) {
1176                 printk(KERN_ERR DRV_NAME
1177                         ": cannot register net device %d\n", rc);
1178                 goto probe_err_register;
1179         }
1180 out:
1181         return rc;
1182
1183 probe_err_register:
1184         kfree(lp->td_ring);
1185 probe_err_td_ring:
1186         iounmap(lp->tx_dma_regs);
1187 probe_err_dma_tx:
1188         iounmap(lp->rx_dma_regs);
1189 probe_err_dma_rx:
1190         iounmap(lp->eth_regs);
1191 probe_err_out:
1192         free_netdev(dev);
1193         goto out;
1194 }
1195
1196 static int korina_remove(struct platform_device *pdev)
1197 {
1198         struct korina_device *bif = platform_get_drvdata(pdev);
1199         struct korina_private *lp = netdev_priv(bif->dev);
1200
1201         iounmap(lp->eth_regs);
1202         iounmap(lp->rx_dma_regs);
1203         iounmap(lp->tx_dma_regs);
1204
1205         platform_set_drvdata(pdev, NULL);
1206         unregister_netdev(bif->dev);
1207         free_netdev(bif->dev);
1208
1209         return 0;
1210 }
1211
1212 static struct platform_driver korina_driver = {
1213         .driver.name = "korina",
1214         .probe = korina_probe,
1215         .remove = korina_remove,
1216 };
1217
1218 static int __init korina_init_module(void)
1219 {
1220         return platform_driver_register(&korina_driver);
1221 }
1222
1223 static void korina_cleanup_module(void)
1224 {
1225         return platform_driver_unregister(&korina_driver);
1226 }
1227
1228 module_init(korina_init_module);
1229 module_exit(korina_cleanup_module);
1230
1231 MODULE_AUTHOR("Philip Rischel <rischelp@idt.com>");
1232 MODULE_AUTHOR("Felix Fietkau <nbd@openwrt.org>");
1233 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
1234 MODULE_DESCRIPTION("IDT RC32434 (Korina) Ethernet driver");
1235 MODULE_LICENSE("GPL");