ifb: add performance flags
[linux-2.6.git] / drivers / net / korina.c
1 /*
2  *  Driver for the IDT RC32434 (Korina) on-chip ethernet controller.
3  *
4  *  Copyright 2004 IDT Inc. (rischelp@idt.com)
5  *  Copyright 2006 Felix Fietkau <nbd@openwrt.org>
6  *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
7  *
8  *  This program is free software; you can redistribute  it and/or modify it
9  *  under  the terms of  the GNU General  Public License as published by the
10  *  Free Software Foundation;  either version 2 of the  License, or (at your
11  *  option) any later version.
12  *
13  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
14  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
15  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
16  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
17  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
19  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
21  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23  *
24  *  You should have received a copy of the  GNU General Public License along
25  *  with this program; if not, write  to the Free Software Foundation, Inc.,
26  *  675 Mass Ave, Cambridge, MA 02139, USA.
27  *
28  *  Writing to a DMA status register:
29  *
30  *  When writing to the status register, you should mask the bit you have
31  *  been testing the status register with. Both Tx and Rx DMA registers
32  *  should stick to this procedure.
33  */
34
35 #include <linux/module.h>
36 #include <linux/kernel.h>
37 #include <linux/moduleparam.h>
38 #include <linux/sched.h>
39 #include <linux/ctype.h>
40 #include <linux/types.h>
41 #include <linux/interrupt.h>
42 #include <linux/init.h>
43 #include <linux/ioport.h>
44 #include <linux/in.h>
45 #include <linux/slab.h>
46 #include <linux/string.h>
47 #include <linux/delay.h>
48 #include <linux/netdevice.h>
49 #include <linux/etherdevice.h>
50 #include <linux/skbuff.h>
51 #include <linux/errno.h>
52 #include <linux/platform_device.h>
53 #include <linux/mii.h>
54 #include <linux/ethtool.h>
55 #include <linux/crc32.h>
56
57 #include <asm/bootinfo.h>
58 #include <asm/system.h>
59 #include <asm/bitops.h>
60 #include <asm/pgtable.h>
61 #include <asm/segment.h>
62 #include <asm/io.h>
63 #include <asm/dma.h>
64
65 #include <asm/mach-rc32434/rb.h>
66 #include <asm/mach-rc32434/rc32434.h>
67 #include <asm/mach-rc32434/eth.h>
68 #include <asm/mach-rc32434/dma_v.h>
69
70 #define DRV_NAME        "korina"
71 #define DRV_VERSION     "0.10"
72 #define DRV_RELDATE     "04Mar2008"
73
74 #define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
75                                    ((dev)->dev_addr[1]))
76 #define STATION_ADDRESS_LOW(dev)  (((dev)->dev_addr[2] << 24) | \
77                                    ((dev)->dev_addr[3] << 16) | \
78                                    ((dev)->dev_addr[4] << 8)  | \
79                                    ((dev)->dev_addr[5]))
80
81 #define MII_CLOCK 1250000       /* no more than 2.5MHz */
82
83 /* the following must be powers of two */
84 #define KORINA_NUM_RDS  64  /* number of receive descriptors */
85 #define KORINA_NUM_TDS  64  /* number of transmit descriptors */
86
87 /* KORINA_RBSIZE is the hardware's default maximum receive
88  * frame size in bytes. Having this hardcoded means that there
89  * is no support for MTU sizes greater than 1500. */
90 #define KORINA_RBSIZE   1536 /* size of one resource buffer = Ether MTU */
91 #define KORINA_RDS_MASK (KORINA_NUM_RDS - 1)
92 #define KORINA_TDS_MASK (KORINA_NUM_TDS - 1)
93 #define RD_RING_SIZE    (KORINA_NUM_RDS * sizeof(struct dma_desc))
94 #define TD_RING_SIZE    (KORINA_NUM_TDS * sizeof(struct dma_desc))
95
96 #define TX_TIMEOUT      (6000 * HZ / 1000)
97
98 enum chain_status { desc_filled, desc_empty };
99 #define IS_DMA_FINISHED(X)   (((X) & (DMA_DESC_FINI)) != 0)
100 #define IS_DMA_DONE(X)   (((X) & (DMA_DESC_DONE)) != 0)
101 #define RCVPKT_LENGTH(X)     (((X) & ETH_RX_LEN) >> ETH_RX_LEN_BIT)
102
103 /* Information that need to be kept for each board. */
104 struct korina_private {
105         struct eth_regs *eth_regs;
106         struct dma_reg *rx_dma_regs;
107         struct dma_reg *tx_dma_regs;
108         struct dma_desc *td_ring; /* transmit descriptor ring */
109         struct dma_desc *rd_ring; /* receive descriptor ring  */
110
111         struct sk_buff *tx_skb[KORINA_NUM_TDS];
112         struct sk_buff *rx_skb[KORINA_NUM_RDS];
113
114         int rx_next_done;
115         int rx_chain_head;
116         int rx_chain_tail;
117         enum chain_status rx_chain_status;
118
119         int tx_next_done;
120         int tx_chain_head;
121         int tx_chain_tail;
122         enum chain_status tx_chain_status;
123         int tx_count;
124         int tx_full;
125
126         int rx_irq;
127         int tx_irq;
128         int ovr_irq;
129         int und_irq;
130
131         spinlock_t lock;        /* NIC xmit lock */
132
133         int dma_halt_cnt;
134         int dma_run_cnt;
135         struct napi_struct napi;
136         struct timer_list media_check_timer;
137         struct mii_if_info mii_if;
138         struct work_struct restart_task;
139         struct net_device *dev;
140         int phy_addr;
141 };
142
143 extern unsigned int idt_cpu_freq;
144
145 static inline void korina_start_dma(struct dma_reg *ch, u32 dma_addr)
146 {
147         writel(0, &ch->dmandptr);
148         writel(dma_addr, &ch->dmadptr);
149 }
150
151 static inline void korina_abort_dma(struct net_device *dev,
152                                         struct dma_reg *ch)
153 {
154        if (readl(&ch->dmac) & DMA_CHAN_RUN_BIT) {
155                writel(0x10, &ch->dmac);
156
157                while (!(readl(&ch->dmas) & DMA_STAT_HALT))
158                        dev->trans_start = jiffies;
159
160                writel(0, &ch->dmas);
161        }
162
163        writel(0, &ch->dmadptr);
164        writel(0, &ch->dmandptr);
165 }
166
167 static inline void korina_chain_dma(struct dma_reg *ch, u32 dma_addr)
168 {
169         writel(dma_addr, &ch->dmandptr);
170 }
171
172 static void korina_abort_tx(struct net_device *dev)
173 {
174         struct korina_private *lp = netdev_priv(dev);
175
176         korina_abort_dma(dev, lp->tx_dma_regs);
177 }
178
179 static void korina_abort_rx(struct net_device *dev)
180 {
181         struct korina_private *lp = netdev_priv(dev);
182
183         korina_abort_dma(dev, lp->rx_dma_regs);
184 }
185
186 static void korina_start_rx(struct korina_private *lp,
187                                         struct dma_desc *rd)
188 {
189         korina_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
190 }
191
192 static void korina_chain_rx(struct korina_private *lp,
193                                         struct dma_desc *rd)
194 {
195         korina_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
196 }
197
198 /* transmit packet */
199 static int korina_send_packet(struct sk_buff *skb, struct net_device *dev)
200 {
201         struct korina_private *lp = netdev_priv(dev);
202         unsigned long flags;
203         u32 length;
204         u32 chain_prev, chain_next;
205         struct dma_desc *td;
206
207         spin_lock_irqsave(&lp->lock, flags);
208
209         td = &lp->td_ring[lp->tx_chain_tail];
210
211         /* stop queue when full, drop pkts if queue already full */
212         if (lp->tx_count >= (KORINA_NUM_TDS - 2)) {
213                 lp->tx_full = 1;
214
215                 if (lp->tx_count == (KORINA_NUM_TDS - 2))
216                         netif_stop_queue(dev);
217                 else {
218                         dev->stats.tx_dropped++;
219                         dev_kfree_skb_any(skb);
220                         spin_unlock_irqrestore(&lp->lock, flags);
221
222                         return NETDEV_TX_BUSY;
223                 }
224         }
225
226         lp->tx_count++;
227
228         lp->tx_skb[lp->tx_chain_tail] = skb;
229
230         length = skb->len;
231         dma_cache_wback((u32)skb->data, skb->len);
232
233         /* Setup the transmit descriptor. */
234         dma_cache_inv((u32) td, sizeof(*td));
235         td->ca = CPHYSADDR(skb->data);
236         chain_prev = (lp->tx_chain_tail - 1) & KORINA_TDS_MASK;
237         chain_next = (lp->tx_chain_tail + 1) & KORINA_TDS_MASK;
238
239         if (readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
240                 if (lp->tx_chain_status == desc_empty) {
241                         /* Update tail */
242                         td->control = DMA_COUNT(length) |
243                                         DMA_DESC_COF | DMA_DESC_IOF;
244                         /* Move tail */
245                         lp->tx_chain_tail = chain_next;
246                         /* Write to NDPTR */
247                         writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),
248                                         &lp->tx_dma_regs->dmandptr);
249                         /* Move head to tail */
250                         lp->tx_chain_head = lp->tx_chain_tail;
251                 } else {
252                         /* Update tail */
253                         td->control = DMA_COUNT(length) |
254                                         DMA_DESC_COF | DMA_DESC_IOF;
255                         /* Link to prev */
256                         lp->td_ring[chain_prev].control &=
257                                         ~DMA_DESC_COF;
258                         /* Link to prev */
259                         lp->td_ring[chain_prev].link =  CPHYSADDR(td);
260                         /* Move tail */
261                         lp->tx_chain_tail = chain_next;
262                         /* Write to NDPTR */
263                         writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),
264                                         &(lp->tx_dma_regs->dmandptr));
265                         /* Move head to tail */
266                         lp->tx_chain_head = lp->tx_chain_tail;
267                         lp->tx_chain_status = desc_empty;
268                 }
269         } else {
270                 if (lp->tx_chain_status == desc_empty) {
271                         /* Update tail */
272                         td->control = DMA_COUNT(length) |
273                                         DMA_DESC_COF | DMA_DESC_IOF;
274                         /* Move tail */
275                         lp->tx_chain_tail = chain_next;
276                         lp->tx_chain_status = desc_filled;
277                 } else {
278                         /* Update tail */
279                         td->control = DMA_COUNT(length) |
280                                         DMA_DESC_COF | DMA_DESC_IOF;
281                         lp->td_ring[chain_prev].control &=
282                                         ~DMA_DESC_COF;
283                         lp->td_ring[chain_prev].link =  CPHYSADDR(td);
284                         lp->tx_chain_tail = chain_next;
285                 }
286         }
287         dma_cache_wback((u32) td, sizeof(*td));
288
289         dev->trans_start = jiffies;
290         spin_unlock_irqrestore(&lp->lock, flags);
291
292         return NETDEV_TX_OK;
293 }
294
295 static int mdio_read(struct net_device *dev, int mii_id, int reg)
296 {
297         struct korina_private *lp = netdev_priv(dev);
298         int ret;
299
300         mii_id = ((lp->rx_irq == 0x2c ? 1 : 0) << 8);
301
302         writel(0, &lp->eth_regs->miimcfg);
303         writel(0, &lp->eth_regs->miimcmd);
304         writel(mii_id | reg, &lp->eth_regs->miimaddr);
305         writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd);
306
307         ret = (int)(readl(&lp->eth_regs->miimrdd));
308         return ret;
309 }
310
311 static void mdio_write(struct net_device *dev, int mii_id, int reg, int val)
312 {
313         struct korina_private *lp = netdev_priv(dev);
314
315         mii_id = ((lp->rx_irq == 0x2c ? 1 : 0) << 8);
316
317         writel(0, &lp->eth_regs->miimcfg);
318         writel(1, &lp->eth_regs->miimcmd);
319         writel(mii_id | reg, &lp->eth_regs->miimaddr);
320         writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd);
321         writel(val, &lp->eth_regs->miimwtd);
322 }
323
324 /* Ethernet Rx DMA interrupt */
325 static irqreturn_t korina_rx_dma_interrupt(int irq, void *dev_id)
326 {
327         struct net_device *dev = dev_id;
328         struct korina_private *lp = netdev_priv(dev);
329         u32 dmas, dmasm;
330         irqreturn_t retval;
331
332         dmas = readl(&lp->rx_dma_regs->dmas);
333         if (dmas & (DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR)) {
334                 dmasm = readl(&lp->rx_dma_regs->dmasm);
335                 writel(dmasm | (DMA_STAT_DONE |
336                                 DMA_STAT_HALT | DMA_STAT_ERR),
337                                 &lp->rx_dma_regs->dmasm);
338
339                 napi_schedule(&lp->napi);
340
341                 if (dmas & DMA_STAT_ERR)
342                         printk(KERN_ERR "%s: DMA error\n", dev->name);
343
344                 retval = IRQ_HANDLED;
345         } else
346                 retval = IRQ_NONE;
347
348         return retval;
349 }
350
351 static int korina_rx(struct net_device *dev, int limit)
352 {
353         struct korina_private *lp = netdev_priv(dev);
354         struct dma_desc *rd = &lp->rd_ring[lp->rx_next_done];
355         struct sk_buff *skb, *skb_new;
356         u8 *pkt_buf;
357         u32 devcs, pkt_len, dmas;
358         int count;
359
360         dma_cache_inv((u32)rd, sizeof(*rd));
361
362         for (count = 0; count < limit; count++) {
363                 skb = lp->rx_skb[lp->rx_next_done];
364                 skb_new = NULL;
365
366                 devcs = rd->devcs;
367
368                 if ((KORINA_RBSIZE - (u32)DMA_COUNT(rd->control)) == 0)
369                         break;
370
371                 /* Update statistics counters */
372                 if (devcs & ETH_RX_CRC)
373                         dev->stats.rx_crc_errors++;
374                 if (devcs & ETH_RX_LOR)
375                         dev->stats.rx_length_errors++;
376                 if (devcs & ETH_RX_LE)
377                         dev->stats.rx_length_errors++;
378                 if (devcs & ETH_RX_OVR)
379                         dev->stats.rx_fifo_errors++;
380                 if (devcs & ETH_RX_CV)
381                         dev->stats.rx_frame_errors++;
382                 if (devcs & ETH_RX_CES)
383                         dev->stats.rx_length_errors++;
384                 if (devcs & ETH_RX_MP)
385                         dev->stats.multicast++;
386
387                 if ((devcs & ETH_RX_LD) != ETH_RX_LD) {
388                         /* check that this is a whole packet
389                          * WARNING: DMA_FD bit incorrectly set
390                          * in Rc32434 (errata ref #077) */
391                         dev->stats.rx_errors++;
392                         dev->stats.rx_dropped++;
393                 } else if ((devcs & ETH_RX_ROK)) {
394                         pkt_len = RCVPKT_LENGTH(devcs);
395
396                         /* must be the (first and) last
397                          * descriptor then */
398                         pkt_buf = (u8 *)lp->rx_skb[lp->rx_next_done]->data;
399
400                         /* invalidate the cache */
401                         dma_cache_inv((unsigned long)pkt_buf, pkt_len - 4);
402
403                         /* Malloc up new buffer. */
404                         skb_new = netdev_alloc_skb_ip_align(dev, KORINA_RBSIZE);
405
406                         if (!skb_new)
407                                 break;
408                         /* Do not count the CRC */
409                         skb_put(skb, pkt_len - 4);
410                         skb->protocol = eth_type_trans(skb, dev);
411
412                         /* Pass the packet to upper layers */
413                         netif_receive_skb(skb);
414                         dev->stats.rx_packets++;
415                         dev->stats.rx_bytes += pkt_len;
416
417                         /* Update the mcast stats */
418                         if (devcs & ETH_RX_MP)
419                                 dev->stats.multicast++;
420
421                         lp->rx_skb[lp->rx_next_done] = skb_new;
422                 }
423
424                 rd->devcs = 0;
425
426                 /* Restore descriptor's curr_addr */
427                 if (skb_new)
428                         rd->ca = CPHYSADDR(skb_new->data);
429                 else
430                         rd->ca = CPHYSADDR(skb->data);
431
432                 rd->control = DMA_COUNT(KORINA_RBSIZE) |
433                         DMA_DESC_COD | DMA_DESC_IOD;
434                 lp->rd_ring[(lp->rx_next_done - 1) &
435                         KORINA_RDS_MASK].control &=
436                         ~DMA_DESC_COD;
437
438                 lp->rx_next_done = (lp->rx_next_done + 1) & KORINA_RDS_MASK;
439                 dma_cache_wback((u32)rd, sizeof(*rd));
440                 rd = &lp->rd_ring[lp->rx_next_done];
441                 writel(~DMA_STAT_DONE, &lp->rx_dma_regs->dmas);
442         }
443
444         dmas = readl(&lp->rx_dma_regs->dmas);
445
446         if (dmas & DMA_STAT_HALT) {
447                 writel(~(DMA_STAT_HALT | DMA_STAT_ERR),
448                                 &lp->rx_dma_regs->dmas);
449
450                 lp->dma_halt_cnt++;
451                 rd->devcs = 0;
452                 skb = lp->rx_skb[lp->rx_next_done];
453                 rd->ca = CPHYSADDR(skb->data);
454                 dma_cache_wback((u32)rd, sizeof(*rd));
455                 korina_chain_rx(lp, rd);
456         }
457
458         return count;
459 }
460
461 static int korina_poll(struct napi_struct *napi, int budget)
462 {
463         struct korina_private *lp =
464                 container_of(napi, struct korina_private, napi);
465         struct net_device *dev = lp->dev;
466         int work_done;
467
468         work_done = korina_rx(dev, budget);
469         if (work_done < budget) {
470                 napi_complete(napi);
471
472                 writel(readl(&lp->rx_dma_regs->dmasm) &
473                         ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR),
474                         &lp->rx_dma_regs->dmasm);
475         }
476         return work_done;
477 }
478
479 /*
480  * Set or clear the multicast filter for this adaptor.
481  */
482 static void korina_multicast_list(struct net_device *dev)
483 {
484         struct korina_private *lp = netdev_priv(dev);
485         unsigned long flags;
486         struct netdev_hw_addr *ha;
487         u32 recognise = ETH_ARC_AB;     /* always accept broadcasts */
488         int i;
489
490         /* Set promiscuous mode */
491         if (dev->flags & IFF_PROMISC)
492                 recognise |= ETH_ARC_PRO;
493
494         else if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 4))
495                 /* All multicast and broadcast */
496                 recognise |= ETH_ARC_AM;
497
498         /* Build the hash table */
499         if (netdev_mc_count(dev) > 4) {
500                 u16 hash_table[4];
501                 u32 crc;
502
503                 for (i = 0; i < 4; i++)
504                         hash_table[i] = 0;
505
506                 netdev_for_each_mc_addr(ha, dev) {
507                         char *addrs = ha->addr;
508
509                         if (!(*addrs & 1))
510                                 continue;
511
512                         crc = ether_crc_le(6, addrs);
513                         crc >>= 26;
514                         hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
515                 }
516                 /* Accept filtered multicast */
517                 recognise |= ETH_ARC_AFM;
518
519                 /* Fill the MAC hash tables with their values */
520                 writel((u32)(hash_table[1] << 16 | hash_table[0]),
521                                         &lp->eth_regs->ethhash0);
522                 writel((u32)(hash_table[3] << 16 | hash_table[2]),
523                                         &lp->eth_regs->ethhash1);
524         }
525
526         spin_lock_irqsave(&lp->lock, flags);
527         writel(recognise, &lp->eth_regs->etharc);
528         spin_unlock_irqrestore(&lp->lock, flags);
529 }
530
531 static void korina_tx(struct net_device *dev)
532 {
533         struct korina_private *lp = netdev_priv(dev);
534         struct dma_desc *td = &lp->td_ring[lp->tx_next_done];
535         u32 devcs;
536         u32 dmas;
537
538         spin_lock(&lp->lock);
539
540         /* Process all desc that are done */
541         while (IS_DMA_FINISHED(td->control)) {
542                 if (lp->tx_full == 1) {
543                         netif_wake_queue(dev);
544                         lp->tx_full = 0;
545                 }
546
547                 devcs = lp->td_ring[lp->tx_next_done].devcs;
548                 if ((devcs & (ETH_TX_FD | ETH_TX_LD)) !=
549                                 (ETH_TX_FD | ETH_TX_LD)) {
550                         dev->stats.tx_errors++;
551                         dev->stats.tx_dropped++;
552
553                         /* Should never happen */
554                         printk(KERN_ERR "%s: split tx ignored\n",
555                                                         dev->name);
556                 } else if (devcs & ETH_TX_TOK) {
557                         dev->stats.tx_packets++;
558                         dev->stats.tx_bytes +=
559                                         lp->tx_skb[lp->tx_next_done]->len;
560                 } else {
561                         dev->stats.tx_errors++;
562                         dev->stats.tx_dropped++;
563
564                         /* Underflow */
565                         if (devcs & ETH_TX_UND)
566                                 dev->stats.tx_fifo_errors++;
567
568                         /* Oversized frame */
569                         if (devcs & ETH_TX_OF)
570                                 dev->stats.tx_aborted_errors++;
571
572                         /* Excessive deferrals */
573                         if (devcs & ETH_TX_ED)
574                                 dev->stats.tx_carrier_errors++;
575
576                         /* Collisions: medium busy */
577                         if (devcs & ETH_TX_EC)
578                                 dev->stats.collisions++;
579
580                         /* Late collision */
581                         if (devcs & ETH_TX_LC)
582                                 dev->stats.tx_window_errors++;
583                 }
584
585                 /* We must always free the original skb */
586                 if (lp->tx_skb[lp->tx_next_done]) {
587                         dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
588                         lp->tx_skb[lp->tx_next_done] = NULL;
589                 }
590
591                 lp->td_ring[lp->tx_next_done].control = DMA_DESC_IOF;
592                 lp->td_ring[lp->tx_next_done].devcs = ETH_TX_FD | ETH_TX_LD;
593                 lp->td_ring[lp->tx_next_done].link = 0;
594                 lp->td_ring[lp->tx_next_done].ca = 0;
595                 lp->tx_count--;
596
597                 /* Go on to next transmission */
598                 lp->tx_next_done = (lp->tx_next_done + 1) & KORINA_TDS_MASK;
599                 td = &lp->td_ring[lp->tx_next_done];
600
601         }
602
603         /* Clear the DMA status register */
604         dmas = readl(&lp->tx_dma_regs->dmas);
605         writel(~dmas, &lp->tx_dma_regs->dmas);
606
607         writel(readl(&lp->tx_dma_regs->dmasm) &
608                         ~(DMA_STAT_FINI | DMA_STAT_ERR),
609                         &lp->tx_dma_regs->dmasm);
610
611         spin_unlock(&lp->lock);
612 }
613
614 static irqreturn_t
615 korina_tx_dma_interrupt(int irq, void *dev_id)
616 {
617         struct net_device *dev = dev_id;
618         struct korina_private *lp = netdev_priv(dev);
619         u32 dmas, dmasm;
620         irqreturn_t retval;
621
622         dmas = readl(&lp->tx_dma_regs->dmas);
623
624         if (dmas & (DMA_STAT_FINI | DMA_STAT_ERR)) {
625                 dmasm = readl(&lp->tx_dma_regs->dmasm);
626                 writel(dmasm | (DMA_STAT_FINI | DMA_STAT_ERR),
627                                 &lp->tx_dma_regs->dmasm);
628
629                 korina_tx(dev);
630
631                 if (lp->tx_chain_status == desc_filled &&
632                         (readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
633                         writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),
634                                 &(lp->tx_dma_regs->dmandptr));
635                         lp->tx_chain_status = desc_empty;
636                         lp->tx_chain_head = lp->tx_chain_tail;
637                         dev->trans_start = jiffies;
638                 }
639                 if (dmas & DMA_STAT_ERR)
640                         printk(KERN_ERR "%s: DMA error\n", dev->name);
641
642                 retval = IRQ_HANDLED;
643         } else
644                 retval = IRQ_NONE;
645
646         return retval;
647 }
648
649
650 static void korina_check_media(struct net_device *dev, unsigned int init_media)
651 {
652         struct korina_private *lp = netdev_priv(dev);
653
654         mii_check_media(&lp->mii_if, 0, init_media);
655
656         if (lp->mii_if.full_duplex)
657                 writel(readl(&lp->eth_regs->ethmac2) | ETH_MAC2_FD,
658                                                 &lp->eth_regs->ethmac2);
659         else
660                 writel(readl(&lp->eth_regs->ethmac2) & ~ETH_MAC2_FD,
661                                                 &lp->eth_regs->ethmac2);
662 }
663
664 static void korina_poll_media(unsigned long data)
665 {
666         struct net_device *dev = (struct net_device *) data;
667         struct korina_private *lp = netdev_priv(dev);
668
669         korina_check_media(dev, 0);
670         mod_timer(&lp->media_check_timer, jiffies + HZ);
671 }
672
673 static void korina_set_carrier(struct mii_if_info *mii)
674 {
675         if (mii->force_media) {
676                 /* autoneg is off: Link is always assumed to be up */
677                 if (!netif_carrier_ok(mii->dev))
678                         netif_carrier_on(mii->dev);
679         } else  /* Let MMI library update carrier status */
680                 korina_check_media(mii->dev, 0);
681 }
682
683 static int korina_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
684 {
685         struct korina_private *lp = netdev_priv(dev);
686         struct mii_ioctl_data *data = if_mii(rq);
687         int rc;
688
689         if (!netif_running(dev))
690                 return -EINVAL;
691         spin_lock_irq(&lp->lock);
692         rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
693         spin_unlock_irq(&lp->lock);
694         korina_set_carrier(&lp->mii_if);
695
696         return rc;
697 }
698
699 /* ethtool helpers */
700 static void netdev_get_drvinfo(struct net_device *dev,
701                         struct ethtool_drvinfo *info)
702 {
703         struct korina_private *lp = netdev_priv(dev);
704
705         strcpy(info->driver, DRV_NAME);
706         strcpy(info->version, DRV_VERSION);
707         strcpy(info->bus_info, lp->dev->name);
708 }
709
710 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
711 {
712         struct korina_private *lp = netdev_priv(dev);
713         int rc;
714
715         spin_lock_irq(&lp->lock);
716         rc = mii_ethtool_gset(&lp->mii_if, cmd);
717         spin_unlock_irq(&lp->lock);
718
719         return rc;
720 }
721
722 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
723 {
724         struct korina_private *lp = netdev_priv(dev);
725         int rc;
726
727         spin_lock_irq(&lp->lock);
728         rc = mii_ethtool_sset(&lp->mii_if, cmd);
729         spin_unlock_irq(&lp->lock);
730         korina_set_carrier(&lp->mii_if);
731
732         return rc;
733 }
734
735 static u32 netdev_get_link(struct net_device *dev)
736 {
737         struct korina_private *lp = netdev_priv(dev);
738
739         return mii_link_ok(&lp->mii_if);
740 }
741
742 static const struct ethtool_ops netdev_ethtool_ops = {
743         .get_drvinfo            = netdev_get_drvinfo,
744         .get_settings           = netdev_get_settings,
745         .set_settings           = netdev_set_settings,
746         .get_link               = netdev_get_link,
747 };
748
749 static int korina_alloc_ring(struct net_device *dev)
750 {
751         struct korina_private *lp = netdev_priv(dev);
752         struct sk_buff *skb;
753         int i;
754
755         /* Initialize the transmit descriptors */
756         for (i = 0; i < KORINA_NUM_TDS; i++) {
757                 lp->td_ring[i].control = DMA_DESC_IOF;
758                 lp->td_ring[i].devcs = ETH_TX_FD | ETH_TX_LD;
759                 lp->td_ring[i].ca = 0;
760                 lp->td_ring[i].link = 0;
761         }
762         lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail =
763                         lp->tx_full = lp->tx_count = 0;
764         lp->tx_chain_status = desc_empty;
765
766         /* Initialize the receive descriptors */
767         for (i = 0; i < KORINA_NUM_RDS; i++) {
768                 skb = netdev_alloc_skb_ip_align(dev, KORINA_RBSIZE);
769                 if (!skb)
770                         return -ENOMEM;
771                 lp->rx_skb[i] = skb;
772                 lp->rd_ring[i].control = DMA_DESC_IOD |
773                                 DMA_COUNT(KORINA_RBSIZE);
774                 lp->rd_ring[i].devcs = 0;
775                 lp->rd_ring[i].ca = CPHYSADDR(skb->data);
776                 lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
777         }
778
779         /* loop back receive descriptors, so the last
780          * descriptor points to the first one */
781         lp->rd_ring[i - 1].link = CPHYSADDR(&lp->rd_ring[0]);
782         lp->rd_ring[i - 1].control |= DMA_DESC_COD;
783
784         lp->rx_next_done  = 0;
785         lp->rx_chain_head = 0;
786         lp->rx_chain_tail = 0;
787         lp->rx_chain_status = desc_empty;
788
789         return 0;
790 }
791
792 static void korina_free_ring(struct net_device *dev)
793 {
794         struct korina_private *lp = netdev_priv(dev);
795         int i;
796
797         for (i = 0; i < KORINA_NUM_RDS; i++) {
798                 lp->rd_ring[i].control = 0;
799                 if (lp->rx_skb[i])
800                         dev_kfree_skb_any(lp->rx_skb[i]);
801                 lp->rx_skb[i] = NULL;
802         }
803
804         for (i = 0; i < KORINA_NUM_TDS; i++) {
805                 lp->td_ring[i].control = 0;
806                 if (lp->tx_skb[i])
807                         dev_kfree_skb_any(lp->tx_skb[i]);
808                 lp->tx_skb[i] = NULL;
809         }
810 }
811
812 /*
813  * Initialize the RC32434 ethernet controller.
814  */
815 static int korina_init(struct net_device *dev)
816 {
817         struct korina_private *lp = netdev_priv(dev);
818
819         /* Disable DMA */
820         korina_abort_tx(dev);
821         korina_abort_rx(dev);
822
823         /* reset ethernet logic */
824         writel(0, &lp->eth_regs->ethintfc);
825         while ((readl(&lp->eth_regs->ethintfc) & ETH_INT_FC_RIP))
826                 dev->trans_start = jiffies;
827
828         /* Enable Ethernet Interface */
829         writel(ETH_INT_FC_EN, &lp->eth_regs->ethintfc);
830
831         /* Allocate rings */
832         if (korina_alloc_ring(dev)) {
833                 printk(KERN_ERR "%s: descriptor allocation failed\n", dev->name);
834                 korina_free_ring(dev);
835                 return -ENOMEM;
836         }
837
838         writel(0, &lp->rx_dma_regs->dmas);
839         /* Start Rx DMA */
840         korina_start_rx(lp, &lp->rd_ring[0]);
841
842         writel(readl(&lp->tx_dma_regs->dmasm) &
843                         ~(DMA_STAT_FINI | DMA_STAT_ERR),
844                         &lp->tx_dma_regs->dmasm);
845         writel(readl(&lp->rx_dma_regs->dmasm) &
846                         ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR),
847                         &lp->rx_dma_regs->dmasm);
848
849         /* Accept only packets destined for this Ethernet device address */
850         writel(ETH_ARC_AB, &lp->eth_regs->etharc);
851
852         /* Set all Ether station address registers to their initial values */
853         writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
854         writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
855
856         writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
857         writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
858
859         writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
860         writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
861
862         writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
863         writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
864
865
866         /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
867         writel(ETH_MAC2_PE | ETH_MAC2_CEN | ETH_MAC2_FD,
868                         &lp->eth_regs->ethmac2);
869
870         /* Back to back inter-packet-gap */
871         writel(0x15, &lp->eth_regs->ethipgt);
872         /* Non - Back to back inter-packet-gap */
873         writel(0x12, &lp->eth_regs->ethipgr);
874
875         /* Management Clock Prescaler Divisor
876          * Clock independent setting */
877         writel(((idt_cpu_freq) / MII_CLOCK + 1) & ~1,
878                        &lp->eth_regs->ethmcp);
879
880         /* don't transmit until fifo contains 48b */
881         writel(48, &lp->eth_regs->ethfifott);
882
883         writel(ETH_MAC1_RE, &lp->eth_regs->ethmac1);
884
885         napi_enable(&lp->napi);
886         netif_start_queue(dev);
887
888         return 0;
889 }
890
891 /*
892  * Restart the RC32434 ethernet controller.
893  */
894 static void korina_restart_task(struct work_struct *work)
895 {
896         struct korina_private *lp = container_of(work,
897                         struct korina_private, restart_task);
898         struct net_device *dev = lp->dev;
899
900         /*
901          * Disable interrupts
902          */
903         disable_irq(lp->rx_irq);
904         disable_irq(lp->tx_irq);
905         disable_irq(lp->ovr_irq);
906         disable_irq(lp->und_irq);
907
908         writel(readl(&lp->tx_dma_regs->dmasm) |
909                                 DMA_STAT_FINI | DMA_STAT_ERR,
910                                 &lp->tx_dma_regs->dmasm);
911         writel(readl(&lp->rx_dma_regs->dmasm) |
912                                 DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR,
913                                 &lp->rx_dma_regs->dmasm);
914
915         korina_free_ring(dev);
916
917         napi_disable(&lp->napi);
918
919         if (korina_init(dev) < 0) {
920                 printk(KERN_ERR "%s: cannot restart device\n", dev->name);
921                 return;
922         }
923         korina_multicast_list(dev);
924
925         enable_irq(lp->und_irq);
926         enable_irq(lp->ovr_irq);
927         enable_irq(lp->tx_irq);
928         enable_irq(lp->rx_irq);
929 }
930
931 static void korina_clear_and_restart(struct net_device *dev, u32 value)
932 {
933         struct korina_private *lp = netdev_priv(dev);
934
935         netif_stop_queue(dev);
936         writel(value, &lp->eth_regs->ethintfc);
937         schedule_work(&lp->restart_task);
938 }
939
940 /* Ethernet Tx Underflow interrupt */
941 static irqreturn_t korina_und_interrupt(int irq, void *dev_id)
942 {
943         struct net_device *dev = dev_id;
944         struct korina_private *lp = netdev_priv(dev);
945         unsigned int und;
946
947         spin_lock(&lp->lock);
948
949         und = readl(&lp->eth_regs->ethintfc);
950
951         if (und & ETH_INT_FC_UND)
952                 korina_clear_and_restart(dev, und & ~ETH_INT_FC_UND);
953
954         spin_unlock(&lp->lock);
955
956         return IRQ_HANDLED;
957 }
958
959 static void korina_tx_timeout(struct net_device *dev)
960 {
961         struct korina_private *lp = netdev_priv(dev);
962
963         schedule_work(&lp->restart_task);
964 }
965
966 /* Ethernet Rx Overflow interrupt */
967 static irqreturn_t
968 korina_ovr_interrupt(int irq, void *dev_id)
969 {
970         struct net_device *dev = dev_id;
971         struct korina_private *lp = netdev_priv(dev);
972         unsigned int ovr;
973
974         spin_lock(&lp->lock);
975         ovr = readl(&lp->eth_regs->ethintfc);
976
977         if (ovr & ETH_INT_FC_OVR)
978                 korina_clear_and_restart(dev, ovr & ~ETH_INT_FC_OVR);
979
980         spin_unlock(&lp->lock);
981
982         return IRQ_HANDLED;
983 }
984
985 #ifdef CONFIG_NET_POLL_CONTROLLER
986 static void korina_poll_controller(struct net_device *dev)
987 {
988         disable_irq(dev->irq);
989         korina_tx_dma_interrupt(dev->irq, dev);
990         enable_irq(dev->irq);
991 }
992 #endif
993
994 static int korina_open(struct net_device *dev)
995 {
996         struct korina_private *lp = netdev_priv(dev);
997         int ret;
998
999         /* Initialize */
1000         ret = korina_init(dev);
1001         if (ret < 0) {
1002                 printk(KERN_ERR "%s: cannot open device\n", dev->name);
1003                 goto out;
1004         }
1005
1006         /* Install the interrupt handler
1007          * that handles the Done Finished
1008          * Ovr and Und Events */
1009         ret = request_irq(lp->rx_irq, korina_rx_dma_interrupt,
1010                         IRQF_DISABLED, "Korina ethernet Rx", dev);
1011         if (ret < 0) {
1012                 printk(KERN_ERR "%s: unable to get Rx DMA IRQ %d\n",
1013                     dev->name, lp->rx_irq);
1014                 goto err_release;
1015         }
1016         ret = request_irq(lp->tx_irq, korina_tx_dma_interrupt,
1017                         IRQF_DISABLED, "Korina ethernet Tx", dev);
1018         if (ret < 0) {
1019                 printk(KERN_ERR "%s: unable to get Tx DMA IRQ %d\n",
1020                     dev->name, lp->tx_irq);
1021                 goto err_free_rx_irq;
1022         }
1023
1024         /* Install handler for overrun error. */
1025         ret = request_irq(lp->ovr_irq, korina_ovr_interrupt,
1026                         IRQF_DISABLED, "Ethernet Overflow", dev);
1027         if (ret < 0) {
1028                 printk(KERN_ERR "%s: unable to get OVR IRQ %d\n",
1029                     dev->name, lp->ovr_irq);
1030                 goto err_free_tx_irq;
1031         }
1032
1033         /* Install handler for underflow error. */
1034         ret = request_irq(lp->und_irq, korina_und_interrupt,
1035                         IRQF_DISABLED, "Ethernet Underflow", dev);
1036         if (ret < 0) {
1037                 printk(KERN_ERR "%s: unable to get UND IRQ %d\n",
1038                     dev->name, lp->und_irq);
1039                 goto err_free_ovr_irq;
1040         }
1041         mod_timer(&lp->media_check_timer, jiffies + 1);
1042 out:
1043         return ret;
1044
1045 err_free_ovr_irq:
1046         free_irq(lp->ovr_irq, dev);
1047 err_free_tx_irq:
1048         free_irq(lp->tx_irq, dev);
1049 err_free_rx_irq:
1050         free_irq(lp->rx_irq, dev);
1051 err_release:
1052         korina_free_ring(dev);
1053         goto out;
1054 }
1055
1056 static int korina_close(struct net_device *dev)
1057 {
1058         struct korina_private *lp = netdev_priv(dev);
1059         u32 tmp;
1060
1061         del_timer(&lp->media_check_timer);
1062
1063         /* Disable interrupts */
1064         disable_irq(lp->rx_irq);
1065         disable_irq(lp->tx_irq);
1066         disable_irq(lp->ovr_irq);
1067         disable_irq(lp->und_irq);
1068
1069         korina_abort_tx(dev);
1070         tmp = readl(&lp->tx_dma_regs->dmasm);
1071         tmp = tmp | DMA_STAT_FINI | DMA_STAT_ERR;
1072         writel(tmp, &lp->tx_dma_regs->dmasm);
1073
1074         korina_abort_rx(dev);
1075         tmp = readl(&lp->rx_dma_regs->dmasm);
1076         tmp = tmp | DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR;
1077         writel(tmp, &lp->rx_dma_regs->dmasm);
1078
1079         korina_free_ring(dev);
1080
1081         napi_disable(&lp->napi);
1082
1083         cancel_work_sync(&lp->restart_task);
1084
1085         free_irq(lp->rx_irq, dev);
1086         free_irq(lp->tx_irq, dev);
1087         free_irq(lp->ovr_irq, dev);
1088         free_irq(lp->und_irq, dev);
1089
1090         return 0;
1091 }
1092
1093 static const struct net_device_ops korina_netdev_ops = {
1094         .ndo_open               = korina_open,
1095         .ndo_stop               = korina_close,
1096         .ndo_start_xmit         = korina_send_packet,
1097         .ndo_set_multicast_list = korina_multicast_list,
1098         .ndo_tx_timeout         = korina_tx_timeout,
1099         .ndo_do_ioctl           = korina_ioctl,
1100         .ndo_change_mtu         = eth_change_mtu,
1101         .ndo_validate_addr      = eth_validate_addr,
1102         .ndo_set_mac_address    = eth_mac_addr,
1103 #ifdef CONFIG_NET_POLL_CONTROLLER
1104         .ndo_poll_controller    = korina_poll_controller,
1105 #endif
1106 };
1107
1108 static int korina_probe(struct platform_device *pdev)
1109 {
1110         struct korina_device *bif = platform_get_drvdata(pdev);
1111         struct korina_private *lp;
1112         struct net_device *dev;
1113         struct resource *r;
1114         int rc;
1115
1116         dev = alloc_etherdev(sizeof(struct korina_private));
1117         if (!dev) {
1118                 printk(KERN_ERR DRV_NAME ": alloc_etherdev failed\n");
1119                 return -ENOMEM;
1120         }
1121         SET_NETDEV_DEV(dev, &pdev->dev);
1122         lp = netdev_priv(dev);
1123
1124         bif->dev = dev;
1125         memcpy(dev->dev_addr, bif->mac, 6);
1126
1127         lp->rx_irq = platform_get_irq_byname(pdev, "korina_rx");
1128         lp->tx_irq = platform_get_irq_byname(pdev, "korina_tx");
1129         lp->ovr_irq = platform_get_irq_byname(pdev, "korina_ovr");
1130         lp->und_irq = platform_get_irq_byname(pdev, "korina_und");
1131
1132         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_regs");
1133         dev->base_addr = r->start;
1134         lp->eth_regs = ioremap_nocache(r->start, resource_size(r));
1135         if (!lp->eth_regs) {
1136                 printk(KERN_ERR DRV_NAME ": cannot remap registers\n");
1137                 rc = -ENXIO;
1138                 goto probe_err_out;
1139         }
1140
1141         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_rx");
1142         lp->rx_dma_regs = ioremap_nocache(r->start, resource_size(r));
1143         if (!lp->rx_dma_regs) {
1144                 printk(KERN_ERR DRV_NAME ": cannot remap Rx DMA registers\n");
1145                 rc = -ENXIO;
1146                 goto probe_err_dma_rx;
1147         }
1148
1149         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_tx");
1150         lp->tx_dma_regs = ioremap_nocache(r->start, resource_size(r));
1151         if (!lp->tx_dma_regs) {
1152                 printk(KERN_ERR DRV_NAME ": cannot remap Tx DMA registers\n");
1153                 rc = -ENXIO;
1154                 goto probe_err_dma_tx;
1155         }
1156
1157         lp->td_ring = kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1158         if (!lp->td_ring) {
1159                 printk(KERN_ERR DRV_NAME ": cannot allocate descriptors\n");
1160                 rc = -ENXIO;
1161                 goto probe_err_td_ring;
1162         }
1163
1164         dma_cache_inv((unsigned long)(lp->td_ring),
1165                         TD_RING_SIZE + RD_RING_SIZE);
1166
1167         /* now convert TD_RING pointer to KSEG1 */
1168         lp->td_ring = (struct dma_desc *)KSEG1ADDR(lp->td_ring);
1169         lp->rd_ring = &lp->td_ring[KORINA_NUM_TDS];
1170
1171         spin_lock_init(&lp->lock);
1172         /* just use the rx dma irq */
1173         dev->irq = lp->rx_irq;
1174         lp->dev = dev;
1175
1176         dev->netdev_ops = &korina_netdev_ops;
1177         dev->ethtool_ops = &netdev_ethtool_ops;
1178         dev->watchdog_timeo = TX_TIMEOUT;
1179         netif_napi_add(dev, &lp->napi, korina_poll, 64);
1180
1181         lp->phy_addr = (((lp->rx_irq == 0x2c? 1:0) << 8) | 0x05);
1182         lp->mii_if.dev = dev;
1183         lp->mii_if.mdio_read = mdio_read;
1184         lp->mii_if.mdio_write = mdio_write;
1185         lp->mii_if.phy_id = lp->phy_addr;
1186         lp->mii_if.phy_id_mask = 0x1f;
1187         lp->mii_if.reg_num_mask = 0x1f;
1188
1189         rc = register_netdev(dev);
1190         if (rc < 0) {
1191                 printk(KERN_ERR DRV_NAME
1192                         ": cannot register net device: %d\n", rc);
1193                 goto probe_err_register;
1194         }
1195         setup_timer(&lp->media_check_timer, korina_poll_media, (unsigned long) dev);
1196
1197         INIT_WORK(&lp->restart_task, korina_restart_task);
1198
1199         printk(KERN_INFO "%s: " DRV_NAME "-" DRV_VERSION " " DRV_RELDATE "\n",
1200                         dev->name);
1201 out:
1202         return rc;
1203
1204 probe_err_register:
1205         kfree(lp->td_ring);
1206 probe_err_td_ring:
1207         iounmap(lp->tx_dma_regs);
1208 probe_err_dma_tx:
1209         iounmap(lp->rx_dma_regs);
1210 probe_err_dma_rx:
1211         iounmap(lp->eth_regs);
1212 probe_err_out:
1213         free_netdev(dev);
1214         goto out;
1215 }
1216
1217 static int korina_remove(struct platform_device *pdev)
1218 {
1219         struct korina_device *bif = platform_get_drvdata(pdev);
1220         struct korina_private *lp = netdev_priv(bif->dev);
1221
1222         iounmap(lp->eth_regs);
1223         iounmap(lp->rx_dma_regs);
1224         iounmap(lp->tx_dma_regs);
1225
1226         platform_set_drvdata(pdev, NULL);
1227         unregister_netdev(bif->dev);
1228         free_netdev(bif->dev);
1229
1230         return 0;
1231 }
1232
1233 static struct platform_driver korina_driver = {
1234         .driver.name = "korina",
1235         .probe = korina_probe,
1236         .remove = korina_remove,
1237 };
1238
1239 static int __init korina_init_module(void)
1240 {
1241         return platform_driver_register(&korina_driver);
1242 }
1243
1244 static void korina_cleanup_module(void)
1245 {
1246         return platform_driver_unregister(&korina_driver);
1247 }
1248
1249 module_init(korina_init_module);
1250 module_exit(korina_cleanup_module);
1251
1252 MODULE_AUTHOR("Philip Rischel <rischelp@idt.com>");
1253 MODULE_AUTHOR("Felix Fietkau <nbd@openwrt.org>");
1254 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
1255 MODULE_DESCRIPTION("IDT RC32434 (Korina) Ethernet driver");
1256 MODULE_LICENSE("GPL");