pch_can: fix 800k comms issue
[linux-2.6.git] / drivers / net / jme.h
1 /*
2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3  *
4  * Copyright 2008 JMicron Technology Corporation
5  * http://www.jmicron.com/
6  * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7  *
8  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22  *
23  */
24
25 #ifndef __JME_H_INCLUDED__
26 #define __JME_H_INCLUDED__
27
28 #define DRV_NAME        "jme"
29 #define DRV_VERSION     "1.0.7"
30 #define PFX             DRV_NAME ": "
31
32 #define PCI_DEVICE_ID_JMICRON_JMC250    0x0250
33 #define PCI_DEVICE_ID_JMICRON_JMC260    0x0260
34
35 /*
36  * Message related definitions
37  */
38 #define JME_DEF_MSG_ENABLE \
39         (NETIF_MSG_PROBE | \
40         NETIF_MSG_LINK | \
41         NETIF_MSG_RX_ERR | \
42         NETIF_MSG_TX_ERR | \
43         NETIF_MSG_HW)
44
45 #ifdef TX_DEBUG
46 #define tx_dbg(priv, fmt, args...)                                      \
47         printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
48 #else
49 #define tx_dbg(priv, fmt, args...)                                      \
50 do {                                                                    \
51         if (0)                                                          \
52                 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
53 } while (0)
54 #endif
55
56 /*
57  * Extra PCI Configuration space interface
58  */
59 #define PCI_DCSR_MRRS           0x59
60 #define PCI_DCSR_MRRS_MASK      0x70
61
62 enum pci_dcsr_mrrs_vals {
63         MRRS_128B       = 0x00,
64         MRRS_256B       = 0x10,
65         MRRS_512B       = 0x20,
66         MRRS_1024B      = 0x30,
67         MRRS_2048B      = 0x40,
68         MRRS_4096B      = 0x50,
69 };
70
71 #define PCI_SPI                 0xB0
72
73 enum pci_spi_bits {
74         SPI_EN          = 0x10,
75         SPI_MISO        = 0x08,
76         SPI_MOSI        = 0x04,
77         SPI_SCLK        = 0x02,
78         SPI_CS          = 0x01,
79 };
80
81 struct jme_spi_op {
82         void __user *uwbuf;
83         void __user *urbuf;
84         __u8    wn;     /* Number of write actions */
85         __u8    rn;     /* Number of read actions */
86         __u8    bitn;   /* Number of bits per action */
87         __u8    spd;    /* The maxim acceptable speed of controller, in MHz.*/
88         __u8    mode;   /* CPOL, CPHA, and Duplex mode of SPI */
89
90         /* Internal use only */
91         u8      *kwbuf;
92         u8      *krbuf;
93         u8      sr;
94         u16     halfclk; /* Half of clock cycle calculated from spd, in ns */
95 };
96
97 enum jme_spi_op_bits {
98         SPI_MODE_CPHA   = 0x01,
99         SPI_MODE_CPOL   = 0x02,
100         SPI_MODE_DUP    = 0x80,
101 };
102
103 #define HALF_US 500     /* 500 ns */
104 #define JMESPIIOCTL     SIOCDEVPRIVATE
105
106 /*
107  * Dynamic(adaptive)/Static PCC values
108  */
109 enum dynamic_pcc_values {
110         PCC_OFF         = 0,
111         PCC_P1          = 1,
112         PCC_P2          = 2,
113         PCC_P3          = 3,
114
115         PCC_OFF_TO      = 0,
116         PCC_P1_TO       = 1,
117         PCC_P2_TO       = 64,
118         PCC_P3_TO       = 128,
119
120         PCC_OFF_CNT     = 0,
121         PCC_P1_CNT      = 1,
122         PCC_P2_CNT      = 16,
123         PCC_P3_CNT      = 32,
124 };
125 struct dynpcc_info {
126         unsigned long   last_bytes;
127         unsigned long   last_pkts;
128         unsigned long   intr_cnt;
129         unsigned char   cur;
130         unsigned char   attempt;
131         unsigned char   cnt;
132 };
133 #define PCC_INTERVAL_US 100000
134 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
135 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
136 #define PCC_P2_THRESHOLD 800
137 #define PCC_INTR_THRESHOLD 800
138 #define PCC_TX_TO 1000
139 #define PCC_TX_CNT 8
140
141 /*
142  * TX/RX Descriptors
143  *
144  * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
145  */
146 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
147 #define TX_DESC_SIZE            16
148 #define TX_RING_NR              8
149 #define TX_RING_ALLOC_SIZE(s)   ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
150
151 struct txdesc {
152         union {
153                 __u8    all[16];
154                 __le32  dw[4];
155                 struct {
156                         /* DW0 */
157                         __le16  vlan;
158                         __u8    rsv1;
159                         __u8    flags;
160
161                         /* DW1 */
162                         __le16  datalen;
163                         __le16  mss;
164
165                         /* DW2 */
166                         __le16  pktsize;
167                         __le16  rsv2;
168
169                         /* DW3 */
170                         __le32  bufaddr;
171                 } desc1;
172                 struct {
173                         /* DW0 */
174                         __le16  rsv1;
175                         __u8    rsv2;
176                         __u8    flags;
177
178                         /* DW1 */
179                         __le16  datalen;
180                         __le16  rsv3;
181
182                         /* DW2 */
183                         __le32  bufaddrh;
184
185                         /* DW3 */
186                         __le32  bufaddrl;
187                 } desc2;
188                 struct {
189                         /* DW0 */
190                         __u8    ehdrsz;
191                         __u8    rsv1;
192                         __u8    rsv2;
193                         __u8    flags;
194
195                         /* DW1 */
196                         __le16  trycnt;
197                         __le16  segcnt;
198
199                         /* DW2 */
200                         __le16  pktsz;
201                         __le16  rsv3;
202
203                         /* DW3 */
204                         __le32  bufaddrl;
205                 } descwb;
206         };
207 };
208
209 enum jme_txdesc_flags_bits {
210         TXFLAG_OWN      = 0x80,
211         TXFLAG_INT      = 0x40,
212         TXFLAG_64BIT    = 0x20,
213         TXFLAG_TCPCS    = 0x10,
214         TXFLAG_UDPCS    = 0x08,
215         TXFLAG_IPCS     = 0x04,
216         TXFLAG_LSEN     = 0x02,
217         TXFLAG_TAGON    = 0x01,
218 };
219
220 #define TXDESC_MSS_SHIFT        2
221 enum jme_txwbdesc_flags_bits {
222         TXWBFLAG_OWN    = 0x80,
223         TXWBFLAG_INT    = 0x40,
224         TXWBFLAG_TMOUT  = 0x20,
225         TXWBFLAG_TRYOUT = 0x10,
226         TXWBFLAG_COL    = 0x08,
227
228         TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
229                           TXWBFLAG_TRYOUT |
230                           TXWBFLAG_COL,
231 };
232
233 #define RX_DESC_SIZE            16
234 #define RX_RING_NR              4
235 #define RX_RING_ALLOC_SIZE(s)   ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
236 #define RX_BUF_DMA_ALIGN        8
237 #define RX_PREPAD_SIZE          10
238 #define ETH_CRC_LEN             2
239 #define RX_VLANHDR_LEN          2
240 #define RX_EXTRA_LEN            (RX_PREPAD_SIZE + \
241                                 ETH_HLEN + \
242                                 ETH_CRC_LEN + \
243                                 RX_VLANHDR_LEN + \
244                                 RX_BUF_DMA_ALIGN)
245
246 struct rxdesc {
247         union {
248                 __u8    all[16];
249                 __le32  dw[4];
250                 struct {
251                         /* DW0 */
252                         __le16  rsv2;
253                         __u8    rsv1;
254                         __u8    flags;
255
256                         /* DW1 */
257                         __le16  datalen;
258                         __le16  wbcpl;
259
260                         /* DW2 */
261                         __le32  bufaddrh;
262
263                         /* DW3 */
264                         __le32  bufaddrl;
265                 } desc1;
266                 struct {
267                         /* DW0 */
268                         __le16  vlan;
269                         __le16  flags;
270
271                         /* DW1 */
272                         __le16  framesize;
273                         __u8    errstat;
274                         __u8    desccnt;
275
276                         /* DW2 */
277                         __le32  rsshash;
278
279                         /* DW3 */
280                         __u8    hashfun;
281                         __u8    hashtype;
282                         __le16  resrv;
283                 } descwb;
284         };
285 };
286
287 enum jme_rxdesc_flags_bits {
288         RXFLAG_OWN      = 0x80,
289         RXFLAG_INT      = 0x40,
290         RXFLAG_64BIT    = 0x20,
291 };
292
293 enum jme_rxwbdesc_flags_bits {
294         RXWBFLAG_OWN            = 0x8000,
295         RXWBFLAG_INT            = 0x4000,
296         RXWBFLAG_MF             = 0x2000,
297         RXWBFLAG_64BIT          = 0x2000,
298         RXWBFLAG_TCPON          = 0x1000,
299         RXWBFLAG_UDPON          = 0x0800,
300         RXWBFLAG_IPCS           = 0x0400,
301         RXWBFLAG_TCPCS          = 0x0200,
302         RXWBFLAG_UDPCS          = 0x0100,
303         RXWBFLAG_TAGON          = 0x0080,
304         RXWBFLAG_IPV4           = 0x0040,
305         RXWBFLAG_IPV6           = 0x0020,
306         RXWBFLAG_PAUSE          = 0x0010,
307         RXWBFLAG_MAGIC          = 0x0008,
308         RXWBFLAG_WAKEUP         = 0x0004,
309         RXWBFLAG_DEST           = 0x0003,
310         RXWBFLAG_DEST_UNI       = 0x0001,
311         RXWBFLAG_DEST_MUL       = 0x0002,
312         RXWBFLAG_DEST_BRO       = 0x0003,
313 };
314
315 enum jme_rxwbdesc_desccnt_mask {
316         RXWBDCNT_WBCPL  = 0x80,
317         RXWBDCNT_DCNT   = 0x7F,
318 };
319
320 enum jme_rxwbdesc_errstat_bits {
321         RXWBERR_LIMIT   = 0x80,
322         RXWBERR_MIIER   = 0x40,
323         RXWBERR_NIBON   = 0x20,
324         RXWBERR_COLON   = 0x10,
325         RXWBERR_ABORT   = 0x08,
326         RXWBERR_SHORT   = 0x04,
327         RXWBERR_OVERUN  = 0x02,
328         RXWBERR_CRCERR  = 0x01,
329         RXWBERR_ALLERR  = 0xFF,
330 };
331
332 /*
333  * Buffer information corresponding to ring descriptors.
334  */
335 struct jme_buffer_info {
336         struct sk_buff *skb;
337         dma_addr_t mapping;
338         int len;
339         int nr_desc;
340         unsigned long start_xmit;
341 };
342
343 /*
344  * The structure holding buffer information and ring descriptors all together.
345  */
346 struct jme_ring {
347         void *alloc;            /* pointer to allocated memory */
348         void *desc;             /* pointer to ring memory  */
349         dma_addr_t dmaalloc;    /* phys address of ring alloc */
350         dma_addr_t dma;         /* phys address for ring dma */
351
352         /* Buffer information corresponding to each descriptor */
353         struct jme_buffer_info *bufinf;
354
355         int next_to_use;
356         atomic_t next_to_clean;
357         atomic_t nr_free;
358 };
359
360 #define NET_STAT(priv) (priv->dev->stats)
361 #define NETDEV_GET_STATS(netdev, fun_ptr)
362 #define DECLARE_NET_DEVICE_STATS
363
364 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
365 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
366         netif_napi_add(dev, napis, pollfn, q);
367 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
368 #define JME_NAPI_WEIGHT(w) int w
369 #define JME_NAPI_WEIGHT_VAL(w) w
370 #define JME_NAPI_WEIGHT_SET(w, r)
371 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
372 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
373 #define JME_NAPI_DISABLE(priv) \
374         if (!napi_disable_pending(&priv->napi)) \
375                 napi_disable(&priv->napi);
376 #define JME_RX_SCHEDULE_PREP(priv) \
377         napi_schedule_prep(&priv->napi)
378 #define JME_RX_SCHEDULE(priv) \
379         __napi_schedule(&priv->napi);
380
381 /*
382  * Jmac Adapter Private data
383  */
384 struct jme_adapter {
385         struct pci_dev          *pdev;
386         struct net_device       *dev;
387         void __iomem            *regs;
388         struct mii_if_info      mii_if;
389         struct jme_ring         rxring[RX_RING_NR];
390         struct jme_ring         txring[TX_RING_NR];
391         spinlock_t              phy_lock;
392         spinlock_t              macaddr_lock;
393         spinlock_t              rxmcs_lock;
394         struct tasklet_struct   rxempty_task;
395         struct tasklet_struct   rxclean_task;
396         struct tasklet_struct   txclean_task;
397         struct tasklet_struct   linkch_task;
398         struct tasklet_struct   pcc_task;
399         unsigned long           flags;
400         u32                     reg_txcs;
401         u32                     reg_txpfc;
402         u32                     reg_rxcs;
403         u32                     reg_rxmcs;
404         u32                     reg_ghc;
405         u32                     reg_pmcs;
406         u32                     phylink;
407         u32                     tx_ring_size;
408         u32                     tx_ring_mask;
409         u32                     tx_wake_threshold;
410         u32                     rx_ring_size;
411         u32                     rx_ring_mask;
412         u8                      mrrs;
413         unsigned int            fpgaver;
414         unsigned int            chiprev;
415         u8                      rev;
416         u32                     msg_enable;
417         struct ethtool_cmd      old_ecmd;
418         unsigned int            old_mtu;
419         struct vlan_group       *vlgrp;
420         struct dynpcc_info      dpi;
421         atomic_t                intr_sem;
422         atomic_t                link_changing;
423         atomic_t                tx_cleaning;
424         atomic_t                rx_cleaning;
425         atomic_t                rx_empty;
426         int                     (*jme_rx)(struct sk_buff *skb);
427         int                     (*jme_vlan_rx)(struct sk_buff *skb,
428                                           struct vlan_group *grp,
429                                           unsigned short vlan_tag);
430         DECLARE_NAPI_STRUCT
431         DECLARE_NET_DEVICE_STATS
432 };
433
434 enum jme_flags_bits {
435         JME_FLAG_MSI            = 1,
436         JME_FLAG_SSET           = 2,
437         JME_FLAG_TXCSUM         = 3,
438         JME_FLAG_TSO            = 4,
439         JME_FLAG_POLL           = 5,
440         JME_FLAG_SHUTDOWN       = 6,
441 };
442
443 #define TX_TIMEOUT              (5 * HZ)
444 #define JME_REG_LEN             0x500
445 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
446
447 static inline struct jme_adapter*
448 jme_napi_priv(struct napi_struct *napi)
449 {
450         struct jme_adapter *jme;
451         jme = container_of(napi, struct jme_adapter, napi);
452         return jme;
453 }
454
455 /*
456  * MMaped I/O Resters
457  */
458 enum jme_iomap_offsets {
459         JME_MAC         = 0x0000,
460         JME_PHY         = 0x0400,
461         JME_MISC        = 0x0800,
462         JME_RSS         = 0x0C00,
463 };
464
465 enum jme_iomap_lens {
466         JME_MAC_LEN     = 0x80,
467         JME_PHY_LEN     = 0x58,
468         JME_MISC_LEN    = 0x98,
469         JME_RSS_LEN     = 0xFF,
470 };
471
472 enum jme_iomap_regs {
473         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
474         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
475         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
476         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
477         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
478         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
479         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
480         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
481
482         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
483         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
484         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
485         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
486         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
487         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
488         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
489         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
490         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
491         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
492         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
493         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
494
495         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
496         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
497         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
498
499
500         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
501         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
502         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
503         JME_SMBINTF     = JME_PHY | 0x44, /* SMB Interface */
504
505
506         JME_TMCSR       = JME_MISC | 0x00, /* Timer Control/Status Register */
507         JME_GPREG0      = JME_MISC | 0x08, /* General purpose REG-0 */
508         JME_GPREG1      = JME_MISC | 0x0C, /* General purpose REG-1 */
509         JME_IEVE        = JME_MISC | 0x20, /* Interrupt Event Status */
510         JME_IREQ        = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
511         JME_IENS        = JME_MISC | 0x28, /* Intr Enable - Setting Port */
512         JME_IENC        = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
513         JME_PCCRX0      = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
514         JME_PCCTX       = JME_MISC | 0x40, /* PCC Control for TX Queues */
515         JME_CHIPMODE    = JME_MISC | 0x44, /* Identify FPGA Version */
516         JME_SHBA_HI     = JME_MISC | 0x48, /* Shadow Register Base HI */
517         JME_SHBA_LO     = JME_MISC | 0x4C, /* Shadow Register Base LO */
518         JME_TIMER1      = JME_MISC | 0x70, /* Timer1 */
519         JME_TIMER2      = JME_MISC | 0x74, /* Timer2 */
520         JME_APMC        = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
521         JME_PCCSRX0     = JME_MISC | 0x80, /* PCC Status of RX0 */
522 };
523
524 /*
525  * TX Control/Status Bits
526  */
527 enum jme_txcs_bits {
528         TXCS_QUEUE7S    = 0x00008000,
529         TXCS_QUEUE6S    = 0x00004000,
530         TXCS_QUEUE5S    = 0x00002000,
531         TXCS_QUEUE4S    = 0x00001000,
532         TXCS_QUEUE3S    = 0x00000800,
533         TXCS_QUEUE2S    = 0x00000400,
534         TXCS_QUEUE1S    = 0x00000200,
535         TXCS_QUEUE0S    = 0x00000100,
536         TXCS_FIFOTH     = 0x000000C0,
537         TXCS_DMASIZE    = 0x00000030,
538         TXCS_BURST      = 0x00000004,
539         TXCS_ENABLE     = 0x00000001,
540 };
541
542 enum jme_txcs_value {
543         TXCS_FIFOTH_16QW        = 0x000000C0,
544         TXCS_FIFOTH_12QW        = 0x00000080,
545         TXCS_FIFOTH_8QW         = 0x00000040,
546         TXCS_FIFOTH_4QW         = 0x00000000,
547
548         TXCS_DMASIZE_64B        = 0x00000000,
549         TXCS_DMASIZE_128B       = 0x00000010,
550         TXCS_DMASIZE_256B       = 0x00000020,
551         TXCS_DMASIZE_512B       = 0x00000030,
552
553         TXCS_SELECT_QUEUE0      = 0x00000000,
554         TXCS_SELECT_QUEUE1      = 0x00010000,
555         TXCS_SELECT_QUEUE2      = 0x00020000,
556         TXCS_SELECT_QUEUE3      = 0x00030000,
557         TXCS_SELECT_QUEUE4      = 0x00040000,
558         TXCS_SELECT_QUEUE5      = 0x00050000,
559         TXCS_SELECT_QUEUE6      = 0x00060000,
560         TXCS_SELECT_QUEUE7      = 0x00070000,
561
562         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
563                                   TXCS_BURST,
564 };
565
566 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
567
568 /*
569  * TX MAC Control/Status Bits
570  */
571 enum jme_txmcs_bit_masks {
572         TXMCS_IFG2              = 0xC0000000,
573         TXMCS_IFG1              = 0x30000000,
574         TXMCS_TTHOLD            = 0x00000300,
575         TXMCS_FBURST            = 0x00000080,
576         TXMCS_CARRIEREXT        = 0x00000040,
577         TXMCS_DEFER             = 0x00000020,
578         TXMCS_BACKOFF           = 0x00000010,
579         TXMCS_CARRIERSENSE      = 0x00000008,
580         TXMCS_COLLISION         = 0x00000004,
581         TXMCS_CRC               = 0x00000002,
582         TXMCS_PADDING           = 0x00000001,
583 };
584
585 enum jme_txmcs_values {
586         TXMCS_IFG2_6_4          = 0x00000000,
587         TXMCS_IFG2_8_5          = 0x40000000,
588         TXMCS_IFG2_10_6         = 0x80000000,
589         TXMCS_IFG2_12_7         = 0xC0000000,
590
591         TXMCS_IFG1_8_4          = 0x00000000,
592         TXMCS_IFG1_12_6         = 0x10000000,
593         TXMCS_IFG1_16_8         = 0x20000000,
594         TXMCS_IFG1_20_10        = 0x30000000,
595
596         TXMCS_TTHOLD_1_8        = 0x00000000,
597         TXMCS_TTHOLD_1_4        = 0x00000100,
598         TXMCS_TTHOLD_1_2        = 0x00000200,
599         TXMCS_TTHOLD_FULL       = 0x00000300,
600
601         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
602                                   TXMCS_IFG1_16_8 |
603                                   TXMCS_TTHOLD_FULL |
604                                   TXMCS_DEFER |
605                                   TXMCS_CRC |
606                                   TXMCS_PADDING,
607 };
608
609 enum jme_txpfc_bits_masks {
610         TXPFC_VLAN_TAG          = 0xFFFF0000,
611         TXPFC_VLAN_EN           = 0x00008000,
612         TXPFC_PF_EN             = 0x00000001,
613 };
614
615 enum jme_txtrhd_bits_masks {
616         TXTRHD_TXPEN            = 0x80000000,
617         TXTRHD_TXP              = 0x7FFFFF00,
618         TXTRHD_TXREN            = 0x00000080,
619         TXTRHD_TXRL             = 0x0000007F,
620 };
621
622 enum jme_txtrhd_shifts {
623         TXTRHD_TXP_SHIFT        = 8,
624         TXTRHD_TXRL_SHIFT       = 0,
625 };
626
627 /*
628  * RX Control/Status Bits
629  */
630 enum jme_rxcs_bit_masks {
631         /* FIFO full threshold for transmitting Tx Pause Packet */
632         RXCS_FIFOTHTP   = 0x30000000,
633         /* FIFO threshold for processing next packet */
634         RXCS_FIFOTHNP   = 0x0C000000,
635         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
636         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
637         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
638         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
639         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
640         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
641         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
642         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
643         RXCS_QST        = 0x00000004, /* Receive queue start */
644         RXCS_SUSPEND    = 0x00000002,
645         RXCS_ENABLE     = 0x00000001,
646 };
647
648 enum jme_rxcs_values {
649         RXCS_FIFOTHTP_16T       = 0x00000000,
650         RXCS_FIFOTHTP_32T       = 0x10000000,
651         RXCS_FIFOTHTP_64T       = 0x20000000,
652         RXCS_FIFOTHTP_128T      = 0x30000000,
653
654         RXCS_FIFOTHNP_16QW      = 0x00000000,
655         RXCS_FIFOTHNP_32QW      = 0x04000000,
656         RXCS_FIFOTHNP_64QW      = 0x08000000,
657         RXCS_FIFOTHNP_128QW     = 0x0C000000,
658
659         RXCS_DMAREQSZ_16B       = 0x00000000,
660         RXCS_DMAREQSZ_32B       = 0x01000000,
661         RXCS_DMAREQSZ_64B       = 0x02000000,
662         RXCS_DMAREQSZ_128B      = 0x03000000,
663
664         RXCS_QUEUESEL_Q0        = 0x00000000,
665         RXCS_QUEUESEL_Q1        = 0x00010000,
666         RXCS_QUEUESEL_Q2        = 0x00020000,
667         RXCS_QUEUESEL_Q3        = 0x00030000,
668
669         RXCS_RETRYGAP_256ns     = 0x00000000,
670         RXCS_RETRYGAP_512ns     = 0x00001000,
671         RXCS_RETRYGAP_1024ns    = 0x00002000,
672         RXCS_RETRYGAP_2048ns    = 0x00003000,
673         RXCS_RETRYGAP_4096ns    = 0x00004000,
674         RXCS_RETRYGAP_8192ns    = 0x00005000,
675         RXCS_RETRYGAP_16384ns   = 0x00006000,
676         RXCS_RETRYGAP_32768ns   = 0x00007000,
677
678         RXCS_RETRYCNT_0         = 0x00000000,
679         RXCS_RETRYCNT_4         = 0x00000100,
680         RXCS_RETRYCNT_8         = 0x00000200,
681         RXCS_RETRYCNT_12        = 0x00000300,
682         RXCS_RETRYCNT_16        = 0x00000400,
683         RXCS_RETRYCNT_20        = 0x00000500,
684         RXCS_RETRYCNT_24        = 0x00000600,
685         RXCS_RETRYCNT_28        = 0x00000700,
686         RXCS_RETRYCNT_32        = 0x00000800,
687         RXCS_RETRYCNT_36        = 0x00000900,
688         RXCS_RETRYCNT_40        = 0x00000A00,
689         RXCS_RETRYCNT_44        = 0x00000B00,
690         RXCS_RETRYCNT_48        = 0x00000C00,
691         RXCS_RETRYCNT_52        = 0x00000D00,
692         RXCS_RETRYCNT_56        = 0x00000E00,
693         RXCS_RETRYCNT_60        = 0x00000F00,
694
695         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
696                                   RXCS_FIFOTHNP_128QW |
697                                   RXCS_DMAREQSZ_128B |
698                                   RXCS_RETRYGAP_256ns |
699                                   RXCS_RETRYCNT_32,
700 };
701
702 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
703
704 /*
705  * RX MAC Control/Status Bits
706  */
707 enum jme_rxmcs_bits {
708         RXMCS_ALLFRAME          = 0x00000800,
709         RXMCS_BRDFRAME          = 0x00000400,
710         RXMCS_MULFRAME          = 0x00000200,
711         RXMCS_UNIFRAME          = 0x00000100,
712         RXMCS_ALLMULFRAME       = 0x00000080,
713         RXMCS_MULFILTERED       = 0x00000040,
714         RXMCS_RXCOLLDEC         = 0x00000020,
715         RXMCS_FLOWCTRL          = 0x00000008,
716         RXMCS_VTAGRM            = 0x00000004,
717         RXMCS_PREPAD            = 0x00000002,
718         RXMCS_CHECKSUM          = 0x00000001,
719
720         RXMCS_DEFAULT           = RXMCS_VTAGRM |
721                                   RXMCS_PREPAD |
722                                   RXMCS_FLOWCTRL |
723                                   RXMCS_CHECKSUM,
724 };
725
726 /*
727  * Wakeup Frame setup interface registers
728  */
729 #define WAKEUP_FRAME_NR 8
730 #define WAKEUP_FRAME_MASK_DWNR  4
731
732 enum jme_wfoi_bit_masks {
733         WFOI_MASK_SEL           = 0x00000070,
734         WFOI_CRC_SEL            = 0x00000008,
735         WFOI_FRAME_SEL          = 0x00000007,
736 };
737
738 enum jme_wfoi_shifts {
739         WFOI_MASK_SHIFT         = 4,
740 };
741
742 /*
743  * SMI Related definitions
744  */
745 enum jme_smi_bit_mask {
746         SMI_DATA_MASK           = 0xFFFF0000,
747         SMI_REG_ADDR_MASK       = 0x0000F800,
748         SMI_PHY_ADDR_MASK       = 0x000007C0,
749         SMI_OP_WRITE            = 0x00000020,
750         /* Set to 1, after req done it'll be cleared to 0 */
751         SMI_OP_REQ              = 0x00000010,
752         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
753         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
754         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
755         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
756 };
757
758 enum jme_smi_bit_shift {
759         SMI_DATA_SHIFT          = 16,
760         SMI_REG_ADDR_SHIFT      = 11,
761         SMI_PHY_ADDR_SHIFT      = 6,
762 };
763
764 static inline u32 smi_reg_addr(int x)
765 {
766         return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
767 }
768
769 static inline u32 smi_phy_addr(int x)
770 {
771         return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
772 }
773
774 #define JME_PHY_TIMEOUT 100 /* 100 msec */
775 #define JME_PHY_REG_NR 32
776
777 /*
778  * Global Host Control
779  */
780 enum jme_ghc_bit_mask {
781         GHC_SWRST               = 0x40000000,
782         GHC_DPX                 = 0x00000040,
783         GHC_SPEED               = 0x00000030,
784         GHC_LINK_POLL           = 0x00000001,
785 };
786
787 enum jme_ghc_speed_val {
788         GHC_SPEED_10M           = 0x00000010,
789         GHC_SPEED_100M          = 0x00000020,
790         GHC_SPEED_1000M         = 0x00000030,
791 };
792
793 enum jme_ghc_to_clk {
794         GHC_TO_CLK_OFF          = 0x00000000,
795         GHC_TO_CLK_GPHY         = 0x00400000,
796         GHC_TO_CLK_PCIE         = 0x00800000,
797         GHC_TO_CLK_INVALID      = 0x00C00000,
798 };
799
800 enum jme_ghc_txmac_clk {
801         GHC_TXMAC_CLK_OFF       = 0x00000000,
802         GHC_TXMAC_CLK_GPHY      = 0x00100000,
803         GHC_TXMAC_CLK_PCIE      = 0x00200000,
804         GHC_TXMAC_CLK_INVALID   = 0x00300000,
805 };
806
807 /*
808  * Power management control and status register
809  */
810 enum jme_pmcs_bit_masks {
811         PMCS_WF7DET     = 0x80000000,
812         PMCS_WF6DET     = 0x40000000,
813         PMCS_WF5DET     = 0x20000000,
814         PMCS_WF4DET     = 0x10000000,
815         PMCS_WF3DET     = 0x08000000,
816         PMCS_WF2DET     = 0x04000000,
817         PMCS_WF1DET     = 0x02000000,
818         PMCS_WF0DET     = 0x01000000,
819         PMCS_LFDET      = 0x00040000,
820         PMCS_LRDET      = 0x00020000,
821         PMCS_MFDET      = 0x00010000,
822         PMCS_WF7EN      = 0x00008000,
823         PMCS_WF6EN      = 0x00004000,
824         PMCS_WF5EN      = 0x00002000,
825         PMCS_WF4EN      = 0x00001000,
826         PMCS_WF3EN      = 0x00000800,
827         PMCS_WF2EN      = 0x00000400,
828         PMCS_WF1EN      = 0x00000200,
829         PMCS_WF0EN      = 0x00000100,
830         PMCS_LFEN       = 0x00000004,
831         PMCS_LREN       = 0x00000002,
832         PMCS_MFEN       = 0x00000001,
833 };
834
835 /*
836  * Giga PHY Status Registers
837  */
838 enum jme_phy_link_bit_mask {
839         PHY_LINK_SPEED_MASK             = 0x0000C000,
840         PHY_LINK_DUPLEX                 = 0x00002000,
841         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
842         PHY_LINK_UP                     = 0x00000400,
843         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
844         PHY_LINK_MDI_STAT               = 0x00000040,
845 };
846
847 enum jme_phy_link_speed_val {
848         PHY_LINK_SPEED_10M              = 0x00000000,
849         PHY_LINK_SPEED_100M             = 0x00004000,
850         PHY_LINK_SPEED_1000M            = 0x00008000,
851 };
852
853 #define JME_SPDRSV_TIMEOUT      500     /* 500 us */
854
855 /*
856  * SMB Control and Status
857  */
858 enum jme_smbcsr_bit_mask {
859         SMBCSR_CNACK    = 0x00020000,
860         SMBCSR_RELOAD   = 0x00010000,
861         SMBCSR_EEPROMD  = 0x00000020,
862         SMBCSR_INITDONE = 0x00000010,
863         SMBCSR_BUSY     = 0x0000000F,
864 };
865
866 enum jme_smbintf_bit_mask {
867         SMBINTF_HWDATR  = 0xFF000000,
868         SMBINTF_HWDATW  = 0x00FF0000,
869         SMBINTF_HWADDR  = 0x0000FF00,
870         SMBINTF_HWRWN   = 0x00000020,
871         SMBINTF_HWCMD   = 0x00000010,
872         SMBINTF_FASTM   = 0x00000008,
873         SMBINTF_GPIOSCL = 0x00000004,
874         SMBINTF_GPIOSDA = 0x00000002,
875         SMBINTF_GPIOEN  = 0x00000001,
876 };
877
878 enum jme_smbintf_vals {
879         SMBINTF_HWRWN_READ      = 0x00000020,
880         SMBINTF_HWRWN_WRITE     = 0x00000000,
881 };
882
883 enum jme_smbintf_shifts {
884         SMBINTF_HWDATR_SHIFT    = 24,
885         SMBINTF_HWDATW_SHIFT    = 16,
886         SMBINTF_HWADDR_SHIFT    = 8,
887 };
888
889 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
890 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
891 #define JME_SMB_LEN 256
892 #define JME_EEPROM_MAGIC 0x250
893
894 /*
895  * Timer Control/Status Register
896  */
897 enum jme_tmcsr_bit_masks {
898         TMCSR_SWIT      = 0x80000000,
899         TMCSR_EN        = 0x01000000,
900         TMCSR_CNT       = 0x00FFFFFF,
901 };
902
903 /*
904  * General Purpose REG-0
905  */
906 enum jme_gpreg0_masks {
907         GPREG0_DISSH            = 0xFF000000,
908         GPREG0_PCIRLMT          = 0x00300000,
909         GPREG0_PCCNOMUTCLR      = 0x00040000,
910         GPREG0_LNKINTPOLL       = 0x00001000,
911         GPREG0_PCCTMR           = 0x00000300,
912         GPREG0_PHYADDR          = 0x0000001F,
913 };
914
915 enum jme_gpreg0_vals {
916         GPREG0_DISSH_DW7        = 0x80000000,
917         GPREG0_DISSH_DW6        = 0x40000000,
918         GPREG0_DISSH_DW5        = 0x20000000,
919         GPREG0_DISSH_DW4        = 0x10000000,
920         GPREG0_DISSH_DW3        = 0x08000000,
921         GPREG0_DISSH_DW2        = 0x04000000,
922         GPREG0_DISSH_DW1        = 0x02000000,
923         GPREG0_DISSH_DW0        = 0x01000000,
924         GPREG0_DISSH_ALL        = 0xFF000000,
925
926         GPREG0_PCIRLMT_8        = 0x00000000,
927         GPREG0_PCIRLMT_6        = 0x00100000,
928         GPREG0_PCIRLMT_5        = 0x00200000,
929         GPREG0_PCIRLMT_4        = 0x00300000,
930
931         GPREG0_PCCTMR_16ns      = 0x00000000,
932         GPREG0_PCCTMR_256ns     = 0x00000100,
933         GPREG0_PCCTMR_1us       = 0x00000200,
934         GPREG0_PCCTMR_1ms       = 0x00000300,
935
936         GPREG0_PHYADDR_1        = 0x00000001,
937
938         GPREG0_DEFAULT          = GPREG0_PCIRLMT_4 |
939                                   GPREG0_PCCTMR_1us |
940                                   GPREG0_PHYADDR_1,
941 };
942
943 /*
944  * General Purpose REG-1
945  * Note: All theses bits defined here are for
946  *       Chip mode revision 0x11 only
947  */
948 enum jme_gpreg1_masks {
949         GPREG1_INTRDELAYUNIT    = 0x00000018,
950         GPREG1_INTRDELAYENABLE  = 0x00000007,
951 };
952
953 enum jme_gpreg1_vals {
954         GPREG1_RSSPATCH         = 0x00000040,
955         GPREG1_HALFMODEPATCH    = 0x00000020,
956
957         GPREG1_INTDLYUNIT_16NS  = 0x00000000,
958         GPREG1_INTDLYUNIT_256NS = 0x00000008,
959         GPREG1_INTDLYUNIT_1US   = 0x00000010,
960         GPREG1_INTDLYUNIT_16US  = 0x00000018,
961
962         GPREG1_INTDLYEN_1U      = 0x00000001,
963         GPREG1_INTDLYEN_2U      = 0x00000002,
964         GPREG1_INTDLYEN_3U      = 0x00000003,
965         GPREG1_INTDLYEN_4U      = 0x00000004,
966         GPREG1_INTDLYEN_5U      = 0x00000005,
967         GPREG1_INTDLYEN_6U      = 0x00000006,
968         GPREG1_INTDLYEN_7U      = 0x00000007,
969
970         GPREG1_DEFAULT          = 0x00000000,
971 };
972
973 /*
974  * Interrupt Status Bits
975  */
976 enum jme_interrupt_bits {
977         INTR_SWINTR     = 0x80000000,
978         INTR_TMINTR     = 0x40000000,
979         INTR_LINKCH     = 0x20000000,
980         INTR_PAUSERCV   = 0x10000000,
981         INTR_MAGICRCV   = 0x08000000,
982         INTR_WAKERCV    = 0x04000000,
983         INTR_PCCRX0TO   = 0x02000000,
984         INTR_PCCRX1TO   = 0x01000000,
985         INTR_PCCRX2TO   = 0x00800000,
986         INTR_PCCRX3TO   = 0x00400000,
987         INTR_PCCTXTO    = 0x00200000,
988         INTR_PCCRX0     = 0x00100000,
989         INTR_PCCRX1     = 0x00080000,
990         INTR_PCCRX2     = 0x00040000,
991         INTR_PCCRX3     = 0x00020000,
992         INTR_PCCTX      = 0x00010000,
993         INTR_RX3EMP     = 0x00008000,
994         INTR_RX2EMP     = 0x00004000,
995         INTR_RX1EMP     = 0x00002000,
996         INTR_RX0EMP     = 0x00001000,
997         INTR_RX3        = 0x00000800,
998         INTR_RX2        = 0x00000400,
999         INTR_RX1        = 0x00000200,
1000         INTR_RX0        = 0x00000100,
1001         INTR_TX7        = 0x00000080,
1002         INTR_TX6        = 0x00000040,
1003         INTR_TX5        = 0x00000020,
1004         INTR_TX4        = 0x00000010,
1005         INTR_TX3        = 0x00000008,
1006         INTR_TX2        = 0x00000004,
1007         INTR_TX1        = 0x00000002,
1008         INTR_TX0        = 0x00000001,
1009 };
1010
1011 static const u32 INTR_ENABLE = INTR_SWINTR |
1012                                  INTR_TMINTR |
1013                                  INTR_LINKCH |
1014                                  INTR_PCCRX0TO |
1015                                  INTR_PCCRX0 |
1016                                  INTR_PCCTXTO |
1017                                  INTR_PCCTX |
1018                                  INTR_RX0EMP;
1019
1020 /*
1021  * PCC Control Registers
1022  */
1023 enum jme_pccrx_masks {
1024         PCCRXTO_MASK    = 0xFFFF0000,
1025         PCCRX_MASK      = 0x0000FF00,
1026 };
1027
1028 enum jme_pcctx_masks {
1029         PCCTXTO_MASK    = 0xFFFF0000,
1030         PCCTX_MASK      = 0x0000FF00,
1031         PCCTX_QS_MASK   = 0x000000FF,
1032 };
1033
1034 enum jme_pccrx_shifts {
1035         PCCRXTO_SHIFT   = 16,
1036         PCCRX_SHIFT     = 8,
1037 };
1038
1039 enum jme_pcctx_shifts {
1040         PCCTXTO_SHIFT   = 16,
1041         PCCTX_SHIFT     = 8,
1042 };
1043
1044 enum jme_pcctx_bits {
1045         PCCTXQ0_EN      = 0x00000001,
1046         PCCTXQ1_EN      = 0x00000002,
1047         PCCTXQ2_EN      = 0x00000004,
1048         PCCTXQ3_EN      = 0x00000008,
1049         PCCTXQ4_EN      = 0x00000010,
1050         PCCTXQ5_EN      = 0x00000020,
1051         PCCTXQ6_EN      = 0x00000040,
1052         PCCTXQ7_EN      = 0x00000080,
1053 };
1054
1055 /*
1056  * Chip Mode Register
1057  */
1058 enum jme_chipmode_bit_masks {
1059         CM_FPGAVER_MASK         = 0xFFFF0000,
1060         CM_CHIPREV_MASK         = 0x0000FF00,
1061         CM_CHIPMODE_MASK        = 0x0000000F,
1062 };
1063
1064 enum jme_chipmode_shifts {
1065         CM_FPGAVER_SHIFT        = 16,
1066         CM_CHIPREV_SHIFT        = 8,
1067 };
1068
1069 /*
1070  * Aggressive Power Mode Control
1071  */
1072 enum jme_apmc_bits {
1073         JME_APMC_PCIE_SD_EN     = 0x40000000,
1074         JME_APMC_PSEUDO_HP_EN   = 0x20000000,
1075         JME_APMC_EPIEN          = 0x04000000,
1076         JME_APMC_EPIEN_CTRL     = 0x03000000,
1077 };
1078
1079 enum jme_apmc_values {
1080         JME_APMC_EPIEN_CTRL_EN  = 0x02000000,
1081         JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1082 };
1083
1084 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1085
1086 #ifdef REG_DEBUG
1087 static char *MAC_REG_NAME[] = {
1088         "JME_TXCS",      "JME_TXDBA_LO",  "JME_TXDBA_HI", "JME_TXQDC",
1089         "JME_TXNDA",     "JME_TXMCS",     "JME_TXPFC",    "JME_TXTRHD",
1090         "JME_RXCS",      "JME_RXDBA_LO",  "JME_RXDBA_HI", "JME_RXQDC",
1091         "JME_RXNDA",     "JME_RXMCS",     "JME_RXUMA_LO", "JME_RXUMA_HI",
1092         "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP",    "JME_WFOI",
1093         "JME_SMI",       "JME_GHC",       "UNKNOWN",      "UNKNOWN",
1094         "JME_PMCS"};
1095
1096 static char *PE_REG_NAME[] = {
1097         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1098         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1099         "UNKNOWN",      "UNKNOWN",     "JME_PHY_CS", "UNKNOWN",
1100         "JME_PHY_LINK", "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1101         "JME_SMBCSR",   "JME_SMBINTF"};
1102
1103 static char *MISC_REG_NAME[] = {
1104         "JME_TMCSR",  "JME_GPIO",     "JME_GPREG0",  "JME_GPREG1",
1105         "JME_IEVE",   "JME_IREQ",     "JME_IENS",    "JME_IENC",
1106         "JME_PCCRX0", "JME_PCCRX1",   "JME_PCCRX2",  "JME_PCCRX3",
1107         "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1108         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1109         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1110         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1111         "JME_TIMER1", "JME_TIMER2",   "UNKNOWN",     "JME_APMC",
1112         "JME_PCCSRX0"};
1113
1114 static inline void reg_dbg(const struct jme_adapter *jme,
1115                 const char *msg, u32 val, u32 reg)
1116 {
1117         const char *regname;
1118         switch (reg & 0xF00) {
1119         case 0x000:
1120                 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1121                 break;
1122         case 0x400:
1123                 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1124                 break;
1125         case 0x800:
1126                 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1127                 break;
1128         default:
1129                 regname = PE_REG_NAME[0];
1130         }
1131         printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1132                         msg, val, regname);
1133 }
1134 #else
1135 static inline void reg_dbg(const struct jme_adapter *jme,
1136                 const char *msg, u32 val, u32 reg) {}
1137 #endif
1138
1139 /*
1140  * Read/Write MMaped I/O Registers
1141  */
1142 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1143 {
1144         return readl(jme->regs + reg);
1145 }
1146
1147 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1148 {
1149         reg_dbg(jme, "REG WRITE", val, reg);
1150         writel(val, jme->regs + reg);
1151         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1152 }
1153
1154 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1155 {
1156         /*
1157          * Read after write should cause flush
1158          */
1159         reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1160         writel(val, jme->regs + reg);
1161         readl(jme->regs + reg);
1162         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1163 }
1164
1165 /*
1166  * PHY Regs
1167  */
1168 enum jme_phy_reg17_bit_masks {
1169         PREG17_SPEED            = 0xC000,
1170         PREG17_DUPLEX           = 0x2000,
1171         PREG17_SPDRSV           = 0x0800,
1172         PREG17_LNKUP            = 0x0400,
1173         PREG17_MDI              = 0x0040,
1174 };
1175
1176 enum jme_phy_reg17_vals {
1177         PREG17_SPEED_10M        = 0x0000,
1178         PREG17_SPEED_100M       = 0x4000,
1179         PREG17_SPEED_1000M      = 0x8000,
1180 };
1181
1182 #define BMSR_ANCOMP               0x0020
1183
1184 /*
1185  * Workaround
1186  */
1187 static inline int is_buggy250(unsigned short device, unsigned int chiprev)
1188 {
1189         return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1190 }
1191
1192 /*
1193  * Function prototypes
1194  */
1195 static int jme_set_settings(struct net_device *netdev,
1196                                 struct ethtool_cmd *ecmd);
1197 static void jme_set_multi(struct net_device *netdev);
1198
1199 #endif