jme: Remove shadow register support
[linux-2.6.git] / drivers / net / jme.h
1 /*
2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3  *
4  * Copyright 2008 JMicron Technology Corporation
5  * http://www.jmicron.com/
6  *
7  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  *
22  */
23
24 #ifndef __JME_H_INCLUDED__
25 #define __JME_H_INCLUDED__
26
27 #define DRV_NAME        "jme"
28 #define DRV_VERSION     "1.0.4"
29 #define PFX             DRV_NAME ": "
30
31 #define PCI_DEVICE_ID_JMICRON_JMC250    0x0250
32 #define PCI_DEVICE_ID_JMICRON_JMC260    0x0260
33
34 /*
35  * Message related definitions
36  */
37 #define JME_DEF_MSG_ENABLE \
38         (NETIF_MSG_PROBE | \
39         NETIF_MSG_LINK | \
40         NETIF_MSG_RX_ERR | \
41         NETIF_MSG_TX_ERR | \
42         NETIF_MSG_HW)
43
44 #define jeprintk(pdev, fmt, args...) \
45         printk(KERN_ERR PFX fmt, ## args)
46
47 #ifdef TX_DEBUG
48 #define tx_dbg(priv, fmt, args...) \
49         printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ## args)
50 #else
51 #define tx_dbg(priv, fmt, args...)
52 #endif
53
54 #define jme_msg(msglvl, type, priv, fmt, args...) \
55         if (netif_msg_##type(priv)) \
56                 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
57
58 #define msg_probe(priv, fmt, args...) \
59         jme_msg(KERN_INFO, probe, priv, fmt, ## args)
60
61 #define msg_link(priv, fmt, args...) \
62         jme_msg(KERN_INFO, link, priv, fmt, ## args)
63
64 #define msg_intr(priv, fmt, args...) \
65         jme_msg(KERN_INFO, intr, priv, fmt, ## args)
66
67 #define msg_rx_err(priv, fmt, args...) \
68         jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
69
70 #define msg_rx_status(priv, fmt, args...) \
71         jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
72
73 #define msg_tx_err(priv, fmt, args...) \
74         jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
75
76 #define msg_tx_done(priv, fmt, args...) \
77         jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
78
79 #define msg_tx_queued(priv, fmt, args...) \
80         jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
81
82 #define msg_hw(priv, fmt, args...) \
83         jme_msg(KERN_ERR, hw, priv, fmt, ## args)
84
85 /*
86  * Extra PCI Configuration space interface
87  */
88 #define PCI_DCSR_MRRS           0x59
89 #define PCI_DCSR_MRRS_MASK      0x70
90
91 enum pci_dcsr_mrrs_vals {
92         MRRS_128B       = 0x00,
93         MRRS_256B       = 0x10,
94         MRRS_512B       = 0x20,
95         MRRS_1024B      = 0x30,
96         MRRS_2048B      = 0x40,
97         MRRS_4096B      = 0x50,
98 };
99
100 #define PCI_SPI                 0xB0
101
102 enum pci_spi_bits {
103         SPI_EN          = 0x10,
104         SPI_MISO        = 0x08,
105         SPI_MOSI        = 0x04,
106         SPI_SCLK        = 0x02,
107         SPI_CS          = 0x01,
108 };
109
110 struct jme_spi_op {
111         void __user *uwbuf;
112         void __user *urbuf;
113         __u8    wn;     /* Number of write actions */
114         __u8    rn;     /* Number of read actions */
115         __u8    bitn;   /* Number of bits per action */
116         __u8    spd;    /* The maxim acceptable speed of controller, in MHz.*/
117         __u8    mode;   /* CPOL, CPHA, and Duplex mode of SPI */
118
119         /* Internal use only */
120         u8      *kwbuf;
121         u8      *krbuf;
122         u8      sr;
123         u16     halfclk; /* Half of clock cycle calculated from spd, in ns */
124 };
125
126 enum jme_spi_op_bits {
127         SPI_MODE_CPHA   = 0x01,
128         SPI_MODE_CPOL   = 0x02,
129         SPI_MODE_DUP    = 0x80,
130 };
131
132 #define HALF_US 500     /* 500 ns */
133 #define JMESPIIOCTL     SIOCDEVPRIVATE
134
135 /*
136  * Dynamic(adaptive)/Static PCC values
137  */
138 enum dynamic_pcc_values {
139         PCC_OFF         = 0,
140         PCC_P1          = 1,
141         PCC_P2          = 2,
142         PCC_P3          = 3,
143
144         PCC_OFF_TO      = 0,
145         PCC_P1_TO       = 1,
146         PCC_P2_TO       = 64,
147         PCC_P3_TO       = 128,
148
149         PCC_OFF_CNT     = 0,
150         PCC_P1_CNT      = 1,
151         PCC_P2_CNT      = 16,
152         PCC_P3_CNT      = 32,
153 };
154 struct dynpcc_info {
155         unsigned long   last_bytes;
156         unsigned long   last_pkts;
157         unsigned long   intr_cnt;
158         unsigned char   cur;
159         unsigned char   attempt;
160         unsigned char   cnt;
161 };
162 #define PCC_INTERVAL_US 100000
163 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
164 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
165 #define PCC_P2_THRESHOLD 800
166 #define PCC_INTR_THRESHOLD 800
167 #define PCC_TX_TO 1000
168 #define PCC_TX_CNT 8
169
170 /*
171  * TX/RX Descriptors
172  *
173  * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
174  */
175 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
176 #define TX_DESC_SIZE            16
177 #define TX_RING_NR              8
178 #define TX_RING_ALLOC_SIZE(s)   ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
179
180 struct txdesc {
181         union {
182                 __u8    all[16];
183                 __le32  dw[4];
184                 struct {
185                         /* DW0 */
186                         __le16  vlan;
187                         __u8    rsv1;
188                         __u8    flags;
189
190                         /* DW1 */
191                         __le16  datalen;
192                         __le16  mss;
193
194                         /* DW2 */
195                         __le16  pktsize;
196                         __le16  rsv2;
197
198                         /* DW3 */
199                         __le32  bufaddr;
200                 } desc1;
201                 struct {
202                         /* DW0 */
203                         __le16  rsv1;
204                         __u8    rsv2;
205                         __u8    flags;
206
207                         /* DW1 */
208                         __le16  datalen;
209                         __le16  rsv3;
210
211                         /* DW2 */
212                         __le32  bufaddrh;
213
214                         /* DW3 */
215                         __le32  bufaddrl;
216                 } desc2;
217                 struct {
218                         /* DW0 */
219                         __u8    ehdrsz;
220                         __u8    rsv1;
221                         __u8    rsv2;
222                         __u8    flags;
223
224                         /* DW1 */
225                         __le16  trycnt;
226                         __le16  segcnt;
227
228                         /* DW2 */
229                         __le16  pktsz;
230                         __le16  rsv3;
231
232                         /* DW3 */
233                         __le32  bufaddrl;
234                 } descwb;
235         };
236 };
237
238 enum jme_txdesc_flags_bits {
239         TXFLAG_OWN      = 0x80,
240         TXFLAG_INT      = 0x40,
241         TXFLAG_64BIT    = 0x20,
242         TXFLAG_TCPCS    = 0x10,
243         TXFLAG_UDPCS    = 0x08,
244         TXFLAG_IPCS     = 0x04,
245         TXFLAG_LSEN     = 0x02,
246         TXFLAG_TAGON    = 0x01,
247 };
248
249 #define TXDESC_MSS_SHIFT        2
250 enum jme_txwbdesc_flags_bits {
251         TXWBFLAG_OWN    = 0x80,
252         TXWBFLAG_INT    = 0x40,
253         TXWBFLAG_TMOUT  = 0x20,
254         TXWBFLAG_TRYOUT = 0x10,
255         TXWBFLAG_COL    = 0x08,
256
257         TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
258                           TXWBFLAG_TRYOUT |
259                           TXWBFLAG_COL,
260 };
261
262 #define RX_DESC_SIZE            16
263 #define RX_RING_NR              4
264 #define RX_RING_ALLOC_SIZE(s)   ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
265 #define RX_BUF_DMA_ALIGN        8
266 #define RX_PREPAD_SIZE          10
267 #define ETH_CRC_LEN             2
268 #define RX_VLANHDR_LEN          2
269 #define RX_EXTRA_LEN            (RX_PREPAD_SIZE + \
270                                 ETH_HLEN + \
271                                 ETH_CRC_LEN + \
272                                 RX_VLANHDR_LEN + \
273                                 RX_BUF_DMA_ALIGN)
274
275 struct rxdesc {
276         union {
277                 __u8    all[16];
278                 __le32  dw[4];
279                 struct {
280                         /* DW0 */
281                         __le16  rsv2;
282                         __u8    rsv1;
283                         __u8    flags;
284
285                         /* DW1 */
286                         __le16  datalen;
287                         __le16  wbcpl;
288
289                         /* DW2 */
290                         __le32  bufaddrh;
291
292                         /* DW3 */
293                         __le32  bufaddrl;
294                 } desc1;
295                 struct {
296                         /* DW0 */
297                         __le16  vlan;
298                         __le16  flags;
299
300                         /* DW1 */
301                         __le16  framesize;
302                         __u8    errstat;
303                         __u8    desccnt;
304
305                         /* DW2 */
306                         __le32  rsshash;
307
308                         /* DW3 */
309                         __u8    hashfun;
310                         __u8    hashtype;
311                         __le16  resrv;
312                 } descwb;
313         };
314 };
315
316 enum jme_rxdesc_flags_bits {
317         RXFLAG_OWN      = 0x80,
318         RXFLAG_INT      = 0x40,
319         RXFLAG_64BIT    = 0x20,
320 };
321
322 enum jme_rxwbdesc_flags_bits {
323         RXWBFLAG_OWN            = 0x8000,
324         RXWBFLAG_INT            = 0x4000,
325         RXWBFLAG_MF             = 0x2000,
326         RXWBFLAG_64BIT          = 0x2000,
327         RXWBFLAG_TCPON          = 0x1000,
328         RXWBFLAG_UDPON          = 0x0800,
329         RXWBFLAG_IPCS           = 0x0400,
330         RXWBFLAG_TCPCS          = 0x0200,
331         RXWBFLAG_UDPCS          = 0x0100,
332         RXWBFLAG_TAGON          = 0x0080,
333         RXWBFLAG_IPV4           = 0x0040,
334         RXWBFLAG_IPV6           = 0x0020,
335         RXWBFLAG_PAUSE          = 0x0010,
336         RXWBFLAG_MAGIC          = 0x0008,
337         RXWBFLAG_WAKEUP         = 0x0004,
338         RXWBFLAG_DEST           = 0x0003,
339         RXWBFLAG_DEST_UNI       = 0x0001,
340         RXWBFLAG_DEST_MUL       = 0x0002,
341         RXWBFLAG_DEST_BRO       = 0x0003,
342 };
343
344 enum jme_rxwbdesc_desccnt_mask {
345         RXWBDCNT_WBCPL  = 0x80,
346         RXWBDCNT_DCNT   = 0x7F,
347 };
348
349 enum jme_rxwbdesc_errstat_bits {
350         RXWBERR_LIMIT   = 0x80,
351         RXWBERR_MIIER   = 0x40,
352         RXWBERR_NIBON   = 0x20,
353         RXWBERR_COLON   = 0x10,
354         RXWBERR_ABORT   = 0x08,
355         RXWBERR_SHORT   = 0x04,
356         RXWBERR_OVERUN  = 0x02,
357         RXWBERR_CRCERR  = 0x01,
358         RXWBERR_ALLERR  = 0xFF,
359 };
360
361 /*
362  * Buffer information corresponding to ring descriptors.
363  */
364 struct jme_buffer_info {
365         struct sk_buff *skb;
366         dma_addr_t mapping;
367         int len;
368         int nr_desc;
369         unsigned long start_xmit;
370 };
371
372 /*
373  * The structure holding buffer information and ring descriptors all together.
374  */
375 struct jme_ring {
376         void *alloc;            /* pointer to allocated memory */
377         void *desc;             /* pointer to ring memory  */
378         dma_addr_t dmaalloc;    /* phys address of ring alloc */
379         dma_addr_t dma;         /* phys address for ring dma */
380
381         /* Buffer information corresponding to each descriptor */
382         struct jme_buffer_info *bufinf;
383
384         int next_to_use;
385         atomic_t next_to_clean;
386         atomic_t nr_free;
387 };
388
389 #define NET_STAT(priv) (priv->dev->stats)
390 #define NETDEV_GET_STATS(netdev, fun_ptr)
391 #define DECLARE_NET_DEVICE_STATS
392
393 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
394 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
395         netif_napi_add(dev, napis, pollfn, q);
396 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
397 #define JME_NAPI_WEIGHT(w) int w
398 #define JME_NAPI_WEIGHT_VAL(w) w
399 #define JME_NAPI_WEIGHT_SET(w, r)
400 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
401 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
402 #define JME_NAPI_DISABLE(priv) \
403         if (!napi_disable_pending(&priv->napi)) \
404                 napi_disable(&priv->napi);
405 #define JME_RX_SCHEDULE_PREP(priv) \
406         napi_schedule_prep(&priv->napi)
407 #define JME_RX_SCHEDULE(priv) \
408         __napi_schedule(&priv->napi);
409
410 /*
411  * Jmac Adapter Private data
412  */
413 struct jme_adapter {
414         struct pci_dev          *pdev;
415         struct net_device       *dev;
416         void __iomem            *regs;
417         struct mii_if_info      mii_if;
418         struct jme_ring         rxring[RX_RING_NR];
419         struct jme_ring         txring[TX_RING_NR];
420         spinlock_t              phy_lock;
421         spinlock_t              macaddr_lock;
422         spinlock_t              rxmcs_lock;
423         struct tasklet_struct   rxempty_task;
424         struct tasklet_struct   rxclean_task;
425         struct tasklet_struct   txclean_task;
426         struct tasklet_struct   linkch_task;
427         struct tasklet_struct   pcc_task;
428         unsigned long           flags;
429         u32                     reg_txcs;
430         u32                     reg_txpfc;
431         u32                     reg_rxcs;
432         u32                     reg_rxmcs;
433         u32                     reg_ghc;
434         u32                     reg_pmcs;
435         u32                     phylink;
436         u32                     tx_ring_size;
437         u32                     tx_ring_mask;
438         u32                     tx_wake_threshold;
439         u32                     rx_ring_size;
440         u32                     rx_ring_mask;
441         u8                      mrrs;
442         unsigned int            fpgaver;
443         unsigned int            chiprev;
444         u8                      rev;
445         u32                     msg_enable;
446         struct ethtool_cmd      old_ecmd;
447         unsigned int            old_mtu;
448         struct vlan_group       *vlgrp;
449         struct dynpcc_info      dpi;
450         atomic_t                intr_sem;
451         atomic_t                link_changing;
452         atomic_t                tx_cleaning;
453         atomic_t                rx_cleaning;
454         atomic_t                rx_empty;
455         int                     (*jme_rx)(struct sk_buff *skb);
456         int                     (*jme_vlan_rx)(struct sk_buff *skb,
457                                           struct vlan_group *grp,
458                                           unsigned short vlan_tag);
459         DECLARE_NAPI_STRUCT
460         DECLARE_NET_DEVICE_STATS
461 };
462
463 enum jme_flags_bits {
464         JME_FLAG_MSI            = 1,
465         JME_FLAG_SSET           = 2,
466         JME_FLAG_TXCSUM         = 3,
467         JME_FLAG_TSO            = 4,
468         JME_FLAG_POLL           = 5,
469         JME_FLAG_SHUTDOWN       = 6,
470 };
471
472 #define TX_TIMEOUT              (5 * HZ)
473 #define JME_REG_LEN             0x500
474 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
475
476 static inline struct jme_adapter*
477 jme_napi_priv(struct napi_struct *napi)
478 {
479         struct jme_adapter *jme;
480         jme = container_of(napi, struct jme_adapter, napi);
481         return jme;
482 }
483
484 /*
485  * MMaped I/O Resters
486  */
487 enum jme_iomap_offsets {
488         JME_MAC         = 0x0000,
489         JME_PHY         = 0x0400,
490         JME_MISC        = 0x0800,
491         JME_RSS         = 0x0C00,
492 };
493
494 enum jme_iomap_lens {
495         JME_MAC_LEN     = 0x80,
496         JME_PHY_LEN     = 0x58,
497         JME_MISC_LEN    = 0x98,
498         JME_RSS_LEN     = 0xFF,
499 };
500
501 enum jme_iomap_regs {
502         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
503         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
504         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
505         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
506         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
507         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
508         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
509         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
510
511         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
512         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
513         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
514         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
515         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
516         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
517         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
518         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
519         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
520         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
521         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
522         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
523
524         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
525         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
526         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
527
528
529         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
530         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
531         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
532         JME_SMBINTF     = JME_PHY | 0x44, /* SMB Interface */
533
534
535         JME_TMCSR       = JME_MISC | 0x00, /* Timer Control/Status Register */
536         JME_GPREG0      = JME_MISC | 0x08, /* General purpose REG-0 */
537         JME_GPREG1      = JME_MISC | 0x0C, /* General purpose REG-1 */
538         JME_IEVE        = JME_MISC | 0x20, /* Interrupt Event Status */
539         JME_IREQ        = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
540         JME_IENS        = JME_MISC | 0x28, /* Intr Enable - Setting Port */
541         JME_IENC        = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
542         JME_PCCRX0      = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
543         JME_PCCTX       = JME_MISC | 0x40, /* PCC Control for TX Queues */
544         JME_CHIPMODE    = JME_MISC | 0x44, /* Identify FPGA Version */
545         JME_SHBA_HI     = JME_MISC | 0x48, /* Shadow Register Base HI */
546         JME_SHBA_LO     = JME_MISC | 0x4C, /* Shadow Register Base LO */
547         JME_TIMER1      = JME_MISC | 0x70, /* Timer1 */
548         JME_TIMER2      = JME_MISC | 0x74, /* Timer2 */
549         JME_APMC        = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
550         JME_PCCSRX0     = JME_MISC | 0x80, /* PCC Status of RX0 */
551 };
552
553 /*
554  * TX Control/Status Bits
555  */
556 enum jme_txcs_bits {
557         TXCS_QUEUE7S    = 0x00008000,
558         TXCS_QUEUE6S    = 0x00004000,
559         TXCS_QUEUE5S    = 0x00002000,
560         TXCS_QUEUE4S    = 0x00001000,
561         TXCS_QUEUE3S    = 0x00000800,
562         TXCS_QUEUE2S    = 0x00000400,
563         TXCS_QUEUE1S    = 0x00000200,
564         TXCS_QUEUE0S    = 0x00000100,
565         TXCS_FIFOTH     = 0x000000C0,
566         TXCS_DMASIZE    = 0x00000030,
567         TXCS_BURST      = 0x00000004,
568         TXCS_ENABLE     = 0x00000001,
569 };
570
571 enum jme_txcs_value {
572         TXCS_FIFOTH_16QW        = 0x000000C0,
573         TXCS_FIFOTH_12QW        = 0x00000080,
574         TXCS_FIFOTH_8QW         = 0x00000040,
575         TXCS_FIFOTH_4QW         = 0x00000000,
576
577         TXCS_DMASIZE_64B        = 0x00000000,
578         TXCS_DMASIZE_128B       = 0x00000010,
579         TXCS_DMASIZE_256B       = 0x00000020,
580         TXCS_DMASIZE_512B       = 0x00000030,
581
582         TXCS_SELECT_QUEUE0      = 0x00000000,
583         TXCS_SELECT_QUEUE1      = 0x00010000,
584         TXCS_SELECT_QUEUE2      = 0x00020000,
585         TXCS_SELECT_QUEUE3      = 0x00030000,
586         TXCS_SELECT_QUEUE4      = 0x00040000,
587         TXCS_SELECT_QUEUE5      = 0x00050000,
588         TXCS_SELECT_QUEUE6      = 0x00060000,
589         TXCS_SELECT_QUEUE7      = 0x00070000,
590
591         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
592                                   TXCS_BURST,
593 };
594
595 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
596
597 /*
598  * TX MAC Control/Status Bits
599  */
600 enum jme_txmcs_bit_masks {
601         TXMCS_IFG2              = 0xC0000000,
602         TXMCS_IFG1              = 0x30000000,
603         TXMCS_TTHOLD            = 0x00000300,
604         TXMCS_FBURST            = 0x00000080,
605         TXMCS_CARRIEREXT        = 0x00000040,
606         TXMCS_DEFER             = 0x00000020,
607         TXMCS_BACKOFF           = 0x00000010,
608         TXMCS_CARRIERSENSE      = 0x00000008,
609         TXMCS_COLLISION         = 0x00000004,
610         TXMCS_CRC               = 0x00000002,
611         TXMCS_PADDING           = 0x00000001,
612 };
613
614 enum jme_txmcs_values {
615         TXMCS_IFG2_6_4          = 0x00000000,
616         TXMCS_IFG2_8_5          = 0x40000000,
617         TXMCS_IFG2_10_6         = 0x80000000,
618         TXMCS_IFG2_12_7         = 0xC0000000,
619
620         TXMCS_IFG1_8_4          = 0x00000000,
621         TXMCS_IFG1_12_6         = 0x10000000,
622         TXMCS_IFG1_16_8         = 0x20000000,
623         TXMCS_IFG1_20_10        = 0x30000000,
624
625         TXMCS_TTHOLD_1_8        = 0x00000000,
626         TXMCS_TTHOLD_1_4        = 0x00000100,
627         TXMCS_TTHOLD_1_2        = 0x00000200,
628         TXMCS_TTHOLD_FULL       = 0x00000300,
629
630         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
631                                   TXMCS_IFG1_16_8 |
632                                   TXMCS_TTHOLD_FULL |
633                                   TXMCS_DEFER |
634                                   TXMCS_CRC |
635                                   TXMCS_PADDING,
636 };
637
638 enum jme_txpfc_bits_masks {
639         TXPFC_VLAN_TAG          = 0xFFFF0000,
640         TXPFC_VLAN_EN           = 0x00008000,
641         TXPFC_PF_EN             = 0x00000001,
642 };
643
644 enum jme_txtrhd_bits_masks {
645         TXTRHD_TXPEN            = 0x80000000,
646         TXTRHD_TXP              = 0x7FFFFF00,
647         TXTRHD_TXREN            = 0x00000080,
648         TXTRHD_TXRL             = 0x0000007F,
649 };
650
651 enum jme_txtrhd_shifts {
652         TXTRHD_TXP_SHIFT        = 8,
653         TXTRHD_TXRL_SHIFT       = 0,
654 };
655
656 /*
657  * RX Control/Status Bits
658  */
659 enum jme_rxcs_bit_masks {
660         /* FIFO full threshold for transmitting Tx Pause Packet */
661         RXCS_FIFOTHTP   = 0x30000000,
662         /* FIFO threshold for processing next packet */
663         RXCS_FIFOTHNP   = 0x0C000000,
664         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
665         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
666         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
667         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
668         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
669         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
670         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
671         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
672         RXCS_QST        = 0x00000004, /* Receive queue start */
673         RXCS_SUSPEND    = 0x00000002,
674         RXCS_ENABLE     = 0x00000001,
675 };
676
677 enum jme_rxcs_values {
678         RXCS_FIFOTHTP_16T       = 0x00000000,
679         RXCS_FIFOTHTP_32T       = 0x10000000,
680         RXCS_FIFOTHTP_64T       = 0x20000000,
681         RXCS_FIFOTHTP_128T      = 0x30000000,
682
683         RXCS_FIFOTHNP_16QW      = 0x00000000,
684         RXCS_FIFOTHNP_32QW      = 0x04000000,
685         RXCS_FIFOTHNP_64QW      = 0x08000000,
686         RXCS_FIFOTHNP_128QW     = 0x0C000000,
687
688         RXCS_DMAREQSZ_16B       = 0x00000000,
689         RXCS_DMAREQSZ_32B       = 0x01000000,
690         RXCS_DMAREQSZ_64B       = 0x02000000,
691         RXCS_DMAREQSZ_128B      = 0x03000000,
692
693         RXCS_QUEUESEL_Q0        = 0x00000000,
694         RXCS_QUEUESEL_Q1        = 0x00010000,
695         RXCS_QUEUESEL_Q2        = 0x00020000,
696         RXCS_QUEUESEL_Q3        = 0x00030000,
697
698         RXCS_RETRYGAP_256ns     = 0x00000000,
699         RXCS_RETRYGAP_512ns     = 0x00001000,
700         RXCS_RETRYGAP_1024ns    = 0x00002000,
701         RXCS_RETRYGAP_2048ns    = 0x00003000,
702         RXCS_RETRYGAP_4096ns    = 0x00004000,
703         RXCS_RETRYGAP_8192ns    = 0x00005000,
704         RXCS_RETRYGAP_16384ns   = 0x00006000,
705         RXCS_RETRYGAP_32768ns   = 0x00007000,
706
707         RXCS_RETRYCNT_0         = 0x00000000,
708         RXCS_RETRYCNT_4         = 0x00000100,
709         RXCS_RETRYCNT_8         = 0x00000200,
710         RXCS_RETRYCNT_12        = 0x00000300,
711         RXCS_RETRYCNT_16        = 0x00000400,
712         RXCS_RETRYCNT_20        = 0x00000500,
713         RXCS_RETRYCNT_24        = 0x00000600,
714         RXCS_RETRYCNT_28        = 0x00000700,
715         RXCS_RETRYCNT_32        = 0x00000800,
716         RXCS_RETRYCNT_36        = 0x00000900,
717         RXCS_RETRYCNT_40        = 0x00000A00,
718         RXCS_RETRYCNT_44        = 0x00000B00,
719         RXCS_RETRYCNT_48        = 0x00000C00,
720         RXCS_RETRYCNT_52        = 0x00000D00,
721         RXCS_RETRYCNT_56        = 0x00000E00,
722         RXCS_RETRYCNT_60        = 0x00000F00,
723
724         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
725                                   RXCS_FIFOTHNP_128QW |
726                                   RXCS_DMAREQSZ_128B |
727                                   RXCS_RETRYGAP_256ns |
728                                   RXCS_RETRYCNT_32,
729 };
730
731 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
732
733 /*
734  * RX MAC Control/Status Bits
735  */
736 enum jme_rxmcs_bits {
737         RXMCS_ALLFRAME          = 0x00000800,
738         RXMCS_BRDFRAME          = 0x00000400,
739         RXMCS_MULFRAME          = 0x00000200,
740         RXMCS_UNIFRAME          = 0x00000100,
741         RXMCS_ALLMULFRAME       = 0x00000080,
742         RXMCS_MULFILTERED       = 0x00000040,
743         RXMCS_RXCOLLDEC         = 0x00000020,
744         RXMCS_FLOWCTRL          = 0x00000008,
745         RXMCS_VTAGRM            = 0x00000004,
746         RXMCS_PREPAD            = 0x00000002,
747         RXMCS_CHECKSUM          = 0x00000001,
748
749         RXMCS_DEFAULT           = RXMCS_VTAGRM |
750                                   RXMCS_PREPAD |
751                                   RXMCS_FLOWCTRL |
752                                   RXMCS_CHECKSUM,
753 };
754
755 /*
756  * Wakeup Frame setup interface registers
757  */
758 #define WAKEUP_FRAME_NR 8
759 #define WAKEUP_FRAME_MASK_DWNR  4
760
761 enum jme_wfoi_bit_masks {
762         WFOI_MASK_SEL           = 0x00000070,
763         WFOI_CRC_SEL            = 0x00000008,
764         WFOI_FRAME_SEL          = 0x00000007,
765 };
766
767 enum jme_wfoi_shifts {
768         WFOI_MASK_SHIFT         = 4,
769 };
770
771 /*
772  * SMI Related definitions
773  */
774 enum jme_smi_bit_mask {
775         SMI_DATA_MASK           = 0xFFFF0000,
776         SMI_REG_ADDR_MASK       = 0x0000F800,
777         SMI_PHY_ADDR_MASK       = 0x000007C0,
778         SMI_OP_WRITE            = 0x00000020,
779         /* Set to 1, after req done it'll be cleared to 0 */
780         SMI_OP_REQ              = 0x00000010,
781         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
782         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
783         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
784         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
785 };
786
787 enum jme_smi_bit_shift {
788         SMI_DATA_SHIFT          = 16,
789         SMI_REG_ADDR_SHIFT      = 11,
790         SMI_PHY_ADDR_SHIFT      = 6,
791 };
792
793 static inline u32 smi_reg_addr(int x)
794 {
795         return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
796 }
797
798 static inline u32 smi_phy_addr(int x)
799 {
800         return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
801 }
802
803 #define JME_PHY_TIMEOUT 100 /* 100 msec */
804 #define JME_PHY_REG_NR 32
805
806 /*
807  * Global Host Control
808  */
809 enum jme_ghc_bit_mask {
810         GHC_SWRST               = 0x40000000,
811         GHC_DPX                 = 0x00000040,
812         GHC_SPEED               = 0x00000030,
813         GHC_LINK_POLL           = 0x00000001,
814 };
815
816 enum jme_ghc_speed_val {
817         GHC_SPEED_10M           = 0x00000010,
818         GHC_SPEED_100M          = 0x00000020,
819         GHC_SPEED_1000M         = 0x00000030,
820 };
821
822 enum jme_ghc_to_clk {
823         GHC_TO_CLK_OFF          = 0x00000000,
824         GHC_TO_CLK_GPHY         = 0x00400000,
825         GHC_TO_CLK_PCIE         = 0x00800000,
826         GHC_TO_CLK_INVALID      = 0x00C00000,
827 };
828
829 enum jme_ghc_txmac_clk {
830         GHC_TXMAC_CLK_OFF       = 0x00000000,
831         GHC_TXMAC_CLK_GPHY      = 0x00100000,
832         GHC_TXMAC_CLK_PCIE      = 0x00200000,
833         GHC_TXMAC_CLK_INVALID   = 0x00300000,
834 };
835
836 /*
837  * Power management control and status register
838  */
839 enum jme_pmcs_bit_masks {
840         PMCS_WF7DET     = 0x80000000,
841         PMCS_WF6DET     = 0x40000000,
842         PMCS_WF5DET     = 0x20000000,
843         PMCS_WF4DET     = 0x10000000,
844         PMCS_WF3DET     = 0x08000000,
845         PMCS_WF2DET     = 0x04000000,
846         PMCS_WF1DET     = 0x02000000,
847         PMCS_WF0DET     = 0x01000000,
848         PMCS_LFDET      = 0x00040000,
849         PMCS_LRDET      = 0x00020000,
850         PMCS_MFDET      = 0x00010000,
851         PMCS_WF7EN      = 0x00008000,
852         PMCS_WF6EN      = 0x00004000,
853         PMCS_WF5EN      = 0x00002000,
854         PMCS_WF4EN      = 0x00001000,
855         PMCS_WF3EN      = 0x00000800,
856         PMCS_WF2EN      = 0x00000400,
857         PMCS_WF1EN      = 0x00000200,
858         PMCS_WF0EN      = 0x00000100,
859         PMCS_LFEN       = 0x00000004,
860         PMCS_LREN       = 0x00000002,
861         PMCS_MFEN       = 0x00000001,
862 };
863
864 /*
865  * Giga PHY Status Registers
866  */
867 enum jme_phy_link_bit_mask {
868         PHY_LINK_SPEED_MASK             = 0x0000C000,
869         PHY_LINK_DUPLEX                 = 0x00002000,
870         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
871         PHY_LINK_UP                     = 0x00000400,
872         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
873         PHY_LINK_MDI_STAT               = 0x00000040,
874 };
875
876 enum jme_phy_link_speed_val {
877         PHY_LINK_SPEED_10M              = 0x00000000,
878         PHY_LINK_SPEED_100M             = 0x00004000,
879         PHY_LINK_SPEED_1000M            = 0x00008000,
880 };
881
882 #define JME_SPDRSV_TIMEOUT      500     /* 500 us */
883
884 /*
885  * SMB Control and Status
886  */
887 enum jme_smbcsr_bit_mask {
888         SMBCSR_CNACK    = 0x00020000,
889         SMBCSR_RELOAD   = 0x00010000,
890         SMBCSR_EEPROMD  = 0x00000020,
891         SMBCSR_INITDONE = 0x00000010,
892         SMBCSR_BUSY     = 0x0000000F,
893 };
894
895 enum jme_smbintf_bit_mask {
896         SMBINTF_HWDATR  = 0xFF000000,
897         SMBINTF_HWDATW  = 0x00FF0000,
898         SMBINTF_HWADDR  = 0x0000FF00,
899         SMBINTF_HWRWN   = 0x00000020,
900         SMBINTF_HWCMD   = 0x00000010,
901         SMBINTF_FASTM   = 0x00000008,
902         SMBINTF_GPIOSCL = 0x00000004,
903         SMBINTF_GPIOSDA = 0x00000002,
904         SMBINTF_GPIOEN  = 0x00000001,
905 };
906
907 enum jme_smbintf_vals {
908         SMBINTF_HWRWN_READ      = 0x00000020,
909         SMBINTF_HWRWN_WRITE     = 0x00000000,
910 };
911
912 enum jme_smbintf_shifts {
913         SMBINTF_HWDATR_SHIFT    = 24,
914         SMBINTF_HWDATW_SHIFT    = 16,
915         SMBINTF_HWADDR_SHIFT    = 8,
916 };
917
918 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
919 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
920 #define JME_SMB_LEN 256
921 #define JME_EEPROM_MAGIC 0x250
922
923 /*
924  * Timer Control/Status Register
925  */
926 enum jme_tmcsr_bit_masks {
927         TMCSR_SWIT      = 0x80000000,
928         TMCSR_EN        = 0x01000000,
929         TMCSR_CNT       = 0x00FFFFFF,
930 };
931
932 /*
933  * General Purpose REG-0
934  */
935 enum jme_gpreg0_masks {
936         GPREG0_DISSH            = 0xFF000000,
937         GPREG0_PCIRLMT          = 0x00300000,
938         GPREG0_PCCNOMUTCLR      = 0x00040000,
939         GPREG0_LNKINTPOLL       = 0x00001000,
940         GPREG0_PCCTMR           = 0x00000300,
941         GPREG0_PHYADDR          = 0x0000001F,
942 };
943
944 enum jme_gpreg0_vals {
945         GPREG0_DISSH_DW7        = 0x80000000,
946         GPREG0_DISSH_DW6        = 0x40000000,
947         GPREG0_DISSH_DW5        = 0x20000000,
948         GPREG0_DISSH_DW4        = 0x10000000,
949         GPREG0_DISSH_DW3        = 0x08000000,
950         GPREG0_DISSH_DW2        = 0x04000000,
951         GPREG0_DISSH_DW1        = 0x02000000,
952         GPREG0_DISSH_DW0        = 0x01000000,
953         GPREG0_DISSH_ALL        = 0xFF000000,
954
955         GPREG0_PCIRLMT_8        = 0x00000000,
956         GPREG0_PCIRLMT_6        = 0x00100000,
957         GPREG0_PCIRLMT_5        = 0x00200000,
958         GPREG0_PCIRLMT_4        = 0x00300000,
959
960         GPREG0_PCCTMR_16ns      = 0x00000000,
961         GPREG0_PCCTMR_256ns     = 0x00000100,
962         GPREG0_PCCTMR_1us       = 0x00000200,
963         GPREG0_PCCTMR_1ms       = 0x00000300,
964
965         GPREG0_PHYADDR_1        = 0x00000001,
966
967         GPREG0_DEFAULT          = GPREG0_PCIRLMT_4 |
968                                   GPREG0_PCCTMR_1us |
969                                   GPREG0_PHYADDR_1,
970 };
971
972 /*
973  * General Purpose REG-1
974  * Note: All theses bits defined here are for
975  *       Chip mode revision 0x11 only
976  */
977 enum jme_gpreg1_masks {
978         GPREG1_INTRDELAYUNIT    = 0x00000018,
979         GPREG1_INTRDELAYENABLE  = 0x00000007,
980 };
981
982 enum jme_gpreg1_vals {
983         GPREG1_RSSPATCH         = 0x00000040,
984         GPREG1_HALFMODEPATCH    = 0x00000020,
985
986         GPREG1_INTDLYUNIT_16NS  = 0x00000000,
987         GPREG1_INTDLYUNIT_256NS = 0x00000008,
988         GPREG1_INTDLYUNIT_1US   = 0x00000010,
989         GPREG1_INTDLYUNIT_16US  = 0x00000018,
990
991         GPREG1_INTDLYEN_1U      = 0x00000001,
992         GPREG1_INTDLYEN_2U      = 0x00000002,
993         GPREG1_INTDLYEN_3U      = 0x00000003,
994         GPREG1_INTDLYEN_4U      = 0x00000004,
995         GPREG1_INTDLYEN_5U      = 0x00000005,
996         GPREG1_INTDLYEN_6U      = 0x00000006,
997         GPREG1_INTDLYEN_7U      = 0x00000007,
998
999         GPREG1_DEFAULT          = 0x00000000,
1000 };
1001
1002 /*
1003  * Interrupt Status Bits
1004  */
1005 enum jme_interrupt_bits {
1006         INTR_SWINTR     = 0x80000000,
1007         INTR_TMINTR     = 0x40000000,
1008         INTR_LINKCH     = 0x20000000,
1009         INTR_PAUSERCV   = 0x10000000,
1010         INTR_MAGICRCV   = 0x08000000,
1011         INTR_WAKERCV    = 0x04000000,
1012         INTR_PCCRX0TO   = 0x02000000,
1013         INTR_PCCRX1TO   = 0x01000000,
1014         INTR_PCCRX2TO   = 0x00800000,
1015         INTR_PCCRX3TO   = 0x00400000,
1016         INTR_PCCTXTO    = 0x00200000,
1017         INTR_PCCRX0     = 0x00100000,
1018         INTR_PCCRX1     = 0x00080000,
1019         INTR_PCCRX2     = 0x00040000,
1020         INTR_PCCRX3     = 0x00020000,
1021         INTR_PCCTX      = 0x00010000,
1022         INTR_RX3EMP     = 0x00008000,
1023         INTR_RX2EMP     = 0x00004000,
1024         INTR_RX1EMP     = 0x00002000,
1025         INTR_RX0EMP     = 0x00001000,
1026         INTR_RX3        = 0x00000800,
1027         INTR_RX2        = 0x00000400,
1028         INTR_RX1        = 0x00000200,
1029         INTR_RX0        = 0x00000100,
1030         INTR_TX7        = 0x00000080,
1031         INTR_TX6        = 0x00000040,
1032         INTR_TX5        = 0x00000020,
1033         INTR_TX4        = 0x00000010,
1034         INTR_TX3        = 0x00000008,
1035         INTR_TX2        = 0x00000004,
1036         INTR_TX1        = 0x00000002,
1037         INTR_TX0        = 0x00000001,
1038 };
1039
1040 static const u32 INTR_ENABLE = INTR_SWINTR |
1041                                  INTR_TMINTR |
1042                                  INTR_LINKCH |
1043                                  INTR_PCCRX0TO |
1044                                  INTR_PCCRX0 |
1045                                  INTR_PCCTXTO |
1046                                  INTR_PCCTX |
1047                                  INTR_RX0EMP;
1048
1049 /*
1050  * PCC Control Registers
1051  */
1052 enum jme_pccrx_masks {
1053         PCCRXTO_MASK    = 0xFFFF0000,
1054         PCCRX_MASK      = 0x0000FF00,
1055 };
1056
1057 enum jme_pcctx_masks {
1058         PCCTXTO_MASK    = 0xFFFF0000,
1059         PCCTX_MASK      = 0x0000FF00,
1060         PCCTX_QS_MASK   = 0x000000FF,
1061 };
1062
1063 enum jme_pccrx_shifts {
1064         PCCRXTO_SHIFT   = 16,
1065         PCCRX_SHIFT     = 8,
1066 };
1067
1068 enum jme_pcctx_shifts {
1069         PCCTXTO_SHIFT   = 16,
1070         PCCTX_SHIFT     = 8,
1071 };
1072
1073 enum jme_pcctx_bits {
1074         PCCTXQ0_EN      = 0x00000001,
1075         PCCTXQ1_EN      = 0x00000002,
1076         PCCTXQ2_EN      = 0x00000004,
1077         PCCTXQ3_EN      = 0x00000008,
1078         PCCTXQ4_EN      = 0x00000010,
1079         PCCTXQ5_EN      = 0x00000020,
1080         PCCTXQ6_EN      = 0x00000040,
1081         PCCTXQ7_EN      = 0x00000080,
1082 };
1083
1084 /*
1085  * Chip Mode Register
1086  */
1087 enum jme_chipmode_bit_masks {
1088         CM_FPGAVER_MASK         = 0xFFFF0000,
1089         CM_CHIPREV_MASK         = 0x0000FF00,
1090         CM_CHIPMODE_MASK        = 0x0000000F,
1091 };
1092
1093 enum jme_chipmode_shifts {
1094         CM_FPGAVER_SHIFT        = 16,
1095         CM_CHIPREV_SHIFT        = 8,
1096 };
1097
1098 /*
1099  * Aggressive Power Mode Control
1100  */
1101 enum jme_apmc_bits {
1102         JME_APMC_PCIE_SD_EN     = 0x40000000,
1103         JME_APMC_PSEUDO_HP_EN   = 0x20000000,
1104         JME_APMC_EPIEN          = 0x04000000,
1105         JME_APMC_EPIEN_CTRL     = 0x03000000,
1106 };
1107
1108 enum jme_apmc_values {
1109         JME_APMC_EPIEN_CTRL_EN  = 0x02000000,
1110         JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1111 };
1112
1113 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1114
1115 #ifdef REG_DEBUG
1116 static char *MAC_REG_NAME[] = {
1117         "JME_TXCS",      "JME_TXDBA_LO",  "JME_TXDBA_HI", "JME_TXQDC",
1118         "JME_TXNDA",     "JME_TXMCS",     "JME_TXPFC",    "JME_TXTRHD",
1119         "JME_RXCS",      "JME_RXDBA_LO",  "JME_RXDBA_HI", "JME_RXQDC",
1120         "JME_RXNDA",     "JME_RXMCS",     "JME_RXUMA_LO", "JME_RXUMA_HI",
1121         "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP",    "JME_WFOI",
1122         "JME_SMI",       "JME_GHC",       "UNKNOWN",      "UNKNOWN",
1123         "JME_PMCS"};
1124
1125 static char *PE_REG_NAME[] = {
1126         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1127         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1128         "UNKNOWN",      "UNKNOWN",     "JME_PHY_CS", "UNKNOWN",
1129         "JME_PHY_LINK", "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1130         "JME_SMBCSR",   "JME_SMBINTF"};
1131
1132 static char *MISC_REG_NAME[] = {
1133         "JME_TMCSR",  "JME_GPIO",     "JME_GPREG0",  "JME_GPREG1",
1134         "JME_IEVE",   "JME_IREQ",     "JME_IENS",    "JME_IENC",
1135         "JME_PCCRX0", "JME_PCCRX1",   "JME_PCCRX2",  "JME_PCCRX3",
1136         "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1137         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1138         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1139         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1140         "JME_TIMER1", "JME_TIMER2",   "UNKNOWN",     "JME_APMC",
1141         "JME_PCCSRX0"};
1142
1143 static inline void reg_dbg(const struct jme_adapter *jme,
1144                 const char *msg, u32 val, u32 reg)
1145 {
1146         const char *regname;
1147         switch (reg & 0xF00) {
1148         case 0x000:
1149                 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1150                 break;
1151         case 0x400:
1152                 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1153                 break;
1154         case 0x800:
1155                 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1156                 break;
1157         default:
1158                 regname = PE_REG_NAME[0];
1159         }
1160         printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1161                         msg, val, regname);
1162 }
1163 #else
1164 static inline void reg_dbg(const struct jme_adapter *jme,
1165                 const char *msg, u32 val, u32 reg) {}
1166 #endif
1167
1168 /*
1169  * Read/Write MMaped I/O Registers
1170  */
1171 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1172 {
1173         return readl(jme->regs + reg);
1174 }
1175
1176 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1177 {
1178         reg_dbg(jme, "REG WRITE", val, reg);
1179         writel(val, jme->regs + reg);
1180         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1181 }
1182
1183 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1184 {
1185         /*
1186          * Read after write should cause flush
1187          */
1188         reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1189         writel(val, jme->regs + reg);
1190         readl(jme->regs + reg);
1191         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1192 }
1193
1194 /*
1195  * PHY Regs
1196  */
1197 enum jme_phy_reg17_bit_masks {
1198         PREG17_SPEED            = 0xC000,
1199         PREG17_DUPLEX           = 0x2000,
1200         PREG17_SPDRSV           = 0x0800,
1201         PREG17_LNKUP            = 0x0400,
1202         PREG17_MDI              = 0x0040,
1203 };
1204
1205 enum jme_phy_reg17_vals {
1206         PREG17_SPEED_10M        = 0x0000,
1207         PREG17_SPEED_100M       = 0x4000,
1208         PREG17_SPEED_1000M      = 0x8000,
1209 };
1210
1211 #define BMSR_ANCOMP               0x0020
1212
1213 /*
1214  * Workaround
1215  */
1216 static inline int is_buggy250(unsigned short device, unsigned int chiprev)
1217 {
1218         return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1219 }
1220
1221 /*
1222  * Function prototypes
1223  */
1224 static int jme_set_settings(struct net_device *netdev,
1225                                 struct ethtool_cmd *ecmd);
1226 static void jme_set_multi(struct net_device *netdev);
1227
1228 #endif