9d3cedd394a0e58977dfb12a8441e5f4b4646728
[linux-2.6.git] / drivers / net / jme.h
1 /*
2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3  *
4  * Copyright 2008 JMicron Technology Corporation
5  * http://www.jmicron.com/
6  *
7  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  *
22  */
23
24 #ifndef __JME_H_INCLUDED__
25 #define __JME_H_INCLUDED__
26
27 #define DRV_NAME        "jme"
28 #define DRV_VERSION     "1.0.4"
29 #define PFX             DRV_NAME ": "
30
31 #define PCI_DEVICE_ID_JMICRON_JMC250    0x0250
32 #define PCI_DEVICE_ID_JMICRON_JMC260    0x0260
33
34 /*
35  * Message related definitions
36  */
37 #define JME_DEF_MSG_ENABLE \
38         (NETIF_MSG_PROBE | \
39         NETIF_MSG_LINK | \
40         NETIF_MSG_RX_ERR | \
41         NETIF_MSG_TX_ERR | \
42         NETIF_MSG_HW)
43
44 #define jeprintk(pdev, fmt, args...) \
45         printk(KERN_ERR PFX fmt, ## args)
46
47 #ifdef TX_DEBUG
48 #define tx_dbg(priv, fmt, args...) \
49         printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ## args)
50 #else
51 #define tx_dbg(priv, fmt, args...)
52 #endif
53
54 #define jme_msg(msglvl, type, priv, fmt, args...) \
55         if (netif_msg_##type(priv)) \
56                 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
57
58 #define msg_probe(priv, fmt, args...) \
59         jme_msg(KERN_INFO, probe, priv, fmt, ## args)
60
61 #define msg_link(priv, fmt, args...) \
62         jme_msg(KERN_INFO, link, priv, fmt, ## args)
63
64 #define msg_intr(priv, fmt, args...) \
65         jme_msg(KERN_INFO, intr, priv, fmt, ## args)
66
67 #define msg_rx_err(priv, fmt, args...) \
68         jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
69
70 #define msg_rx_status(priv, fmt, args...) \
71         jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
72
73 #define msg_tx_err(priv, fmt, args...) \
74         jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
75
76 #define msg_tx_done(priv, fmt, args...) \
77         jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
78
79 #define msg_tx_queued(priv, fmt, args...) \
80         jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
81
82 #define msg_hw(priv, fmt, args...) \
83         jme_msg(KERN_ERR, hw, priv, fmt, ## args)
84
85 /*
86  * Extra PCI Configuration space interface
87  */
88 #define PCI_DCSR_MRRS           0x59
89 #define PCI_DCSR_MRRS_MASK      0x70
90
91 enum pci_dcsr_mrrs_vals {
92         MRRS_128B       = 0x00,
93         MRRS_256B       = 0x10,
94         MRRS_512B       = 0x20,
95         MRRS_1024B      = 0x30,
96         MRRS_2048B      = 0x40,
97         MRRS_4096B      = 0x50,
98 };
99
100 #define PCI_SPI                 0xB0
101
102 enum pci_spi_bits {
103         SPI_EN          = 0x10,
104         SPI_MISO        = 0x08,
105         SPI_MOSI        = 0x04,
106         SPI_SCLK        = 0x02,
107         SPI_CS          = 0x01,
108 };
109
110 struct jme_spi_op {
111         void __user *uwbuf;
112         void __user *urbuf;
113         __u8    wn;     /* Number of write actions */
114         __u8    rn;     /* Number of read actions */
115         __u8    bitn;   /* Number of bits per action */
116         __u8    spd;    /* The maxim acceptable speed of controller, in MHz.*/
117         __u8    mode;   /* CPOL, CPHA, and Duplex mode of SPI */
118
119         /* Internal use only */
120         u8      *kwbuf;
121         u8      *krbuf;
122         u8      sr;
123         u16     halfclk; /* Half of clock cycle calculated from spd, in ns */
124 };
125
126 enum jme_spi_op_bits {
127         SPI_MODE_CPHA   = 0x01,
128         SPI_MODE_CPOL   = 0x02,
129         SPI_MODE_DUP    = 0x80,
130 };
131
132 #define HALF_US 500     /* 500 ns */
133 #define JMESPIIOCTL     SIOCDEVPRIVATE
134
135 /*
136  * Dynamic(adaptive)/Static PCC values
137  */
138 enum dynamic_pcc_values {
139         PCC_OFF         = 0,
140         PCC_P1          = 1,
141         PCC_P2          = 2,
142         PCC_P3          = 3,
143
144         PCC_OFF_TO      = 0,
145         PCC_P1_TO       = 1,
146         PCC_P2_TO       = 64,
147         PCC_P3_TO       = 128,
148
149         PCC_OFF_CNT     = 0,
150         PCC_P1_CNT      = 1,
151         PCC_P2_CNT      = 16,
152         PCC_P3_CNT      = 32,
153 };
154 struct dynpcc_info {
155         unsigned long   last_bytes;
156         unsigned long   last_pkts;
157         unsigned long   intr_cnt;
158         unsigned char   cur;
159         unsigned char   attempt;
160         unsigned char   cnt;
161 };
162 #define PCC_INTERVAL_US 100000
163 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
164 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
165 #define PCC_P2_THRESHOLD 800
166 #define PCC_INTR_THRESHOLD 800
167 #define PCC_TX_TO 1000
168 #define PCC_TX_CNT 8
169
170 /*
171  * TX/RX Descriptors
172  *
173  * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
174  */
175 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
176 #define TX_DESC_SIZE            16
177 #define TX_RING_NR              8
178 #define TX_RING_ALLOC_SIZE(s)   ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
179
180 struct txdesc {
181         union {
182                 __u8    all[16];
183                 __le32  dw[4];
184                 struct {
185                         /* DW0 */
186                         __le16  vlan;
187                         __u8    rsv1;
188                         __u8    flags;
189
190                         /* DW1 */
191                         __le16  datalen;
192                         __le16  mss;
193
194                         /* DW2 */
195                         __le16  pktsize;
196                         __le16  rsv2;
197
198                         /* DW3 */
199                         __le32  bufaddr;
200                 } desc1;
201                 struct {
202                         /* DW0 */
203                         __le16  rsv1;
204                         __u8    rsv2;
205                         __u8    flags;
206
207                         /* DW1 */
208                         __le16  datalen;
209                         __le16  rsv3;
210
211                         /* DW2 */
212                         __le32  bufaddrh;
213
214                         /* DW3 */
215                         __le32  bufaddrl;
216                 } desc2;
217                 struct {
218                         /* DW0 */
219                         __u8    ehdrsz;
220                         __u8    rsv1;
221                         __u8    rsv2;
222                         __u8    flags;
223
224                         /* DW1 */
225                         __le16  trycnt;
226                         __le16  segcnt;
227
228                         /* DW2 */
229                         __le16  pktsz;
230                         __le16  rsv3;
231
232                         /* DW3 */
233                         __le32  bufaddrl;
234                 } descwb;
235         };
236 };
237
238 enum jme_txdesc_flags_bits {
239         TXFLAG_OWN      = 0x80,
240         TXFLAG_INT      = 0x40,
241         TXFLAG_64BIT    = 0x20,
242         TXFLAG_TCPCS    = 0x10,
243         TXFLAG_UDPCS    = 0x08,
244         TXFLAG_IPCS     = 0x04,
245         TXFLAG_LSEN     = 0x02,
246         TXFLAG_TAGON    = 0x01,
247 };
248
249 #define TXDESC_MSS_SHIFT        2
250 enum jme_txwbdesc_flags_bits {
251         TXWBFLAG_OWN    = 0x80,
252         TXWBFLAG_INT    = 0x40,
253         TXWBFLAG_TMOUT  = 0x20,
254         TXWBFLAG_TRYOUT = 0x10,
255         TXWBFLAG_COL    = 0x08,
256
257         TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
258                           TXWBFLAG_TRYOUT |
259                           TXWBFLAG_COL,
260 };
261
262 #define RX_DESC_SIZE            16
263 #define RX_RING_NR              4
264 #define RX_RING_ALLOC_SIZE(s)   ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
265 #define RX_BUF_DMA_ALIGN        8
266 #define RX_PREPAD_SIZE          10
267 #define ETH_CRC_LEN             2
268 #define RX_VLANHDR_LEN          2
269 #define RX_EXTRA_LEN            (RX_PREPAD_SIZE + \
270                                 ETH_HLEN + \
271                                 ETH_CRC_LEN + \
272                                 RX_VLANHDR_LEN + \
273                                 RX_BUF_DMA_ALIGN)
274
275 struct rxdesc {
276         union {
277                 __u8    all[16];
278                 __le32  dw[4];
279                 struct {
280                         /* DW0 */
281                         __le16  rsv2;
282                         __u8    rsv1;
283                         __u8    flags;
284
285                         /* DW1 */
286                         __le16  datalen;
287                         __le16  wbcpl;
288
289                         /* DW2 */
290                         __le32  bufaddrh;
291
292                         /* DW3 */
293                         __le32  bufaddrl;
294                 } desc1;
295                 struct {
296                         /* DW0 */
297                         __le16  vlan;
298                         __le16  flags;
299
300                         /* DW1 */
301                         __le16  framesize;
302                         __u8    errstat;
303                         __u8    desccnt;
304
305                         /* DW2 */
306                         __le32  rsshash;
307
308                         /* DW3 */
309                         __u8    hashfun;
310                         __u8    hashtype;
311                         __le16  resrv;
312                 } descwb;
313         };
314 };
315
316 enum jme_rxdesc_flags_bits {
317         RXFLAG_OWN      = 0x80,
318         RXFLAG_INT      = 0x40,
319         RXFLAG_64BIT    = 0x20,
320 };
321
322 enum jme_rxwbdesc_flags_bits {
323         RXWBFLAG_OWN            = 0x8000,
324         RXWBFLAG_INT            = 0x4000,
325         RXWBFLAG_MF             = 0x2000,
326         RXWBFLAG_64BIT          = 0x2000,
327         RXWBFLAG_TCPON          = 0x1000,
328         RXWBFLAG_UDPON          = 0x0800,
329         RXWBFLAG_IPCS           = 0x0400,
330         RXWBFLAG_TCPCS          = 0x0200,
331         RXWBFLAG_UDPCS          = 0x0100,
332         RXWBFLAG_TAGON          = 0x0080,
333         RXWBFLAG_IPV4           = 0x0040,
334         RXWBFLAG_IPV6           = 0x0020,
335         RXWBFLAG_PAUSE          = 0x0010,
336         RXWBFLAG_MAGIC          = 0x0008,
337         RXWBFLAG_WAKEUP         = 0x0004,
338         RXWBFLAG_DEST           = 0x0003,
339         RXWBFLAG_DEST_UNI       = 0x0001,
340         RXWBFLAG_DEST_MUL       = 0x0002,
341         RXWBFLAG_DEST_BRO       = 0x0003,
342 };
343
344 enum jme_rxwbdesc_desccnt_mask {
345         RXWBDCNT_WBCPL  = 0x80,
346         RXWBDCNT_DCNT   = 0x7F,
347 };
348
349 enum jme_rxwbdesc_errstat_bits {
350         RXWBERR_LIMIT   = 0x80,
351         RXWBERR_MIIER   = 0x40,
352         RXWBERR_NIBON   = 0x20,
353         RXWBERR_COLON   = 0x10,
354         RXWBERR_ABORT   = 0x08,
355         RXWBERR_SHORT   = 0x04,
356         RXWBERR_OVERUN  = 0x02,
357         RXWBERR_CRCERR  = 0x01,
358         RXWBERR_ALLERR  = 0xFF,
359 };
360
361 /*
362  * Buffer information corresponding to ring descriptors.
363  */
364 struct jme_buffer_info {
365         struct sk_buff *skb;
366         dma_addr_t mapping;
367         int len;
368         int nr_desc;
369         unsigned long start_xmit;
370 };
371
372 /*
373  * The structure holding buffer information and ring descriptors all together.
374  */
375 struct jme_ring {
376         void *alloc;            /* pointer to allocated memory */
377         void *desc;             /* pointer to ring memory  */
378         dma_addr_t dmaalloc;    /* phys address of ring alloc */
379         dma_addr_t dma;         /* phys address for ring dma */
380
381         /* Buffer information corresponding to each descriptor */
382         struct jme_buffer_info *bufinf;
383
384         int next_to_use;
385         atomic_t next_to_clean;
386         atomic_t nr_free;
387 };
388
389 #define NET_STAT(priv) (priv->dev->stats)
390 #define NETDEV_GET_STATS(netdev, fun_ptr)
391 #define DECLARE_NET_DEVICE_STATS
392
393 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
394 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
395         netif_napi_add(dev, napis, pollfn, q);
396 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
397 #define JME_NAPI_WEIGHT(w) int w
398 #define JME_NAPI_WEIGHT_VAL(w) w
399 #define JME_NAPI_WEIGHT_SET(w, r)
400 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
401 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
402 #define JME_NAPI_DISABLE(priv) \
403         if (!napi_disable_pending(&priv->napi)) \
404                 napi_disable(&priv->napi);
405 #define JME_RX_SCHEDULE_PREP(priv) \
406         napi_schedule_prep(&priv->napi)
407 #define JME_RX_SCHEDULE(priv) \
408         __napi_schedule(&priv->napi);
409
410 /*
411  * Jmac Adapter Private data
412  */
413 #define SHADOW_REG_NR 8
414 struct jme_adapter {
415         struct pci_dev          *pdev;
416         struct net_device       *dev;
417         void __iomem            *regs;
418         dma_addr_t              shadow_dma;
419         u32                     *shadow_regs;
420         struct mii_if_info      mii_if;
421         struct jme_ring         rxring[RX_RING_NR];
422         struct jme_ring         txring[TX_RING_NR];
423         spinlock_t              phy_lock;
424         spinlock_t              macaddr_lock;
425         spinlock_t              rxmcs_lock;
426         struct tasklet_struct   rxempty_task;
427         struct tasklet_struct   rxclean_task;
428         struct tasklet_struct   txclean_task;
429         struct tasklet_struct   linkch_task;
430         struct tasklet_struct   pcc_task;
431         unsigned long           flags;
432         u32                     reg_txcs;
433         u32                     reg_txpfc;
434         u32                     reg_rxcs;
435         u32                     reg_rxmcs;
436         u32                     reg_ghc;
437         u32                     reg_pmcs;
438         u32                     phylink;
439         u32                     tx_ring_size;
440         u32                     tx_ring_mask;
441         u32                     tx_wake_threshold;
442         u32                     rx_ring_size;
443         u32                     rx_ring_mask;
444         u8                      mrrs;
445         unsigned int            fpgaver;
446         unsigned int            chiprev;
447         u8                      rev;
448         u32                     msg_enable;
449         struct ethtool_cmd      old_ecmd;
450         unsigned int            old_mtu;
451         struct vlan_group       *vlgrp;
452         struct dynpcc_info      dpi;
453         atomic_t                intr_sem;
454         atomic_t                link_changing;
455         atomic_t                tx_cleaning;
456         atomic_t                rx_cleaning;
457         atomic_t                rx_empty;
458         int                     (*jme_rx)(struct sk_buff *skb);
459         int                     (*jme_vlan_rx)(struct sk_buff *skb,
460                                           struct vlan_group *grp,
461                                           unsigned short vlan_tag);
462         DECLARE_NAPI_STRUCT
463         DECLARE_NET_DEVICE_STATS
464 };
465
466 enum shadow_reg_val {
467         SHADOW_IEVE = 0,
468 };
469
470 enum jme_flags_bits {
471         JME_FLAG_MSI            = 1,
472         JME_FLAG_SSET           = 2,
473         JME_FLAG_TXCSUM         = 3,
474         JME_FLAG_TSO            = 4,
475         JME_FLAG_POLL           = 5,
476         JME_FLAG_SHUTDOWN       = 6,
477 };
478
479 #define TX_TIMEOUT              (5 * HZ)
480 #define JME_REG_LEN             0x500
481 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
482
483 static inline struct jme_adapter*
484 jme_napi_priv(struct napi_struct *napi)
485 {
486         struct jme_adapter *jme;
487         jme = container_of(napi, struct jme_adapter, napi);
488         return jme;
489 }
490
491 /*
492  * MMaped I/O Resters
493  */
494 enum jme_iomap_offsets {
495         JME_MAC         = 0x0000,
496         JME_PHY         = 0x0400,
497         JME_MISC        = 0x0800,
498         JME_RSS         = 0x0C00,
499 };
500
501 enum jme_iomap_lens {
502         JME_MAC_LEN     = 0x80,
503         JME_PHY_LEN     = 0x58,
504         JME_MISC_LEN    = 0x98,
505         JME_RSS_LEN     = 0xFF,
506 };
507
508 enum jme_iomap_regs {
509         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
510         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
511         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
512         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
513         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
514         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
515         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
516         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
517
518         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
519         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
520         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
521         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
522         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
523         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
524         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
525         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
526         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
527         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
528         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
529         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
530
531         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
532         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
533         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
534
535
536         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
537         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
538         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
539         JME_SMBINTF     = JME_PHY | 0x44, /* SMB Interface */
540
541
542         JME_TMCSR       = JME_MISC | 0x00, /* Timer Control/Status Register */
543         JME_GPREG0      = JME_MISC | 0x08, /* General purpose REG-0 */
544         JME_GPREG1      = JME_MISC | 0x0C, /* General purpose REG-1 */
545         JME_IEVE        = JME_MISC | 0x20, /* Interrupt Event Status */
546         JME_IREQ        = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
547         JME_IENS        = JME_MISC | 0x28, /* Intr Enable - Setting Port */
548         JME_IENC        = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
549         JME_PCCRX0      = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
550         JME_PCCTX       = JME_MISC | 0x40, /* PCC Control for TX Queues */
551         JME_CHIPMODE    = JME_MISC | 0x44, /* Identify FPGA Version */
552         JME_SHBA_HI     = JME_MISC | 0x48, /* Shadow Register Base HI */
553         JME_SHBA_LO     = JME_MISC | 0x4C, /* Shadow Register Base LO */
554         JME_TIMER1      = JME_MISC | 0x70, /* Timer1 */
555         JME_TIMER2      = JME_MISC | 0x74, /* Timer2 */
556         JME_APMC        = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
557         JME_PCCSRX0     = JME_MISC | 0x80, /* PCC Status of RX0 */
558 };
559
560 /*
561  * TX Control/Status Bits
562  */
563 enum jme_txcs_bits {
564         TXCS_QUEUE7S    = 0x00008000,
565         TXCS_QUEUE6S    = 0x00004000,
566         TXCS_QUEUE5S    = 0x00002000,
567         TXCS_QUEUE4S    = 0x00001000,
568         TXCS_QUEUE3S    = 0x00000800,
569         TXCS_QUEUE2S    = 0x00000400,
570         TXCS_QUEUE1S    = 0x00000200,
571         TXCS_QUEUE0S    = 0x00000100,
572         TXCS_FIFOTH     = 0x000000C0,
573         TXCS_DMASIZE    = 0x00000030,
574         TXCS_BURST      = 0x00000004,
575         TXCS_ENABLE     = 0x00000001,
576 };
577
578 enum jme_txcs_value {
579         TXCS_FIFOTH_16QW        = 0x000000C0,
580         TXCS_FIFOTH_12QW        = 0x00000080,
581         TXCS_FIFOTH_8QW         = 0x00000040,
582         TXCS_FIFOTH_4QW         = 0x00000000,
583
584         TXCS_DMASIZE_64B        = 0x00000000,
585         TXCS_DMASIZE_128B       = 0x00000010,
586         TXCS_DMASIZE_256B       = 0x00000020,
587         TXCS_DMASIZE_512B       = 0x00000030,
588
589         TXCS_SELECT_QUEUE0      = 0x00000000,
590         TXCS_SELECT_QUEUE1      = 0x00010000,
591         TXCS_SELECT_QUEUE2      = 0x00020000,
592         TXCS_SELECT_QUEUE3      = 0x00030000,
593         TXCS_SELECT_QUEUE4      = 0x00040000,
594         TXCS_SELECT_QUEUE5      = 0x00050000,
595         TXCS_SELECT_QUEUE6      = 0x00060000,
596         TXCS_SELECT_QUEUE7      = 0x00070000,
597
598         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
599                                   TXCS_BURST,
600 };
601
602 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
603
604 /*
605  * TX MAC Control/Status Bits
606  */
607 enum jme_txmcs_bit_masks {
608         TXMCS_IFG2              = 0xC0000000,
609         TXMCS_IFG1              = 0x30000000,
610         TXMCS_TTHOLD            = 0x00000300,
611         TXMCS_FBURST            = 0x00000080,
612         TXMCS_CARRIEREXT        = 0x00000040,
613         TXMCS_DEFER             = 0x00000020,
614         TXMCS_BACKOFF           = 0x00000010,
615         TXMCS_CARRIERSENSE      = 0x00000008,
616         TXMCS_COLLISION         = 0x00000004,
617         TXMCS_CRC               = 0x00000002,
618         TXMCS_PADDING           = 0x00000001,
619 };
620
621 enum jme_txmcs_values {
622         TXMCS_IFG2_6_4          = 0x00000000,
623         TXMCS_IFG2_8_5          = 0x40000000,
624         TXMCS_IFG2_10_6         = 0x80000000,
625         TXMCS_IFG2_12_7         = 0xC0000000,
626
627         TXMCS_IFG1_8_4          = 0x00000000,
628         TXMCS_IFG1_12_6         = 0x10000000,
629         TXMCS_IFG1_16_8         = 0x20000000,
630         TXMCS_IFG1_20_10        = 0x30000000,
631
632         TXMCS_TTHOLD_1_8        = 0x00000000,
633         TXMCS_TTHOLD_1_4        = 0x00000100,
634         TXMCS_TTHOLD_1_2        = 0x00000200,
635         TXMCS_TTHOLD_FULL       = 0x00000300,
636
637         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
638                                   TXMCS_IFG1_16_8 |
639                                   TXMCS_TTHOLD_FULL |
640                                   TXMCS_DEFER |
641                                   TXMCS_CRC |
642                                   TXMCS_PADDING,
643 };
644
645 enum jme_txpfc_bits_masks {
646         TXPFC_VLAN_TAG          = 0xFFFF0000,
647         TXPFC_VLAN_EN           = 0x00008000,
648         TXPFC_PF_EN             = 0x00000001,
649 };
650
651 enum jme_txtrhd_bits_masks {
652         TXTRHD_TXPEN            = 0x80000000,
653         TXTRHD_TXP              = 0x7FFFFF00,
654         TXTRHD_TXREN            = 0x00000080,
655         TXTRHD_TXRL             = 0x0000007F,
656 };
657
658 enum jme_txtrhd_shifts {
659         TXTRHD_TXP_SHIFT        = 8,
660         TXTRHD_TXRL_SHIFT       = 0,
661 };
662
663 /*
664  * RX Control/Status Bits
665  */
666 enum jme_rxcs_bit_masks {
667         /* FIFO full threshold for transmitting Tx Pause Packet */
668         RXCS_FIFOTHTP   = 0x30000000,
669         /* FIFO threshold for processing next packet */
670         RXCS_FIFOTHNP   = 0x0C000000,
671         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
672         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
673         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
674         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
675         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
676         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
677         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
678         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
679         RXCS_QST        = 0x00000004, /* Receive queue start */
680         RXCS_SUSPEND    = 0x00000002,
681         RXCS_ENABLE     = 0x00000001,
682 };
683
684 enum jme_rxcs_values {
685         RXCS_FIFOTHTP_16T       = 0x00000000,
686         RXCS_FIFOTHTP_32T       = 0x10000000,
687         RXCS_FIFOTHTP_64T       = 0x20000000,
688         RXCS_FIFOTHTP_128T      = 0x30000000,
689
690         RXCS_FIFOTHNP_16QW      = 0x00000000,
691         RXCS_FIFOTHNP_32QW      = 0x04000000,
692         RXCS_FIFOTHNP_64QW      = 0x08000000,
693         RXCS_FIFOTHNP_128QW     = 0x0C000000,
694
695         RXCS_DMAREQSZ_16B       = 0x00000000,
696         RXCS_DMAREQSZ_32B       = 0x01000000,
697         RXCS_DMAREQSZ_64B       = 0x02000000,
698         RXCS_DMAREQSZ_128B      = 0x03000000,
699
700         RXCS_QUEUESEL_Q0        = 0x00000000,
701         RXCS_QUEUESEL_Q1        = 0x00010000,
702         RXCS_QUEUESEL_Q2        = 0x00020000,
703         RXCS_QUEUESEL_Q3        = 0x00030000,
704
705         RXCS_RETRYGAP_256ns     = 0x00000000,
706         RXCS_RETRYGAP_512ns     = 0x00001000,
707         RXCS_RETRYGAP_1024ns    = 0x00002000,
708         RXCS_RETRYGAP_2048ns    = 0x00003000,
709         RXCS_RETRYGAP_4096ns    = 0x00004000,
710         RXCS_RETRYGAP_8192ns    = 0x00005000,
711         RXCS_RETRYGAP_16384ns   = 0x00006000,
712         RXCS_RETRYGAP_32768ns   = 0x00007000,
713
714         RXCS_RETRYCNT_0         = 0x00000000,
715         RXCS_RETRYCNT_4         = 0x00000100,
716         RXCS_RETRYCNT_8         = 0x00000200,
717         RXCS_RETRYCNT_12        = 0x00000300,
718         RXCS_RETRYCNT_16        = 0x00000400,
719         RXCS_RETRYCNT_20        = 0x00000500,
720         RXCS_RETRYCNT_24        = 0x00000600,
721         RXCS_RETRYCNT_28        = 0x00000700,
722         RXCS_RETRYCNT_32        = 0x00000800,
723         RXCS_RETRYCNT_36        = 0x00000900,
724         RXCS_RETRYCNT_40        = 0x00000A00,
725         RXCS_RETRYCNT_44        = 0x00000B00,
726         RXCS_RETRYCNT_48        = 0x00000C00,
727         RXCS_RETRYCNT_52        = 0x00000D00,
728         RXCS_RETRYCNT_56        = 0x00000E00,
729         RXCS_RETRYCNT_60        = 0x00000F00,
730
731         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
732                                   RXCS_FIFOTHNP_128QW |
733                                   RXCS_DMAREQSZ_128B |
734                                   RXCS_RETRYGAP_256ns |
735                                   RXCS_RETRYCNT_32,
736 };
737
738 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
739
740 /*
741  * RX MAC Control/Status Bits
742  */
743 enum jme_rxmcs_bits {
744         RXMCS_ALLFRAME          = 0x00000800,
745         RXMCS_BRDFRAME          = 0x00000400,
746         RXMCS_MULFRAME          = 0x00000200,
747         RXMCS_UNIFRAME          = 0x00000100,
748         RXMCS_ALLMULFRAME       = 0x00000080,
749         RXMCS_MULFILTERED       = 0x00000040,
750         RXMCS_RXCOLLDEC         = 0x00000020,
751         RXMCS_FLOWCTRL          = 0x00000008,
752         RXMCS_VTAGRM            = 0x00000004,
753         RXMCS_PREPAD            = 0x00000002,
754         RXMCS_CHECKSUM          = 0x00000001,
755
756         RXMCS_DEFAULT           = RXMCS_VTAGRM |
757                                   RXMCS_PREPAD |
758                                   RXMCS_FLOWCTRL |
759                                   RXMCS_CHECKSUM,
760 };
761
762 /*
763  * Wakeup Frame setup interface registers
764  */
765 #define WAKEUP_FRAME_NR 8
766 #define WAKEUP_FRAME_MASK_DWNR  4
767
768 enum jme_wfoi_bit_masks {
769         WFOI_MASK_SEL           = 0x00000070,
770         WFOI_CRC_SEL            = 0x00000008,
771         WFOI_FRAME_SEL          = 0x00000007,
772 };
773
774 enum jme_wfoi_shifts {
775         WFOI_MASK_SHIFT         = 4,
776 };
777
778 /*
779  * SMI Related definitions
780  */
781 enum jme_smi_bit_mask {
782         SMI_DATA_MASK           = 0xFFFF0000,
783         SMI_REG_ADDR_MASK       = 0x0000F800,
784         SMI_PHY_ADDR_MASK       = 0x000007C0,
785         SMI_OP_WRITE            = 0x00000020,
786         /* Set to 1, after req done it'll be cleared to 0 */
787         SMI_OP_REQ              = 0x00000010,
788         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
789         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
790         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
791         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
792 };
793
794 enum jme_smi_bit_shift {
795         SMI_DATA_SHIFT          = 16,
796         SMI_REG_ADDR_SHIFT      = 11,
797         SMI_PHY_ADDR_SHIFT      = 6,
798 };
799
800 static inline u32 smi_reg_addr(int x)
801 {
802         return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
803 }
804
805 static inline u32 smi_phy_addr(int x)
806 {
807         return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
808 }
809
810 #define JME_PHY_TIMEOUT 100 /* 100 msec */
811 #define JME_PHY_REG_NR 32
812
813 /*
814  * Global Host Control
815  */
816 enum jme_ghc_bit_mask {
817         GHC_SWRST               = 0x40000000,
818         GHC_DPX                 = 0x00000040,
819         GHC_SPEED               = 0x00000030,
820         GHC_LINK_POLL           = 0x00000001,
821 };
822
823 enum jme_ghc_speed_val {
824         GHC_SPEED_10M           = 0x00000010,
825         GHC_SPEED_100M          = 0x00000020,
826         GHC_SPEED_1000M         = 0x00000030,
827 };
828
829 enum jme_ghc_to_clk {
830         GHC_TO_CLK_OFF          = 0x00000000,
831         GHC_TO_CLK_GPHY         = 0x00400000,
832         GHC_TO_CLK_PCIE         = 0x00800000,
833         GHC_TO_CLK_INVALID      = 0x00C00000,
834 };
835
836 enum jme_ghc_txmac_clk {
837         GHC_TXMAC_CLK_OFF       = 0x00000000,
838         GHC_TXMAC_CLK_GPHY      = 0x00100000,
839         GHC_TXMAC_CLK_PCIE      = 0x00200000,
840         GHC_TXMAC_CLK_INVALID   = 0x00300000,
841 };
842
843 /*
844  * Power management control and status register
845  */
846 enum jme_pmcs_bit_masks {
847         PMCS_WF7DET     = 0x80000000,
848         PMCS_WF6DET     = 0x40000000,
849         PMCS_WF5DET     = 0x20000000,
850         PMCS_WF4DET     = 0x10000000,
851         PMCS_WF3DET     = 0x08000000,
852         PMCS_WF2DET     = 0x04000000,
853         PMCS_WF1DET     = 0x02000000,
854         PMCS_WF0DET     = 0x01000000,
855         PMCS_LFDET      = 0x00040000,
856         PMCS_LRDET      = 0x00020000,
857         PMCS_MFDET      = 0x00010000,
858         PMCS_WF7EN      = 0x00008000,
859         PMCS_WF6EN      = 0x00004000,
860         PMCS_WF5EN      = 0x00002000,
861         PMCS_WF4EN      = 0x00001000,
862         PMCS_WF3EN      = 0x00000800,
863         PMCS_WF2EN      = 0x00000400,
864         PMCS_WF1EN      = 0x00000200,
865         PMCS_WF0EN      = 0x00000100,
866         PMCS_LFEN       = 0x00000004,
867         PMCS_LREN       = 0x00000002,
868         PMCS_MFEN       = 0x00000001,
869 };
870
871 /*
872  * Giga PHY Status Registers
873  */
874 enum jme_phy_link_bit_mask {
875         PHY_LINK_SPEED_MASK             = 0x0000C000,
876         PHY_LINK_DUPLEX                 = 0x00002000,
877         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
878         PHY_LINK_UP                     = 0x00000400,
879         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
880         PHY_LINK_MDI_STAT               = 0x00000040,
881 };
882
883 enum jme_phy_link_speed_val {
884         PHY_LINK_SPEED_10M              = 0x00000000,
885         PHY_LINK_SPEED_100M             = 0x00004000,
886         PHY_LINK_SPEED_1000M            = 0x00008000,
887 };
888
889 #define JME_SPDRSV_TIMEOUT      500     /* 500 us */
890
891 /*
892  * SMB Control and Status
893  */
894 enum jme_smbcsr_bit_mask {
895         SMBCSR_CNACK    = 0x00020000,
896         SMBCSR_RELOAD   = 0x00010000,
897         SMBCSR_EEPROMD  = 0x00000020,
898         SMBCSR_INITDONE = 0x00000010,
899         SMBCSR_BUSY     = 0x0000000F,
900 };
901
902 enum jme_smbintf_bit_mask {
903         SMBINTF_HWDATR  = 0xFF000000,
904         SMBINTF_HWDATW  = 0x00FF0000,
905         SMBINTF_HWADDR  = 0x0000FF00,
906         SMBINTF_HWRWN   = 0x00000020,
907         SMBINTF_HWCMD   = 0x00000010,
908         SMBINTF_FASTM   = 0x00000008,
909         SMBINTF_GPIOSCL = 0x00000004,
910         SMBINTF_GPIOSDA = 0x00000002,
911         SMBINTF_GPIOEN  = 0x00000001,
912 };
913
914 enum jme_smbintf_vals {
915         SMBINTF_HWRWN_READ      = 0x00000020,
916         SMBINTF_HWRWN_WRITE     = 0x00000000,
917 };
918
919 enum jme_smbintf_shifts {
920         SMBINTF_HWDATR_SHIFT    = 24,
921         SMBINTF_HWDATW_SHIFT    = 16,
922         SMBINTF_HWADDR_SHIFT    = 8,
923 };
924
925 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
926 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
927 #define JME_SMB_LEN 256
928 #define JME_EEPROM_MAGIC 0x250
929
930 /*
931  * Timer Control/Status Register
932  */
933 enum jme_tmcsr_bit_masks {
934         TMCSR_SWIT      = 0x80000000,
935         TMCSR_EN        = 0x01000000,
936         TMCSR_CNT       = 0x00FFFFFF,
937 };
938
939 /*
940  * General Purpose REG-0
941  */
942 enum jme_gpreg0_masks {
943         GPREG0_DISSH            = 0xFF000000,
944         GPREG0_PCIRLMT          = 0x00300000,
945         GPREG0_PCCNOMUTCLR      = 0x00040000,
946         GPREG0_LNKINTPOLL       = 0x00001000,
947         GPREG0_PCCTMR           = 0x00000300,
948         GPREG0_PHYADDR          = 0x0000001F,
949 };
950
951 enum jme_gpreg0_vals {
952         GPREG0_DISSH_DW7        = 0x80000000,
953         GPREG0_DISSH_DW6        = 0x40000000,
954         GPREG0_DISSH_DW5        = 0x20000000,
955         GPREG0_DISSH_DW4        = 0x10000000,
956         GPREG0_DISSH_DW3        = 0x08000000,
957         GPREG0_DISSH_DW2        = 0x04000000,
958         GPREG0_DISSH_DW1        = 0x02000000,
959         GPREG0_DISSH_DW0        = 0x01000000,
960         GPREG0_DISSH_ALL        = 0xFF000000,
961
962         GPREG0_PCIRLMT_8        = 0x00000000,
963         GPREG0_PCIRLMT_6        = 0x00100000,
964         GPREG0_PCIRLMT_5        = 0x00200000,
965         GPREG0_PCIRLMT_4        = 0x00300000,
966
967         GPREG0_PCCTMR_16ns      = 0x00000000,
968         GPREG0_PCCTMR_256ns     = 0x00000100,
969         GPREG0_PCCTMR_1us       = 0x00000200,
970         GPREG0_PCCTMR_1ms       = 0x00000300,
971
972         GPREG0_PHYADDR_1        = 0x00000001,
973
974         GPREG0_DEFAULT          = GPREG0_PCIRLMT_4 |
975                                   GPREG0_PCCTMR_1us |
976                                   GPREG0_PHYADDR_1,
977 };
978
979 /*
980  * General Purpose REG-1
981  * Note: All theses bits defined here are for
982  *       Chip mode revision 0x11 only
983  */
984 enum jme_gpreg1_masks {
985         GPREG1_INTRDELAYUNIT    = 0x00000018,
986         GPREG1_INTRDELAYENABLE  = 0x00000007,
987 };
988
989 enum jme_gpreg1_vals {
990         GPREG1_RSSPATCH         = 0x00000040,
991         GPREG1_HALFMODEPATCH    = 0x00000020,
992
993         GPREG1_INTDLYUNIT_16NS  = 0x00000000,
994         GPREG1_INTDLYUNIT_256NS = 0x00000008,
995         GPREG1_INTDLYUNIT_1US   = 0x00000010,
996         GPREG1_INTDLYUNIT_16US  = 0x00000018,
997
998         GPREG1_INTDLYEN_1U      = 0x00000001,
999         GPREG1_INTDLYEN_2U      = 0x00000002,
1000         GPREG1_INTDLYEN_3U      = 0x00000003,
1001         GPREG1_INTDLYEN_4U      = 0x00000004,
1002         GPREG1_INTDLYEN_5U      = 0x00000005,
1003         GPREG1_INTDLYEN_6U      = 0x00000006,
1004         GPREG1_INTDLYEN_7U      = 0x00000007,
1005
1006         GPREG1_DEFAULT          = 0x00000000,
1007 };
1008
1009 /*
1010  * Interrupt Status Bits
1011  */
1012 enum jme_interrupt_bits {
1013         INTR_SWINTR     = 0x80000000,
1014         INTR_TMINTR     = 0x40000000,
1015         INTR_LINKCH     = 0x20000000,
1016         INTR_PAUSERCV   = 0x10000000,
1017         INTR_MAGICRCV   = 0x08000000,
1018         INTR_WAKERCV    = 0x04000000,
1019         INTR_PCCRX0TO   = 0x02000000,
1020         INTR_PCCRX1TO   = 0x01000000,
1021         INTR_PCCRX2TO   = 0x00800000,
1022         INTR_PCCRX3TO   = 0x00400000,
1023         INTR_PCCTXTO    = 0x00200000,
1024         INTR_PCCRX0     = 0x00100000,
1025         INTR_PCCRX1     = 0x00080000,
1026         INTR_PCCRX2     = 0x00040000,
1027         INTR_PCCRX3     = 0x00020000,
1028         INTR_PCCTX      = 0x00010000,
1029         INTR_RX3EMP     = 0x00008000,
1030         INTR_RX2EMP     = 0x00004000,
1031         INTR_RX1EMP     = 0x00002000,
1032         INTR_RX0EMP     = 0x00001000,
1033         INTR_RX3        = 0x00000800,
1034         INTR_RX2        = 0x00000400,
1035         INTR_RX1        = 0x00000200,
1036         INTR_RX0        = 0x00000100,
1037         INTR_TX7        = 0x00000080,
1038         INTR_TX6        = 0x00000040,
1039         INTR_TX5        = 0x00000020,
1040         INTR_TX4        = 0x00000010,
1041         INTR_TX3        = 0x00000008,
1042         INTR_TX2        = 0x00000004,
1043         INTR_TX1        = 0x00000002,
1044         INTR_TX0        = 0x00000001,
1045 };
1046
1047 static const u32 INTR_ENABLE = INTR_SWINTR |
1048                                  INTR_TMINTR |
1049                                  INTR_LINKCH |
1050                                  INTR_PCCRX0TO |
1051                                  INTR_PCCRX0 |
1052                                  INTR_PCCTXTO |
1053                                  INTR_PCCTX |
1054                                  INTR_RX0EMP;
1055
1056 /*
1057  * PCC Control Registers
1058  */
1059 enum jme_pccrx_masks {
1060         PCCRXTO_MASK    = 0xFFFF0000,
1061         PCCRX_MASK      = 0x0000FF00,
1062 };
1063
1064 enum jme_pcctx_masks {
1065         PCCTXTO_MASK    = 0xFFFF0000,
1066         PCCTX_MASK      = 0x0000FF00,
1067         PCCTX_QS_MASK   = 0x000000FF,
1068 };
1069
1070 enum jme_pccrx_shifts {
1071         PCCRXTO_SHIFT   = 16,
1072         PCCRX_SHIFT     = 8,
1073 };
1074
1075 enum jme_pcctx_shifts {
1076         PCCTXTO_SHIFT   = 16,
1077         PCCTX_SHIFT     = 8,
1078 };
1079
1080 enum jme_pcctx_bits {
1081         PCCTXQ0_EN      = 0x00000001,
1082         PCCTXQ1_EN      = 0x00000002,
1083         PCCTXQ2_EN      = 0x00000004,
1084         PCCTXQ3_EN      = 0x00000008,
1085         PCCTXQ4_EN      = 0x00000010,
1086         PCCTXQ5_EN      = 0x00000020,
1087         PCCTXQ6_EN      = 0x00000040,
1088         PCCTXQ7_EN      = 0x00000080,
1089 };
1090
1091 /*
1092  * Chip Mode Register
1093  */
1094 enum jme_chipmode_bit_masks {
1095         CM_FPGAVER_MASK         = 0xFFFF0000,
1096         CM_CHIPREV_MASK         = 0x0000FF00,
1097         CM_CHIPMODE_MASK        = 0x0000000F,
1098 };
1099
1100 enum jme_chipmode_shifts {
1101         CM_FPGAVER_SHIFT        = 16,
1102         CM_CHIPREV_SHIFT        = 8,
1103 };
1104
1105 /*
1106  * Shadow base address register bits
1107  */
1108 enum jme_shadow_base_address_bits {
1109         SHBA_POSTEN     = 0x1,
1110 };
1111
1112 /*
1113  * Aggressive Power Mode Control
1114  */
1115 enum jme_apmc_bits {
1116         JME_APMC_PCIE_SD_EN     = 0x40000000,
1117         JME_APMC_PSEUDO_HP_EN   = 0x20000000,
1118         JME_APMC_EPIEN          = 0x04000000,
1119         JME_APMC_EPIEN_CTRL     = 0x03000000,
1120 };
1121
1122 enum jme_apmc_values {
1123         JME_APMC_EPIEN_CTRL_EN  = 0x02000000,
1124         JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1125 };
1126
1127 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1128
1129 #ifdef REG_DEBUG
1130 static char *MAC_REG_NAME[] = {
1131         "JME_TXCS",      "JME_TXDBA_LO",  "JME_TXDBA_HI", "JME_TXQDC",
1132         "JME_TXNDA",     "JME_TXMCS",     "JME_TXPFC",    "JME_TXTRHD",
1133         "JME_RXCS",      "JME_RXDBA_LO",  "JME_RXDBA_HI", "JME_RXQDC",
1134         "JME_RXNDA",     "JME_RXMCS",     "JME_RXUMA_LO", "JME_RXUMA_HI",
1135         "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP",    "JME_WFOI",
1136         "JME_SMI",       "JME_GHC",       "UNKNOWN",      "UNKNOWN",
1137         "JME_PMCS"};
1138
1139 static char *PE_REG_NAME[] = {
1140         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1141         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1142         "UNKNOWN",      "UNKNOWN",     "JME_PHY_CS", "UNKNOWN",
1143         "JME_PHY_LINK", "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1144         "JME_SMBCSR",   "JME_SMBINTF"};
1145
1146 static char *MISC_REG_NAME[] = {
1147         "JME_TMCSR",  "JME_GPIO",     "JME_GPREG0",  "JME_GPREG1",
1148         "JME_IEVE",   "JME_IREQ",     "JME_IENS",    "JME_IENC",
1149         "JME_PCCRX0", "JME_PCCRX1",   "JME_PCCRX2",  "JME_PCCRX3",
1150         "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1151         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1152         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1153         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1154         "JME_TIMER1", "JME_TIMER2",   "UNKNOWN",     "JME_APMC",
1155         "JME_PCCSRX0"};
1156
1157 static inline void reg_dbg(const struct jme_adapter *jme,
1158                 const char *msg, u32 val, u32 reg)
1159 {
1160         const char *regname;
1161         switch (reg & 0xF00) {
1162         case 0x000:
1163                 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1164                 break;
1165         case 0x400:
1166                 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1167                 break;
1168         case 0x800:
1169                 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1170                 break;
1171         default:
1172                 regname = PE_REG_NAME[0];
1173         }
1174         printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1175                         msg, val, regname);
1176 }
1177 #else
1178 static inline void reg_dbg(const struct jme_adapter *jme,
1179                 const char *msg, u32 val, u32 reg) {}
1180 #endif
1181
1182 /*
1183  * Read/Write MMaped I/O Registers
1184  */
1185 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1186 {
1187         return readl(jme->regs + reg);
1188 }
1189
1190 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1191 {
1192         reg_dbg(jme, "REG WRITE", val, reg);
1193         writel(val, jme->regs + reg);
1194         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1195 }
1196
1197 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1198 {
1199         /*
1200          * Read after write should cause flush
1201          */
1202         reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1203         writel(val, jme->regs + reg);
1204         readl(jme->regs + reg);
1205         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1206 }
1207
1208 /*
1209  * PHY Regs
1210  */
1211 enum jme_phy_reg17_bit_masks {
1212         PREG17_SPEED            = 0xC000,
1213         PREG17_DUPLEX           = 0x2000,
1214         PREG17_SPDRSV           = 0x0800,
1215         PREG17_LNKUP            = 0x0400,
1216         PREG17_MDI              = 0x0040,
1217 };
1218
1219 enum jme_phy_reg17_vals {
1220         PREG17_SPEED_10M        = 0x0000,
1221         PREG17_SPEED_100M       = 0x4000,
1222         PREG17_SPEED_1000M      = 0x8000,
1223 };
1224
1225 #define BMSR_ANCOMP               0x0020
1226
1227 /*
1228  * Workaround
1229  */
1230 static inline int is_buggy250(unsigned short device, unsigned int chiprev)
1231 {
1232         return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1233 }
1234
1235 /*
1236  * Function prototypes
1237  */
1238 static int jme_set_settings(struct net_device *netdev,
1239                                 struct ethtool_cmd *ecmd);
1240 static void jme_set_multi(struct net_device *netdev);
1241
1242 #endif