Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes...
[linux-2.6.git] / drivers / net / jme.h
1 /*
2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3  *
4  * Copyright 2008 JMicron Technology Corporation
5  * http://www.jmicron.com/
6  *
7  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  *
22  */
23
24 #ifndef __JME_H_INCLUDED__
25 #define __JME_H_INCLUDED__
26
27 #define DRV_NAME        "jme"
28 #define DRV_VERSION     "1.0.6"
29 #define PFX             DRV_NAME ": "
30
31 #define PCI_DEVICE_ID_JMICRON_JMC250    0x0250
32 #define PCI_DEVICE_ID_JMICRON_JMC260    0x0260
33
34 /*
35  * Message related definitions
36  */
37 #define JME_DEF_MSG_ENABLE \
38         (NETIF_MSG_PROBE | \
39         NETIF_MSG_LINK | \
40         NETIF_MSG_RX_ERR | \
41         NETIF_MSG_TX_ERR | \
42         NETIF_MSG_HW)
43
44 #define jeprintk(pdev, fmt, args...) \
45         printk(KERN_ERR PFX fmt, ## args)
46
47 #ifdef TX_DEBUG
48 #define tx_dbg(priv, fmt, args...)                                      \
49         printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
50 #else
51 #define tx_dbg(priv, fmt, args...)                                      \
52 do {                                                                    \
53         if (0)                                                          \
54                 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
55 } while (0)
56 #endif
57
58 /*
59  * Extra PCI Configuration space interface
60  */
61 #define PCI_DCSR_MRRS           0x59
62 #define PCI_DCSR_MRRS_MASK      0x70
63
64 enum pci_dcsr_mrrs_vals {
65         MRRS_128B       = 0x00,
66         MRRS_256B       = 0x10,
67         MRRS_512B       = 0x20,
68         MRRS_1024B      = 0x30,
69         MRRS_2048B      = 0x40,
70         MRRS_4096B      = 0x50,
71 };
72
73 #define PCI_SPI                 0xB0
74
75 enum pci_spi_bits {
76         SPI_EN          = 0x10,
77         SPI_MISO        = 0x08,
78         SPI_MOSI        = 0x04,
79         SPI_SCLK        = 0x02,
80         SPI_CS          = 0x01,
81 };
82
83 struct jme_spi_op {
84         void __user *uwbuf;
85         void __user *urbuf;
86         __u8    wn;     /* Number of write actions */
87         __u8    rn;     /* Number of read actions */
88         __u8    bitn;   /* Number of bits per action */
89         __u8    spd;    /* The maxim acceptable speed of controller, in MHz.*/
90         __u8    mode;   /* CPOL, CPHA, and Duplex mode of SPI */
91
92         /* Internal use only */
93         u8      *kwbuf;
94         u8      *krbuf;
95         u8      sr;
96         u16     halfclk; /* Half of clock cycle calculated from spd, in ns */
97 };
98
99 enum jme_spi_op_bits {
100         SPI_MODE_CPHA   = 0x01,
101         SPI_MODE_CPOL   = 0x02,
102         SPI_MODE_DUP    = 0x80,
103 };
104
105 #define HALF_US 500     /* 500 ns */
106 #define JMESPIIOCTL     SIOCDEVPRIVATE
107
108 /*
109  * Dynamic(adaptive)/Static PCC values
110  */
111 enum dynamic_pcc_values {
112         PCC_OFF         = 0,
113         PCC_P1          = 1,
114         PCC_P2          = 2,
115         PCC_P3          = 3,
116
117         PCC_OFF_TO      = 0,
118         PCC_P1_TO       = 1,
119         PCC_P2_TO       = 64,
120         PCC_P3_TO       = 128,
121
122         PCC_OFF_CNT     = 0,
123         PCC_P1_CNT      = 1,
124         PCC_P2_CNT      = 16,
125         PCC_P3_CNT      = 32,
126 };
127 struct dynpcc_info {
128         unsigned long   last_bytes;
129         unsigned long   last_pkts;
130         unsigned long   intr_cnt;
131         unsigned char   cur;
132         unsigned char   attempt;
133         unsigned char   cnt;
134 };
135 #define PCC_INTERVAL_US 100000
136 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
137 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
138 #define PCC_P2_THRESHOLD 800
139 #define PCC_INTR_THRESHOLD 800
140 #define PCC_TX_TO 1000
141 #define PCC_TX_CNT 8
142
143 /*
144  * TX/RX Descriptors
145  *
146  * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
147  */
148 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
149 #define TX_DESC_SIZE            16
150 #define TX_RING_NR              8
151 #define TX_RING_ALLOC_SIZE(s)   ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
152
153 struct txdesc {
154         union {
155                 __u8    all[16];
156                 __le32  dw[4];
157                 struct {
158                         /* DW0 */
159                         __le16  vlan;
160                         __u8    rsv1;
161                         __u8    flags;
162
163                         /* DW1 */
164                         __le16  datalen;
165                         __le16  mss;
166
167                         /* DW2 */
168                         __le16  pktsize;
169                         __le16  rsv2;
170
171                         /* DW3 */
172                         __le32  bufaddr;
173                 } desc1;
174                 struct {
175                         /* DW0 */
176                         __le16  rsv1;
177                         __u8    rsv2;
178                         __u8    flags;
179
180                         /* DW1 */
181                         __le16  datalen;
182                         __le16  rsv3;
183
184                         /* DW2 */
185                         __le32  bufaddrh;
186
187                         /* DW3 */
188                         __le32  bufaddrl;
189                 } desc2;
190                 struct {
191                         /* DW0 */
192                         __u8    ehdrsz;
193                         __u8    rsv1;
194                         __u8    rsv2;
195                         __u8    flags;
196
197                         /* DW1 */
198                         __le16  trycnt;
199                         __le16  segcnt;
200
201                         /* DW2 */
202                         __le16  pktsz;
203                         __le16  rsv3;
204
205                         /* DW3 */
206                         __le32  bufaddrl;
207                 } descwb;
208         };
209 };
210
211 enum jme_txdesc_flags_bits {
212         TXFLAG_OWN      = 0x80,
213         TXFLAG_INT      = 0x40,
214         TXFLAG_64BIT    = 0x20,
215         TXFLAG_TCPCS    = 0x10,
216         TXFLAG_UDPCS    = 0x08,
217         TXFLAG_IPCS     = 0x04,
218         TXFLAG_LSEN     = 0x02,
219         TXFLAG_TAGON    = 0x01,
220 };
221
222 #define TXDESC_MSS_SHIFT        2
223 enum jme_txwbdesc_flags_bits {
224         TXWBFLAG_OWN    = 0x80,
225         TXWBFLAG_INT    = 0x40,
226         TXWBFLAG_TMOUT  = 0x20,
227         TXWBFLAG_TRYOUT = 0x10,
228         TXWBFLAG_COL    = 0x08,
229
230         TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
231                           TXWBFLAG_TRYOUT |
232                           TXWBFLAG_COL,
233 };
234
235 #define RX_DESC_SIZE            16
236 #define RX_RING_NR              4
237 #define RX_RING_ALLOC_SIZE(s)   ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
238 #define RX_BUF_DMA_ALIGN        8
239 #define RX_PREPAD_SIZE          10
240 #define ETH_CRC_LEN             2
241 #define RX_VLANHDR_LEN          2
242 #define RX_EXTRA_LEN            (RX_PREPAD_SIZE + \
243                                 ETH_HLEN + \
244                                 ETH_CRC_LEN + \
245                                 RX_VLANHDR_LEN + \
246                                 RX_BUF_DMA_ALIGN)
247
248 struct rxdesc {
249         union {
250                 __u8    all[16];
251                 __le32  dw[4];
252                 struct {
253                         /* DW0 */
254                         __le16  rsv2;
255                         __u8    rsv1;
256                         __u8    flags;
257
258                         /* DW1 */
259                         __le16  datalen;
260                         __le16  wbcpl;
261
262                         /* DW2 */
263                         __le32  bufaddrh;
264
265                         /* DW3 */
266                         __le32  bufaddrl;
267                 } desc1;
268                 struct {
269                         /* DW0 */
270                         __le16  vlan;
271                         __le16  flags;
272
273                         /* DW1 */
274                         __le16  framesize;
275                         __u8    errstat;
276                         __u8    desccnt;
277
278                         /* DW2 */
279                         __le32  rsshash;
280
281                         /* DW3 */
282                         __u8    hashfun;
283                         __u8    hashtype;
284                         __le16  resrv;
285                 } descwb;
286         };
287 };
288
289 enum jme_rxdesc_flags_bits {
290         RXFLAG_OWN      = 0x80,
291         RXFLAG_INT      = 0x40,
292         RXFLAG_64BIT    = 0x20,
293 };
294
295 enum jme_rxwbdesc_flags_bits {
296         RXWBFLAG_OWN            = 0x8000,
297         RXWBFLAG_INT            = 0x4000,
298         RXWBFLAG_MF             = 0x2000,
299         RXWBFLAG_64BIT          = 0x2000,
300         RXWBFLAG_TCPON          = 0x1000,
301         RXWBFLAG_UDPON          = 0x0800,
302         RXWBFLAG_IPCS           = 0x0400,
303         RXWBFLAG_TCPCS          = 0x0200,
304         RXWBFLAG_UDPCS          = 0x0100,
305         RXWBFLAG_TAGON          = 0x0080,
306         RXWBFLAG_IPV4           = 0x0040,
307         RXWBFLAG_IPV6           = 0x0020,
308         RXWBFLAG_PAUSE          = 0x0010,
309         RXWBFLAG_MAGIC          = 0x0008,
310         RXWBFLAG_WAKEUP         = 0x0004,
311         RXWBFLAG_DEST           = 0x0003,
312         RXWBFLAG_DEST_UNI       = 0x0001,
313         RXWBFLAG_DEST_MUL       = 0x0002,
314         RXWBFLAG_DEST_BRO       = 0x0003,
315 };
316
317 enum jme_rxwbdesc_desccnt_mask {
318         RXWBDCNT_WBCPL  = 0x80,
319         RXWBDCNT_DCNT   = 0x7F,
320 };
321
322 enum jme_rxwbdesc_errstat_bits {
323         RXWBERR_LIMIT   = 0x80,
324         RXWBERR_MIIER   = 0x40,
325         RXWBERR_NIBON   = 0x20,
326         RXWBERR_COLON   = 0x10,
327         RXWBERR_ABORT   = 0x08,
328         RXWBERR_SHORT   = 0x04,
329         RXWBERR_OVERUN  = 0x02,
330         RXWBERR_CRCERR  = 0x01,
331         RXWBERR_ALLERR  = 0xFF,
332 };
333
334 /*
335  * Buffer information corresponding to ring descriptors.
336  */
337 struct jme_buffer_info {
338         struct sk_buff *skb;
339         dma_addr_t mapping;
340         int len;
341         int nr_desc;
342         unsigned long start_xmit;
343 };
344
345 /*
346  * The structure holding buffer information and ring descriptors all together.
347  */
348 struct jme_ring {
349         void *alloc;            /* pointer to allocated memory */
350         void *desc;             /* pointer to ring memory  */
351         dma_addr_t dmaalloc;    /* phys address of ring alloc */
352         dma_addr_t dma;         /* phys address for ring dma */
353
354         /* Buffer information corresponding to each descriptor */
355         struct jme_buffer_info *bufinf;
356
357         int next_to_use;
358         atomic_t next_to_clean;
359         atomic_t nr_free;
360 };
361
362 #define NET_STAT(priv) (priv->dev->stats)
363 #define NETDEV_GET_STATS(netdev, fun_ptr)
364 #define DECLARE_NET_DEVICE_STATS
365
366 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
367 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
368         netif_napi_add(dev, napis, pollfn, q);
369 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
370 #define JME_NAPI_WEIGHT(w) int w
371 #define JME_NAPI_WEIGHT_VAL(w) w
372 #define JME_NAPI_WEIGHT_SET(w, r)
373 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
374 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
375 #define JME_NAPI_DISABLE(priv) \
376         if (!napi_disable_pending(&priv->napi)) \
377                 napi_disable(&priv->napi);
378 #define JME_RX_SCHEDULE_PREP(priv) \
379         napi_schedule_prep(&priv->napi)
380 #define JME_RX_SCHEDULE(priv) \
381         __napi_schedule(&priv->napi);
382
383 /*
384  * Jmac Adapter Private data
385  */
386 struct jme_adapter {
387         struct pci_dev          *pdev;
388         struct net_device       *dev;
389         void __iomem            *regs;
390         struct mii_if_info      mii_if;
391         struct jme_ring         rxring[RX_RING_NR];
392         struct jme_ring         txring[TX_RING_NR];
393         spinlock_t              phy_lock;
394         spinlock_t              macaddr_lock;
395         spinlock_t              rxmcs_lock;
396         struct tasklet_struct   rxempty_task;
397         struct tasklet_struct   rxclean_task;
398         struct tasklet_struct   txclean_task;
399         struct tasklet_struct   linkch_task;
400         struct tasklet_struct   pcc_task;
401         unsigned long           flags;
402         u32                     reg_txcs;
403         u32                     reg_txpfc;
404         u32                     reg_rxcs;
405         u32                     reg_rxmcs;
406         u32                     reg_ghc;
407         u32                     reg_pmcs;
408         u32                     phylink;
409         u32                     tx_ring_size;
410         u32                     tx_ring_mask;
411         u32                     tx_wake_threshold;
412         u32                     rx_ring_size;
413         u32                     rx_ring_mask;
414         u8                      mrrs;
415         unsigned int            fpgaver;
416         unsigned int            chiprev;
417         u8                      rev;
418         u32                     msg_enable;
419         struct ethtool_cmd      old_ecmd;
420         unsigned int            old_mtu;
421         struct vlan_group       *vlgrp;
422         struct dynpcc_info      dpi;
423         atomic_t                intr_sem;
424         atomic_t                link_changing;
425         atomic_t                tx_cleaning;
426         atomic_t                rx_cleaning;
427         atomic_t                rx_empty;
428         int                     (*jme_rx)(struct sk_buff *skb);
429         int                     (*jme_vlan_rx)(struct sk_buff *skb,
430                                           struct vlan_group *grp,
431                                           unsigned short vlan_tag);
432         DECLARE_NAPI_STRUCT
433         DECLARE_NET_DEVICE_STATS
434 };
435
436 enum jme_flags_bits {
437         JME_FLAG_MSI            = 1,
438         JME_FLAG_SSET           = 2,
439         JME_FLAG_TXCSUM         = 3,
440         JME_FLAG_TSO            = 4,
441         JME_FLAG_POLL           = 5,
442         JME_FLAG_SHUTDOWN       = 6,
443 };
444
445 #define TX_TIMEOUT              (5 * HZ)
446 #define JME_REG_LEN             0x500
447 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
448
449 static inline struct jme_adapter*
450 jme_napi_priv(struct napi_struct *napi)
451 {
452         struct jme_adapter *jme;
453         jme = container_of(napi, struct jme_adapter, napi);
454         return jme;
455 }
456
457 /*
458  * MMaped I/O Resters
459  */
460 enum jme_iomap_offsets {
461         JME_MAC         = 0x0000,
462         JME_PHY         = 0x0400,
463         JME_MISC        = 0x0800,
464         JME_RSS         = 0x0C00,
465 };
466
467 enum jme_iomap_lens {
468         JME_MAC_LEN     = 0x80,
469         JME_PHY_LEN     = 0x58,
470         JME_MISC_LEN    = 0x98,
471         JME_RSS_LEN     = 0xFF,
472 };
473
474 enum jme_iomap_regs {
475         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
476         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
477         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
478         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
479         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
480         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
481         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
482         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
483
484         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
485         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
486         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
487         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
488         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
489         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
490         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
491         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
492         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
493         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
494         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
495         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
496
497         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
498         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
499         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
500
501
502         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
503         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
504         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
505         JME_SMBINTF     = JME_PHY | 0x44, /* SMB Interface */
506
507
508         JME_TMCSR       = JME_MISC | 0x00, /* Timer Control/Status Register */
509         JME_GPREG0      = JME_MISC | 0x08, /* General purpose REG-0 */
510         JME_GPREG1      = JME_MISC | 0x0C, /* General purpose REG-1 */
511         JME_IEVE        = JME_MISC | 0x20, /* Interrupt Event Status */
512         JME_IREQ        = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
513         JME_IENS        = JME_MISC | 0x28, /* Intr Enable - Setting Port */
514         JME_IENC        = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
515         JME_PCCRX0      = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
516         JME_PCCTX       = JME_MISC | 0x40, /* PCC Control for TX Queues */
517         JME_CHIPMODE    = JME_MISC | 0x44, /* Identify FPGA Version */
518         JME_SHBA_HI     = JME_MISC | 0x48, /* Shadow Register Base HI */
519         JME_SHBA_LO     = JME_MISC | 0x4C, /* Shadow Register Base LO */
520         JME_TIMER1      = JME_MISC | 0x70, /* Timer1 */
521         JME_TIMER2      = JME_MISC | 0x74, /* Timer2 */
522         JME_APMC        = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
523         JME_PCCSRX0     = JME_MISC | 0x80, /* PCC Status of RX0 */
524 };
525
526 /*
527  * TX Control/Status Bits
528  */
529 enum jme_txcs_bits {
530         TXCS_QUEUE7S    = 0x00008000,
531         TXCS_QUEUE6S    = 0x00004000,
532         TXCS_QUEUE5S    = 0x00002000,
533         TXCS_QUEUE4S    = 0x00001000,
534         TXCS_QUEUE3S    = 0x00000800,
535         TXCS_QUEUE2S    = 0x00000400,
536         TXCS_QUEUE1S    = 0x00000200,
537         TXCS_QUEUE0S    = 0x00000100,
538         TXCS_FIFOTH     = 0x000000C0,
539         TXCS_DMASIZE    = 0x00000030,
540         TXCS_BURST      = 0x00000004,
541         TXCS_ENABLE     = 0x00000001,
542 };
543
544 enum jme_txcs_value {
545         TXCS_FIFOTH_16QW        = 0x000000C0,
546         TXCS_FIFOTH_12QW        = 0x00000080,
547         TXCS_FIFOTH_8QW         = 0x00000040,
548         TXCS_FIFOTH_4QW         = 0x00000000,
549
550         TXCS_DMASIZE_64B        = 0x00000000,
551         TXCS_DMASIZE_128B       = 0x00000010,
552         TXCS_DMASIZE_256B       = 0x00000020,
553         TXCS_DMASIZE_512B       = 0x00000030,
554
555         TXCS_SELECT_QUEUE0      = 0x00000000,
556         TXCS_SELECT_QUEUE1      = 0x00010000,
557         TXCS_SELECT_QUEUE2      = 0x00020000,
558         TXCS_SELECT_QUEUE3      = 0x00030000,
559         TXCS_SELECT_QUEUE4      = 0x00040000,
560         TXCS_SELECT_QUEUE5      = 0x00050000,
561         TXCS_SELECT_QUEUE6      = 0x00060000,
562         TXCS_SELECT_QUEUE7      = 0x00070000,
563
564         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
565                                   TXCS_BURST,
566 };
567
568 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
569
570 /*
571  * TX MAC Control/Status Bits
572  */
573 enum jme_txmcs_bit_masks {
574         TXMCS_IFG2              = 0xC0000000,
575         TXMCS_IFG1              = 0x30000000,
576         TXMCS_TTHOLD            = 0x00000300,
577         TXMCS_FBURST            = 0x00000080,
578         TXMCS_CARRIEREXT        = 0x00000040,
579         TXMCS_DEFER             = 0x00000020,
580         TXMCS_BACKOFF           = 0x00000010,
581         TXMCS_CARRIERSENSE      = 0x00000008,
582         TXMCS_COLLISION         = 0x00000004,
583         TXMCS_CRC               = 0x00000002,
584         TXMCS_PADDING           = 0x00000001,
585 };
586
587 enum jme_txmcs_values {
588         TXMCS_IFG2_6_4          = 0x00000000,
589         TXMCS_IFG2_8_5          = 0x40000000,
590         TXMCS_IFG2_10_6         = 0x80000000,
591         TXMCS_IFG2_12_7         = 0xC0000000,
592
593         TXMCS_IFG1_8_4          = 0x00000000,
594         TXMCS_IFG1_12_6         = 0x10000000,
595         TXMCS_IFG1_16_8         = 0x20000000,
596         TXMCS_IFG1_20_10        = 0x30000000,
597
598         TXMCS_TTHOLD_1_8        = 0x00000000,
599         TXMCS_TTHOLD_1_4        = 0x00000100,
600         TXMCS_TTHOLD_1_2        = 0x00000200,
601         TXMCS_TTHOLD_FULL       = 0x00000300,
602
603         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
604                                   TXMCS_IFG1_16_8 |
605                                   TXMCS_TTHOLD_FULL |
606                                   TXMCS_DEFER |
607                                   TXMCS_CRC |
608                                   TXMCS_PADDING,
609 };
610
611 enum jme_txpfc_bits_masks {
612         TXPFC_VLAN_TAG          = 0xFFFF0000,
613         TXPFC_VLAN_EN           = 0x00008000,
614         TXPFC_PF_EN             = 0x00000001,
615 };
616
617 enum jme_txtrhd_bits_masks {
618         TXTRHD_TXPEN            = 0x80000000,
619         TXTRHD_TXP              = 0x7FFFFF00,
620         TXTRHD_TXREN            = 0x00000080,
621         TXTRHD_TXRL             = 0x0000007F,
622 };
623
624 enum jme_txtrhd_shifts {
625         TXTRHD_TXP_SHIFT        = 8,
626         TXTRHD_TXRL_SHIFT       = 0,
627 };
628
629 /*
630  * RX Control/Status Bits
631  */
632 enum jme_rxcs_bit_masks {
633         /* FIFO full threshold for transmitting Tx Pause Packet */
634         RXCS_FIFOTHTP   = 0x30000000,
635         /* FIFO threshold for processing next packet */
636         RXCS_FIFOTHNP   = 0x0C000000,
637         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
638         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
639         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
640         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
641         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
642         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
643         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
644         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
645         RXCS_QST        = 0x00000004, /* Receive queue start */
646         RXCS_SUSPEND    = 0x00000002,
647         RXCS_ENABLE     = 0x00000001,
648 };
649
650 enum jme_rxcs_values {
651         RXCS_FIFOTHTP_16T       = 0x00000000,
652         RXCS_FIFOTHTP_32T       = 0x10000000,
653         RXCS_FIFOTHTP_64T       = 0x20000000,
654         RXCS_FIFOTHTP_128T      = 0x30000000,
655
656         RXCS_FIFOTHNP_16QW      = 0x00000000,
657         RXCS_FIFOTHNP_32QW      = 0x04000000,
658         RXCS_FIFOTHNP_64QW      = 0x08000000,
659         RXCS_FIFOTHNP_128QW     = 0x0C000000,
660
661         RXCS_DMAREQSZ_16B       = 0x00000000,
662         RXCS_DMAREQSZ_32B       = 0x01000000,
663         RXCS_DMAREQSZ_64B       = 0x02000000,
664         RXCS_DMAREQSZ_128B      = 0x03000000,
665
666         RXCS_QUEUESEL_Q0        = 0x00000000,
667         RXCS_QUEUESEL_Q1        = 0x00010000,
668         RXCS_QUEUESEL_Q2        = 0x00020000,
669         RXCS_QUEUESEL_Q3        = 0x00030000,
670
671         RXCS_RETRYGAP_256ns     = 0x00000000,
672         RXCS_RETRYGAP_512ns     = 0x00001000,
673         RXCS_RETRYGAP_1024ns    = 0x00002000,
674         RXCS_RETRYGAP_2048ns    = 0x00003000,
675         RXCS_RETRYGAP_4096ns    = 0x00004000,
676         RXCS_RETRYGAP_8192ns    = 0x00005000,
677         RXCS_RETRYGAP_16384ns   = 0x00006000,
678         RXCS_RETRYGAP_32768ns   = 0x00007000,
679
680         RXCS_RETRYCNT_0         = 0x00000000,
681         RXCS_RETRYCNT_4         = 0x00000100,
682         RXCS_RETRYCNT_8         = 0x00000200,
683         RXCS_RETRYCNT_12        = 0x00000300,
684         RXCS_RETRYCNT_16        = 0x00000400,
685         RXCS_RETRYCNT_20        = 0x00000500,
686         RXCS_RETRYCNT_24        = 0x00000600,
687         RXCS_RETRYCNT_28        = 0x00000700,
688         RXCS_RETRYCNT_32        = 0x00000800,
689         RXCS_RETRYCNT_36        = 0x00000900,
690         RXCS_RETRYCNT_40        = 0x00000A00,
691         RXCS_RETRYCNT_44        = 0x00000B00,
692         RXCS_RETRYCNT_48        = 0x00000C00,
693         RXCS_RETRYCNT_52        = 0x00000D00,
694         RXCS_RETRYCNT_56        = 0x00000E00,
695         RXCS_RETRYCNT_60        = 0x00000F00,
696
697         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
698                                   RXCS_FIFOTHNP_128QW |
699                                   RXCS_DMAREQSZ_128B |
700                                   RXCS_RETRYGAP_256ns |
701                                   RXCS_RETRYCNT_32,
702 };
703
704 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
705
706 /*
707  * RX MAC Control/Status Bits
708  */
709 enum jme_rxmcs_bits {
710         RXMCS_ALLFRAME          = 0x00000800,
711         RXMCS_BRDFRAME          = 0x00000400,
712         RXMCS_MULFRAME          = 0x00000200,
713         RXMCS_UNIFRAME          = 0x00000100,
714         RXMCS_ALLMULFRAME       = 0x00000080,
715         RXMCS_MULFILTERED       = 0x00000040,
716         RXMCS_RXCOLLDEC         = 0x00000020,
717         RXMCS_FLOWCTRL          = 0x00000008,
718         RXMCS_VTAGRM            = 0x00000004,
719         RXMCS_PREPAD            = 0x00000002,
720         RXMCS_CHECKSUM          = 0x00000001,
721
722         RXMCS_DEFAULT           = RXMCS_VTAGRM |
723                                   RXMCS_PREPAD |
724                                   RXMCS_FLOWCTRL |
725                                   RXMCS_CHECKSUM,
726 };
727
728 /*
729  * Wakeup Frame setup interface registers
730  */
731 #define WAKEUP_FRAME_NR 8
732 #define WAKEUP_FRAME_MASK_DWNR  4
733
734 enum jme_wfoi_bit_masks {
735         WFOI_MASK_SEL           = 0x00000070,
736         WFOI_CRC_SEL            = 0x00000008,
737         WFOI_FRAME_SEL          = 0x00000007,
738 };
739
740 enum jme_wfoi_shifts {
741         WFOI_MASK_SHIFT         = 4,
742 };
743
744 /*
745  * SMI Related definitions
746  */
747 enum jme_smi_bit_mask {
748         SMI_DATA_MASK           = 0xFFFF0000,
749         SMI_REG_ADDR_MASK       = 0x0000F800,
750         SMI_PHY_ADDR_MASK       = 0x000007C0,
751         SMI_OP_WRITE            = 0x00000020,
752         /* Set to 1, after req done it'll be cleared to 0 */
753         SMI_OP_REQ              = 0x00000010,
754         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
755         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
756         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
757         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
758 };
759
760 enum jme_smi_bit_shift {
761         SMI_DATA_SHIFT          = 16,
762         SMI_REG_ADDR_SHIFT      = 11,
763         SMI_PHY_ADDR_SHIFT      = 6,
764 };
765
766 static inline u32 smi_reg_addr(int x)
767 {
768         return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
769 }
770
771 static inline u32 smi_phy_addr(int x)
772 {
773         return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
774 }
775
776 #define JME_PHY_TIMEOUT 100 /* 100 msec */
777 #define JME_PHY_REG_NR 32
778
779 /*
780  * Global Host Control
781  */
782 enum jme_ghc_bit_mask {
783         GHC_SWRST               = 0x40000000,
784         GHC_DPX                 = 0x00000040,
785         GHC_SPEED               = 0x00000030,
786         GHC_LINK_POLL           = 0x00000001,
787 };
788
789 enum jme_ghc_speed_val {
790         GHC_SPEED_10M           = 0x00000010,
791         GHC_SPEED_100M          = 0x00000020,
792         GHC_SPEED_1000M         = 0x00000030,
793 };
794
795 enum jme_ghc_to_clk {
796         GHC_TO_CLK_OFF          = 0x00000000,
797         GHC_TO_CLK_GPHY         = 0x00400000,
798         GHC_TO_CLK_PCIE         = 0x00800000,
799         GHC_TO_CLK_INVALID      = 0x00C00000,
800 };
801
802 enum jme_ghc_txmac_clk {
803         GHC_TXMAC_CLK_OFF       = 0x00000000,
804         GHC_TXMAC_CLK_GPHY      = 0x00100000,
805         GHC_TXMAC_CLK_PCIE      = 0x00200000,
806         GHC_TXMAC_CLK_INVALID   = 0x00300000,
807 };
808
809 /*
810  * Power management control and status register
811  */
812 enum jme_pmcs_bit_masks {
813         PMCS_WF7DET     = 0x80000000,
814         PMCS_WF6DET     = 0x40000000,
815         PMCS_WF5DET     = 0x20000000,
816         PMCS_WF4DET     = 0x10000000,
817         PMCS_WF3DET     = 0x08000000,
818         PMCS_WF2DET     = 0x04000000,
819         PMCS_WF1DET     = 0x02000000,
820         PMCS_WF0DET     = 0x01000000,
821         PMCS_LFDET      = 0x00040000,
822         PMCS_LRDET      = 0x00020000,
823         PMCS_MFDET      = 0x00010000,
824         PMCS_WF7EN      = 0x00008000,
825         PMCS_WF6EN      = 0x00004000,
826         PMCS_WF5EN      = 0x00002000,
827         PMCS_WF4EN      = 0x00001000,
828         PMCS_WF3EN      = 0x00000800,
829         PMCS_WF2EN      = 0x00000400,
830         PMCS_WF1EN      = 0x00000200,
831         PMCS_WF0EN      = 0x00000100,
832         PMCS_LFEN       = 0x00000004,
833         PMCS_LREN       = 0x00000002,
834         PMCS_MFEN       = 0x00000001,
835 };
836
837 /*
838  * Giga PHY Status Registers
839  */
840 enum jme_phy_link_bit_mask {
841         PHY_LINK_SPEED_MASK             = 0x0000C000,
842         PHY_LINK_DUPLEX                 = 0x00002000,
843         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
844         PHY_LINK_UP                     = 0x00000400,
845         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
846         PHY_LINK_MDI_STAT               = 0x00000040,
847 };
848
849 enum jme_phy_link_speed_val {
850         PHY_LINK_SPEED_10M              = 0x00000000,
851         PHY_LINK_SPEED_100M             = 0x00004000,
852         PHY_LINK_SPEED_1000M            = 0x00008000,
853 };
854
855 #define JME_SPDRSV_TIMEOUT      500     /* 500 us */
856
857 /*
858  * SMB Control and Status
859  */
860 enum jme_smbcsr_bit_mask {
861         SMBCSR_CNACK    = 0x00020000,
862         SMBCSR_RELOAD   = 0x00010000,
863         SMBCSR_EEPROMD  = 0x00000020,
864         SMBCSR_INITDONE = 0x00000010,
865         SMBCSR_BUSY     = 0x0000000F,
866 };
867
868 enum jme_smbintf_bit_mask {
869         SMBINTF_HWDATR  = 0xFF000000,
870         SMBINTF_HWDATW  = 0x00FF0000,
871         SMBINTF_HWADDR  = 0x0000FF00,
872         SMBINTF_HWRWN   = 0x00000020,
873         SMBINTF_HWCMD   = 0x00000010,
874         SMBINTF_FASTM   = 0x00000008,
875         SMBINTF_GPIOSCL = 0x00000004,
876         SMBINTF_GPIOSDA = 0x00000002,
877         SMBINTF_GPIOEN  = 0x00000001,
878 };
879
880 enum jme_smbintf_vals {
881         SMBINTF_HWRWN_READ      = 0x00000020,
882         SMBINTF_HWRWN_WRITE     = 0x00000000,
883 };
884
885 enum jme_smbintf_shifts {
886         SMBINTF_HWDATR_SHIFT    = 24,
887         SMBINTF_HWDATW_SHIFT    = 16,
888         SMBINTF_HWADDR_SHIFT    = 8,
889 };
890
891 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
892 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
893 #define JME_SMB_LEN 256
894 #define JME_EEPROM_MAGIC 0x250
895
896 /*
897  * Timer Control/Status Register
898  */
899 enum jme_tmcsr_bit_masks {
900         TMCSR_SWIT      = 0x80000000,
901         TMCSR_EN        = 0x01000000,
902         TMCSR_CNT       = 0x00FFFFFF,
903 };
904
905 /*
906  * General Purpose REG-0
907  */
908 enum jme_gpreg0_masks {
909         GPREG0_DISSH            = 0xFF000000,
910         GPREG0_PCIRLMT          = 0x00300000,
911         GPREG0_PCCNOMUTCLR      = 0x00040000,
912         GPREG0_LNKINTPOLL       = 0x00001000,
913         GPREG0_PCCTMR           = 0x00000300,
914         GPREG0_PHYADDR          = 0x0000001F,
915 };
916
917 enum jme_gpreg0_vals {
918         GPREG0_DISSH_DW7        = 0x80000000,
919         GPREG0_DISSH_DW6        = 0x40000000,
920         GPREG0_DISSH_DW5        = 0x20000000,
921         GPREG0_DISSH_DW4        = 0x10000000,
922         GPREG0_DISSH_DW3        = 0x08000000,
923         GPREG0_DISSH_DW2        = 0x04000000,
924         GPREG0_DISSH_DW1        = 0x02000000,
925         GPREG0_DISSH_DW0        = 0x01000000,
926         GPREG0_DISSH_ALL        = 0xFF000000,
927
928         GPREG0_PCIRLMT_8        = 0x00000000,
929         GPREG0_PCIRLMT_6        = 0x00100000,
930         GPREG0_PCIRLMT_5        = 0x00200000,
931         GPREG0_PCIRLMT_4        = 0x00300000,
932
933         GPREG0_PCCTMR_16ns      = 0x00000000,
934         GPREG0_PCCTMR_256ns     = 0x00000100,
935         GPREG0_PCCTMR_1us       = 0x00000200,
936         GPREG0_PCCTMR_1ms       = 0x00000300,
937
938         GPREG0_PHYADDR_1        = 0x00000001,
939
940         GPREG0_DEFAULT          = GPREG0_PCIRLMT_4 |
941                                   GPREG0_PCCTMR_1us |
942                                   GPREG0_PHYADDR_1,
943 };
944
945 /*
946  * General Purpose REG-1
947  * Note: All theses bits defined here are for
948  *       Chip mode revision 0x11 only
949  */
950 enum jme_gpreg1_masks {
951         GPREG1_INTRDELAYUNIT    = 0x00000018,
952         GPREG1_INTRDELAYENABLE  = 0x00000007,
953 };
954
955 enum jme_gpreg1_vals {
956         GPREG1_RSSPATCH         = 0x00000040,
957         GPREG1_HALFMODEPATCH    = 0x00000020,
958
959         GPREG1_INTDLYUNIT_16NS  = 0x00000000,
960         GPREG1_INTDLYUNIT_256NS = 0x00000008,
961         GPREG1_INTDLYUNIT_1US   = 0x00000010,
962         GPREG1_INTDLYUNIT_16US  = 0x00000018,
963
964         GPREG1_INTDLYEN_1U      = 0x00000001,
965         GPREG1_INTDLYEN_2U      = 0x00000002,
966         GPREG1_INTDLYEN_3U      = 0x00000003,
967         GPREG1_INTDLYEN_4U      = 0x00000004,
968         GPREG1_INTDLYEN_5U      = 0x00000005,
969         GPREG1_INTDLYEN_6U      = 0x00000006,
970         GPREG1_INTDLYEN_7U      = 0x00000007,
971
972         GPREG1_DEFAULT          = 0x00000000,
973 };
974
975 /*
976  * Interrupt Status Bits
977  */
978 enum jme_interrupt_bits {
979         INTR_SWINTR     = 0x80000000,
980         INTR_TMINTR     = 0x40000000,
981         INTR_LINKCH     = 0x20000000,
982         INTR_PAUSERCV   = 0x10000000,
983         INTR_MAGICRCV   = 0x08000000,
984         INTR_WAKERCV    = 0x04000000,
985         INTR_PCCRX0TO   = 0x02000000,
986         INTR_PCCRX1TO   = 0x01000000,
987         INTR_PCCRX2TO   = 0x00800000,
988         INTR_PCCRX3TO   = 0x00400000,
989         INTR_PCCTXTO    = 0x00200000,
990         INTR_PCCRX0     = 0x00100000,
991         INTR_PCCRX1     = 0x00080000,
992         INTR_PCCRX2     = 0x00040000,
993         INTR_PCCRX3     = 0x00020000,
994         INTR_PCCTX      = 0x00010000,
995         INTR_RX3EMP     = 0x00008000,
996         INTR_RX2EMP     = 0x00004000,
997         INTR_RX1EMP     = 0x00002000,
998         INTR_RX0EMP     = 0x00001000,
999         INTR_RX3        = 0x00000800,
1000         INTR_RX2        = 0x00000400,
1001         INTR_RX1        = 0x00000200,
1002         INTR_RX0        = 0x00000100,
1003         INTR_TX7        = 0x00000080,
1004         INTR_TX6        = 0x00000040,
1005         INTR_TX5        = 0x00000020,
1006         INTR_TX4        = 0x00000010,
1007         INTR_TX3        = 0x00000008,
1008         INTR_TX2        = 0x00000004,
1009         INTR_TX1        = 0x00000002,
1010         INTR_TX0        = 0x00000001,
1011 };
1012
1013 static const u32 INTR_ENABLE = INTR_SWINTR |
1014                                  INTR_TMINTR |
1015                                  INTR_LINKCH |
1016                                  INTR_PCCRX0TO |
1017                                  INTR_PCCRX0 |
1018                                  INTR_PCCTXTO |
1019                                  INTR_PCCTX |
1020                                  INTR_RX0EMP;
1021
1022 /*
1023  * PCC Control Registers
1024  */
1025 enum jme_pccrx_masks {
1026         PCCRXTO_MASK    = 0xFFFF0000,
1027         PCCRX_MASK      = 0x0000FF00,
1028 };
1029
1030 enum jme_pcctx_masks {
1031         PCCTXTO_MASK    = 0xFFFF0000,
1032         PCCTX_MASK      = 0x0000FF00,
1033         PCCTX_QS_MASK   = 0x000000FF,
1034 };
1035
1036 enum jme_pccrx_shifts {
1037         PCCRXTO_SHIFT   = 16,
1038         PCCRX_SHIFT     = 8,
1039 };
1040
1041 enum jme_pcctx_shifts {
1042         PCCTXTO_SHIFT   = 16,
1043         PCCTX_SHIFT     = 8,
1044 };
1045
1046 enum jme_pcctx_bits {
1047         PCCTXQ0_EN      = 0x00000001,
1048         PCCTXQ1_EN      = 0x00000002,
1049         PCCTXQ2_EN      = 0x00000004,
1050         PCCTXQ3_EN      = 0x00000008,
1051         PCCTXQ4_EN      = 0x00000010,
1052         PCCTXQ5_EN      = 0x00000020,
1053         PCCTXQ6_EN      = 0x00000040,
1054         PCCTXQ7_EN      = 0x00000080,
1055 };
1056
1057 /*
1058  * Chip Mode Register
1059  */
1060 enum jme_chipmode_bit_masks {
1061         CM_FPGAVER_MASK         = 0xFFFF0000,
1062         CM_CHIPREV_MASK         = 0x0000FF00,
1063         CM_CHIPMODE_MASK        = 0x0000000F,
1064 };
1065
1066 enum jme_chipmode_shifts {
1067         CM_FPGAVER_SHIFT        = 16,
1068         CM_CHIPREV_SHIFT        = 8,
1069 };
1070
1071 /*
1072  * Aggressive Power Mode Control
1073  */
1074 enum jme_apmc_bits {
1075         JME_APMC_PCIE_SD_EN     = 0x40000000,
1076         JME_APMC_PSEUDO_HP_EN   = 0x20000000,
1077         JME_APMC_EPIEN          = 0x04000000,
1078         JME_APMC_EPIEN_CTRL     = 0x03000000,
1079 };
1080
1081 enum jme_apmc_values {
1082         JME_APMC_EPIEN_CTRL_EN  = 0x02000000,
1083         JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1084 };
1085
1086 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1087
1088 #ifdef REG_DEBUG
1089 static char *MAC_REG_NAME[] = {
1090         "JME_TXCS",      "JME_TXDBA_LO",  "JME_TXDBA_HI", "JME_TXQDC",
1091         "JME_TXNDA",     "JME_TXMCS",     "JME_TXPFC",    "JME_TXTRHD",
1092         "JME_RXCS",      "JME_RXDBA_LO",  "JME_RXDBA_HI", "JME_RXQDC",
1093         "JME_RXNDA",     "JME_RXMCS",     "JME_RXUMA_LO", "JME_RXUMA_HI",
1094         "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP",    "JME_WFOI",
1095         "JME_SMI",       "JME_GHC",       "UNKNOWN",      "UNKNOWN",
1096         "JME_PMCS"};
1097
1098 static char *PE_REG_NAME[] = {
1099         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1100         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1101         "UNKNOWN",      "UNKNOWN",     "JME_PHY_CS", "UNKNOWN",
1102         "JME_PHY_LINK", "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1103         "JME_SMBCSR",   "JME_SMBINTF"};
1104
1105 static char *MISC_REG_NAME[] = {
1106         "JME_TMCSR",  "JME_GPIO",     "JME_GPREG0",  "JME_GPREG1",
1107         "JME_IEVE",   "JME_IREQ",     "JME_IENS",    "JME_IENC",
1108         "JME_PCCRX0", "JME_PCCRX1",   "JME_PCCRX2",  "JME_PCCRX3",
1109         "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1110         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1111         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1112         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1113         "JME_TIMER1", "JME_TIMER2",   "UNKNOWN",     "JME_APMC",
1114         "JME_PCCSRX0"};
1115
1116 static inline void reg_dbg(const struct jme_adapter *jme,
1117                 const char *msg, u32 val, u32 reg)
1118 {
1119         const char *regname;
1120         switch (reg & 0xF00) {
1121         case 0x000:
1122                 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1123                 break;
1124         case 0x400:
1125                 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1126                 break;
1127         case 0x800:
1128                 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1129                 break;
1130         default:
1131                 regname = PE_REG_NAME[0];
1132         }
1133         printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1134                         msg, val, regname);
1135 }
1136 #else
1137 static inline void reg_dbg(const struct jme_adapter *jme,
1138                 const char *msg, u32 val, u32 reg) {}
1139 #endif
1140
1141 /*
1142  * Read/Write MMaped I/O Registers
1143  */
1144 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1145 {
1146         return readl(jme->regs + reg);
1147 }
1148
1149 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1150 {
1151         reg_dbg(jme, "REG WRITE", val, reg);
1152         writel(val, jme->regs + reg);
1153         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1154 }
1155
1156 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1157 {
1158         /*
1159          * Read after write should cause flush
1160          */
1161         reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1162         writel(val, jme->regs + reg);
1163         readl(jme->regs + reg);
1164         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1165 }
1166
1167 /*
1168  * PHY Regs
1169  */
1170 enum jme_phy_reg17_bit_masks {
1171         PREG17_SPEED            = 0xC000,
1172         PREG17_DUPLEX           = 0x2000,
1173         PREG17_SPDRSV           = 0x0800,
1174         PREG17_LNKUP            = 0x0400,
1175         PREG17_MDI              = 0x0040,
1176 };
1177
1178 enum jme_phy_reg17_vals {
1179         PREG17_SPEED_10M        = 0x0000,
1180         PREG17_SPEED_100M       = 0x4000,
1181         PREG17_SPEED_1000M      = 0x8000,
1182 };
1183
1184 #define BMSR_ANCOMP               0x0020
1185
1186 /*
1187  * Workaround
1188  */
1189 static inline int is_buggy250(unsigned short device, unsigned int chiprev)
1190 {
1191         return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1192 }
1193
1194 /*
1195  * Function prototypes
1196  */
1197 static int jme_set_settings(struct net_device *netdev,
1198                                 struct ethtool_cmd *ecmd);
1199 static void jme_set_multi(struct net_device *netdev);
1200
1201 #endif