bitops: rename for_each_bit() to for_each_set_bit()
[linux-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3   Intel 10 Gigabit PCI Express Linux driver
4   Copyright(c) 1999 - 2010 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <scsi/fc/fc_fcoe.h>
44
45 #include "ixgbe.h"
46 #include "ixgbe_common.h"
47 #include "ixgbe_dcb_82599.h"
48 #include "ixgbe_sriov.h"
49
50 char ixgbe_driver_name[] = "ixgbe";
51 static const char ixgbe_driver_string[] =
52                               "Intel(R) 10 Gigabit PCI Express Network Driver";
53
54 #define DRV_VERSION "2.0.62-k2"
55 const char ixgbe_driver_version[] = DRV_VERSION;
56 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
57
58 static const struct ixgbe_info *ixgbe_info_tbl[] = {
59         [board_82598] = &ixgbe_82598_info,
60         [board_82599] = &ixgbe_82599_info,
61 };
62
63 /* ixgbe_pci_tbl - PCI Device ID Table
64  *
65  * Wildcard entries (PCI_ANY_ID) should come last
66  * Last entry must be all 0s
67  *
68  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
69  *   Class, Class Mask, private data (not used) }
70  */
71 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
72         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
73          board_82598 },
74         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
75          board_82598 },
76         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
77          board_82598 },
78         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
79          board_82598 },
80         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
81          board_82598 },
82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
83          board_82598 },
84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
85          board_82598 },
86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
87          board_82598 },
88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
89          board_82598 },
90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
91          board_82598 },
92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
93          board_82598 },
94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
95          board_82598 },
96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
97          board_82599 },
98         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
99          board_82599 },
100         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
101          board_82599 },
102         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
103          board_82599 },
104         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
105          board_82599 },
106         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
107          board_82599 },
108         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
109          board_82599 },
110         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
111          board_82599 },
112
113         /* required last entry */
114         {0, }
115 };
116 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
117
118 #ifdef CONFIG_IXGBE_DCA
119 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
120                             void *p);
121 static struct notifier_block dca_notifier = {
122         .notifier_call = ixgbe_notify_dca,
123         .next          = NULL,
124         .priority      = 0
125 };
126 #endif
127
128 #ifdef CONFIG_PCI_IOV
129 static unsigned int max_vfs;
130 module_param(max_vfs, uint, 0);
131 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
132                  "per physical function");
133 #endif /* CONFIG_PCI_IOV */
134
135 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
136 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
137 MODULE_LICENSE("GPL");
138 MODULE_VERSION(DRV_VERSION);
139
140 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
141
142 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
143 {
144         struct ixgbe_hw *hw = &adapter->hw;
145         u32 gcr;
146         u32 gpie;
147         u32 vmdctl;
148
149 #ifdef CONFIG_PCI_IOV
150         /* disable iov and allow time for transactions to clear */
151         pci_disable_sriov(adapter->pdev);
152 #endif
153
154         /* turn off device IOV mode */
155         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
156         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
157         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
158         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
159         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
160         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
161
162         /* set default pool back to 0 */
163         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
164         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
165         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
166
167         /* take a breather then clean up driver data */
168         msleep(100);
169         if (adapter->vfinfo)
170                 kfree(adapter->vfinfo);
171         adapter->vfinfo = NULL;
172
173         adapter->num_vfs = 0;
174         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
175 }
176
177 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
178 {
179         u32 ctrl_ext;
180
181         /* Let firmware take over control of h/w */
182         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
183         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
184                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
185 }
186
187 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
188 {
189         u32 ctrl_ext;
190
191         /* Let firmware know the driver has taken over */
192         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
193         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
194                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
195 }
196
197 /*
198  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
199  * @adapter: pointer to adapter struct
200  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
201  * @queue: queue to map the corresponding interrupt to
202  * @msix_vector: the vector to map to the corresponding queue
203  *
204  */
205 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
206                            u8 queue, u8 msix_vector)
207 {
208         u32 ivar, index;
209         struct ixgbe_hw *hw = &adapter->hw;
210         switch (hw->mac.type) {
211         case ixgbe_mac_82598EB:
212                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
213                 if (direction == -1)
214                         direction = 0;
215                 index = (((direction * 64) + queue) >> 2) & 0x1F;
216                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
217                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
218                 ivar |= (msix_vector << (8 * (queue & 0x3)));
219                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
220                 break;
221         case ixgbe_mac_82599EB:
222                 if (direction == -1) {
223                         /* other causes */
224                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
225                         index = ((queue & 1) * 8);
226                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
227                         ivar &= ~(0xFF << index);
228                         ivar |= (msix_vector << index);
229                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
230                         break;
231                 } else {
232                         /* tx or rx causes */
233                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
234                         index = ((16 * (queue & 1)) + (8 * direction));
235                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
236                         ivar &= ~(0xFF << index);
237                         ivar |= (msix_vector << index);
238                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
239                         break;
240                 }
241         default:
242                 break;
243         }
244 }
245
246 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
247                                           u64 qmask)
248 {
249         u32 mask;
250
251         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
252                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
253                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
254         } else {
255                 mask = (qmask & 0xFFFFFFFF);
256                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
257                 mask = (qmask >> 32);
258                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
259         }
260 }
261
262 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
263                                              struct ixgbe_tx_buffer
264                                              *tx_buffer_info)
265 {
266         if (tx_buffer_info->dma) {
267                 if (tx_buffer_info->mapped_as_page)
268                         pci_unmap_page(adapter->pdev,
269                                        tx_buffer_info->dma,
270                                        tx_buffer_info->length,
271                                        PCI_DMA_TODEVICE);
272                 else
273                         pci_unmap_single(adapter->pdev,
274                                          tx_buffer_info->dma,
275                                          tx_buffer_info->length,
276                                          PCI_DMA_TODEVICE);
277                 tx_buffer_info->dma = 0;
278         }
279         if (tx_buffer_info->skb) {
280                 dev_kfree_skb_any(tx_buffer_info->skb);
281                 tx_buffer_info->skb = NULL;
282         }
283         tx_buffer_info->time_stamp = 0;
284         /* tx_buffer_info must be completely set up in the transmit path */
285 }
286
287 /**
288  * ixgbe_tx_is_paused - check if the tx ring is paused
289  * @adapter: the ixgbe adapter
290  * @tx_ring: the corresponding tx_ring
291  *
292  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
293  * corresponding TC of this tx_ring when checking TFCS.
294  *
295  * Returns : true if paused
296  */
297 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
298                                       struct ixgbe_ring *tx_ring)
299 {
300         u32 txoff = IXGBE_TFCS_TXOFF;
301
302 #ifdef CONFIG_IXGBE_DCB
303         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
304                 int tc;
305                 int reg_idx = tx_ring->reg_idx;
306                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
307
308                 switch (adapter->hw.mac.type) {
309                 case ixgbe_mac_82598EB:
310                         tc = reg_idx >> 2;
311                         txoff = IXGBE_TFCS_TXOFF0;
312                         break;
313                 case ixgbe_mac_82599EB:
314                         tc = 0;
315                         txoff = IXGBE_TFCS_TXOFF;
316                         if (dcb_i == 8) {
317                                 /* TC0, TC1 */
318                                 tc = reg_idx >> 5;
319                                 if (tc == 2) /* TC2, TC3 */
320                                         tc += (reg_idx - 64) >> 4;
321                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
322                                         tc += 1 + ((reg_idx - 96) >> 3);
323                         } else if (dcb_i == 4) {
324                                 /* TC0, TC1 */
325                                 tc = reg_idx >> 6;
326                                 if (tc == 1) {
327                                         tc += (reg_idx - 64) >> 5;
328                                         if (tc == 2) /* TC2, TC3 */
329                                                 tc += (reg_idx - 96) >> 4;
330                                 }
331                         }
332                         break;
333                 default:
334                         tc = 0;
335                 }
336                 txoff <<= tc;
337         }
338 #endif
339         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
340 }
341
342 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
343                                        struct ixgbe_ring *tx_ring,
344                                        unsigned int eop)
345 {
346         struct ixgbe_hw *hw = &adapter->hw;
347
348         /* Detect a transmit hang in hardware, this serializes the
349          * check with the clearing of time_stamp and movement of eop */
350         adapter->detect_tx_hung = false;
351         if (tx_ring->tx_buffer_info[eop].time_stamp &&
352             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
353             !ixgbe_tx_is_paused(adapter, tx_ring)) {
354                 /* detected Tx unit hang */
355                 union ixgbe_adv_tx_desc *tx_desc;
356                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
357                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
358                         "  Tx Queue             <%d>\n"
359                         "  TDH, TDT             <%x>, <%x>\n"
360                         "  next_to_use          <%x>\n"
361                         "  next_to_clean        <%x>\n"
362                         "tx_buffer_info[next_to_clean]\n"
363                         "  time_stamp           <%lx>\n"
364                         "  jiffies              <%lx>\n",
365                         tx_ring->queue_index,
366                         IXGBE_READ_REG(hw, tx_ring->head),
367                         IXGBE_READ_REG(hw, tx_ring->tail),
368                         tx_ring->next_to_use, eop,
369                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
370                 return true;
371         }
372
373         return false;
374 }
375
376 #define IXGBE_MAX_TXD_PWR       14
377 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
378
379 /* Tx Descriptors needed, worst case */
380 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
381                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
382 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
383         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
384
385 static void ixgbe_tx_timeout(struct net_device *netdev);
386
387 /**
388  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
389  * @q_vector: structure containing interrupt and ring information
390  * @tx_ring: tx ring to clean
391  **/
392 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
393                                struct ixgbe_ring *tx_ring)
394 {
395         struct ixgbe_adapter *adapter = q_vector->adapter;
396         struct net_device *netdev = adapter->netdev;
397         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
398         struct ixgbe_tx_buffer *tx_buffer_info;
399         unsigned int i, eop, count = 0;
400         unsigned int total_bytes = 0, total_packets = 0;
401
402         i = tx_ring->next_to_clean;
403         eop = tx_ring->tx_buffer_info[i].next_to_watch;
404         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
405
406         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
407                (count < tx_ring->work_limit)) {
408                 bool cleaned = false;
409                 for ( ; !cleaned; count++) {
410                         struct sk_buff *skb;
411                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
412                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
413                         cleaned = (i == eop);
414                         skb = tx_buffer_info->skb;
415
416                         if (cleaned && skb) {
417                                 unsigned int segs, bytecount;
418                                 unsigned int hlen = skb_headlen(skb);
419
420                                 /* gso_segs is currently only valid for tcp */
421                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
422 #ifdef IXGBE_FCOE
423                                 /* adjust for FCoE Sequence Offload */
424                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
425                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
426                                     skb_is_gso(skb)) {
427                                         hlen = skb_transport_offset(skb) +
428                                                 sizeof(struct fc_frame_header) +
429                                                 sizeof(struct fcoe_crc_eof);
430                                         segs = DIV_ROUND_UP(skb->len - hlen,
431                                                 skb_shinfo(skb)->gso_size);
432                                 }
433 #endif /* IXGBE_FCOE */
434                                 /* multiply data chunks by size of headers */
435                                 bytecount = ((segs - 1) * hlen) + skb->len;
436                                 total_packets += segs;
437                                 total_bytes += bytecount;
438                         }
439
440                         ixgbe_unmap_and_free_tx_resource(adapter,
441                                                          tx_buffer_info);
442
443                         tx_desc->wb.status = 0;
444
445                         i++;
446                         if (i == tx_ring->count)
447                                 i = 0;
448                 }
449
450                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
451                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
452         }
453
454         tx_ring->next_to_clean = i;
455
456 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
457         if (unlikely(count && netif_carrier_ok(netdev) &&
458                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
459                 /* Make sure that anybody stopping the queue after this
460                  * sees the new next_to_clean.
461                  */
462                 smp_mb();
463                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
464                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
465                         netif_wake_subqueue(netdev, tx_ring->queue_index);
466                         ++tx_ring->restart_queue;
467                 }
468         }
469
470         if (adapter->detect_tx_hung) {
471                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
472                         /* schedule immediate reset if we believe we hung */
473                         DPRINTK(PROBE, INFO,
474                                 "tx hang %d detected, resetting adapter\n",
475                                 adapter->tx_timeout_count + 1);
476                         ixgbe_tx_timeout(adapter->netdev);
477                 }
478         }
479
480         /* re-arm the interrupt */
481         if (count >= tx_ring->work_limit)
482                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
483
484         tx_ring->total_bytes += total_bytes;
485         tx_ring->total_packets += total_packets;
486         tx_ring->stats.packets += total_packets;
487         tx_ring->stats.bytes += total_bytes;
488         return (count < tx_ring->work_limit);
489 }
490
491 #ifdef CONFIG_IXGBE_DCA
492 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
493                                 struct ixgbe_ring *rx_ring)
494 {
495         u32 rxctrl;
496         int cpu = get_cpu();
497         int q = rx_ring->reg_idx;
498
499         if (rx_ring->cpu != cpu) {
500                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
501                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
502                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
503                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
504                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
505                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
506                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
507                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
508                 }
509                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
510                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
511                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
512                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
513                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
514                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
515                 rx_ring->cpu = cpu;
516         }
517         put_cpu();
518 }
519
520 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
521                                 struct ixgbe_ring *tx_ring)
522 {
523         u32 txctrl;
524         int cpu = get_cpu();
525         int q = tx_ring->reg_idx;
526         struct ixgbe_hw *hw = &adapter->hw;
527
528         if (tx_ring->cpu != cpu) {
529                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
530                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
531                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
532                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
533                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
534                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
535                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
536                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
537                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
538                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
539                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
540                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
541                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
542                 }
543                 tx_ring->cpu = cpu;
544         }
545         put_cpu();
546 }
547
548 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
549 {
550         int i;
551
552         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
553                 return;
554
555         /* always use CB2 mode, difference is masked in the CB driver */
556         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
557
558         for (i = 0; i < adapter->num_tx_queues; i++) {
559                 adapter->tx_ring[i]->cpu = -1;
560                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
561         }
562         for (i = 0; i < adapter->num_rx_queues; i++) {
563                 adapter->rx_ring[i]->cpu = -1;
564                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
565         }
566 }
567
568 static int __ixgbe_notify_dca(struct device *dev, void *data)
569 {
570         struct net_device *netdev = dev_get_drvdata(dev);
571         struct ixgbe_adapter *adapter = netdev_priv(netdev);
572         unsigned long event = *(unsigned long *)data;
573
574         switch (event) {
575         case DCA_PROVIDER_ADD:
576                 /* if we're already enabled, don't do it again */
577                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
578                         break;
579                 if (dca_add_requester(dev) == 0) {
580                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
581                         ixgbe_setup_dca(adapter);
582                         break;
583                 }
584                 /* Fall Through since DCA is disabled. */
585         case DCA_PROVIDER_REMOVE:
586                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
587                         dca_remove_requester(dev);
588                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
589                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
590                 }
591                 break;
592         }
593
594         return 0;
595 }
596
597 #endif /* CONFIG_IXGBE_DCA */
598 /**
599  * ixgbe_receive_skb - Send a completed packet up the stack
600  * @adapter: board private structure
601  * @skb: packet to send up
602  * @status: hardware indication of status of receive
603  * @rx_ring: rx descriptor ring (for a specific queue) to setup
604  * @rx_desc: rx descriptor
605  **/
606 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
607                               struct sk_buff *skb, u8 status,
608                               struct ixgbe_ring *ring,
609                               union ixgbe_adv_rx_desc *rx_desc)
610 {
611         struct ixgbe_adapter *adapter = q_vector->adapter;
612         struct napi_struct *napi = &q_vector->napi;
613         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
614         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
615
616         skb_record_rx_queue(skb, ring->queue_index);
617         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
618                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
619                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
620                 else
621                         napi_gro_receive(napi, skb);
622         } else {
623                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
624                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
625                 else
626                         netif_rx(skb);
627         }
628 }
629
630 /**
631  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
632  * @adapter: address of board private structure
633  * @status_err: hardware indication of status of receive
634  * @skb: skb currently being received and modified
635  **/
636 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
637                                      union ixgbe_adv_rx_desc *rx_desc,
638                                      struct sk_buff *skb)
639 {
640         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
641
642         skb->ip_summed = CHECKSUM_NONE;
643
644         /* Rx csum disabled */
645         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
646                 return;
647
648         /* if IP and error */
649         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
650             (status_err & IXGBE_RXDADV_ERR_IPE)) {
651                 adapter->hw_csum_rx_error++;
652                 return;
653         }
654
655         if (!(status_err & IXGBE_RXD_STAT_L4CS))
656                 return;
657
658         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
659                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
660
661                 /*
662                  * 82599 errata, UDP frames with a 0 checksum can be marked as
663                  * checksum errors.
664                  */
665                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
666                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
667                         return;
668
669                 adapter->hw_csum_rx_error++;
670                 return;
671         }
672
673         /* It must be a TCP or UDP packet with a valid checksum */
674         skb->ip_summed = CHECKSUM_UNNECESSARY;
675 }
676
677 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
678                                          struct ixgbe_ring *rx_ring, u32 val)
679 {
680         /*
681          * Force memory writes to complete before letting h/w
682          * know there are new descriptors to fetch.  (Only
683          * applicable for weak-ordered memory model archs,
684          * such as IA-64).
685          */
686         wmb();
687         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
688 }
689
690 /**
691  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
692  * @adapter: address of board private structure
693  **/
694 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
695                                    struct ixgbe_ring *rx_ring,
696                                    int cleaned_count)
697 {
698         struct pci_dev *pdev = adapter->pdev;
699         union ixgbe_adv_rx_desc *rx_desc;
700         struct ixgbe_rx_buffer *bi;
701         unsigned int i;
702
703         i = rx_ring->next_to_use;
704         bi = &rx_ring->rx_buffer_info[i];
705
706         while (cleaned_count--) {
707                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
708
709                 if (!bi->page_dma &&
710                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
711                         if (!bi->page) {
712                                 bi->page = alloc_page(GFP_ATOMIC);
713                                 if (!bi->page) {
714                                         adapter->alloc_rx_page_failed++;
715                                         goto no_buffers;
716                                 }
717                                 bi->page_offset = 0;
718                         } else {
719                                 /* use a half page if we're re-using */
720                                 bi->page_offset ^= (PAGE_SIZE / 2);
721                         }
722
723                         bi->page_dma = pci_map_page(pdev, bi->page,
724                                                     bi->page_offset,
725                                                     (PAGE_SIZE / 2),
726                                                     PCI_DMA_FROMDEVICE);
727                 }
728
729                 if (!bi->skb) {
730                         struct sk_buff *skb;
731                         /* netdev_alloc_skb reserves 32 bytes up front!! */
732                         uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
733                         skb = netdev_alloc_skb(adapter->netdev, bufsz);
734
735                         if (!skb) {
736                                 adapter->alloc_rx_buff_failed++;
737                                 goto no_buffers;
738                         }
739
740                         /* advance the data pointer to the next cache line */
741                         skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
742                                           - skb->data));
743
744                         bi->skb = skb;
745                         bi->dma = pci_map_single(pdev, skb->data,
746                                                  rx_ring->rx_buf_len,
747                                                  PCI_DMA_FROMDEVICE);
748                 }
749                 /* Refresh the desc even if buffer_addrs didn't change because
750                  * each write-back erases this info. */
751                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
752                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
753                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
754                 } else {
755                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
756                 }
757
758                 i++;
759                 if (i == rx_ring->count)
760                         i = 0;
761                 bi = &rx_ring->rx_buffer_info[i];
762         }
763
764 no_buffers:
765         if (rx_ring->next_to_use != i) {
766                 rx_ring->next_to_use = i;
767                 if (i-- == 0)
768                         i = (rx_ring->count - 1);
769
770                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
771         }
772 }
773
774 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
775 {
776         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
777 }
778
779 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
780 {
781         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
782 }
783
784 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
785 {
786         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
787                 IXGBE_RXDADV_RSCCNT_MASK) >>
788                 IXGBE_RXDADV_RSCCNT_SHIFT;
789 }
790
791 /**
792  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
793  * @skb: pointer to the last skb in the rsc queue
794  * @count: pointer to number of packets coalesced in this context
795  *
796  * This function changes a queue full of hw rsc buffers into a completed
797  * packet.  It uses the ->prev pointers to find the first packet and then
798  * turns it into the frag list owner.
799  **/
800 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
801                                                         u64 *count)
802 {
803         unsigned int frag_list_size = 0;
804
805         while (skb->prev) {
806                 struct sk_buff *prev = skb->prev;
807                 frag_list_size += skb->len;
808                 skb->prev = NULL;
809                 skb = prev;
810                 *count += 1;
811         }
812
813         skb_shinfo(skb)->frag_list = skb->next;
814         skb->next = NULL;
815         skb->len += frag_list_size;
816         skb->data_len += frag_list_size;
817         skb->truesize += frag_list_size;
818         return skb;
819 }
820
821 struct ixgbe_rsc_cb {
822         dma_addr_t dma;
823 };
824
825 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
826
827 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
828                                struct ixgbe_ring *rx_ring,
829                                int *work_done, int work_to_do)
830 {
831         struct ixgbe_adapter *adapter = q_vector->adapter;
832         struct net_device *netdev = adapter->netdev;
833         struct pci_dev *pdev = adapter->pdev;
834         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
835         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
836         struct sk_buff *skb;
837         unsigned int i, rsc_count = 0;
838         u32 len, staterr;
839         u16 hdr_info;
840         bool cleaned = false;
841         int cleaned_count = 0;
842         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
843 #ifdef IXGBE_FCOE
844         int ddp_bytes = 0;
845 #endif /* IXGBE_FCOE */
846
847         i = rx_ring->next_to_clean;
848         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
849         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
850         rx_buffer_info = &rx_ring->rx_buffer_info[i];
851
852         while (staterr & IXGBE_RXD_STAT_DD) {
853                 u32 upper_len = 0;
854                 if (*work_done >= work_to_do)
855                         break;
856                 (*work_done)++;
857
858                 rmb(); /* read descriptor and rx_buffer_info after status DD */
859                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
860                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
861                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
862                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
863                         if (len > IXGBE_RX_HDR_SIZE)
864                                 len = IXGBE_RX_HDR_SIZE;
865                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
866                 } else {
867                         len = le16_to_cpu(rx_desc->wb.upper.length);
868                 }
869
870                 cleaned = true;
871                 skb = rx_buffer_info->skb;
872                 prefetch(skb->data);
873                 rx_buffer_info->skb = NULL;
874
875                 if (rx_buffer_info->dma) {
876                         if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
877                             (!(staterr & IXGBE_RXD_STAT_EOP)) &&
878                                  (!(skb->prev)))
879                                 /*
880                                  * When HWRSC is enabled, delay unmapping
881                                  * of the first packet. It carries the
882                                  * header information, HW may still
883                                  * access the header after the writeback.
884                                  * Only unmap it when EOP is reached
885                                  */
886                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
887                         else
888                                 pci_unmap_single(pdev, rx_buffer_info->dma,
889                                                  rx_ring->rx_buf_len,
890                                                  PCI_DMA_FROMDEVICE);
891                         rx_buffer_info->dma = 0;
892                         skb_put(skb, len);
893                 }
894
895                 if (upper_len) {
896                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
897                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
898                         rx_buffer_info->page_dma = 0;
899                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
900                                            rx_buffer_info->page,
901                                            rx_buffer_info->page_offset,
902                                            upper_len);
903
904                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
905                             (page_count(rx_buffer_info->page) != 1))
906                                 rx_buffer_info->page = NULL;
907                         else
908                                 get_page(rx_buffer_info->page);
909
910                         skb->len += upper_len;
911                         skb->data_len += upper_len;
912                         skb->truesize += upper_len;
913                 }
914
915                 i++;
916                 if (i == rx_ring->count)
917                         i = 0;
918
919                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
920                 prefetch(next_rxd);
921                 cleaned_count++;
922
923                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
924                         rsc_count = ixgbe_get_rsc_count(rx_desc);
925
926                 if (rsc_count) {
927                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
928                                      IXGBE_RXDADV_NEXTP_SHIFT;
929                         next_buffer = &rx_ring->rx_buffer_info[nextp];
930                 } else {
931                         next_buffer = &rx_ring->rx_buffer_info[i];
932                 }
933
934                 if (staterr & IXGBE_RXD_STAT_EOP) {
935                         if (skb->prev)
936                                 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
937                         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
938                                 if (IXGBE_RSC_CB(skb)->dma)
939                                         pci_unmap_single(pdev, IXGBE_RSC_CB(skb)->dma,
940                                                          rx_ring->rx_buf_len,
941                                                          PCI_DMA_FROMDEVICE);
942                                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
943                                         rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
944                                 else
945                                         rx_ring->rsc_count++;
946                                 rx_ring->rsc_flush++;
947                         }
948                         rx_ring->stats.packets++;
949                         rx_ring->stats.bytes += skb->len;
950                 } else {
951                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
952                                 rx_buffer_info->skb = next_buffer->skb;
953                                 rx_buffer_info->dma = next_buffer->dma;
954                                 next_buffer->skb = skb;
955                                 next_buffer->dma = 0;
956                         } else {
957                                 skb->next = next_buffer->skb;
958                                 skb->next->prev = skb;
959                         }
960                         rx_ring->non_eop_descs++;
961                         goto next_desc;
962                 }
963
964                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
965                         dev_kfree_skb_irq(skb);
966                         goto next_desc;
967                 }
968
969                 ixgbe_rx_checksum(adapter, rx_desc, skb);
970
971                 /* probably a little skewed due to removing CRC */
972                 total_rx_bytes += skb->len;
973                 total_rx_packets++;
974
975                 skb->protocol = eth_type_trans(skb, adapter->netdev);
976 #ifdef IXGBE_FCOE
977                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
978                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
979                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
980                         if (!ddp_bytes)
981                                 goto next_desc;
982                 }
983 #endif /* IXGBE_FCOE */
984                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
985
986 next_desc:
987                 rx_desc->wb.upper.status_error = 0;
988
989                 /* return some buffers to hardware, one at a time is too slow */
990                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
991                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
992                         cleaned_count = 0;
993                 }
994
995                 /* use prefetched values */
996                 rx_desc = next_rxd;
997                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
998
999                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1000         }
1001
1002         rx_ring->next_to_clean = i;
1003         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1004
1005         if (cleaned_count)
1006                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1007
1008 #ifdef IXGBE_FCOE
1009         /* include DDPed FCoE data */
1010         if (ddp_bytes > 0) {
1011                 unsigned int mss;
1012
1013                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1014                         sizeof(struct fc_frame_header) -
1015                         sizeof(struct fcoe_crc_eof);
1016                 if (mss > 512)
1017                         mss &= ~511;
1018                 total_rx_bytes += ddp_bytes;
1019                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1020         }
1021 #endif /* IXGBE_FCOE */
1022
1023         rx_ring->total_packets += total_rx_packets;
1024         rx_ring->total_bytes += total_rx_bytes;
1025         netdev->stats.rx_bytes += total_rx_bytes;
1026         netdev->stats.rx_packets += total_rx_packets;
1027
1028         return cleaned;
1029 }
1030
1031 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1032 /**
1033  * ixgbe_configure_msix - Configure MSI-X hardware
1034  * @adapter: board private structure
1035  *
1036  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1037  * interrupts.
1038  **/
1039 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1040 {
1041         struct ixgbe_q_vector *q_vector;
1042         int i, j, q_vectors, v_idx, r_idx;
1043         u32 mask;
1044
1045         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1046
1047         /*
1048          * Populate the IVAR table and set the ITR values to the
1049          * corresponding register.
1050          */
1051         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1052                 q_vector = adapter->q_vector[v_idx];
1053                 /* XXX for_each_set_bit(...) */
1054                 r_idx = find_first_bit(q_vector->rxr_idx,
1055                                        adapter->num_rx_queues);
1056
1057                 for (i = 0; i < q_vector->rxr_count; i++) {
1058                         j = adapter->rx_ring[r_idx]->reg_idx;
1059                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1060                         r_idx = find_next_bit(q_vector->rxr_idx,
1061                                               adapter->num_rx_queues,
1062                                               r_idx + 1);
1063                 }
1064                 r_idx = find_first_bit(q_vector->txr_idx,
1065                                        adapter->num_tx_queues);
1066
1067                 for (i = 0; i < q_vector->txr_count; i++) {
1068                         j = adapter->tx_ring[r_idx]->reg_idx;
1069                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1070                         r_idx = find_next_bit(q_vector->txr_idx,
1071                                               adapter->num_tx_queues,
1072                                               r_idx + 1);
1073                 }
1074
1075                 if (q_vector->txr_count && !q_vector->rxr_count)
1076                         /* tx only */
1077                         q_vector->eitr = adapter->tx_eitr_param;
1078                 else if (q_vector->rxr_count)
1079                         /* rx or mixed */
1080                         q_vector->eitr = adapter->rx_eitr_param;
1081
1082                 ixgbe_write_eitr(q_vector);
1083         }
1084
1085         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1086                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1087                                v_idx);
1088         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1089                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1090         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1091
1092         /* set up to autoclear timer, and the vectors */
1093         mask = IXGBE_EIMS_ENABLE_MASK;
1094         if (adapter->num_vfs)
1095                 mask &= ~(IXGBE_EIMS_OTHER |
1096                           IXGBE_EIMS_MAILBOX |
1097                           IXGBE_EIMS_LSC);
1098         else
1099                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1100         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1101 }
1102
1103 enum latency_range {
1104         lowest_latency = 0,
1105         low_latency = 1,
1106         bulk_latency = 2,
1107         latency_invalid = 255
1108 };
1109
1110 /**
1111  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1112  * @adapter: pointer to adapter
1113  * @eitr: eitr setting (ints per sec) to give last timeslice
1114  * @itr_setting: current throttle rate in ints/second
1115  * @packets: the number of packets during this measurement interval
1116  * @bytes: the number of bytes during this measurement interval
1117  *
1118  *      Stores a new ITR value based on packets and byte
1119  *      counts during the last interrupt.  The advantage of per interrupt
1120  *      computation is faster updates and more accurate ITR for the current
1121  *      traffic pattern.  Constants in this function were computed
1122  *      based on theoretical maximum wire speed and thresholds were set based
1123  *      on testing data as well as attempting to minimize response time
1124  *      while increasing bulk throughput.
1125  *      this functionality is controlled by the InterruptThrottleRate module
1126  *      parameter (see ixgbe_param.c)
1127  **/
1128 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1129                            u32 eitr, u8 itr_setting,
1130                            int packets, int bytes)
1131 {
1132         unsigned int retval = itr_setting;
1133         u32 timepassed_us;
1134         u64 bytes_perint;
1135
1136         if (packets == 0)
1137                 goto update_itr_done;
1138
1139
1140         /* simple throttlerate management
1141          *    0-20MB/s lowest (100000 ints/s)
1142          *   20-100MB/s low   (20000 ints/s)
1143          *  100-1249MB/s bulk (8000 ints/s)
1144          */
1145         /* what was last interrupt timeslice? */
1146         timepassed_us = 1000000/eitr;
1147         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1148
1149         switch (itr_setting) {
1150         case lowest_latency:
1151                 if (bytes_perint > adapter->eitr_low)
1152                         retval = low_latency;
1153                 break;
1154         case low_latency:
1155                 if (bytes_perint > adapter->eitr_high)
1156                         retval = bulk_latency;
1157                 else if (bytes_perint <= adapter->eitr_low)
1158                         retval = lowest_latency;
1159                 break;
1160         case bulk_latency:
1161                 if (bytes_perint <= adapter->eitr_high)
1162                         retval = low_latency;
1163                 break;
1164         }
1165
1166 update_itr_done:
1167         return retval;
1168 }
1169
1170 /**
1171  * ixgbe_write_eitr - write EITR register in hardware specific way
1172  * @q_vector: structure containing interrupt and ring information
1173  *
1174  * This function is made to be called by ethtool and by the driver
1175  * when it needs to update EITR registers at runtime.  Hardware
1176  * specific quirks/differences are taken care of here.
1177  */
1178 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1179 {
1180         struct ixgbe_adapter *adapter = q_vector->adapter;
1181         struct ixgbe_hw *hw = &adapter->hw;
1182         int v_idx = q_vector->v_idx;
1183         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1184
1185         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1186                 /* must write high and low 16 bits to reset counter */
1187                 itr_reg |= (itr_reg << 16);
1188         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1189                 /*
1190                  * set the WDIS bit to not clear the timer bits and cause an
1191                  * immediate assertion of the interrupt
1192                  */
1193                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1194         }
1195         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1196 }
1197
1198 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1199 {
1200         struct ixgbe_adapter *adapter = q_vector->adapter;
1201         u32 new_itr;
1202         u8 current_itr, ret_itr;
1203         int i, r_idx;
1204         struct ixgbe_ring *rx_ring, *tx_ring;
1205
1206         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1207         for (i = 0; i < q_vector->txr_count; i++) {
1208                 tx_ring = adapter->tx_ring[r_idx];
1209                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1210                                            q_vector->tx_itr,
1211                                            tx_ring->total_packets,
1212                                            tx_ring->total_bytes);
1213                 /* if the result for this queue would decrease interrupt
1214                  * rate for this vector then use that result */
1215                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1216                                     q_vector->tx_itr - 1 : ret_itr);
1217                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1218                                       r_idx + 1);
1219         }
1220
1221         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1222         for (i = 0; i < q_vector->rxr_count; i++) {
1223                 rx_ring = adapter->rx_ring[r_idx];
1224                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1225                                            q_vector->rx_itr,
1226                                            rx_ring->total_packets,
1227                                            rx_ring->total_bytes);
1228                 /* if the result for this queue would decrease interrupt
1229                  * rate for this vector then use that result */
1230                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1231                                     q_vector->rx_itr - 1 : ret_itr);
1232                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1233                                       r_idx + 1);
1234         }
1235
1236         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1237
1238         switch (current_itr) {
1239         /* counts and packets in update_itr are dependent on these numbers */
1240         case lowest_latency:
1241                 new_itr = 100000;
1242                 break;
1243         case low_latency:
1244                 new_itr = 20000; /* aka hwitr = ~200 */
1245                 break;
1246         case bulk_latency:
1247         default:
1248                 new_itr = 8000;
1249                 break;
1250         }
1251
1252         if (new_itr != q_vector->eitr) {
1253                 /* do an exponential smoothing */
1254                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1255
1256                 /* save the algorithm value here, not the smoothed one */
1257                 q_vector->eitr = new_itr;
1258
1259                 ixgbe_write_eitr(q_vector);
1260         }
1261
1262         return;
1263 }
1264
1265 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1266 {
1267         struct ixgbe_hw *hw = &adapter->hw;
1268
1269         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1270             (eicr & IXGBE_EICR_GPI_SDP1)) {
1271                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1272                 /* write to clear the interrupt */
1273                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1274         }
1275 }
1276
1277 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1278 {
1279         struct ixgbe_hw *hw = &adapter->hw;
1280
1281         if (eicr & IXGBE_EICR_GPI_SDP1) {
1282                 /* Clear the interrupt */
1283                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1284                 schedule_work(&adapter->multispeed_fiber_task);
1285         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1286                 /* Clear the interrupt */
1287                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1288                 schedule_work(&adapter->sfp_config_module_task);
1289         } else {
1290                 /* Interrupt isn't for us... */
1291                 return;
1292         }
1293 }
1294
1295 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1296 {
1297         struct ixgbe_hw *hw = &adapter->hw;
1298
1299         adapter->lsc_int++;
1300         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1301         adapter->link_check_timeout = jiffies;
1302         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1303                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1304                 IXGBE_WRITE_FLUSH(hw);
1305                 schedule_work(&adapter->watchdog_task);
1306         }
1307 }
1308
1309 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1310 {
1311         struct net_device *netdev = data;
1312         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1313         struct ixgbe_hw *hw = &adapter->hw;
1314         u32 eicr;
1315
1316         /*
1317          * Workaround for Silicon errata.  Use clear-by-write instead
1318          * of clear-by-read.  Reading with EICS will return the
1319          * interrupt causes without clearing, which later be done
1320          * with the write to EICR.
1321          */
1322         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1323         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1324
1325         if (eicr & IXGBE_EICR_LSC)
1326                 ixgbe_check_lsc(adapter);
1327
1328         if (eicr & IXGBE_EICR_MAILBOX)
1329                 ixgbe_msg_task(adapter);
1330
1331         if (hw->mac.type == ixgbe_mac_82598EB)
1332                 ixgbe_check_fan_failure(adapter, eicr);
1333
1334         if (hw->mac.type == ixgbe_mac_82599EB) {
1335                 ixgbe_check_sfp_event(adapter, eicr);
1336
1337                 /* Handle Flow Director Full threshold interrupt */
1338                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1339                         int i;
1340                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1341                         /* Disable transmits before FDIR Re-initialization */
1342                         netif_tx_stop_all_queues(netdev);
1343                         for (i = 0; i < adapter->num_tx_queues; i++) {
1344                                 struct ixgbe_ring *tx_ring =
1345                                                             adapter->tx_ring[i];
1346                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1347                                                        &tx_ring->reinit_state))
1348                                         schedule_work(&adapter->fdir_reinit_task);
1349                         }
1350                 }
1351         }
1352         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1353                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1354
1355         return IRQ_HANDLED;
1356 }
1357
1358 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1359                                            u64 qmask)
1360 {
1361         u32 mask;
1362
1363         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1364                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1365                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1366         } else {
1367                 mask = (qmask & 0xFFFFFFFF);
1368                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1369                 mask = (qmask >> 32);
1370                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1371         }
1372         /* skip the flush */
1373 }
1374
1375 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1376                                             u64 qmask)
1377 {
1378         u32 mask;
1379
1380         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1381                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1382                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1383         } else {
1384                 mask = (qmask & 0xFFFFFFFF);
1385                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1386                 mask = (qmask >> 32);
1387                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1388         }
1389         /* skip the flush */
1390 }
1391
1392 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1393 {
1394         struct ixgbe_q_vector *q_vector = data;
1395         struct ixgbe_adapter  *adapter = q_vector->adapter;
1396         struct ixgbe_ring     *tx_ring;
1397         int i, r_idx;
1398
1399         if (!q_vector->txr_count)
1400                 return IRQ_HANDLED;
1401
1402         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1403         for (i = 0; i < q_vector->txr_count; i++) {
1404                 tx_ring = adapter->tx_ring[r_idx];
1405                 tx_ring->total_bytes = 0;
1406                 tx_ring->total_packets = 0;
1407                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1408                                       r_idx + 1);
1409         }
1410
1411         /* EIAM disabled interrupts (on this vector) for us */
1412         napi_schedule(&q_vector->napi);
1413
1414         return IRQ_HANDLED;
1415 }
1416
1417 /**
1418  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1419  * @irq: unused
1420  * @data: pointer to our q_vector struct for this interrupt vector
1421  **/
1422 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1423 {
1424         struct ixgbe_q_vector *q_vector = data;
1425         struct ixgbe_adapter  *adapter = q_vector->adapter;
1426         struct ixgbe_ring  *rx_ring;
1427         int r_idx;
1428         int i;
1429
1430         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1431         for (i = 0;  i < q_vector->rxr_count; i++) {
1432                 rx_ring = adapter->rx_ring[r_idx];
1433                 rx_ring->total_bytes = 0;
1434                 rx_ring->total_packets = 0;
1435                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1436                                       r_idx + 1);
1437         }
1438
1439         if (!q_vector->rxr_count)
1440                 return IRQ_HANDLED;
1441
1442         /* disable interrupts on this vector only */
1443         /* EIAM disabled interrupts (on this vector) for us */
1444         napi_schedule(&q_vector->napi);
1445
1446         return IRQ_HANDLED;
1447 }
1448
1449 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1450 {
1451         struct ixgbe_q_vector *q_vector = data;
1452         struct ixgbe_adapter  *adapter = q_vector->adapter;
1453         struct ixgbe_ring  *ring;
1454         int r_idx;
1455         int i;
1456
1457         if (!q_vector->txr_count && !q_vector->rxr_count)
1458                 return IRQ_HANDLED;
1459
1460         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1461         for (i = 0; i < q_vector->txr_count; i++) {
1462                 ring = adapter->tx_ring[r_idx];
1463                 ring->total_bytes = 0;
1464                 ring->total_packets = 0;
1465                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1466                                       r_idx + 1);
1467         }
1468
1469         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1470         for (i = 0; i < q_vector->rxr_count; i++) {
1471                 ring = adapter->rx_ring[r_idx];
1472                 ring->total_bytes = 0;
1473                 ring->total_packets = 0;
1474                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1475                                       r_idx + 1);
1476         }
1477
1478         /* EIAM disabled interrupts (on this vector) for us */
1479         napi_schedule(&q_vector->napi);
1480
1481         return IRQ_HANDLED;
1482 }
1483
1484 /**
1485  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1486  * @napi: napi struct with our devices info in it
1487  * @budget: amount of work driver is allowed to do this pass, in packets
1488  *
1489  * This function is optimized for cleaning one queue only on a single
1490  * q_vector!!!
1491  **/
1492 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1493 {
1494         struct ixgbe_q_vector *q_vector =
1495                                container_of(napi, struct ixgbe_q_vector, napi);
1496         struct ixgbe_adapter *adapter = q_vector->adapter;
1497         struct ixgbe_ring *rx_ring = NULL;
1498         int work_done = 0;
1499         long r_idx;
1500
1501         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1502         rx_ring = adapter->rx_ring[r_idx];
1503 #ifdef CONFIG_IXGBE_DCA
1504         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1505                 ixgbe_update_rx_dca(adapter, rx_ring);
1506 #endif
1507
1508         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1509
1510         /* If all Rx work done, exit the polling mode */
1511         if (work_done < budget) {
1512                 napi_complete(napi);
1513                 if (adapter->rx_itr_setting & 1)
1514                         ixgbe_set_itr_msix(q_vector);
1515                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1516                         ixgbe_irq_enable_queues(adapter,
1517                                                 ((u64)1 << q_vector->v_idx));
1518         }
1519
1520         return work_done;
1521 }
1522
1523 /**
1524  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1525  * @napi: napi struct with our devices info in it
1526  * @budget: amount of work driver is allowed to do this pass, in packets
1527  *
1528  * This function will clean more than one rx queue associated with a
1529  * q_vector.
1530  **/
1531 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1532 {
1533         struct ixgbe_q_vector *q_vector =
1534                                container_of(napi, struct ixgbe_q_vector, napi);
1535         struct ixgbe_adapter *adapter = q_vector->adapter;
1536         struct ixgbe_ring *ring = NULL;
1537         int work_done = 0, i;
1538         long r_idx;
1539         bool tx_clean_complete = true;
1540
1541         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1542         for (i = 0; i < q_vector->txr_count; i++) {
1543                 ring = adapter->tx_ring[r_idx];
1544 #ifdef CONFIG_IXGBE_DCA
1545                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1546                         ixgbe_update_tx_dca(adapter, ring);
1547 #endif
1548                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1549                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1550                                       r_idx + 1);
1551         }
1552
1553         /* attempt to distribute budget to each queue fairly, but don't allow
1554          * the budget to go below 1 because we'll exit polling */
1555         budget /= (q_vector->rxr_count ?: 1);
1556         budget = max(budget, 1);
1557         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1558         for (i = 0; i < q_vector->rxr_count; i++) {
1559                 ring = adapter->rx_ring[r_idx];
1560 #ifdef CONFIG_IXGBE_DCA
1561                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1562                         ixgbe_update_rx_dca(adapter, ring);
1563 #endif
1564                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1565                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1566                                       r_idx + 1);
1567         }
1568
1569         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1570         ring = adapter->rx_ring[r_idx];
1571         /* If all Rx work done, exit the polling mode */
1572         if (work_done < budget) {
1573                 napi_complete(napi);
1574                 if (adapter->rx_itr_setting & 1)
1575                         ixgbe_set_itr_msix(q_vector);
1576                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1577                         ixgbe_irq_enable_queues(adapter,
1578                                                 ((u64)1 << q_vector->v_idx));
1579                 return 0;
1580         }
1581
1582         return work_done;
1583 }
1584
1585 /**
1586  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1587  * @napi: napi struct with our devices info in it
1588  * @budget: amount of work driver is allowed to do this pass, in packets
1589  *
1590  * This function is optimized for cleaning one queue only on a single
1591  * q_vector!!!
1592  **/
1593 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1594 {
1595         struct ixgbe_q_vector *q_vector =
1596                                container_of(napi, struct ixgbe_q_vector, napi);
1597         struct ixgbe_adapter *adapter = q_vector->adapter;
1598         struct ixgbe_ring *tx_ring = NULL;
1599         int work_done = 0;
1600         long r_idx;
1601
1602         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1603         tx_ring = adapter->tx_ring[r_idx];
1604 #ifdef CONFIG_IXGBE_DCA
1605         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1606                 ixgbe_update_tx_dca(adapter, tx_ring);
1607 #endif
1608
1609         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1610                 work_done = budget;
1611
1612         /* If all Tx work done, exit the polling mode */
1613         if (work_done < budget) {
1614                 napi_complete(napi);
1615                 if (adapter->tx_itr_setting & 1)
1616                         ixgbe_set_itr_msix(q_vector);
1617                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1618                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1619         }
1620
1621         return work_done;
1622 }
1623
1624 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1625                                      int r_idx)
1626 {
1627         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1628
1629         set_bit(r_idx, q_vector->rxr_idx);
1630         q_vector->rxr_count++;
1631 }
1632
1633 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1634                                      int t_idx)
1635 {
1636         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1637
1638         set_bit(t_idx, q_vector->txr_idx);
1639         q_vector->txr_count++;
1640 }
1641
1642 /**
1643  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1644  * @adapter: board private structure to initialize
1645  * @vectors: allotted vector count for descriptor rings
1646  *
1647  * This function maps descriptor rings to the queue-specific vectors
1648  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1649  * one vector per ring/queue, but on a constrained vector budget, we
1650  * group the rings as "efficiently" as possible.  You would add new
1651  * mapping configurations in here.
1652  **/
1653 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1654                                       int vectors)
1655 {
1656         int v_start = 0;
1657         int rxr_idx = 0, txr_idx = 0;
1658         int rxr_remaining = adapter->num_rx_queues;
1659         int txr_remaining = adapter->num_tx_queues;
1660         int i, j;
1661         int rqpv, tqpv;
1662         int err = 0;
1663
1664         /* No mapping required if MSI-X is disabled. */
1665         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1666                 goto out;
1667
1668         /*
1669          * The ideal configuration...
1670          * We have enough vectors to map one per queue.
1671          */
1672         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1673                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1674                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1675
1676                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1677                         map_vector_to_txq(adapter, v_start, txr_idx);
1678
1679                 goto out;
1680         }
1681
1682         /*
1683          * If we don't have enough vectors for a 1-to-1
1684          * mapping, we'll have to group them so there are
1685          * multiple queues per vector.
1686          */
1687         /* Re-adjusting *qpv takes care of the remainder. */
1688         for (i = v_start; i < vectors; i++) {
1689                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1690                 for (j = 0; j < rqpv; j++) {
1691                         map_vector_to_rxq(adapter, i, rxr_idx);
1692                         rxr_idx++;
1693                         rxr_remaining--;
1694                 }
1695         }
1696         for (i = v_start; i < vectors; i++) {
1697                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1698                 for (j = 0; j < tqpv; j++) {
1699                         map_vector_to_txq(adapter, i, txr_idx);
1700                         txr_idx++;
1701                         txr_remaining--;
1702                 }
1703         }
1704
1705 out:
1706         return err;
1707 }
1708
1709 /**
1710  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1711  * @adapter: board private structure
1712  *
1713  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1714  * interrupts from the kernel.
1715  **/
1716 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1717 {
1718         struct net_device *netdev = adapter->netdev;
1719         irqreturn_t (*handler)(int, void *);
1720         int i, vector, q_vectors, err;
1721         int ri=0, ti=0;
1722
1723         /* Decrement for Other and TCP Timer vectors */
1724         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1725
1726         /* Map the Tx/Rx rings to the vectors we were allotted. */
1727         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1728         if (err)
1729                 goto out;
1730
1731 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1732                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1733                          &ixgbe_msix_clean_many)
1734         for (vector = 0; vector < q_vectors; vector++) {
1735                 handler = SET_HANDLER(adapter->q_vector[vector]);
1736
1737                 if(handler == &ixgbe_msix_clean_rx) {
1738                         sprintf(adapter->name[vector], "%s-%s-%d",
1739                                 netdev->name, "rx", ri++);
1740                 }
1741                 else if(handler == &ixgbe_msix_clean_tx) {
1742                         sprintf(adapter->name[vector], "%s-%s-%d",
1743                                 netdev->name, "tx", ti++);
1744                 }
1745                 else
1746                         sprintf(adapter->name[vector], "%s-%s-%d",
1747                                 netdev->name, "TxRx", vector);
1748
1749                 err = request_irq(adapter->msix_entries[vector].vector,
1750                                   handler, 0, adapter->name[vector],
1751                                   adapter->q_vector[vector]);
1752                 if (err) {
1753                         DPRINTK(PROBE, ERR,
1754                                 "request_irq failed for MSIX interrupt "
1755                                 "Error: %d\n", err);
1756                         goto free_queue_irqs;
1757                 }
1758         }
1759
1760         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1761         err = request_irq(adapter->msix_entries[vector].vector,
1762                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1763         if (err) {
1764                 DPRINTK(PROBE, ERR,
1765                         "request_irq for msix_lsc failed: %d\n", err);
1766                 goto free_queue_irqs;
1767         }
1768
1769         return 0;
1770
1771 free_queue_irqs:
1772         for (i = vector - 1; i >= 0; i--)
1773                 free_irq(adapter->msix_entries[--vector].vector,
1774                          adapter->q_vector[i]);
1775         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1776         pci_disable_msix(adapter->pdev);
1777         kfree(adapter->msix_entries);
1778         adapter->msix_entries = NULL;
1779 out:
1780         return err;
1781 }
1782
1783 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1784 {
1785         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1786         u8 current_itr;
1787         u32 new_itr = q_vector->eitr;
1788         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
1789         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
1790
1791         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1792                                             q_vector->tx_itr,
1793                                             tx_ring->total_packets,
1794                                             tx_ring->total_bytes);
1795         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1796                                             q_vector->rx_itr,
1797                                             rx_ring->total_packets,
1798                                             rx_ring->total_bytes);
1799
1800         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1801
1802         switch (current_itr) {
1803         /* counts and packets in update_itr are dependent on these numbers */
1804         case lowest_latency:
1805                 new_itr = 100000;
1806                 break;
1807         case low_latency:
1808                 new_itr = 20000; /* aka hwitr = ~200 */
1809                 break;
1810         case bulk_latency:
1811                 new_itr = 8000;
1812                 break;
1813         default:
1814                 break;
1815         }
1816
1817         if (new_itr != q_vector->eitr) {
1818                 /* do an exponential smoothing */
1819                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1820
1821                 /* save the algorithm value here, not the smoothed one */
1822                 q_vector->eitr = new_itr;
1823
1824                 ixgbe_write_eitr(q_vector);
1825         }
1826
1827         return;
1828 }
1829
1830 /**
1831  * ixgbe_irq_enable - Enable default interrupt generation settings
1832  * @adapter: board private structure
1833  **/
1834 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1835 {
1836         u32 mask;
1837
1838         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1839         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1840                 mask |= IXGBE_EIMS_GPI_SDP1;
1841         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1842                 mask |= IXGBE_EIMS_ECC;
1843                 mask |= IXGBE_EIMS_GPI_SDP1;
1844                 mask |= IXGBE_EIMS_GPI_SDP2;
1845                 if (adapter->num_vfs)
1846                         mask |= IXGBE_EIMS_MAILBOX;
1847         }
1848         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1849             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1850                 mask |= IXGBE_EIMS_FLOW_DIR;
1851
1852         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1853         ixgbe_irq_enable_queues(adapter, ~0);
1854         IXGBE_WRITE_FLUSH(&adapter->hw);
1855
1856         if (adapter->num_vfs > 32) {
1857                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1858                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1859         }
1860 }
1861
1862 /**
1863  * ixgbe_intr - legacy mode Interrupt Handler
1864  * @irq: interrupt number
1865  * @data: pointer to a network interface device structure
1866  **/
1867 static irqreturn_t ixgbe_intr(int irq, void *data)
1868 {
1869         struct net_device *netdev = data;
1870         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1871         struct ixgbe_hw *hw = &adapter->hw;
1872         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1873         u32 eicr;
1874
1875         /*
1876          * Workaround for silicon errata.  Mask the interrupts
1877          * before the read of EICR.
1878          */
1879         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1880
1881         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1882          * therefore no explict interrupt disable is necessary */
1883         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1884         if (!eicr) {
1885                 /* shared interrupt alert!
1886                  * make sure interrupts are enabled because the read will
1887                  * have disabled interrupts due to EIAM */
1888                 ixgbe_irq_enable(adapter);
1889                 return IRQ_NONE;        /* Not our interrupt */
1890         }
1891
1892         if (eicr & IXGBE_EICR_LSC)
1893                 ixgbe_check_lsc(adapter);
1894
1895         if (hw->mac.type == ixgbe_mac_82599EB)
1896                 ixgbe_check_sfp_event(adapter, eicr);
1897
1898         ixgbe_check_fan_failure(adapter, eicr);
1899
1900         if (napi_schedule_prep(&(q_vector->napi))) {
1901                 adapter->tx_ring[0]->total_packets = 0;
1902                 adapter->tx_ring[0]->total_bytes = 0;
1903                 adapter->rx_ring[0]->total_packets = 0;
1904                 adapter->rx_ring[0]->total_bytes = 0;
1905                 /* would disable interrupts here but EIAM disabled it */
1906                 __napi_schedule(&(q_vector->napi));
1907         }
1908
1909         return IRQ_HANDLED;
1910 }
1911
1912 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1913 {
1914         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1915
1916         for (i = 0; i < q_vectors; i++) {
1917                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1918                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1919                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1920                 q_vector->rxr_count = 0;
1921                 q_vector->txr_count = 0;
1922         }
1923 }
1924
1925 /**
1926  * ixgbe_request_irq - initialize interrupts
1927  * @adapter: board private structure
1928  *
1929  * Attempts to configure interrupts using the best available
1930  * capabilities of the hardware and kernel.
1931  **/
1932 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1933 {
1934         struct net_device *netdev = adapter->netdev;
1935         int err;
1936
1937         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1938                 err = ixgbe_request_msix_irqs(adapter);
1939         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1940                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
1941                                   netdev->name, netdev);
1942         } else {
1943                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
1944                                   netdev->name, netdev);
1945         }
1946
1947         if (err)
1948                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1949
1950         return err;
1951 }
1952
1953 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1954 {
1955         struct net_device *netdev = adapter->netdev;
1956
1957         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1958                 int i, q_vectors;
1959
1960                 q_vectors = adapter->num_msix_vectors;
1961
1962                 i = q_vectors - 1;
1963                 free_irq(adapter->msix_entries[i].vector, netdev);
1964
1965                 i--;
1966                 for (; i >= 0; i--) {
1967                         free_irq(adapter->msix_entries[i].vector,
1968                                  adapter->q_vector[i]);
1969                 }
1970
1971                 ixgbe_reset_q_vectors(adapter);
1972         } else {
1973                 free_irq(adapter->pdev->irq, netdev);
1974         }
1975 }
1976
1977 /**
1978  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1979  * @adapter: board private structure
1980  **/
1981 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1982 {
1983         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1984                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1985         } else {
1986                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1987                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1988                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1989                 if (adapter->num_vfs > 32)
1990                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
1991         }
1992         IXGBE_WRITE_FLUSH(&adapter->hw);
1993         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1994                 int i;
1995                 for (i = 0; i < adapter->num_msix_vectors; i++)
1996                         synchronize_irq(adapter->msix_entries[i].vector);
1997         } else {
1998                 synchronize_irq(adapter->pdev->irq);
1999         }
2000 }
2001
2002 /**
2003  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2004  *
2005  **/
2006 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2007 {
2008         struct ixgbe_hw *hw = &adapter->hw;
2009
2010         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2011                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2012
2013         ixgbe_set_ivar(adapter, 0, 0, 0);
2014         ixgbe_set_ivar(adapter, 1, 0, 0);
2015
2016         map_vector_to_rxq(adapter, 0, 0);
2017         map_vector_to_txq(adapter, 0, 0);
2018
2019         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
2020 }
2021
2022 /**
2023  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2024  * @adapter: board private structure
2025  *
2026  * Configure the Tx unit of the MAC after a reset.
2027  **/
2028 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2029 {
2030         u64 tdba;
2031         struct ixgbe_hw *hw = &adapter->hw;
2032         u32 i, j, tdlen, txctrl;
2033
2034         /* Setup the HW Tx Head and Tail descriptor pointers */
2035         for (i = 0; i < adapter->num_tx_queues; i++) {
2036                 struct ixgbe_ring *ring = adapter->tx_ring[i];
2037                 j = ring->reg_idx;
2038                 tdba = ring->dma;
2039                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
2040                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
2041                                 (tdba & DMA_BIT_MASK(32)));
2042                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2043                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2044                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2045                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
2046                 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2047                 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
2048                 /*
2049                  * Disable Tx Head Writeback RO bit, since this hoses
2050                  * bookkeeping if things aren't delivered in order.
2051                  */
2052                 switch (hw->mac.type) {
2053                 case ixgbe_mac_82598EB:
2054                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2055                         break;
2056                 case ixgbe_mac_82599EB:
2057                 default:
2058                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2059                         break;
2060                 }
2061                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
2062                 switch (hw->mac.type) {
2063                 case ixgbe_mac_82598EB:
2064                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2065                         break;
2066                 case ixgbe_mac_82599EB:
2067                 default:
2068                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2069                         break;
2070                 }
2071         }
2072
2073         if (hw->mac.type == ixgbe_mac_82599EB) {
2074                 u32 rttdcs;
2075                 u32 mask;
2076
2077                 /* disable the arbiter while setting MTQC */
2078                 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2079                 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2080                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2081
2082                 /* set transmit pool layout */
2083                 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2084                 switch (adapter->flags & mask) {
2085
2086                 case (IXGBE_FLAG_SRIOV_ENABLED):
2087                         IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2088                                         (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2089                         break;
2090
2091                 case (IXGBE_FLAG_DCB_ENABLED):
2092                         /* We enable 8 traffic classes, DCB only */
2093                         IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2094                                       (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2095                         break;
2096
2097                 default:
2098                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2099                         break;
2100                 }
2101
2102                 /* re-eable the arbiter */
2103                 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2104                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2105         }
2106 }
2107
2108 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2109
2110 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2111                                    struct ixgbe_ring *rx_ring)
2112 {
2113         u32 srrctl;
2114         int index;
2115         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2116
2117         index = rx_ring->reg_idx;
2118         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2119                 unsigned long mask;
2120                 mask = (unsigned long) feature[RING_F_RSS].mask;
2121                 index = index & mask;
2122         }
2123         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2124
2125         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2126         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2127
2128         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2129                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2130
2131         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2132 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2133                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2134 #else
2135                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2136 #endif
2137                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2138         } else {
2139                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2140                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2141                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2142         }
2143
2144         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2145 }
2146
2147 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2148 {
2149         u32 mrqc = 0;
2150         int mask;
2151
2152         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2153                 return mrqc;
2154
2155         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2156 #ifdef CONFIG_IXGBE_DCB
2157                                  | IXGBE_FLAG_DCB_ENABLED
2158 #endif
2159                                  | IXGBE_FLAG_SRIOV_ENABLED
2160                                 );
2161
2162         switch (mask) {
2163         case (IXGBE_FLAG_RSS_ENABLED):
2164                 mrqc = IXGBE_MRQC_RSSEN;
2165                 break;
2166         case (IXGBE_FLAG_SRIOV_ENABLED):
2167                 mrqc = IXGBE_MRQC_VMDQEN;
2168                 break;
2169 #ifdef CONFIG_IXGBE_DCB
2170         case (IXGBE_FLAG_DCB_ENABLED):
2171                 mrqc = IXGBE_MRQC_RT8TCEN;
2172                 break;
2173 #endif /* CONFIG_IXGBE_DCB */
2174         default:
2175                 break;
2176         }
2177
2178         return mrqc;
2179 }
2180
2181 /**
2182  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2183  * @adapter:    address of board private structure
2184  * @index:      index of ring to set
2185  **/
2186 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
2187 {
2188         struct ixgbe_ring *rx_ring;
2189         struct ixgbe_hw *hw = &adapter->hw;
2190         int j;
2191         u32 rscctrl;
2192         int rx_buf_len;
2193
2194         rx_ring = adapter->rx_ring[index];
2195         j = rx_ring->reg_idx;
2196         rx_buf_len = rx_ring->rx_buf_len;
2197         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2198         rscctrl |= IXGBE_RSCCTL_RSCEN;
2199         /*
2200          * we must limit the number of descriptors so that the
2201          * total size of max desc * buf_len is not greater
2202          * than 65535
2203          */
2204         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2205 #if (MAX_SKB_FRAGS > 16)
2206                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2207 #elif (MAX_SKB_FRAGS > 8)
2208                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2209 #elif (MAX_SKB_FRAGS > 4)
2210                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2211 #else
2212                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2213 #endif
2214         } else {
2215                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2216                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2217                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2218                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2219                 else
2220                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2221         }
2222         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2223 }
2224
2225 /**
2226  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2227  * @adapter: board private structure
2228  *
2229  * Configure the Rx unit of the MAC after a reset.
2230  **/
2231 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2232 {
2233         u64 rdba;
2234         struct ixgbe_hw *hw = &adapter->hw;
2235         struct ixgbe_ring *rx_ring;
2236         struct net_device *netdev = adapter->netdev;
2237         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2238         int i, j;
2239         u32 rdlen, rxctrl, rxcsum;
2240         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2241                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2242                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2243         u32 fctrl, hlreg0;
2244         u32 reta = 0, mrqc = 0;
2245         u32 rdrxctl;
2246         int rx_buf_len;
2247
2248         /* Decide whether to use packet split mode or not */
2249         /* Do not use packet split if we're in SR-IOV Mode */
2250         if (!adapter->num_vfs)
2251                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2252
2253         /* Set the RX buffer length according to the mode */
2254         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2255                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2256                 if (hw->mac.type == ixgbe_mac_82599EB) {
2257                         /* PSRTYPE must be initialized in 82599 */
2258                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2259                                       IXGBE_PSRTYPE_UDPHDR |
2260                                       IXGBE_PSRTYPE_IPV4HDR |
2261                                       IXGBE_PSRTYPE_IPV6HDR |
2262                                       IXGBE_PSRTYPE_L2HDR;
2263                         IXGBE_WRITE_REG(hw,
2264                                         IXGBE_PSRTYPE(adapter->num_vfs),
2265                                         psrtype);
2266                 }
2267         } else {
2268                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2269                     (netdev->mtu <= ETH_DATA_LEN))
2270                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2271                 else
2272                         rx_buf_len = ALIGN(max_frame, 1024);
2273         }
2274
2275         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2276         fctrl |= IXGBE_FCTRL_BAM;
2277         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2278         fctrl |= IXGBE_FCTRL_PMCF;
2279         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2280
2281         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2282         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2283                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2284         else
2285                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2286 #ifdef IXGBE_FCOE
2287         if (netdev->features & NETIF_F_FCOE_MTU)
2288                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2289 #endif
2290         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2291
2292         rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
2293         /* disable receives while setting up the descriptors */
2294         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2295         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2296
2297         /*
2298          * Setup the HW Rx Head and Tail Descriptor Pointers and
2299          * the Base and Length of the Rx Descriptor Ring
2300          */
2301         for (i = 0; i < adapter->num_rx_queues; i++) {
2302                 rx_ring = adapter->rx_ring[i];
2303                 rdba = rx_ring->dma;
2304                 j = rx_ring->reg_idx;
2305                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2306                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2307                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2308                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2309                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2310                 rx_ring->head = IXGBE_RDH(j);
2311                 rx_ring->tail = IXGBE_RDT(j);
2312                 rx_ring->rx_buf_len = rx_buf_len;
2313
2314                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2315                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2316                 else
2317                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2318
2319 #ifdef IXGBE_FCOE
2320                 if (netdev->features & NETIF_F_FCOE_MTU) {
2321                         struct ixgbe_ring_feature *f;
2322                         f = &adapter->ring_feature[RING_F_FCOE];
2323                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2324                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2325                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2326                                         rx_ring->rx_buf_len =
2327                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2328                         }
2329                 }
2330
2331 #endif /* IXGBE_FCOE */
2332                 ixgbe_configure_srrctl(adapter, rx_ring);
2333         }
2334
2335         if (hw->mac.type == ixgbe_mac_82598EB) {
2336                 /*
2337                  * For VMDq support of different descriptor types or
2338                  * buffer sizes through the use of multiple SRRCTL
2339                  * registers, RDRXCTL.MVMEN must be set to 1
2340                  *
2341                  * also, the manual doesn't mention it clearly but DCA hints
2342                  * will only use queue 0's tags unless this bit is set.  Side
2343                  * effects of setting this bit are only that SRRCTL must be
2344                  * fully programmed [0..15]
2345                  */
2346                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2347                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2348                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2349         }
2350
2351         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2352                 u32 vt_reg_bits;
2353                 u32 reg_offset, vf_shift;
2354                 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2355                 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2356                         | IXGBE_VT_CTL_REPLEN;
2357                 vt_reg_bits |= (adapter->num_vfs <<
2358                                 IXGBE_VT_CTL_POOL_SHIFT);
2359                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2360                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2361
2362                 vf_shift = adapter->num_vfs % 32;
2363                 reg_offset = adapter->num_vfs / 32;
2364                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2365                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2366                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2367                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2368                 /* Enable only the PF's pool for Tx/Rx */
2369                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2370                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2371                 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2372                 ixgbe_set_vmolr(hw, adapter->num_vfs);
2373         }
2374
2375         /* Program MRQC for the distribution of queues */
2376         mrqc = ixgbe_setup_mrqc(adapter);
2377
2378         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2379                 /* Fill out redirection table */
2380                 for (i = 0, j = 0; i < 128; i++, j++) {
2381                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2382                                 j = 0;
2383                         /* reta = 4-byte sliding window of
2384                          * 0x00..(indices-1)(indices-1)00..etc. */
2385                         reta = (reta << 8) | (j * 0x11);
2386                         if ((i & 3) == 3)
2387                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2388                 }
2389
2390                 /* Fill out hash function seeds */
2391                 for (i = 0; i < 10; i++)
2392                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2393
2394                 if (hw->mac.type == ixgbe_mac_82598EB)
2395                         mrqc |= IXGBE_MRQC_RSSEN;
2396                     /* Perform hash on these packet types */
2397                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2398                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2399                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2400                       | IXGBE_MRQC_RSS_FIELD_IPV6
2401                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2402                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2403         }
2404         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2405
2406         if (adapter->num_vfs) {
2407                 u32 reg;
2408
2409                 /* Map PF MAC address in RAR Entry 0 to first pool
2410                  * following VFs */
2411                 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2412
2413                 /* Set up VF register offsets for selected VT Mode, i.e.
2414                  * 64 VFs for SR-IOV */
2415                 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2416                 reg |= IXGBE_GCR_EXT_SRIOV;
2417                 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2418         }
2419
2420         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2421
2422         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2423             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2424                 /* Disable indicating checksum in descriptor, enables
2425                  * RSS hash */
2426                 rxcsum |= IXGBE_RXCSUM_PCSD;
2427         }
2428         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2429                 /* Enable IPv4 payload checksum for UDP fragments
2430                  * if PCSD is not set */
2431                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2432         }
2433
2434         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2435
2436         if (hw->mac.type == ixgbe_mac_82599EB) {
2437                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2438                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2439                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2440                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2441         }
2442
2443         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2444                 /* Enable 82599 HW-RSC */
2445                 for (i = 0; i < adapter->num_rx_queues; i++)
2446                         ixgbe_configure_rscctl(adapter, i);
2447
2448                 /* Disable RSC for ACK packets */
2449                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2450                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2451         }
2452 }
2453
2454 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2455 {
2456         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2457         struct ixgbe_hw *hw = &adapter->hw;
2458         int pool_ndx = adapter->num_vfs;
2459
2460         /* add VID to filter table */
2461         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
2462 }
2463
2464 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2465 {
2466         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2467         struct ixgbe_hw *hw = &adapter->hw;
2468         int pool_ndx = adapter->num_vfs;
2469
2470         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2471                 ixgbe_irq_disable(adapter);
2472
2473         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2474
2475         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2476                 ixgbe_irq_enable(adapter);
2477
2478         /* remove VID from filter table */
2479         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
2480 }
2481
2482 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2483                                    struct vlan_group *grp)
2484 {
2485         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2486         u32 ctrl;
2487         int i, j;
2488
2489         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2490                 ixgbe_irq_disable(adapter);
2491         adapter->vlgrp = grp;
2492
2493         /*
2494          * For a DCB driver, always enable VLAN tag stripping so we can
2495          * still receive traffic from a DCB-enabled host even if we're
2496          * not in DCB mode.
2497          */
2498         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2499
2500         /* Disable CFI check */
2501         ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2502
2503         /* enable VLAN tag stripping */
2504         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2505                 ctrl |= IXGBE_VLNCTRL_VME;
2506         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2507                 for (i = 0; i < adapter->num_rx_queues; i++) {
2508                         u32 ctrl;
2509                         j = adapter->rx_ring[i]->reg_idx;
2510                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2511                         ctrl |= IXGBE_RXDCTL_VME;
2512                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2513                 }
2514         }
2515
2516         IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2517
2518         ixgbe_vlan_rx_add_vid(netdev, 0);
2519
2520         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2521                 ixgbe_irq_enable(adapter);
2522 }
2523
2524 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2525 {
2526         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2527
2528         if (adapter->vlgrp) {
2529                 u16 vid;
2530                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2531                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2532                                 continue;
2533                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2534                 }
2535         }
2536 }
2537
2538 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2539 {
2540         struct dev_mc_list *mc_ptr;
2541         u8 *addr = *mc_addr_ptr;
2542         *vmdq = 0;
2543
2544         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2545         if (mc_ptr->next)
2546                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2547         else
2548                 *mc_addr_ptr = NULL;
2549
2550         return addr;
2551 }
2552
2553 /**
2554  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2555  * @netdev: network interface device structure
2556  *
2557  * The set_rx_method entry point is called whenever the unicast/multicast
2558  * address list or the network interface flags are updated.  This routine is
2559  * responsible for configuring the hardware for proper unicast, multicast and
2560  * promiscuous mode.
2561  **/
2562 void ixgbe_set_rx_mode(struct net_device *netdev)
2563 {
2564         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2565         struct ixgbe_hw *hw = &adapter->hw;
2566         u32 fctrl, vlnctrl;
2567         u8 *addr_list = NULL;
2568         int addr_count = 0;
2569
2570         /* Check for Promiscuous and All Multicast modes */
2571
2572         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2573         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2574
2575         if (netdev->flags & IFF_PROMISC) {
2576                 hw->addr_ctrl.user_set_promisc = 1;
2577                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2578                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2579         } else {
2580                 if (netdev->flags & IFF_ALLMULTI) {
2581                         fctrl |= IXGBE_FCTRL_MPE;
2582                         fctrl &= ~IXGBE_FCTRL_UPE;
2583                 } else {
2584                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2585                 }
2586                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2587                 hw->addr_ctrl.user_set_promisc = 0;
2588         }
2589
2590         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2591         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2592
2593         /* reprogram secondary unicast list */
2594         hw->mac.ops.update_uc_addr_list(hw, netdev);
2595
2596         /* reprogram multicast list */
2597         addr_count = netdev_mc_count(netdev);
2598         if (addr_count)
2599                 addr_list = netdev->mc_list->dmi_addr;
2600         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2601                                         ixgbe_addr_list_itr);
2602         if (adapter->num_vfs)
2603                 ixgbe_restore_vf_multicasts(adapter);
2604 }
2605
2606 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2607 {
2608         int q_idx;
2609         struct ixgbe_q_vector *q_vector;
2610         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2611
2612         /* legacy and MSI only use one vector */
2613         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2614                 q_vectors = 1;
2615
2616         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2617                 struct napi_struct *napi;
2618                 q_vector = adapter->q_vector[q_idx];
2619                 napi = &q_vector->napi;
2620                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2621                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2622                                 if (q_vector->txr_count == 1)
2623                                         napi->poll = &ixgbe_clean_txonly;
2624                                 else if (q_vector->rxr_count == 1)
2625                                         napi->poll = &ixgbe_clean_rxonly;
2626                         }
2627                 }
2628
2629                 napi_enable(napi);
2630         }
2631 }
2632
2633 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2634 {
2635         int q_idx;
2636         struct ixgbe_q_vector *q_vector;
2637         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2638
2639         /* legacy and MSI only use one vector */
2640         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2641                 q_vectors = 1;
2642
2643         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2644                 q_vector = adapter->q_vector[q_idx];
2645                 napi_disable(&q_vector->napi);
2646         }
2647 }
2648
2649 #ifdef CONFIG_IXGBE_DCB
2650 /*
2651  * ixgbe_configure_dcb - Configure DCB hardware
2652  * @adapter: ixgbe adapter struct
2653  *
2654  * This is called by the driver on open to configure the DCB hardware.
2655  * This is also called by the gennetlink interface when reconfiguring
2656  * the DCB state.
2657  */
2658 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2659 {
2660         struct ixgbe_hw *hw = &adapter->hw;
2661         u32 txdctl, vlnctrl;
2662         int i, j;
2663
2664         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2665         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2666         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2667
2668         /* reconfigure the hardware */
2669         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2670
2671         for (i = 0; i < adapter->num_tx_queues; i++) {
2672                 j = adapter->tx_ring[i]->reg_idx;
2673                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2674                 /* PThresh workaround for Tx hang with DFP enabled. */
2675                 txdctl |= 32;
2676                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2677         }
2678         /* Enable VLAN tag insert/strip */
2679         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2680         if (hw->mac.type == ixgbe_mac_82598EB) {
2681                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2682                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2683                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2684         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2685                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2686                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2687                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2688                 for (i = 0; i < adapter->num_rx_queues; i++) {
2689                         j = adapter->rx_ring[i]->reg_idx;
2690                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2691                         vlnctrl |= IXGBE_RXDCTL_VME;
2692                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2693                 }
2694         }
2695         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2696 }
2697
2698 #endif
2699 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2700 {
2701         struct net_device *netdev = adapter->netdev;
2702         struct ixgbe_hw *hw = &adapter->hw;
2703         int i;
2704
2705         ixgbe_set_rx_mode(netdev);
2706
2707         ixgbe_restore_vlan(adapter);
2708 #ifdef CONFIG_IXGBE_DCB
2709         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2710                 if (hw->mac.type == ixgbe_mac_82598EB)
2711                         netif_set_gso_max_size(netdev, 32768);
2712                 else
2713                         netif_set_gso_max_size(netdev, 65536);
2714                 ixgbe_configure_dcb(adapter);
2715         } else {
2716                 netif_set_gso_max_size(netdev, 65536);
2717         }
2718 #else
2719         netif_set_gso_max_size(netdev, 65536);
2720 #endif
2721
2722 #ifdef IXGBE_FCOE
2723         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2724                 ixgbe_configure_fcoe(adapter);
2725
2726 #endif /* IXGBE_FCOE */
2727         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2728                 for (i = 0; i < adapter->num_tx_queues; i++)
2729                         adapter->tx_ring[i]->atr_sample_rate =
2730                                                        adapter->atr_sample_rate;
2731                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2732         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2733                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2734         }
2735
2736         ixgbe_configure_tx(adapter);
2737         ixgbe_configure_rx(adapter);
2738         for (i = 0; i < adapter->num_rx_queues; i++)
2739                 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
2740                                        (adapter->rx_ring[i]->count - 1));
2741 }
2742
2743 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2744 {
2745         switch (hw->phy.type) {
2746         case ixgbe_phy_sfp_avago:
2747         case ixgbe_phy_sfp_ftl:
2748         case ixgbe_phy_sfp_intel:
2749         case ixgbe_phy_sfp_unknown:
2750         case ixgbe_phy_tw_tyco:
2751         case ixgbe_phy_tw_unknown:
2752                 return true;
2753         default:
2754                 return false;
2755         }
2756 }
2757
2758 /**
2759  * ixgbe_sfp_link_config - set up SFP+ link
2760  * @adapter: pointer to private adapter struct
2761  **/
2762 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2763 {
2764         struct ixgbe_hw *hw = &adapter->hw;
2765
2766                 if (hw->phy.multispeed_fiber) {
2767                         /*
2768                          * In multispeed fiber setups, the device may not have
2769                          * had a physical connection when the driver loaded.
2770                          * If that's the case, the initial link configuration
2771                          * couldn't get the MAC into 10G or 1G mode, so we'll
2772                          * never have a link status change interrupt fire.
2773                          * We need to try and force an autonegotiation
2774                          * session, then bring up link.
2775                          */
2776                         hw->mac.ops.setup_sfp(hw);
2777                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2778                                 schedule_work(&adapter->multispeed_fiber_task);
2779                 } else {
2780                         /*
2781                          * Direct Attach Cu and non-multispeed fiber modules
2782                          * still need to be configured properly prior to
2783                          * attempting link.
2784                          */
2785                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2786                                 schedule_work(&adapter->sfp_config_module_task);
2787                 }
2788 }
2789
2790 /**
2791  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2792  * @hw: pointer to private hardware struct
2793  *
2794  * Returns 0 on success, negative on failure
2795  **/
2796 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2797 {
2798         u32 autoneg;
2799         bool negotiation, link_up = false;
2800         u32 ret = IXGBE_ERR_LINK_SETUP;
2801
2802         if (hw->mac.ops.check_link)
2803                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2804
2805         if (ret)
2806                 goto link_cfg_out;
2807
2808         if (hw->mac.ops.get_link_capabilities)
2809                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2810         if (ret)
2811                 goto link_cfg_out;
2812
2813         if (hw->mac.ops.setup_link)
2814                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2815 link_cfg_out:
2816         return ret;
2817 }
2818
2819 #define IXGBE_MAX_RX_DESC_POLL 10
2820 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2821                                               int rxr)
2822 {
2823         int j = adapter->rx_ring[rxr]->reg_idx;
2824         int k;
2825
2826         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2827                 if (IXGBE_READ_REG(&adapter->hw,
2828                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2829                         break;
2830                 else
2831                         msleep(1);
2832         }
2833         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2834                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2835                         "not set within the polling period\n", rxr);
2836         }
2837         ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
2838                               (adapter->rx_ring[rxr]->count - 1));
2839 }
2840
2841 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2842 {
2843         struct net_device *netdev = adapter->netdev;
2844         struct ixgbe_hw *hw = &adapter->hw;
2845         int i, j = 0;
2846         int num_rx_rings = adapter->num_rx_queues;
2847         int err;
2848         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2849         u32 txdctl, rxdctl, mhadd;
2850         u32 dmatxctl;
2851         u32 gpie;
2852         u32 ctrl_ext;
2853
2854         ixgbe_get_hw_control(adapter);
2855
2856         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2857             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2858                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2859                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2860                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2861                 } else {
2862                         /* MSI only */
2863                         gpie = 0;
2864                 }
2865                 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2866                         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
2867                         gpie |= IXGBE_GPIE_VTMODE_64;
2868                 }
2869                 /* XXX: to interrupt immediately for EICS writes, enable this */
2870                 /* gpie |= IXGBE_GPIE_EIMEN; */
2871                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2872         }
2873
2874         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2875                 /*
2876                  * use EIAM to auto-mask when MSI-X interrupt is asserted
2877                  * this saves a register write for every interrupt
2878                  */
2879                 switch (hw->mac.type) {
2880                 case ixgbe_mac_82598EB:
2881                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2882                         break;
2883                 default:
2884                 case ixgbe_mac_82599EB:
2885                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
2886                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
2887                         break;
2888                 }
2889         } else {
2890                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2891                  * specifically only auto mask tx and rx interrupts */
2892                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2893         }
2894
2895         /* Enable fan failure interrupt if media type is copper */
2896         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2897                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2898                 gpie |= IXGBE_SDP1_GPIEN;
2899                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2900         }
2901
2902         if (hw->mac.type == ixgbe_mac_82599EB) {
2903                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2904                 gpie |= IXGBE_SDP1_GPIEN;
2905                 gpie |= IXGBE_SDP2_GPIEN;
2906                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2907         }
2908
2909 #ifdef IXGBE_FCOE
2910         /* adjust max frame to be able to do baby jumbo for FCoE */
2911         if ((netdev->features & NETIF_F_FCOE_MTU) &&
2912             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2913                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2914
2915 #endif /* IXGBE_FCOE */
2916         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2917         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2918                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2919                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2920
2921                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2922         }
2923
2924         for (i = 0; i < adapter->num_tx_queues; i++) {
2925                 j = adapter->tx_ring[i]->reg_idx;
2926                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2927                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2928                 txdctl |= (8 << 16);
2929                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2930         }
2931
2932         if (hw->mac.type == ixgbe_mac_82599EB) {
2933                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2934                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2935                 dmatxctl |= IXGBE_DMATXCTL_TE;
2936                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2937         }
2938         for (i = 0; i < adapter->num_tx_queues; i++) {
2939                 j = adapter->tx_ring[i]->reg_idx;
2940                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2941                 txdctl |= IXGBE_TXDCTL_ENABLE;
2942                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2943                 if (hw->mac.type == ixgbe_mac_82599EB) {
2944                         int wait_loop = 10;
2945                         /* poll for Tx Enable ready */
2946                         do {
2947                                 msleep(1);
2948                                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2949                         } while (--wait_loop &&
2950                                  !(txdctl & IXGBE_TXDCTL_ENABLE));
2951                         if (!wait_loop)
2952                                 DPRINTK(DRV, ERR, "Could not enable "
2953                                         "Tx Queue %d\n", j);
2954                 }
2955         }
2956
2957         for (i = 0; i < num_rx_rings; i++) {
2958                 j = adapter->rx_ring[i]->reg_idx;
2959                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2960                 /* enable PTHRESH=32 descriptors (half the internal cache)
2961                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2962                  * this also removes a pesky rx_no_buffer_count increment */
2963                 rxdctl |= 0x0020;
2964                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2965                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2966                 if (hw->mac.type == ixgbe_mac_82599EB)
2967                         ixgbe_rx_desc_queue_enable(adapter, i);
2968         }
2969         /* enable all receives */
2970         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2971         if (hw->mac.type == ixgbe_mac_82598EB)
2972                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2973         else
2974                 rxdctl |= IXGBE_RXCTRL_RXEN;
2975         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2976
2977         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2978                 ixgbe_configure_msix(adapter);
2979         else
2980                 ixgbe_configure_msi_and_legacy(adapter);
2981
2982         clear_bit(__IXGBE_DOWN, &adapter->state);
2983         ixgbe_napi_enable_all(adapter);
2984
2985         /* clear any pending interrupts, may auto mask */
2986         IXGBE_READ_REG(hw, IXGBE_EICR);
2987
2988         ixgbe_irq_enable(adapter);
2989
2990         /*
2991          * If this adapter has a fan, check to see if we had a failure
2992          * before we enabled the interrupt.
2993          */
2994         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2995                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2996                 if (esdp & IXGBE_ESDP_SDP1)
2997                         DPRINTK(DRV, CRIT,
2998                                 "Fan has stopped, replace the adapter\n");
2999         }
3000
3001         /*
3002          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3003          * arrived before interrupts were enabled but after probe.  Such
3004          * devices wouldn't have their type identified yet. We need to
3005          * kick off the SFP+ module setup first, then try to bring up link.
3006          * If we're not hot-pluggable SFP+, we just need to configure link
3007          * and bring it up.
3008          */
3009         if (hw->phy.type == ixgbe_phy_unknown) {
3010                 err = hw->phy.ops.identify(hw);
3011                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3012                         /*
3013                          * Take the device down and schedule the sfp tasklet
3014                          * which will unregister_netdev and log it.
3015                          */
3016                         ixgbe_down(adapter);
3017                         schedule_work(&adapter->sfp_config_module_task);
3018                         return err;
3019                 }
3020         }
3021
3022         if (ixgbe_is_sfp(hw)) {
3023                 ixgbe_sfp_link_config(adapter);
3024         } else {
3025                 err = ixgbe_non_sfp_link_config(hw);
3026                 if (err)
3027                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
3028         }
3029
3030         for (i = 0; i < adapter->num_tx_queues; i++)
3031                 set_bit(__IXGBE_FDIR_INIT_DONE,
3032                         &(adapter->tx_ring[i]->reinit_state));
3033
3034         /* enable transmits */
3035         netif_tx_start_all_queues(netdev);
3036
3037         /* bring the link up in the watchdog, this could race with our first
3038          * link up interrupt but shouldn't be a problem */
3039         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3040         adapter->link_check_timeout = jiffies;
3041         mod_timer(&adapter->watchdog_timer, jiffies);
3042
3043         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3044         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3045         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3046         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3047
3048         return 0;
3049 }
3050
3051 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3052 {
3053         WARN_ON(in_interrupt());
3054         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3055                 msleep(1);
3056         ixgbe_down(adapter);
3057         ixgbe_up(adapter);
3058         clear_bit(__IXGBE_RESETTING, &adapter->state);
3059 }
3060
3061 int ixgbe_up(struct ixgbe_adapter *adapter)
3062 {
3063         /* hardware has been reset, we need to reload some things */
3064         ixgbe_configure(adapter);
3065
3066         return ixgbe_up_complete(adapter);
3067 }
3068
3069 void ixgbe_reset(struct ixgbe_adapter *adapter)
3070 {
3071         struct ixgbe_hw *hw = &adapter->hw;
3072         int err;
3073
3074         err = hw->mac.ops.init_hw(hw);
3075         switch (err) {
3076         case 0:
3077         case IXGBE_ERR_SFP_NOT_PRESENT:
3078                 break;
3079         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3080                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
3081                 break;
3082         case IXGBE_ERR_EEPROM_VERSION:
3083                 /* We are running on a pre-production device, log a warning */
3084                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
3085                          "adapter/LOM.  Please be aware there may be issues "
3086                          "associated with your hardware.  If you are "
3087                          "experiencing problems please contact your Intel or "
3088                          "hardware representative who provided you with this "
3089                          "hardware.\n");
3090                 break;
3091         default:
3092                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
3093         }
3094
3095         /* reprogram the RAR[0] in case user changed it. */
3096         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3097                             IXGBE_RAH_AV);
3098 }
3099
3100 /**
3101  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3102  * @adapter: board private structure
3103  * @rx_ring: ring to free buffers from
3104  **/
3105 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3106                                 struct ixgbe_ring *rx_ring)
3107 {
3108         struct pci_dev *pdev = adapter->pdev;
3109         unsigned long size;
3110         unsigned int i;
3111
3112         /* Free all the Rx ring sk_buffs */
3113
3114         for (i = 0; i < rx_ring->count; i++) {
3115                 struct ixgbe_rx_buffer *rx_buffer_info;
3116
3117                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3118                 if (rx_buffer_info->dma) {
3119                         pci_unmap_single(pdev, rx_buffer_info->dma,
3120                                          rx_ring->rx_buf_len,
3121                                          PCI_DMA_FROMDEVICE);
3122                         rx_buffer_info->dma = 0;
3123                 }
3124                 if (rx_buffer_info->skb) {
3125                         struct sk_buff *skb = rx_buffer_info->skb;
3126                         rx_buffer_info->skb = NULL;
3127                         do {
3128                                 struct sk_buff *this = skb;
3129                                 if (IXGBE_RSC_CB(this)->dma)
3130                                         pci_unmap_single(pdev, IXGBE_RSC_CB(this)->dma,
3131                                                          rx_ring->rx_buf_len,
3132                                                          PCI_DMA_FROMDEVICE);
3133                                 skb = skb->prev;
3134                                 dev_kfree_skb(this);
3135                         } while (skb);
3136                 }
3137                 if (!rx_buffer_info->page)
3138                         continue;
3139                 if (rx_buffer_info->page_dma) {
3140                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
3141                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
3142                         rx_buffer_info->page_dma = 0;
3143                 }
3144                 put_page(rx_buffer_info->page);
3145                 rx_buffer_info->page = NULL;
3146                 rx_buffer_info->page_offset = 0;
3147         }
3148
3149         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3150         memset(rx_ring->rx_buffer_info, 0, size);
3151
3152         /* Zero out the descriptor ring */
3153         memset(rx_ring->desc, 0, rx_ring->size);
3154
3155         rx_ring->next_to_clean = 0;
3156         rx_ring->next_to_use = 0;
3157
3158         if (rx_ring->head)
3159                 writel(0, adapter->hw.hw_addr + rx_ring->head);
3160         if (rx_ring->tail)
3161                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3162 }
3163
3164 /**
3165  * ixgbe_clean_tx_ring - Free Tx Buffers
3166  * @adapter: board private structure
3167  * @tx_ring: ring to be cleaned
3168  **/
3169 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3170                                 struct ixgbe_ring *tx_ring)
3171 {
3172         struct ixgbe_tx_buffer *tx_buffer_info;
3173         unsigned long size;
3174         unsigned int i;
3175
3176         /* Free all the Tx ring sk_buffs */
3177
3178         for (i = 0; i < tx_ring->count; i++) {
3179                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3180                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3181         }
3182
3183         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3184         memset(tx_ring->tx_buffer_info, 0, size);
3185
3186         /* Zero out the descriptor ring */
3187         memset(tx_ring->desc, 0, tx_ring->size);
3188
3189         tx_ring->next_to_use = 0;
3190         tx_ring->next_to_clean = 0;
3191
3192         if (tx_ring->head)
3193                 writel(0, adapter->hw.hw_addr + tx_ring->head);
3194         if (tx_ring->tail)
3195                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3196 }
3197
3198 /**
3199  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3200  * @adapter: board private structure
3201  **/
3202 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3203 {
3204         int i;
3205
3206         for (i = 0; i < adapter->num_rx_queues; i++)
3207                 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
3208 }
3209
3210 /**
3211  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3212  * @adapter: board private structure
3213  **/
3214 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3215 {
3216         int i;
3217
3218         for (i = 0; i < adapter->num_tx_queues; i++)
3219                 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
3220 }
3221
3222 void ixgbe_down(struct ixgbe_adapter *adapter)
3223 {
3224         struct net_device *netdev = adapter->netdev;
3225         struct ixgbe_hw *hw = &adapter->hw;
3226         u32 rxctrl;
3227         u32 txdctl;
3228         int i, j;
3229
3230         /* signal that we are down to the interrupt handler */
3231         set_bit(__IXGBE_DOWN, &adapter->state);
3232
3233         /* disable receive for all VFs and wait one second */
3234         if (adapter->num_vfs) {
3235                 for (i = 0 ; i < adapter->num_vfs; i++)
3236                         adapter->vfinfo[i].clear_to_send = 0;
3237
3238                 /* ping all the active vfs to let them know we are going down */
3239                 ixgbe_ping_all_vfs(adapter);
3240                 /* Disable all VFTE/VFRE TX/RX */
3241                 ixgbe_disable_tx_rx(adapter);
3242         }
3243
3244         /* disable receives */
3245         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3246         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3247
3248         netif_tx_disable(netdev);
3249
3250         IXGBE_WRITE_FLUSH(hw);
3251         msleep(10);
3252
3253         netif_tx_stop_all_queues(netdev);
3254
3255         ixgbe_irq_disable(adapter);
3256
3257         ixgbe_napi_disable_all(adapter);
3258
3259         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3260         del_timer_sync(&adapter->sfp_timer);
3261         del_timer_sync(&adapter->watchdog_timer);
3262         cancel_work_sync(&adapter->watchdog_task);
3263
3264         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3265             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3266                 cancel_work_sync(&adapter->fdir_reinit_task);
3267
3268         /* disable transmits in the hardware now that interrupts are off */
3269         for (i = 0; i < adapter->num_tx_queues; i++) {
3270                 j = adapter->tx_ring[i]->reg_idx;
3271                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3272                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3273                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3274         }
3275         /* Disable the Tx DMA engine on 82599 */
3276         if (hw->mac.type == ixgbe_mac_82599EB)
3277                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3278                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3279                                  ~IXGBE_DMATXCTL_TE));
3280
3281         netif_carrier_off(netdev);
3282
3283         /* clear n-tuple filters that are cached */
3284         ethtool_ntuple_flush(netdev);
3285
3286         if (!pci_channel_offline(adapter->pdev))
3287                 ixgbe_reset(adapter);
3288         ixgbe_clean_all_tx_rings(adapter);
3289         ixgbe_clean_all_rx_rings(adapter);
3290
3291 #ifdef CONFIG_IXGBE_DCA
3292         /* since we reset the hardware DCA settings were cleared */
3293         ixgbe_setup_dca(adapter);
3294 #endif
3295 }
3296
3297 /**
3298  * ixgbe_poll - NAPI Rx polling callback
3299  * @napi: structure for representing this polling device
3300  * @budget: how many packets driver is allowed to clean
3301  *
3302  * This function is used for legacy and MSI, NAPI mode
3303  **/
3304 static int ixgbe_poll(struct napi_struct *napi, int budget)
3305 {
3306         struct ixgbe_q_vector *q_vector =
3307                                 container_of(napi, struct ixgbe_q_vector, napi);
3308         struct ixgbe_adapter *adapter = q_vector->adapter;
3309         int tx_clean_complete, work_done = 0;
3310
3311 #ifdef CONFIG_IXGBE_DCA
3312         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3313                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3314                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3315         }
3316 #endif
3317
3318         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3319         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3320
3321         if (!tx_clean_complete)
3322                 work_done = budget;
3323
3324         /* If budget not fully consumed, exit the polling mode */
3325         if (work_done < budget) {
3326                 napi_complete(napi);
3327                 if (adapter->rx_itr_setting & 1)
3328                         ixgbe_set_itr(adapter);
3329                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3330                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3331         }
3332         return work_done;
3333 }
3334
3335 /**
3336  * ixgbe_tx_timeout - Respond to a Tx Hang
3337  * @netdev: network interface device structure
3338  **/
3339 static void ixgbe_tx_timeout(struct net_device *netdev)
3340 {
3341         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3342
3343         /* Do the reset outside of interrupt context */
3344         schedule_work(&adapter->reset_task);
3345 }
3346
3347 static void ixgbe_reset_task(struct work_struct *work)
3348 {
3349         struct ixgbe_adapter *adapter;
3350         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3351
3352         /* If we're already down or resetting, just bail */
3353         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3354             test_bit(__IXGBE_RESETTING, &adapter->state))
3355                 return;
3356
3357         adapter->tx_timeout_count++;
3358
3359         ixgbe_reinit_locked(adapter);
3360 }
3361
3362 #ifdef CONFIG_IXGBE_DCB
3363 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3364 {
3365         bool ret = false;
3366         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3367
3368         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3369                 return ret;
3370
3371         f->mask = 0x7 << 3;
3372         adapter->num_rx_queues = f->indices;
3373         adapter->num_tx_queues = f->indices;
3374         ret = true;
3375
3376         return ret;
3377 }
3378 #endif
3379
3380 /**
3381  * ixgbe_set_rss_queues: Allocate queues for RSS
3382  * @adapter: board private structure to initialize
3383  *
3384  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3385  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3386  *
3387  **/
3388 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3389 {
3390         bool ret = false;
3391         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3392
3393         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3394                 f->mask = 0xF;
3395                 adapter->num_rx_queues = f->indices;
3396                 adapter->num_tx_queues = f->indices;
3397                 ret = true;
3398         } else {
3399                 ret = false;
3400         }
3401
3402         return ret;
3403 }
3404
3405 /**
3406  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3407  * @adapter: board private structure to initialize
3408  *
3409  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3410  * to the original CPU that initiated the Tx session.  This runs in addition
3411  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3412  * Rx load across CPUs using RSS.
3413  *
3414  **/
3415 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3416 {
3417         bool ret = false;
3418         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3419
3420         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3421         f_fdir->mask = 0;
3422
3423         /* Flow Director must have RSS enabled */
3424         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3425             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3426              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3427                 adapter->num_tx_queues = f_fdir->indices;
3428                 adapter->num_rx_queues = f_fdir->indices;
3429                 ret = true;
3430         } else {
3431                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3432                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3433         }
3434         return ret;
3435 }
3436
3437 #ifdef IXGBE_FCOE
3438 /**
3439  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3440  * @adapter: board private structure to initialize
3441  *
3442  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3443  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3444  * rx queues out of the max number of rx queues, instead, it is used as the
3445  * index of the first rx queue used by FCoE.
3446  *
3447  **/
3448 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3449 {
3450         bool ret = false;
3451         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3452
3453         f->indices = min((int)num_online_cpus(), f->indices);
3454         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3455                 adapter->num_rx_queues = 1;
3456                 adapter->num_tx_queues = 1;
3457 #ifdef CONFIG_IXGBE_DCB
3458                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3459                         DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
3460                         ixgbe_set_dcb_queues(adapter);
3461                 }
3462 #endif
3463                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3464                         DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
3465                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3466                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3467                                 ixgbe_set_fdir_queues(adapter);
3468                         else
3469                                 ixgbe_set_rss_queues(adapter);
3470                 }
3471                 /* adding FCoE rx rings to the end */
3472                 f->mask = adapter->num_rx_queues;
3473                 adapter->num_rx_queues += f->indices;
3474                 adapter->num_tx_queues += f->indices;
3475
3476                 ret = true;
3477         }
3478
3479         return ret;
3480 }
3481
3482 #endif /* IXGBE_FCOE */
3483 /**
3484  * ixgbe_set_sriov_queues: Allocate queues for IOV use
3485  * @adapter: board private structure to initialize
3486  *
3487  * IOV doesn't actually use anything, so just NAK the
3488  * request for now and let the other queue routines
3489  * figure out what to do.
3490  */
3491 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
3492 {
3493         return false;
3494 }
3495
3496 /*
3497  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3498  * @adapter: board private structure to initialize
3499  *
3500  * This is the top level queue allocation routine.  The order here is very
3501  * important, starting with the "most" number of features turned on at once,
3502  * and ending with the smallest set of features.  This way large combinations
3503  * can be allocated if they're turned on, and smaller combinations are the
3504  * fallthrough conditions.
3505  *
3506  **/
3507 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3508 {
3509         /* Start with base case */
3510         adapter->num_rx_queues = 1;
3511         adapter->num_tx_queues = 1;
3512         adapter->num_rx_pools = adapter->num_rx_queues;
3513         adapter->num_rx_queues_per_pool = 1;
3514
3515         if (ixgbe_set_sriov_queues(adapter))
3516                 return;
3517
3518 #ifdef IXGBE_FCOE
3519         if (ixgbe_set_fcoe_queues(adapter))
3520                 goto done;
3521
3522 #endif /* IXGBE_FCOE */
3523 #ifdef CONFIG_IXGBE_DCB
3524         if (ixgbe_set_dcb_queues(adapter))
3525                 goto done;
3526
3527 #endif
3528         if (ixgbe_set_fdir_queues(adapter))
3529                 goto done;
3530
3531         if (ixgbe_set_rss_queues(adapter))
3532                 goto done;
3533
3534         /* fallback to base case */
3535         adapter->num_rx_queues = 1;
3536         adapter->num_tx_queues = 1;
3537
3538 done:
3539         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3540         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3541 }
3542
3543 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3544                                        int vectors)
3545 {
3546         int err, vector_threshold;
3547
3548         /* We'll want at least 3 (vector_threshold):
3549          * 1) TxQ[0] Cleanup
3550          * 2) RxQ[0] Cleanup
3551          * 3) Other (Link Status Change, etc.)
3552          * 4) TCP Timer (optional)
3553          */
3554         vector_threshold = MIN_MSIX_COUNT;
3555
3556         /* The more we get, the more we will assign to Tx/Rx Cleanup
3557          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3558          * Right now, we simply care about how many we'll get; we'll
3559          * set them up later while requesting irq's.
3560          */
3561         while (vectors >= vector_threshold) {
3562                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3563                                       vectors);
3564                 if (!err) /* Success in acquiring all requested vectors. */
3565                         break;
3566                 else if (err < 0)
3567                         vectors = 0; /* Nasty failure, quit now */
3568                 else /* err == number of vectors we should try again with */
3569                         vectors = err;
3570         }
3571
3572         if (vectors < vector_threshold) {
3573                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3574                  * This just means we'll go with either a single MSI
3575                  * vector or fall back to legacy interrupts.
3576                  */
3577                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3578                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3579                 kfree(adapter->msix_entries);
3580                 adapter->msix_entries = NULL;
3581         } else {
3582                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3583                 /*
3584                  * Adjust for only the vectors we'll use, which is minimum
3585                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3586                  * vectors we were allocated.
3587                  */
3588                 adapter->num_msix_vectors = min(vectors,
3589                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3590         }
3591 }
3592
3593 /**
3594  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3595  * @adapter: board private structure to initialize
3596  *
3597  * Cache the descriptor ring offsets for RSS to the assigned rings.
3598  *
3599  **/
3600 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3601 {
3602         int i;
3603         bool ret = false;
3604
3605         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3606                 for (i = 0; i < adapter->num_rx_queues; i++)
3607                         adapter->rx_ring[i]->reg_idx = i;
3608                 for (i = 0; i < adapter->num_tx_queues; i++)
3609                         adapter->tx_ring[i]->reg_idx = i;
3610                 ret = true;
3611         } else {
3612                 ret = false;
3613         }
3614
3615         return ret;
3616 }
3617
3618 #ifdef CONFIG_IXGBE_DCB
3619 /**
3620  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3621  * @adapter: board private structure to initialize
3622  *
3623  * Cache the descriptor ring offsets for DCB to the assigned rings.
3624  *
3625  **/
3626 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3627 {
3628         int i;
3629         bool ret = false;
3630         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3631
3632         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3633                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3634                         /* the number of queues is assumed to be symmetric */
3635                         for (i = 0; i < dcb_i; i++) {
3636                                 adapter->rx_ring[i]->reg_idx = i << 3;
3637                                 adapter->tx_ring[i]->reg_idx = i << 2;
3638                         }
3639                         ret = true;
3640                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3641                         if (dcb_i == 8) {
3642                                 /*
3643                                  * Tx TC0 starts at: descriptor queue 0
3644                                  * Tx TC1 starts at: descriptor queue 32
3645                                  * Tx TC2 starts at: descriptor queue 64
3646                                  * Tx TC3 starts at: descriptor queue 80
3647                                  * Tx TC4 starts at: descriptor queue 96
3648                                  * Tx TC5 starts at: descriptor queue 104
3649                                  * Tx TC6 starts at: descriptor queue 112
3650                                  * Tx TC7 starts at: descriptor queue 120
3651                                  *
3652                                  * Rx TC0-TC7 are offset by 16 queues each
3653                                  */
3654                                 for (i = 0; i < 3; i++) {
3655                                         adapter->tx_ring[i]->reg_idx = i << 5;
3656                                         adapter->rx_ring[i]->reg_idx = i << 4;
3657                                 }
3658                                 for ( ; i < 5; i++) {
3659                                         adapter->tx_ring[i]->reg_idx =
3660                                                                  ((i + 2) << 4);
3661                                         adapter->rx_ring[i]->reg_idx = i << 4;
3662                                 }
3663                                 for ( ; i < dcb_i; i++) {
3664                                         adapter->tx_ring[i]->reg_idx =
3665                                                                  ((i + 8) << 3);
3666                                         adapter->rx_ring[i]->reg_idx = i << 4;
3667                                 }
3668
3669                                 ret = true;
3670                         } else if (dcb_i == 4) {
3671                                 /*
3672                                  * Tx TC0 starts at: descriptor queue 0
3673                                  * Tx TC1 starts at: descriptor queue 64
3674                                  * Tx TC2 starts at: descriptor queue 96
3675                                  * Tx TC3 starts at: descriptor queue 112
3676                                  *
3677                                  * Rx TC0-TC3 are offset by 32 queues each
3678                                  */
3679                                 adapter->tx_ring[0]->reg_idx = 0;
3680                                 adapter->tx_ring[1]->reg_idx = 64;
3681                                 adapter->tx_ring[2]->reg_idx = 96;
3682                                 adapter->tx_ring[3]->reg_idx = 112;
3683                                 for (i = 0 ; i < dcb_i; i++)
3684                                         adapter->rx_ring[i]->reg_idx = i << 5;
3685
3686                                 ret = true;
3687                         } else {
3688                                 ret = false;
3689                         }
3690                 } else {
3691                         ret = false;
3692                 }
3693         } else {
3694                 ret = false;
3695         }
3696
3697         return ret;
3698 }
3699 #endif
3700
3701 /**
3702  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3703  * @adapter: board private structure to initialize
3704  *
3705  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3706  *
3707  **/
3708 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3709 {
3710         int i;
3711         bool ret = false;
3712
3713         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3714             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3715              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3716                 for (i = 0; i < adapter->num_rx_queues; i++)
3717                         adapter->rx_ring[i]->reg_idx = i;
3718                 for (i = 0; i < adapter->num_tx_queues; i++)
3719                         adapter->tx_ring[i]->reg_idx = i;
3720                 ret = true;
3721         }
3722
3723         return ret;
3724 }
3725
3726 #ifdef IXGBE_FCOE
3727 /**
3728  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3729  * @adapter: board private structure to initialize
3730  *
3731  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3732  *
3733  */
3734 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3735 {
3736         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
3737         bool ret = false;
3738         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3739
3740         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3741 #ifdef CONFIG_IXGBE_DCB
3742                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3743                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3744
3745                         ixgbe_cache_ring_dcb(adapter);
3746                         /* find out queues in TC for FCoE */
3747                         fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
3748                         fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
3749                         /*
3750                          * In 82599, the number of Tx queues for each traffic
3751                          * class for both 8-TC and 4-TC modes are:
3752                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3753                          * 8 TCs:  32  32  16  16   8   8   8   8
3754                          * 4 TCs:  64  64  32  32
3755                          * We have max 8 queues for FCoE, where 8 the is
3756                          * FCoE redirection table size. If TC for FCoE is
3757                          * less than or equal to TC3, we have enough queues
3758                          * to add max of 8 queues for FCoE, so we start FCoE
3759                          * tx descriptor from the next one, i.e., reg_idx + 1.
3760                          * If TC for FCoE is above TC3, implying 8 TC mode,
3761                          * and we need 8 for FCoE, we have to take all queues
3762                          * in that traffic class for FCoE.
3763                          */
3764                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3765                                 fcoe_tx_i--;
3766                 }
3767 #endif /* CONFIG_IXGBE_DCB */
3768                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3769                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3770                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3771                                 ixgbe_cache_ring_fdir(adapter);
3772                         else
3773                                 ixgbe_cache_ring_rss(adapter);
3774
3775                         fcoe_rx_i = f->mask;
3776                         fcoe_tx_i = f->mask;
3777                 }
3778                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3779                         adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
3780                         adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
3781                 }
3782                 ret = true;
3783         }
3784         return ret;
3785 }
3786
3787 #endif /* IXGBE_FCOE */
3788 /**
3789  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
3790  * @adapter: board private structure to initialize
3791  *
3792  * SR-IOV doesn't use any descriptor rings but changes the default if
3793  * no other mapping is used.
3794  *
3795  */
3796 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
3797 {
3798         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
3799         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
3800         if (adapter->num_vfs)
3801                 return true;
3802         else
3803                 return false;
3804 }
3805
3806 /**
3807  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3808  * @adapter: board private structure to initialize
3809  *
3810  * Once we know the feature-set enabled for the device, we'll cache
3811  * the register offset the descriptor ring is assigned to.
3812  *
3813  * Note, the order the various feature calls is important.  It must start with
3814  * the "most" features enabled at the same time, then trickle down to the
3815  * least amount of features turned on at once.
3816  **/
3817 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3818 {
3819         /* start with default case */
3820         adapter->rx_ring[0]->reg_idx = 0;
3821         adapter->tx_ring[0]->reg_idx = 0;
3822
3823         if (ixgbe_cache_ring_sriov(adapter))
3824                 return;
3825
3826 #ifdef IXGBE_FCOE
3827         if (ixgbe_cache_ring_fcoe(adapter))
3828                 return;
3829
3830 #endif /* IXGBE_FCOE */
3831 #ifdef CONFIG_IXGBE_DCB
3832         if (ixgbe_cache_ring_dcb(adapter))
3833                 return;
3834
3835 #endif
3836         if (ixgbe_cache_ring_fdir(adapter))
3837                 return;
3838
3839         if (ixgbe_cache_ring_rss(adapter))
3840                 return;
3841 }
3842
3843 /**
3844  * ixgbe_alloc_queues - Allocate memory for all rings
3845  * @adapter: board private structure to initialize
3846  *
3847  * We allocate one ring per queue at run-time since we don't know the
3848  * number of queues at compile-time.  The polling_netdev array is
3849  * intended for Multiqueue, but should work fine with a single queue.
3850  **/
3851 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3852 {
3853         int i;
3854         int orig_node = adapter->node;
3855
3856         for (i = 0; i < adapter->num_tx_queues; i++) {
3857                 struct ixgbe_ring *ring = adapter->tx_ring[i];
3858                 if (orig_node == -1) {
3859                         int cur_node = next_online_node(adapter->node);
3860                         if (cur_node == MAX_NUMNODES)
3861                                 cur_node = first_online_node;
3862                         adapter->node = cur_node;
3863                 }
3864                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3865                                     adapter->node);
3866                 if (!ring)
3867                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3868                 if (!ring)
3869                         goto err_tx_ring_allocation;
3870                 ring->count = adapter->tx_ring_count;
3871                 ring->queue_index = i;
3872                 ring->numa_node = adapter->node;
3873
3874                 adapter->tx_ring[i] = ring;
3875         }
3876
3877         /* Restore the adapter's original node */
3878         adapter->node = orig_node;
3879
3880         for (i = 0; i < adapter->num_rx_queues; i++) {
3881                 struct ixgbe_ring *ring = adapter->rx_ring[i];
3882                 if (orig_node == -1) {
3883                         int cur_node = next_online_node(adapter->node);
3884                         if (cur_node == MAX_NUMNODES)
3885                                 cur_node = first_online_node;
3886                         adapter->node = cur_node;
3887                 }
3888                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3889                                     adapter->node);
3890                 if (!ring)
3891                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3892                 if (!ring)
3893                         goto err_rx_ring_allocation;
3894                 ring->count = adapter->rx_ring_count;
3895                 ring->queue_index = i;
3896                 ring->numa_node = adapter->node;
3897
3898                 adapter->rx_ring[i] = ring;
3899         }
3900
3901         /* Restore the adapter's original node */
3902         adapter->node = orig_node;
3903
3904         ixgbe_cache_ring_register(adapter);
3905
3906         return 0;
3907
3908 err_rx_ring_allocation:
3909         for (i = 0; i < adapter->num_tx_queues; i++)
3910                 kfree(adapter->tx_ring[i]);
3911 err_tx_ring_allocation:
3912         return -ENOMEM;
3913 }
3914
3915 /**
3916  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3917  * @adapter: board private structure to initialize
3918  *
3919  * Attempt to configure the interrupts using the best available
3920  * capabilities of the hardware and the kernel.
3921  **/
3922 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3923 {
3924         struct ixgbe_hw *hw = &adapter->hw;
3925         int err = 0;
3926         int vector, v_budget;
3927
3928         /*
3929          * It's easy to be greedy for MSI-X vectors, but it really
3930          * doesn't do us much good if we have a lot more vectors
3931          * than CPU's.  So let's be conservative and only ask for
3932          * (roughly) the same number of vectors as there are CPU's.
3933          */
3934         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3935                        (int)num_online_cpus()) + NON_Q_VECTORS;
3936
3937         /*
3938          * At the same time, hardware can only support a maximum of
3939          * hw.mac->max_msix_vectors vectors.  With features
3940          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3941          * descriptor queues supported by our device.  Thus, we cap it off in
3942          * those rare cases where the cpu count also exceeds our vector limit.
3943          */
3944         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3945
3946         /* A failure in MSI-X entry allocation isn't fatal, but it does
3947          * mean we disable MSI-X capabilities of the adapter. */
3948         adapter->msix_entries = kcalloc(v_budget,
3949                                         sizeof(struct msix_entry), GFP_KERNEL);
3950         if (adapter->msix_entries) {
3951                 for (vector = 0; vector < v_budget; vector++)
3952                         adapter->msix_entries[vector].entry = vector;
3953
3954                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3955
3956                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3957                         goto out;
3958         }
3959
3960         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3961         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3962         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3963         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3964         adapter->atr_sample_rate = 0;
3965         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3966                 ixgbe_disable_sriov(adapter);
3967
3968         ixgbe_set_num_queues(adapter);
3969
3970         err = pci_enable_msi(adapter->pdev);
3971         if (!err) {
3972                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3973         } else {
3974                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3975                         "falling back to legacy.  Error: %d\n", err);
3976                 /* reset err */
3977                 err = 0;
3978         }
3979
3980 out:
3981         return err;
3982 }
3983
3984 /**
3985  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3986  * @adapter: board private structure to initialize
3987  *
3988  * We allocate one q_vector per queue interrupt.  If allocation fails we
3989  * return -ENOMEM.
3990  **/
3991 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3992 {
3993         int q_idx, num_q_vectors;
3994         struct ixgbe_q_vector *q_vector;
3995         int napi_vectors;
3996         int (*poll)(struct napi_struct *, int);
3997
3998         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3999                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4000                 napi_vectors = adapter->num_rx_queues;
4001                 poll = &ixgbe_clean_rxtx_many;
4002         } else {
4003                 num_q_vectors = 1;
4004                 napi_vectors = 1;
4005                 poll = &ixgbe_poll;
4006         }
4007
4008         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4009                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4010                                         GFP_KERNEL, adapter->node);
4011                 if (!q_vector)
4012                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4013                                            GFP_KERNEL);
4014                 if (!q_vector)
4015                         goto err_out;
4016                 q_vector->adapter = adapter;
4017                 if (q_vector->txr_count && !q_vector->rxr_count)
4018                         q_vector->eitr = adapter->tx_eitr_param;
4019                 else
4020                         q_vector->eitr = adapter->rx_eitr_param;
4021                 q_vector->v_idx = q_idx;
4022                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4023                 adapter->q_vector[q_idx] = q_vector;
4024         }
4025
4026         return 0;
4027
4028 err_out:
4029         while (q_idx) {
4030                 q_idx--;
4031                 q_vector = adapter->q_vector[q_idx];
4032                 netif_napi_del(&q_vector->napi);
4033                 kfree(q_vector);
4034                 adapter->q_vector[q_idx] = NULL;
4035         }
4036         return -ENOMEM;
4037 }
4038
4039 /**
4040  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4041  * @adapter: board private structure to initialize
4042  *
4043  * This function frees the memory allocated to the q_vectors.  In addition if
4044  * NAPI is enabled it will delete any references to the NAPI struct prior
4045  * to freeing the q_vector.
4046  **/
4047 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4048 {
4049         int q_idx, num_q_vectors;
4050
4051         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4052                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4053         else
4054                 num_q_vectors = 1;
4055
4056         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4057                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4058                 adapter->q_vector[q_idx] = NULL;
4059                 netif_napi_del(&q_vector->napi);
4060                 kfree(q_vector);
4061         }
4062 }
4063
4064 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4065 {
4066         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4067                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4068                 pci_disable_msix(adapter->pdev);
4069                 kfree(adapter->msix_entries);
4070                 adapter->msix_entries = NULL;
4071         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4072                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4073                 pci_disable_msi(adapter->pdev);
4074         }
4075         return;
4076 }
4077
4078 /**
4079  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4080  * @adapter: board private structure to initialize
4081  *
4082  * We determine which interrupt scheme to use based on...
4083  * - Kernel support (MSI, MSI-X)
4084  *   - which can be user-defined (via MODULE_PARAM)
4085  * - Hardware queue count (num_*_queues)
4086  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4087  **/
4088 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4089 {
4090         int err;
4091
4092         /* Number of supported queues */
4093         ixgbe_set_num_queues(adapter);
4094
4095         err = ixgbe_set_interrupt_capability(adapter);
4096         if (err) {
4097                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
4098                 goto err_set_interrupt;
4099         }
4100
4101         err = ixgbe_alloc_q_vectors(adapter);
4102         if (err) {
4103                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
4104                         "vectors\n");
4105                 goto err_alloc_q_vectors;
4106         }
4107
4108         err = ixgbe_alloc_queues(adapter);
4109         if (err) {
4110                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
4111                 goto err_alloc_queues;
4112         }
4113
4114         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
4115                 "Tx Queue count = %u\n",
4116                 (adapter->num_rx_queues > 1) ? "Enabled" :
4117                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
4118
4119         set_bit(__IXGBE_DOWN, &adapter->state);
4120
4121         return 0;
4122
4123 err_alloc_queues:
4124         ixgbe_free_q_vectors(adapter);
4125 err_alloc_q_vectors:
4126         ixgbe_reset_interrupt_capability(adapter);
4127 err_set_interrupt:
4128         return err;
4129 }
4130
4131 /**
4132  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4133  * @adapter: board private structure to clear interrupt scheme on
4134  *
4135  * We go through and clear interrupt specific resources and reset the structure
4136  * to pre-load conditions
4137  **/
4138 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4139 {
4140         int i;
4141
4142         for (i = 0; i < adapter->num_tx_queues; i++) {
4143                 kfree(adapter->tx_ring[i]);
4144                 adapter->tx_ring[i] = NULL;
4145         }
4146         for (i = 0; i < adapter->num_rx_queues; i++) {
4147                 kfree(adapter->rx_ring[i]);
4148                 adapter->rx_ring[i] = NULL;
4149         }
4150
4151         ixgbe_free_q_vectors(adapter);
4152         ixgbe_reset_interrupt_capability(adapter);
4153 }
4154
4155 /**
4156  * ixgbe_sfp_timer - worker thread to find a missing module
4157  * @data: pointer to our adapter struct
4158  **/
4159 static void ixgbe_sfp_timer(unsigned long data)
4160 {
4161         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4162
4163         /*
4164          * Do the sfp_timer outside of interrupt context due to the
4165          * delays that sfp+ detection requires
4166          */
4167         schedule_work(&adapter->sfp_task);
4168 }
4169
4170 /**
4171  * ixgbe_sfp_task - worker thread to find a missing module
4172  * @work: pointer to work_struct containing our data
4173  **/
4174 static void ixgbe_sfp_task(struct work_struct *work)
4175 {
4176         struct ixgbe_adapter *adapter = container_of(work,
4177                                                      struct ixgbe_adapter,
4178                                                      sfp_task);
4179         struct ixgbe_hw *hw = &adapter->hw;
4180
4181         if ((hw->phy.type == ixgbe_phy_nl) &&
4182             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4183                 s32 ret = hw->phy.ops.identify_sfp(hw);
4184                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4185                         goto reschedule;
4186                 ret = hw->phy.ops.reset(hw);
4187                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4188                         dev_err(&adapter->pdev->dev, "failed to initialize "
4189                                 "because an unsupported SFP+ module type "
4190                                 "was detected.\n"
4191                                 "Reload the driver after installing a "
4192                                 "supported module.\n");
4193                         unregister_netdev(adapter->netdev);
4194                 } else {
4195                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
4196                                 hw->phy.sfp_type);
4197                 }
4198                 /* don't need this routine any more */
4199                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4200         }
4201         return;
4202 reschedule:
4203         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4204                 mod_timer(&adapter->sfp_timer,
4205                           round_jiffies(jiffies + (2 * HZ)));
4206 }
4207
4208 /**
4209  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4210  * @adapter: board private structure to initialize
4211  *
4212  * ixgbe_sw_init initializes the Adapter private data structure.
4213  * Fields are initialized based on PCI device information and
4214  * OS network device settings (MTU size).
4215  **/
4216 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4217 {
4218         struct ixgbe_hw *hw = &adapter->hw;
4219         struct pci_dev *pdev = adapter->pdev;
4220         struct net_device *dev = adapter->netdev;
4221         unsigned int rss;
4222 #ifdef CONFIG_IXGBE_DCB
4223         int j;
4224         struct tc_configuration *tc;
4225 #endif
4226
4227         /* PCI config space info */
4228
4229         hw->vendor_id = pdev->vendor;
4230         hw->device_id = pdev->device;
4231         hw->revision_id = pdev->revision;
4232         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4233         hw->subsystem_device_id = pdev->subsystem_device;
4234
4235         /* Set capability flags */
4236         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4237         adapter->ring_feature[RING_F_RSS].indices = rss;
4238         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4239         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4240         if (hw->mac.type == ixgbe_mac_82598EB) {
4241                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4242                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4243                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4244         } else if (hw->mac.type == ixgbe_mac_82599EB) {
4245                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4246                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4247                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4248                 if (dev->features & NETIF_F_NTUPLE) {
4249                         /* Flow Director perfect filter enabled */
4250                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4251                         adapter->atr_sample_rate = 0;
4252                         spin_lock_init(&adapter->fdir_perfect_lock);
4253                 } else {
4254                         /* Flow Director hash filters enabled */
4255                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4256                         adapter->atr_sample_rate = 20;
4257                 }
4258                 adapter->ring_feature[RING_F_FDIR].indices =
4259                                                          IXGBE_MAX_FDIR_INDICES;
4260                 adapter->fdir_pballoc = 0;
4261 #ifdef IXGBE_FCOE
4262                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4263                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4264                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4265 #ifdef CONFIG_IXGBE_DCB
4266                 /* Default traffic class to use for FCoE */
4267                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4268 #endif
4269 #endif /* IXGBE_FCOE */
4270         }
4271
4272 #ifdef CONFIG_IXGBE_DCB
4273         /* Configure DCB traffic classes */
4274         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4275                 tc = &adapter->dcb_cfg.tc_config[j];
4276                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4277                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4278                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4279                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4280                 tc->dcb_pfc = pfc_disabled;
4281         }
4282         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4283         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4284         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4285         adapter->dcb_cfg.pfc_mode_enable = false;
4286         adapter->dcb_cfg.round_robin_enable = false;
4287         adapter->dcb_set_bitmap = 0x00;
4288         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4289                            adapter->ring_feature[RING_F_DCB].indices);
4290
4291 #endif
4292
4293         /* default flow control settings */
4294         hw->fc.requested_mode = ixgbe_fc_full;
4295         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4296 #ifdef CONFIG_DCB
4297         adapter->last_lfc_mode = hw->fc.current_mode;
4298 #endif
4299         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4300         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4301         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4302         hw->fc.send_xon = true;
4303         hw->fc.disable_fc_autoneg = false;
4304
4305         /* enable itr by default in dynamic mode */
4306         adapter->rx_itr_setting = 1;
4307         adapter->rx_eitr_param = 20000;
4308         adapter->tx_itr_setting = 1;
4309         adapter->tx_eitr_param = 10000;
4310
4311         /* set defaults for eitr in MegaBytes */
4312         adapter->eitr_low = 10;
4313         adapter->eitr_high = 20;
4314
4315         /* set default ring sizes */
4316         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4317         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4318
4319         /* initialize eeprom parameters */
4320         if (ixgbe_init_eeprom_params_generic(hw)) {
4321                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4322                 return -EIO;
4323         }
4324
4325         /* enable rx csum by default */
4326         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4327
4328         /* get assigned NUMA node */
4329         adapter->node = dev_to_node(&pdev->dev);
4330
4331         set_bit(__IXGBE_DOWN, &adapter->state);
4332
4333         return 0;
4334 }
4335
4336 /**
4337  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4338  * @adapter: board private structure
4339  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4340  *
4341  * Return 0 on success, negative on failure
4342  **/
4343 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4344                              struct ixgbe_ring *tx_ring)
4345 {
4346         struct pci_dev *pdev = adapter->pdev;
4347         int size;
4348
4349         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4350         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4351         if (!tx_ring->tx_buffer_info)
4352                 tx_ring->tx_buffer_info = vmalloc(size);
4353         if (!tx_ring->tx_buffer_info)
4354                 goto err;
4355         memset(tx_ring->tx_buffer_info, 0, size);
4356
4357         /* round up to nearest 4K */
4358         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4359         tx_ring->size = ALIGN(tx_ring->size, 4096);
4360
4361         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4362                                              &tx_ring->dma);
4363         if (!tx_ring->desc)
4364                 goto err;
4365
4366         tx_ring->next_to_use = 0;
4367         tx_ring->next_to_clean = 0;
4368         tx_ring->work_limit = tx_ring->count;
4369         return 0;
4370
4371 err:
4372         vfree(tx_ring->tx_buffer_info);
4373         tx_ring->tx_buffer_info = NULL;
4374         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4375                             "descriptor ring\n");
4376         return -ENOMEM;
4377 }
4378
4379 /**
4380  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4381  * @adapter: board private structure
4382  *
4383  * If this function returns with an error, then it's possible one or
4384  * more of the rings is populated (while the rest are not).  It is the
4385  * callers duty to clean those orphaned rings.
4386  *
4387  * Return 0 on success, negative on failure
4388  **/
4389 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4390 {
4391         int i, err = 0;
4392
4393         for (i = 0; i < adapter->num_tx_queues; i++) {
4394                 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
4395                 if (!err)
4396                         continue;
4397                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4398                 break;
4399         }
4400
4401         return err;
4402 }
4403
4404 /**
4405  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4406  * @adapter: board private structure
4407  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4408  *
4409  * Returns 0 on success, negative on failure
4410  **/
4411 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4412                              struct ixgbe_ring *rx_ring)
4413 {
4414         struct pci_dev *pdev = adapter->pdev;
4415         int size;
4416
4417         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4418         rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4419         if (!rx_ring->rx_buffer_info)
4420                 rx_ring->rx_buffer_info = vmalloc(size);
4421         if (!rx_ring->rx_buffer_info) {
4422                 DPRINTK(PROBE, ERR,
4423                         "vmalloc allocation failed for the rx desc ring\n");
4424                 goto alloc_failed;
4425         }
4426         memset(rx_ring->rx_buffer_info, 0, size);
4427
4428         /* Round up to nearest 4K */
4429         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4430         rx_ring->size = ALIGN(rx_ring->size, 4096);
4431
4432         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
4433
4434         if (!rx_ring->desc) {
4435                 DPRINTK(PROBE, ERR,
4436                         "Memory allocation failed for the rx desc ring\n");
4437                 vfree(rx_ring->rx_buffer_info);
4438                 goto alloc_failed;
4439         }
4440
4441         rx_ring->next_to_clean = 0;
4442         rx_ring->next_to_use = 0;
4443
4444         return 0;
4445
4446 alloc_failed:
4447         return -ENOMEM;
4448 }
4449
4450 /**
4451  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4452  * @adapter: board private structure
4453  *
4454  * If this function returns with an error, then it's possible one or
4455  * more of the rings is populated (while the rest are not).  It is the
4456  * callers duty to clean those orphaned rings.
4457  *
4458  * Return 0 on success, negative on failure
4459  **/
4460
4461 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4462 {
4463         int i, err = 0;
4464
4465         for (i = 0; i < adapter->num_rx_queues; i++) {
4466                 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
4467                 if (!err)
4468                         continue;
4469                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4470                 break;
4471         }
4472
4473         return err;
4474 }
4475
4476 /**
4477  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4478  * @adapter: board private structure
4479  * @tx_ring: Tx descriptor ring for a specific queue
4480  *
4481  * Free all transmit software resources
4482  **/
4483 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4484                              struct ixgbe_ring *tx_ring)
4485 {
4486         struct pci_dev *pdev = adapter->pdev;
4487
4488         ixgbe_clean_tx_ring(adapter, tx_ring);
4489
4490         vfree(tx_ring->tx_buffer_info);
4491         tx_ring->tx_buffer_info = NULL;
4492
4493         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4494
4495         tx_ring->desc = NULL;
4496 }
4497
4498 /**
4499  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4500  * @adapter: board private structure
4501  *
4502  * Free all transmit software resources
4503  **/
4504 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4505 {
4506         int i;
4507
4508         for (i = 0; i < adapter->num_tx_queues; i++)
4509                 if (adapter->tx_ring[i]->desc)
4510                         ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
4511 }
4512
4513 /**
4514  * ixgbe_free_rx_resources - Free Rx Resources
4515  * @adapter: board private structure
4516  * @rx_ring: ring to clean the resources from
4517  *
4518  * Free all receive software resources
4519  **/
4520 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4521                              struct ixgbe_ring *rx_ring)
4522 {
4523         struct pci_dev *pdev = adapter->pdev;
4524
4525         ixgbe_clean_rx_ring(adapter, rx_ring);
4526
4527         vfree(rx_ring->rx_buffer_info);
4528         rx_ring->rx_buffer_info = NULL;
4529
4530         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4531
4532         rx_ring->desc = NULL;
4533 }
4534
4535 /**
4536  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4537  * @adapter: board private structure
4538  *
4539  * Free all receive software resources
4540  **/
4541 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4542 {
4543         int i;
4544
4545         for (i = 0; i < adapter->num_rx_queues; i++)
4546                 if (adapter->rx_ring[i]->desc)
4547                         ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
4548 }
4549
4550 /**
4551  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4552  * @netdev: network interface device structure
4553  * @new_mtu: new value for maximum frame size
4554  *
4555  * Returns 0 on success, negative on failure
4556  **/
4557 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4558 {
4559         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4560         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4561
4562         /* MTU < 68 is an error and causes problems on some kernels */
4563         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4564                 return -EINVAL;
4565
4566         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4567                 netdev->mtu, new_mtu);
4568         /* must set new MTU before calling down or up */
4569         netdev->mtu = new_mtu;
4570
4571         if (netif_running(netdev))
4572                 ixgbe_reinit_locked(adapter);
4573
4574         return 0;
4575 }
4576
4577 /**
4578  * ixgbe_open - Called when a network interface is made active
4579  * @netdev: network interface device structure
4580  *
4581  * Returns 0 on success, negative value on failure
4582  *
4583  * The open entry point is called when a network interface is made
4584  * active by the system (IFF_UP).  At this point all resources needed
4585  * for transmit and receive operations are allocated, the interrupt
4586  * handler is registered with the OS, the watchdog timer is started,
4587  * and the stack is notified that the interface is ready.
4588  **/
4589 static int ixgbe_open(struct net_device *netdev)
4590 {
4591         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4592         int err;
4593
4594         /* disallow open during test */
4595         if (test_bit(__IXGBE_TESTING, &adapter->state))
4596                 return -EBUSY;
4597
4598         netif_carrier_off(netdev);
4599
4600         /* allocate transmit descriptors */
4601         err = ixgbe_setup_all_tx_resources(adapter);
4602         if (err)
4603                 goto err_setup_tx;
4604
4605         /* allocate receive descriptors */
4606         err = ixgbe_setup_all_rx_resources(adapter);
4607         if (err)
4608                 goto err_setup_rx;
4609
4610         ixgbe_configure(adapter);
4611
4612         err = ixgbe_request_irq(adapter);
4613         if (err)
4614                 goto err_req_irq;
4615
4616         err = ixgbe_up_complete(adapter);
4617         if (err)
4618                 goto err_up;
4619
4620         netif_tx_start_all_queues(netdev);
4621
4622         return 0;
4623
4624 err_up:
4625         ixgbe_release_hw_control(adapter);
4626         ixgbe_free_irq(adapter);
4627 err_req_irq:
4628 err_setup_rx:
4629         ixgbe_free_all_rx_resources(adapter);
4630 err_setup_tx:
4631         ixgbe_free_all_tx_resources(adapter);
4632         ixgbe_reset(adapter);
4633
4634         return err;
4635 }
4636
4637 /**
4638  * ixgbe_close - Disables a network interface
4639  * @netdev: network interface device structure
4640  *
4641  * Returns 0, this is not allowed to fail
4642  *
4643  * The close entry point is called when an interface is de-activated
4644  * by the OS.  The hardware is still under the drivers control, but
4645  * needs to be disabled.  A global MAC reset is issued to stop the
4646  * hardware, and all transmit and receive resources are freed.
4647  **/
4648 static int ixgbe_close(struct net_device *netdev)
4649 {
4650         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4651
4652         ixgbe_down(adapter);
4653         ixgbe_free_irq(adapter);
4654
4655         ixgbe_free_all_tx_resources(adapter);
4656         ixgbe_free_all_rx_resources(adapter);
4657
4658         ixgbe_release_hw_control(adapter);
4659
4660         return 0;
4661 }
4662
4663 #ifdef CONFIG_PM
4664 static int ixgbe_resume(struct pci_dev *pdev)
4665 {
4666         struct net_device *netdev = pci_get_drvdata(pdev);
4667         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4668         u32 err;
4669
4670         pci_set_power_state(pdev, PCI_D0);
4671         pci_restore_state(pdev);
4672         /*
4673          * pci_restore_state clears dev->state_saved so call
4674          * pci_save_state to restore it.
4675          */
4676         pci_save_state(pdev);
4677
4678         err = pci_enable_device_mem(pdev);
4679         if (err) {
4680                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4681                                 "suspend\n");
4682                 return err;
4683         }
4684         pci_set_master(pdev);
4685
4686         pci_wake_from_d3(pdev, false);
4687
4688         err = ixgbe_init_interrupt_scheme(adapter);
4689         if (err) {
4690                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4691                                 "device\n");
4692                 return err;
4693         }
4694
4695         ixgbe_reset(adapter);
4696
4697         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4698
4699         if (netif_running(netdev)) {
4700                 err = ixgbe_open(adapter->netdev);
4701                 if (err)
4702                         return err;
4703         }
4704
4705         netif_device_attach(netdev);
4706
4707         return 0;
4708 }
4709 #endif /* CONFIG_PM */
4710
4711 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4712 {
4713         struct net_device *netdev = pci_get_drvdata(pdev);
4714         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4715         struct ixgbe_hw *hw = &adapter->hw;
4716         u32 ctrl, fctrl;
4717         u32 wufc = adapter->wol;
4718 #ifdef CONFIG_PM
4719         int retval = 0;
4720 #endif
4721
4722         netif_device_detach(netdev);
4723
4724         if (netif_running(netdev)) {
4725                 ixgbe_down(adapter);
4726                 ixgbe_free_irq(adapter);
4727                 ixgbe_free_all_tx_resources(adapter);
4728                 ixgbe_free_all_rx_resources(adapter);
4729         }
4730         ixgbe_clear_interrupt_scheme(adapter);
4731
4732 #ifdef CONFIG_PM
4733         retval = pci_save_state(pdev);
4734         if (retval)
4735                 return retval;
4736
4737 #endif
4738         if (wufc) {
4739                 ixgbe_set_rx_mode(netdev);
4740
4741                 /* turn on all-multi mode if wake on multicast is enabled */
4742                 if (wufc & IXGBE_WUFC_MC) {
4743                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4744                         fctrl |= IXGBE_FCTRL_MPE;
4745                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4746                 }
4747
4748                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4749                 ctrl |= IXGBE_CTRL_GIO_DIS;
4750                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4751
4752                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4753         } else {
4754                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4755                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4756         }
4757
4758         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4759                 pci_wake_from_d3(pdev, true);
4760         else
4761                 pci_wake_from_d3(pdev, false);
4762
4763         *enable_wake = !!wufc;
4764
4765         ixgbe_release_hw_control(adapter);
4766
4767         pci_disable_device(pdev);
4768
4769         return 0;
4770 }
4771
4772 #ifdef CONFIG_PM
4773 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4774 {
4775         int retval;
4776         bool wake;
4777
4778         retval = __ixgbe_shutdown(pdev, &wake);
4779         if (retval)
4780                 return retval;
4781
4782         if (wake) {
4783                 pci_prepare_to_sleep(pdev);
4784         } else {
4785                 pci_wake_from_d3(pdev, false);
4786                 pci_set_power_state(pdev, PCI_D3hot);
4787         }
4788
4789         return 0;
4790 }
4791 #endif /* CONFIG_PM */
4792
4793 static void ixgbe_shutdown(struct pci_dev *pdev)
4794 {
4795         bool wake;
4796
4797         __ixgbe_shutdown(pdev, &wake);
4798
4799         if (system_state == SYSTEM_POWER_OFF) {
4800                 pci_wake_from_d3(pdev, wake);
4801                 pci_set_power_state(pdev, PCI_D3hot);
4802         }
4803 }
4804
4805 /**
4806  * ixgbe_update_stats - Update the board statistics counters.
4807  * @adapter: board private structure
4808  **/
4809 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4810 {
4811         struct net_device *netdev = adapter->netdev;
4812         struct ixgbe_hw *hw = &adapter->hw;
4813         u64 total_mpc = 0;
4814         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4815         u64 non_eop_descs = 0, restart_queue = 0;
4816
4817         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
4818                 u64 rsc_count = 0;
4819                 u64 rsc_flush = 0;
4820                 for (i = 0; i < 16; i++)
4821                         adapter->hw_rx_no_dma_resources +=
4822                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4823                 for (i = 0; i < adapter->num_rx_queues; i++) {
4824                         rsc_count += adapter->rx_ring[i]->rsc_count;
4825                         rsc_flush += adapter->rx_ring[i]->rsc_flush;
4826                 }
4827                 adapter->rsc_total_count = rsc_count;
4828                 adapter->rsc_total_flush = rsc_flush;
4829         }
4830
4831         /* gather some stats to the adapter struct that are per queue */
4832         for (i = 0; i < adapter->num_tx_queues; i++)
4833                 restart_queue += adapter->tx_ring[i]->restart_queue;
4834         adapter->restart_queue = restart_queue;
4835
4836         for (i = 0; i < adapter->num_rx_queues; i++)
4837                 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
4838         adapter->non_eop_descs = non_eop_descs;
4839
4840         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4841         for (i = 0; i < 8; i++) {
4842                 /* for packet buffers not used, the register should read 0 */
4843                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4844                 missed_rx += mpc;
4845                 adapter->stats.mpc[i] += mpc;
4846                 total_mpc += adapter->stats.mpc[i];
4847                 if (hw->mac.type == ixgbe_mac_82598EB)
4848                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4849                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4850                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4851                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4852                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4853                 if (hw->mac.type == ixgbe_mac_82599EB) {
4854                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4855                                                             IXGBE_PXONRXCNT(i));
4856                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4857                                                            IXGBE_PXOFFRXCNT(i));
4858                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4859                 } else {
4860                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4861                                                               IXGBE_PXONRXC(i));
4862                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4863                                                              IXGBE_PXOFFRXC(i));
4864                 }
4865                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4866                                                             IXGBE_PXONTXC(i));
4867                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4868                                                              IXGBE_PXOFFTXC(i));
4869         }
4870         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4871         /* work around hardware counting issue */
4872         adapter->stats.gprc -= missed_rx;
4873
4874         /* 82598 hardware only has a 32 bit counter in the high register */
4875         if (hw->mac.type == ixgbe_mac_82599EB) {
4876                 u64 tmp;
4877                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4878                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4879                 adapter->stats.gorc += (tmp << 32);
4880                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4881                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4882                 adapter->stats.gotc += (tmp << 32);
4883                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4884                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4885                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4886                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4887                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4888                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4889 #ifdef IXGBE_FCOE
4890                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4891                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4892                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4893                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4894                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4895                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4896 #endif /* IXGBE_FCOE */
4897         } else {
4898                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4899                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4900                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4901                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4902                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4903         }
4904         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4905         adapter->stats.bprc += bprc;
4906         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4907         if (hw->mac.type == ixgbe_mac_82598EB)
4908                 adapter->stats.mprc -= bprc;
4909         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4910         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4911         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4912         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4913         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4914         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4915         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4916         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4917         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4918         adapter->stats.lxontxc += lxon;
4919         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4920         adapter->stats.lxofftxc += lxoff;
4921         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4922         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4923         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4924         /*
4925          * 82598 errata - tx of flow control packets is included in tx counters
4926          */
4927         xon_off_tot = lxon + lxoff;
4928         adapter->stats.gptc -= xon_off_tot;
4929         adapter->stats.mptc -= xon_off_tot;
4930         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4931         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4932         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4933         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4934         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4935         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4936         adapter->stats.ptc64 -= xon_off_tot;
4937         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4938         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4939         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4940         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4941         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4942         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4943
4944         /* Fill out the OS statistics structure */
4945         netdev->stats.multicast = adapter->stats.mprc;
4946
4947         /* Rx Errors */
4948         netdev->stats.rx_errors = adapter->stats.crcerrs +
4949                                        adapter->stats.rlec;
4950         netdev->stats.rx_dropped = 0;
4951         netdev->stats.rx_length_errors = adapter->stats.rlec;
4952         netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4953         netdev->stats.rx_missed_errors = total_mpc;
4954 }
4955
4956 /**
4957  * ixgbe_watchdog - Timer Call-back
4958  * @data: pointer to adapter cast into an unsigned long
4959  **/
4960 static void ixgbe_watchdog(unsigned long data)
4961 {
4962         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4963         struct ixgbe_hw *hw = &adapter->hw;
4964         u64 eics = 0;
4965         int i;
4966
4967         /*
4968          *  Do the watchdog outside of interrupt context due to the lovely
4969          * delays that some of the newer hardware requires
4970          */
4971
4972         if (test_bit(__IXGBE_DOWN, &adapter->state))
4973                 goto watchdog_short_circuit;
4974
4975         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4976                 /*
4977                  * for legacy and MSI interrupts don't set any bits
4978                  * that are enabled for EIAM, because this operation
4979                  * would set *both* EIMS and EICS for any bit in EIAM
4980                  */
4981                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4982                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4983                 goto watchdog_reschedule;
4984         }
4985
4986         /* get one bit for every active tx/rx interrupt vector */
4987         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4988                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4989                 if (qv->rxr_count || qv->txr_count)
4990                         eics |= ((u64)1 << i);
4991         }
4992
4993         /* Cause software interrupt to ensure rx rings are cleaned */
4994         ixgbe_irq_rearm_queues(adapter, eics);
4995
4996 watchdog_reschedule:
4997         /* Reset the timer */
4998         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4999
5000 watchdog_short_circuit:
5001         schedule_work(&adapter->watchdog_task);
5002 }
5003
5004 /**
5005  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5006  * @work: pointer to work_struct containing our data
5007  **/
5008 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5009 {
5010         struct ixgbe_adapter *adapter = container_of(work,
5011                                                      struct ixgbe_adapter,
5012                                                      multispeed_fiber_task);
5013         struct ixgbe_hw *hw = &adapter->hw;
5014         u32 autoneg;
5015         bool negotiation;
5016
5017         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5018         autoneg = hw->phy.autoneg_advertised;
5019         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5020                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5021         if (hw->mac.ops.setup_link)
5022                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5023         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5024         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5025 }
5026
5027 /**
5028  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5029  * @work: pointer to work_struct containing our data
5030  **/
5031 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5032 {
5033         struct ixgbe_adapter *adapter = container_of(work,
5034                                                      struct ixgbe_adapter,
5035                                                      sfp_config_module_task);
5036         struct ixgbe_hw *hw = &adapter->hw;
5037         u32 err;
5038
5039         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5040
5041         /* Time for electrical oscillations to settle down */
5042         msleep(100);
5043         err = hw->phy.ops.identify_sfp(hw);
5044
5045         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5046                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5047                         "an unsupported SFP+ module type was detected.\n"
5048                         "Reload the driver after installing a supported "
5049                         "module.\n");
5050                 unregister_netdev(adapter->netdev);
5051                 return;
5052         }
5053         hw->mac.ops.setup_sfp(hw);
5054
5055         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5056                 /* This will also work for DA Twinax connections */
5057                 schedule_work(&adapter->multispeed_fiber_task);
5058         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5059 }
5060
5061 /**
5062  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5063  * @work: pointer to work_struct containing our data
5064  **/
5065 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5066 {
5067         struct ixgbe_adapter *adapter = container_of(work,
5068                                                      struct ixgbe_adapter,
5069                                                      fdir_reinit_task);
5070         struct ixgbe_hw *hw = &adapter->hw;
5071         int i;
5072
5073         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5074                 for (i = 0; i < adapter->num_tx_queues; i++)
5075                         set_bit(__IXGBE_FDIR_INIT_DONE,
5076                                 &(adapter->tx_ring[i]->reinit_state));
5077         } else {
5078                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
5079                         "ignored adding FDIR ATR filters \n");
5080         }
5081         /* Done FDIR Re-initialization, enable transmits */
5082         netif_tx_start_all_queues(adapter->netdev);
5083 }
5084
5085 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5086
5087 /**
5088  * ixgbe_watchdog_task - worker thread to bring link up
5089  * @work: pointer to work_struct containing our data
5090  **/
5091 static void ixgbe_watchdog_task(struct work_struct *work)
5092 {
5093         struct ixgbe_adapter *adapter = container_of(work,
5094                                                      struct ixgbe_adapter,
5095                                                      watchdog_task);
5096         struct net_device *netdev = adapter->netdev;
5097         struct ixgbe_hw *hw = &adapter->hw;
5098         u32 link_speed;
5099         bool link_up;
5100         int i;
5101         struct ixgbe_ring *tx_ring;
5102         int some_tx_pending = 0;
5103
5104         mutex_lock(&ixgbe_watchdog_lock);
5105
5106         link_up = adapter->link_up;
5107         link_speed = adapter->link_speed;
5108
5109         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5110                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5111                 if (link_up) {
5112 #ifdef CONFIG_DCB
5113                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5114                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5115                                         hw->mac.ops.fc_enable(hw, i);
5116                         } else {
5117                                 hw->mac.ops.fc_enable(hw, 0);
5118                         }
5119 #else
5120                         hw->mac.ops.fc_enable(hw, 0);
5121 #endif
5122                 }
5123
5124                 if (link_up ||
5125                     time_after(jiffies, (adapter->link_check_timeout +
5126                                          IXGBE_TRY_LINK_TIMEOUT))) {
5127                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5128                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5129                 }
5130                 adapter->link_up = link_up;
5131                 adapter->link_speed = link_speed;
5132         }
5133
5134         if (link_up) {
5135                 if (!netif_carrier_ok(netdev)) {
5136                         bool flow_rx, flow_tx;
5137
5138                         if (hw->mac.type == ixgbe_mac_82599EB) {
5139                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5140                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5141                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5142                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5143                         } else {
5144                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5145                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5146                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5147                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5148                         }
5149
5150                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
5151                                "Flow Control: %s\n",
5152                                netdev->name,
5153                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5154                                 "10 Gbps" :
5155                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5156                                  "1 Gbps" : "unknown speed")),
5157                                ((flow_rx && flow_tx) ? "RX/TX" :
5158                                 (flow_rx ? "RX" :
5159                                 (flow_tx ? "TX" : "None"))));
5160
5161                         netif_carrier_on(netdev);
5162                 } else {
5163                         /* Force detection of hung controller */
5164                         adapter->detect_tx_hung = true;
5165                 }
5166         } else {
5167                 adapter->link_up = false;
5168                 adapter->link_speed = 0;
5169                 if (netif_carrier_ok(netdev)) {
5170                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
5171                                netdev->name);
5172                         netif_carrier_off(netdev);
5173                 }
5174         }
5175
5176         if (!netif_carrier_ok(netdev)) {
5177                 for (i = 0; i < adapter->num_tx_queues; i++) {
5178                         tx_ring = adapter->tx_ring[i];
5179                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5180                                 some_tx_pending = 1;
5181                                 break;
5182                         }
5183                 }
5184
5185                 if (some_tx_pending) {
5186                         /* We've lost link, so the controller stops DMA,
5187                          * but we've got queued Tx work that's never going
5188                          * to get done, so reset controller to flush Tx.
5189                          * (Do the reset outside of interrupt context).
5190                          */
5191                          schedule_work(&adapter->reset_task);
5192                 }
5193         }
5194
5195         ixgbe_update_stats(adapter);
5196         mutex_unlock(&ixgbe_watchdog_lock);
5197 }
5198
5199 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5200                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5201                      u32 tx_flags, u8 *hdr_len)
5202 {
5203         struct ixgbe_adv_tx_context_desc *context_desc;
5204         unsigned int i;
5205         int err;
5206         struct ixgbe_tx_buffer *tx_buffer_info;
5207         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5208         u32 mss_l4len_idx, l4len;
5209
5210         if (skb_is_gso(skb)) {
5211                 if (skb_header_cloned(skb)) {
5212                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5213                         if (err)
5214                                 return err;
5215                 }
5216                 l4len = tcp_hdrlen(skb);
5217                 *hdr_len += l4len;
5218
5219                 if (skb->protocol == htons(ETH_P_IP)) {
5220                         struct iphdr *iph = ip_hdr(skb);
5221                         iph->tot_len = 0;
5222                         iph->check = 0;
5223                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5224                                                                  iph->daddr, 0,
5225                                                                  IPPROTO_TCP,
5226                                                                  0);
5227                 } else if (skb_is_gso_v6(skb)) {
5228                         ipv6_hdr(skb)->payload_len = 0;
5229                         tcp_hdr(skb)->check =
5230                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5231                                              &ipv6_hdr(skb)->daddr,
5232                                              0, IPPROTO_TCP, 0);
5233                 }
5234
5235                 i = tx_ring->next_to_use;
5236
5237                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5238                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5239
5240                 /* VLAN MACLEN IPLEN */
5241                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5242                         vlan_macip_lens |=
5243                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5244                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5245                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5246                 *hdr_len += skb_network_offset(skb);
5247                 vlan_macip_lens |=
5248                     (skb_transport_header(skb) - skb_network_header(skb));
5249                 *hdr_len +=
5250                     (skb_transport_header(skb) - skb_network_header(skb));
5251                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5252                 context_desc->seqnum_seed = 0;
5253
5254                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5255                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5256                                    IXGBE_ADVTXD_DTYP_CTXT);
5257
5258                 if (skb->protocol == htons(ETH_P_IP))
5259                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5260                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5261                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5262
5263                 /* MSS L4LEN IDX */
5264                 mss_l4len_idx =
5265                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5266                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5267                 /* use index 1 for TSO */
5268                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5269                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5270
5271                 tx_buffer_info->time_stamp = jiffies;
5272                 tx_buffer_info->next_to_watch = i;
5273
5274                 i++;
5275                 if (i == tx_ring->count)
5276                         i = 0;
5277                 tx_ring->next_to_use = i;
5278
5279                 return true;
5280         }
5281         return false;
5282 }
5283
5284 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5285                           struct ixgbe_ring *tx_ring,
5286                           struct sk_buff *skb, u32 tx_flags)
5287 {
5288         struct ixgbe_adv_tx_context_desc *context_desc;
5289         unsigned int i;
5290         struct ixgbe_tx_buffer *tx_buffer_info;
5291         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5292
5293         if (skb->ip_summed == CHECKSUM_PARTIAL ||
5294             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5295                 i = tx_ring->next_to_use;
5296                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5297                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5298
5299                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5300                         vlan_macip_lens |=
5301                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5302                 vlan_macip_lens |= (skb_network_offset(skb) <<
5303                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5304                 if (skb->ip_summed == CHECKSUM_PARTIAL)
5305                         vlan_macip_lens |= (skb_transport_header(skb) -
5306                                             skb_network_header(skb));
5307
5308                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5309                 context_desc->seqnum_seed = 0;
5310
5311                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5312                                     IXGBE_ADVTXD_DTYP_CTXT);
5313
5314                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5315                         __be16 protocol;
5316
5317                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5318                                 const struct vlan_ethhdr *vhdr =
5319                                         (const struct vlan_ethhdr *)skb->data;
5320
5321                                 protocol = vhdr->h_vlan_encapsulated_proto;
5322                         } else {
5323                                 protocol = skb->protocol;
5324                         }
5325
5326                         switch (protocol) {
5327                         case cpu_to_be16(ETH_P_IP):
5328                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5329                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5330                                         type_tucmd_mlhl |=
5331                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5332                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5333                                         type_tucmd_mlhl |=
5334                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5335                                 break;
5336                         case cpu_to_be16(ETH_P_IPV6):
5337                                 /* XXX what about other V6 headers?? */
5338                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5339                                         type_tucmd_mlhl |=
5340                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5341                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5342                                         type_tucmd_mlhl |=
5343                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5344                                 break;
5345                         default:
5346                                 if (unlikely(net_ratelimit())) {
5347                                         DPRINTK(PROBE, WARNING,
5348                                          "partial checksum but proto=%x!\n",
5349                                          skb->protocol);
5350                                 }
5351                                 break;
5352                         }
5353                 }
5354
5355                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5356                 /* use index zero for tx checksum offload */
5357                 context_desc->mss_l4len_idx = 0;
5358
5359                 tx_buffer_info->time_stamp = jiffies;
5360                 tx_buffer_info->next_to_watch = i;
5361
5362                 i++;
5363                 if (i == tx_ring->count)
5364                         i = 0;
5365                 tx_ring->next_to_use = i;
5366
5367                 return true;
5368         }
5369
5370         return false;
5371 }
5372
5373 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5374                         struct ixgbe_ring *tx_ring,
5375                         struct sk_buff *skb, u32 tx_flags,
5376                         unsigned int first)
5377 {
5378         struct pci_dev *pdev = adapter->pdev;
5379         struct ixgbe_tx_buffer *tx_buffer_info;
5380         unsigned int len;
5381         unsigned int total = skb->len;
5382         unsigned int offset = 0, size, count = 0, i;
5383         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5384         unsigned int f;
5385
5386         i = tx_ring->next_to_use;
5387
5388         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5389                 /* excluding fcoe_crc_eof for FCoE */
5390                 total -= sizeof(struct fcoe_crc_eof);
5391
5392         len = min(skb_headlen(skb), total);
5393         while (len) {
5394                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5395                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5396
5397                 tx_buffer_info->length = size;
5398                 tx_buffer_info->mapped_as_page = false;
5399                 tx_buffer_info->dma = pci_map_single(pdev,
5400                                                      skb->data + offset,
5401                                                      size, PCI_DMA_TODEVICE);
5402                 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5403                         goto dma_error;
5404                 tx_buffer_info->time_stamp = jiffies;
5405                 tx_buffer_info->next_to_watch = i;
5406
5407                 len -= size;
5408                 total -= size;
5409                 offset += size;
5410                 count++;
5411
5412                 if (len) {
5413                         i++;
5414                         if (i == tx_ring->count)
5415                                 i = 0;
5416                 }
5417         }
5418
5419         for (f = 0; f < nr_frags; f++) {
5420                 struct skb_frag_struct *frag;
5421
5422                 frag = &skb_shinfo(skb)->frags[f];
5423                 len = min((unsigned int)frag->size, total);
5424                 offset = frag->page_offset;
5425
5426                 while (len) {
5427                         i++;
5428                         if (i == tx_ring->count)
5429                                 i = 0;
5430
5431                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
5432                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5433
5434                         tx_buffer_info->length = size;
5435                         tx_buffer_info->dma = pci_map_page(adapter->pdev,
5436                                                            frag->page,
5437                                                            offset, size,
5438                                                            PCI_DMA_TODEVICE);
5439                         tx_buffer_info->mapped_as_page = true;
5440                         if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5441                                 goto dma_error;
5442                         tx_buffer_info->time_stamp = jiffies;
5443                         tx_buffer_info->next_to_watch = i;
5444
5445                         len -= size;
5446                         total -= size;
5447                         offset += size;
5448                         count++;
5449                 }
5450                 if (total == 0)
5451                         break;
5452         }
5453
5454         tx_ring->tx_buffer_info[i].skb = skb;
5455         tx_ring->tx_buffer_info[first].next_to_watch = i;
5456
5457         return count;
5458
5459 dma_error:
5460         dev_err(&pdev->dev, "TX DMA map failed\n");
5461
5462         /* clear timestamp and dma mappings for failed tx_buffer_info map */
5463         tx_buffer_info->dma = 0;
5464         tx_buffer_info->time_stamp = 0;
5465         tx_buffer_info->next_to_watch = 0;
5466         if (count)
5467                 count--;
5468
5469         /* clear timestamp and dma mappings for remaining portion of packet */
5470         while (count--) {
5471                 if (i==0)
5472                         i += tx_ring->count;
5473                 i--;
5474                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5475                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5476         }
5477
5478         return 0;
5479 }
5480
5481 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5482                            struct ixgbe_ring *tx_ring,
5483                            int tx_flags, int count, u32 paylen, u8 hdr_len)
5484 {
5485         union ixgbe_adv_tx_desc *tx_desc = NULL;
5486         struct ixgbe_tx_buffer *tx_buffer_info;
5487         u32 olinfo_status = 0, cmd_type_len = 0;
5488         unsigned int i;
5489         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5490
5491         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5492
5493         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5494
5495         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5496                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5497
5498         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5499                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5500
5501                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5502                                  IXGBE_ADVTXD_POPTS_SHIFT;
5503
5504                 /* use index 1 context for tso */
5505                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5506                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5507                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5508                                          IXGBE_ADVTXD_POPTS_SHIFT;
5509
5510         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5511                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5512                                  IXGBE_ADVTXD_POPTS_SHIFT;
5513
5514         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5515                 olinfo_status |= IXGBE_ADVTXD_CC;
5516                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5517                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5518                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5519         }
5520
5521         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5522
5523         i = tx_ring->next_to_use;
5524         while (count--) {
5525                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5526                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5527                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5528                 tx_desc->read.cmd_type_len =
5529                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5530                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5531                 i++;
5532                 if (i == tx_ring->count)
5533                         i = 0;
5534         }
5535
5536         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5537
5538         /*
5539          * Force memory writes to complete before letting h/w
5540          * know there are new descriptors to fetch.  (Only
5541          * applicable for weak-ordered memory model archs,
5542          * such as IA-64).
5543          */
5544         wmb();
5545
5546         tx_ring->next_to_use = i;
5547         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5548 }
5549
5550 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5551                       int queue, u32 tx_flags)
5552 {
5553         /* Right now, we support IPv4 only */
5554         struct ixgbe_atr_input atr_input;
5555         struct tcphdr *th;
5556         struct iphdr *iph = ip_hdr(skb);
5557         struct ethhdr *eth = (struct ethhdr *)skb->data;
5558         u16 vlan_id, src_port, dst_port, flex_bytes;
5559         u32 src_ipv4_addr, dst_ipv4_addr;
5560         u8 l4type = 0;
5561
5562         /* check if we're UDP or TCP */
5563         if (iph->protocol == IPPROTO_TCP) {
5564                 th = tcp_hdr(skb);
5565                 src_port = th->source;
5566                 dst_port = th->dest;
5567                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5568                 /* l4type IPv4 type is 0, no need to assign */
5569         } else {
5570                 /* Unsupported L4 header, just bail here */
5571                 return;
5572         }
5573
5574         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5575
5576         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5577                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5578         src_ipv4_addr = iph->saddr;
5579         dst_ipv4_addr = iph->daddr;
5580         flex_bytes = eth->h_proto;
5581
5582         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5583         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5584         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5585         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5586         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5587         /* src and dst are inverted, think how the receiver sees them */
5588         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5589         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5590
5591         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5592         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5593 }
5594
5595 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5596                                  struct ixgbe_ring *tx_ring, int size)
5597 {
5598         netif_stop_subqueue(netdev, tx_ring->queue_index);
5599         /* Herbert's original patch had:
5600          *  smp_mb__after_netif_stop_queue();
5601          * but since that doesn't exist yet, just open code it. */
5602         smp_mb();
5603
5604         /* We need to check again in a case another CPU has just
5605          * made room available. */
5606         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5607                 return -EBUSY;
5608
5609         /* A reprieve! - use start_queue because it doesn't call schedule */
5610         netif_start_subqueue(netdev, tx_ring->queue_index);
5611         ++tx_ring->restart_queue;
5612         return 0;
5613 }
5614
5615 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5616                               struct ixgbe_ring *tx_ring, int size)
5617 {
5618         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5619                 return 0;
5620         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5621 }
5622
5623 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5624 {
5625         struct ixgbe_adapter *adapter = netdev_priv(dev);
5626         int txq = smp_processor_id();
5627
5628         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5629                 while (unlikely(txq >= dev->real_num_tx_queues))
5630                         txq -= dev->real_num_tx_queues;
5631                 return txq;
5632         }
5633
5634 #ifdef IXGBE_FCOE
5635         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5636             (skb->protocol == htons(ETH_P_FCOE))) {
5637                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5638                 txq += adapter->ring_feature[RING_F_FCOE].mask;
5639                 return txq;
5640         }
5641 #endif
5642         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5643                 if (skb->priority == TC_PRIO_CONTROL)
5644                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
5645                 else
5646                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
5647                                >> 13;
5648                 return txq;
5649         }
5650
5651         return skb_tx_hash(dev, skb);
5652 }
5653
5654 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5655                                     struct net_device *netdev)
5656 {
5657         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5658         struct ixgbe_ring *tx_ring;
5659         struct netdev_queue *txq;
5660         unsigned int first;
5661         unsigned int tx_flags = 0;
5662         u8 hdr_len = 0;
5663         int tso;
5664         int count = 0;
5665         unsigned int f;
5666
5667         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5668                 tx_flags |= vlan_tx_tag_get(skb);
5669                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5670                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5671                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
5672                 }
5673                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5674                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5675         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5676                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
5677                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5678                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5679         }
5680
5681         tx_ring = adapter->tx_ring[skb->queue_mapping];
5682
5683         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5684             (skb->protocol == htons(ETH_P_FCOE))) {
5685                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5686 #ifdef IXGBE_FCOE
5687 #ifdef CONFIG_IXGBE_DCB
5688                 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5689                               << IXGBE_TX_FLAGS_VLAN_SHIFT);
5690                 tx_flags |= ((adapter->fcoe.up << 13)
5691                               << IXGBE_TX_FLAGS_VLAN_SHIFT);
5692 #endif
5693 #endif
5694         }
5695         /* four things can cause us to need a context descriptor */
5696         if (skb_is_gso(skb) ||
5697             (skb->ip_summed == CHECKSUM_PARTIAL) ||
5698             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5699             (tx_flags & IXGBE_TX_FLAGS_FCOE))
5700                 count++;
5701
5702         count += TXD_USE_COUNT(skb_headlen(skb));
5703         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5704                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5705
5706         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5707                 adapter->tx_busy++;
5708                 return NETDEV_TX_BUSY;
5709         }
5710
5711         first = tx_ring->next_to_use;
5712         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5713 #ifdef IXGBE_FCOE
5714                 /* setup tx offload for FCoE */
5715                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5716                 if (tso < 0) {
5717                         dev_kfree_skb_any(skb);
5718                         return NETDEV_TX_OK;
5719                 }
5720                 if (tso)
5721                         tx_flags |= IXGBE_TX_FLAGS_FSO;
5722 #endif /* IXGBE_FCOE */
5723         } else {
5724                 if (skb->protocol == htons(ETH_P_IP))
5725                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
5726                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5727                 if (tso < 0) {
5728                         dev_kfree_skb_any(skb);
5729                         return NETDEV_TX_OK;
5730                 }
5731
5732                 if (tso)
5733                         tx_flags |= IXGBE_TX_FLAGS_TSO;
5734                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5735                          (skb->ip_summed == CHECKSUM_PARTIAL))
5736                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
5737         }
5738
5739         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5740         if (count) {
5741                 /* add the ATR filter if ATR is on */
5742                 if (tx_ring->atr_sample_rate) {
5743                         ++tx_ring->atr_count;
5744                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5745                              test_bit(__IXGBE_FDIR_INIT_DONE,
5746                                       &tx_ring->reinit_state)) {
5747                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5748                                           tx_flags);
5749                                 tx_ring->atr_count = 0;
5750                         }
5751                 }
5752                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
5753                 txq->tx_bytes += skb->len;
5754                 txq->tx_packets++;
5755                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5756                                hdr_len);
5757                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5758
5759         } else {
5760                 dev_kfree_skb_any(skb);
5761                 tx_ring->tx_buffer_info[first].time_stamp = 0;
5762                 tx_ring->next_to_use = first;
5763         }
5764
5765         return NETDEV_TX_OK;
5766 }
5767
5768 /**
5769  * ixgbe_set_mac - Change the Ethernet Address of the NIC
5770  * @netdev: network interface device structure
5771  * @p: pointer to an address structure
5772  *
5773  * Returns 0 on success, negative on failure
5774  **/
5775 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5776 {
5777         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5778         struct ixgbe_hw *hw = &adapter->hw;
5779         struct sockaddr *addr = p;
5780
5781         if (!is_valid_ether_addr(addr->sa_data))
5782                 return -EADDRNOTAVAIL;
5783
5784         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5785         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5786
5787         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
5788                             IXGBE_RAH_AV);
5789
5790         return 0;
5791 }
5792
5793 static int
5794 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5795 {
5796         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5797         struct ixgbe_hw *hw = &adapter->hw;
5798         u16 value;
5799         int rc;
5800
5801         if (prtad != hw->phy.mdio.prtad)
5802                 return -EINVAL;
5803         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5804         if (!rc)
5805                 rc = value;
5806         return rc;
5807 }
5808
5809 static int ixgbe_mdio_write(struct net_device *netdev,&nbs