Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3   Intel 10 Gigabit PCI Express Linux driver
4   Copyright(c) 1999 - 2010 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
45
46 #include "ixgbe.h"
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
50
51 char ixgbe_driver_name[] = "ixgbe";
52 static const char ixgbe_driver_string[] =
53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
54
55 #define DRV_VERSION "2.0.62-k2"
56 const char ixgbe_driver_version[] = DRV_VERSION;
57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
58
59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
60         [board_82598] = &ixgbe_82598_info,
61         [board_82599] = &ixgbe_82599_info,
62 };
63
64 /* ixgbe_pci_tbl - PCI Device ID Table
65  *
66  * Wildcard entries (PCI_ANY_ID) should come last
67  * Last entry must be all 0s
68  *
69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70  *   Class, Class Mask, private data (not used) }
71  */
72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74          board_82598 },
75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
76          board_82598 },
77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
78          board_82598 },
79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80          board_82598 },
81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82          board_82598 },
83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
84          board_82598 },
85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86          board_82598 },
87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88          board_82598 },
89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90          board_82598 },
91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92          board_82598 },
93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94          board_82598 },
95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96          board_82598 },
97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98          board_82599 },
99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100          board_82599 },
101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102          board_82599 },
103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104          board_82599 },
105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106          board_82599 },
107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108          board_82599 },
109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110          board_82599 },
111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
112          board_82599 },
113
114         /* required last entry */
115         {0, }
116 };
117 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
118
119 #ifdef CONFIG_IXGBE_DCA
120 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
121                             void *p);
122 static struct notifier_block dca_notifier = {
123         .notifier_call = ixgbe_notify_dca,
124         .next          = NULL,
125         .priority      = 0
126 };
127 #endif
128
129 #ifdef CONFIG_PCI_IOV
130 static unsigned int max_vfs;
131 module_param(max_vfs, uint, 0);
132 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
133                  "per physical function");
134 #endif /* CONFIG_PCI_IOV */
135
136 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
137 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
138 MODULE_LICENSE("GPL");
139 MODULE_VERSION(DRV_VERSION);
140
141 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
142
143 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
144 {
145         struct ixgbe_hw *hw = &adapter->hw;
146         u32 gcr;
147         u32 gpie;
148         u32 vmdctl;
149
150 #ifdef CONFIG_PCI_IOV
151         /* disable iov and allow time for transactions to clear */
152         pci_disable_sriov(adapter->pdev);
153 #endif
154
155         /* turn off device IOV mode */
156         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
157         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
158         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
159         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
160         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
161         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
162
163         /* set default pool back to 0 */
164         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
165         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
166         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
167
168         /* take a breather then clean up driver data */
169         msleep(100);
170         if (adapter->vfinfo)
171                 kfree(adapter->vfinfo);
172         adapter->vfinfo = NULL;
173
174         adapter->num_vfs = 0;
175         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
176 }
177
178 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
179 {
180         u32 ctrl_ext;
181
182         /* Let firmware take over control of h/w */
183         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
184         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
185                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
186 }
187
188 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
189 {
190         u32 ctrl_ext;
191
192         /* Let firmware know the driver has taken over */
193         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
194         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
195                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
196 }
197
198 /*
199  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
200  * @adapter: pointer to adapter struct
201  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
202  * @queue: queue to map the corresponding interrupt to
203  * @msix_vector: the vector to map to the corresponding queue
204  *
205  */
206 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
207                            u8 queue, u8 msix_vector)
208 {
209         u32 ivar, index;
210         struct ixgbe_hw *hw = &adapter->hw;
211         switch (hw->mac.type) {
212         case ixgbe_mac_82598EB:
213                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
214                 if (direction == -1)
215                         direction = 0;
216                 index = (((direction * 64) + queue) >> 2) & 0x1F;
217                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
218                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
219                 ivar |= (msix_vector << (8 * (queue & 0x3)));
220                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
221                 break;
222         case ixgbe_mac_82599EB:
223                 if (direction == -1) {
224                         /* other causes */
225                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
226                         index = ((queue & 1) * 8);
227                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
228                         ivar &= ~(0xFF << index);
229                         ivar |= (msix_vector << index);
230                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
231                         break;
232                 } else {
233                         /* tx or rx causes */
234                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
235                         index = ((16 * (queue & 1)) + (8 * direction));
236                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
237                         ivar &= ~(0xFF << index);
238                         ivar |= (msix_vector << index);
239                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
240                         break;
241                 }
242         default:
243                 break;
244         }
245 }
246
247 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
248                                           u64 qmask)
249 {
250         u32 mask;
251
252         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
253                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
254                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
255         } else {
256                 mask = (qmask & 0xFFFFFFFF);
257                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
258                 mask = (qmask >> 32);
259                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
260         }
261 }
262
263 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
264                                              struct ixgbe_tx_buffer
265                                              *tx_buffer_info)
266 {
267         if (tx_buffer_info->dma) {
268                 if (tx_buffer_info->mapped_as_page)
269                         pci_unmap_page(adapter->pdev,
270                                        tx_buffer_info->dma,
271                                        tx_buffer_info->length,
272                                        PCI_DMA_TODEVICE);
273                 else
274                         pci_unmap_single(adapter->pdev,
275                                          tx_buffer_info->dma,
276                                          tx_buffer_info->length,
277                                          PCI_DMA_TODEVICE);
278                 tx_buffer_info->dma = 0;
279         }
280         if (tx_buffer_info->skb) {
281                 dev_kfree_skb_any(tx_buffer_info->skb);
282                 tx_buffer_info->skb = NULL;
283         }
284         tx_buffer_info->time_stamp = 0;
285         /* tx_buffer_info must be completely set up in the transmit path */
286 }
287
288 /**
289  * ixgbe_tx_is_paused - check if the tx ring is paused
290  * @adapter: the ixgbe adapter
291  * @tx_ring: the corresponding tx_ring
292  *
293  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
294  * corresponding TC of this tx_ring when checking TFCS.
295  *
296  * Returns : true if paused
297  */
298 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
299                                       struct ixgbe_ring *tx_ring)
300 {
301         u32 txoff = IXGBE_TFCS_TXOFF;
302
303 #ifdef CONFIG_IXGBE_DCB
304         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
305                 int tc;
306                 int reg_idx = tx_ring->reg_idx;
307                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
308
309                 switch (adapter->hw.mac.type) {
310                 case ixgbe_mac_82598EB:
311                         tc = reg_idx >> 2;
312                         txoff = IXGBE_TFCS_TXOFF0;
313                         break;
314                 case ixgbe_mac_82599EB:
315                         tc = 0;
316                         txoff = IXGBE_TFCS_TXOFF;
317                         if (dcb_i == 8) {
318                                 /* TC0, TC1 */
319                                 tc = reg_idx >> 5;
320                                 if (tc == 2) /* TC2, TC3 */
321                                         tc += (reg_idx - 64) >> 4;
322                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
323                                         tc += 1 + ((reg_idx - 96) >> 3);
324                         } else if (dcb_i == 4) {
325                                 /* TC0, TC1 */
326                                 tc = reg_idx >> 6;
327                                 if (tc == 1) {
328                                         tc += (reg_idx - 64) >> 5;
329                                         if (tc == 2) /* TC2, TC3 */
330                                                 tc += (reg_idx - 96) >> 4;
331                                 }
332                         }
333                         break;
334                 default:
335                         tc = 0;
336                 }
337                 txoff <<= tc;
338         }
339 #endif
340         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
341 }
342
343 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
344                                        struct ixgbe_ring *tx_ring,
345                                        unsigned int eop)
346 {
347         struct ixgbe_hw *hw = &adapter->hw;
348
349         /* Detect a transmit hang in hardware, this serializes the
350          * check with the clearing of time_stamp and movement of eop */
351         adapter->detect_tx_hung = false;
352         if (tx_ring->tx_buffer_info[eop].time_stamp &&
353             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
354             !ixgbe_tx_is_paused(adapter, tx_ring)) {
355                 /* detected Tx unit hang */
356                 union ixgbe_adv_tx_desc *tx_desc;
357                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
358                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
359                         "  Tx Queue             <%d>\n"
360                         "  TDH, TDT             <%x>, <%x>\n"
361                         "  next_to_use          <%x>\n"
362                         "  next_to_clean        <%x>\n"
363                         "tx_buffer_info[next_to_clean]\n"
364                         "  time_stamp           <%lx>\n"
365                         "  jiffies              <%lx>\n",
366                         tx_ring->queue_index,
367                         IXGBE_READ_REG(hw, tx_ring->head),
368                         IXGBE_READ_REG(hw, tx_ring->tail),
369                         tx_ring->next_to_use, eop,
370                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
371                 return true;
372         }
373
374         return false;
375 }
376
377 #define IXGBE_MAX_TXD_PWR       14
378 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
379
380 /* Tx Descriptors needed, worst case */
381 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
382                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
383 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
384         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
385
386 static void ixgbe_tx_timeout(struct net_device *netdev);
387
388 /**
389  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
390  * @q_vector: structure containing interrupt and ring information
391  * @tx_ring: tx ring to clean
392  **/
393 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
394                                struct ixgbe_ring *tx_ring)
395 {
396         struct ixgbe_adapter *adapter = q_vector->adapter;
397         struct net_device *netdev = adapter->netdev;
398         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
399         struct ixgbe_tx_buffer *tx_buffer_info;
400         unsigned int i, eop, count = 0;
401         unsigned int total_bytes = 0, total_packets = 0;
402
403         i = tx_ring->next_to_clean;
404         eop = tx_ring->tx_buffer_info[i].next_to_watch;
405         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
406
407         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
408                (count < tx_ring->work_limit)) {
409                 bool cleaned = false;
410                 for ( ; !cleaned; count++) {
411                         struct sk_buff *skb;
412                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
413                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
414                         cleaned = (i == eop);
415                         skb = tx_buffer_info->skb;
416
417                         if (cleaned && skb) {
418                                 unsigned int segs, bytecount;
419                                 unsigned int hlen = skb_headlen(skb);
420
421                                 /* gso_segs is currently only valid for tcp */
422                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
423 #ifdef IXGBE_FCOE
424                                 /* adjust for FCoE Sequence Offload */
425                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
426                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
427                                     skb_is_gso(skb)) {
428                                         hlen = skb_transport_offset(skb) +
429                                                 sizeof(struct fc_frame_header) +
430                                                 sizeof(struct fcoe_crc_eof);
431                                         segs = DIV_ROUND_UP(skb->len - hlen,
432                                                 skb_shinfo(skb)->gso_size);
433                                 }
434 #endif /* IXGBE_FCOE */
435                                 /* multiply data chunks by size of headers */
436                                 bytecount = ((segs - 1) * hlen) + skb->len;
437                                 total_packets += segs;
438                                 total_bytes += bytecount;
439                         }
440
441                         ixgbe_unmap_and_free_tx_resource(adapter,
442                                                          tx_buffer_info);
443
444                         tx_desc->wb.status = 0;
445
446                         i++;
447                         if (i == tx_ring->count)
448                                 i = 0;
449                 }
450
451                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
452                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
453         }
454
455         tx_ring->next_to_clean = i;
456
457 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
458         if (unlikely(count && netif_carrier_ok(netdev) &&
459                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
460                 /* Make sure that anybody stopping the queue after this
461                  * sees the new next_to_clean.
462                  */
463                 smp_mb();
464                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
465                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
466                         netif_wake_subqueue(netdev, tx_ring->queue_index);
467                         ++tx_ring->restart_queue;
468                 }
469         }
470
471         if (adapter->detect_tx_hung) {
472                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
473                         /* schedule immediate reset if we believe we hung */
474                         DPRINTK(PROBE, INFO,
475                                 "tx hang %d detected, resetting adapter\n",
476                                 adapter->tx_timeout_count + 1);
477                         ixgbe_tx_timeout(adapter->netdev);
478                 }
479         }
480
481         /* re-arm the interrupt */
482         if (count >= tx_ring->work_limit)
483                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
484
485         tx_ring->total_bytes += total_bytes;
486         tx_ring->total_packets += total_packets;
487         tx_ring->stats.packets += total_packets;
488         tx_ring->stats.bytes += total_bytes;
489         return (count < tx_ring->work_limit);
490 }
491
492 #ifdef CONFIG_IXGBE_DCA
493 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
494                                 struct ixgbe_ring *rx_ring)
495 {
496         u32 rxctrl;
497         int cpu = get_cpu();
498         int q = rx_ring->reg_idx;
499
500         if (rx_ring->cpu != cpu) {
501                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
502                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
503                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
504                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
505                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
506                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
507                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
508                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
509                 }
510                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
511                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
512                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
513                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
514                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
515                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
516                 rx_ring->cpu = cpu;
517         }
518         put_cpu();
519 }
520
521 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
522                                 struct ixgbe_ring *tx_ring)
523 {
524         u32 txctrl;
525         int cpu = get_cpu();
526         int q = tx_ring->reg_idx;
527         struct ixgbe_hw *hw = &adapter->hw;
528
529         if (tx_ring->cpu != cpu) {
530                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
531                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
532                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
533                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
534                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
535                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
536                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
537                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
538                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
539                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
540                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
541                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
542                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
543                 }
544                 tx_ring->cpu = cpu;
545         }
546         put_cpu();
547 }
548
549 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
550 {
551         int i;
552
553         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
554                 return;
555
556         /* always use CB2 mode, difference is masked in the CB driver */
557         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
558
559         for (i = 0; i < adapter->num_tx_queues; i++) {
560                 adapter->tx_ring[i]->cpu = -1;
561                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
562         }
563         for (i = 0; i < adapter->num_rx_queues; i++) {
564                 adapter->rx_ring[i]->cpu = -1;
565                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
566         }
567 }
568
569 static int __ixgbe_notify_dca(struct device *dev, void *data)
570 {
571         struct net_device *netdev = dev_get_drvdata(dev);
572         struct ixgbe_adapter *adapter = netdev_priv(netdev);
573         unsigned long event = *(unsigned long *)data;
574
575         switch (event) {
576         case DCA_PROVIDER_ADD:
577                 /* if we're already enabled, don't do it again */
578                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
579                         break;
580                 if (dca_add_requester(dev) == 0) {
581                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
582                         ixgbe_setup_dca(adapter);
583                         break;
584                 }
585                 /* Fall Through since DCA is disabled. */
586         case DCA_PROVIDER_REMOVE:
587                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
588                         dca_remove_requester(dev);
589                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
590                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
591                 }
592                 break;
593         }
594
595         return 0;
596 }
597
598 #endif /* CONFIG_IXGBE_DCA */
599 /**
600  * ixgbe_receive_skb - Send a completed packet up the stack
601  * @adapter: board private structure
602  * @skb: packet to send up
603  * @status: hardware indication of status of receive
604  * @rx_ring: rx descriptor ring (for a specific queue) to setup
605  * @rx_desc: rx descriptor
606  **/
607 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
608                               struct sk_buff *skb, u8 status,
609                               struct ixgbe_ring *ring,
610                               union ixgbe_adv_rx_desc *rx_desc)
611 {
612         struct ixgbe_adapter *adapter = q_vector->adapter;
613         struct napi_struct *napi = &q_vector->napi;
614         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
615         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
616
617         skb_record_rx_queue(skb, ring->queue_index);
618         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
619                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
620                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
621                 else
622                         napi_gro_receive(napi, skb);
623         } else {
624                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
625                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
626                 else
627                         netif_rx(skb);
628         }
629 }
630
631 /**
632  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
633  * @adapter: address of board private structure
634  * @status_err: hardware indication of status of receive
635  * @skb: skb currently being received and modified
636  **/
637 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
638                                      union ixgbe_adv_rx_desc *rx_desc,
639                                      struct sk_buff *skb)
640 {
641         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
642
643         skb->ip_summed = CHECKSUM_NONE;
644
645         /* Rx csum disabled */
646         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
647                 return;
648
649         /* if IP and error */
650         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
651             (status_err & IXGBE_RXDADV_ERR_IPE)) {
652                 adapter->hw_csum_rx_error++;
653                 return;
654         }
655
656         if (!(status_err & IXGBE_RXD_STAT_L4CS))
657                 return;
658
659         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
660                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
661
662                 /*
663                  * 82599 errata, UDP frames with a 0 checksum can be marked as
664                  * checksum errors.
665                  */
666                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
667                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
668                         return;
669
670                 adapter->hw_csum_rx_error++;
671                 return;
672         }
673
674         /* It must be a TCP or UDP packet with a valid checksum */
675         skb->ip_summed = CHECKSUM_UNNECESSARY;
676 }
677
678 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
679                                          struct ixgbe_ring *rx_ring, u32 val)
680 {
681         /*
682          * Force memory writes to complete before letting h/w
683          * know there are new descriptors to fetch.  (Only
684          * applicable for weak-ordered memory model archs,
685          * such as IA-64).
686          */
687         wmb();
688         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
689 }
690
691 /**
692  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
693  * @adapter: address of board private structure
694  **/
695 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
696                                    struct ixgbe_ring *rx_ring,
697                                    int cleaned_count)
698 {
699         struct pci_dev *pdev = adapter->pdev;
700         union ixgbe_adv_rx_desc *rx_desc;
701         struct ixgbe_rx_buffer *bi;
702         unsigned int i;
703
704         i = rx_ring->next_to_use;
705         bi = &rx_ring->rx_buffer_info[i];
706
707         while (cleaned_count--) {
708                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
709
710                 if (!bi->page_dma &&
711                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
712                         if (!bi->page) {
713                                 bi->page = alloc_page(GFP_ATOMIC);
714                                 if (!bi->page) {
715                                         adapter->alloc_rx_page_failed++;
716                                         goto no_buffers;
717                                 }
718                                 bi->page_offset = 0;
719                         } else {
720                                 /* use a half page if we're re-using */
721                                 bi->page_offset ^= (PAGE_SIZE / 2);
722                         }
723
724                         bi->page_dma = pci_map_page(pdev, bi->page,
725                                                     bi->page_offset,
726                                                     (PAGE_SIZE / 2),
727                                                     PCI_DMA_FROMDEVICE);
728                 }
729
730                 if (!bi->skb) {
731                         struct sk_buff *skb;
732                         /* netdev_alloc_skb reserves 32 bytes up front!! */
733                         uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
734                         skb = netdev_alloc_skb(adapter->netdev, bufsz);
735
736                         if (!skb) {
737                                 adapter->alloc_rx_buff_failed++;
738                                 goto no_buffers;
739                         }
740
741                         /* advance the data pointer to the next cache line */
742                         skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
743                                           - skb->data));
744
745                         bi->skb = skb;
746                         bi->dma = pci_map_single(pdev, skb->data,
747                                                  rx_ring->rx_buf_len,
748                                                  PCI_DMA_FROMDEVICE);
749                 }
750                 /* Refresh the desc even if buffer_addrs didn't change because
751                  * each write-back erases this info. */
752                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
753                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
754                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
755                 } else {
756                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
757                 }
758
759                 i++;
760                 if (i == rx_ring->count)
761                         i = 0;
762                 bi = &rx_ring->rx_buffer_info[i];
763         }
764
765 no_buffers:
766         if (rx_ring->next_to_use != i) {
767                 rx_ring->next_to_use = i;
768                 if (i-- == 0)
769                         i = (rx_ring->count - 1);
770
771                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
772         }
773 }
774
775 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
776 {
777         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
778 }
779
780 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
781 {
782         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
783 }
784
785 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
786 {
787         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
788                 IXGBE_RXDADV_RSCCNT_MASK) >>
789                 IXGBE_RXDADV_RSCCNT_SHIFT;
790 }
791
792 /**
793  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
794  * @skb: pointer to the last skb in the rsc queue
795  * @count: pointer to number of packets coalesced in this context
796  *
797  * This function changes a queue full of hw rsc buffers into a completed
798  * packet.  It uses the ->prev pointers to find the first packet and then
799  * turns it into the frag list owner.
800  **/
801 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
802                                                         u64 *count)
803 {
804         unsigned int frag_list_size = 0;
805
806         while (skb->prev) {
807                 struct sk_buff *prev = skb->prev;
808                 frag_list_size += skb->len;
809                 skb->prev = NULL;
810                 skb = prev;
811                 *count += 1;
812         }
813
814         skb_shinfo(skb)->frag_list = skb->next;
815         skb->next = NULL;
816         skb->len += frag_list_size;
817         skb->data_len += frag_list_size;
818         skb->truesize += frag_list_size;
819         return skb;
820 }
821
822 struct ixgbe_rsc_cb {
823         dma_addr_t dma;
824 };
825
826 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
827
828 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
829                                struct ixgbe_ring *rx_ring,
830                                int *work_done, int work_to_do)
831 {
832         struct ixgbe_adapter *adapter = q_vector->adapter;
833         struct net_device *netdev = adapter->netdev;
834         struct pci_dev *pdev = adapter->pdev;
835         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
836         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
837         struct sk_buff *skb;
838         unsigned int i, rsc_count = 0;
839         u32 len, staterr;
840         u16 hdr_info;
841         bool cleaned = false;
842         int cleaned_count = 0;
843         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
844 #ifdef IXGBE_FCOE
845         int ddp_bytes = 0;
846 #endif /* IXGBE_FCOE */
847
848         i = rx_ring->next_to_clean;
849         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
850         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
851         rx_buffer_info = &rx_ring->rx_buffer_info[i];
852
853         while (staterr & IXGBE_RXD_STAT_DD) {
854                 u32 upper_len = 0;
855                 if (*work_done >= work_to_do)
856                         break;
857                 (*work_done)++;
858
859                 rmb(); /* read descriptor and rx_buffer_info after status DD */
860                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
861                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
862                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
863                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
864                         if (len > IXGBE_RX_HDR_SIZE)
865                                 len = IXGBE_RX_HDR_SIZE;
866                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
867                 } else {
868                         len = le16_to_cpu(rx_desc->wb.upper.length);
869                 }
870
871                 cleaned = true;
872                 skb = rx_buffer_info->skb;
873                 prefetch(skb->data);
874                 rx_buffer_info->skb = NULL;
875
876                 if (rx_buffer_info->dma) {
877                         if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
878                             (!(staterr & IXGBE_RXD_STAT_EOP)) &&
879                                  (!(skb->prev)))
880                                 /*
881                                  * When HWRSC is enabled, delay unmapping
882                                  * of the first packet. It carries the
883                                  * header information, HW may still
884                                  * access the header after the writeback.
885                                  * Only unmap it when EOP is reached
886                                  */
887                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
888                         else
889                                 pci_unmap_single(pdev, rx_buffer_info->dma,
890                                                  rx_ring->rx_buf_len,
891                                                  PCI_DMA_FROMDEVICE);
892                         rx_buffer_info->dma = 0;
893                         skb_put(skb, len);
894                 }
895
896                 if (upper_len) {
897                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
898                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
899                         rx_buffer_info->page_dma = 0;
900                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
901                                            rx_buffer_info->page,
902                                            rx_buffer_info->page_offset,
903                                            upper_len);
904
905                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
906                             (page_count(rx_buffer_info->page) != 1))
907                                 rx_buffer_info->page = NULL;
908                         else
909                                 get_page(rx_buffer_info->page);
910
911                         skb->len += upper_len;
912                         skb->data_len += upper_len;
913                         skb->truesize += upper_len;
914                 }
915
916                 i++;
917                 if (i == rx_ring->count)
918                         i = 0;
919
920                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
921                 prefetch(next_rxd);
922                 cleaned_count++;
923
924                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
925                         rsc_count = ixgbe_get_rsc_count(rx_desc);
926
927                 if (rsc_count) {
928                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
929                                      IXGBE_RXDADV_NEXTP_SHIFT;
930                         next_buffer = &rx_ring->rx_buffer_info[nextp];
931                 } else {
932                         next_buffer = &rx_ring->rx_buffer_info[i];
933                 }
934
935                 if (staterr & IXGBE_RXD_STAT_EOP) {
936                         if (skb->prev)
937                                 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
938                         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
939                                 if (IXGBE_RSC_CB(skb)->dma) {
940                                         pci_unmap_single(pdev, IXGBE_RSC_CB(skb)->dma,
941                                                          rx_ring->rx_buf_len,
942                                                          PCI_DMA_FROMDEVICE);
943                                         IXGBE_RSC_CB(skb)->dma = 0;
944                                 }
945                                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
946                                         rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
947                                 else
948                                         rx_ring->rsc_count++;
949                                 rx_ring->rsc_flush++;
950                         }
951                         rx_ring->stats.packets++;
952                         rx_ring->stats.bytes += skb->len;
953                 } else {
954                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
955                                 rx_buffer_info->skb = next_buffer->skb;
956                                 rx_buffer_info->dma = next_buffer->dma;
957                                 next_buffer->skb = skb;
958                                 next_buffer->dma = 0;
959                         } else {
960                                 skb->next = next_buffer->skb;
961                                 skb->next->prev = skb;
962                         }
963                         rx_ring->non_eop_descs++;
964                         goto next_desc;
965                 }
966
967                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
968                         dev_kfree_skb_irq(skb);
969                         goto next_desc;
970                 }
971
972                 ixgbe_rx_checksum(adapter, rx_desc, skb);
973
974                 /* probably a little skewed due to removing CRC */
975                 total_rx_bytes += skb->len;
976                 total_rx_packets++;
977
978                 skb->protocol = eth_type_trans(skb, adapter->netdev);
979 #ifdef IXGBE_FCOE
980                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
981                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
982                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
983                         if (!ddp_bytes)
984                                 goto next_desc;
985                 }
986 #endif /* IXGBE_FCOE */
987                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
988
989 next_desc:
990                 rx_desc->wb.upper.status_error = 0;
991
992                 /* return some buffers to hardware, one at a time is too slow */
993                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
994                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
995                         cleaned_count = 0;
996                 }
997
998                 /* use prefetched values */
999                 rx_desc = next_rxd;
1000                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1001
1002                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1003         }
1004
1005         rx_ring->next_to_clean = i;
1006         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1007
1008         if (cleaned_count)
1009                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1010
1011 #ifdef IXGBE_FCOE
1012         /* include DDPed FCoE data */
1013         if (ddp_bytes > 0) {
1014                 unsigned int mss;
1015
1016                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1017                         sizeof(struct fc_frame_header) -
1018                         sizeof(struct fcoe_crc_eof);
1019                 if (mss > 512)
1020                         mss &= ~511;
1021                 total_rx_bytes += ddp_bytes;
1022                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1023         }
1024 #endif /* IXGBE_FCOE */
1025
1026         rx_ring->total_packets += total_rx_packets;
1027         rx_ring->total_bytes += total_rx_bytes;
1028         netdev->stats.rx_bytes += total_rx_bytes;
1029         netdev->stats.rx_packets += total_rx_packets;
1030
1031         return cleaned;
1032 }
1033
1034 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1035 /**
1036  * ixgbe_configure_msix - Configure MSI-X hardware
1037  * @adapter: board private structure
1038  *
1039  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1040  * interrupts.
1041  **/
1042 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1043 {
1044         struct ixgbe_q_vector *q_vector;
1045         int i, j, q_vectors, v_idx, r_idx;
1046         u32 mask;
1047
1048         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1049
1050         /*
1051          * Populate the IVAR table and set the ITR values to the
1052          * corresponding register.
1053          */
1054         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1055                 q_vector = adapter->q_vector[v_idx];
1056                 /* XXX for_each_set_bit(...) */
1057                 r_idx = find_first_bit(q_vector->rxr_idx,
1058                                        adapter->num_rx_queues);
1059
1060                 for (i = 0; i < q_vector->rxr_count; i++) {
1061                         j = adapter->rx_ring[r_idx]->reg_idx;
1062                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1063                         r_idx = find_next_bit(q_vector->rxr_idx,
1064                                               adapter->num_rx_queues,
1065                                               r_idx + 1);
1066                 }
1067                 r_idx = find_first_bit(q_vector->txr_idx,
1068                                        adapter->num_tx_queues);
1069
1070                 for (i = 0; i < q_vector->txr_count; i++) {
1071                         j = adapter->tx_ring[r_idx]->reg_idx;
1072                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1073                         r_idx = find_next_bit(q_vector->txr_idx,
1074                                               adapter->num_tx_queues,
1075                                               r_idx + 1);
1076                 }
1077
1078                 if (q_vector->txr_count && !q_vector->rxr_count)
1079                         /* tx only */
1080                         q_vector->eitr = adapter->tx_eitr_param;
1081                 else if (q_vector->rxr_count)
1082                         /* rx or mixed */
1083                         q_vector->eitr = adapter->rx_eitr_param;
1084
1085                 ixgbe_write_eitr(q_vector);
1086         }
1087
1088         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1089                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1090                                v_idx);
1091         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1092                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1093         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1094
1095         /* set up to autoclear timer, and the vectors */
1096         mask = IXGBE_EIMS_ENABLE_MASK;
1097         if (adapter->num_vfs)
1098                 mask &= ~(IXGBE_EIMS_OTHER |
1099                           IXGBE_EIMS_MAILBOX |
1100                           IXGBE_EIMS_LSC);
1101         else
1102                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1103         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1104 }
1105
1106 enum latency_range {
1107         lowest_latency = 0,
1108         low_latency = 1,
1109         bulk_latency = 2,
1110         latency_invalid = 255
1111 };
1112
1113 /**
1114  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1115  * @adapter: pointer to adapter
1116  * @eitr: eitr setting (ints per sec) to give last timeslice
1117  * @itr_setting: current throttle rate in ints/second
1118  * @packets: the number of packets during this measurement interval
1119  * @bytes: the number of bytes during this measurement interval
1120  *
1121  *      Stores a new ITR value based on packets and byte
1122  *      counts during the last interrupt.  The advantage of per interrupt
1123  *      computation is faster updates and more accurate ITR for the current
1124  *      traffic pattern.  Constants in this function were computed
1125  *      based on theoretical maximum wire speed and thresholds were set based
1126  *      on testing data as well as attempting to minimize response time
1127  *      while increasing bulk throughput.
1128  *      this functionality is controlled by the InterruptThrottleRate module
1129  *      parameter (see ixgbe_param.c)
1130  **/
1131 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1132                            u32 eitr, u8 itr_setting,
1133                            int packets, int bytes)
1134 {
1135         unsigned int retval = itr_setting;
1136         u32 timepassed_us;
1137         u64 bytes_perint;
1138
1139         if (packets == 0)
1140                 goto update_itr_done;
1141
1142
1143         /* simple throttlerate management
1144          *    0-20MB/s lowest (100000 ints/s)
1145          *   20-100MB/s low   (20000 ints/s)
1146          *  100-1249MB/s bulk (8000 ints/s)
1147          */
1148         /* what was last interrupt timeslice? */
1149         timepassed_us = 1000000/eitr;
1150         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1151
1152         switch (itr_setting) {
1153         case lowest_latency:
1154                 if (bytes_perint > adapter->eitr_low)
1155                         retval = low_latency;
1156                 break;
1157         case low_latency:
1158                 if (bytes_perint > adapter->eitr_high)
1159                         retval = bulk_latency;
1160                 else if (bytes_perint <= adapter->eitr_low)
1161                         retval = lowest_latency;
1162                 break;
1163         case bulk_latency:
1164                 if (bytes_perint <= adapter->eitr_high)
1165                         retval = low_latency;
1166                 break;
1167         }
1168
1169 update_itr_done:
1170         return retval;
1171 }
1172
1173 /**
1174  * ixgbe_write_eitr - write EITR register in hardware specific way
1175  * @q_vector: structure containing interrupt and ring information
1176  *
1177  * This function is made to be called by ethtool and by the driver
1178  * when it needs to update EITR registers at runtime.  Hardware
1179  * specific quirks/differences are taken care of here.
1180  */
1181 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1182 {
1183         struct ixgbe_adapter *adapter = q_vector->adapter;
1184         struct ixgbe_hw *hw = &adapter->hw;
1185         int v_idx = q_vector->v_idx;
1186         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1187
1188         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1189                 /* must write high and low 16 bits to reset counter */
1190                 itr_reg |= (itr_reg << 16);
1191         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1192                 /*
1193                  * set the WDIS bit to not clear the timer bits and cause an
1194                  * immediate assertion of the interrupt
1195                  */
1196                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1197         }
1198         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1199 }
1200
1201 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1202 {
1203         struct ixgbe_adapter *adapter = q_vector->adapter;
1204         u32 new_itr;
1205         u8 current_itr, ret_itr;
1206         int i, r_idx;
1207         struct ixgbe_ring *rx_ring, *tx_ring;
1208
1209         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1210         for (i = 0; i < q_vector->txr_count; i++) {
1211                 tx_ring = adapter->tx_ring[r_idx];
1212                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1213                                            q_vector->tx_itr,
1214                                            tx_ring->total_packets,
1215                                            tx_ring->total_bytes);
1216                 /* if the result for this queue would decrease interrupt
1217                  * rate for this vector then use that result */
1218                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1219                                     q_vector->tx_itr - 1 : ret_itr);
1220                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1221                                       r_idx + 1);
1222         }
1223
1224         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1225         for (i = 0; i < q_vector->rxr_count; i++) {
1226                 rx_ring = adapter->rx_ring[r_idx];
1227                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1228                                            q_vector->rx_itr,
1229                                            rx_ring->total_packets,
1230                                            rx_ring->total_bytes);
1231                 /* if the result for this queue would decrease interrupt
1232                  * rate for this vector then use that result */
1233                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1234                                     q_vector->rx_itr - 1 : ret_itr);
1235                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1236                                       r_idx + 1);
1237         }
1238
1239         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1240
1241         switch (current_itr) {
1242         /* counts and packets in update_itr are dependent on these numbers */
1243         case lowest_latency:
1244                 new_itr = 100000;
1245                 break;
1246         case low_latency:
1247                 new_itr = 20000; /* aka hwitr = ~200 */
1248                 break;
1249         case bulk_latency:
1250         default:
1251                 new_itr = 8000;
1252                 break;
1253         }
1254
1255         if (new_itr != q_vector->eitr) {
1256                 /* do an exponential smoothing */
1257                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1258
1259                 /* save the algorithm value here, not the smoothed one */
1260                 q_vector->eitr = new_itr;
1261
1262                 ixgbe_write_eitr(q_vector);
1263         }
1264
1265         return;
1266 }
1267
1268 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1269 {
1270         struct ixgbe_hw *hw = &adapter->hw;
1271
1272         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1273             (eicr & IXGBE_EICR_GPI_SDP1)) {
1274                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1275                 /* write to clear the interrupt */
1276                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1277         }
1278 }
1279
1280 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1281 {
1282         struct ixgbe_hw *hw = &adapter->hw;
1283
1284         if (eicr & IXGBE_EICR_GPI_SDP1) {
1285                 /* Clear the interrupt */
1286                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1287                 schedule_work(&adapter->multispeed_fiber_task);
1288         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1289                 /* Clear the interrupt */
1290                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1291                 schedule_work(&adapter->sfp_config_module_task);
1292         } else {
1293                 /* Interrupt isn't for us... */
1294                 return;
1295         }
1296 }
1297
1298 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1299 {
1300         struct ixgbe_hw *hw = &adapter->hw;
1301
1302         adapter->lsc_int++;
1303         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1304         adapter->link_check_timeout = jiffies;
1305         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1306                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1307                 IXGBE_WRITE_FLUSH(hw);
1308                 schedule_work(&adapter->watchdog_task);
1309         }
1310 }
1311
1312 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1313 {
1314         struct net_device *netdev = data;
1315         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1316         struct ixgbe_hw *hw = &adapter->hw;
1317         u32 eicr;
1318
1319         /*
1320          * Workaround for Silicon errata.  Use clear-by-write instead
1321          * of clear-by-read.  Reading with EICS will return the
1322          * interrupt causes without clearing, which later be done
1323          * with the write to EICR.
1324          */
1325         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1326         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1327
1328         if (eicr & IXGBE_EICR_LSC)
1329                 ixgbe_check_lsc(adapter);
1330
1331         if (eicr & IXGBE_EICR_MAILBOX)
1332                 ixgbe_msg_task(adapter);
1333
1334         if (hw->mac.type == ixgbe_mac_82598EB)
1335                 ixgbe_check_fan_failure(adapter, eicr);
1336
1337         if (hw->mac.type == ixgbe_mac_82599EB) {
1338                 ixgbe_check_sfp_event(adapter, eicr);
1339
1340                 /* Handle Flow Director Full threshold interrupt */
1341                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1342                         int i;
1343                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1344                         /* Disable transmits before FDIR Re-initialization */
1345                         netif_tx_stop_all_queues(netdev);
1346                         for (i = 0; i < adapter->num_tx_queues; i++) {
1347                                 struct ixgbe_ring *tx_ring =
1348                                                             adapter->tx_ring[i];
1349                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1350                                                        &tx_ring->reinit_state))
1351                                         schedule_work(&adapter->fdir_reinit_task);
1352                         }
1353                 }
1354         }
1355         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1356                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1357
1358         return IRQ_HANDLED;
1359 }
1360
1361 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1362                                            u64 qmask)
1363 {
1364         u32 mask;
1365
1366         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1367                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1368                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1369         } else {
1370                 mask = (qmask & 0xFFFFFFFF);
1371                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1372                 mask = (qmask >> 32);
1373                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1374         }
1375         /* skip the flush */
1376 }
1377
1378 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1379                                             u64 qmask)
1380 {
1381         u32 mask;
1382
1383         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1384                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1385                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1386         } else {
1387                 mask = (qmask & 0xFFFFFFFF);
1388                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1389                 mask = (qmask >> 32);
1390                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1391         }
1392         /* skip the flush */
1393 }
1394
1395 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1396 {
1397         struct ixgbe_q_vector *q_vector = data;
1398         struct ixgbe_adapter  *adapter = q_vector->adapter;
1399         struct ixgbe_ring     *tx_ring;
1400         int i, r_idx;
1401
1402         if (!q_vector->txr_count)
1403                 return IRQ_HANDLED;
1404
1405         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1406         for (i = 0; i < q_vector->txr_count; i++) {
1407                 tx_ring = adapter->tx_ring[r_idx];
1408                 tx_ring->total_bytes = 0;
1409                 tx_ring->total_packets = 0;
1410                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1411                                       r_idx + 1);
1412         }
1413
1414         /* EIAM disabled interrupts (on this vector) for us */
1415         napi_schedule(&q_vector->napi);
1416
1417         return IRQ_HANDLED;
1418 }
1419
1420 /**
1421  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1422  * @irq: unused
1423  * @data: pointer to our q_vector struct for this interrupt vector
1424  **/
1425 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1426 {
1427         struct ixgbe_q_vector *q_vector = data;
1428         struct ixgbe_adapter  *adapter = q_vector->adapter;
1429         struct ixgbe_ring  *rx_ring;
1430         int r_idx;
1431         int i;
1432
1433         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1434         for (i = 0;  i < q_vector->rxr_count; i++) {
1435                 rx_ring = adapter->rx_ring[r_idx];
1436                 rx_ring->total_bytes = 0;
1437                 rx_ring->total_packets = 0;
1438                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1439                                       r_idx + 1);
1440         }
1441
1442         if (!q_vector->rxr_count)
1443                 return IRQ_HANDLED;
1444
1445         /* disable interrupts on this vector only */
1446         /* EIAM disabled interrupts (on this vector) for us */
1447         napi_schedule(&q_vector->napi);
1448
1449         return IRQ_HANDLED;
1450 }
1451
1452 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1453 {
1454         struct ixgbe_q_vector *q_vector = data;
1455         struct ixgbe_adapter  *adapter = q_vector->adapter;
1456         struct ixgbe_ring  *ring;
1457         int r_idx;
1458         int i;
1459
1460         if (!q_vector->txr_count && !q_vector->rxr_count)
1461                 return IRQ_HANDLED;
1462
1463         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1464         for (i = 0; i < q_vector->txr_count; i++) {
1465                 ring = adapter->tx_ring[r_idx];
1466                 ring->total_bytes = 0;
1467                 ring->total_packets = 0;
1468                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1469                                       r_idx + 1);
1470         }
1471
1472         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1473         for (i = 0; i < q_vector->rxr_count; i++) {
1474                 ring = adapter->rx_ring[r_idx];
1475                 ring->total_bytes = 0;
1476                 ring->total_packets = 0;
1477                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1478                                       r_idx + 1);
1479         }
1480
1481         /* EIAM disabled interrupts (on this vector) for us */
1482         napi_schedule(&q_vector->napi);
1483
1484         return IRQ_HANDLED;
1485 }
1486
1487 /**
1488  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1489  * @napi: napi struct with our devices info in it
1490  * @budget: amount of work driver is allowed to do this pass, in packets
1491  *
1492  * This function is optimized for cleaning one queue only on a single
1493  * q_vector!!!
1494  **/
1495 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1496 {
1497         struct ixgbe_q_vector *q_vector =
1498                                container_of(napi, struct ixgbe_q_vector, napi);
1499         struct ixgbe_adapter *adapter = q_vector->adapter;
1500         struct ixgbe_ring *rx_ring = NULL;
1501         int work_done = 0;
1502         long r_idx;
1503
1504         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1505         rx_ring = adapter->rx_ring[r_idx];
1506 #ifdef CONFIG_IXGBE_DCA
1507         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1508                 ixgbe_update_rx_dca(adapter, rx_ring);
1509 #endif
1510
1511         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1512
1513         /* If all Rx work done, exit the polling mode */
1514         if (work_done < budget) {
1515                 napi_complete(napi);
1516                 if (adapter->rx_itr_setting & 1)
1517                         ixgbe_set_itr_msix(q_vector);
1518                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1519                         ixgbe_irq_enable_queues(adapter,
1520                                                 ((u64)1 << q_vector->v_idx));
1521         }
1522
1523         return work_done;
1524 }
1525
1526 /**
1527  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1528  * @napi: napi struct with our devices info in it
1529  * @budget: amount of work driver is allowed to do this pass, in packets
1530  *
1531  * This function will clean more than one rx queue associated with a
1532  * q_vector.
1533  **/
1534 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1535 {
1536         struct ixgbe_q_vector *q_vector =
1537                                container_of(napi, struct ixgbe_q_vector, napi);
1538         struct ixgbe_adapter *adapter = q_vector->adapter;
1539         struct ixgbe_ring *ring = NULL;
1540         int work_done = 0, i;
1541         long r_idx;
1542         bool tx_clean_complete = true;
1543
1544         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1545         for (i = 0; i < q_vector->txr_count; i++) {
1546                 ring = adapter->tx_ring[r_idx];
1547 #ifdef CONFIG_IXGBE_DCA
1548                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1549                         ixgbe_update_tx_dca(adapter, ring);
1550 #endif
1551                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1552                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1553                                       r_idx + 1);
1554         }
1555
1556         /* attempt to distribute budget to each queue fairly, but don't allow
1557          * the budget to go below 1 because we'll exit polling */
1558         budget /= (q_vector->rxr_count ?: 1);
1559         budget = max(budget, 1);
1560         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1561         for (i = 0; i < q_vector->rxr_count; i++) {
1562                 ring = adapter->rx_ring[r_idx];
1563 #ifdef CONFIG_IXGBE_DCA
1564                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1565                         ixgbe_update_rx_dca(adapter, ring);
1566 #endif
1567                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1568                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1569                                       r_idx + 1);
1570         }
1571
1572         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1573         ring = adapter->rx_ring[r_idx];
1574         /* If all Rx work done, exit the polling mode */
1575         if (work_done < budget) {
1576                 napi_complete(napi);
1577                 if (adapter->rx_itr_setting & 1)
1578                         ixgbe_set_itr_msix(q_vector);
1579                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1580                         ixgbe_irq_enable_queues(adapter,
1581                                                 ((u64)1 << q_vector->v_idx));
1582                 return 0;
1583         }
1584
1585         return work_done;
1586 }
1587
1588 /**
1589  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1590  * @napi: napi struct with our devices info in it
1591  * @budget: amount of work driver is allowed to do this pass, in packets
1592  *
1593  * This function is optimized for cleaning one queue only on a single
1594  * q_vector!!!
1595  **/
1596 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1597 {
1598         struct ixgbe_q_vector *q_vector =
1599                                container_of(napi, struct ixgbe_q_vector, napi);
1600         struct ixgbe_adapter *adapter = q_vector->adapter;
1601         struct ixgbe_ring *tx_ring = NULL;
1602         int work_done = 0;
1603         long r_idx;
1604
1605         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1606         tx_ring = adapter->tx_ring[r_idx];
1607 #ifdef CONFIG_IXGBE_DCA
1608         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1609                 ixgbe_update_tx_dca(adapter, tx_ring);
1610 #endif
1611
1612         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1613                 work_done = budget;
1614
1615         /* If all Tx work done, exit the polling mode */
1616         if (work_done < budget) {
1617                 napi_complete(napi);
1618                 if (adapter->tx_itr_setting & 1)
1619                         ixgbe_set_itr_msix(q_vector);
1620                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1621                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1622         }
1623
1624         return work_done;
1625 }
1626
1627 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1628                                      int r_idx)
1629 {
1630         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1631
1632         set_bit(r_idx, q_vector->rxr_idx);
1633         q_vector->rxr_count++;
1634 }
1635
1636 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1637                                      int t_idx)
1638 {
1639         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1640
1641         set_bit(t_idx, q_vector->txr_idx);
1642         q_vector->txr_count++;
1643 }
1644
1645 /**
1646  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1647  * @adapter: board private structure to initialize
1648  * @vectors: allotted vector count for descriptor rings
1649  *
1650  * This function maps descriptor rings to the queue-specific vectors
1651  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1652  * one vector per ring/queue, but on a constrained vector budget, we
1653  * group the rings as "efficiently" as possible.  You would add new
1654  * mapping configurations in here.
1655  **/
1656 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1657                                       int vectors)
1658 {
1659         int v_start = 0;
1660         int rxr_idx = 0, txr_idx = 0;
1661         int rxr_remaining = adapter->num_rx_queues;
1662         int txr_remaining = adapter->num_tx_queues;
1663         int i, j;
1664         int rqpv, tqpv;
1665         int err = 0;
1666
1667         /* No mapping required if MSI-X is disabled. */
1668         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1669                 goto out;
1670
1671         /*
1672          * The ideal configuration...
1673          * We have enough vectors to map one per queue.
1674          */
1675         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1676                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1677                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1678
1679                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1680                         map_vector_to_txq(adapter, v_start, txr_idx);
1681
1682                 goto out;
1683         }
1684
1685         /*
1686          * If we don't have enough vectors for a 1-to-1
1687          * mapping, we'll have to group them so there are
1688          * multiple queues per vector.
1689          */
1690         /* Re-adjusting *qpv takes care of the remainder. */
1691         for (i = v_start; i < vectors; i++) {
1692                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1693                 for (j = 0; j < rqpv; j++) {
1694                         map_vector_to_rxq(adapter, i, rxr_idx);
1695                         rxr_idx++;
1696                         rxr_remaining--;
1697                 }
1698         }
1699         for (i = v_start; i < vectors; i++) {
1700                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1701                 for (j = 0; j < tqpv; j++) {
1702                         map_vector_to_txq(adapter, i, txr_idx);
1703                         txr_idx++;
1704                         txr_remaining--;
1705                 }
1706         }
1707
1708 out:
1709         return err;
1710 }
1711
1712 /**
1713  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1714  * @adapter: board private structure
1715  *
1716  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1717  * interrupts from the kernel.
1718  **/
1719 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1720 {
1721         struct net_device *netdev = adapter->netdev;
1722         irqreturn_t (*handler)(int, void *);
1723         int i, vector, q_vectors, err;
1724         int ri=0, ti=0;
1725
1726         /* Decrement for Other and TCP Timer vectors */
1727         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1728
1729         /* Map the Tx/Rx rings to the vectors we were allotted. */
1730         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1731         if (err)
1732                 goto out;
1733
1734 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1735                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1736                          &ixgbe_msix_clean_many)
1737         for (vector = 0; vector < q_vectors; vector++) {
1738                 handler = SET_HANDLER(adapter->q_vector[vector]);
1739
1740                 if(handler == &ixgbe_msix_clean_rx) {
1741                         sprintf(adapter->name[vector], "%s-%s-%d",
1742                                 netdev->name, "rx", ri++);
1743                 }
1744                 else if(handler == &ixgbe_msix_clean_tx) {
1745                         sprintf(adapter->name[vector], "%s-%s-%d",
1746                                 netdev->name, "tx", ti++);
1747                 }
1748                 else
1749                         sprintf(adapter->name[vector], "%s-%s-%d",
1750                                 netdev->name, "TxRx", vector);
1751
1752                 err = request_irq(adapter->msix_entries[vector].vector,
1753                                   handler, 0, adapter->name[vector],
1754                                   adapter->q_vector[vector]);
1755                 if (err) {
1756                         DPRINTK(PROBE, ERR,
1757                                 "request_irq failed for MSIX interrupt "
1758                                 "Error: %d\n", err);
1759                         goto free_queue_irqs;
1760                 }
1761         }
1762
1763         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1764         err = request_irq(adapter->msix_entries[vector].vector,
1765                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1766         if (err) {
1767                 DPRINTK(PROBE, ERR,
1768                         "request_irq for msix_lsc failed: %d\n", err);
1769                 goto free_queue_irqs;
1770         }
1771
1772         return 0;
1773
1774 free_queue_irqs:
1775         for (i = vector - 1; i >= 0; i--)
1776                 free_irq(adapter->msix_entries[--vector].vector,
1777                          adapter->q_vector[i]);
1778         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1779         pci_disable_msix(adapter->pdev);
1780         kfree(adapter->msix_entries);
1781         adapter->msix_entries = NULL;
1782 out:
1783         return err;
1784 }
1785
1786 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1787 {
1788         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1789         u8 current_itr;
1790         u32 new_itr = q_vector->eitr;
1791         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
1792         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
1793
1794         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1795                                             q_vector->tx_itr,
1796                                             tx_ring->total_packets,
1797                                             tx_ring->total_bytes);
1798         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1799                                             q_vector->rx_itr,
1800                                             rx_ring->total_packets,
1801                                             rx_ring->total_bytes);
1802
1803         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1804
1805         switch (current_itr) {
1806         /* counts and packets in update_itr are dependent on these numbers */
1807         case lowest_latency:
1808                 new_itr = 100000;
1809                 break;
1810         case low_latency:
1811                 new_itr = 20000; /* aka hwitr = ~200 */
1812                 break;
1813         case bulk_latency:
1814                 new_itr = 8000;
1815                 break;
1816         default:
1817                 break;
1818         }
1819
1820         if (new_itr != q_vector->eitr) {
1821                 /* do an exponential smoothing */
1822                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1823
1824                 /* save the algorithm value here, not the smoothed one */
1825                 q_vector->eitr = new_itr;
1826
1827                 ixgbe_write_eitr(q_vector);
1828         }
1829
1830         return;
1831 }
1832
1833 /**
1834  * ixgbe_irq_enable - Enable default interrupt generation settings
1835  * @adapter: board private structure
1836  **/
1837 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1838 {
1839         u32 mask;
1840
1841         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1842         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1843                 mask |= IXGBE_EIMS_GPI_SDP1;
1844         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1845                 mask |= IXGBE_EIMS_ECC;
1846                 mask |= IXGBE_EIMS_GPI_SDP1;
1847                 mask |= IXGBE_EIMS_GPI_SDP2;
1848                 if (adapter->num_vfs)
1849                         mask |= IXGBE_EIMS_MAILBOX;
1850         }
1851         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1852             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1853                 mask |= IXGBE_EIMS_FLOW_DIR;
1854
1855         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1856         ixgbe_irq_enable_queues(adapter, ~0);
1857         IXGBE_WRITE_FLUSH(&adapter->hw);
1858
1859         if (adapter->num_vfs > 32) {
1860                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1861                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1862         }
1863 }
1864
1865 /**
1866  * ixgbe_intr - legacy mode Interrupt Handler
1867  * @irq: interrupt number
1868  * @data: pointer to a network interface device structure
1869  **/
1870 static irqreturn_t ixgbe_intr(int irq, void *data)
1871 {
1872         struct net_device *netdev = data;
1873         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1874         struct ixgbe_hw *hw = &adapter->hw;
1875         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1876         u32 eicr;
1877
1878         /*
1879          * Workaround for silicon errata.  Mask the interrupts
1880          * before the read of EICR.
1881          */
1882         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1883
1884         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1885          * therefore no explict interrupt disable is necessary */
1886         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1887         if (!eicr) {
1888                 /* shared interrupt alert!
1889                  * make sure interrupts are enabled because the read will
1890                  * have disabled interrupts due to EIAM */
1891                 ixgbe_irq_enable(adapter);
1892                 return IRQ_NONE;        /* Not our interrupt */
1893         }
1894
1895         if (eicr & IXGBE_EICR_LSC)
1896                 ixgbe_check_lsc(adapter);
1897
1898         if (hw->mac.type == ixgbe_mac_82599EB)
1899                 ixgbe_check_sfp_event(adapter, eicr);
1900
1901         ixgbe_check_fan_failure(adapter, eicr);
1902
1903         if (napi_schedule_prep(&(q_vector->napi))) {
1904                 adapter->tx_ring[0]->total_packets = 0;
1905                 adapter->tx_ring[0]->total_bytes = 0;
1906                 adapter->rx_ring[0]->total_packets = 0;
1907                 adapter->rx_ring[0]->total_bytes = 0;
1908                 /* would disable interrupts here but EIAM disabled it */
1909                 __napi_schedule(&(q_vector->napi));
1910         }
1911
1912         return IRQ_HANDLED;
1913 }
1914
1915 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1916 {
1917         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1918
1919         for (i = 0; i < q_vectors; i++) {
1920                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1921                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1922                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1923                 q_vector->rxr_count = 0;
1924                 q_vector->txr_count = 0;
1925         }
1926 }
1927
1928 /**
1929  * ixgbe_request_irq - initialize interrupts
1930  * @adapter: board private structure
1931  *
1932  * Attempts to configure interrupts using the best available
1933  * capabilities of the hardware and kernel.
1934  **/
1935 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1936 {
1937         struct net_device *netdev = adapter->netdev;
1938         int err;
1939
1940         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1941                 err = ixgbe_request_msix_irqs(adapter);
1942         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1943                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
1944                                   netdev->name, netdev);
1945         } else {
1946                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
1947                                   netdev->name, netdev);
1948         }
1949
1950         if (err)
1951                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1952
1953         return err;
1954 }
1955
1956 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1957 {
1958         struct net_device *netdev = adapter->netdev;
1959
1960         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1961                 int i, q_vectors;
1962
1963                 q_vectors = adapter->num_msix_vectors;
1964
1965                 i = q_vectors - 1;
1966                 free_irq(adapter->msix_entries[i].vector, netdev);
1967
1968                 i--;
1969                 for (; i >= 0; i--) {
1970                         free_irq(adapter->msix_entries[i].vector,
1971                                  adapter->q_vector[i]);
1972                 }
1973
1974                 ixgbe_reset_q_vectors(adapter);
1975         } else {
1976                 free_irq(adapter->pdev->irq, netdev);
1977         }
1978 }
1979
1980 /**
1981  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1982  * @adapter: board private structure
1983  **/
1984 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1985 {
1986         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1987                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1988         } else {
1989                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1990                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1991                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1992                 if (adapter->num_vfs > 32)
1993                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
1994         }
1995         IXGBE_WRITE_FLUSH(&adapter->hw);
1996         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1997                 int i;
1998                 for (i = 0; i < adapter->num_msix_vectors; i++)
1999                         synchronize_irq(adapter->msix_entries[i].vector);
2000         } else {
2001                 synchronize_irq(adapter->pdev->irq);
2002         }
2003 }
2004
2005 /**
2006  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2007  *
2008  **/
2009 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2010 {
2011         struct ixgbe_hw *hw = &adapter->hw;
2012
2013         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2014                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2015
2016         ixgbe_set_ivar(adapter, 0, 0, 0);
2017         ixgbe_set_ivar(adapter, 1, 0, 0);
2018
2019         map_vector_to_rxq(adapter, 0, 0);
2020         map_vector_to_txq(adapter, 0, 0);
2021
2022         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
2023 }
2024
2025 /**
2026  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2027  * @adapter: board private structure
2028  *
2029  * Configure the Tx unit of the MAC after a reset.
2030  **/
2031 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2032 {
2033         u64 tdba;
2034         struct ixgbe_hw *hw = &adapter->hw;
2035         u32 i, j, tdlen, txctrl;
2036
2037         /* Setup the HW Tx Head and Tail descriptor pointers */
2038         for (i = 0; i < adapter->num_tx_queues; i++) {
2039                 struct ixgbe_ring *ring = adapter->tx_ring[i];
2040                 j = ring->reg_idx;
2041                 tdba = ring->dma;
2042                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
2043                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
2044                                 (tdba & DMA_BIT_MASK(32)));
2045                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2046                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2047                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2048                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
2049                 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2050                 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
2051                 /*
2052                  * Disable Tx Head Writeback RO bit, since this hoses
2053                  * bookkeeping if things aren't delivered in order.
2054                  */
2055                 switch (hw->mac.type) {
2056                 case ixgbe_mac_82598EB:
2057                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2058                         break;
2059                 case ixgbe_mac_82599EB:
2060                 default:
2061                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2062                         break;
2063                 }
2064                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
2065                 switch (hw->mac.type) {
2066                 case ixgbe_mac_82598EB:
2067                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2068                         break;
2069                 case ixgbe_mac_82599EB:
2070                 default:
2071                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2072                         break;
2073                 }
2074         }
2075
2076         if (hw->mac.type == ixgbe_mac_82599EB) {
2077                 u32 rttdcs;
2078                 u32 mask;
2079
2080                 /* disable the arbiter while setting MTQC */
2081                 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2082                 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2083                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2084
2085                 /* set transmit pool layout */
2086                 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2087                 switch (adapter->flags & mask) {
2088
2089                 case (IXGBE_FLAG_SRIOV_ENABLED):
2090                         IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2091                                         (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2092                         break;
2093
2094                 case (IXGBE_FLAG_DCB_ENABLED):
2095                         /* We enable 8 traffic classes, DCB only */
2096                         IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2097                                       (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2098                         break;
2099
2100                 default:
2101                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2102                         break;
2103                 }
2104
2105                 /* re-eable the arbiter */
2106                 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2107                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2108         }
2109 }
2110
2111 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2112
2113 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2114                                    struct ixgbe_ring *rx_ring)
2115 {
2116         u32 srrctl;
2117         int index;
2118         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2119
2120         index = rx_ring->reg_idx;
2121         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2122                 unsigned long mask;
2123                 mask = (unsigned long) feature[RING_F_RSS].mask;
2124                 index = index & mask;
2125         }
2126         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2127
2128         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2129         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2130
2131         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2132                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2133
2134         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2135 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2136                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2137 #else
2138                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2139 #endif
2140                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2141         } else {
2142                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2143                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2144                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2145         }
2146
2147         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2148 }
2149
2150 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2151 {
2152         u32 mrqc = 0;
2153         int mask;
2154
2155         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2156                 return mrqc;
2157
2158         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2159 #ifdef CONFIG_IXGBE_DCB
2160                                  | IXGBE_FLAG_DCB_ENABLED
2161 #endif
2162                                  | IXGBE_FLAG_SRIOV_ENABLED
2163                                 );
2164
2165         switch (mask) {
2166         case (IXGBE_FLAG_RSS_ENABLED):
2167                 mrqc = IXGBE_MRQC_RSSEN;
2168                 break;
2169         case (IXGBE_FLAG_SRIOV_ENABLED):
2170                 mrqc = IXGBE_MRQC_VMDQEN;
2171                 break;
2172 #ifdef CONFIG_IXGBE_DCB
2173         case (IXGBE_FLAG_DCB_ENABLED):
2174                 mrqc = IXGBE_MRQC_RT8TCEN;
2175                 break;
2176 #endif /* CONFIG_IXGBE_DCB */
2177         default:
2178                 break;
2179         }
2180
2181         return mrqc;
2182 }
2183
2184 /**
2185  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2186  * @adapter:    address of board private structure
2187  * @index:      index of ring to set
2188  **/
2189 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
2190 {
2191         struct ixgbe_ring *rx_ring;
2192         struct ixgbe_hw *hw = &adapter->hw;
2193         int j;
2194         u32 rscctrl;
2195         int rx_buf_len;
2196
2197         rx_ring = adapter->rx_ring[index];
2198         j = rx_ring->reg_idx;
2199         rx_buf_len = rx_ring->rx_buf_len;
2200         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2201         rscctrl |= IXGBE_RSCCTL_RSCEN;
2202         /*
2203          * we must limit the number of descriptors so that the
2204          * total size of max desc * buf_len is not greater
2205          * than 65535
2206          */
2207         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2208 #if (MAX_SKB_FRAGS > 16)
2209                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2210 #elif (MAX_SKB_FRAGS > 8)
2211                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2212 #elif (MAX_SKB_FRAGS > 4)
2213                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2214 #else
2215                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2216 #endif
2217         } else {
2218                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2219                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2220                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2221                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2222                 else
2223                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2224         }
2225         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2226 }
2227
2228 /**
2229  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2230  * @adapter: board private structure
2231  *
2232  * Configure the Rx unit of the MAC after a reset.
2233  **/
2234 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2235 {
2236         u64 rdba;
2237         struct ixgbe_hw *hw = &adapter->hw;
2238         struct ixgbe_ring *rx_ring;
2239         struct net_device *netdev = adapter->netdev;
2240         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2241         int i, j;
2242         u32 rdlen, rxctrl, rxcsum;
2243         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2244                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2245                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2246         u32 fctrl, hlreg0;
2247         u32 reta = 0, mrqc = 0;
2248         u32 rdrxctl;
2249         int rx_buf_len;
2250
2251         /* Decide whether to use packet split mode or not */
2252         /* Do not use packet split if we're in SR-IOV Mode */
2253         if (!adapter->num_vfs)
2254                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2255
2256         /* Set the RX buffer length according to the mode */
2257         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2258                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2259                 if (hw->mac.type == ixgbe_mac_82599EB) {
2260                         /* PSRTYPE must be initialized in 82599 */
2261                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2262                                       IXGBE_PSRTYPE_UDPHDR |
2263                                       IXGBE_PSRTYPE_IPV4HDR |
2264                                       IXGBE_PSRTYPE_IPV6HDR |
2265                                       IXGBE_PSRTYPE_L2HDR;
2266                         IXGBE_WRITE_REG(hw,
2267                                         IXGBE_PSRTYPE(adapter->num_vfs),
2268                                         psrtype);
2269                 }
2270         } else {
2271                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2272                     (netdev->mtu <= ETH_DATA_LEN))
2273                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2274                 else
2275                         rx_buf_len = ALIGN(max_frame, 1024);
2276         }
2277
2278         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2279         fctrl |= IXGBE_FCTRL_BAM;
2280         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2281         fctrl |= IXGBE_FCTRL_PMCF;
2282         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2283
2284         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2285         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2286                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2287         else
2288                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2289 #ifdef IXGBE_FCOE
2290         if (netdev->features & NETIF_F_FCOE_MTU)
2291                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2292 #endif
2293         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2294
2295         rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
2296         /* disable receives while setting up the descriptors */
2297         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2298         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2299
2300         /*
2301          * Setup the HW Rx Head and Tail Descriptor Pointers and
2302          * the Base and Length of the Rx Descriptor Ring
2303          */
2304         for (i = 0; i < adapter->num_rx_queues; i++) {
2305                 rx_ring = adapter->rx_ring[i];
2306                 rdba = rx_ring->dma;
2307                 j = rx_ring->reg_idx;
2308                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2309                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2310                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2311                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2312                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2313                 rx_ring->head = IXGBE_RDH(j);
2314                 rx_ring->tail = IXGBE_RDT(j);
2315                 rx_ring->rx_buf_len = rx_buf_len;
2316
2317                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2318                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2319                 else
2320                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2321
2322 #ifdef IXGBE_FCOE
2323                 if (netdev->features & NETIF_F_FCOE_MTU) {
2324                         struct ixgbe_ring_feature *f;
2325                         f = &adapter->ring_feature[RING_F_FCOE];
2326                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2327                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2328                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2329                                         rx_ring->rx_buf_len =
2330                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2331                         }
2332                 }
2333
2334 #endif /* IXGBE_FCOE */
2335                 ixgbe_configure_srrctl(adapter, rx_ring);
2336         }
2337
2338         if (hw->mac.type == ixgbe_mac_82598EB) {
2339                 /*
2340                  * For VMDq support of different descriptor types or
2341                  * buffer sizes through the use of multiple SRRCTL
2342                  * registers, RDRXCTL.MVMEN must be set to 1
2343                  *
2344                  * also, the manual doesn't mention it clearly but DCA hints
2345                  * will only use queue 0's tags unless this bit is set.  Side
2346                  * effects of setting this bit are only that SRRCTL must be
2347                  * fully programmed [0..15]
2348                  */
2349                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2350                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2351                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2352         }
2353
2354         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2355                 u32 vt_reg_bits;
2356                 u32 reg_offset, vf_shift;
2357                 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2358                 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2359                         | IXGBE_VT_CTL_REPLEN;
2360                 vt_reg_bits |= (adapter->num_vfs <<
2361                                 IXGBE_VT_CTL_POOL_SHIFT);
2362                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2363                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2364
2365                 vf_shift = adapter->num_vfs % 32;
2366                 reg_offset = adapter->num_vfs / 32;
2367                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2368                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2369                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2370                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2371                 /* Enable only the PF's pool for Tx/Rx */
2372                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2373                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2374                 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2375                 ixgbe_set_vmolr(hw, adapter->num_vfs);
2376         }
2377
2378         /* Program MRQC for the distribution of queues */
2379         mrqc = ixgbe_setup_mrqc(adapter);
2380
2381         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2382                 /* Fill out redirection table */
2383                 for (i = 0, j = 0; i < 128; i++, j++) {
2384                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2385                                 j = 0;
2386                         /* reta = 4-byte sliding window of
2387                          * 0x00..(indices-1)(indices-1)00..etc. */
2388                         reta = (reta << 8) | (j * 0x11);
2389                         if ((i & 3) == 3)
2390                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2391                 }
2392
2393                 /* Fill out hash function seeds */
2394                 for (i = 0; i < 10; i++)
2395                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2396
2397                 if (hw->mac.type == ixgbe_mac_82598EB)
2398                         mrqc |= IXGBE_MRQC_RSSEN;
2399                     /* Perform hash on these packet types */
2400                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2401                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2402                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2403                       | IXGBE_MRQC_RSS_FIELD_IPV6
2404                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2405                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2406         }
2407         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2408
2409         if (adapter->num_vfs) {
2410                 u32 reg;
2411
2412                 /* Map PF MAC address in RAR Entry 0 to first pool
2413                  * following VFs */
2414                 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2415
2416                 /* Set up VF register offsets for selected VT Mode, i.e.
2417                  * 64 VFs for SR-IOV */
2418                 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2419                 reg |= IXGBE_GCR_EXT_SRIOV;
2420                 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2421         }
2422
2423         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2424
2425         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2426             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2427                 /* Disable indicating checksum in descriptor, enables
2428                  * RSS hash */
2429                 rxcsum |= IXGBE_RXCSUM_PCSD;
2430         }
2431         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2432                 /* Enable IPv4 payload checksum for UDP fragments
2433                  * if PCSD is not set */
2434                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2435         }
2436
2437         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2438
2439         if (hw->mac.type == ixgbe_mac_82599EB) {
2440                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2441                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2442                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2443                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2444         }
2445
2446         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2447                 /* Enable 82599 HW-RSC */
2448                 for (i = 0; i < adapter->num_rx_queues; i++)
2449                         ixgbe_configure_rscctl(adapter, i);
2450
2451                 /* Disable RSC for ACK packets */
2452                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2453                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2454         }
2455 }
2456
2457 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2458 {
2459         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2460         struct ixgbe_hw *hw = &adapter->hw;
2461         int pool_ndx = adapter->num_vfs;
2462
2463         /* add VID to filter table */
2464         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
2465 }
2466
2467 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2468 {
2469         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2470         struct ixgbe_hw *hw = &adapter->hw;
2471         int pool_ndx = adapter->num_vfs;
2472
2473         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2474                 ixgbe_irq_disable(adapter);
2475
2476         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2477
2478         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2479                 ixgbe_irq_enable(adapter);
2480
2481         /* remove VID from filter table */
2482         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
2483 }
2484
2485 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2486                                    struct vlan_group *grp)
2487 {
2488         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2489         u32 ctrl;
2490         int i, j;
2491
2492         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2493                 ixgbe_irq_disable(adapter);
2494         adapter->vlgrp = grp;
2495
2496         /*
2497          * For a DCB driver, always enable VLAN tag stripping so we can
2498          * still receive traffic from a DCB-enabled host even if we're
2499          * not in DCB mode.
2500          */
2501         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2502
2503         /* Disable CFI check */
2504         ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2505
2506         /* enable VLAN tag stripping */
2507         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2508                 ctrl |= IXGBE_VLNCTRL_VME;
2509         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2510                 for (i = 0; i < adapter->num_rx_queues; i++) {
2511                         u32 ctrl;
2512                         j = adapter->rx_ring[i]->reg_idx;
2513                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2514                         ctrl |= IXGBE_RXDCTL_VME;
2515                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2516                 }
2517         }
2518
2519         IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2520
2521         ixgbe_vlan_rx_add_vid(netdev, 0);
2522
2523         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2524                 ixgbe_irq_enable(adapter);
2525 }
2526
2527 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2528 {
2529         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2530
2531         if (adapter->vlgrp) {
2532                 u16 vid;
2533                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2534                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2535                                 continue;
2536                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2537                 }
2538         }
2539 }
2540
2541 /**
2542  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2543  * @netdev: network interface device structure
2544  *
2545  * The set_rx_method entry point is called whenever the unicast/multicast
2546  * address list or the network interface flags are updated.  This routine is
2547  * responsible for configuring the hardware for proper unicast, multicast and
2548  * promiscuous mode.
2549  **/
2550 void ixgbe_set_rx_mode(struct net_device *netdev)
2551 {
2552         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2553         struct ixgbe_hw *hw = &adapter->hw;
2554         u32 fctrl, vlnctrl;
2555
2556         /* Check for Promiscuous and All Multicast modes */
2557
2558         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2559         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2560
2561         if (netdev->flags & IFF_PROMISC) {
2562                 hw->addr_ctrl.user_set_promisc = 1;
2563                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2564                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2565         } else {
2566                 if (netdev->flags & IFF_ALLMULTI) {
2567                         fctrl |= IXGBE_FCTRL_MPE;
2568                         fctrl &= ~IXGBE_FCTRL_UPE;
2569                 } else {
2570                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2571                 }
2572                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2573                 hw->addr_ctrl.user_set_promisc = 0;
2574         }
2575
2576         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2577         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2578
2579         /* reprogram secondary unicast list */
2580         hw->mac.ops.update_uc_addr_list(hw, netdev);
2581
2582         /* reprogram multicast list */
2583         hw->mac.ops.update_mc_addr_list(hw, netdev);
2584
2585         if (adapter->num_vfs)
2586                 ixgbe_restore_vf_multicasts(adapter);
2587 }
2588
2589 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2590 {
2591         int q_idx;
2592         struct ixgbe_q_vector *q_vector;
2593         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2594
2595         /* legacy and MSI only use one vector */
2596         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2597                 q_vectors = 1;
2598
2599         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2600                 struct napi_struct *napi;
2601                 q_vector = adapter->q_vector[q_idx];
2602                 napi = &q_vector->napi;
2603                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2604                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2605                                 if (q_vector->txr_count == 1)
2606                                         napi->poll = &ixgbe_clean_txonly;
2607                                 else if (q_vector->rxr_count == 1)
2608                                         napi->poll = &ixgbe_clean_rxonly;
2609                         }
2610                 }
2611
2612                 napi_enable(napi);
2613         }
2614 }
2615
2616 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2617 {
2618         int q_idx;
2619         struct ixgbe_q_vector *q_vector;
2620         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2621
2622         /* legacy and MSI only use one vector */
2623         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2624                 q_vectors = 1;
2625
2626         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2627                 q_vector = adapter->q_vector[q_idx];
2628                 napi_disable(&q_vector->napi);
2629         }
2630 }
2631
2632 #ifdef CONFIG_IXGBE_DCB
2633 /*
2634  * ixgbe_configure_dcb - Configure DCB hardware
2635  * @adapter: ixgbe adapter struct
2636  *
2637  * This is called by the driver on open to configure the DCB hardware.
2638  * This is also called by the gennetlink interface when reconfiguring
2639  * the DCB state.
2640  */
2641 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2642 {
2643         struct ixgbe_hw *hw = &adapter->hw;
2644         u32 txdctl, vlnctrl;
2645         int i, j;
2646
2647         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2648         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2649         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2650
2651         /* reconfigure the hardware */
2652         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2653
2654         for (i = 0; i < adapter->num_tx_queues; i++) {
2655                 j = adapter->tx_ring[i]->reg_idx;
2656                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2657                 /* PThresh workaround for Tx hang with DFP enabled. */
2658                 txdctl |= 32;
2659                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2660         }
2661         /* Enable VLAN tag insert/strip */
2662         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2663         if (hw->mac.type == ixgbe_mac_82598EB) {
2664                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2665                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2666                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2667         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2668                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2669                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2670                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2671                 for (i = 0; i < adapter->num_rx_queues; i++) {
2672                         j = adapter->rx_ring[i]->reg_idx;
2673                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2674                         vlnctrl |= IXGBE_RXDCTL_VME;
2675                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2676                 }
2677         }
2678         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2679 }
2680
2681 #endif
2682 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2683 {
2684         struct net_device *netdev = adapter->netdev;
2685         struct ixgbe_hw *hw = &adapter->hw;
2686         int i;
2687
2688         ixgbe_set_rx_mode(netdev);
2689
2690         ixgbe_restore_vlan(adapter);
2691 #ifdef CONFIG_IXGBE_DCB
2692         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2693                 if (hw->mac.type == ixgbe_mac_82598EB)
2694                         netif_set_gso_max_size(netdev, 32768);
2695                 else
2696                         netif_set_gso_max_size(netdev, 65536);
2697                 ixgbe_configure_dcb(adapter);
2698         } else {
2699                 netif_set_gso_max_size(netdev, 65536);
2700         }
2701 #else
2702         netif_set_gso_max_size(netdev, 65536);
2703 #endif
2704
2705 #ifdef IXGBE_FCOE
2706         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2707                 ixgbe_configure_fcoe(adapter);
2708
2709 #endif /* IXGBE_FCOE */
2710         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2711                 for (i = 0; i < adapter->num_tx_queues; i++)
2712                         adapter->tx_ring[i]->atr_sample_rate =
2713                                                        adapter->atr_sample_rate;
2714                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2715         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2716                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2717         }
2718
2719         ixgbe_configure_tx(adapter);
2720         ixgbe_configure_rx(adapter);
2721         for (i = 0; i < adapter->num_rx_queues; i++)
2722                 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
2723                                        (adapter->rx_ring[i]->count - 1));
2724 }
2725
2726 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2727 {
2728         switch (hw->phy.type) {
2729         case ixgbe_phy_sfp_avago:
2730         case ixgbe_phy_sfp_ftl:
2731         case ixgbe_phy_sfp_intel:
2732         case ixgbe_phy_sfp_unknown:
2733         case ixgbe_phy_tw_tyco:
2734         case ixgbe_phy_tw_unknown:
2735                 return true;
2736         default:
2737                 return false;
2738         }
2739 }
2740
2741 /**
2742  * ixgbe_sfp_link_config - set up SFP+ link
2743  * @adapter: pointer to private adapter struct
2744  **/
2745 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2746 {
2747         struct ixgbe_hw *hw = &adapter->hw;
2748
2749                 if (hw->phy.multispeed_fiber) {
2750                         /*
2751                          * In multispeed fiber setups, the device may not have
2752                          * had a physical connection when the driver loaded.
2753                          * If that's the case, the initial link configuration
2754                          * couldn't get the MAC into 10G or 1G mode, so we'll
2755                          * never have a link status change interrupt fire.
2756                          * We need to try and force an autonegotiation
2757                          * session, then bring up link.
2758                          */
2759                         hw->mac.ops.setup_sfp(hw);
2760                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2761                                 schedule_work(&adapter->multispeed_fiber_task);
2762                 } else {
2763                         /*
2764                          * Direct Attach Cu and non-multispeed fiber modules
2765                          * still need to be configured properly prior to
2766                          * attempting link.
2767                          */
2768                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2769                                 schedule_work(&adapter->sfp_config_module_task);
2770                 }
2771 }
2772
2773 /**
2774  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2775  * @hw: pointer to private hardware struct
2776  *
2777  * Returns 0 on success, negative on failure
2778  **/
2779 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2780 {
2781         u32 autoneg;
2782         bool negotiation, link_up = false;
2783         u32 ret = IXGBE_ERR_LINK_SETUP;
2784
2785         if (hw->mac.ops.check_link)
2786                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2787
2788         if (ret)
2789                 goto link_cfg_out;
2790
2791         if (hw->mac.ops.get_link_capabilities)
2792                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2793         if (ret)
2794                 goto link_cfg_out;
2795
2796         if (hw->mac.ops.setup_link)
2797                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2798 link_cfg_out:
2799         return ret;
2800 }
2801
2802 #define IXGBE_MAX_RX_DESC_POLL 10
2803 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2804                                               int rxr)
2805 {
2806         int j = adapter->rx_ring[rxr]->reg_idx;
2807         int k;
2808
2809         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2810                 if (IXGBE_READ_REG(&adapter->hw,
2811                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2812                         break;
2813                 else
2814                         msleep(1);
2815         }
2816         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2817                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2818                         "not set within the polling period\n", rxr);
2819         }
2820         ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
2821                               (adapter->rx_ring[rxr]->count - 1));
2822 }
2823
2824 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2825 {
2826         struct net_device *netdev = adapter->netdev;
2827         struct ixgbe_hw *hw = &adapter->hw;
2828         int i, j = 0;
2829         int num_rx_rings = adapter->num_rx_queues;
2830         int err;
2831         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2832         u32 txdctl, rxdctl, mhadd;
2833         u32 dmatxctl;
2834         u32 gpie;
2835         u32 ctrl_ext;
2836
2837         ixgbe_get_hw_control(adapter);
2838
2839         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2840             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2841                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2842                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2843                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2844                 } else {
2845                         /* MSI only */
2846                         gpie = 0;
2847                 }
2848                 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2849                         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
2850                         gpie |= IXGBE_GPIE_VTMODE_64;
2851                 }
2852                 /* XXX: to interrupt immediately for EICS writes, enable this */
2853                 /* gpie |= IXGBE_GPIE_EIMEN; */
2854                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2855         }
2856
2857         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2858                 /*
2859                  * use EIAM to auto-mask when MSI-X interrupt is asserted
2860                  * this saves a register write for every interrupt
2861                  */
2862                 switch (hw->mac.type) {
2863                 case ixgbe_mac_82598EB:
2864                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2865                         break;
2866                 default:
2867                 case ixgbe_mac_82599EB:
2868                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
2869                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
2870                         break;
2871                 }
2872         } else {
2873                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2874                  * specifically only auto mask tx and rx interrupts */
2875                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2876         }
2877
2878         /* Enable fan failure interrupt if media type is copper */
2879         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2880                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2881                 gpie |= IXGBE_SDP1_GPIEN;
2882                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2883         }
2884
2885         if (hw->mac.type == ixgbe_mac_82599EB) {
2886                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2887                 gpie |= IXGBE_SDP1_GPIEN;
2888                 gpie |= IXGBE_SDP2_GPIEN;
2889                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2890         }
2891
2892 #ifdef IXGBE_FCOE
2893         /* adjust max frame to be able to do baby jumbo for FCoE */
2894         if ((netdev->features & NETIF_F_FCOE_MTU) &&
2895             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2896                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2897
2898 #endif /* IXGBE_FCOE */
2899         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2900         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2901                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2902                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2903
2904                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2905         }
2906
2907         for (i = 0; i < adapter->num_tx_queues; i++) {
2908                 j = adapter->tx_ring[i]->reg_idx;
2909                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2910                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2911                 txdctl |= (8 << 16);
2912                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2913         }
2914
2915         if (hw->mac.type == ixgbe_mac_82599EB) {
2916                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2917                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2918                 dmatxctl |= IXGBE_DMATXCTL_TE;
2919                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2920         }
2921         for (i = 0; i < adapter->num_tx_queues; i++) {
2922                 j = adapter->tx_ring[i]->reg_idx;
2923                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2924                 txdctl |= IXGBE_TXDCTL_ENABLE;
2925                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2926                 if (hw->mac.type == ixgbe_mac_82599EB) {
2927                         int wait_loop = 10;
2928                         /* poll for Tx Enable ready */
2929                         do {
2930                                 msleep(1);
2931                                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2932                         } while (--wait_loop &&
2933                                  !(txdctl & IXGBE_TXDCTL_ENABLE));
2934                         if (!wait_loop)
2935                                 DPRINTK(DRV, ERR, "Could not enable "
2936                                         "Tx Queue %d\n", j);
2937                 }
2938         }
2939
2940         for (i = 0; i < num_rx_rings; i++) {
2941                 j = adapter->rx_ring[i]->reg_idx;
2942                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2943                 /* enable PTHRESH=32 descriptors (half the internal cache)
2944                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2945                  * this also removes a pesky rx_no_buffer_count increment */
2946                 rxdctl |= 0x0020;
2947                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2948                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2949                 if (hw->mac.type == ixgbe_mac_82599EB)
2950                         ixgbe_rx_desc_queue_enable(adapter, i);
2951         }
2952         /* enable all receives */
2953         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2954         if (hw->mac.type == ixgbe_mac_82598EB)
2955                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2956         else
2957                 rxdctl |= IXGBE_RXCTRL_RXEN;
2958         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2959
2960         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2961                 ixgbe_configure_msix(adapter);
2962         else
2963                 ixgbe_configure_msi_and_legacy(adapter);
2964
2965         clear_bit(__IXGBE_DOWN, &adapter->state);
2966         ixgbe_napi_enable_all(adapter);
2967
2968         /* clear any pending interrupts, may auto mask */
2969         IXGBE_READ_REG(hw, IXGBE_EICR);
2970
2971         ixgbe_irq_enable(adapter);
2972
2973         /*
2974          * If this adapter has a fan, check to see if we had a failure
2975          * before we enabled the interrupt.
2976          */
2977         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2978                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2979                 if (esdp & IXGBE_ESDP_SDP1)
2980                         DPRINTK(DRV, CRIT,
2981                                 "Fan has stopped, replace the adapter\n");
2982         }
2983
2984         /*
2985          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2986          * arrived before interrupts were enabled but after probe.  Such
2987          * devices wouldn't have their type identified yet. We need to
2988          * kick off the SFP+ module setup first, then try to bring up link.
2989          * If we're not hot-pluggable SFP+, we just need to configure link
2990          * and bring it up.
2991          */
2992         if (hw->phy.type == ixgbe_phy_unknown) {
2993                 err = hw->phy.ops.identify(hw);
2994                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2995                         /*
2996                          * Take the device down and schedule the sfp tasklet
2997                          * which will unregister_netdev and log it.
2998                          */
2999                         ixgbe_down(adapter);
3000                         schedule_work(&adapter->sfp_config_module_task);
3001                         return err;
3002                 }
3003         }
3004
3005         if (ixgbe_is_sfp(hw)) {
3006                 ixgbe_sfp_link_config(adapter);
3007         } else {
3008                 err = ixgbe_non_sfp_link_config(hw);
3009                 if (err)
3010                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
3011         }
3012
3013         for (i = 0; i < adapter->num_tx_queues; i++)
3014                 set_bit(__IXGBE_FDIR_INIT_DONE,
3015                         &(adapter->tx_ring[i]->reinit_state));
3016
3017         /* enable transmits */
3018         netif_tx_start_all_queues(netdev);
3019
3020         /* bring the link up in the watchdog, this could race with our first
3021          * link up interrupt but shouldn't be a problem */
3022         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3023         adapter->link_check_timeout = jiffies;
3024         mod_timer(&adapter->watchdog_timer, jiffies);
3025
3026         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3027         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3028         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3029         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3030
3031         return 0;
3032 }
3033
3034 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3035 {
3036         WARN_ON(in_interrupt());
3037         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3038                 msleep(1);
3039         ixgbe_down(adapter);
3040         /*
3041          * If SR-IOV enabled then wait a bit before bringing the adapter
3042          * back up to give the VFs time to respond to the reset.  The
3043          * two second wait is based upon the watchdog timer cycle in
3044          * the VF driver.
3045          */
3046         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3047                 msleep(2000);
3048         ixgbe_up(adapter);
3049         clear_bit(__IXGBE_RESETTING, &adapter->state);
3050 }
3051
3052 int ixgbe_up(struct ixgbe_adapter *adapter)
3053 {
3054         /* hardware has been reset, we need to reload some things */
3055         ixgbe_configure(adapter);
3056
3057         return ixgbe_up_complete(adapter);
3058 }
3059
3060 void ixgbe_reset(struct ixgbe_adapter *adapter)
3061 {
3062         struct ixgbe_hw *hw = &adapter->hw;
3063         int err;
3064
3065         err = hw->mac.ops.init_hw(hw);
3066         switch (err) {
3067         case 0:
3068         case IXGBE_ERR_SFP_NOT_PRESENT:
3069                 break;
3070         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3071                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
3072                 break;
3073         case IXGBE_ERR_EEPROM_VERSION:
3074                 /* We are running on a pre-production device, log a warning */
3075                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
3076                          "adapter/LOM.  Please be aware there may be issues "
3077                          "associated with your hardware.  If you are "
3078                          "experiencing problems please contact your Intel or "
3079                          "hardware representative who provided you with this "
3080                          "hardware.\n");
3081                 break;
3082         default:
3083                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
3084         }
3085
3086         /* reprogram the RAR[0] in case user changed it. */
3087         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3088                             IXGBE_RAH_AV);
3089 }
3090
3091 /**
3092  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3093  * @adapter: board private structure
3094  * @rx_ring: ring to free buffers from
3095  **/
3096 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3097                                 struct ixgbe_ring *rx_ring)
3098 {
3099         struct pci_dev *pdev = adapter->pdev;
3100         unsigned long size;
3101         unsigned int i;
3102
3103         /* Free all the Rx ring sk_buffs */
3104
3105         for (i = 0; i < rx_ring->count; i++) {
3106                 struct ixgbe_rx_buffer *rx_buffer_info;
3107
3108                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3109                 if (rx_buffer_info->dma) {
3110                         pci_unmap_single(pdev, rx_buffer_info->dma,
3111                                          rx_ring->rx_buf_len,
3112                                          PCI_DMA_FROMDEVICE);
3113                         rx_buffer_info->dma = 0;
3114                 }
3115                 if (rx_buffer_info->skb) {
3116                         struct sk_buff *skb = rx_buffer_info->skb;
3117                         rx_buffer_info->skb = NULL;
3118                         do {
3119                                 struct sk_buff *this = skb;
3120                                 if (IXGBE_RSC_CB(this)->dma) {
3121                                         pci_unmap_single(pdev, IXGBE_RSC_CB(this)->dma,
3122                                                          rx_ring->rx_buf_len,
3123                                                          PCI_DMA_FROMDEVICE);
3124                                         IXGBE_RSC_CB(this)->dma = 0;
3125                                 }
3126                                 skb = skb->prev;
3127                                 dev_kfree_skb(this);
3128                         } while (skb);
3129                 }
3130                 if (!rx_buffer_info->page)
3131                         continue;
3132                 if (rx_buffer_info->page_dma) {
3133                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
3134                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
3135                         rx_buffer_info->page_dma = 0;
3136                 }
3137                 put_page(rx_buffer_info->page);
3138                 rx_buffer_info->page = NULL;
3139                 rx_buffer_info->page_offset = 0;
3140         }
3141
3142         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3143         memset(rx_ring->rx_buffer_info, 0, size);
3144
3145         /* Zero out the descriptor ring */
3146         memset(rx_ring->desc, 0, rx_ring->size);
3147
3148         rx_ring->next_to_clean = 0;
3149         rx_ring->next_to_use = 0;
3150
3151         if (rx_ring->head)
3152                 writel(0, adapter->hw.hw_addr + rx_ring->head);
3153         if (rx_ring->tail)
3154                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3155 }
3156
3157 /**
3158  * ixgbe_clean_tx_ring - Free Tx Buffers
3159  * @adapter: board private structure
3160  * @tx_ring: ring to be cleaned
3161  **/
3162 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3163                                 struct ixgbe_ring *tx_ring)
3164 {
3165         struct ixgbe_tx_buffer *tx_buffer_info;
3166         unsigned long size;
3167         unsigned int i;
3168
3169         /* Free all the Tx ring sk_buffs */
3170
3171         for (i = 0; i < tx_ring->count; i++) {
3172                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3173                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3174         }
3175
3176         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3177         memset(tx_ring->tx_buffer_info, 0, size);
3178
3179         /* Zero out the descriptor ring */
3180         memset(tx_ring->desc, 0, tx_ring->size);
3181
3182         tx_ring->next_to_use = 0;
3183         tx_ring->next_to_clean = 0;
3184
3185         if (tx_ring->head)
3186                 writel(0, adapter->hw.hw_addr + tx_ring->head);
3187         if (tx_ring->tail)
3188                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3189 }
3190
3191 /**
3192  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3193  * @adapter: board private structure
3194  **/
3195 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3196 {
3197         int i;
3198
3199         for (i = 0; i < adapter->num_rx_queues; i++)
3200                 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
3201 }
3202
3203 /**
3204  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3205  * @adapter: board private structure
3206  **/
3207 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3208 {
3209         int i;
3210
3211         for (i = 0; i < adapter->num_tx_queues; i++)
3212                 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
3213 }
3214
3215 void ixgbe_down(struct ixgbe_adapter *adapter)
3216 {
3217         struct net_device *netdev = adapter->netdev;
3218         struct ixgbe_hw *hw = &adapter->hw;
3219         u32 rxctrl;
3220         u32 txdctl;
3221         int i, j;
3222
3223         /* signal that we are down to the interrupt handler */
3224         set_bit(__IXGBE_DOWN, &adapter->state);
3225
3226         /* disable receive for all VFs and wait one second */
3227         if (adapter->num_vfs) {
3228                 /* ping all the active vfs to let them know we are going down */
3229                 ixgbe_ping_all_vfs(adapter);
3230
3231                 /* Disable all VFTE/VFRE TX/RX */
3232                 ixgbe_disable_tx_rx(adapter);
3233
3234                 /* Mark all the VFs as inactive */
3235                 for (i = 0 ; i < adapter->num_vfs; i++)
3236                         adapter->vfinfo[i].clear_to_send = 0;
3237         }
3238
3239         /* disable receives */
3240         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3241         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3242
3243         netif_tx_disable(netdev);
3244
3245         IXGBE_WRITE_FLUSH(hw);
3246         msleep(10);
3247
3248         netif_tx_stop_all_queues(netdev);
3249
3250         ixgbe_irq_disable(adapter);
3251
3252         ixgbe_napi_disable_all(adapter);
3253
3254         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3255         del_timer_sync(&adapter->sfp_timer);
3256         del_timer_sync(&adapter->watchdog_timer);
3257         cancel_work_sync(&adapter->watchdog_task);
3258
3259         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3260             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3261                 cancel_work_sync(&adapter->fdir_reinit_task);
3262
3263         /* disable transmits in the hardware now that interrupts are off */
3264         for (i = 0; i < adapter->num_tx_queues; i++) {
3265                 j = adapter->tx_ring[i]->reg_idx;
3266                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3267                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3268                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3269         }
3270         /* Disable the Tx DMA engine on 82599 */
3271         if (hw->mac.type == ixgbe_mac_82599EB)
3272                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3273                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3274                                  ~IXGBE_DMATXCTL_TE));
3275
3276         netif_carrier_off(netdev);
3277
3278         /* clear n-tuple filters that are cached */
3279         ethtool_ntuple_flush(netdev);
3280
3281         if (!pci_channel_offline(adapter->pdev))
3282                 ixgbe_reset(adapter);
3283         ixgbe_clean_all_tx_rings(adapter);
3284         ixgbe_clean_all_rx_rings(adapter);
3285
3286 #ifdef CONFIG_IXGBE_DCA
3287         /* since we reset the hardware DCA settings were cleared */
3288         ixgbe_setup_dca(adapter);
3289 #endif
3290 }
3291
3292 /**
3293  * ixgbe_poll - NAPI Rx polling callback
3294  * @napi: structure for representing this polling device
3295  * @budget: how many packets driver is allowed to clean
3296  *
3297  * This function is used for legacy and MSI, NAPI mode
3298  **/
3299 static int ixgbe_poll(struct napi_struct *napi, int budget)
3300 {
3301         struct ixgbe_q_vector *q_vector =
3302                                 container_of(napi, struct ixgbe_q_vector, napi);
3303         struct ixgbe_adapter *adapter = q_vector->adapter;
3304         int tx_clean_complete, work_done = 0;
3305
3306 #ifdef CONFIG_IXGBE_DCA
3307         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3308                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3309                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3310         }
3311 #endif
3312
3313         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3314         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3315
3316         if (!tx_clean_complete)
3317                 work_done = budget;
3318
3319         /* If budget not fully consumed, exit the polling mode */
3320         if (work_done < budget) {
3321                 napi_complete(napi);
3322                 if (adapter->rx_itr_setting & 1)
3323                         ixgbe_set_itr(adapter);
3324                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3325                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3326         }
3327         return work_done;
3328 }
3329
3330 /**
3331  * ixgbe_tx_timeout - Respond to a Tx Hang
3332  * @netdev: network interface device structure
3333  **/
3334 static void ixgbe_tx_timeout(struct net_device *netdev)
3335 {
3336         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3337
3338         /* Do the reset outside of interrupt context */
3339         schedule_work(&adapter->reset_task);
3340 }
3341
3342 static void ixgbe_reset_task(struct work_struct *work)
3343 {
3344         struct ixgbe_adapter *adapter;
3345         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3346
3347         /* If we're already down or resetting, just bail */
3348         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3349             test_bit(__IXGBE_RESETTING, &adapter->state))
3350                 return;
3351
3352         adapter->tx_timeout_count++;
3353
3354         ixgbe_reinit_locked(adapter);
3355 }
3356
3357 #ifdef CONFIG_IXGBE_DCB
3358 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3359 {
3360         bool ret = false;
3361         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3362
3363         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3364                 return ret;
3365
3366         f->mask = 0x7 << 3;
3367         adapter->num_rx_queues = f->indices;
3368         adapter->num_tx_queues = f->indices;
3369         ret = true;
3370
3371         return ret;
3372 }
3373 #endif
3374
3375 /**
3376  * ixgbe_set_rss_queues: Allocate queues for RSS
3377  * @adapter: board private structure to initialize
3378  *
3379  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3380  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3381  *
3382  **/
3383 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3384 {
3385         bool ret = false;
3386         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3387
3388         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3389                 f->mask = 0xF;
3390                 adapter->num_rx_queues = f->indices;
3391                 adapter->num_tx_queues = f->indices;
3392                 ret = true;
3393         } else {
3394                 ret = false;
3395         }
3396
3397         return ret;
3398 }
3399
3400 /**
3401  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3402  * @adapter: board private structure to initialize
3403  *
3404  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3405  * to the original CPU that initiated the Tx session.  This runs in addition
3406  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3407  * Rx load across CPUs using RSS.
3408  *
3409  **/
3410 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3411 {
3412         bool ret = false;
3413         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3414
3415         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3416         f_fdir->mask = 0;
3417
3418         /* Flow Director must have RSS enabled */
3419         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3420             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3421              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3422                 adapter->num_tx_queues = f_fdir->indices;
3423                 adapter->num_rx_queues = f_fdir->indices;
3424                 ret = true;
3425         } else {
3426                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3427                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3428         }
3429         return ret;
3430 }
3431
3432 #ifdef IXGBE_FCOE
3433 /**
3434  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3435  * @adapter: board private structure to initialize
3436  *
3437  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3438  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3439  * rx queues out of the max number of rx queues, instead, it is used as the
3440  * index of the first rx queue used by FCoE.
3441  *
3442  **/
3443 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3444 {
3445         bool ret = false;
3446         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3447
3448         f->indices = min((int)num_online_cpus(), f->indices);
3449         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3450                 adapter->num_rx_queues = 1;
3451                 adapter->num_tx_queues = 1;
3452 #ifdef CONFIG_IXGBE_DCB
3453                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3454                         DPRINTK(PROBE, INFO, "FCoE enabled with DCB\n");
3455                         ixgbe_set_dcb_queues(adapter);
3456                 }
3457 #endif
3458                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3459                         DPRINTK(PROBE, INFO, "FCoE enabled with RSS\n");
3460                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3461                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3462                                 ixgbe_set_fdir_queues(adapter);
3463                         else
3464                                 ixgbe_set_rss_queues(adapter);
3465                 }
3466                 /* adding FCoE rx rings to the end */
3467                 f->mask = adapter->num_rx_queues;
3468                 adapter->num_rx_queues += f->indices;
3469                 adapter->num_tx_queues += f->indices;
3470
3471                 ret = true;
3472         }
3473
3474         return ret;
3475 }
3476
3477 #endif /* IXGBE_FCOE */
3478 /**
3479  * ixgbe_set_sriov_queues: Allocate queues for IOV use
3480  * @adapter: board private structure to initialize
3481  *
3482  * IOV doesn't actually use anything, so just NAK the
3483  * request for now and let the other queue routines
3484  * figure out what to do.
3485  */
3486 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
3487 {
3488         return false;
3489 }
3490
3491 /*
3492  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3493  * @adapter: board private structure to initialize
3494  *
3495  * This is the top level queue allocation routine.  The order here is very
3496  * important, starting with the "most" number of features turned on at once,
3497  * and ending with the smallest set of features.  This way large combinations
3498  * can be allocated if they're turned on, and smaller combinations are the
3499  * fallthrough conditions.
3500  *
3501  **/
3502 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3503 {
3504         /* Start with base case */
3505         adapter->num_rx_queues = 1;
3506         adapter->num_tx_queues = 1;
3507         adapter->num_rx_pools = adapter->num_rx_queues;
3508         adapter->num_rx_queues_per_pool = 1;
3509
3510         if (ixgbe_set_sriov_queues(adapter))
3511                 return;
3512
3513 #ifdef IXGBE_FCOE
3514         if (ixgbe_set_fcoe_queues(adapter))
3515                 goto done;
3516
3517 #endif /* IXGBE_FCOE */
3518 #ifdef CONFIG_IXGBE_DCB
3519         if (ixgbe_set_dcb_queues(adapter))
3520                 goto done;
3521
3522 #endif
3523         if (ixgbe_set_fdir_queues(adapter))
3524                 goto done;
3525
3526         if (ixgbe_set_rss_queues(adapter))
3527                 goto done;
3528
3529         /* fallback to base case */
3530         adapter->num_rx_queues = 1;
3531         adapter->num_tx_queues = 1;
3532
3533 done:
3534         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3535         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3536 }
3537
3538 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3539                                        int vectors)
3540 {
3541         int err, vector_threshold;
3542
3543         /* We'll want at least 3 (vector_threshold):
3544          * 1) TxQ[0] Cleanup
3545          * 2) RxQ[0] Cleanup
3546          * 3) Other (Link Status Change, etc.)
3547          * 4) TCP Timer (optional)
3548          */
3549         vector_threshold = MIN_MSIX_COUNT;
3550
3551         /* The more we get, the more we will assign to Tx/Rx Cleanup
3552          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3553          * Right now, we simply care about how many we'll get; we'll
3554          * set them up later while requesting irq's.
3555          */
3556         while (vectors >= vector_threshold) {
3557                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3558                                       vectors);
3559                 if (!err) /* Success in acquiring all requested vectors. */
3560                         break;
3561                 else if (err < 0)
3562                         vectors = 0; /* Nasty failure, quit now */
3563                 else /* err == number of vectors we should try again with */
3564                         vectors = err;
3565         }
3566
3567         if (vectors < vector_threshold) {
3568                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3569                  * This just means we'll go with either a single MSI
3570                  * vector or fall back to legacy interrupts.
3571                  */
3572                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3573                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3574                 kfree(adapter->msix_entries);
3575                 adapter->msix_entries = NULL;
3576         } else {
3577                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3578                 /*
3579                  * Adjust for only the vectors we'll use, which is minimum
3580                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3581                  * vectors we were allocated.
3582                  */
3583                 adapter->num_msix_vectors = min(vectors,
3584                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3585         }
3586 }
3587
3588 /**
3589  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3590  * @adapter: board private structure to initialize
3591  *
3592  * Cache the descriptor ring offsets for RSS to the assigned rings.
3593  *
3594  **/
3595 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3596 {
3597         int i;
3598         bool ret = false;
3599
3600         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3601                 for (i = 0; i < adapter->num_rx_queues; i++)
3602                         adapter->rx_ring[i]->reg_idx = i;
3603                 for (i = 0; i < adapter->num_tx_queues; i++)
3604                         adapter->tx_ring[i]->reg_idx = i;
3605                 ret = true;
3606         } else {
3607                 ret = false;
3608         }
3609
3610         return ret;
3611 }
3612
3613 #ifdef CONFIG_IXGBE_DCB
3614 /**
3615  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3616  * @adapter: board private structure to initialize
3617  *
3618  * Cache the descriptor ring offsets for DCB to the assigned rings.
3619  *
3620  **/
3621 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3622 {
3623         int i;
3624         bool ret = false;
3625         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3626
3627         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3628                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3629                         /* the number of queues is assumed to be symmetric */
3630                         for (i = 0; i < dcb_i; i++) {
3631                                 adapter->rx_ring[i]->reg_idx = i << 3;
3632                                 adapter->tx_ring[i]->reg_idx = i << 2;
3633                         }
3634                         ret = true;
3635                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3636                         if (dcb_i == 8) {
3637                                 /*
3638                                  * Tx TC0 starts at: descriptor queue 0
3639                                  * Tx TC1 starts at: descriptor queue 32
3640                                  * Tx TC2 starts at: descriptor queue 64
3641                                  * Tx TC3 starts at: descriptor queue 80
3642                                  * Tx TC4 starts at: descriptor queue 96
3643                                  * Tx TC5 starts at: descriptor queue 104
3644                                  * Tx TC6 starts at: descriptor queue 112
3645                                  * Tx TC7 starts at: descriptor queue 120
3646                                  *
3647                                  * Rx TC0-TC7 are offset by 16 queues each
3648                                  */
3649                                 for (i = 0; i < 3; i++) {
3650                                         adapter->tx_ring[i]->reg_idx = i << 5;
3651                                         adapter->rx_ring[i]->reg_idx = i << 4;
3652                                 }
3653                                 for ( ; i < 5; i++) {
3654                                         adapter->tx_ring[i]->reg_idx =
3655                                                                  ((i + 2) << 4);
3656                                         adapter->rx_ring[i]->reg_idx = i << 4;
3657                                 }
3658                                 for ( ; i < dcb_i; i++) {
3659                                         adapter->tx_ring[i]->reg_idx =
3660                                                                  ((i + 8) << 3);
3661                                         adapter->rx_ring[i]->reg_idx = i << 4;
3662                                 }
3663
3664                                 ret = true;
3665                         } else if (dcb_i == 4) {
3666                                 /*
3667                                  * Tx TC0 starts at: descriptor queue 0
3668                                  * Tx TC1 starts at: descriptor queue 64
3669                                  * Tx TC2 starts at: descriptor queue 96
3670                                  * Tx TC3 starts at: descriptor queue 112
3671                                  *
3672                                  * Rx TC0-TC3 are offset by 32 queues each
3673                                  */
3674                                 adapter->tx_ring[0]->reg_idx = 0;
3675                                 adapter->tx_ring[1]->reg_idx = 64;
3676                                 adapter->tx_ring[2]->reg_idx = 96;
3677                                 adapter->tx_ring[3]->reg_idx = 112;
3678                                 for (i = 0 ; i < dcb_i; i++)
3679                                         adapter->rx_ring[i]->reg_idx = i << 5;
3680
3681                                 ret = true;
3682                         } else {
3683                                 ret = false;
3684                         }
3685                 } else {
3686                         ret = false;
3687                 }
3688         } else {
3689                 ret = false;
3690         }
3691
3692         return ret;
3693 }
3694 #endif
3695
3696 /**
3697  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3698  * @adapter: board private structure to initialize
3699  *
3700  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3701  *
3702  **/
3703 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3704 {
3705         int i;
3706         bool ret = false;
3707
3708         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3709             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3710              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3711                 for (i = 0; i < adapter->num_rx_queues; i++)
3712                         adapter->rx_ring[i]->reg_idx = i;
3713                 for (i = 0; i < adapter->num_tx_queues; i++)
3714                         adapter->tx_ring[i]->reg_idx = i;
3715                 ret = true;
3716         }
3717
3718         return ret;
3719 }
3720
3721 #ifdef IXGBE_FCOE
3722 /**
3723  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3724  * @adapter: board private structure to initialize
3725  *
3726  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3727  *
3728  */
3729 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3730 {
3731         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
3732         bool ret = false;
3733         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3734
3735         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3736 #ifdef CONFIG_IXGBE_DCB
3737                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3738                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3739
3740                         ixgbe_cache_ring_dcb(adapter);
3741                         /* find out queues in TC for FCoE */
3742                         fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
3743                         fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
3744                         /*
3745                          * In 82599, the number of Tx queues for each traffic
3746                          * class for both 8-TC and 4-TC modes are:
3747                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3748                          * 8 TCs:  32  32  16  16   8   8   8   8
3749                          * 4 TCs:  64  64  32  32
3750                          * We have max 8 queues for FCoE, where 8 the is
3751                          * FCoE redirection table size. If TC for FCoE is
3752                          * less than or equal to TC3, we have enough queues
3753                          * to add max of 8 queues for FCoE, so we start FCoE
3754                          * tx descriptor from the next one, i.e., reg_idx + 1.
3755                          * If TC for FCoE is above TC3, implying 8 TC mode,
3756                          * and we need 8 for FCoE, we have to take all queues
3757                          * in that traffic class for FCoE.
3758                          */
3759                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3760                                 fcoe_tx_i--;
3761                 }
3762 #endif /* CONFIG_IXGBE_DCB */
3763                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3764                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3765                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3766                                 ixgbe_cache_ring_fdir(adapter);
3767                         else
3768                                 ixgbe_cache_ring_rss(adapter);
3769
3770                         fcoe_rx_i = f->mask;
3771                         fcoe_tx_i = f->mask;
3772                 }
3773                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3774                         adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
3775                         adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
3776                 }
3777                 ret = true;
3778         }
3779         return ret;
3780 }
3781
3782 #endif /* IXGBE_FCOE */
3783 /**
3784  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
3785  * @adapter: board private structure to initialize
3786  *
3787  * SR-IOV doesn't use any descriptor rings but changes the default if
3788  * no other mapping is used.
3789  *
3790  */
3791 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
3792 {
3793         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
3794         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
3795         if (adapter->num_vfs)
3796                 return true;
3797         else
3798                 return false;
3799 }
3800
3801 /**
3802  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3803  * @adapter: board private structure to initialize
3804  *
3805  * Once we know the feature-set enabled for the device, we'll cache
3806  * the register offset the descriptor ring is assigned to.
3807  *
3808  * Note, the order the various feature calls is important.  It must start with
3809  * the "most" features enabled at the same time, then trickle down to the
3810  * least amount of features turned on at once.
3811  **/
3812 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3813 {
3814         /* start with default case */
3815         adapter->rx_ring[0]->reg_idx = 0;
3816         adapter->tx_ring[0]->reg_idx = 0;
3817
3818         if (ixgbe_cache_ring_sriov(adapter))
3819                 return;
3820
3821 #ifdef IXGBE_FCOE
3822         if (ixgbe_cache_ring_fcoe(adapter))
3823                 return;
3824
3825 #endif /* IXGBE_FCOE */
3826 #ifdef CONFIG_IXGBE_DCB
3827         if (ixgbe_cache_ring_dcb(adapter))
3828                 return;
3829
3830 #endif
3831         if (ixgbe_cache_ring_fdir(adapter))
3832                 return;
3833
3834         if (ixgbe_cache_ring_rss(adapter))
3835                 return;
3836 }
3837
3838 /**
3839  * ixgbe_alloc_queues - Allocate memory for all rings
3840  * @adapter: board private structure to initialize
3841  *
3842  * We allocate one ring per queue at run-time since we don't know the
3843  * number of queues at compile-time.  The polling_netdev array is
3844  * intended for Multiqueue, but should work fine with a single queue.
3845  **/
3846 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3847 {
3848         int i;
3849         int orig_node = adapter->node;
3850
3851         for (i = 0; i < adapter->num_tx_queues; i++) {
3852                 struct ixgbe_ring *ring = adapter->tx_ring[i];
3853                 if (orig_node == -1) {
3854                         int cur_node = next_online_node(adapter->node);
3855                         if (cur_node == MAX_NUMNODES)
3856                                 cur_node = first_online_node;
3857                         adapter->node = cur_node;
3858                 }
3859                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3860                                     adapter->node);
3861                 if (!ring)
3862                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3863                 if (!ring)
3864                         goto err_tx_ring_allocation;
3865                 ring->count = adapter->tx_ring_count;
3866                 ring->queue_index = i;
3867                 ring->numa_node = adapter->node;
3868
3869                 adapter->tx_ring[i] = ring;
3870         }
3871
3872         /* Restore the adapter's original node */
3873         adapter->node = orig_node;
3874
3875         for (i = 0; i < adapter->num_rx_queues; i++) {
3876                 struct ixgbe_ring *ring = adapter->rx_ring[i];
3877                 if (orig_node == -1) {
3878                         int cur_node = next_online_node(adapter->node);
3879                         if (cur_node == MAX_NUMNODES)
3880                                 cur_node = first_online_node;
3881                         adapter->node = cur_node;
3882                 }
3883                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3884                                     adapter->node);
3885                 if (!ring)
3886                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3887                 if (!ring)
3888                         goto err_rx_ring_allocation;
3889                 ring->count = adapter->rx_ring_count;
3890                 ring->queue_index = i;
3891                 ring->numa_node = adapter->node;
3892
3893                 adapter->rx_ring[i] = ring;
3894         }
3895
3896         /* Restore the adapter's original node */
3897         adapter->node = orig_node;
3898
3899         ixgbe_cache_ring_register(adapter);
3900
3901         return 0;
3902
3903 err_rx_ring_allocation:
3904         for (i = 0; i < adapter->num_tx_queues; i++)
3905                 kfree(adapter->tx_ring[i]);
3906 err_tx_ring_allocation:
3907         return -ENOMEM;
3908 }
3909
3910 /**
3911  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3912  * @adapter: board private structure to initialize
3913  *
3914  * Attempt to configure the interrupts using the best available
3915  * capabilities of the hardware and the kernel.
3916  **/
3917 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3918 {
3919         struct ixgbe_hw *hw = &adapter->hw;
3920         int err = 0;
3921         int vector, v_budget;
3922
3923         /*
3924          * It's easy to be greedy for MSI-X vectors, but it really
3925          * doesn't do us much good if we have a lot more vectors
3926          * than CPU's.  So let's be conservative and only ask for
3927          * (roughly) the same number of vectors as there are CPU's.
3928          */
3929         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3930                        (int)num_online_cpus()) + NON_Q_VECTORS;
3931
3932         /*
3933          * At the same time, hardware can only support a maximum of
3934          * hw.mac->max_msix_vectors vectors.  With features
3935          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3936          * descriptor queues supported by our device.  Thus, we cap it off in
3937          * those rare cases where the cpu count also exceeds our vector limit.
3938          */
3939         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3940
3941         /* A failure in MSI-X entry allocation isn't fatal, but it does
3942          * mean we disable MSI-X capabilities of the adapter. */
3943         adapter->msix_entries = kcalloc(v_budget,
3944                                         sizeof(struct msix_entry), GFP_KERNEL);
3945         if (adapter->msix_entries) {
3946                 for (vector = 0; vector < v_budget; vector++)
3947                         adapter->msix_entries[vector].entry = vector;
3948
3949                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3950
3951                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3952                         goto out;
3953         }
3954
3955         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3956         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3957         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3958         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3959         adapter->atr_sample_rate = 0;
3960         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3961                 ixgbe_disable_sriov(adapter);
3962
3963         ixgbe_set_num_queues(adapter);
3964
3965         err = pci_enable_msi(adapter->pdev);
3966         if (!err) {
3967                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3968         } else {
3969                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3970                         "falling back to legacy.  Error: %d\n", err);
3971                 /* reset err */
3972                 err = 0;
3973         }
3974
3975 out:
3976         return err;
3977 }
3978
3979 /**
3980  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3981  * @adapter: board private structure to initialize
3982  *
3983  * We allocate one q_vector per queue interrupt.  If allocation fails we
3984  * return -ENOMEM.
3985  **/
3986 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3987 {
3988         int q_idx, num_q_vectors;
3989         struct ixgbe_q_vector *q_vector;
3990         int napi_vectors;
3991         int (*poll)(struct napi_struct *, int);
3992
3993         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3994                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3995                 napi_vectors = adapter->num_rx_queues;
3996                 poll = &ixgbe_clean_rxtx_many;
3997         } else {
3998                 num_q_vectors = 1;
3999                 napi_vectors = 1;
4000                 poll = &ixgbe_poll;
4001         }
4002
4003         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4004                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4005                                         GFP_KERNEL, adapter->node);
4006                 if (!q_vector)
4007                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4008                                            GFP_KERNEL);
4009                 if (!q_vector)
4010                         goto err_out;
4011                 q_vector->adapter = adapter;
4012                 if (q_vector->txr_count && !q_vector->rxr_count)
4013                         q_vector->eitr = adapter->tx_eitr_param;
4014                 else
4015                         q_vector->eitr = adapter->rx_eitr_param;
4016                 q_vector->v_idx = q_idx;
4017                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4018                 adapter->q_vector[q_idx] = q_vector;
4019         }
4020
4021         return 0;
4022
4023 err_out:
4024         while (q_idx) {
4025                 q_idx--;
4026                 q_vector = adapter->q_vector[q_idx];
4027                 netif_napi_del(&q_vector->napi);
4028                 kfree(q_vector);
4029                 adapter->q_vector[q_idx] = NULL;
4030         }
4031         return -ENOMEM;
4032 }
4033
4034 /**
4035  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4036  * @adapter: board private structure to initialize
4037  *
4038  * This function frees the memory allocated to the q_vectors.  In addition if
4039  * NAPI is enabled it will delete any references to the NAPI struct prior
4040  * to freeing the q_vector.
4041  **/
4042 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4043 {
4044         int q_idx, num_q_vectors;
4045
4046         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4047                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4048         else
4049                 num_q_vectors = 1;
4050
4051         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4052                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4053                 adapter->q_vector[q_idx] = NULL;
4054                 netif_napi_del(&q_vector->napi);
4055                 kfree(q_vector);
4056         }
4057 }
4058
4059 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4060 {
4061         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4062                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4063                 pci_disable_msix(adapter->pdev);
4064                 kfree(adapter->msix_entries);
4065                 adapter->msix_entries = NULL;
4066         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4067                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4068                 pci_disable_msi(adapter->pdev);
4069         }
4070         return;
4071 }
4072
4073 /**
4074  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4075  * @adapter: board private structure to initialize
4076  *
4077  * We determine which interrupt scheme to use based on...
4078  * - Kernel support (MSI, MSI-X)
4079  *   - which can be user-defined (via MODULE_PARAM)
4080  * - Hardware queue count (num_*_queues)
4081  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4082  **/
4083 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4084 {
4085         int err;
4086
4087         /* Number of supported queues */
4088         ixgbe_set_num_queues(adapter);
4089
4090         err = ixgbe_set_interrupt_capability(adapter);
4091         if (err) {
4092                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
4093                 goto err_set_interrupt;
4094         }
4095
4096         err = ixgbe_alloc_q_vectors(adapter);
4097         if (err) {
4098                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
4099                         "vectors\n");
4100                 goto err_alloc_q_vectors;
4101         }
4102
4103         err = ixgbe_alloc_queues(adapter);
4104         if (err) {
4105                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
4106                 goto err_alloc_queues;
4107         }
4108
4109         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
4110                 "Tx Queue count = %u\n",
4111                 (adapter->num_rx_queues > 1) ? "Enabled" :
4112                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
4113
4114         set_bit(__IXGBE_DOWN, &adapter->state);
4115
4116         return 0;
4117
4118 err_alloc_queues:
4119         ixgbe_free_q_vectors(adapter);
4120 err_alloc_q_vectors:
4121         ixgbe_reset_interrupt_capability(adapter);
4122 err_set_interrupt:
4123         return err;
4124 }
4125
4126 /**
4127  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4128  * @adapter: board private structure to clear interrupt scheme on
4129  *
4130  * We go through and clear interrupt specific resources and reset the structure
4131  * to pre-load conditions
4132  **/
4133 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4134 {
4135         int i;
4136
4137         for (i = 0; i < adapter->num_tx_queues; i++) {
4138                 kfree(adapter->tx_ring[i]);
4139                 adapter->tx_ring[i] = NULL;
4140         }
4141         for (i = 0; i < adapter->num_rx_queues; i++) {
4142                 kfree(adapter->rx_ring[i]);
4143                 adapter->rx_ring[i] = NULL;
4144         }
4145
4146         ixgbe_free_q_vectors(adapter);
4147         ixgbe_reset_interrupt_capability(adapter);
4148 }
4149
4150 /**
4151  * ixgbe_sfp_timer - worker thread to find a missing module
4152  * @data: pointer to our adapter struct
4153  **/
4154 static void ixgbe_sfp_timer(unsigned long data)
4155 {
4156         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4157
4158         /*
4159          * Do the sfp_timer outside of interrupt context due to the
4160          * delays that sfp+ detection requires
4161          */
4162         schedule_work(&adapter->sfp_task);
4163 }
4164
4165 /**
4166  * ixgbe_sfp_task - worker thread to find a missing module
4167  * @work: pointer to work_struct containing our data
4168  **/
4169 static void ixgbe_sfp_task(struct work_struct *work)
4170 {
4171         struct ixgbe_adapter *adapter = container_of(work,
4172                                                      struct ixgbe_adapter,
4173                                                      sfp_task);
4174         struct ixgbe_hw *hw = &adapter->hw;
4175
4176         if ((hw->phy.type == ixgbe_phy_nl) &&
4177             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4178                 s32 ret = hw->phy.ops.identify_sfp(hw);
4179                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4180                         goto reschedule;
4181                 ret = hw->phy.ops.reset(hw);
4182                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4183                         dev_err(&adapter->pdev->dev, "failed to initialize "
4184                                 "because an unsupported SFP+ module type "
4185                                 "was detected.\n"
4186                                 "Reload the driver after installing a "
4187                                 "supported module.\n");
4188                         unregister_netdev(adapter->netdev);
4189                 } else {
4190                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
4191                                 hw->phy.sfp_type);
4192                 }
4193                 /* don't need this routine any more */
4194                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4195         }
4196         return;
4197 reschedule:
4198         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4199                 mod_timer(&adapter->sfp_timer,
4200                           round_jiffies(jiffies + (2 * HZ)));
4201 }
4202
4203 /**
4204  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4205  * @adapter: board private structure to initialize
4206  *
4207  * ixgbe_sw_init initializes the Adapter private data structure.
4208  * Fields are initialized based on PCI device information and
4209  * OS network device settings (MTU size).
4210  **/
4211 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4212 {
4213         struct ixgbe_hw *hw = &adapter->hw;
4214         struct pci_dev *pdev = adapter->pdev;
4215         struct net_device *dev = adapter->netdev;
4216         unsigned int rss;
4217 #ifdef CONFIG_IXGBE_DCB
4218         int j;
4219         struct tc_configuration *tc;
4220 #endif
4221
4222         /* PCI config space info */
4223
4224         hw->vendor_id = pdev->vendor;
4225         hw->device_id = pdev->device;
4226         hw->revision_id = pdev->revision;
4227         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4228         hw->subsystem_device_id = pdev->subsystem_device;
4229
4230         /* Set capability flags */
4231         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4232         adapter->ring_feature[RING_F_RSS].indices = rss;
4233         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4234         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4235         if (hw->mac.type == ixgbe_mac_82598EB) {
4236                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4237                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4238                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4239         } else if (hw->mac.type == ixgbe_mac_82599EB) {
4240                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4241                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4242                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4243                 if (dev->features & NETIF_F_NTUPLE) {
4244                         /* Flow Director perfect filter enabled */
4245                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4246                         adapter->atr_sample_rate = 0;
4247                         spin_lock_init(&adapter->fdir_perfect_lock);
4248                 } else {
4249                         /* Flow Director hash filters enabled */
4250                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4251                         adapter->atr_sample_rate = 20;
4252                 }
4253                 adapter->ring_feature[RING_F_FDIR].indices =
4254                                                          IXGBE_MAX_FDIR_INDICES;
4255                 adapter->fdir_pballoc = 0;
4256 #ifdef IXGBE_FCOE
4257                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4258                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4259                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4260 #ifdef CONFIG_IXGBE_DCB
4261                 /* Default traffic class to use for FCoE */
4262                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4263 #endif
4264 #endif /* IXGBE_FCOE */
4265         }
4266
4267 #ifdef CONFIG_IXGBE_DCB
4268         /* Configure DCB traffic classes */
4269         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4270                 tc = &adapter->dcb_cfg.tc_config[j];
4271                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4272                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4273                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4274                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4275                 tc->dcb_pfc = pfc_disabled;
4276         }
4277         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4278         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4279         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4280         adapter->dcb_cfg.pfc_mode_enable = false;
4281         adapter->dcb_cfg.round_robin_enable = false;
4282         adapter->dcb_set_bitmap = 0x00;
4283         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4284                            adapter->ring_feature[RING_F_DCB].indices);
4285
4286 #endif
4287
4288         /* default flow control settings */
4289         hw->fc.requested_mode = ixgbe_fc_full;
4290         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4291 #ifdef CONFIG_DCB
4292         adapter->last_lfc_mode = hw->fc.current_mode;
4293 #endif
4294         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4295         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4296         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4297         hw->fc.send_xon = true;
4298         hw->fc.disable_fc_autoneg = false;
4299
4300         /* enable itr by default in dynamic mode */
4301         adapter->rx_itr_setting = 1;
4302         adapter->rx_eitr_param = 20000;
4303         adapter->tx_itr_setting = 1;
4304         adapter->tx_eitr_param = 10000;
4305
4306         /* set defaults for eitr in MegaBytes */
4307         adapter->eitr_low = 10;
4308         adapter->eitr_high = 20;
4309
4310         /* set default ring sizes */
4311         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4312         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4313
4314         /* initialize eeprom parameters */
4315         if (ixgbe_init_eeprom_params_generic(hw)) {
4316                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4317                 return -EIO;
4318         }
4319
4320         /* enable rx csum by default */
4321         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4322
4323         /* get assigned NUMA node */
4324         adapter->node = dev_to_node(&pdev->dev);
4325
4326         set_bit(__IXGBE_DOWN, &adapter->state);
4327
4328         return 0;
4329 }
4330
4331 /**
4332  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4333  * @adapter: board private structure
4334  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4335  *
4336  * Return 0 on success, negative on failure
4337  **/
4338 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4339                              struct ixgbe_ring *tx_ring)
4340 {
4341         struct pci_dev *pdev = adapter->pdev;
4342         int size;
4343
4344         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4345         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4346         if (!tx_ring->tx_buffer_info)
4347                 tx_ring->tx_buffer_info = vmalloc(size);
4348         if (!tx_ring->tx_buffer_info)
4349                 goto err;
4350         memset(tx_ring->tx_buffer_info, 0, size);
4351
4352         /* round up to nearest 4K */
4353         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4354         tx_ring->size = ALIGN(tx_ring->size, 4096);
4355
4356         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4357                                              &tx_ring->dma);
4358         if (!tx_ring->desc)
4359                 goto err;
4360
4361         tx_ring->next_to_use = 0;
4362         tx_ring->next_to_clean = 0;
4363         tx_ring->work_limit = tx_ring->count;
4364         return 0;
4365
4366 err:
4367         vfree(tx_ring->tx_buffer_info);
4368         tx_ring->tx_buffer_info = NULL;
4369         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4370                             "descriptor ring\n");
4371         return -ENOMEM;
4372 }
4373
4374 /**
4375  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4376  * @adapter: board private structure
4377  *
4378  * If this function returns with an error, then it's possible one or
4379  * more of the rings is populated (while the rest are not).  It is the
4380  * callers duty to clean those orphaned rings.
4381  *
4382  * Return 0 on success, negative on failure
4383  **/
4384 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4385 {
4386         int i, err = 0;
4387
4388         for (i = 0; i < adapter->num_tx_queues; i++) {
4389                 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
4390                 if (!err)
4391                         continue;
4392                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4393                 break;
4394         }
4395
4396         return err;
4397 }
4398
4399 /**
4400  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4401  * @adapter: board private structure
4402  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4403  *
4404  * Returns 0 on success, negative on failure
4405  **/
4406 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4407                              struct ixgbe_ring *rx_ring)
4408 {
4409         struct pci_dev *pdev = adapter->pdev;
4410         int size;
4411
4412         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4413         rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4414         if (!rx_ring->rx_buffer_info)
4415                 rx_ring->rx_buffer_info = vmalloc(size);
4416         if (!rx_ring->rx_buffer_info) {
4417                 DPRINTK(PROBE, ERR,
4418                         "vmalloc allocation failed for the rx desc ring\n");
4419                 goto alloc_failed;
4420         }
4421         memset(rx_ring->rx_buffer_info, 0, size);
4422
4423         /* Round up to nearest 4K */
4424         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4425         rx_ring->size = ALIGN(rx_ring->size, 4096);
4426
4427         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
4428
4429         if (!rx_ring->desc) {
4430                 DPRINTK(PROBE, ERR,
4431                         "Memory allocation failed for the rx desc ring\n");
4432                 vfree(rx_ring->rx_buffer_info);
4433                 goto alloc_failed;
4434         }
4435
4436         rx_ring->next_to_clean = 0;
4437         rx_ring->next_to_use = 0;
4438
4439         return 0;
4440
4441 alloc_failed:
4442         return -ENOMEM;
4443 }
4444
4445 /**
4446  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4447  * @adapter: board private structure
4448  *
4449  * If this function returns with an error, then it's possible one or
4450  * more of the rings is populated (while the rest are not).  It is the
4451  * callers duty to clean those orphaned rings.
4452  *
4453  * Return 0 on success, negative on failure
4454  **/
4455
4456 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4457 {
4458         int i, err = 0;
4459
4460         for (i = 0; i < adapter->num_rx_queues; i++) {
4461                 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
4462                 if (!err)
4463                         continue;
4464                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4465                 break;
4466         }
4467
4468         return err;
4469 }
4470
4471 /**
4472  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4473  * @adapter: board private structure
4474  * @tx_ring: Tx descriptor ring for a specific queue
4475  *
4476  * Free all transmit software resources
4477  **/
4478 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4479                              struct ixgbe_ring *tx_ring)
4480 {
4481         struct pci_dev *pdev = adapter->pdev;
4482
4483         ixgbe_clean_tx_ring(adapter, tx_ring);
4484
4485         vfree(tx_ring->tx_buffer_info);
4486         tx_ring->tx_buffer_info = NULL;
4487
4488         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4489
4490         tx_ring->desc = NULL;
4491 }
4492
4493 /**
4494  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4495  * @adapter: board private structure
4496  *
4497  * Free all transmit software resources
4498  **/
4499 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4500 {
4501         int i;
4502
4503         for (i = 0; i < adapter->num_tx_queues; i++)
4504                 if (adapter->tx_ring[i]->desc)
4505                         ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
4506 }
4507
4508 /**
4509  * ixgbe_free_rx_resources - Free Rx Resources
4510  * @adapter: board private structure
4511  * @rx_ring: ring to clean the resources from
4512  *
4513  * Free all receive software resources
4514  **/
4515 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4516                              struct ixgbe_ring *rx_ring)
4517 {
4518         struct pci_dev *pdev = adapter->pdev;
4519
4520         ixgbe_clean_rx_ring(adapter, rx_ring);
4521
4522         vfree(rx_ring->rx_buffer_info);
4523         rx_ring->rx_buffer_info = NULL;
4524
4525         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4526
4527         rx_ring->desc = NULL;
4528 }
4529
4530 /**
4531  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4532  * @adapter: board private structure
4533  *
4534  * Free all receive software resources
4535  **/
4536 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4537 {
4538         int i;
4539
4540         for (i = 0; i < adapter->num_rx_queues; i++)
4541                 if (adapter->rx_ring[i]->desc)
4542                         ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
4543 }
4544
4545 /**
4546  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4547  * @netdev: network interface device structure
4548  * @new_mtu: new value for maximum frame size
4549  *
4550  * Returns 0 on success, negative on failure
4551  **/
4552 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4553 {
4554         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4555         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4556
4557         /* MTU < 68 is an error and causes problems on some kernels */
4558         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4559                 return -EINVAL;
4560
4561         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4562                 netdev->mtu, new_mtu);
4563         /* must set new MTU before calling down or up */
4564         netdev->mtu = new_mtu;
4565
4566         if (netif_running(netdev))
4567                 ixgbe_reinit_locked(adapter);
4568
4569         return 0;
4570 }
4571
4572 /**
4573  * ixgbe_open - Called when a network interface is made active
4574  * @netdev: network interface device structure
4575  *
4576  * Returns 0 on success, negative value on failure
4577  *
4578  * The open entry point is called when a network interface is made
4579  * active by the system (IFF_UP).  At this point all resources needed
4580  * for transmit and receive operations are allocated, the interrupt
4581  * handler is registered with the OS, the watchdog timer is started,
4582  * and the stack is notified that the interface is ready.
4583  **/
4584 static int ixgbe_open(struct net_device *netdev)
4585 {
4586         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4587         int err;
4588
4589         /* disallow open during test */
4590         if (test_bit(__IXGBE_TESTING, &adapter->state))
4591                 return -EBUSY;
4592
4593         netif_carrier_off(netdev);
4594
4595         /* allocate transmit descriptors */
4596         err = ixgbe_setup_all_tx_resources(adapter);
4597         if (err)
4598                 goto err_setup_tx;
4599
4600         /* allocate receive descriptors */
4601         err = ixgbe_setup_all_rx_resources(adapter);
4602         if (err)
4603                 goto err_setup_rx;
4604
4605         ixgbe_configure(adapter);
4606
4607         err = ixgbe_request_irq(adapter);
4608         if (err)
4609                 goto err_req_irq;
4610
4611         err = ixgbe_up_complete(adapter);
4612         if (err)
4613                 goto err_up;
4614
4615         netif_tx_start_all_queues(netdev);
4616
4617         return 0;
4618
4619 err_up:
4620         ixgbe_release_hw_control(adapter);
4621         ixgbe_free_irq(adapter);
4622 err_req_irq:
4623 err_setup_rx:
4624         ixgbe_free_all_rx_resources(adapter);
4625 err_setup_tx:
4626         ixgbe_free_all_tx_resources(adapter);
4627         ixgbe_reset(adapter);
4628
4629         return err;
4630 }
4631
4632 /**
4633  * ixgbe_close - Disables a network interface
4634  * @netdev: network interface device structure
4635  *
4636  * Returns 0, this is not allowed to fail
4637  *
4638  * The close entry point is called when an interface is de-activated
4639  * by the OS.  The hardware is still under the drivers control, but
4640  * needs to be disabled.  A global MAC reset is issued to stop the
4641  * hardware, and all transmit and receive resources are freed.
4642  **/
4643 static int ixgbe_close(struct net_device *netdev)
4644 {
4645         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4646
4647         ixgbe_down(adapter);
4648         ixgbe_free_irq(adapter);
4649
4650         ixgbe_free_all_tx_resources(adapter);
4651         ixgbe_free_all_rx_resources(adapter);
4652
4653         ixgbe_release_hw_control(adapter);
4654
4655         return 0;
4656 }
4657
4658 #ifdef CONFIG_PM
4659 static int ixgbe_resume(struct pci_dev *pdev)
4660 {
4661         struct net_device *netdev = pci_get_drvdata(pdev);
4662         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4663         u32 err;
4664
4665         pci_set_power_state(pdev, PCI_D0);
4666         pci_restore_state(pdev);
4667         /*
4668          * pci_restore_state clears dev->state_saved so call
4669          * pci_save_state to restore it.
4670          */
4671         pci_save_state(pdev);
4672
4673         err = pci_enable_device_mem(pdev);
4674         if (err) {
4675                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4676                                 "suspend\n");
4677                 return err;
4678         }
4679         pci_set_master(pdev);
4680
4681         pci_wake_from_d3(pdev, false);
4682
4683         err = ixgbe_init_interrupt_scheme(adapter);
4684         if (err) {
4685                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4686                                 "device\n");
4687                 return err;
4688         }
4689
4690         ixgbe_reset(adapter);
4691
4692         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4693
4694         if (netif_running(netdev)) {
4695                 err = ixgbe_open(adapter->netdev);
4696                 if (err)
4697                         return err;
4698         }
4699
4700         netif_device_attach(netdev);
4701
4702         return 0;
4703 }
4704 #endif /* CONFIG_PM */
4705
4706 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4707 {
4708         struct net_device *netdev = pci_get_drvdata(pdev);
4709         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4710         struct ixgbe_hw *hw = &adapter->hw;
4711         u32 ctrl, fctrl;
4712         u32 wufc = adapter->wol;
4713 #ifdef CONFIG_PM
4714         int retval = 0;
4715 #endif
4716
4717         netif_device_detach(netdev);
4718
4719         if (netif_running(netdev)) {
4720                 ixgbe_down(adapter);
4721                 ixgbe_free_irq(adapter);
4722                 ixgbe_free_all_tx_resources(adapter);
4723                 ixgbe_free_all_rx_resources(adapter);
4724         }
4725         ixgbe_clear_interrupt_scheme(adapter);
4726
4727 #ifdef CONFIG_PM
4728         retval = pci_save_state(pdev);
4729         if (retval)
4730                 return retval;
4731
4732 #endif
4733         if (wufc) {
4734                 ixgbe_set_rx_mode(netdev);
4735
4736                 /* turn on all-multi mode if wake on multicast is enabled */
4737                 if (wufc & IXGBE_WUFC_MC) {
4738                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4739                         fctrl |= IXGBE_FCTRL_MPE;
4740                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4741                 }
4742
4743                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4744                 ctrl |= IXGBE_CTRL_GIO_DIS;
4745                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4746
4747                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4748         } else {
4749                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4750                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4751         }
4752
4753         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4754                 pci_wake_from_d3(pdev, true);
4755         else
4756                 pci_wake_from_d3(pdev, false);
4757
4758         *enable_wake = !!wufc;
4759
4760         ixgbe_release_hw_control(adapter);
4761
4762         pci_disable_device(pdev);
4763
4764         return 0;
4765 }
4766
4767 #ifdef CONFIG_PM
4768 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4769 {
4770         int retval;
4771         bool wake;
4772
4773         retval = __ixgbe_shutdown(pdev, &wake);
4774         if (retval)
4775                 return retval;
4776
4777         if (wake) {
4778                 pci_prepare_to_sleep(pdev);
4779         } else {
4780                 pci_wake_from_d3(pdev, false);
4781                 pci_set_power_state(pdev, PCI_D3hot);
4782         }
4783
4784         return 0;
4785 }
4786 #endif /* CONFIG_PM */
4787
4788 static void ixgbe_shutdown(struct pci_dev *pdev)
4789 {
4790         bool wake;
4791
4792         __ixgbe_shutdown(pdev, &wake);
4793
4794         if (system_state == SYSTEM_POWER_OFF) {
4795                 pci_wake_from_d3(pdev, wake);
4796                 pci_set_power_state(pdev, PCI_D3hot);
4797         }
4798 }
4799
4800 /**
4801  * ixgbe_update_stats - Update the board statistics counters.
4802  * @adapter: board private structure
4803  **/
4804 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4805 {
4806         struct net_device *netdev = adapter->netdev;
4807         struct ixgbe_hw *hw = &adapter->hw;
4808         u64 total_mpc = 0;
4809         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4810         u64 non_eop_descs = 0, restart_queue = 0;
4811
4812         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
4813                 u64 rsc_count = 0;
4814                 u64 rsc_flush = 0;
4815                 for (i = 0; i < 16; i++)
4816                         adapter->hw_rx_no_dma_resources +=
4817                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4818                 for (i = 0; i < adapter->num_rx_queues; i++) {
4819                         rsc_count += adapter->rx_ring[i]->rsc_count;
4820                         rsc_flush += adapter->rx_ring[i]->rsc_flush;
4821                 }
4822                 adapter->rsc_total_count = rsc_count;
4823                 adapter->rsc_total_flush = rsc_flush;
4824         }
4825
4826         /* gather some stats to the adapter struct that are per queue */
4827         for (i = 0; i < adapter->num_tx_queues; i++)
4828                 restart_queue += adapter->tx_ring[i]->restart_queue;
4829         adapter->restart_queue = restart_queue;
4830
4831         for (i = 0; i < adapter->num_rx_queues; i++)
4832                 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
4833         adapter->non_eop_descs = non_eop_descs;
4834
4835         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4836         for (i = 0; i < 8; i++) {
4837                 /* for packet buffers not used, the register should read 0 */
4838                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4839                 missed_rx += mpc;
4840                 adapter->stats.mpc[i] += mpc;
4841                 total_mpc += adapter->stats.mpc[i];
4842                 if (hw->mac.type == ixgbe_mac_82598EB)
4843                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4844                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4845                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4846                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4847                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4848                 if (hw->mac.type == ixgbe_mac_82599EB) {
4849                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4850                                                             IXGBE_PXONRXCNT(i));
4851                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4852                                                            IXGBE_PXOFFRXCNT(i));
4853                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4854                 } else {
4855                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4856                                                               IXGBE_PXONRXC(i));
4857                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4858                                                              IXGBE_PXOFFRXC(i));
4859                 }
4860                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4861                                                             IXGBE_PXONTXC(i));
4862                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4863                                                              IXGBE_PXOFFTXC(i));
4864         }
4865         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4866         /* work around hardware counting issue */
4867         adapter->stats.gprc -= missed_rx;
4868
4869         /* 82598 hardware only has a 32 bit counter in the high register */
4870         if (hw->mac.type == ixgbe_mac_82599EB) {
4871                 u64 tmp;
4872                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4873                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4874                 adapter->stats.gorc += (tmp << 32);
4875                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4876                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4877                 adapter->stats.gotc += (tmp << 32);
4878                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4879                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4880                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4881                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4882                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4883                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4884 #ifdef IXGBE_FCOE
4885                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4886                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4887                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4888                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4889                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4890                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4891 #endif /* IXGBE_FCOE */
4892         } else {
4893                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4894                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4895                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4896                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4897                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4898         }
4899         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4900         adapter->stats.bprc += bprc;
4901         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4902         if (hw->mac.type == ixgbe_mac_82598EB)
4903                 adapter->stats.mprc -= bprc;
4904         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4905         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4906         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4907         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4908         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4909         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4910         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4911         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4912         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4913         adapter->stats.lxontxc += lxon;
4914         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4915         adapter->stats.lxofftxc += lxoff;
4916         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4917         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4918         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4919         /*
4920          * 82598 errata - tx of flow control packets is included in tx counters
4921          */
4922         xon_off_tot = lxon + lxoff;
4923         adapter->stats.gptc -= xon_off_tot;
4924         adapter->stats.mptc -= xon_off_tot;
4925         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4926         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4927         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4928         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4929         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4930         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4931         adapter->stats.ptc64 -= xon_off_tot;
4932         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4933         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4934         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4935         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4936         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4937         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4938
4939         /* Fill out the OS statistics structure */
4940         netdev->stats.multicast = adapter->stats.mprc;
4941
4942         /* Rx Errors */
4943         netdev->stats.rx_errors = adapter->stats.crcerrs +
4944                                        adapter->stats.rlec;
4945         netdev->stats.rx_dropped = 0;
4946         netdev->stats.rx_length_errors = adapter->stats.rlec;
4947         netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4948         netdev->stats.rx_missed_errors = total_mpc;
4949 }
4950
4951 /**
4952  * ixgbe_watchdog - Timer Call-back
4953  * @data: pointer to adapter cast into an unsigned long
4954  **/
4955 static void ixgbe_watchdog(unsigned long data)
4956 {
4957         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4958         struct ixgbe_hw *hw = &adapter->hw;
4959         u64 eics = 0;
4960         int i;
4961
4962         /*
4963          *  Do the watchdog outside of interrupt context due to the lovely
4964          * delays that some of the newer hardware requires
4965          */
4966
4967         if (test_bit(__IXGBE_DOWN, &adapter->state))
4968                 goto watchdog_short_circuit;
4969
4970         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4971                 /*
4972                  * for legacy and MSI interrupts don't set any bits
4973                  * that are enabled for EIAM, because this operation
4974                  * would set *both* EIMS and EICS for any bit in EIAM
4975                  */
4976                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4977                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4978                 goto watchdog_reschedule;
4979         }
4980
4981         /* get one bit for every active tx/rx interrupt vector */
4982         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4983                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4984                 if (qv->rxr_count || qv->txr_count)
4985                         eics |= ((u64)1 << i);
4986         }
4987
4988         /* Cause software interrupt to ensure rx rings are cleaned */
4989         ixgbe_irq_rearm_queues(adapter, eics);
4990
4991 watchdog_reschedule:
4992         /* Reset the timer */
4993         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4994
4995 watchdog_short_circuit:
4996         schedule_work(&adapter->watchdog_task);
4997 }
4998
4999 /**
5000  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5001  * @work: pointer to work_struct containing our data
5002  **/
5003 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5004 {
5005         struct ixgbe_adapter *adapter = container_of(work,
5006                                                      struct ixgbe_adapter,
5007                                                      multispeed_fiber_task);
5008         struct ixgbe_hw *hw = &adapter->hw;
5009         u32 autoneg;
5010         bool negotiation;
5011
5012         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5013         autoneg = hw->phy.autoneg_advertised;
5014         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5015                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5016         hw->mac.autotry_restart = false;
5017         if (hw->mac.ops.setup_link)
5018                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5019         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5020         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5021 }
5022
5023 /**
5024  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5025  * @work: pointer to work_struct containing our data
5026  **/
5027 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5028 {
5029         struct ixgbe_adapter *adapter = container_of(work,
5030                                                      struct ixgbe_adapter,
5031                                                      sfp_config_module_task);
5032         struct ixgbe_hw *hw = &adapter->hw;
5033         u32 err;
5034
5035         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5036
5037         /* Time for electrical oscillations to settle down */
5038         msleep(100);
5039         err = hw->phy.ops.identify_sfp(hw);
5040
5041         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5042                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5043                         "an unsupported SFP+ module type was detected.\n"
5044                         "Reload the driver after installing a supported "
5045                         "module.\n");
5046                 unregister_netdev(adapter->netdev);
5047                 return;
5048         }
5049         hw->mac.ops.setup_sfp(hw);
5050
5051         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5052                 /* This will also work for DA Twinax connections */
5053                 schedule_work(&adapter->multispeed_fiber_task);
5054         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5055 }
5056
5057 /**
5058  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5059  * @work: pointer to work_struct containing our data
5060  **/
5061 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5062 {
5063         struct ixgbe_adapter *adapter = container_of(work,
5064                                                      struct ixgbe_adapter,
5065                                                      fdir_reinit_task);
5066         struct ixgbe_hw *hw = &adapter->hw;
5067         int i;
5068
5069         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5070                 for (i = 0; i < adapter->num_tx_queues; i++)
5071                         set_bit(__IXGBE_FDIR_INIT_DONE,
5072                                 &(adapter->tx_ring[i]->reinit_state));
5073         } else {
5074                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
5075                         "ignored adding FDIR ATR filters\n");
5076         }
5077         /* Done FDIR Re-initialization, enable transmits */
5078         netif_tx_start_all_queues(adapter->netdev);
5079 }
5080
5081 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5082
5083 /**
5084  * ixgbe_watchdog_task - worker thread to bring link up
5085  * @work: pointer to work_struct containing our data
5086  **/
5087 static void ixgbe_watchdog_task(struct work_struct *work)
5088 {
5089         struct ixgbe_adapter *adapter = container_of(work,
5090                                                      struct ixgbe_adapter,
5091                                                      watchdog_task);
5092         struct net_device *netdev = adapter->netdev;
5093         struct ixgbe_hw *hw = &adapter->hw;
5094         u32 link_speed;
5095         bool link_up;
5096         int i;
5097         struct ixgbe_ring *tx_ring;
5098         int some_tx_pending = 0;
5099
5100         mutex_lock(&ixgbe_watchdog_lock);
5101
5102         link_up = adapter->link_up;
5103         link_speed = adapter->link_speed;
5104
5105         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5106                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5107                 if (link_up) {
5108 #ifdef CONFIG_DCB
5109                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5110                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5111                                         hw->mac.ops.fc_enable(hw, i);
5112                         } else {
5113                                 hw->mac.ops.fc_enable(hw, 0);
5114                         }
5115 #else
5116                         hw->mac.ops.fc_enable(hw, 0);
5117 #endif
5118                 }
5119
5120                 if (link_up ||
5121                     time_after(jiffies, (adapter->link_check_timeout +
5122                                          IXGBE_TRY_LINK_TIMEOUT))) {
5123                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5124                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5125                 }
5126                 adapter->link_up = link_up;
5127                 adapter->link_speed = link_speed;
5128         }
5129
5130         if (link_up) {
5131                 if (!netif_carrier_ok(netdev)) {
5132                         bool flow_rx, flow_tx;
5133
5134                         if (hw->mac.type == ixgbe_mac_82599EB) {
5135                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5136                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5137                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5138                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5139                         } else {
5140                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5141                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5142                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5143                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5144                         }
5145
5146                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
5147                                "Flow Control: %s\n",
5148                                netdev->name,
5149                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5150                                 "10 Gbps" :
5151                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5152                                  "1 Gbps" : "unknown speed")),
5153                                ((flow_rx && flow_tx) ? "RX/TX" :
5154                                 (flow_rx ? "RX" :
5155                                 (flow_tx ? "TX" : "None"))));
5156
5157                         netif_carrier_on(netdev);
5158                 } else {
5159                         /* Force detection of hung controller */
5160                         adapter->detect_tx_hung = true;
5161                 }
5162         } else {
5163                 adapter->link_up = false;
5164                 adapter->link_speed = 0;
5165                 if (netif_carrier_ok(netdev)) {
5166                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
5167                                netdev->name);
5168                         netif_carrier_off(netdev);
5169                 }
5170         }
5171
5172         if (!netif_carrier_ok(netdev)) {
5173                 for (i = 0; i < adapter->num_tx_queues; i++) {
5174                         tx_ring = adapter->tx_ring[i];
5175                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5176                                 some_tx_pending = 1;
5177                                 break;
5178                         }
5179                 }
5180
5181                 if (some_tx_pending) {
5182                         /* We've lost link, so the controller stops DMA,
5183                          * but we've got queued Tx work that's never going
5184                          * to get done, so reset controller to flush Tx.
5185                          * (Do the reset outside of interrupt context).
5186                          */
5187                          schedule_work(&adapter->reset_task);
5188                 }
5189         }
5190
5191         ixgbe_update_stats(adapter);
5192         mutex_unlock(&ixgbe_watchdog_lock);
5193 }
5194
5195 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5196                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5197                      u32 tx_flags, u8 *hdr_len)
5198 {
5199         struct ixgbe_adv_tx_context_desc *context_desc;
5200         unsigned int i;
5201         int err;
5202         struct ixgbe_tx_buffer *tx_buffer_info;
5203         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5204         u32 mss_l4len_idx, l4len;
5205
5206         if (skb_is_gso(skb)) {
5207                 if (skb_header_cloned(skb)) {
5208                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5209                         if (err)
5210                                 return err;
5211                 }
5212                 l4len = tcp_hdrlen(skb);
5213                 *hdr_len += l4len;
5214
5215                 if (skb->protocol == htons(ETH_P_IP)) {
5216                         struct iphdr *iph = ip_hdr(skb);
5217                         iph->tot_len = 0;
5218                         iph->check = 0;
5219                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5220                                                                  iph->daddr, 0,
5221                                                                  IPPROTO_TCP,
5222                                                                  0);
5223                 } else if (skb_is_gso_v6(skb)) {
5224                         ipv6_hdr(skb)->payload_len = 0;
5225                         tcp_hdr(skb)->check =
5226                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5227                                              &ipv6_hdr(skb)->daddr,
5228                                              0, IPPROTO_TCP, 0);
5229                 }
5230
5231                 i = tx_ring->next_to_use;
5232
5233                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5234                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5235
5236                 /* VLAN MACLEN IPLEN */
5237                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5238                         vlan_macip_lens |=
5239                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5240                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5241                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5242                 *hdr_len += skb_network_offset(skb);
5243                 vlan_macip_lens |=
5244                     (skb_transport_header(skb) - skb_network_header(skb));
5245                 *hdr_len +=
5246                     (skb_transport_header(skb) - skb_network_header(skb));
5247                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5248                 context_desc->seqnum_seed = 0;
5249
5250                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5251                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5252                                    IXGBE_ADVTXD_DTYP_CTXT);
5253
5254                 if (skb->protocol == htons(ETH_P_IP))
5255                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5256                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5257                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5258
5259                 /* MSS L4LEN IDX */
5260                 mss_l4len_idx =
5261                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5262                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5263                 /* use index 1 for TSO */
5264                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5265                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5266
5267                 tx_buffer_info->time_stamp = jiffies;
5268                 tx_buffer_info->next_to_watch = i;
5269
5270                 i++;
5271                 if (i == tx_ring->count)
5272                         i = 0;
5273                 tx_ring->next_to_use = i;
5274
5275                 return true;
5276         }
5277         return false;
5278 }
5279
5280 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5281                           struct ixgbe_ring *tx_ring,
5282                           struct sk_buff *skb, u32 tx_flags)
5283 {
5284         struct ixgbe_adv_tx_context_desc *context_desc;
5285         unsigned int i;
5286         struct ixgbe_tx_buffer *tx_buffer_info;
5287         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5288
5289         if (skb->ip_summed == CHECKSUM_PARTIAL ||
5290             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5291                 i = tx_ring->next_to_use;
5292                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5293                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5294
5295                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5296                         vlan_macip_lens |=
5297                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5298                 vlan_macip_lens |= (skb_network_offset(skb) <<
5299                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5300                 if (skb->ip_summed == CHECKSUM_PARTIAL)
5301                         vlan_macip_lens |= (skb_transport_header(skb) -
5302                                             skb_network_header(skb));
5303
5304                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5305                 context_desc->seqnum_seed = 0;
5306
5307                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5308                                     IXGBE_ADVTXD_DTYP_CTXT);
5309
5310                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5311                         __be16 protocol;
5312
5313                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5314                                 const struct vlan_ethhdr *vhdr =
5315                                         (const struct vlan_ethhdr *)skb->data;
5316
5317                                 protocol = vhdr->h_vlan_encapsulated_proto;
5318                         } else {
5319                                 protocol = skb->protocol;
5320                         }
5321
5322                         switch (protocol) {
5323                         case cpu_to_be16(ETH_P_IP):
5324                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5325                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5326                                         type_tucmd_mlhl |=
5327                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5328                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5329                                         type_tucmd_mlhl |=
5330                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5331                                 break;
5332                         case cpu_to_be16(ETH_P_IPV6):
5333                                 /* XXX what about other V6 headers?? */
5334                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5335                                         type_tucmd_mlhl |=
5336                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5337                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5338                                         type_tucmd_mlhl |=
5339                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5340                                 break;
5341                         default:
5342                                 if (unlikely(net_ratelimit())) {
5343                                         DPRINTK(PROBE, WARNING,
5344                                          "partial checksum but proto=%x!\n",
5345                                          skb->protocol);
5346                                 }
5347                                 break;
5348                         }
5349                 }
5350
5351                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5352                 /* use index zero for tx checksum offload */
5353                 context_desc->mss_l4len_idx = 0;
5354
5355                 tx_buffer_info->time_stamp = jiffies;
5356                 tx_buffer_info->next_to_watch = i;
5357
5358                 i++;
5359                 if (i == tx_ring->count)
5360                         i = 0;
5361                 tx_ring->next_to_use = i;
5362
5363                 return true;
5364         }
5365
5366         return false;
5367 }
5368
5369 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5370                         struct ixgbe_ring *tx_ring,
5371                         struct sk_buff *skb, u32 tx_flags,
5372                         unsigned int first)
5373 {
5374         struct pci_dev *pdev = adapter->pdev;
5375         struct ixgbe_tx_buffer *tx_buffer_info;
5376         unsigned int len;
5377         unsigned int total = skb->len;
5378         unsigned int offset = 0, size, count = 0, i;
5379         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5380         unsigned int f;
5381
5382         i = tx_ring->next_to_use;
5383
5384         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5385                 /* excluding fcoe_crc_eof for FCoE */
5386                 total -= sizeof(struct fcoe_crc_eof);
5387
5388         len = min(skb_headlen(skb), total);
5389         while (len) {
5390                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5391                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5392
5393                 tx_buffer_info->length = size;
5394                 tx_buffer_info->mapped_as_page = false;
5395                 tx_buffer_info->dma = pci_map_single(pdev,
5396                                                      skb->data + offset,
5397                                                      size, PCI_DMA_TODEVICE);
5398                 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5399                         goto dma_error;
5400                 tx_buffer_info->time_stamp = jiffies;
5401                 tx_buffer_info->next_to_watch = i;
5402
5403                 len -= size;
5404                 total -= size;
5405                 offset += size;
5406                 count++;
5407
5408                 if (len) {
5409                         i++;
5410                         if (i == tx_ring->count)
5411                                 i = 0;
5412                 }
5413         }
5414
5415         for (f = 0; f < nr_frags; f++) {
5416                 struct skb_frag_struct *frag;
5417
5418                 frag = &skb_shinfo(skb)->frags[f];
5419                 len = min((unsigned int)frag->size, total);
5420                 offset = frag->page_offset;
5421
5422                 while (len) {
5423                         i++;
5424                         if (i == tx_ring->count)
5425                                 i = 0;
5426
5427                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
5428                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5429
5430                         tx_buffer_info->length = size;
5431                         tx_buffer_info->dma = pci_map_page(adapter->pdev,
5432                                                            frag->page,
5433                                                            offset, size,
5434                                                            PCI_DMA_TODEVICE);
5435                         tx_buffer_info->mapped_as_page = true;
5436                         if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5437                                 goto dma_error;
5438                         tx_buffer_info->time_stamp = jiffies;
5439                         tx_buffer_info->next_to_watch = i;
5440
5441                         len -= size;
5442                         total -= size;
5443                         offset += size;
5444                         count++;
5445                 }
5446                 if (total == 0)
5447                         break;
5448         }
5449
5450         tx_ring->tx_buffer_info[i].skb = skb;
5451         tx_ring->tx_buffer_info[first].next_to_watch = i;
5452
5453         return count;
5454
5455 dma_error:
5456         dev_err(&pdev->dev, "TX DMA map failed\n");
5457
5458         /* clear timestamp and dma mappings for failed tx_buffer_info map */
5459         tx_buffer_info->dma = 0;
5460         tx_buffer_info->time_stamp = 0;
5461         tx_buffer_info->next_to_watch = 0;
5462         if (count)
5463                 count--;
5464
5465         /* clear timestamp and dma mappings for remaining portion of packet */
5466         while (count--) {
5467                 if (i==0)
5468                         i += tx_ring->count;
5469                 i--;
5470                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5471                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5472         }
5473
5474         return 0;
5475 }
5476
5477 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5478                            struct ixgbe_ring *tx_ring,
5479                            int tx_flags, int count, u32 paylen, u8 hdr_len)
5480 {
5481         union ixgbe_adv_tx_desc *tx_desc = NULL;
5482         struct ixgbe_tx_buffer *tx_buffer_info;
5483         u32 olinfo_status = 0, cmd_type_len = 0;
5484         unsigned int i;
5485         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5486
5487         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5488
5489         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5490
5491         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5492                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5493
5494         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5495                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5496
5497                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5498                                  IXGBE_ADVTXD_POPTS_SHIFT;
5499
5500                 /* use index 1 context for tso */
5501                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5502                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5503                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5504                                          IXGBE_ADVTXD_POPTS_SHIFT;
5505
5506         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5507                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5508                                  IXGBE_ADVTXD_POPTS_SHIFT;
5509
5510         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5511                 olinfo_status |= IXGBE_ADVTXD_CC;
5512                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5513                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5514                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5515         }
5516
5517         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5518
5519         i = tx_ring->next_to_use;
5520         while (count--) {
5521                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5522                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5523                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5524                 tx_desc->read.cmd_type_len =
5525                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5526                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5527                 i++;
5528                 if (i == tx_ring->count)
5529                         i = 0;
5530         }
5531
5532         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5533
5534         /*
5535          * Force memory writes to complete before letting h/w
5536          * know there are new descriptors to fetch.  (Only
5537          * applicable for weak-ordered memory model archs,
5538          * such as IA-64).
5539          */
5540         wmb();
5541
5542         tx_ring->next_to_use = i;
5543         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5544 }
5545
5546 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5547                       int queue, u32 tx_flags)
5548 {
5549         /* Right now, we support IPv4 only */
5550         struct ixgbe_atr_input atr_input;
5551         struct tcphdr *th;
5552         struct iphdr *iph = ip_hdr(skb);
5553         struct ethhdr *eth = (struct ethhdr *)skb->data;
5554         u16 vlan_id, src_port, dst_port, flex_bytes;
5555         u32 src_ipv4_addr, dst_ipv4_addr;
5556         u8 l4type = 0;
5557
5558         /* check if we're UDP or TCP */
5559         if (iph->protocol == IPPROTO_TCP) {
5560                 th = tcp_hdr(skb);
5561                 src_port = th->source;
5562                 dst_port = th->dest;
5563                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5564                 /* l4type IPv4 type is 0, no need to assign */
5565         } else {
5566                 /* Unsupported L4 header, just bail here */
5567                 return;
5568         }
5569
5570         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5571
5572         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5573                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5574         src_ipv4_addr = iph->saddr;
5575         dst_ipv4_addr = iph->daddr;
5576         flex_bytes = eth->h_proto;
5577
5578         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5579         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5580         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5581         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5582         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5583         /* src and dst are inverted, think how the receiver sees them */
5584         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5585         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5586
5587         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5588         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5589 }
5590
5591 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5592                                  struct ixgbe_ring *tx_ring, int size)
5593 {
5594         netif_stop_subqueue(netdev, tx_ring->queue_index);
5595         /* Herbert's original patch had:
5596          *  smp_mb__after_netif_stop_queue();
5597          * but since that doesn't exist yet, just open code it. */
5598         smp_mb();
5599
5600         /* We need to check again in a case another CPU has just
5601          * made room available. */
5602         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5603                 return -EBUSY;
5604
5605         /* A reprieve! - use start_queue because it doesn't call schedule */
5606         netif_start_subqueue(netdev, tx_ring->queue_index);
5607         ++tx_ring->restart_queue;
5608         return 0;
5609 }
5610
5611 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5612                               struct ixgbe_ring *tx_ring, int size)
5613 {
5614         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5615                 return 0;
5616         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5617 }
5618
5619 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5620 {
5621         struct ixgbe_adapter *adapter = netdev_priv(dev);
5622         int txq = smp_processor_id();
5623
5624         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5625                 while (unlikely(txq >= dev->real_num_tx_queues))
5626                         txq -= dev->real_num_tx_queues;
5627                 return txq;
5628         }
5629
5630 #ifdef IXGBE_FCOE
5631         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5632             ((skb->protocol == htons(ETH_P_FCOE)) ||
5633              (skb->protocol == htons(ETH_P_FIP)))) {
5634                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5635                 txq += adapter->ring_feature[RING_F_FCOE].mask;
5636                 return txq;
5637         }
5638 #endif
5639         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5640                 if (skb->priority == TC_PRIO_CONTROL)
5641                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
5642                 else
5643                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
5644                                >> 13;
5645                 return txq;
5646         }
5647
5648         return skb_tx_hash(dev, skb);
5649 }
5650
5651 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5652                                     struct net_device *netdev)
5653 {
5654         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5655         struct ixgbe_ring *tx_ring;
5656         struct netdev_queue *txq;
5657         unsigned int first;
5658         unsigned int tx_flags = 0;
5659         u8 hdr_len = 0;
5660         int tso;
5661         int count = 0;
5662         unsigned int f;
5663
5664         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5665                 tx_flags |= vlan_tx_tag_get(skb);
5666                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5667                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5668                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
5669                 }
5670                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5671                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5672         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5673                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
5674                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5675                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5676         }
5677
5678         tx_ring = adapter->tx_ring[skb->queue_mapping];
5679
5680 #ifdef IXGBE_FCOE
5681         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
5682 #ifdef CONFIG_IXGBE_DCB
5683                 /* for FCoE with DCB, we force the priority to what
5684                  * was specified by the switch */
5685                 if ((skb->protocol == htons(ETH_P_FCOE)) ||
5686                     (skb->protocol == htons(ETH_P_FIP))) {
5687                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5688                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
5689                         tx_flags |= ((adapter->fcoe.up << 13)
5690                                      << IXGBE_TX_FLAGS_VLAN_SHIFT);
5691                 }
5692 #endif
5693                 /* flag for FCoE offloads */
5694                 if (skb->protocol == htons(ETH_P_FCOE))
5695                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
5696         }
5697 #endif
5698
5699         /* four things can cause us to need a context descriptor */
5700         if (skb_is_gso(skb) ||
5701             (skb->ip_summed == CHECKSUM_PARTIAL) ||
5702             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5703             (tx_flags & IXGBE_TX_FLAGS_FCOE))
5704                 count++;
5705
5706         count += TXD_USE_COUNT(skb_headlen(skb));
5707         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5708                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5709
5710         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5711                 adapter->tx_busy++;
5712                 return NETDEV_TX_BUSY;
5713         }
5714
5715         first = tx_ring->next_to_use;
5716         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5717 #ifdef IXGBE_FCOE
5718                 /* setup tx offload for FCoE */
5719                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5720                 if (tso < 0) {
5721                         dev_kfree_skb_any(skb);
5722                         return NETDEV_TX_OK;
5723                 }
5724                 if (tso)
5725                         tx_flags |= IXGBE_TX_FLAGS_FSO;
5726 #endif /* IXGBE_FCOE */
5727         } else {
5728                 if (skb->protocol == htons(ETH_P_IP))
5729                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
5730                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5731                 if (tso < 0) {
5732                         dev_kfree_skb_any(skb);
5733                         return NETDEV_TX_OK;
5734                 }
5735
5736                 if (tso)
5737                         tx_flags |= IXGBE_TX_FLAGS_TSO;
5738                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5739                          (skb->ip_summed == CHECKSUM_PARTIAL))
5740                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
5741         }
5742
5743         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5744         if (count) {
5745                 /* add the ATR filter if ATR is on */
5746                 if (tx_ring->atr_sample_rate) {
5747                         ++tx_ring->atr_count;
5748                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5749                              test_bit(__IXGBE_FDIR_INIT_DONE,
5750                                       &tx_ring->reinit_state)) {
5751                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5752                                           tx_flags);
5753                                 tx_ring->atr_count = 0;
5754                         }
5755                 }
5756                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
5757                 txq->tx_bytes += skb->len;
5758                 txq->tx_packets++;
5759                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5760                                hdr_len);
5761                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5762
5763         } else {
5764                 dev_kfree_skb_any(skb);
5765                 tx_ring->tx_buffer_info[first].time_stamp = 0;
5766                 tx_ring->next_to_use = first;
5767         }
5768
5769         return NETDEV_TX_OK;
5770 }
5771
5772 /**
5773  * ixgbe_set_mac - Change the Ethernet Address of the NIC
5774  * @netdev: network interface device structure
5775  * @p: pointer to an address structure
5776  *
5777  * Returns 0 on success, negative on failure
5778  **/
5779 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5780 {
5781         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5782         struct ixgbe_hw *hw = &adapter->hw;
5783         struct sockaddr *addr = p;
5784
5785         if (!is_valid_ether_addr(addr->sa_data))
5786                 return -EADDRNOTAVAIL;
5787
5788         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5789         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5790
5791         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
5792                             IXGBE_RAH_AV);
5793
5794         return 0;
5795 }
5796
5797 static int
5798 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)