Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6
[linux-2.6.git] / drivers / net / ixgbe / ixgbe_ethtool.c
1 /*******************************************************************************
2
3   Intel 10 Gigabit PCI Express Linux driver
4   Copyright(c) 1999 - 2010 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* ethtool support for ixgbe */
29
30 #include <linux/types.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/vmalloc.h>
36 #include <linux/uaccess.h>
37
38 #include "ixgbe.h"
39
40
41 #define IXGBE_ALL_RAR_ENTRIES 16
42
43 enum {NETDEV_STATS, IXGBE_STATS};
44
45 struct ixgbe_stats {
46         char stat_string[ETH_GSTRING_LEN];
47         int type;
48         int sizeof_stat;
49         int stat_offset;
50 };
51
52 #define IXGBE_STAT(m)           IXGBE_STATS, \
53                                 sizeof(((struct ixgbe_adapter *)0)->m), \
54                                 offsetof(struct ixgbe_adapter, m)
55 #define IXGBE_NETDEV_STAT(m)    NETDEV_STATS, \
56                                 sizeof(((struct net_device *)0)->m), \
57                                 offsetof(struct net_device, m)
58
59 static struct ixgbe_stats ixgbe_gstrings_stats[] = {
60         {"rx_packets", IXGBE_NETDEV_STAT(stats.rx_packets)},
61         {"tx_packets", IXGBE_NETDEV_STAT(stats.tx_packets)},
62         {"rx_bytes", IXGBE_NETDEV_STAT(stats.rx_bytes)},
63         {"tx_bytes", IXGBE_NETDEV_STAT(stats.tx_bytes)},
64         {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
65         {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
66         {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
67         {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
68         {"lsc_int", IXGBE_STAT(lsc_int)},
69         {"tx_busy", IXGBE_STAT(tx_busy)},
70         {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
71         {"rx_errors", IXGBE_NETDEV_STAT(stats.rx_errors)},
72         {"tx_errors", IXGBE_NETDEV_STAT(stats.tx_errors)},
73         {"rx_dropped", IXGBE_NETDEV_STAT(stats.rx_dropped)},
74         {"tx_dropped", IXGBE_NETDEV_STAT(stats.tx_dropped)},
75         {"multicast", IXGBE_NETDEV_STAT(stats.multicast)},
76         {"broadcast", IXGBE_STAT(stats.bprc)},
77         {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
78         {"collisions", IXGBE_NETDEV_STAT(stats.collisions)},
79         {"rx_over_errors", IXGBE_NETDEV_STAT(stats.rx_over_errors)},
80         {"rx_crc_errors", IXGBE_NETDEV_STAT(stats.rx_crc_errors)},
81         {"rx_frame_errors", IXGBE_NETDEV_STAT(stats.rx_frame_errors)},
82         {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
83         {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
84         {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
85         {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
86         {"rx_fifo_errors", IXGBE_NETDEV_STAT(stats.rx_fifo_errors)},
87         {"rx_missed_errors", IXGBE_NETDEV_STAT(stats.rx_missed_errors)},
88         {"tx_aborted_errors", IXGBE_NETDEV_STAT(stats.tx_aborted_errors)},
89         {"tx_carrier_errors", IXGBE_NETDEV_STAT(stats.tx_carrier_errors)},
90         {"tx_fifo_errors", IXGBE_NETDEV_STAT(stats.tx_fifo_errors)},
91         {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(stats.tx_heartbeat_errors)},
92         {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
93         {"tx_restart_queue", IXGBE_STAT(restart_queue)},
94         {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
95         {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
96         {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
97         {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
98         {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
99         {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
100         {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
101         {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
102         {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
103         {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
104 #ifdef IXGBE_FCOE
105         {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
106         {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
107         {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
108         {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
109         {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
110         {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
111 #endif /* IXGBE_FCOE */
112 };
113
114 #define IXGBE_QUEUE_STATS_LEN \
115         ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
116         ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
117         (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
118 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
119 #define IXGBE_PB_STATS_LEN ( \
120                  (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
121                  IXGBE_FLAG_DCB_ENABLED) ? \
122                  (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
123                   sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
124                   sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
125                   sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
126                   / sizeof(u64) : 0)
127 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
128                          IXGBE_PB_STATS_LEN + \
129                          IXGBE_QUEUE_STATS_LEN)
130
131 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
132         "Register test  (offline)", "Eeprom test    (offline)",
133         "Interrupt test (offline)", "Loopback test  (offline)",
134         "Link test   (on/offline)"
135 };
136 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
137
138 static int ixgbe_get_settings(struct net_device *netdev,
139                               struct ethtool_cmd *ecmd)
140 {
141         struct ixgbe_adapter *adapter = netdev_priv(netdev);
142         struct ixgbe_hw *hw = &adapter->hw;
143         u32 link_speed = 0;
144         bool link_up;
145
146         ecmd->supported = SUPPORTED_10000baseT_Full;
147         ecmd->autoneg = AUTONEG_ENABLE;
148         ecmd->transceiver = XCVR_EXTERNAL;
149         if ((hw->phy.media_type == ixgbe_media_type_copper) ||
150             (hw->phy.multispeed_fiber)) {
151                 ecmd->supported |= (SUPPORTED_1000baseT_Full |
152                                     SUPPORTED_Autoneg);
153
154                 ecmd->advertising = ADVERTISED_Autoneg;
155                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
156                         ecmd->advertising |= ADVERTISED_10000baseT_Full;
157                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
158                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
159                 /*
160                  * It's possible that phy.autoneg_advertised may not be
161                  * set yet.  If so display what the default would be -
162                  * both 1G and 10G supported.
163                  */
164                 if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full |
165                                            ADVERTISED_10000baseT_Full)))
166                         ecmd->advertising |= (ADVERTISED_10000baseT_Full |
167                                               ADVERTISED_1000baseT_Full);
168
169                 if (hw->phy.media_type == ixgbe_media_type_copper) {
170                         ecmd->supported |= SUPPORTED_TP;
171                         ecmd->advertising |= ADVERTISED_TP;
172                         ecmd->port = PORT_TP;
173                 } else {
174                         ecmd->supported |= SUPPORTED_FIBRE;
175                         ecmd->advertising |= ADVERTISED_FIBRE;
176                         ecmd->port = PORT_FIBRE;
177                 }
178         } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
179                 /* Set as FIBRE until SERDES defined in kernel */
180                 if (hw->device_id == IXGBE_DEV_ID_82598_BX) {
181                         ecmd->supported = (SUPPORTED_1000baseT_Full |
182                                            SUPPORTED_FIBRE);
183                         ecmd->advertising = (ADVERTISED_1000baseT_Full |
184                                              ADVERTISED_FIBRE);
185                         ecmd->port = PORT_FIBRE;
186                         ecmd->autoneg = AUTONEG_DISABLE;
187                 } else {
188                         ecmd->supported |= (SUPPORTED_1000baseT_Full |
189                                             SUPPORTED_FIBRE);
190                         ecmd->advertising = (ADVERTISED_10000baseT_Full |
191                                              ADVERTISED_1000baseT_Full |
192                                              ADVERTISED_FIBRE);
193                         ecmd->port = PORT_FIBRE;
194                 }
195         } else {
196                 ecmd->supported |= SUPPORTED_FIBRE;
197                 ecmd->advertising = (ADVERTISED_10000baseT_Full |
198                                      ADVERTISED_FIBRE);
199                 ecmd->port = PORT_FIBRE;
200                 ecmd->autoneg = AUTONEG_DISABLE;
201         }
202
203         /* Get PHY type */
204         switch (adapter->hw.phy.type) {
205         case ixgbe_phy_tn:
206         case ixgbe_phy_cu_unknown:
207                 /* Copper 10G-BASET */
208                 ecmd->port = PORT_TP;
209                 break;
210         case ixgbe_phy_qt:
211                 ecmd->port = PORT_FIBRE;
212                 break;
213         case ixgbe_phy_nl:
214         case ixgbe_phy_tw_tyco:
215         case ixgbe_phy_tw_unknown:
216         case ixgbe_phy_sfp_ftl:
217         case ixgbe_phy_sfp_avago:
218         case ixgbe_phy_sfp_intel:
219         case ixgbe_phy_sfp_unknown:
220                 switch (adapter->hw.phy.sfp_type) {
221                 /* SFP+ devices, further checking needed */
222                 case ixgbe_sfp_type_da_cu:
223                 case ixgbe_sfp_type_da_cu_core0:
224                 case ixgbe_sfp_type_da_cu_core1:
225                         ecmd->port = PORT_DA;
226                         break;
227                 case ixgbe_sfp_type_sr:
228                 case ixgbe_sfp_type_lr:
229                 case ixgbe_sfp_type_srlr_core0:
230                 case ixgbe_sfp_type_srlr_core1:
231                         ecmd->port = PORT_FIBRE;
232                         break;
233                 case ixgbe_sfp_type_not_present:
234                         ecmd->port = PORT_NONE;
235                         break;
236                 case ixgbe_sfp_type_unknown:
237                 default:
238                         ecmd->port = PORT_OTHER;
239                         break;
240                 }
241                 break;
242         case ixgbe_phy_xaui:
243                 ecmd->port = PORT_NONE;
244                 break;
245         case ixgbe_phy_unknown:
246         case ixgbe_phy_generic:
247         case ixgbe_phy_sfp_unsupported:
248         default:
249                 ecmd->port = PORT_OTHER;
250                 break;
251         }
252
253         hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
254         if (link_up) {
255                 ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
256                                SPEED_10000 : SPEED_1000;
257                 ecmd->duplex = DUPLEX_FULL;
258         } else {
259                 ecmd->speed = -1;
260                 ecmd->duplex = -1;
261         }
262
263         return 0;
264 }
265
266 static int ixgbe_set_settings(struct net_device *netdev,
267                               struct ethtool_cmd *ecmd)
268 {
269         struct ixgbe_adapter *adapter = netdev_priv(netdev);
270         struct ixgbe_hw *hw = &adapter->hw;
271         u32 advertised, old;
272         s32 err = 0;
273
274         if ((hw->phy.media_type == ixgbe_media_type_copper) ||
275             (hw->phy.multispeed_fiber)) {
276                 /* 10000/copper and 1000/copper must autoneg
277                  * this function does not support any duplex forcing, but can
278                  * limit the advertising of the adapter to only 10000 or 1000 */
279                 if (ecmd->autoneg == AUTONEG_DISABLE)
280                         return -EINVAL;
281
282                 old = hw->phy.autoneg_advertised;
283                 advertised = 0;
284                 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
285                         advertised |= IXGBE_LINK_SPEED_10GB_FULL;
286
287                 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
288                         advertised |= IXGBE_LINK_SPEED_1GB_FULL;
289
290                 if (old == advertised)
291                         return err;
292                 /* this sets the link speed and restarts auto-neg */
293                 hw->mac.autotry_restart = true;
294                 err = hw->mac.ops.setup_link(hw, advertised, true, true);
295                 if (err) {
296                         DPRINTK(PROBE, INFO,
297                                 "setup link failed with code %d\n", err);
298                         hw->mac.ops.setup_link(hw, old, true, true);
299                 }
300         } else {
301                 /* in this case we currently only support 10Gb/FULL */
302                 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
303                     (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
304                     (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
305                         return -EINVAL;
306         }
307
308         return err;
309 }
310
311 static void ixgbe_get_pauseparam(struct net_device *netdev,
312                                  struct ethtool_pauseparam *pause)
313 {
314         struct ixgbe_adapter *adapter = netdev_priv(netdev);
315         struct ixgbe_hw *hw = &adapter->hw;
316
317         /*
318          * Flow Control Autoneg isn't on if
319          *  - we didn't ask for it OR
320          *  - it failed, we know this by tx & rx being off
321          */
322         if (hw->fc.disable_fc_autoneg ||
323             (hw->fc.current_mode == ixgbe_fc_none))
324                 pause->autoneg = 0;
325         else
326                 pause->autoneg = 1;
327
328 #ifdef CONFIG_DCB
329         if (hw->fc.current_mode == ixgbe_fc_pfc) {
330                 pause->rx_pause = 0;
331                 pause->tx_pause = 0;
332         }
333
334 #endif
335         if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
336                 pause->rx_pause = 1;
337         } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
338                 pause->tx_pause = 1;
339         } else if (hw->fc.current_mode == ixgbe_fc_full) {
340                 pause->rx_pause = 1;
341                 pause->tx_pause = 1;
342         }
343 }
344
345 static int ixgbe_set_pauseparam(struct net_device *netdev,
346                                 struct ethtool_pauseparam *pause)
347 {
348         struct ixgbe_adapter *adapter = netdev_priv(netdev);
349         struct ixgbe_hw *hw = &adapter->hw;
350         struct ixgbe_fc_info fc;
351
352 #ifdef CONFIG_DCB
353         if (adapter->dcb_cfg.pfc_mode_enable ||
354                 ((hw->mac.type == ixgbe_mac_82598EB) &&
355                 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
356                 return -EINVAL;
357
358 #endif
359
360         fc = hw->fc;
361
362         if (pause->autoneg != AUTONEG_ENABLE)
363                 fc.disable_fc_autoneg = true;
364         else
365                 fc.disable_fc_autoneg = false;
366
367         if (pause->rx_pause && pause->tx_pause)
368                 fc.requested_mode = ixgbe_fc_full;
369         else if (pause->rx_pause && !pause->tx_pause)
370                 fc.requested_mode = ixgbe_fc_rx_pause;
371         else if (!pause->rx_pause && pause->tx_pause)
372                 fc.requested_mode = ixgbe_fc_tx_pause;
373         else if (!pause->rx_pause && !pause->tx_pause)
374                 fc.requested_mode = ixgbe_fc_none;
375         else
376                 return -EINVAL;
377
378 #ifdef CONFIG_DCB
379         adapter->last_lfc_mode = fc.requested_mode;
380 #endif
381
382         /* if the thing changed then we'll update and use new autoneg */
383         if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
384                 hw->fc = fc;
385                 if (netif_running(netdev))
386                         ixgbe_reinit_locked(adapter);
387                 else
388                         ixgbe_reset(adapter);
389         }
390
391         return 0;
392 }
393
394 static u32 ixgbe_get_rx_csum(struct net_device *netdev)
395 {
396         struct ixgbe_adapter *adapter = netdev_priv(netdev);
397         return (adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED);
398 }
399
400 static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
401 {
402         struct ixgbe_adapter *adapter = netdev_priv(netdev);
403         if (data)
404                 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
405         else
406                 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
407
408         if (netif_running(netdev))
409                 ixgbe_reinit_locked(adapter);
410         else
411                 ixgbe_reset(adapter);
412
413         return 0;
414 }
415
416 static u32 ixgbe_get_tx_csum(struct net_device *netdev)
417 {
418         return (netdev->features & NETIF_F_IP_CSUM) != 0;
419 }
420
421 static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
422 {
423         struct ixgbe_adapter *adapter = netdev_priv(netdev);
424
425         if (data) {
426                 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
427                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
428                         netdev->features |= NETIF_F_SCTP_CSUM;
429         } else {
430                 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
431                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
432                         netdev->features &= ~NETIF_F_SCTP_CSUM;
433         }
434
435         return 0;
436 }
437
438 static int ixgbe_set_tso(struct net_device *netdev, u32 data)
439 {
440         if (data) {
441                 netdev->features |= NETIF_F_TSO;
442                 netdev->features |= NETIF_F_TSO6;
443         } else {
444                 netdev->features &= ~NETIF_F_TSO;
445                 netdev->features &= ~NETIF_F_TSO6;
446         }
447         return 0;
448 }
449
450 static u32 ixgbe_get_msglevel(struct net_device *netdev)
451 {
452         struct ixgbe_adapter *adapter = netdev_priv(netdev);
453         return adapter->msg_enable;
454 }
455
456 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
457 {
458         struct ixgbe_adapter *adapter = netdev_priv(netdev);
459         adapter->msg_enable = data;
460 }
461
462 static int ixgbe_get_regs_len(struct net_device *netdev)
463 {
464 #define IXGBE_REGS_LEN  1128
465         return IXGBE_REGS_LEN * sizeof(u32);
466 }
467
468 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
469
470 static void ixgbe_get_regs(struct net_device *netdev,
471                            struct ethtool_regs *regs, void *p)
472 {
473         struct ixgbe_adapter *adapter = netdev_priv(netdev);
474         struct ixgbe_hw *hw = &adapter->hw;
475         u32 *regs_buff = p;
476         u8 i;
477
478         memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
479
480         regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
481
482         /* General Registers */
483         regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
484         regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
485         regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
486         regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
487         regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
488         regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
489         regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
490         regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
491
492         /* NVM Register */
493         regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
494         regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
495         regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
496         regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
497         regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
498         regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
499         regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
500         regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
501         regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
502         regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
503
504         /* Interrupt */
505         /* don't read EICR because it can clear interrupt causes, instead
506          * read EICS which is a shadow but doesn't clear EICR */
507         regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
508         regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
509         regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
510         regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
511         regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
512         regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
513         regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
514         regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
515         regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
516         regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
517         regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
518         regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
519
520         /* Flow Control */
521         regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
522         regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
523         regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
524         regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
525         regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
526         for (i = 0; i < 8; i++)
527                 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
528         for (i = 0; i < 8; i++)
529                 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
530         regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
531         regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
532
533         /* Receive DMA */
534         for (i = 0; i < 64; i++)
535                 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
536         for (i = 0; i < 64; i++)
537                 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
538         for (i = 0; i < 64; i++)
539                 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
540         for (i = 0; i < 64; i++)
541                 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
542         for (i = 0; i < 64; i++)
543                 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
544         for (i = 0; i < 64; i++)
545                 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
546         for (i = 0; i < 16; i++)
547                 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
548         for (i = 0; i < 16; i++)
549                 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
550         regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
551         for (i = 0; i < 8; i++)
552                 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
553         regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
554         regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
555
556         /* Receive */
557         regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
558         regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
559         for (i = 0; i < 16; i++)
560                 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
561         for (i = 0; i < 16; i++)
562                 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
563         regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
564         regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
565         regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
566         regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
567         regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
568         regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
569         for (i = 0; i < 8; i++)
570                 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
571         for (i = 0; i < 8; i++)
572                 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
573         regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
574
575         /* Transmit */
576         for (i = 0; i < 32; i++)
577                 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
578         for (i = 0; i < 32; i++)
579                 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
580         for (i = 0; i < 32; i++)
581                 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
582         for (i = 0; i < 32; i++)
583                 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
584         for (i = 0; i < 32; i++)
585                 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
586         for (i = 0; i < 32; i++)
587                 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
588         for (i = 0; i < 32; i++)
589                 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
590         for (i = 0; i < 32; i++)
591                 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
592         regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
593         for (i = 0; i < 16; i++)
594                 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
595         regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
596         for (i = 0; i < 8; i++)
597                 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
598         regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
599
600         /* Wake Up */
601         regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
602         regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
603         regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
604         regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
605         regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
606         regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
607         regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
608         regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
609         regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
610
611         regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
612         regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
613         regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
614         regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
615         for (i = 0; i < 8; i++)
616                 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
617         for (i = 0; i < 8; i++)
618                 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
619         for (i = 0; i < 8; i++)
620                 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
621         for (i = 0; i < 8; i++)
622                 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
623         for (i = 0; i < 8; i++)
624                 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
625         for (i = 0; i < 8; i++)
626                 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
627
628         /* Statistics */
629         regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
630         regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
631         regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
632         regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
633         for (i = 0; i < 8; i++)
634                 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
635         regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
636         regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
637         regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
638         regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
639         regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
640         regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
641         regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
642         for (i = 0; i < 8; i++)
643                 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
644         for (i = 0; i < 8; i++)
645                 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
646         for (i = 0; i < 8; i++)
647                 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
648         for (i = 0; i < 8; i++)
649                 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
650         regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
651         regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
652         regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
653         regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
654         regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
655         regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
656         regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
657         regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
658         regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
659         regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
660         regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
661         regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
662         for (i = 0; i < 8; i++)
663                 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
664         regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
665         regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
666         regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
667         regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
668         regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
669         regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
670         regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
671         regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
672         regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
673         regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
674         regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
675         regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
676         regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
677         regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
678         regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
679         regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
680         regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
681         regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
682         regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
683         for (i = 0; i < 16; i++)
684                 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
685         for (i = 0; i < 16; i++)
686                 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
687         for (i = 0; i < 16; i++)
688                 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
689         for (i = 0; i < 16; i++)
690                 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
691
692         /* MAC */
693         regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
694         regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
695         regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
696         regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
697         regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
698         regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
699         regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
700         regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
701         regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
702         regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
703         regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
704         regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
705         regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
706         regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
707         regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
708         regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
709         regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
710         regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
711         regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
712         regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
713         regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
714         regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
715         regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
716         regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
717         regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
718         regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
719         regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
720         regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
721         regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
722         regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
723         regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
724         regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
725         regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
726
727         /* Diagnostic */
728         regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
729         for (i = 0; i < 8; i++)
730                 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
731         regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
732         for (i = 0; i < 4; i++)
733                 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
734         regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
735         regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
736         for (i = 0; i < 8; i++)
737                 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
738         regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
739         for (i = 0; i < 4; i++)
740                 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
741         regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
742         regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
743         regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
744         regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
745         regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
746         regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
747         regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
748         regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
749         regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
750         regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
751         regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
752         for (i = 0; i < 8; i++)
753                 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
754         regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
755         regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
756         regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
757         regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
758         regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
759         regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
760         regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
761         regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
762         regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
763 }
764
765 static int ixgbe_get_eeprom_len(struct net_device *netdev)
766 {
767         struct ixgbe_adapter *adapter = netdev_priv(netdev);
768         return adapter->hw.eeprom.word_size * 2;
769 }
770
771 static int ixgbe_get_eeprom(struct net_device *netdev,
772                             struct ethtool_eeprom *eeprom, u8 *bytes)
773 {
774         struct ixgbe_adapter *adapter = netdev_priv(netdev);
775         struct ixgbe_hw *hw = &adapter->hw;
776         u16 *eeprom_buff;
777         int first_word, last_word, eeprom_len;
778         int ret_val = 0;
779         u16 i;
780
781         if (eeprom->len == 0)
782                 return -EINVAL;
783
784         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
785
786         first_word = eeprom->offset >> 1;
787         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
788         eeprom_len = last_word - first_word + 1;
789
790         eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
791         if (!eeprom_buff)
792                 return -ENOMEM;
793
794         for (i = 0; i < eeprom_len; i++) {
795                 if ((ret_val = hw->eeprom.ops.read(hw, first_word + i,
796                     &eeprom_buff[i])))
797                         break;
798         }
799
800         /* Device's eeprom is always little-endian, word addressable */
801         for (i = 0; i < eeprom_len; i++)
802                 le16_to_cpus(&eeprom_buff[i]);
803
804         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
805         kfree(eeprom_buff);
806
807         return ret_val;
808 }
809
810 static void ixgbe_get_drvinfo(struct net_device *netdev,
811                               struct ethtool_drvinfo *drvinfo)
812 {
813         struct ixgbe_adapter *adapter = netdev_priv(netdev);
814         char firmware_version[32];
815
816         strncpy(drvinfo->driver, ixgbe_driver_name, 32);
817         strncpy(drvinfo->version, ixgbe_driver_version, 32);
818
819         sprintf(firmware_version, "%d.%d-%d",
820                 (adapter->eeprom_version & 0xF000) >> 12,
821                 (adapter->eeprom_version & 0x0FF0) >> 4,
822                 adapter->eeprom_version & 0x000F);
823
824         strncpy(drvinfo->fw_version, firmware_version, 32);
825         strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
826         drvinfo->n_stats = IXGBE_STATS_LEN;
827         drvinfo->testinfo_len = IXGBE_TEST_LEN;
828         drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
829 }
830
831 static void ixgbe_get_ringparam(struct net_device *netdev,
832                                 struct ethtool_ringparam *ring)
833 {
834         struct ixgbe_adapter *adapter = netdev_priv(netdev);
835         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
836         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
837
838         ring->rx_max_pending = IXGBE_MAX_RXD;
839         ring->tx_max_pending = IXGBE_MAX_TXD;
840         ring->rx_mini_max_pending = 0;
841         ring->rx_jumbo_max_pending = 0;
842         ring->rx_pending = rx_ring->count;
843         ring->tx_pending = tx_ring->count;
844         ring->rx_mini_pending = 0;
845         ring->rx_jumbo_pending = 0;
846 }
847
848 static int ixgbe_set_ringparam(struct net_device *netdev,
849                                struct ethtool_ringparam *ring)
850 {
851         struct ixgbe_adapter *adapter = netdev_priv(netdev);
852         struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
853         int i, err = 0;
854         u32 new_rx_count, new_tx_count;
855         bool need_update = false;
856
857         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
858                 return -EINVAL;
859
860         new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
861         new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
862         new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
863
864         new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
865         new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
866         new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
867
868         if ((new_tx_count == adapter->tx_ring[0]->count) &&
869             (new_rx_count == adapter->rx_ring[0]->count)) {
870                 /* nothing to do */
871                 return 0;
872         }
873
874         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
875                 msleep(1);
876
877         if (!netif_running(adapter->netdev)) {
878                 for (i = 0; i < adapter->num_tx_queues; i++)
879                         adapter->tx_ring[i]->count = new_tx_count;
880                 for (i = 0; i < adapter->num_rx_queues; i++)
881                         adapter->rx_ring[i]->count = new_rx_count;
882                 adapter->tx_ring_count = new_tx_count;
883                 adapter->rx_ring_count = new_rx_count;
884                 goto clear_reset;
885         }
886
887         temp_tx_ring = vmalloc(adapter->num_tx_queues * sizeof(struct ixgbe_ring));
888         if (!temp_tx_ring) {
889                 err = -ENOMEM;
890                 goto clear_reset;
891         }
892
893         if (new_tx_count != adapter->tx_ring_count) {
894                 for (i = 0; i < adapter->num_tx_queues; i++) {
895                         memcpy(&temp_tx_ring[i], adapter->tx_ring[i],
896                                sizeof(struct ixgbe_ring));
897                         temp_tx_ring[i].count = new_tx_count;
898                         err = ixgbe_setup_tx_resources(adapter,
899                                                        &temp_tx_ring[i]);
900                         if (err) {
901                                 while (i) {
902                                         i--;
903                                         ixgbe_free_tx_resources(adapter,
904                                                               &temp_tx_ring[i]);
905                                 }
906                                 goto clear_reset;
907                         }
908                 }
909                 need_update = true;
910         }
911
912         temp_rx_ring = vmalloc(adapter->num_rx_queues * sizeof(struct ixgbe_ring));
913         if (!temp_rx_ring) {
914                 err = -ENOMEM;
915                 goto err_setup;
916         }
917
918         if (new_rx_count != adapter->rx_ring_count) {
919                 for (i = 0; i < adapter->num_rx_queues; i++) {
920                         memcpy(&temp_rx_ring[i], adapter->rx_ring[i],
921                                sizeof(struct ixgbe_ring));
922                         temp_rx_ring[i].count = new_rx_count;
923                         err = ixgbe_setup_rx_resources(adapter,
924                                                        &temp_rx_ring[i]);
925                         if (err) {
926                                 while (i) {
927                                         i--;
928                                         ixgbe_free_rx_resources(adapter,
929                                                               &temp_rx_ring[i]);
930                                 }
931                                 goto err_setup;
932                         }
933                 }
934                 need_update = true;
935         }
936
937         /* if rings need to be updated, here's the place to do it in one shot */
938         if (need_update) {
939                 ixgbe_down(adapter);
940
941                 /* tx */
942                 if (new_tx_count != adapter->tx_ring_count) {
943                         for (i = 0; i < adapter->num_tx_queues; i++) {
944                                 ixgbe_free_tx_resources(adapter,
945                                                         adapter->tx_ring[i]);
946                                 memcpy(adapter->tx_ring[i], &temp_tx_ring[i],
947                                        sizeof(struct ixgbe_ring));
948                         }
949                         adapter->tx_ring_count = new_tx_count;
950                 }
951
952                 /* rx */
953                 if (new_rx_count != adapter->rx_ring_count) {
954                         for (i = 0; i < adapter->num_rx_queues; i++) {
955                                 ixgbe_free_rx_resources(adapter,
956                                                         adapter->rx_ring[i]);
957                                 memcpy(adapter->rx_ring[i], &temp_rx_ring[i],
958                                        sizeof(struct ixgbe_ring));
959                         }
960                         adapter->rx_ring_count = new_rx_count;
961                 }
962                 ixgbe_up(adapter);
963         }
964
965         vfree(temp_rx_ring);
966 err_setup:
967         vfree(temp_tx_ring);
968 clear_reset:
969         clear_bit(__IXGBE_RESETTING, &adapter->state);
970         return err;
971 }
972
973 static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
974 {
975         switch (sset) {
976         case ETH_SS_TEST:
977                 return IXGBE_TEST_LEN;
978         case ETH_SS_STATS:
979                 return IXGBE_STATS_LEN;
980         case ETH_SS_NTUPLE_FILTERS:
981                 return (ETHTOOL_MAX_NTUPLE_LIST_ENTRY *
982                         ETHTOOL_MAX_NTUPLE_STRING_PER_ENTRY);
983         default:
984                 return -EOPNOTSUPP;
985         }
986 }
987
988 static void ixgbe_get_ethtool_stats(struct net_device *netdev,
989                                     struct ethtool_stats *stats, u64 *data)
990 {
991         struct ixgbe_adapter *adapter = netdev_priv(netdev);
992         u64 *queue_stat;
993         int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64);
994         int j, k;
995         int i;
996         char *p = NULL;
997
998         ixgbe_update_stats(adapter);
999         dev_get_stats(netdev);
1000         for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1001                 switch (ixgbe_gstrings_stats[i].type) {
1002                 case NETDEV_STATS:
1003                         p = (char *) netdev +
1004                                         ixgbe_gstrings_stats[i].stat_offset;
1005                         break;
1006                 case IXGBE_STATS:
1007                         p = (char *) adapter +
1008                                         ixgbe_gstrings_stats[i].stat_offset;
1009                         break;
1010                 }
1011
1012                 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
1013                            sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1014         }
1015         for (j = 0; j < adapter->num_tx_queues; j++) {
1016                 queue_stat = (u64 *)&adapter->tx_ring[j]->stats;
1017                 for (k = 0; k < stat_count; k++)
1018                         data[i + k] = queue_stat[k];
1019                 i += k;
1020         }
1021         for (j = 0; j < adapter->num_rx_queues; j++) {
1022                 queue_stat = (u64 *)&adapter->rx_ring[j]->stats;
1023                 for (k = 0; k < stat_count; k++)
1024                         data[i + k] = queue_stat[k];
1025                 i += k;
1026         }
1027         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1028                 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
1029                         data[i++] = adapter->stats.pxontxc[j];
1030                         data[i++] = adapter->stats.pxofftxc[j];
1031                 }
1032                 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
1033                         data[i++] = adapter->stats.pxonrxc[j];
1034                         data[i++] = adapter->stats.pxoffrxc[j];
1035                 }
1036         }
1037 }
1038
1039 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
1040                               u8 *data)
1041 {
1042         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1043         char *p = (char *)data;
1044         int i;
1045
1046         switch (stringset) {
1047         case ETH_SS_TEST:
1048                 memcpy(data, *ixgbe_gstrings_test,
1049                        IXGBE_TEST_LEN * ETH_GSTRING_LEN);
1050                 break;
1051         case ETH_SS_STATS:
1052                 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1053                         memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1054                                ETH_GSTRING_LEN);
1055                         p += ETH_GSTRING_LEN;
1056                 }
1057                 for (i = 0; i < adapter->num_tx_queues; i++) {
1058                         sprintf(p, "tx_queue_%u_packets", i);
1059                         p += ETH_GSTRING_LEN;
1060                         sprintf(p, "tx_queue_%u_bytes", i);
1061                         p += ETH_GSTRING_LEN;
1062                 }
1063                 for (i = 0; i < adapter->num_rx_queues; i++) {
1064                         sprintf(p, "rx_queue_%u_packets", i);
1065                         p += ETH_GSTRING_LEN;
1066                         sprintf(p, "rx_queue_%u_bytes", i);
1067                         p += ETH_GSTRING_LEN;
1068                 }
1069                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1070                         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
1071                                 sprintf(p, "tx_pb_%u_pxon", i);
1072                                 p += ETH_GSTRING_LEN;
1073                                 sprintf(p, "tx_pb_%u_pxoff", i);
1074                                 p += ETH_GSTRING_LEN;
1075                         }
1076                         for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
1077                                 sprintf(p, "rx_pb_%u_pxon", i);
1078                                 p += ETH_GSTRING_LEN;
1079                                 sprintf(p, "rx_pb_%u_pxoff", i);
1080                                 p += ETH_GSTRING_LEN;
1081                         }
1082                 }
1083                 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1084                 break;
1085         }
1086 }
1087
1088 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1089 {
1090         struct ixgbe_hw *hw = &adapter->hw;
1091         bool link_up;
1092         u32 link_speed = 0;
1093         *data = 0;
1094
1095         hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1096         if (link_up)
1097                 return *data;
1098         else
1099                 *data = 1;
1100         return *data;
1101 }
1102
1103 /* ethtool register test data */
1104 struct ixgbe_reg_test {
1105         u16 reg;
1106         u8  array_len;
1107         u8  test_type;
1108         u32 mask;
1109         u32 write;
1110 };
1111
1112 /* In the hardware, registers are laid out either singly, in arrays
1113  * spaced 0x40 bytes apart, or in contiguous tables.  We assume
1114  * most tests take place on arrays or single registers (handled
1115  * as a single-element array) and special-case the tables.
1116  * Table tests are always pattern tests.
1117  *
1118  * We also make provision for some required setup steps by specifying
1119  * registers to be written without any read-back testing.
1120  */
1121
1122 #define PATTERN_TEST    1
1123 #define SET_READ_TEST   2
1124 #define WRITE_NO_TEST   3
1125 #define TABLE32_TEST    4
1126 #define TABLE64_TEST_LO 5
1127 #define TABLE64_TEST_HI 6
1128
1129 /* default 82599 register test */
1130 static struct ixgbe_reg_test reg_test_82599[] = {
1131         { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1132         { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1133         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1134         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1135         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1136         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1137         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1138         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1139         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1140         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1141         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1142         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1143         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1144         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1145         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1146         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1147         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1148         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1149         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1150         { 0, 0, 0, 0 }
1151 };
1152
1153 /* default 82598 register test */
1154 static struct ixgbe_reg_test reg_test_82598[] = {
1155         { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1156         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1157         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1158         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1159         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1160         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1161         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1162         /* Enable all four RX queues before testing. */
1163         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1164         /* RDH is read-only for 82598, only test RDT. */
1165         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1166         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1167         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1168         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1169         { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1170         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1171         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1172         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1173         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1174         { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1175         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1176         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1177         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1178         { 0, 0, 0, 0 }
1179 };
1180
1181 #define REG_PATTERN_TEST(R, M, W)                                             \
1182 {                                                                             \
1183         u32 pat, val, before;                                                 \
1184         const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
1185         for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {                       \
1186                 before = readl(adapter->hw.hw_addr + R);                      \
1187                 writel((_test[pat] & W), (adapter->hw.hw_addr + R));          \
1188                 val = readl(adapter->hw.hw_addr + R);                         \
1189                 if (val != (_test[pat] & W & M)) {                            \
1190                         DPRINTK(DRV, ERR, "pattern test reg %04X failed: got "\
1191                                           "0x%08X expected 0x%08X\n",         \
1192                                 R, val, (_test[pat] & W & M));                \
1193                         *data = R;                                            \
1194                         writel(before, adapter->hw.hw_addr + R);              \
1195                         return 1;                                             \
1196                 }                                                             \
1197                 writel(before, adapter->hw.hw_addr + R);                      \
1198         }                                                                     \
1199 }
1200
1201 #define REG_SET_AND_CHECK(R, M, W)                                            \
1202 {                                                                             \
1203         u32 val, before;                                                      \
1204         before = readl(adapter->hw.hw_addr + R);                              \
1205         writel((W & M), (adapter->hw.hw_addr + R));                           \
1206         val = readl(adapter->hw.hw_addr + R);                                 \
1207         if ((W & M) != (val & M)) {                                           \
1208                 DPRINTK(DRV, ERR, "set/check reg %04X test failed: got 0x%08X "\
1209                                  "expected 0x%08X\n", R, (val & M), (W & M)); \
1210                 *data = R;                                                    \
1211                 writel(before, (adapter->hw.hw_addr + R));                    \
1212                 return 1;                                                     \
1213         }                                                                     \
1214         writel(before, (adapter->hw.hw_addr + R));                            \
1215 }
1216
1217 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1218 {
1219         struct ixgbe_reg_test *test;
1220         u32 value, before, after;
1221         u32 i, toggle;
1222
1223         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1224                 toggle = 0x7FFFF30F;
1225                 test = reg_test_82599;
1226         } else {
1227                 toggle = 0x7FFFF3FF;
1228                 test = reg_test_82598;
1229         }
1230
1231         /*
1232          * Because the status register is such a special case,
1233          * we handle it separately from the rest of the register
1234          * tests.  Some bits are read-only, some toggle, and some
1235          * are writeable on newer MACs.
1236          */
1237         before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1238         value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1239         IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1240         after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1241         if (value != after) {
1242                 DPRINTK(DRV, ERR, "failed STATUS register test got: "
1243                         "0x%08X expected: 0x%08X\n", after, value);
1244                 *data = 1;
1245                 return 1;
1246         }
1247         /* restore previous status */
1248         IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1249
1250         /*
1251          * Perform the remainder of the register test, looping through
1252          * the test table until we either fail or reach the null entry.
1253          */
1254         while (test->reg) {
1255                 for (i = 0; i < test->array_len; i++) {
1256                         switch (test->test_type) {
1257                         case PATTERN_TEST:
1258                                 REG_PATTERN_TEST(test->reg + (i * 0x40),
1259                                                 test->mask,
1260                                                 test->write);
1261                                 break;
1262                         case SET_READ_TEST:
1263                                 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1264                                                 test->mask,
1265                                                 test->write);
1266                                 break;
1267                         case WRITE_NO_TEST:
1268                                 writel(test->write,
1269                                        (adapter->hw.hw_addr + test->reg)
1270                                        + (i * 0x40));
1271                                 break;
1272                         case TABLE32_TEST:
1273                                 REG_PATTERN_TEST(test->reg + (i * 4),
1274                                                 test->mask,
1275                                                 test->write);
1276                                 break;
1277                         case TABLE64_TEST_LO:
1278                                 REG_PATTERN_TEST(test->reg + (i * 8),
1279                                                 test->mask,
1280                                                 test->write);
1281                                 break;
1282                         case TABLE64_TEST_HI:
1283                                 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1284                                                 test->mask,
1285                                                 test->write);
1286                                 break;
1287                         }
1288                 }
1289                 test++;
1290         }
1291
1292         *data = 0;
1293         return 0;
1294 }
1295
1296 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1297 {
1298         struct ixgbe_hw *hw = &adapter->hw;
1299         if (hw->eeprom.ops.validate_checksum(hw, NULL))
1300                 *data = 1;
1301         else
1302                 *data = 0;
1303         return *data;
1304 }
1305
1306 static irqreturn_t ixgbe_test_intr(int irq, void *data)
1307 {
1308         struct net_device *netdev = (struct net_device *) data;
1309         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1310
1311         adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1312
1313         return IRQ_HANDLED;
1314 }
1315
1316 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1317 {
1318         struct net_device *netdev = adapter->netdev;
1319         u32 mask, i = 0, shared_int = true;
1320         u32 irq = adapter->pdev->irq;
1321
1322         *data = 0;
1323
1324         /* Hook up test interrupt handler just for this test */
1325         if (adapter->msix_entries) {
1326                 /* NOTE: we don't test MSI-X interrupts here, yet */
1327                 return 0;
1328         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1329                 shared_int = false;
1330                 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
1331                                 netdev)) {
1332                         *data = 1;
1333                         return -1;
1334                 }
1335         } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
1336                                 netdev->name, netdev)) {
1337                 shared_int = false;
1338         } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
1339                                netdev->name, netdev)) {
1340                 *data = 1;
1341                 return -1;
1342         }
1343         DPRINTK(HW, INFO, "testing %s interrupt\n",
1344                 (shared_int ? "shared" : "unshared"));
1345
1346         /* Disable all the interrupts */
1347         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1348         msleep(10);
1349
1350         /* Test each interrupt */
1351         for (; i < 10; i++) {
1352                 /* Interrupt to test */
1353                 mask = 1 << i;
1354
1355                 if (!shared_int) {
1356                         /*
1357                          * Disable the interrupts to be reported in
1358                          * the cause register and then force the same
1359                          * interrupt and see if one gets posted.  If
1360                          * an interrupt was posted to the bus, the
1361                          * test failed.
1362                          */
1363                         adapter->test_icr = 0;
1364                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1365                                         ~mask & 0x00007FFF);
1366                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1367                                         ~mask & 0x00007FFF);
1368                         msleep(10);
1369
1370                         if (adapter->test_icr & mask) {
1371                                 *data = 3;
1372                                 break;
1373                         }
1374                 }
1375
1376                 /*
1377                  * Enable the interrupt to be reported in the cause
1378                  * register and then force the same interrupt and see
1379                  * if one gets posted.  If an interrupt was not posted
1380                  * to the bus, the test failed.
1381                  */
1382                 adapter->test_icr = 0;
1383                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1384                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1385                 msleep(10);
1386
1387                 if (!(adapter->test_icr &mask)) {
1388                         *data = 4;
1389                         break;
1390                 }
1391
1392                 if (!shared_int) {
1393                         /*
1394                          * Disable the other interrupts to be reported in
1395                          * the cause register and then force the other
1396                          * interrupts and see if any get posted.  If
1397                          * an interrupt was posted to the bus, the
1398                          * test failed.
1399                          */
1400                         adapter->test_icr = 0;
1401                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1402                                         ~mask & 0x00007FFF);
1403                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1404                                         ~mask & 0x00007FFF);
1405                         msleep(10);
1406
1407                         if (adapter->test_icr) {
1408                                 *data = 5;
1409                                 break;
1410                         }
1411                 }
1412         }
1413
1414         /* Disable all the interrupts */
1415         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1416         msleep(10);
1417
1418         /* Unhook test interrupt handler */
1419         free_irq(irq, netdev);
1420
1421         return *data;
1422 }
1423
1424 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1425 {
1426         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1427         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1428         struct ixgbe_hw *hw = &adapter->hw;
1429         struct pci_dev *pdev = adapter->pdev;
1430         u32 reg_ctl;
1431         int i;
1432
1433         /* shut down the DMA engines now so they can be reinitialized later */
1434
1435         /* first Rx */
1436         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1437         reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1438         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
1439         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(0));
1440         reg_ctl &= ~IXGBE_RXDCTL_ENABLE;
1441         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(0), reg_ctl);
1442
1443         /* now Tx */
1444         reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(0));
1445         reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1446         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(0), reg_ctl);
1447         if (hw->mac.type == ixgbe_mac_82599EB) {
1448                 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1449                 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1450                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1451         }
1452
1453         ixgbe_reset(adapter);
1454
1455         if (tx_ring->desc && tx_ring->tx_buffer_info) {
1456                 for (i = 0; i < tx_ring->count; i++) {
1457                         struct ixgbe_tx_buffer *buf =
1458                                         &(tx_ring->tx_buffer_info[i]);
1459                         if (buf->dma)
1460                                 pci_unmap_single(pdev, buf->dma, buf->length,
1461                                                  PCI_DMA_TODEVICE);
1462                         if (buf->skb)
1463                                 dev_kfree_skb(buf->skb);
1464                 }
1465         }
1466
1467         if (rx_ring->desc && rx_ring->rx_buffer_info) {
1468                 for (i = 0; i < rx_ring->count; i++) {
1469                         struct ixgbe_rx_buffer *buf =
1470                                         &(rx_ring->rx_buffer_info[i]);
1471                         if (buf->dma)
1472                                 pci_unmap_single(pdev, buf->dma,
1473                                                  IXGBE_RXBUFFER_2048,
1474                                                  PCI_DMA_FROMDEVICE);
1475                         if (buf->skb)
1476                                 dev_kfree_skb(buf->skb);
1477                 }
1478         }
1479
1480         if (tx_ring->desc) {
1481                 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1482                                     tx_ring->dma);
1483                 tx_ring->desc = NULL;
1484         }
1485         if (rx_ring->desc) {
1486                 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1487                                     rx_ring->dma);
1488                 rx_ring->desc = NULL;
1489         }
1490
1491         kfree(tx_ring->tx_buffer_info);
1492         tx_ring->tx_buffer_info = NULL;
1493         kfree(rx_ring->rx_buffer_info);
1494         rx_ring->rx_buffer_info = NULL;
1495
1496         return;
1497 }
1498
1499 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1500 {
1501         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1502         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1503         struct pci_dev *pdev = adapter->pdev;
1504         u32 rctl, reg_data;
1505         int i, ret_val;
1506
1507         /* Setup Tx descriptor ring and Tx buffers */
1508
1509         if (!tx_ring->count)
1510                 tx_ring->count = IXGBE_DEFAULT_TXD;
1511
1512         tx_ring->tx_buffer_info = kcalloc(tx_ring->count,
1513                                           sizeof(struct ixgbe_tx_buffer),
1514                                           GFP_KERNEL);
1515         if (!(tx_ring->tx_buffer_info)) {
1516                 ret_val = 1;
1517                 goto err_nomem;
1518         }
1519
1520         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
1521         tx_ring->size = ALIGN(tx_ring->size, 4096);
1522         if (!(tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1523                                                    &tx_ring->dma))) {
1524                 ret_val = 2;
1525                 goto err_nomem;
1526         }
1527         tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1528
1529         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAL(0),
1530                         ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1531         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAH(0),
1532                         ((u64) tx_ring->dma >> 32));
1533         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDLEN(0),
1534                         tx_ring->count * sizeof(union ixgbe_adv_tx_desc));
1535         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDH(0), 0);
1536         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), 0);
1537
1538         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1539         reg_data |= IXGBE_HLREG0_TXPADEN;
1540         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1541
1542         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1543                 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1544                 reg_data |= IXGBE_DMATXCTL_TE;
1545                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1546         }
1547         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_TXDCTL(0));
1548         reg_data |= IXGBE_TXDCTL_ENABLE;
1549         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TXDCTL(0), reg_data);
1550
1551         for (i = 0; i < tx_ring->count; i++) {
1552                 union ixgbe_adv_tx_desc *desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
1553                 struct sk_buff *skb;
1554                 unsigned int size = 1024;
1555
1556                 skb = alloc_skb(size, GFP_KERNEL);
1557                 if (!skb) {
1558                         ret_val = 3;
1559                         goto err_nomem;
1560                 }
1561                 skb_put(skb, size);
1562                 tx_ring->tx_buffer_info[i].skb = skb;
1563                 tx_ring->tx_buffer_info[i].length = skb->len;
1564                 tx_ring->tx_buffer_info[i].dma =
1565                         pci_map_single(pdev, skb->data, skb->len,
1566                                        PCI_DMA_TODEVICE);
1567                 desc->read.buffer_addr =
1568                                     cpu_to_le64(tx_ring->tx_buffer_info[i].dma);
1569                 desc->read.cmd_type_len = cpu_to_le32(skb->len);
1570                 desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD_EOP |
1571                                                        IXGBE_TXD_CMD_IFCS |
1572                                                        IXGBE_TXD_CMD_RS);
1573                 desc->read.olinfo_status = 0;
1574                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1575                         desc->read.olinfo_status |=
1576                                         (skb->len << IXGBE_ADVTXD_PAYLEN_SHIFT);
1577
1578         }
1579
1580         /* Setup Rx Descriptor ring and Rx buffers */
1581
1582         if (!rx_ring->count)
1583                 rx_ring->count = IXGBE_DEFAULT_RXD;
1584
1585         rx_ring->rx_buffer_info = kcalloc(rx_ring->count,
1586                                           sizeof(struct ixgbe_rx_buffer),
1587                                           GFP_KERNEL);
1588         if (!(rx_ring->rx_buffer_info)) {
1589                 ret_val = 4;
1590                 goto err_nomem;
1591         }
1592
1593         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
1594         rx_ring->size = ALIGN(rx_ring->size, 4096);
1595         if (!(rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1596                                                    &rx_ring->dma))) {
1597                 ret_val = 5;
1598                 goto err_nomem;
1599         }
1600         rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1601
1602         rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1603         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
1604         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAL(0),
1605                         ((u64)rx_ring->dma & 0xFFFFFFFF));
1606         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAH(0),
1607                         ((u64) rx_ring->dma >> 32));
1608         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDLEN(0), rx_ring->size);
1609         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDH(0), 0);
1610         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), 0);
1611
1612         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1613         reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1614         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1615
1616         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1617         reg_data &= ~IXGBE_HLREG0_LPBK;
1618         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1619
1620         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RDRXCTL);
1621 #define IXGBE_RDRXCTL_RDMTS_MASK    0x00000003 /* Receive Descriptor Minimum
1622                                                   Threshold Size mask */
1623         reg_data &= ~IXGBE_RDRXCTL_RDMTS_MASK;
1624         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDRXCTL, reg_data);
1625
1626         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MCSTCTRL);
1627 #define IXGBE_MCSTCTRL_MO_MASK      0x00000003 /* Multicast Offset mask */
1628         reg_data &= ~IXGBE_MCSTCTRL_MO_MASK;
1629         reg_data |= adapter->hw.mac.mc_filter_type;
1630         IXGBE_WRITE_REG(&adapter->hw, IXGBE_MCSTCTRL, reg_data);
1631
1632         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(0));
1633         reg_data |= IXGBE_RXDCTL_ENABLE;
1634         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(0), reg_data);
1635         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1636                 int j = adapter->rx_ring[0]->reg_idx;
1637                 u32 k;
1638                 for (k = 0; k < 10; k++) {
1639                         if (IXGBE_READ_REG(&adapter->hw,
1640                                            IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
1641                                 break;
1642                         else
1643                                 msleep(1);
1644                 }
1645         }
1646
1647         rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1648         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1649
1650         for (i = 0; i < rx_ring->count; i++) {
1651                 union ixgbe_adv_rx_desc *rx_desc =
1652                                                  IXGBE_RX_DESC_ADV(*rx_ring, i);
1653                 struct sk_buff *skb;
1654
1655                 skb = alloc_skb(IXGBE_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL);
1656                 if (!skb) {
1657                         ret_val = 6;
1658                         goto err_nomem;
1659                 }
1660                 skb_reserve(skb, NET_IP_ALIGN);
1661                 rx_ring->rx_buffer_info[i].skb = skb;
1662                 rx_ring->rx_buffer_info[i].dma =
1663                         pci_map_single(pdev, skb->data, IXGBE_RXBUFFER_2048,
1664                                        PCI_DMA_FROMDEVICE);
1665                 rx_desc->read.pkt_addr =
1666                                 cpu_to_le64(rx_ring->rx_buffer_info[i].dma);
1667                 memset(skb->data, 0x00, skb->len);
1668         }
1669
1670         return 0;
1671
1672 err_nomem:
1673         ixgbe_free_desc_rings(adapter);
1674         return ret_val;
1675 }
1676
1677 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1678 {
1679         struct ixgbe_hw *hw = &adapter->hw;
1680         u32 reg_data;
1681
1682         /* right now we only support MAC loopback in the driver */
1683
1684         /* Setup MAC loopback */
1685         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1686         reg_data |= IXGBE_HLREG0_LPBK;
1687         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1688
1689         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1690         reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1691         reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1692         IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
1693
1694         /* Disable Atlas Tx lanes; re-enabled in reset path */
1695         if (hw->mac.type == ixgbe_mac_82598EB) {
1696                 u8 atlas;
1697
1698                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1699                 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1700                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1701
1702                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1703                 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1704                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1705
1706                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1707                 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1708                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1709
1710                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1711                 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1712                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1713         }
1714
1715         return 0;
1716 }
1717
1718 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1719 {
1720         u32 reg_data;
1721
1722         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1723         reg_data &= ~IXGBE_HLREG0_LPBK;
1724         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1725 }
1726
1727 static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1728                                       unsigned int frame_size)
1729 {
1730         memset(skb->data, 0xFF, frame_size);
1731         frame_size &= ~1;
1732         memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1733         memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1734         memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1735 }
1736
1737 static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1738                                     unsigned int frame_size)
1739 {
1740         frame_size &= ~1;
1741         if (*(skb->data + 3) == 0xFF) {
1742                 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1743                     (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1744                         return 0;
1745                 }
1746         }
1747         return 13;
1748 }
1749
1750 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1751 {
1752         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1753         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1754         struct pci_dev *pdev = adapter->pdev;
1755         int i, j, k, l, lc, good_cnt, ret_val = 0;
1756         unsigned long time;
1757
1758         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), rx_ring->count - 1);
1759
1760         /*
1761          * Calculate the loop count based on the largest descriptor ring
1762          * The idea is to wrap the largest ring a number of times using 64
1763          * send/receive pairs during each loop
1764          */
1765
1766         if (rx_ring->count <= tx_ring->count)
1767                 lc = ((tx_ring->count / 64) * 2) + 1;
1768         else
1769                 lc = ((rx_ring->count / 64) * 2) + 1;
1770
1771         k = l = 0;
1772         for (j = 0; j <= lc; j++) {
1773                 for (i = 0; i < 64; i++) {
1774                         ixgbe_create_lbtest_frame(
1775                                         tx_ring->tx_buffer_info[k].skb,
1776                                         1024);
1777                         pci_dma_sync_single_for_device(pdev,
1778                                 tx_ring->tx_buffer_info[k].dma,
1779                                 tx_ring->tx_buffer_info[k].length,
1780                                 PCI_DMA_TODEVICE);
1781                         if (unlikely(++k == tx_ring->count))
1782                                 k = 0;
1783                 }
1784                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), k);
1785                 msleep(200);
1786                 /* set the start time for the receive */
1787                 time = jiffies;
1788                 good_cnt = 0;
1789                 do {
1790                         /* receive the sent packets */
1791                         pci_dma_sync_single_for_cpu(pdev,
1792                                         rx_ring->rx_buffer_info[l].dma,
1793                                         IXGBE_RXBUFFER_2048,
1794                                         PCI_DMA_FROMDEVICE);
1795                         ret_val = ixgbe_check_lbtest_frame(
1796                                         rx_ring->rx_buffer_info[l].skb, 1024);
1797                         if (!ret_val)
1798                                 good_cnt++;
1799                         if (++l == rx_ring->count)
1800                                 l = 0;
1801                         /*
1802                          * time + 20 msecs (200 msecs on 2.4) is more than
1803                          * enough time to complete the receives, if it's
1804                          * exceeded, break and error off
1805                          */
1806                 } while (good_cnt < 64 && jiffies < (time + 20));
1807                 if (good_cnt != 64) {
1808                         /* ret_val is the same as mis-compare */
1809                         ret_val = 13;
1810                         break;
1811                 }
1812                 if (jiffies >= (time + 20)) {
1813                         /* Error code for time out error */
1814                         ret_val = 14;
1815                         break;
1816                 }
1817         }
1818
1819         return ret_val;
1820 }
1821
1822 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1823 {
1824         *data = ixgbe_setup_desc_rings(adapter);
1825         if (*data)
1826                 goto out;
1827         *data = ixgbe_setup_loopback_test(adapter);
1828         if (*data)
1829                 goto err_loopback;
1830         *data = ixgbe_run_loopback_test(adapter);
1831         ixgbe_loopback_cleanup(adapter);
1832
1833 err_loopback:
1834         ixgbe_free_desc_rings(adapter);
1835 out:
1836         return *data;
1837 }
1838
1839 static void ixgbe_diag_test(struct net_device *netdev,
1840                             struct ethtool_test *eth_test, u64 *data)
1841 {
1842         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1843         bool if_running = netif_running(netdev);
1844
1845         set_bit(__IXGBE_TESTING, &adapter->state);
1846         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1847                 /* Offline tests */
1848
1849                 DPRINTK(HW, INFO, "offline testing starting\n");
1850
1851                 /* Link test performed before hardware reset so autoneg doesn't
1852                  * interfere with test result */
1853                 if (ixgbe_link_test(adapter, &data[4]))
1854                         eth_test->flags |= ETH_TEST_FL_FAILED;
1855
1856                 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1857                         int i;
1858                         for (i = 0; i < adapter->num_vfs; i++) {
1859                                 if (adapter->vfinfo[i].clear_to_send) {
1860                                         netdev_warn(netdev, "%s",
1861                                                     "offline diagnostic is not "
1862                                                     "supported when VFs are "
1863                                                     "present\n");
1864                                         data[0] = 1;
1865                                         data[1] = 1;
1866                                         data[2] = 1;
1867                                         data[3] = 1;
1868                                         eth_test->flags |= ETH_TEST_FL_FAILED;
1869                                         clear_bit(__IXGBE_TESTING,
1870                                                   &adapter->state);
1871                                         goto skip_ol_tests;
1872                                 }
1873                         }
1874                 }
1875
1876                 if (if_running)
1877                         /* indicate we're in test mode */
1878                         dev_close(netdev);
1879                 else
1880                         ixgbe_reset(adapter);
1881
1882                 DPRINTK(HW, INFO, "register testing starting\n");
1883                 if (ixgbe_reg_test(adapter, &data[0]))
1884                         eth_test->flags |= ETH_TEST_FL_FAILED;
1885
1886                 ixgbe_reset(adapter);
1887                 DPRINTK(HW, INFO, "eeprom testing starting\n");
1888                 if (ixgbe_eeprom_test(adapter, &data[1]))
1889                         eth_test->flags |= ETH_TEST_FL_FAILED;
1890
1891                 ixgbe_reset(adapter);
1892                 DPRINTK(HW, INFO, "interrupt testing starting\n");
1893                 if (ixgbe_intr_test(adapter, &data[2]))
1894                         eth_test->flags |= ETH_TEST_FL_FAILED;
1895
1896                 /* If SRIOV or VMDq is enabled then skip MAC
1897                  * loopback diagnostic. */
1898                 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
1899                                       IXGBE_FLAG_VMDQ_ENABLED)) {
1900                         DPRINTK(HW, INFO, "Skip MAC loopback diagnostic in VT "
1901                                 "mode\n");
1902                         data[3] = 0;
1903                         goto skip_loopback;
1904                 }
1905
1906                 ixgbe_reset(adapter);
1907                 DPRINTK(HW, INFO, "loopback testing starting\n");
1908                 if (ixgbe_loopback_test(adapter, &data[3]))
1909                         eth_test->flags |= ETH_TEST_FL_FAILED;
1910
1911 skip_loopback:
1912                 ixgbe_reset(adapter);
1913
1914                 clear_bit(__IXGBE_TESTING, &adapter->state);
1915                 if (if_running)
1916                         dev_open(netdev);
1917         } else {
1918                 DPRINTK(HW, INFO, "online testing starting\n");
1919                 /* Online tests */
1920                 if (ixgbe_link_test(adapter, &data[4]))
1921                         eth_test->flags |= ETH_TEST_FL_FAILED;
1922
1923                 /* Online tests aren't run; pass by default */
1924                 data[0] = 0;
1925                 data[1] = 0;
1926                 data[2] = 0;
1927                 data[3] = 0;
1928
1929                 clear_bit(__IXGBE_TESTING, &adapter->state);
1930         }
1931 skip_ol_tests:
1932         msleep_interruptible(4 * 1000);
1933 }
1934
1935 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1936                                struct ethtool_wolinfo *wol)
1937 {
1938         struct ixgbe_hw *hw = &adapter->hw;
1939         int retval = 1;
1940
1941         switch(hw->device_id) {
1942         case IXGBE_DEV_ID_82599_KX4:
1943                 retval = 0;
1944                 break;
1945         default:
1946                 wol->supported = 0;
1947         }
1948
1949         return retval;
1950 }
1951
1952 static void ixgbe_get_wol(struct net_device *netdev,
1953                           struct ethtool_wolinfo *wol)
1954 {
1955         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1956
1957         wol->supported = WAKE_UCAST | WAKE_MCAST |
1958                          WAKE_BCAST | WAKE_MAGIC;
1959         wol->wolopts = 0;
1960
1961         if (ixgbe_wol_exclusion(adapter, wol) ||
1962             !device_can_wakeup(&adapter->pdev->dev))
1963                 return;
1964
1965         if (adapter->wol & IXGBE_WUFC_EX)
1966                 wol->wolopts |= WAKE_UCAST;
1967         if (adapter->wol & IXGBE_WUFC_MC)
1968                 wol->wolopts |= WAKE_MCAST;
1969         if (adapter->wol & IXGBE_WUFC_BC)
1970                 wol->wolopts |= WAKE_BCAST;
1971         if (adapter->wol & IXGBE_WUFC_MAG)
1972                 wol->wolopts |= WAKE_MAGIC;
1973
1974         return;
1975 }
1976
1977 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1978 {
1979         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1980
1981         if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1982                 return -EOPNOTSUPP;
1983
1984         if (ixgbe_wol_exclusion(adapter, wol))
1985                 return wol->wolopts ? -EOPNOTSUPP : 0;
1986
1987         adapter->wol = 0;
1988
1989         if (wol->wolopts & WAKE_UCAST)
1990                 adapter->wol |= IXGBE_WUFC_EX;
1991         if (wol->wolopts & WAKE_MCAST)
1992                 adapter->wol |= IXGBE_WUFC_MC;
1993         if (wol->wolopts & WAKE_BCAST)
1994                 adapter->wol |= IXGBE_WUFC_BC;
1995         if (wol->wolopts & WAKE_MAGIC)
1996                 adapter->wol |= IXGBE_WUFC_MAG;
1997
1998         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1999
2000         return 0;
2001 }
2002
2003 static int ixgbe_nway_reset(struct net_device *netdev)
2004 {
2005         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2006
2007         if (netif_running(netdev))
2008                 ixgbe_reinit_locked(adapter);
2009
2010         return 0;
2011 }
2012
2013 static int ixgbe_phys_id(struct net_device *netdev, u32 data)
2014 {
2015         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2016         struct ixgbe_hw *hw = &adapter->hw;
2017         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2018         u32 i;
2019
2020         if (!data || data > 300)
2021                 data = 300;
2022
2023         for (i = 0; i < (data * 1000); i += 400) {
2024                 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
2025                 msleep_interruptible(200);
2026                 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
2027                 msleep_interruptible(200);
2028         }
2029
2030         /* Restore LED settings */
2031         IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg);
2032
2033         return 0;
2034 }
2035
2036 static int ixgbe_get_coalesce(struct net_device *netdev,
2037                               struct ethtool_coalesce *ec)
2038 {
2039         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2040
2041         ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0]->work_limit;
2042
2043         /* only valid if in constant ITR mode */
2044         switch (adapter->rx_itr_setting) {
2045         case 0:
2046                 /* throttling disabled */
2047                 ec->rx_coalesce_usecs = 0;
2048                 break;
2049         case 1:
2050                 /* dynamic ITR mode */
2051                 ec->rx_coalesce_usecs = 1;
2052                 break;
2053         default:
2054                 /* fixed interrupt rate mode */
2055                 ec->rx_coalesce_usecs = 1000000/adapter->rx_eitr_param;
2056                 break;
2057         }
2058
2059         /* if in mixed tx/rx queues per vector mode, report only rx settings */
2060         if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count)
2061                 return 0;
2062
2063         /* only valid if in constant ITR mode */
2064         switch (adapter->tx_itr_setting) {
2065         case 0:
2066                 /* throttling disabled */
2067                 ec->tx_coalesce_usecs = 0;
2068                 break;
2069         case 1:
2070                 /* dynamic ITR mode */
2071                 ec->tx_coalesce_usecs = 1;
2072                 break;
2073         default:
2074                 ec->tx_coalesce_usecs = 1000000/adapter->tx_eitr_param;
2075                 break;
2076         }
2077
2078         return 0;
2079 }
2080
2081 static int ixgbe_set_coalesce(struct net_device *netdev,
2082                               struct ethtool_coalesce *ec)
2083 {
2084         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2085         struct ixgbe_q_vector *q_vector;
2086         int i;
2087
2088         /* don't accept tx specific changes if we've got mixed RxTx vectors */
2089         if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count
2090            && ec->tx_coalesce_usecs)
2091                 return -EINVAL;
2092
2093         if (ec->tx_max_coalesced_frames_irq)
2094                 adapter->tx_ring[0]->work_limit = ec->tx_max_coalesced_frames_irq;
2095
2096         if (ec->rx_coalesce_usecs > 1) {
2097                 /* check the limits */
2098                 if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2099                     (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2100                         return -EINVAL;
2101
2102                 /* store the value in ints/second */
2103                 adapter->rx_eitr_param = 1000000/ec->rx_coalesce_usecs;
2104
2105                 /* static value of interrupt rate */
2106                 adapter->rx_itr_setting = adapter->rx_eitr_param;
2107                 /* clear the lower bit as its used for dynamic state */
2108                 adapter->rx_itr_setting &= ~1;
2109         } else if (ec->rx_coalesce_usecs == 1) {
2110                 /* 1 means dynamic mode */
2111                 adapter->rx_eitr_param = 20000;
2112                 adapter->rx_itr_setting = 1;
2113         } else {
2114                 /*
2115                  * any other value means disable eitr, which is best
2116                  * served by setting the interrupt rate very high
2117                  */
2118                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2119                         adapter->rx_eitr_param = IXGBE_MAX_RSC_INT_RATE;
2120                 else
2121                         adapter->rx_eitr_param = IXGBE_MAX_INT_RATE;
2122                 adapter->rx_itr_setting = 0;
2123         }
2124
2125         if (ec->tx_coalesce_usecs > 1) {
2126                 /* check the limits */
2127                 if ((1000000/ec->tx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2128                     (1000000/ec->tx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2129                         return -EINVAL;
2130
2131                 /* store the value in ints/second */
2132                 adapter->tx_eitr_param = 1000000/ec->tx_coalesce_usecs;
2133
2134                 /* static value of interrupt rate */
2135                 adapter->tx_itr_setting = adapter->tx_eitr_param;
2136
2137                 /* clear the lower bit as its used for dynamic state */
2138                 adapter->tx_itr_setting &= ~1;
2139         } else if (ec->tx_coalesce_usecs == 1) {
2140                 /* 1 means dynamic mode */
2141                 adapter->tx_eitr_param = 10000;
2142                 adapter->tx_itr_setting = 1;
2143         } else {
2144                 adapter->tx_eitr_param = IXGBE_MAX_INT_RATE;
2145                 adapter->tx_itr_setting = 0;
2146         }
2147
2148         /* MSI/MSIx Interrupt Mode */
2149         if (adapter->flags &
2150             (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) {
2151                 int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2152                 for (i = 0; i < num_vectors; i++) {
2153                         q_vector = adapter->q_vector[i];
2154                         if (q_vector->txr_count && !q_vector->rxr_count)
2155                                 /* tx only */
2156                                 q_vector->eitr = adapter->tx_eitr_param;
2157                         else
2158                                 /* rx only or mixed */
2159                                 q_vector->eitr = adapter->rx_eitr_param;
2160                         ixgbe_write_eitr(q_vector);
2161                 }
2162         /* Legacy Interrupt Mode */
2163         } else {
2164                 q_vector = adapter->q_vector[0];
2165                 q_vector->eitr = adapter->rx_eitr_param;
2166                 ixgbe_write_eitr(q_vector);
2167         }
2168
2169         return 0;
2170 }
2171
2172 static int ixgbe_set_flags(struct net_device *netdev, u32 data)
2173 {
2174         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2175         bool need_reset = false;
2176
2177         ethtool_op_set_flags(netdev, data);
2178
2179         /* if state changes we need to update adapter->flags and reset */
2180         if ((!!(data & ETH_FLAG_LRO)) != 
2181             (!!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) {
2182                 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
2183                 need_reset = true;
2184         }
2185
2186         /*
2187          * Check if Flow Director n-tuple support was enabled or disabled.  If
2188          * the state changed, we need to reset.
2189          */
2190         if ((adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) &&
2191             (!(data & ETH_FLAG_NTUPLE))) {
2192                 /* turn off Flow Director perfect, set hash and reset */
2193                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2194                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
2195                 need_reset = true;
2196         } else if ((!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) &&
2197                    (data & ETH_FLAG_NTUPLE)) {
2198                 /* turn off Flow Director hash, enable perfect and reset */
2199                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
2200                 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2201                 need_reset = true;
2202         } else {
2203                 /* no state change */
2204         }
2205
2206         if (need_reset) {
2207                 if (netif_running(netdev))
2208                         ixgbe_reinit_locked(adapter);
2209                 else
2210                         ixgbe_reset(adapter);
2211         }
2212
2213         return 0;
2214 }
2215
2216 static int ixgbe_set_rx_ntuple(struct net_device *dev,
2217                                struct ethtool_rx_ntuple *cmd)
2218 {
2219         struct ixgbe_adapter *adapter = netdev_priv(dev);
2220         struct ethtool_rx_ntuple_flow_spec fs = cmd->fs;
2221         struct ixgbe_atr_input input_struct;
2222         struct ixgbe_atr_input_masks input_masks;
2223         int target_queue;
2224
2225         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2226                 return -EOPNOTSUPP;
2227
2228         /*
2229          * Don't allow programming if the action is a queue greater than
2230          * the number of online Tx queues.
2231          */
2232         if ((fs.action >= adapter->num_tx_queues) ||
2233             (fs.action < ETHTOOL_RXNTUPLE_ACTION_DROP))
2234                 return -EINVAL;
2235
2236         memset(&input_struct, 0, sizeof(struct ixgbe_atr_input));
2237         memset(&input_masks, 0, sizeof(struct ixgbe_atr_input_masks));
2238
2239         input_masks.src_ip_mask = fs.m_u.tcp_ip4_spec.ip4src;
2240         input_masks.dst_ip_mask = fs.m_u.tcp_ip4_spec.ip4dst;
2241         input_masks.src_port_mask = fs.m_u.tcp_ip4_spec.psrc;
2242         input_masks.dst_port_mask = fs.m_u.tcp_ip4_spec.pdst;
2243         input_masks.vlan_id_mask = fs.vlan_tag_mask;
2244         /* only use the lowest 2 bytes for flex bytes */
2245         input_masks.data_mask = (fs.data_mask & 0xffff);
2246
2247         switch (fs.flow_type) {
2248         case TCP_V4_FLOW:
2249                 ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_TCP);
2250                 break;
2251         case UDP_V4_FLOW:
2252                 ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_UDP);
2253                 break;
2254         case SCTP_V4_FLOW:
2255                 ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_SCTP);
2256                 break;
2257         default:
2258                 return -1;
2259         }
2260
2261         /* Mask bits from the inputs based on user-supplied mask */
2262         ixgbe_atr_set_src_ipv4_82599(&input_struct,
2263                     (fs.h_u.tcp_ip4_spec.ip4src & ~fs.m_u.tcp_ip4_spec.ip4src));
2264         ixgbe_atr_set_dst_ipv4_82599(&input_struct,
2265                     (fs.h_u.tcp_ip4_spec.ip4dst & ~fs.m_u.tcp_ip4_spec.ip4dst));
2266         /* 82599 expects these to be byte-swapped for perfect filtering */
2267         ixgbe_atr_set_src_port_82599(&input_struct,
2268                ((ntohs(fs.h_u.tcp_ip4_spec.psrc)) & ~fs.m_u.tcp_ip4_spec.psrc));
2269         ixgbe_atr_set_dst_port_82599(&input_struct,
2270                ((ntohs(fs.h_u.tcp_ip4_spec.pdst)) & ~fs.m_u.tcp_ip4_spec.pdst));
2271
2272         /* VLAN and Flex bytes are either completely masked or not */
2273         if (!fs.vlan_tag_mask)
2274                 ixgbe_atr_set_vlan_id_82599(&input_struct, fs.vlan_tag);
2275
2276         if (!input_masks.data_mask)
2277                 /* make sure we only use the first 2 bytes of user data */
2278                 ixgbe_atr_set_flex_byte_82599(&input_struct,
2279                                               (fs.data & 0xffff));
2280
2281         /* determine if we need to drop or route the packet */
2282         if (fs.action == ETHTOOL_RXNTUPLE_ACTION_DROP)
2283                 target_queue = MAX_RX_QUEUES - 1;
2284         else
2285                 target_queue = fs.action;
2286
2287         spin_lock(&adapter->fdir_perfect_lock);
2288         ixgbe_fdir_add_perfect_filter_82599(&adapter->hw, &input_struct,
2289                                             &input_masks, 0, target_queue);
2290         spin_unlock(&adapter->fdir_perfect_lock);
2291
2292         return 0;
2293 }
2294
2295 static const struct ethtool_ops ixgbe_ethtool_ops = {
2296         .get_settings           = ixgbe_get_settings,
2297         .set_settings           = ixgbe_set_settings,
2298         .get_drvinfo            = ixgbe_get_drvinfo,
2299         .get_regs_len           = ixgbe_get_regs_len,
2300         .get_regs               = ixgbe_get_regs,
2301         .get_wol                = ixgbe_get_wol,
2302         .set_wol                = ixgbe_set_wol,
2303         .nway_reset             = ixgbe_nway_reset,
2304         .get_link               = ethtool_op_get_link,
2305         .get_eeprom_len         = ixgbe_get_eeprom_len,
2306         .get_eeprom             = ixgbe_get_eeprom,
2307         .get_ringparam          = ixgbe_get_ringparam,
2308         .set_ringparam          = ixgbe_set_ringparam,
2309         .get_pauseparam         = ixgbe_get_pauseparam,
2310         .set_pauseparam         = ixgbe_set_pauseparam,
2311         .get_rx_csum            = ixgbe_get_rx_csum,
2312         .set_rx_csum            = ixgbe_set_rx_csum,
2313         .get_tx_csum            = ixgbe_get_tx_csum,
2314         .set_tx_csum            = ixgbe_set_tx_csum,
2315         .get_sg                 = ethtool_op_get_sg,
2316         .set_sg                 = ethtool_op_set_sg,
2317         .get_msglevel           = ixgbe_get_msglevel,
2318         .set_msglevel           = ixgbe_set_msglevel,
2319         .get_tso                = ethtool_op_get_tso,
2320         .set_tso                = ixgbe_set_tso,
2321         .self_test              = ixgbe_diag_test,
2322         .get_strings            = ixgbe_get_strings,
2323         .phys_id                = ixgbe_phys_id,
2324         .get_sset_count         = ixgbe_get_sset_count,
2325         .get_ethtool_stats      = ixgbe_get_ethtool_stats,
2326         .get_coalesce           = ixgbe_get_coalesce,
2327         .set_coalesce           = ixgbe_set_coalesce,
2328         .get_flags              = ethtool_op_get_flags,
2329         .set_flags              = ixgbe_set_flags,
2330         .set_rx_ntuple          = ixgbe_set_rx_ntuple,
2331 };
2332
2333 void ixgbe_set_ethtool_ops(struct net_device *netdev)
2334 {
2335         SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2336 }