ixgbe: Modify 82599 HWRSC statistics counters
[linux-2.6.git] / drivers / net / ixgbe / ixgbe_ethtool.c
1 /*******************************************************************************
2
3   Intel 10 Gigabit PCI Express Linux driver
4   Copyright(c) 1999 - 2009 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* ethtool support for ixgbe */
29
30 #include <linux/types.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/vmalloc.h>
36 #include <linux/uaccess.h>
37
38 #include "ixgbe.h"
39
40
41 #define IXGBE_ALL_RAR_ENTRIES 16
42
43 enum {NETDEV_STATS, IXGBE_STATS};
44
45 struct ixgbe_stats {
46         char stat_string[ETH_GSTRING_LEN];
47         int type;
48         int sizeof_stat;
49         int stat_offset;
50 };
51
52 #define IXGBE_STAT(m)           IXGBE_STATS, \
53                                 sizeof(((struct ixgbe_adapter *)0)->m), \
54                                 offsetof(struct ixgbe_adapter, m)
55 #define IXGBE_NETDEV_STAT(m)    NETDEV_STATS, \
56                                 sizeof(((struct net_device *)0)->m), \
57                                 offsetof(struct net_device, m)
58
59 static struct ixgbe_stats ixgbe_gstrings_stats[] = {
60         {"rx_packets", IXGBE_NETDEV_STAT(stats.rx_packets)},
61         {"tx_packets", IXGBE_NETDEV_STAT(stats.tx_packets)},
62         {"rx_bytes", IXGBE_NETDEV_STAT(stats.rx_bytes)},
63         {"tx_bytes", IXGBE_NETDEV_STAT(stats.tx_bytes)},
64         {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
65         {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
66         {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
67         {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
68         {"lsc_int", IXGBE_STAT(lsc_int)},
69         {"tx_busy", IXGBE_STAT(tx_busy)},
70         {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
71         {"rx_errors", IXGBE_NETDEV_STAT(stats.rx_errors)},
72         {"tx_errors", IXGBE_NETDEV_STAT(stats.tx_errors)},
73         {"rx_dropped", IXGBE_NETDEV_STAT(stats.rx_dropped)},
74         {"tx_dropped", IXGBE_NETDEV_STAT(stats.tx_dropped)},
75         {"multicast", IXGBE_NETDEV_STAT(stats.multicast)},
76         {"broadcast", IXGBE_STAT(stats.bprc)},
77         {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
78         {"collisions", IXGBE_NETDEV_STAT(stats.collisions)},
79         {"rx_over_errors", IXGBE_NETDEV_STAT(stats.rx_over_errors)},
80         {"rx_crc_errors", IXGBE_NETDEV_STAT(stats.rx_crc_errors)},
81         {"rx_frame_errors", IXGBE_NETDEV_STAT(stats.rx_frame_errors)},
82         {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
83         {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
84         {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
85         {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
86         {"rx_fifo_errors", IXGBE_NETDEV_STAT(stats.rx_fifo_errors)},
87         {"rx_missed_errors", IXGBE_NETDEV_STAT(stats.rx_missed_errors)},
88         {"tx_aborted_errors", IXGBE_NETDEV_STAT(stats.tx_aborted_errors)},
89         {"tx_carrier_errors", IXGBE_NETDEV_STAT(stats.tx_carrier_errors)},
90         {"tx_fifo_errors", IXGBE_NETDEV_STAT(stats.tx_fifo_errors)},
91         {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(stats.tx_heartbeat_errors)},
92         {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
93         {"tx_restart_queue", IXGBE_STAT(restart_queue)},
94         {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
95         {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
96         {"tx_tcp4_seg_ctxt", IXGBE_STAT(hw_tso_ctxt)},
97         {"tx_tcp6_seg_ctxt", IXGBE_STAT(hw_tso6_ctxt)},
98         {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
99         {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
100         {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
101         {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
102         {"rx_csum_offload_good", IXGBE_STAT(hw_csum_rx_good)},
103         {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
104         {"tx_csum_offload_ctxt", IXGBE_STAT(hw_csum_tx_good)},
105         {"rx_header_split", IXGBE_STAT(rx_hdr_split)},
106         {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
107         {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
108         {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
109 #ifdef IXGBE_FCOE
110         {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
111         {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
112         {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
113         {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
114         {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
115         {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
116 #endif /* IXGBE_FCOE */
117 };
118
119 #define IXGBE_QUEUE_STATS_LEN \
120         ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
121         ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
122         (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
123 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
124 #define IXGBE_PB_STATS_LEN ( \
125                  (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
126                  IXGBE_FLAG_DCB_ENABLED) ? \
127                  (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
128                   sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
129                   sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
130                   sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
131                   / sizeof(u64) : 0)
132 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
133                          IXGBE_PB_STATS_LEN + \
134                          IXGBE_QUEUE_STATS_LEN)
135
136 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
137         "Register test  (offline)", "Eeprom test    (offline)",
138         "Interrupt test (offline)", "Loopback test  (offline)",
139         "Link test   (on/offline)"
140 };
141 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
142
143 static int ixgbe_get_settings(struct net_device *netdev,
144                               struct ethtool_cmd *ecmd)
145 {
146         struct ixgbe_adapter *adapter = netdev_priv(netdev);
147         struct ixgbe_hw *hw = &adapter->hw;
148         u32 link_speed = 0;
149         bool link_up;
150
151         ecmd->supported = SUPPORTED_10000baseT_Full;
152         ecmd->autoneg = AUTONEG_ENABLE;
153         ecmd->transceiver = XCVR_EXTERNAL;
154         if ((hw->phy.media_type == ixgbe_media_type_copper) ||
155             (hw->phy.multispeed_fiber)) {
156                 ecmd->supported |= (SUPPORTED_1000baseT_Full |
157                                     SUPPORTED_Autoneg);
158
159                 ecmd->advertising = ADVERTISED_Autoneg;
160                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
161                         ecmd->advertising |= ADVERTISED_10000baseT_Full;
162                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
163                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
164                 /*
165                  * It's possible that phy.autoneg_advertised may not be
166                  * set yet.  If so display what the default would be -
167                  * both 1G and 10G supported.
168                  */
169                 if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full |
170                                            ADVERTISED_10000baseT_Full)))
171                         ecmd->advertising |= (ADVERTISED_10000baseT_Full |
172                                               ADVERTISED_1000baseT_Full);
173
174                 if (hw->phy.media_type == ixgbe_media_type_copper) {
175                         ecmd->supported |= SUPPORTED_TP;
176                         ecmd->advertising |= ADVERTISED_TP;
177                         ecmd->port = PORT_TP;
178                 } else {
179                         ecmd->supported |= SUPPORTED_FIBRE;
180                         ecmd->advertising |= ADVERTISED_FIBRE;
181                         ecmd->port = PORT_FIBRE;
182                 }
183         } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
184                 /* Set as FIBRE until SERDES defined in kernel */
185                 if (hw->device_id == IXGBE_DEV_ID_82598_BX) {
186                         ecmd->supported = (SUPPORTED_1000baseT_Full |
187                                            SUPPORTED_FIBRE);
188                         ecmd->advertising = (ADVERTISED_1000baseT_Full |
189                                              ADVERTISED_FIBRE);
190                         ecmd->port = PORT_FIBRE;
191                         ecmd->autoneg = AUTONEG_DISABLE;
192                 } else {
193                         ecmd->supported |= (SUPPORTED_1000baseT_Full |
194                                             SUPPORTED_FIBRE);
195                         ecmd->advertising = (ADVERTISED_10000baseT_Full |
196                                              ADVERTISED_1000baseT_Full |
197                                              ADVERTISED_FIBRE);
198                         ecmd->port = PORT_FIBRE;
199                 }
200         } else {
201                 ecmd->supported |= SUPPORTED_FIBRE;
202                 ecmd->advertising = (ADVERTISED_10000baseT_Full |
203                                      ADVERTISED_FIBRE);
204                 ecmd->port = PORT_FIBRE;
205                 ecmd->autoneg = AUTONEG_DISABLE;
206         }
207
208         hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
209         if (link_up) {
210                 ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
211                                SPEED_10000 : SPEED_1000;
212                 ecmd->duplex = DUPLEX_FULL;
213         } else {
214                 ecmd->speed = -1;
215                 ecmd->duplex = -1;
216         }
217
218         return 0;
219 }
220
221 static int ixgbe_set_settings(struct net_device *netdev,
222                               struct ethtool_cmd *ecmd)
223 {
224         struct ixgbe_adapter *adapter = netdev_priv(netdev);
225         struct ixgbe_hw *hw = &adapter->hw;
226         u32 advertised, old;
227         s32 err = 0;
228
229         if ((hw->phy.media_type == ixgbe_media_type_copper) ||
230             (hw->phy.multispeed_fiber)) {
231                 /* 10000/copper and 1000/copper must autoneg
232                  * this function does not support any duplex forcing, but can
233                  * limit the advertising of the adapter to only 10000 or 1000 */
234                 if (ecmd->autoneg == AUTONEG_DISABLE)
235                         return -EINVAL;
236
237                 old = hw->phy.autoneg_advertised;
238                 advertised = 0;
239                 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
240                         advertised |= IXGBE_LINK_SPEED_10GB_FULL;
241
242                 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
243                         advertised |= IXGBE_LINK_SPEED_1GB_FULL;
244
245                 if (old == advertised)
246                         return err;
247                 /* this sets the link speed and restarts auto-neg */
248                 hw->mac.autotry_restart = true;
249                 err = hw->mac.ops.setup_link(hw, advertised, true, true);
250                 if (err) {
251                         DPRINTK(PROBE, INFO,
252                                 "setup link failed with code %d\n", err);
253                         hw->mac.ops.setup_link(hw, old, true, true);
254                 }
255         } else {
256                 /* in this case we currently only support 10Gb/FULL */
257                 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
258                     (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
259                     (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
260                         return -EINVAL;
261         }
262
263         return err;
264 }
265
266 static void ixgbe_get_pauseparam(struct net_device *netdev,
267                                  struct ethtool_pauseparam *pause)
268 {
269         struct ixgbe_adapter *adapter = netdev_priv(netdev);
270         struct ixgbe_hw *hw = &adapter->hw;
271
272         /*
273          * Flow Control Autoneg isn't on if
274          *  - we didn't ask for it OR
275          *  - it failed, we know this by tx & rx being off
276          */
277         if (hw->fc.disable_fc_autoneg ||
278             (hw->fc.current_mode == ixgbe_fc_none))
279                 pause->autoneg = 0;
280         else
281                 pause->autoneg = 1;
282
283 #ifdef CONFIG_DCB
284         if (hw->fc.current_mode == ixgbe_fc_pfc) {
285                 pause->rx_pause = 0;
286                 pause->tx_pause = 0;
287         }
288
289 #endif
290         if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
291                 pause->rx_pause = 1;
292         } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
293                 pause->tx_pause = 1;
294         } else if (hw->fc.current_mode == ixgbe_fc_full) {
295                 pause->rx_pause = 1;
296                 pause->tx_pause = 1;
297         }
298 }
299
300 static int ixgbe_set_pauseparam(struct net_device *netdev,
301                                 struct ethtool_pauseparam *pause)
302 {
303         struct ixgbe_adapter *adapter = netdev_priv(netdev);
304         struct ixgbe_hw *hw = &adapter->hw;
305         struct ixgbe_fc_info fc;
306
307 #ifdef CONFIG_DCB
308         if (adapter->dcb_cfg.pfc_mode_enable ||
309                 ((hw->mac.type == ixgbe_mac_82598EB) &&
310                 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
311                 return -EINVAL;
312
313 #endif
314
315         fc = hw->fc;
316
317         if (pause->autoneg != AUTONEG_ENABLE)
318                 fc.disable_fc_autoneg = true;
319         else
320                 fc.disable_fc_autoneg = false;
321
322         if (pause->rx_pause && pause->tx_pause)
323                 fc.requested_mode = ixgbe_fc_full;
324         else if (pause->rx_pause && !pause->tx_pause)
325                 fc.requested_mode = ixgbe_fc_rx_pause;
326         else if (!pause->rx_pause && pause->tx_pause)
327                 fc.requested_mode = ixgbe_fc_tx_pause;
328         else if (!pause->rx_pause && !pause->tx_pause)
329                 fc.requested_mode = ixgbe_fc_none;
330         else
331                 return -EINVAL;
332
333 #ifdef CONFIG_DCB
334         adapter->last_lfc_mode = fc.requested_mode;
335 #endif
336
337         /* if the thing changed then we'll update and use new autoneg */
338         if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
339                 hw->fc = fc;
340                 if (netif_running(netdev))
341                         ixgbe_reinit_locked(adapter);
342                 else
343                         ixgbe_reset(adapter);
344         }
345
346         return 0;
347 }
348
349 static u32 ixgbe_get_rx_csum(struct net_device *netdev)
350 {
351         struct ixgbe_adapter *adapter = netdev_priv(netdev);
352         return (adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED);
353 }
354
355 static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
356 {
357         struct ixgbe_adapter *adapter = netdev_priv(netdev);
358         if (data)
359                 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
360         else
361                 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
362
363         if (netif_running(netdev))
364                 ixgbe_reinit_locked(adapter);
365         else
366                 ixgbe_reset(adapter);
367
368         return 0;
369 }
370
371 static u32 ixgbe_get_tx_csum(struct net_device *netdev)
372 {
373         return (netdev->features & NETIF_F_IP_CSUM) != 0;
374 }
375
376 static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
377 {
378         struct ixgbe_adapter *adapter = netdev_priv(netdev);
379
380         if (data) {
381                 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
382                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
383                         netdev->features |= NETIF_F_SCTP_CSUM;
384         } else {
385                 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
386                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
387                         netdev->features &= ~NETIF_F_SCTP_CSUM;
388         }
389
390         return 0;
391 }
392
393 static int ixgbe_set_tso(struct net_device *netdev, u32 data)
394 {
395         if (data) {
396                 netdev->features |= NETIF_F_TSO;
397                 netdev->features |= NETIF_F_TSO6;
398         } else {
399                 netif_tx_stop_all_queues(netdev);
400                 netdev->features &= ~NETIF_F_TSO;
401                 netdev->features &= ~NETIF_F_TSO6;
402                 netif_tx_start_all_queues(netdev);
403         }
404         return 0;
405 }
406
407 static u32 ixgbe_get_msglevel(struct net_device *netdev)
408 {
409         struct ixgbe_adapter *adapter = netdev_priv(netdev);
410         return adapter->msg_enable;
411 }
412
413 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
414 {
415         struct ixgbe_adapter *adapter = netdev_priv(netdev);
416         adapter->msg_enable = data;
417 }
418
419 static int ixgbe_get_regs_len(struct net_device *netdev)
420 {
421 #define IXGBE_REGS_LEN  1128
422         return IXGBE_REGS_LEN * sizeof(u32);
423 }
424
425 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
426
427 static void ixgbe_get_regs(struct net_device *netdev,
428                            struct ethtool_regs *regs, void *p)
429 {
430         struct ixgbe_adapter *adapter = netdev_priv(netdev);
431         struct ixgbe_hw *hw = &adapter->hw;
432         u32 *regs_buff = p;
433         u8 i;
434
435         memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
436
437         regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
438
439         /* General Registers */
440         regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
441         regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
442         regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
443         regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
444         regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
445         regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
446         regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
447         regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
448
449         /* NVM Register */
450         regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
451         regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
452         regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
453         regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
454         regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
455         regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
456         regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
457         regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
458         regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
459         regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
460
461         /* Interrupt */
462         /* don't read EICR because it can clear interrupt causes, instead
463          * read EICS which is a shadow but doesn't clear EICR */
464         regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
465         regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
466         regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
467         regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
468         regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
469         regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
470         regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
471         regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
472         regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
473         regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
474         regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
475         regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
476
477         /* Flow Control */
478         regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
479         regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
480         regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
481         regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
482         regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
483         for (i = 0; i < 8; i++)
484                 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
485         for (i = 0; i < 8; i++)
486                 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
487         regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
488         regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
489
490         /* Receive DMA */
491         for (i = 0; i < 64; i++)
492                 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
493         for (i = 0; i < 64; i++)
494                 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
495         for (i = 0; i < 64; i++)
496                 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
497         for (i = 0; i < 64; i++)
498                 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
499         for (i = 0; i < 64; i++)
500                 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
501         for (i = 0; i < 64; i++)
502                 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
503         for (i = 0; i < 16; i++)
504                 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
505         for (i = 0; i < 16; i++)
506                 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
507         regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
508         for (i = 0; i < 8; i++)
509                 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
510         regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
511         regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
512
513         /* Receive */
514         regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
515         regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
516         for (i = 0; i < 16; i++)
517                 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
518         for (i = 0; i < 16; i++)
519                 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
520         regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
521         regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
522         regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
523         regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
524         regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
525         regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
526         for (i = 0; i < 8; i++)
527                 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
528         for (i = 0; i < 8; i++)
529                 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
530         regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
531
532         /* Transmit */
533         for (i = 0; i < 32; i++)
534                 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
535         for (i = 0; i < 32; i++)
536                 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
537         for (i = 0; i < 32; i++)
538                 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
539         for (i = 0; i < 32; i++)
540                 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
541         for (i = 0; i < 32; i++)
542                 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
543         for (i = 0; i < 32; i++)
544                 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
545         for (i = 0; i < 32; i++)
546                 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
547         for (i = 0; i < 32; i++)
548                 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
549         regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
550         for (i = 0; i < 16; i++)
551                 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
552         regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
553         for (i = 0; i < 8; i++)
554                 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
555         regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
556
557         /* Wake Up */
558         regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
559         regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
560         regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
561         regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
562         regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
563         regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
564         regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
565         regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
566         regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
567
568         regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
569         regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
570         regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
571         regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
572         for (i = 0; i < 8; i++)
573                 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
574         for (i = 0; i < 8; i++)
575                 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
576         for (i = 0; i < 8; i++)
577                 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
578         for (i = 0; i < 8; i++)
579                 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
580         for (i = 0; i < 8; i++)
581                 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
582         for (i = 0; i < 8; i++)
583                 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
584
585         /* Statistics */
586         regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
587         regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
588         regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
589         regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
590         for (i = 0; i < 8; i++)
591                 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
592         regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
593         regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
594         regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
595         regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
596         regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
597         regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
598         regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
599         for (i = 0; i < 8; i++)
600                 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
601         for (i = 0; i < 8; i++)
602                 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
603         for (i = 0; i < 8; i++)
604                 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
605         for (i = 0; i < 8; i++)
606                 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
607         regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
608         regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
609         regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
610         regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
611         regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
612         regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
613         regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
614         regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
615         regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
616         regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
617         regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
618         regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
619         for (i = 0; i < 8; i++)
620                 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
621         regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
622         regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
623         regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
624         regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
625         regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
626         regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
627         regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
628         regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
629         regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
630         regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
631         regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
632         regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
633         regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
634         regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
635         regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
636         regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
637         regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
638         regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
639         regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
640         for (i = 0; i < 16; i++)
641                 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
642         for (i = 0; i < 16; i++)
643                 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
644         for (i = 0; i < 16; i++)
645                 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
646         for (i = 0; i < 16; i++)
647                 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
648
649         /* MAC */
650         regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
651         regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
652         regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
653         regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
654         regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
655         regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
656         regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
657         regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
658         regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
659         regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
660         regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
661         regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
662         regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
663         regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
664         regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
665         regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
666         regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
667         regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
668         regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
669         regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
670         regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
671         regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
672         regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
673         regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
674         regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
675         regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
676         regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
677         regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
678         regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
679         regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
680         regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
681         regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
682         regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
683
684         /* Diagnostic */
685         regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
686         for (i = 0; i < 8; i++)
687                 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
688         regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
689         for (i = 0; i < 4; i++)
690                 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
691         regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
692         regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
693         for (i = 0; i < 8; i++)
694                 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
695         regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
696         for (i = 0; i < 4; i++)
697                 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
698         regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
699         regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
700         regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
701         regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
702         regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
703         regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
704         regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
705         regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
706         regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
707         regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
708         regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
709         for (i = 0; i < 8; i++)
710                 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
711         regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
712         regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
713         regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
714         regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
715         regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
716         regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
717         regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
718         regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
719         regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
720 }
721
722 static int ixgbe_get_eeprom_len(struct net_device *netdev)
723 {
724         struct ixgbe_adapter *adapter = netdev_priv(netdev);
725         return adapter->hw.eeprom.word_size * 2;
726 }
727
728 static int ixgbe_get_eeprom(struct net_device *netdev,
729                             struct ethtool_eeprom *eeprom, u8 *bytes)
730 {
731         struct ixgbe_adapter *adapter = netdev_priv(netdev);
732         struct ixgbe_hw *hw = &adapter->hw;
733         u16 *eeprom_buff;
734         int first_word, last_word, eeprom_len;
735         int ret_val = 0;
736         u16 i;
737
738         if (eeprom->len == 0)
739                 return -EINVAL;
740
741         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
742
743         first_word = eeprom->offset >> 1;
744         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
745         eeprom_len = last_word - first_word + 1;
746
747         eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
748         if (!eeprom_buff)
749                 return -ENOMEM;
750
751         for (i = 0; i < eeprom_len; i++) {
752                 if ((ret_val = hw->eeprom.ops.read(hw, first_word + i,
753                     &eeprom_buff[i])))
754                         break;
755         }
756
757         /* Device's eeprom is always little-endian, word addressable */
758         for (i = 0; i < eeprom_len; i++)
759                 le16_to_cpus(&eeprom_buff[i]);
760
761         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
762         kfree(eeprom_buff);
763
764         return ret_val;
765 }
766
767 static void ixgbe_get_drvinfo(struct net_device *netdev,
768                               struct ethtool_drvinfo *drvinfo)
769 {
770         struct ixgbe_adapter *adapter = netdev_priv(netdev);
771         char firmware_version[32];
772
773         strncpy(drvinfo->driver, ixgbe_driver_name, 32);
774         strncpy(drvinfo->version, ixgbe_driver_version, 32);
775
776         sprintf(firmware_version, "%d.%d-%d",
777                 (adapter->eeprom_version & 0xF000) >> 12,
778                 (adapter->eeprom_version & 0x0FF0) >> 4,
779                 adapter->eeprom_version & 0x000F);
780
781         strncpy(drvinfo->fw_version, firmware_version, 32);
782         strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
783         drvinfo->n_stats = IXGBE_STATS_LEN;
784         drvinfo->testinfo_len = IXGBE_TEST_LEN;
785         drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
786 }
787
788 static void ixgbe_get_ringparam(struct net_device *netdev,
789                                 struct ethtool_ringparam *ring)
790 {
791         struct ixgbe_adapter *adapter = netdev_priv(netdev);
792         struct ixgbe_ring *tx_ring = adapter->tx_ring;
793         struct ixgbe_ring *rx_ring = adapter->rx_ring;
794
795         ring->rx_max_pending = IXGBE_MAX_RXD;
796         ring->tx_max_pending = IXGBE_MAX_TXD;
797         ring->rx_mini_max_pending = 0;
798         ring->rx_jumbo_max_pending = 0;
799         ring->rx_pending = rx_ring->count;
800         ring->tx_pending = tx_ring->count;
801         ring->rx_mini_pending = 0;
802         ring->rx_jumbo_pending = 0;
803 }
804
805 static int ixgbe_set_ringparam(struct net_device *netdev,
806                                struct ethtool_ringparam *ring)
807 {
808         struct ixgbe_adapter *adapter = netdev_priv(netdev);
809         struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
810         int i, err = 0;
811         u32 new_rx_count, new_tx_count;
812         bool need_update = false;
813
814         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
815                 return -EINVAL;
816
817         new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
818         new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
819         new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
820
821         new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
822         new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
823         new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
824
825         if ((new_tx_count == adapter->tx_ring->count) &&
826             (new_rx_count == adapter->rx_ring->count)) {
827                 /* nothing to do */
828                 return 0;
829         }
830
831         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
832                 msleep(1);
833
834         if (!netif_running(adapter->netdev)) {
835                 for (i = 0; i < adapter->num_tx_queues; i++)
836                         adapter->tx_ring[i].count = new_tx_count;
837                 for (i = 0; i < adapter->num_rx_queues; i++)
838                         adapter->rx_ring[i].count = new_rx_count;
839                 adapter->tx_ring_count = new_tx_count;
840                 adapter->rx_ring_count = new_rx_count;
841                 goto err_setup;
842         }
843
844         temp_tx_ring = kcalloc(adapter->num_tx_queues,
845                                sizeof(struct ixgbe_ring), GFP_KERNEL);
846         if (!temp_tx_ring) {
847                 err = -ENOMEM;
848                 goto err_setup;
849         }
850
851         if (new_tx_count != adapter->tx_ring_count) {
852                 memcpy(temp_tx_ring, adapter->tx_ring,
853                        adapter->num_tx_queues * sizeof(struct ixgbe_ring));
854                 for (i = 0; i < adapter->num_tx_queues; i++) {
855                         temp_tx_ring[i].count = new_tx_count;
856                         err = ixgbe_setup_tx_resources(adapter,
857                                                        &temp_tx_ring[i]);
858                         if (err) {
859                                 while (i) {
860                                         i--;
861                                         ixgbe_free_tx_resources(adapter,
862                                                                 &temp_tx_ring[i]);
863                                 }
864                                 goto err_setup;
865                         }
866                 }
867                 need_update = true;
868         }
869
870         temp_rx_ring = kcalloc(adapter->num_rx_queues,
871                                sizeof(struct ixgbe_ring), GFP_KERNEL);
872         if ((!temp_rx_ring) && (need_update)) {
873                 for (i = 0; i < adapter->num_tx_queues; i++)
874                         ixgbe_free_tx_resources(adapter, &temp_tx_ring[i]);
875                 kfree(temp_tx_ring);
876                 err = -ENOMEM;
877                 goto err_setup;
878         }
879
880         if (new_rx_count != adapter->rx_ring_count) {
881                 memcpy(temp_rx_ring, adapter->rx_ring,
882                        adapter->num_rx_queues * sizeof(struct ixgbe_ring));
883                 for (i = 0; i < adapter->num_rx_queues; i++) {
884                         temp_rx_ring[i].count = new_rx_count;
885                         err = ixgbe_setup_rx_resources(adapter,
886                                                        &temp_rx_ring[i]);
887                         if (err) {
888                                 while (i) {
889                                         i--;
890                                         ixgbe_free_rx_resources(adapter,
891                                                               &temp_rx_ring[i]);
892                                 }
893                                 goto err_setup;
894                         }
895                 }
896                 need_update = true;
897         }
898
899         /* if rings need to be updated, here's the place to do it in one shot */
900         if (need_update) {
901                 ixgbe_down(adapter);
902
903                 /* tx */
904                 if (new_tx_count != adapter->tx_ring_count) {
905                         kfree(adapter->tx_ring);
906                         adapter->tx_ring = temp_tx_ring;
907                         temp_tx_ring = NULL;
908                         adapter->tx_ring_count = new_tx_count;
909                 }
910
911                 /* rx */
912                 if (new_rx_count != adapter->rx_ring_count) {
913                         kfree(adapter->rx_ring);
914                         adapter->rx_ring = temp_rx_ring;
915                         temp_rx_ring = NULL;
916                         adapter->rx_ring_count = new_rx_count;
917                 }
918                 ixgbe_up(adapter);
919         }
920 err_setup:
921         clear_bit(__IXGBE_RESETTING, &adapter->state);
922         return err;
923 }
924
925 static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
926 {
927         switch (sset) {
928         case ETH_SS_TEST:
929                 return IXGBE_TEST_LEN;
930         case ETH_SS_STATS:
931                 return IXGBE_STATS_LEN;
932         default:
933                 return -EOPNOTSUPP;
934         }
935 }
936
937 static void ixgbe_get_ethtool_stats(struct net_device *netdev,
938                                     struct ethtool_stats *stats, u64 *data)
939 {
940         struct ixgbe_adapter *adapter = netdev_priv(netdev);
941         u64 *queue_stat;
942         int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64);
943         int j, k;
944         int i;
945         char *p = NULL;
946
947         ixgbe_update_stats(adapter);
948         for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
949                 switch (ixgbe_gstrings_stats[i].type) {
950                 case NETDEV_STATS:
951                         p = (char *) netdev +
952                                         ixgbe_gstrings_stats[i].stat_offset;
953                         break;
954                 case IXGBE_STATS:
955                         p = (char *) adapter +
956                                         ixgbe_gstrings_stats[i].stat_offset;
957                         break;
958                 }
959
960                 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
961                            sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
962         }
963         for (j = 0; j < adapter->num_tx_queues; j++) {
964                 queue_stat = (u64 *)&adapter->tx_ring[j].stats;
965                 for (k = 0; k < stat_count; k++)
966                         data[i + k] = queue_stat[k];
967                 i += k;
968         }
969         for (j = 0; j < adapter->num_rx_queues; j++) {
970                 queue_stat = (u64 *)&adapter->rx_ring[j].stats;
971                 for (k = 0; k < stat_count; k++)
972                         data[i + k] = queue_stat[k];
973                 i += k;
974         }
975         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
976                 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
977                         data[i++] = adapter->stats.pxontxc[j];
978                         data[i++] = adapter->stats.pxofftxc[j];
979                 }
980                 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
981                         data[i++] = adapter->stats.pxonrxc[j];
982                         data[i++] = adapter->stats.pxoffrxc[j];
983                 }
984         }
985 }
986
987 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
988                               u8 *data)
989 {
990         struct ixgbe_adapter *adapter = netdev_priv(netdev);
991         char *p = (char *)data;
992         int i;
993
994         switch (stringset) {
995         case ETH_SS_TEST:
996                 memcpy(data, *ixgbe_gstrings_test,
997                        IXGBE_TEST_LEN * ETH_GSTRING_LEN);
998                 break;
999         case ETH_SS_STATS:
1000                 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1001                         memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1002                                ETH_GSTRING_LEN);
1003                         p += ETH_GSTRING_LEN;
1004                 }
1005                 for (i = 0; i < adapter->num_tx_queues; i++) {
1006                         sprintf(p, "tx_queue_%u_packets", i);
1007                         p += ETH_GSTRING_LEN;
1008                         sprintf(p, "tx_queue_%u_bytes", i);
1009                         p += ETH_GSTRING_LEN;
1010                 }
1011                 for (i = 0; i < adapter->num_rx_queues; i++) {
1012                         sprintf(p, "rx_queue_%u_packets", i);
1013                         p += ETH_GSTRING_LEN;
1014                         sprintf(p, "rx_queue_%u_bytes", i);
1015                         p += ETH_GSTRING_LEN;
1016                 }
1017                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1018                         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
1019                                 sprintf(p, "tx_pb_%u_pxon", i);
1020                                 p += ETH_GSTRING_LEN;
1021                                 sprintf(p, "tx_pb_%u_pxoff", i);
1022                                 p += ETH_GSTRING_LEN;
1023                         }
1024                         for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
1025                                 sprintf(p, "rx_pb_%u_pxon", i);
1026                                 p += ETH_GSTRING_LEN;
1027                                 sprintf(p, "rx_pb_%u_pxoff", i);
1028                                 p += ETH_GSTRING_LEN;
1029                         }
1030                 }
1031                 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1032                 break;
1033         }
1034 }
1035
1036 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1037 {
1038         struct ixgbe_hw *hw = &adapter->hw;
1039         bool link_up;
1040         u32 link_speed = 0;
1041         *data = 0;
1042
1043         hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1044         if (link_up)
1045                 return *data;
1046         else
1047                 *data = 1;
1048         return *data;
1049 }
1050
1051 /* ethtool register test data */
1052 struct ixgbe_reg_test {
1053         u16 reg;
1054         u8  array_len;
1055         u8  test_type;
1056         u32 mask;
1057         u32 write;
1058 };
1059
1060 /* In the hardware, registers are laid out either singly, in arrays
1061  * spaced 0x40 bytes apart, or in contiguous tables.  We assume
1062  * most tests take place on arrays or single registers (handled
1063  * as a single-element array) and special-case the tables.
1064  * Table tests are always pattern tests.
1065  *
1066  * We also make provision for some required setup steps by specifying
1067  * registers to be written without any read-back testing.
1068  */
1069
1070 #define PATTERN_TEST    1
1071 #define SET_READ_TEST   2
1072 #define WRITE_NO_TEST   3
1073 #define TABLE32_TEST    4
1074 #define TABLE64_TEST_LO 5
1075 #define TABLE64_TEST_HI 6
1076
1077 /* default 82599 register test */
1078 static struct ixgbe_reg_test reg_test_82599[] = {
1079         { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1080         { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1081         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1082         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1083         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1084         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1085         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1086         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1087         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1088         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1089         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1090         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1091         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1092         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1093         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1094         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1095         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1096         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1097         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1098         { 0, 0, 0, 0 }
1099 };
1100
1101 /* default 82598 register test */
1102 static struct ixgbe_reg_test reg_test_82598[] = {
1103         { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1104         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1105         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1106         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1107         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1108         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1109         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1110         /* Enable all four RX queues before testing. */
1111         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1112         /* RDH is read-only for 82598, only test RDT. */
1113         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1114         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1115         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1116         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1117         { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1118         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1119         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1120         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1121         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1122         { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1123         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1124         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1125         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1126         { 0, 0, 0, 0 }
1127 };
1128
1129 #define REG_PATTERN_TEST(R, M, W)                                             \
1130 {                                                                             \
1131         u32 pat, val, before;                                                 \
1132         const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
1133         for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {                       \
1134                 before = readl(adapter->hw.hw_addr + R);                      \
1135                 writel((_test[pat] & W), (adapter->hw.hw_addr + R));          \
1136                 val = readl(adapter->hw.hw_addr + R);                         \
1137                 if (val != (_test[pat] & W & M)) {                            \
1138                         DPRINTK(DRV, ERR, "pattern test reg %04X failed: got "\
1139                                           "0x%08X expected 0x%08X\n",         \
1140                                 R, val, (_test[pat] & W & M));                \
1141                         *data = R;                                            \
1142                         writel(before, adapter->hw.hw_addr + R);              \
1143                         return 1;                                             \
1144                 }                                                             \
1145                 writel(before, adapter->hw.hw_addr + R);                      \
1146         }                                                                     \
1147 }
1148
1149 #define REG_SET_AND_CHECK(R, M, W)                                            \
1150 {                                                                             \
1151         u32 val, before;                                                      \
1152         before = readl(adapter->hw.hw_addr + R);                              \
1153         writel((W & M), (adapter->hw.hw_addr + R));                           \
1154         val = readl(adapter->hw.hw_addr + R);                                 \
1155         if ((W & M) != (val & M)) {                                           \
1156                 DPRINTK(DRV, ERR, "set/check reg %04X test failed: got 0x%08X "\
1157                                  "expected 0x%08X\n", R, (val & M), (W & M)); \
1158                 *data = R;                                                    \
1159                 writel(before, (adapter->hw.hw_addr + R));                    \
1160                 return 1;                                                     \
1161         }                                                                     \
1162         writel(before, (adapter->hw.hw_addr + R));                            \
1163 }
1164
1165 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1166 {
1167         struct ixgbe_reg_test *test;
1168         u32 value, before, after;
1169         u32 i, toggle;
1170
1171         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1172                 toggle = 0x7FFFF30F;
1173                 test = reg_test_82599;
1174         } else {
1175                 toggle = 0x7FFFF3FF;
1176                 test = reg_test_82598;
1177         }
1178
1179         /*
1180          * Because the status register is such a special case,
1181          * we handle it separately from the rest of the register
1182          * tests.  Some bits are read-only, some toggle, and some
1183          * are writeable on newer MACs.
1184          */
1185         before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1186         value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1187         IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1188         after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1189         if (value != after) {
1190                 DPRINTK(DRV, ERR, "failed STATUS register test got: "
1191                         "0x%08X expected: 0x%08X\n", after, value);
1192                 *data = 1;
1193                 return 1;
1194         }
1195         /* restore previous status */
1196         IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1197
1198         /*
1199          * Perform the remainder of the register test, looping through
1200          * the test table until we either fail or reach the null entry.
1201          */
1202         while (test->reg) {
1203                 for (i = 0; i < test->array_len; i++) {
1204                         switch (test->test_type) {
1205                         case PATTERN_TEST:
1206                                 REG_PATTERN_TEST(test->reg + (i * 0x40),
1207                                                 test->mask,
1208                                                 test->write);
1209                                 break;
1210                         case SET_READ_TEST:
1211                                 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1212                                                 test->mask,
1213                                                 test->write);
1214                                 break;
1215                         case WRITE_NO_TEST:
1216                                 writel(test->write,
1217                                        (adapter->hw.hw_addr + test->reg)
1218                                        + (i * 0x40));
1219                                 break;
1220                         case TABLE32_TEST:
1221                                 REG_PATTERN_TEST(test->reg + (i * 4),
1222                                                 test->mask,
1223                                                 test->write);
1224                                 break;
1225                         case TABLE64_TEST_LO:
1226                                 REG_PATTERN_TEST(test->reg + (i * 8),
1227                                                 test->mask,
1228                                                 test->write);
1229                                 break;
1230                         case TABLE64_TEST_HI:
1231                                 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1232                                                 test->mask,
1233                                                 test->write);
1234                                 break;
1235                         }
1236                 }
1237                 test++;
1238         }
1239
1240         *data = 0;
1241         return 0;
1242 }
1243
1244 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1245 {
1246         struct ixgbe_hw *hw = &adapter->hw;
1247         if (hw->eeprom.ops.validate_checksum(hw, NULL))
1248                 *data = 1;
1249         else
1250                 *data = 0;
1251         return *data;
1252 }
1253
1254 static irqreturn_t ixgbe_test_intr(int irq, void *data)
1255 {
1256         struct net_device *netdev = (struct net_device *) data;
1257         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1258
1259         adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1260
1261         return IRQ_HANDLED;
1262 }
1263
1264 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1265 {
1266         struct net_device *netdev = adapter->netdev;
1267         u32 mask, i = 0, shared_int = true;
1268         u32 irq = adapter->pdev->irq;
1269
1270         *data = 0;
1271
1272         /* Hook up test interrupt handler just for this test */
1273         if (adapter->msix_entries) {
1274                 /* NOTE: we don't test MSI-X interrupts here, yet */
1275                 return 0;
1276         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1277                 shared_int = false;
1278                 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
1279                                 netdev)) {
1280                         *data = 1;
1281                         return -1;
1282                 }
1283         } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
1284                                 netdev->name, netdev)) {
1285                 shared_int = false;
1286         } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
1287                                netdev->name, netdev)) {
1288                 *data = 1;
1289                 return -1;
1290         }
1291         DPRINTK(HW, INFO, "testing %s interrupt\n",
1292                 (shared_int ? "shared" : "unshared"));
1293
1294         /* Disable all the interrupts */
1295         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1296         msleep(10);
1297
1298         /* Test each interrupt */
1299         for (; i < 10; i++) {
1300                 /* Interrupt to test */
1301                 mask = 1 << i;
1302
1303                 if (!shared_int) {
1304                         /*
1305                          * Disable the interrupts to be reported in
1306                          * the cause register and then force the same
1307                          * interrupt and see if one gets posted.  If
1308                          * an interrupt was posted to the bus, the
1309                          * test failed.
1310                          */
1311                         adapter->test_icr = 0;
1312                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1313                                         ~mask & 0x00007FFF);
1314                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1315                                         ~mask & 0x00007FFF);
1316                         msleep(10);
1317
1318                         if (adapter->test_icr & mask) {
1319                                 *data = 3;
1320                                 break;
1321                         }
1322                 }
1323
1324                 /*
1325                  * Enable the interrupt to be reported in the cause
1326                  * register and then force the same interrupt and see
1327                  * if one gets posted.  If an interrupt was not posted
1328                  * to the bus, the test failed.
1329                  */
1330                 adapter->test_icr = 0;
1331                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1332                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1333                 msleep(10);
1334
1335                 if (!(adapter->test_icr &mask)) {
1336                         *data = 4;
1337                         break;
1338                 }
1339
1340                 if (!shared_int) {
1341                         /*
1342                          * Disable the other interrupts to be reported in
1343                          * the cause register and then force the other
1344                          * interrupts and see if any get posted.  If
1345                          * an interrupt was posted to the bus, the
1346                          * test failed.
1347                          */
1348                         adapter->test_icr = 0;
1349                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1350                                         ~mask & 0x00007FFF);
1351                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1352                                         ~mask & 0x00007FFF);
1353                         msleep(10);
1354
1355                         if (adapter->test_icr) {
1356                                 *data = 5;
1357                                 break;
1358                         }
1359                 }
1360         }
1361
1362         /* Disable all the interrupts */
1363         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1364         msleep(10);
1365
1366         /* Unhook test interrupt handler */
1367         free_irq(irq, netdev);
1368
1369         return *data;
1370 }
1371
1372 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1373 {
1374         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1375         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1376         struct ixgbe_hw *hw = &adapter->hw;
1377         struct pci_dev *pdev = adapter->pdev;
1378         u32 reg_ctl;
1379         int i;
1380
1381         /* shut down the DMA engines now so they can be reinitialized later */
1382
1383         /* first Rx */
1384         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1385         reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1386         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
1387         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(0));
1388         reg_ctl &= ~IXGBE_RXDCTL_ENABLE;
1389         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(0), reg_ctl);
1390
1391         /* now Tx */
1392         reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(0));
1393         reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1394         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(0), reg_ctl);
1395         if (hw->mac.type == ixgbe_mac_82599EB) {
1396                 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1397                 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1398                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1399         }
1400
1401         ixgbe_reset(adapter);
1402
1403         if (tx_ring->desc && tx_ring->tx_buffer_info) {
1404                 for (i = 0; i < tx_ring->count; i++) {
1405                         struct ixgbe_tx_buffer *buf =
1406                                         &(tx_ring->tx_buffer_info[i]);
1407                         if (buf->dma)
1408                                 pci_unmap_single(pdev, buf->dma, buf->length,
1409                                                  PCI_DMA_TODEVICE);
1410                         if (buf->skb)
1411                                 dev_kfree_skb(buf->skb);
1412                 }
1413         }
1414
1415         if (rx_ring->desc && rx_ring->rx_buffer_info) {
1416                 for (i = 0; i < rx_ring->count; i++) {
1417                         struct ixgbe_rx_buffer *buf =
1418                                         &(rx_ring->rx_buffer_info[i]);
1419                         if (buf->dma)
1420                                 pci_unmap_single(pdev, buf->dma,
1421                                                  IXGBE_RXBUFFER_2048,
1422                                                  PCI_DMA_FROMDEVICE);
1423                         if (buf->skb)
1424                                 dev_kfree_skb(buf->skb);
1425                 }
1426         }
1427
1428         if (tx_ring->desc) {
1429                 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1430                                     tx_ring->dma);
1431                 tx_ring->desc = NULL;
1432         }
1433         if (rx_ring->desc) {
1434                 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1435                                     rx_ring->dma);
1436                 rx_ring->desc = NULL;
1437         }
1438
1439         kfree(tx_ring->tx_buffer_info);
1440         tx_ring->tx_buffer_info = NULL;
1441         kfree(rx_ring->rx_buffer_info);
1442         rx_ring->rx_buffer_info = NULL;
1443
1444         return;
1445 }
1446
1447 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1448 {
1449         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1450         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1451         struct pci_dev *pdev = adapter->pdev;
1452         u32 rctl, reg_data;
1453         int i, ret_val;
1454
1455         /* Setup Tx descriptor ring and Tx buffers */
1456
1457         if (!tx_ring->count)
1458                 tx_ring->count = IXGBE_DEFAULT_TXD;
1459
1460         tx_ring->tx_buffer_info = kcalloc(tx_ring->count,
1461                                           sizeof(struct ixgbe_tx_buffer),
1462                                           GFP_KERNEL);
1463         if (!(tx_ring->tx_buffer_info)) {
1464                 ret_val = 1;
1465                 goto err_nomem;
1466         }
1467
1468         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
1469         tx_ring->size = ALIGN(tx_ring->size, 4096);
1470         if (!(tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1471                                                    &tx_ring->dma))) {
1472                 ret_val = 2;
1473                 goto err_nomem;
1474         }
1475         tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1476
1477         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAL(0),
1478                         ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1479         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAH(0),
1480                         ((u64) tx_ring->dma >> 32));
1481         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDLEN(0),
1482                         tx_ring->count * sizeof(union ixgbe_adv_tx_desc));
1483         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDH(0), 0);
1484         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), 0);
1485
1486         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1487         reg_data |= IXGBE_HLREG0_TXPADEN;
1488         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1489
1490         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1491                 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1492                 reg_data |= IXGBE_DMATXCTL_TE;
1493                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1494         }
1495         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_TXDCTL(0));
1496         reg_data |= IXGBE_TXDCTL_ENABLE;
1497         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TXDCTL(0), reg_data);
1498
1499         for (i = 0; i < tx_ring->count; i++) {
1500                 union ixgbe_adv_tx_desc *desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
1501                 struct sk_buff *skb;
1502                 unsigned int size = 1024;
1503
1504                 skb = alloc_skb(size, GFP_KERNEL);
1505                 if (!skb) {
1506                         ret_val = 3;
1507                         goto err_nomem;
1508                 }
1509                 skb_put(skb, size);
1510                 tx_ring->tx_buffer_info[i].skb = skb;
1511                 tx_ring->tx_buffer_info[i].length = skb->len;
1512                 tx_ring->tx_buffer_info[i].dma =
1513                         pci_map_single(pdev, skb->data, skb->len,
1514                                        PCI_DMA_TODEVICE);
1515                 desc->read.buffer_addr =
1516                                     cpu_to_le64(tx_ring->tx_buffer_info[i].dma);
1517                 desc->read.cmd_type_len = cpu_to_le32(skb->len);
1518                 desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD_EOP |
1519                                                        IXGBE_TXD_CMD_IFCS |
1520                                                        IXGBE_TXD_CMD_RS);
1521                 desc->read.olinfo_status = 0;
1522                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1523                         desc->read.olinfo_status |=
1524                                         (skb->len << IXGBE_ADVTXD_PAYLEN_SHIFT);
1525
1526         }
1527
1528         /* Setup Rx Descriptor ring and Rx buffers */
1529
1530         if (!rx_ring->count)
1531                 rx_ring->count = IXGBE_DEFAULT_RXD;
1532
1533         rx_ring->rx_buffer_info = kcalloc(rx_ring->count,
1534                                           sizeof(struct ixgbe_rx_buffer),
1535                                           GFP_KERNEL);
1536         if (!(rx_ring->rx_buffer_info)) {
1537                 ret_val = 4;
1538                 goto err_nomem;
1539         }
1540
1541         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
1542         rx_ring->size = ALIGN(rx_ring->size, 4096);
1543         if (!(rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1544                                                    &rx_ring->dma))) {
1545                 ret_val = 5;
1546                 goto err_nomem;
1547         }
1548         rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1549
1550         rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1551         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
1552         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAL(0),
1553                         ((u64)rx_ring->dma & 0xFFFFFFFF));
1554         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAH(0),
1555                         ((u64) rx_ring->dma >> 32));
1556         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDLEN(0), rx_ring->size);
1557         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDH(0), 0);
1558         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), 0);
1559
1560         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1561         reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1562         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1563
1564         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1565         reg_data &= ~IXGBE_HLREG0_LPBK;
1566         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1567
1568         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RDRXCTL);
1569 #define IXGBE_RDRXCTL_RDMTS_MASK    0x00000003 /* Receive Descriptor Minimum
1570                                                   Threshold Size mask */
1571         reg_data &= ~IXGBE_RDRXCTL_RDMTS_MASK;
1572         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDRXCTL, reg_data);
1573
1574         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MCSTCTRL);
1575 #define IXGBE_MCSTCTRL_MO_MASK      0x00000003 /* Multicast Offset mask */
1576         reg_data &= ~IXGBE_MCSTCTRL_MO_MASK;
1577         reg_data |= adapter->hw.mac.mc_filter_type;
1578         IXGBE_WRITE_REG(&adapter->hw, IXGBE_MCSTCTRL, reg_data);
1579
1580         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(0));
1581         reg_data |= IXGBE_RXDCTL_ENABLE;
1582         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(0), reg_data);
1583         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1584                 int j = adapter->rx_ring[0].reg_idx;
1585                 u32 k;
1586                 for (k = 0; k < 10; k++) {
1587                         if (IXGBE_READ_REG(&adapter->hw,
1588                                            IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
1589                                 break;
1590                         else
1591                                 msleep(1);
1592                 }
1593         }
1594
1595         rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1596         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1597
1598         for (i = 0; i < rx_ring->count; i++) {
1599                 union ixgbe_adv_rx_desc *rx_desc =
1600                                                  IXGBE_RX_DESC_ADV(*rx_ring, i);
1601                 struct sk_buff *skb;
1602
1603                 skb = alloc_skb(IXGBE_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL);
1604                 if (!skb) {
1605                         ret_val = 6;
1606                         goto err_nomem;
1607                 }
1608                 skb_reserve(skb, NET_IP_ALIGN);
1609                 rx_ring->rx_buffer_info[i].skb = skb;
1610                 rx_ring->rx_buffer_info[i].dma =
1611                         pci_map_single(pdev, skb->data, IXGBE_RXBUFFER_2048,
1612                                        PCI_DMA_FROMDEVICE);
1613                 rx_desc->read.pkt_addr =
1614                                 cpu_to_le64(rx_ring->rx_buffer_info[i].dma);
1615                 memset(skb->data, 0x00, skb->len);
1616         }
1617
1618         return 0;
1619
1620 err_nomem:
1621         ixgbe_free_desc_rings(adapter);
1622         return ret_val;
1623 }
1624
1625 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1626 {
1627         struct ixgbe_hw *hw = &adapter->hw;
1628         u32 reg_data;
1629
1630         /* right now we only support MAC loopback in the driver */
1631
1632         /* Setup MAC loopback */
1633         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1634         reg_data |= IXGBE_HLREG0_LPBK;
1635         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1636
1637         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1638         reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1639         reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1640         IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
1641
1642         /* Disable Atlas Tx lanes; re-enabled in reset path */
1643         if (hw->mac.type == ixgbe_mac_82598EB) {
1644                 u8 atlas;
1645
1646                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1647                 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1648                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1649
1650                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1651                 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1652                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1653
1654                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1655                 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1656                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1657
1658                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1659                 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1660                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1661         }
1662
1663         return 0;
1664 }
1665
1666 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1667 {
1668         u32 reg_data;
1669
1670         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1671         reg_data &= ~IXGBE_HLREG0_LPBK;
1672         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1673 }
1674
1675 static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1676                                       unsigned int frame_size)
1677 {
1678         memset(skb->data, 0xFF, frame_size);
1679         frame_size &= ~1;
1680         memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1681         memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1682         memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1683 }
1684
1685 static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1686                                     unsigned int frame_size)
1687 {
1688         frame_size &= ~1;
1689         if (*(skb->data + 3) == 0xFF) {
1690                 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1691                     (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1692                         return 0;
1693                 }
1694         }
1695         return 13;
1696 }
1697
1698 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1699 {
1700         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1701         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1702         struct pci_dev *pdev = adapter->pdev;
1703         int i, j, k, l, lc, good_cnt, ret_val = 0;
1704         unsigned long time;
1705
1706         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), rx_ring->count - 1);
1707
1708         /*
1709          * Calculate the loop count based on the largest descriptor ring
1710          * The idea is to wrap the largest ring a number of times using 64
1711          * send/receive pairs during each loop
1712          */
1713
1714         if (rx_ring->count <= tx_ring->count)
1715                 lc = ((tx_ring->count / 64) * 2) + 1;
1716         else
1717                 lc = ((rx_ring->count / 64) * 2) + 1;
1718
1719         k = l = 0;
1720         for (j = 0; j <= lc; j++) {
1721                 for (i = 0; i < 64; i++) {
1722                         ixgbe_create_lbtest_frame(
1723                                         tx_ring->tx_buffer_info[k].skb,
1724                                         1024);
1725                         pci_dma_sync_single_for_device(pdev,
1726                                 tx_ring->tx_buffer_info[k].dma,
1727                                 tx_ring->tx_buffer_info[k].length,
1728                                 PCI_DMA_TODEVICE);
1729                         if (unlikely(++k == tx_ring->count))
1730                                 k = 0;
1731                 }
1732                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), k);
1733                 msleep(200);
1734                 /* set the start time for the receive */
1735                 time = jiffies;
1736                 good_cnt = 0;
1737                 do {
1738                         /* receive the sent packets */
1739                         pci_dma_sync_single_for_cpu(pdev,
1740                                         rx_ring->rx_buffer_info[l].dma,
1741                                         IXGBE_RXBUFFER_2048,
1742                                         PCI_DMA_FROMDEVICE);
1743                         ret_val = ixgbe_check_lbtest_frame(
1744                                         rx_ring->rx_buffer_info[l].skb, 1024);
1745                         if (!ret_val)
1746                                 good_cnt++;
1747                         if (++l == rx_ring->count)
1748                                 l = 0;
1749                         /*
1750                          * time + 20 msecs (200 msecs on 2.4) is more than
1751                          * enough time to complete the receives, if it's
1752                          * exceeded, break and error off
1753                          */
1754                 } while (good_cnt < 64 && jiffies < (time + 20));
1755                 if (good_cnt != 64) {
1756                         /* ret_val is the same as mis-compare */
1757                         ret_val = 13;
1758                         break;
1759                 }
1760                 if (jiffies >= (time + 20)) {
1761                         /* Error code for time out error */
1762                         ret_val = 14;
1763                         break;
1764                 }
1765         }
1766
1767         return ret_val;
1768 }
1769
1770 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1771 {
1772         *data = ixgbe_setup_desc_rings(adapter);
1773         if (*data)
1774                 goto out;
1775         *data = ixgbe_setup_loopback_test(adapter);
1776         if (*data)
1777                 goto err_loopback;
1778         *data = ixgbe_run_loopback_test(adapter);
1779         ixgbe_loopback_cleanup(adapter);
1780
1781 err_loopback:
1782         ixgbe_free_desc_rings(adapter);
1783 out:
1784         return *data;
1785 }
1786
1787 static void ixgbe_diag_test(struct net_device *netdev,
1788                             struct ethtool_test *eth_test, u64 *data)
1789 {
1790         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1791         bool if_running = netif_running(netdev);
1792
1793         set_bit(__IXGBE_TESTING, &adapter->state);
1794         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1795                 /* Offline tests */
1796
1797                 DPRINTK(HW, INFO, "offline testing starting\n");
1798
1799                 /* Link test performed before hardware reset so autoneg doesn't
1800                  * interfere with test result */
1801                 if (ixgbe_link_test(adapter, &data[4]))
1802                         eth_test->flags |= ETH_TEST_FL_FAILED;
1803
1804                 if (if_running)
1805                         /* indicate we're in test mode */
1806                         dev_close(netdev);
1807                 else
1808                         ixgbe_reset(adapter);
1809
1810                 DPRINTK(HW, INFO, "register testing starting\n");
1811                 if (ixgbe_reg_test(adapter, &data[0]))
1812                         eth_test->flags |= ETH_TEST_FL_FAILED;
1813
1814                 ixgbe_reset(adapter);
1815                 DPRINTK(HW, INFO, "eeprom testing starting\n");
1816                 if (ixgbe_eeprom_test(adapter, &data[1]))
1817                         eth_test->flags |= ETH_TEST_FL_FAILED;
1818
1819                 ixgbe_reset(adapter);
1820                 DPRINTK(HW, INFO, "interrupt testing starting\n");
1821                 if (ixgbe_intr_test(adapter, &data[2]))
1822                         eth_test->flags |= ETH_TEST_FL_FAILED;
1823
1824                 ixgbe_reset(adapter);
1825                 DPRINTK(HW, INFO, "loopback testing starting\n");
1826                 if (ixgbe_loopback_test(adapter, &data[3]))
1827                         eth_test->flags |= ETH_TEST_FL_FAILED;
1828
1829                 ixgbe_reset(adapter);
1830
1831                 clear_bit(__IXGBE_TESTING, &adapter->state);
1832                 if (if_running)
1833                         dev_open(netdev);
1834         } else {
1835                 DPRINTK(HW, INFO, "online testing starting\n");
1836                 /* Online tests */
1837                 if (ixgbe_link_test(adapter, &data[4]))
1838                         eth_test->flags |= ETH_TEST_FL_FAILED;
1839
1840                 /* Online tests aren't run; pass by default */
1841                 data[0] = 0;
1842                 data[1] = 0;
1843                 data[2] = 0;
1844                 data[3] = 0;
1845
1846                 clear_bit(__IXGBE_TESTING, &adapter->state);
1847         }
1848         msleep_interruptible(4 * 1000);
1849 }
1850
1851 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1852                                struct ethtool_wolinfo *wol)
1853 {
1854         struct ixgbe_hw *hw = &adapter->hw;
1855         int retval = 1;
1856
1857         switch(hw->device_id) {
1858         case IXGBE_DEV_ID_82599_KX4:
1859                 retval = 0;
1860                 break;
1861         default:
1862                 wol->supported = 0;
1863         }
1864
1865         return retval;
1866 }
1867
1868 static void ixgbe_get_wol(struct net_device *netdev,
1869                           struct ethtool_wolinfo *wol)
1870 {
1871         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1872
1873         wol->supported = WAKE_UCAST | WAKE_MCAST |
1874                          WAKE_BCAST | WAKE_MAGIC;
1875         wol->wolopts = 0;
1876
1877         if (ixgbe_wol_exclusion(adapter, wol) ||
1878             !device_can_wakeup(&adapter->pdev->dev))
1879                 return;
1880
1881         if (adapter->wol & IXGBE_WUFC_EX)
1882                 wol->wolopts |= WAKE_UCAST;
1883         if (adapter->wol & IXGBE_WUFC_MC)
1884                 wol->wolopts |= WAKE_MCAST;
1885         if (adapter->wol & IXGBE_WUFC_BC)
1886                 wol->wolopts |= WAKE_BCAST;
1887         if (adapter->wol & IXGBE_WUFC_MAG)
1888                 wol->wolopts |= WAKE_MAGIC;
1889
1890         return;
1891 }
1892
1893 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1894 {
1895         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1896
1897         if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1898                 return -EOPNOTSUPP;
1899
1900         if (ixgbe_wol_exclusion(adapter, wol))
1901                 return wol->wolopts ? -EOPNOTSUPP : 0;
1902
1903         adapter->wol = 0;
1904
1905         if (wol->wolopts & WAKE_UCAST)
1906                 adapter->wol |= IXGBE_WUFC_EX;
1907         if (wol->wolopts & WAKE_MCAST)
1908                 adapter->wol |= IXGBE_WUFC_MC;
1909         if (wol->wolopts & WAKE_BCAST)
1910                 adapter->wol |= IXGBE_WUFC_BC;
1911         if (wol->wolopts & WAKE_MAGIC)
1912                 adapter->wol |= IXGBE_WUFC_MAG;
1913
1914         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1915
1916         return 0;
1917 }
1918
1919 static int ixgbe_nway_reset(struct net_device *netdev)
1920 {
1921         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1922
1923         if (netif_running(netdev))
1924                 ixgbe_reinit_locked(adapter);
1925
1926         return 0;
1927 }
1928
1929 static int ixgbe_phys_id(struct net_device *netdev, u32 data)
1930 {
1931         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1932         struct ixgbe_hw *hw = &adapter->hw;
1933         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1934         u32 i;
1935
1936         if (!data || data > 300)
1937                 data = 300;
1938
1939         for (i = 0; i < (data * 1000); i += 400) {
1940                 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
1941                 msleep_interruptible(200);
1942                 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
1943                 msleep_interruptible(200);
1944         }
1945
1946         /* Restore LED settings */
1947         IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg);
1948
1949         return 0;
1950 }
1951
1952 static int ixgbe_get_coalesce(struct net_device *netdev,
1953                               struct ethtool_coalesce *ec)
1954 {
1955         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1956
1957         ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0].work_limit;
1958
1959         /* only valid if in constant ITR mode */
1960         switch (adapter->rx_itr_setting) {
1961         case 0:
1962                 /* throttling disabled */
1963                 ec->rx_coalesce_usecs = 0;
1964                 break;
1965         case 1:
1966                 /* dynamic ITR mode */
1967                 ec->rx_coalesce_usecs = 1;
1968                 break;
1969         default:
1970                 /* fixed interrupt rate mode */
1971                 ec->rx_coalesce_usecs = 1000000/adapter->rx_eitr_param;
1972                 break;
1973         }
1974
1975         /* only valid if in constant ITR mode */
1976         switch (adapter->tx_itr_setting) {
1977         case 0:
1978                 /* throttling disabled */
1979                 ec->tx_coalesce_usecs = 0;
1980                 break;
1981         case 1:
1982                 /* dynamic ITR mode */
1983                 ec->tx_coalesce_usecs = 1;
1984                 break;
1985         default:
1986                 ec->tx_coalesce_usecs = 1000000/adapter->tx_eitr_param;
1987                 break;
1988         }
1989
1990         return 0;
1991 }
1992
1993 static int ixgbe_set_coalesce(struct net_device *netdev,
1994                               struct ethtool_coalesce *ec)
1995 {
1996         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1997         struct ixgbe_q_vector *q_vector;
1998         int i;
1999
2000         /*
2001          * don't accept tx specific changes if we've got mixed RxTx vectors
2002          * test and jump out here if needed before changing the rx numbers
2003          */
2004         if ((1000000/ec->tx_coalesce_usecs) != adapter->tx_eitr_param &&
2005             adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count)
2006                 return -EINVAL;
2007
2008         if (ec->tx_max_coalesced_frames_irq)
2009                 adapter->tx_ring[0].work_limit = ec->tx_max_coalesced_frames_irq;
2010
2011         if (ec->rx_coalesce_usecs > 1) {
2012                 /* check the limits */
2013                 if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2014                     (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2015                         return -EINVAL;
2016
2017                 /* store the value in ints/second */
2018                 adapter->rx_eitr_param = 1000000/ec->rx_coalesce_usecs;
2019
2020                 /* static value of interrupt rate */
2021                 adapter->rx_itr_setting = adapter->rx_eitr_param;
2022                 /* clear the lower bit as its used for dynamic state */
2023                 adapter->rx_itr_setting &= ~1;
2024         } else if (ec->rx_coalesce_usecs == 1) {
2025                 /* 1 means dynamic mode */
2026                 adapter->rx_eitr_param = 20000;
2027                 adapter->rx_itr_setting = 1;
2028         } else {
2029                 /*
2030                  * any other value means disable eitr, which is best
2031                  * served by setting the interrupt rate very high
2032                  */
2033                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2034                         adapter->rx_eitr_param = IXGBE_MAX_RSC_INT_RATE;
2035                 else
2036                         adapter->rx_eitr_param = IXGBE_MAX_INT_RATE;
2037                 adapter->rx_itr_setting = 0;
2038         }
2039
2040         if (ec->tx_coalesce_usecs > 1) {
2041                 /* check the limits */
2042                 if ((1000000/ec->tx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2043                     (1000000/ec->tx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2044                         return -EINVAL;
2045
2046                 /* store the value in ints/second */
2047                 adapter->tx_eitr_param = 1000000/ec->tx_coalesce_usecs;
2048
2049                 /* static value of interrupt rate */
2050                 adapter->tx_itr_setting = adapter->tx_eitr_param;
2051
2052                 /* clear the lower bit as its used for dynamic state */
2053                 adapter->tx_itr_setting &= ~1;
2054         } else if (ec->tx_coalesce_usecs == 1) {
2055                 /* 1 means dynamic mode */
2056                 adapter->tx_eitr_param = 10000;
2057                 adapter->tx_itr_setting = 1;
2058         } else {
2059                 adapter->tx_eitr_param = IXGBE_MAX_INT_RATE;
2060                 adapter->tx_itr_setting = 0;
2061         }
2062
2063         /* MSI/MSIx Interrupt Mode */
2064         if (adapter->flags &
2065             (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) {
2066                 int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2067                 for (i = 0; i < num_vectors; i++) {
2068                         q_vector = adapter->q_vector[i];
2069                         if (q_vector->txr_count && !q_vector->rxr_count)
2070                                 /* tx only */
2071                                 q_vector->eitr = adapter->tx_eitr_param;
2072                         else
2073                                 /* rx only or mixed */
2074                                 q_vector->eitr = adapter->rx_eitr_param;
2075                         ixgbe_write_eitr(q_vector);
2076                 }
2077         /* Legacy Interrupt Mode */
2078         } else {
2079                 q_vector = adapter->q_vector[0];
2080                 q_vector->eitr = adapter->rx_eitr_param;
2081                 ixgbe_write_eitr(q_vector);
2082         }
2083
2084         return 0;
2085 }
2086
2087 static int ixgbe_set_flags(struct net_device *netdev, u32 data)
2088 {
2089         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2090
2091         ethtool_op_set_flags(netdev, data);
2092
2093         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
2094                 return 0;
2095
2096         /* if state changes we need to update adapter->flags and reset */
2097         if ((!!(data & ETH_FLAG_LRO)) != 
2098             (!!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) {
2099                 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
2100                 if (netif_running(netdev))
2101                         ixgbe_reinit_locked(adapter);
2102                 else
2103                         ixgbe_reset(adapter);
2104         }
2105         return 0;
2106
2107 }
2108
2109 static const struct ethtool_ops ixgbe_ethtool_ops = {
2110         .get_settings           = ixgbe_get_settings,
2111         .set_settings           = ixgbe_set_settings,
2112         .get_drvinfo            = ixgbe_get_drvinfo,
2113         .get_regs_len           = ixgbe_get_regs_len,
2114         .get_regs               = ixgbe_get_regs,
2115         .get_wol                = ixgbe_get_wol,
2116         .set_wol                = ixgbe_set_wol,
2117         .nway_reset             = ixgbe_nway_reset,
2118         .get_link               = ethtool_op_get_link,
2119         .get_eeprom_len         = ixgbe_get_eeprom_len,
2120         .get_eeprom             = ixgbe_get_eeprom,
2121         .get_ringparam          = ixgbe_get_ringparam,
2122         .set_ringparam          = ixgbe_set_ringparam,
2123         .get_pauseparam         = ixgbe_get_pauseparam,
2124         .set_pauseparam         = ixgbe_set_pauseparam,
2125         .get_rx_csum            = ixgbe_get_rx_csum,
2126         .set_rx_csum            = ixgbe_set_rx_csum,
2127         .get_tx_csum            = ixgbe_get_tx_csum,
2128         .set_tx_csum            = ixgbe_set_tx_csum,
2129         .get_sg                 = ethtool_op_get_sg,
2130         .set_sg                 = ethtool_op_set_sg,
2131         .get_msglevel           = ixgbe_get_msglevel,
2132         .set_msglevel           = ixgbe_set_msglevel,
2133         .get_tso                = ethtool_op_get_tso,
2134         .set_tso                = ixgbe_set_tso,
2135         .self_test              = ixgbe_diag_test,
2136         .get_strings            = ixgbe_get_strings,
2137         .phys_id                = ixgbe_phys_id,
2138         .get_sset_count         = ixgbe_get_sset_count,
2139         .get_ethtool_stats      = ixgbe_get_ethtool_stats,
2140         .get_coalesce           = ixgbe_get_coalesce,
2141         .set_coalesce           = ixgbe_set_coalesce,
2142         .get_flags              = ethtool_op_get_flags,
2143         .set_flags              = ixgbe_set_flags,
2144 };
2145
2146 void ixgbe_set_ethtool_ops(struct net_device *netdev)
2147 {
2148         SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2149 }